diff --git a/src/i2c.rs b/src/i2c.rs
new file mode 100644
index 0000000000000000000000000000000000000000..c07031d7870bb38283ac756acc6cbc85d9207631
--- /dev/null
+++ b/src/i2c.rs
@@ -0,0 +1,69 @@
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+
+use cortex_m_rt::entry;
+use cortex_m_semihosting::hprintln;
+
+use stm32l4xx_hal as hal;
+
+use crate::hal::i2c;
+use crate::hal::i2c::I2c;
+
+use crate::hal::prelude::*;
+
+#[entry]
+fn main() -> ! {
+    hprintln! {"Nucleo-l476RG is alive !"};
+
+    /*
+        setup peripherals
+    */
+
+    let periphs = hal::stm32::Peripherals::take().unwrap();
+    let mut flash = periphs.FLASH.constrain(); // .constrain();
+    let mut rcc = periphs.RCC.constrain();
+    let mut pwr = periphs.PWR.constrain(&mut rcc.apb1r1);
+    // let mut gpioa = periphs.GPIOA.split(&mut rcc.ahb2);
+    let mut gpiob = periphs.GPIOB.split(&mut rcc.ahb2);
+    let clocks = rcc.cfgr.freeze(&mut flash.acr, &mut pwr);
+
+    /*
+        setup i2c
+    */
+
+    let mut scl = gpiob.pb13.into_alternate_open_drain::<4>(
+        &mut gpiob.moder,
+        &mut gpiob.otyper,
+        &mut gpiob.afrh,
+    );
+    scl.internal_pull_up(&mut gpiob.pupdr, true);
+
+    let mut sda = gpiob.pb14.into_alternate_open_drain::<4>(
+        &mut gpiob.moder,
+        &mut gpiob.otyper,
+        &mut gpiob.afrh,
+    );
+    sda.internal_pull_up(&mut gpiob.pupdr, true);
+
+    let mut i2c = I2c::i2c2(
+        periphs.I2C2,
+        (scl, sda),
+        i2c::Config::new(100.kHz(), clocks),
+        &mut rcc.apb1r1,
+    );
+
+    let mut buffer = [0u8; 4];
+
+    const MPL115A2_ADDR_WRITE: u8 = 0xC0;
+    const MPL115A2_ADDR_READ: u8 = 0xC1;
+
+    i2c.write_read(MPL115A2_ADDR_WRITE, &[0x04], &mut buffer)
+        .unwrap();
+    hprintln!("TEST: {}", buffer[0]);
+
+    loop {
+        continue;
+    }
+}