diff --git a/CMSISv2p00_LPC17xx/.cproject b/CMSISv2p00_LPC17xx/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..c43d0df3c90517651e44fd5f0c180e8cc86d9ae7
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/.cproject
@@ -0,0 +1,511 @@
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+ <runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.lib.release.1079171862;com.crt.advproject.config.lib.release.1079171862.;com.crt.advproject.gas.lib.release.48688322;com.crt.advproject.assembler.input.1808596896">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+ <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+ <buildOutputProvider>
+ <openAction enabled="false" filePath=""/>
+ <parser enabled="false"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="com.crt.advproject.specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="false" filePath=""/>
+ <parser enabled="false"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="com.crt.advproject.specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="false" filePath=""/>
+ <parser enabled="false"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="com.crt.advproject.specsFile">
+ <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="makefileGenerator">
+ <runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="openCmsis"/>
+ <storageModule moduleId="com.crt.advproject"/>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>
\ No newline at end of file
diff --git a/CMSISv2p00_LPC17xx/.project b/CMSISv2p00_LPC17xx/.project
new file mode 100644
index 0000000000000000000000000000000000000000..5cd9643f190838c28b92a155ea0e46662740d5e4
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/.project
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>CMSISv2p00_LPC17xx</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ <dictionary>
+ <key>?name?</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.append_environment</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildArguments</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildCommand</key>
+ <value>make</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildLocation</key>
+ <value>${workspace_loc:/CMSISv2p00_LPC17xx/Debug}</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+ <value>clean</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.contents</key>
+ <value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.stopOnError</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+ <value>true</value>
+ </dictionary>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/CMSISv2p00_LPC17xx/.settings/language.settings.xml b/CMSISv2p00_LPC17xx/.settings/language.settings.xml
new file mode 100644
index 0000000000000000000000000000000000000000..f50a266ddcfd59a8019ab5080d45096651bf5218
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="com.crt.advproject.config.lib.debug.1814355025" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="227759477465743802" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+ <configuration id="com.crt.advproject.config.lib.release.1079171862" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="234512289041408538" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+</project>
\ No newline at end of file
diff --git a/CMSISv2p00_LPC17xx/.settings/org.eclipse.core.resources.prefs b/CMSISv2p00_LPC17xx/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..99f26c0203a7844de00dbfc56e6a35d8ed3c022c
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8
diff --git a/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a b/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a
new file mode 100644
index 0000000000000000000000000000000000000000..19a1e00e3178e911307cbd9c5ea9c4ac0345b32a
Binary files /dev/null and b/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a differ
diff --git a/CMSISv2p00_LPC17xx/Debug/makefile b/CMSISv2p00_LPC17xx/Debug/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d5733729375e2972a8dc5e576808193b390f9c59
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/Debug/makefile
@@ -0,0 +1,50 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all: libCMSISv2p00_LPC17xx.a
+
+# Tool invocations
+libCMSISv2p00_LPC17xx.a: $(OBJS) $(USER_OBJS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Archiver'
+ arm-none-eabi-ar -r "libCMSISv2p00_LPC17xx.a" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+ $(MAKE) --no-print-directory post-build
+
+# Other Targets
+clean:
+ -$(RM) $(OBJS)$(ARCHIVES)$(C_DEPS) libCMSISv2p00_LPC17xx.a
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size libCMSISv2p00_LPC17xx.a ; # arm-none-eabi-objdump -h -S libCMSISv2p00_LPC17xx.a >libCMSISv2p00_LPC17xx.lss
+ -@echo ' '
+
+.PHONY: all clean dependents
+.SECONDARY: post-build
+
+-include ../makefile.targets
diff --git a/CMSISv2p00_LPC17xx/Debug/objects.mk b/CMSISv2p00_LPC17xx/Debug/objects.mk
new file mode 100644
index 0000000000000000000000000000000000000000..dc31e16c685929c0d9eb5bd448a36f54b1533d57
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/CMSISv2p00_LPC17xx/Debug/sources.mk b/CMSISv2p00_LPC17xx/Debug/sources.mk
new file mode 100644
index 0000000000000000000000000000000000000000..b73fb96b731b873895da424d46937f565bffdad2
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/Debug/sources.mk
@@ -0,0 +1,18 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+OBJ_SRCS :=
+S_SRCS :=
+ASM_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+O_SRCS :=
+OBJS :=
+ARCHIVES :=
+C_DEPS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
diff --git a/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d b/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
new file mode 100644
index 0000000000000000000000000000000000000000..d76bd1475e2b78bd2db55716eb44660c8226eb09
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
@@ -0,0 +1 @@
+src/core_cm3.o src/core_cm3.d: ../src/core_cm3.c
diff --git a/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o b/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o
new file mode 100644
index 0000000000000000000000000000000000000000..128ee21e8a72ab6654e4428f1e17a9df5dd4b2d0
Binary files /dev/null and b/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o differ
diff --git a/CMSISv2p00_LPC17xx/Debug/src/subdir.mk b/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
new file mode 100644
index 0000000000000000000000000000000000000000..fe6f04c7b99800f0291526256e671a7f0e956ed8
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../src/core_cm3.c \
+../src/system_LPC17xx.c
+
+OBJS += \
+./src/core_cm3.o \
+./src/system_LPC17xx.o
+
+C_DEPS += \
+./src/core_cm3.d \
+./src/system_LPC17xx.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I../inc -O0 -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb -D__REDLIB__ -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d b/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
new file mode 100644
index 0000000000000000000000000000000000000000..a132246a2c91746f6c6034f6fe7dcf2b0dc5b37a
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
@@ -0,0 +1,13 @@
+src/system_LPC17xx.o src/system_LPC17xx.d: ../src/system_LPC17xx.c \
+ ../inc/LPC17xx.h ../inc/core_cm3.h ../inc/core_cmInstr.h \
+ ../inc/core_cmFunc.h ../inc/system_LPC17xx.h
+
+../inc/LPC17xx.h:
+
+../inc/core_cm3.h:
+
+../inc/core_cmInstr.h:
+
+../inc/core_cmFunc.h:
+
+../inc/system_LPC17xx.h:
diff --git a/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o b/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o
new file mode 100644
index 0000000000000000000000000000000000000000..1478507dc774750d650918f90db6ee713abe2462
Binary files /dev/null and b/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o differ
diff --git a/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf b/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..e04afaee6286ce461b2ab5f286c6f99b232f5ae0
Binary files /dev/null and b/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf differ
diff --git a/CMSISv2p00_LPC17xx/docs/cmsis_readme.txt b/CMSISv2p00_LPC17xx/docs/cmsis_readme.txt
new file mode 100644
index 0000000000000000000000000000000000000000..316499c01484d26210923d66c1ff8d9950d54c41
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/docs/cmsis_readme.txt
@@ -0,0 +1,44 @@
+CMSIS : Cortex Microcontroller Software Interface Standard
+==========================================================
+
+Introduction
+~~~~~~~~~~~~
+CMSIS defines for a Cortex-M Microcontroller System:
+
+ * A common way to access peripheral registers and a
+ common way to define exception vectors.
+ * The register names of the Core Peripherals and the
+ names of the Core Exception Vectors.
+ * An device independent interface for RTOS Kernels
+ including a debug channel.
+
+By using CMSIS compliant software components, the user can
+easier re-use template code. CMSIS is intended to enable the
+combination of software components from multiple middleware
+vendors.
+
+This project contains appropriate files for this MCU family
+taken from CMSIS. A full copy of the CMSIS files, together
+with additional information on CMSIS can be found at:
+
+ http://www.onarm.com/
+ http://www.arm.com/
+
+Documentation
+~~~~~~~~~~~~~
+The standard CMSIS documentation can be found within the
+Code Red IDE help system, via:
+
+Help -> Help Contents -> Code Red Product Documentation -> CMSIS
+
+More information on the use of CMSIS within the Code Red IDE
+can be found in the Support area of the Code Red website at
+
+ http://www.code-red-tech.com/
+
+At the time of writing, the CMSIS FAQ can be found directly
+at:
+
+ http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS
+
+
diff --git a/CMSISv2p00_LPC17xx/history.txt b/CMSISv2p00_LPC17xx/history.txt
new file mode 100644
index 0000000000000000000000000000000000000000..42ca3af7c11a3248d21c506e76871712823716be
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/history.txt
@@ -0,0 +1,12 @@
+History of updates to CMSISv2p00_LPC17xx
+========================================
+
+7 March 2011
+------------
+LPC17xx CMSIS 2.0 library project using ARM
+Cortex-M3 CMSIS files as supplied in ARM's CMSIS 2.0
+December 2010 release, together with device/board
+specific files from NXP (as previously supplied in
+CMSISv1p30_LPC17xx library project, dated 24 Aug 2010).
+
+Note files are built -Os for both Debug and Release
\ No newline at end of file
diff --git a/CMSISv2p00_LPC17xx/inc/LPC17xx.h b/CMSISv2p00_LPC17xx/inc/LPC17xx.h
new file mode 100644
index 0000000000000000000000000000000000000000..8c4050b3a2a4e07ee5b53e5bc1dfc8df8d231ca0
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/inc/LPC17xx.h
@@ -0,0 +1,1035 @@
+/**************************************************************************//**
+ * @file LPC17xx.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * NXP LPC17xx Device Series
+ * @version: V1.09
+ * @date: 17. March 2010
+
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ SPI_IRQn = 13, /*!< SPI Interrupt */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /* USB Activity interrupt */
+ CANActivity_IRQn = 34, /* CAN Activity interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system_LPC17xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON;
+ __IO uint32_t PLL1CFG;
+ __I uint32_t PLL1STAT;
+ __O uint32_t PLL1FEED;
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ __IO uint32_t CANSLEEPCLR;
+ __IO uint32_t CANWAKEFLAGS;
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ uint32_t RESERVED5;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ __IO uint32_t DMAREQSEL;
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+ __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ union {
+ __IO uint32_t FIODIR;
+ struct {
+ __IO uint16_t FIODIRL;
+ __IO uint16_t FIODIRH;
+ };
+ struct {
+ __IO uint8_t FIODIR0;
+ __IO uint8_t FIODIR1;
+ __IO uint8_t FIODIR2;
+ __IO uint8_t FIODIR3;
+ };
+ };
+ uint32_t RESERVED0[3];
+ union {
+ __IO uint32_t FIOMASK;
+ struct {
+ __IO uint16_t FIOMASKL;
+ __IO uint16_t FIOMASKH;
+ };
+ struct {
+ __IO uint8_t FIOMASK0;
+ __IO uint8_t FIOMASK1;
+ __IO uint8_t FIOMASK2;
+ __IO uint8_t FIOMASK3;
+ };
+ };
+ union {
+ __IO uint32_t FIOPIN;
+ struct {
+ __IO uint16_t FIOPINL;
+ __IO uint16_t FIOPINH;
+ };
+ struct {
+ __IO uint8_t FIOPIN0;
+ __IO uint8_t FIOPIN1;
+ __IO uint8_t FIOPIN2;
+ __IO uint8_t FIOPIN3;
+ };
+ };
+ union {
+ __IO uint32_t FIOSET;
+ struct {
+ __IO uint16_t FIOSETL;
+ __IO uint16_t FIOSETH;
+ };
+ struct {
+ __IO uint8_t FIOSET0;
+ __IO uint8_t FIOSET1;
+ __IO uint8_t FIOSET2;
+ __IO uint8_t FIOSET3;
+ };
+ };
+ union {
+ __O uint32_t FIOCLR;
+ struct {
+ __O uint16_t FIOCLRL;
+ __O uint16_t FIOCLRH;
+ };
+ struct {
+ __O uint8_t FIOCLR0;
+ __O uint8_t FIOCLR1;
+ __O uint8_t FIOCLR2;
+ __O uint8_t FIOCLR3;
+ };
+ };
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART0_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __IO uint32_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __IO uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t RICOMPVAL;
+ __IO uint32_t RIMASK;
+ __IO uint8_t RICTRL;
+ uint8_t RESERVED0[3];
+ __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t MCCON;
+ __O uint32_t MCCON_SET;
+ __O uint32_t MCCON_CLR;
+ __I uint32_t MCCAPCON;
+ __O uint32_t MCCAPCON_SET;
+ __O uint32_t MCCAPCON_CLR;
+ __IO uint32_t MCTIM0;
+ __IO uint32_t MCTIM1;
+ __IO uint32_t MCTIM2;
+ __IO uint32_t MCPER0;
+ __IO uint32_t MCPER1;
+ __IO uint32_t MCPER2;
+ __IO uint32_t MCPW0;
+ __IO uint32_t MCPW1;
+ __IO uint32_t MCPW2;
+ __IO uint32_t MCDEADTIME;
+ __IO uint32_t MCCCP;
+ __IO uint32_t MCCR0;
+ __IO uint32_t MCCR1;
+ __IO uint32_t MCCR2;
+ __I uint32_t MCINTEN;
+ __O uint32_t MCINTEN_SET;
+ __O uint32_t MCINTEN_CLR;
+ __I uint32_t MCCNTCON;
+ __O uint32_t MCCNTCON_SET;
+ __O uint32_t MCCNTCON_CLR;
+ __I uint32_t MCINTFLAG;
+ __O uint32_t MCINTFLAG_SET;
+ __O uint32_t MCINTFLAG_CLR;
+ __O uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t QEICON;
+ __I uint32_t QEISTAT;
+ __IO uint32_t QEICONF;
+ __I uint32_t QEIPOS;
+ __IO uint32_t QEIMAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP;
+ __IO uint32_t QEILOAD;
+ __I uint32_t QEITIME;
+ __I uint32_t QEIVEL;
+ __I uint32_t QEICAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTER;
+ uint32_t RESERVED0[998];
+ __O uint32_t QEIIEC;
+ __O uint32_t QEIIES;
+ __I uint32_t QEIINTSTAT;
+ __I uint32_t QEIIE;
+ __O uint32_t QEICLR;
+ __O uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+ __IO uint32_t FCANIE;
+ __IO uint32_t FCANIC0;
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_GPIO_BASE (0x2009C000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
+#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+
+#endif // __LPC17xx_H__
diff --git a/CMSISv2p00_LPC17xx/inc/core_cm3.h b/CMSISv2p00_LPC17xx/inc/core_cm3.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b019a48e18b77392c1d737a361076c09db711f4
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/inc/core_cm3.h
@@ -0,0 +1,1236 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V2.01
+ * @date 06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M3
+
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+ It consists of:
+
+ - Cortex-M Core Register Definitions
+ - Cortex-M functions
+ - Cortex-M instructions
+
+ The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+ access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
+ List of Lint messages which will be suppressed and not shown:
+ - not yet checked
+ .
+ Note: To re-enable a Message, insert a space before 'lint' *
+
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core
+ - Cortex-M core Revision Number
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+#include <stdint.h> /*!< standard types definitions */
+#include "core_cmInstr.h" /*!< Core Instruction Access */
+#include "core_cmFunc.h" /*!< Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE CMSIS Core
+ Type definitions for the Cortex-M Core Registers
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC CMSIS NVIC
+ Type definitions for the Cortex-M NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB CMSIS SCB
+ Type definitions for the Cortex-M System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick CMSIS SysTick
+ Type definitions for the Cortex-M System Timer Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM CMSIS ITM
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_InterruptType CMSIS Interrupt Type
+ Type definitions for the Cortex-M Interrupt Type Register
+ @{
+ */
+
+/** \brief Structure type to access the Interrupt Type Register.
+ */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
+#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
+#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
+
+/*@}*/ /* end of group CMSIS_InterruptType */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU CMSIS MPU
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug
+ Type definitions for the Cortex-M Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ This function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ This function gets the priority grouping from NVIC Interrupt Controller.
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+ \return Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ This function enables a device specific interupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ This function disables a device specific interupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ This function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Number of the interrupt for get pending
+ \return 0 Interrupt status is not pending
+ \return 1 Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ This function sets the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ This function clears the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ This function reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Number of the interrupt for get active
+ \return 0 Interrupt status is not active
+ \return 1 Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ This function sets the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ Note: The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Number of the interrupt for set priority
+ \param [in] priority Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ This function reads the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ The returned priority value is automatically aligned to the implemented
+ priority bits of the microcontroller.
+
+ \param [in] IRQn Number of the interrupt for get priority
+ \return Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ This function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The returned priority value can be used for NVIC_SetPriority(...) function
+
+ \param [in] PriorityGroup Used priority group
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)
+ \param [in] SubPriority Sub priority value (starting from 0)
+ \return Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ This function decodes an interrupt priority value with the given priority group to
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The priority value can be retrieved with NVIC_GetPriority(...) function
+
+ \param [in] Priority Priority value
+ \param [in] PriorityGroup Used priority group
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)
+ \param [out] pSubPriority Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ This function initialises the system tick timer and its interrupt and start the system tick timer.
+ Counter is in free running mode to generate periodical interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief ITM Send Character
+
+ This function transmits a character via the ITM channel 0.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \param [in] ch Character to transmit
+ \return Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ This function inputs a character via external variable ITM_RxBuffer.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \return Received character
+ \return -1 No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ This function checks external variable ITM_RxBuffer whether a character is available or not.
+ It returns '1' if a character is available and '0' if no character is available.
+
+ \return 0 No character available
+ \return 1 Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*lint -restore */
diff --git a/CMSISv2p00_LPC17xx/inc/core_cmFunc.h b/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..1ff04d9251269313ca091a92ba7802b9591032e2
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
@@ -0,0 +1,844 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V2.01
+ * @date 06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H__
+#define __CORE_CMFUNC_H__
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_CONTROL(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_CONTROL(uint32_t control);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_IPSR(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_APSR(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_xPSR(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_PSP(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_PSP(uint32_t topOfProcStack);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_MSP(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_MSP(uint32_t topOfMainStack);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_PRIMASK(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_PRIMASK(uint32_t priMask);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+#endif /* __ARMCC_VERSION */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_BASEPRI(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_BASEPRI(uint32_t basePri);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_FAULTMASK(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_FAULTMASK(uint32_t faultMask);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+#endif /* __ARMCC_VERSION */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+ #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+#pragma diag_suppress=Pe940
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_irq __enable_interrupt
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_irq __disable_interrupt
+
+
+/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
+/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+static uint32_t __get_IPSR(void)
+{
+ __ASM("mrs r0, ipsr");
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+static uint32_t __get_APSR(void)
+{
+ __ASM("mrs r0, apsr");
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+static uint32_t __get_xPSR(void)
+{
+ __ASM("mrs r0, psr"); // assembler does not know "xpsr"
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+static uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+static void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+static uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+static void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+}
+
+
+/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
+/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+static __INLINE void __enable_fault_irq(void)
+{
+ __ASM ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+static __INLINE void __disable_fault_irq(void)
+{
+ __ASM ("cpsid f");
+}
+
+
+/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
+/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
+/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
+/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+static uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM("vmrs r0, fpscr");
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+static void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM("vmsr fpscr, r0");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H__ */
diff --git a/CMSISv2p00_LPC17xx/inc/core_cmInstr.h b/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
new file mode 100644
index 0000000000000000000000000000000000000000..95ce06cb27ed1f8752ffa189c03e047619b70b6d
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
@@ -0,0 +1,775 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V2.01
+ * @date 06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H__
+#define __CORE_CMINSTR_H__
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern uint32_t __REV16(uint32_t value);
+#else /* (__ARMCC_VERSION >= 400677) */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern int32_t __REVSH(int32_t value);
+#else /* (__ARMCC_VERSION >= 400677) */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __CLREX(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+#define __CLREX __clrex
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#include <intrinsics.h> /* IAR Intrinsics */
+
+#pragma diag_suppress=Pe940
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __no_operation
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+static __INLINE void __WFI(void)
+{
+ __ASM ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+static __INLINE void __WFE(void)
+{
+ __ASM ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+static __INLINE void __SEV(void)
+{
+ __ASM ("sev");
+}
+
+
+/* intrinsic void __ISB(void) (see intrinsics.h) */
+/* intrinsic void __DSB(void) (see intrinsics.h) */
+/* intrinsic void __DMB(void) (see intrinsics.h) */
+/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
+/* intrinsic __SSAT (see intrinsics.h) */
+/* intrinsic __USAT (see intrinsics.h) */
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static uint32_t __REV16(uint32_t value)
+{
+ __ASM("rev16 r0, r0");
+}
+
+
+/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+static uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+static uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
+static uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+static __INLINE void __CLREX(void)
+{
+ __ASM ("clrex");
+}
+
+/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#pragma diag_default=Pe940
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H__ */
diff --git a/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h b/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
new file mode 100644
index 0000000000000000000000000000000000000000..e58767e9cd70a1bcf2707b214b12945b72db29aa
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC17xx.h
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC17xx Device Series
+ * @version V1.02
+ * @date 08. September 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC17xx_H */
diff --git a/CMSISv2p00_LPC17xx/src/core_cm3.c b/CMSISv2p00_LPC17xx/src/core_cm3.c
new file mode 100644
index 0000000000000000000000000000000000000000..fd052ce27c92d20ef02223b036b51c56b74e1b53
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/src/core_cm3.c
@@ -0,0 +1,339 @@
+/**************************************************************************//**
+ * @file core_cm3.c
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version V2.00
+ * @date 13. September 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ########################## Core Instruction Access ######################### */
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __CLREX(void)
+{
+ clrex
+}
+#endif /* __ARMCC_VERSION */
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_IPSR(void)
+{
+ mrs r0, ipsr
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_APSR(void)
+{
+ mrs r0, apsr
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_xPSR(void)
+{
+ mrs r0, xpsr
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask Register.
+
+ \return Fault Mask value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set the Fault Mask
+
+ This function assigns the given value to the Fault Mask Register.
+
+ \param [in] faultMask Fault Mask value value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
diff --git a/CMSISv2p00_LPC17xx/src/system_LPC17xx.c b/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
new file mode 100644
index 0000000000000000000000000000000000000000..b9d674ab0eb93fca549764c66144dfff77871109
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
@@ -0,0 +1,532 @@
+/**************************************************************************//**
+ * @file system_LPC17xx.c
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC17xx Device Series
+ * @version V1.08
+ * @date 12. May 2010
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC17xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS)
+// <o1.4> OSCRANGE: Main Oscillator Range Select
+// <0=> 1 MHz to 20 MHz
+// <1=> 15 MHz to 24 MHz
+// <e1.5> OSCEN: Main Oscillator Enable
+// </e>
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL)
+// <o2.0..1> CLKSRC: PLL Clock Source Selection
+// <0=> Internal RC oscillator
+// <1=> Main oscillator
+// <2=> RTC oscillator
+// </h>
+//
+// <e3> PLL0 Configuration (Main PLL)
+// <h> PLL0 Configuration Register (PLL0CFG)
+// <i> F_cco0 = (2 * M * F_in) / N
+// <i> F_in must be in the range of 32 kHz to 50 MHz
+// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+// <o4.0..14> MSEL: PLL Multiplier Selection
+// <6-32768><#-1>
+// <i> M Value
+// <o4.16..23> NSEL: PLL Divider Selection
+// <1-256><#-1>
+// <i> N Value
+// </h>
+// </e>
+//
+// <e5> PLL1 Configuration (USB PLL)
+// <h> PLL1 Configuration Register (PLL1CFG)
+// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
+// <i> F_cco1 = F_osc * M * 2 * P
+// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
+// <o6.0..4> MSEL: PLL Multiplier Selection
+// <1-32><#-1>
+// <i> M Value (for USB maximum value is 4)
+// <o6.5..6> PSEL: PLL Divider Selection
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// <i> P Value
+// </h>
+// </e>
+//
+// <h> CPU Clock Configuration Register (CCLKCFG)
+// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
+// <1-256><#-1>
+// </h>
+//
+// <h> USB Clock Configuration Register (USBCLKCFG)
+// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
+// <0-15>
+// <i> Divide is USBSEL + 1
+// </h>
+//
+// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
+// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// </h>
+//
+// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
+// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP)
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
+// <o11.3> PCUART0: UART 0 power/clock enable
+// <o11.4> PCUART1: UART 1 power/clock enable
+// <o11.6> PCPWM1: PWM 1 power/clock enable
+// <o11.7> PCI2C0: I2C interface 0 power/clock enable
+// <o11.8> PCSPI: SPI interface power/clock enable
+// <o11.9> PCRTC: RTC power/clock enable
+// <o11.10> PCSSP1: SSP interface 1 power/clock enable
+// <o11.12> PCAD: A/D converter power/clock enable
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable
+// <o11.15> PCGPIO: GPIOs power/clock enable
+// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
+// <o11.17> PCMC: Motor control PWM power/clock enable
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
+// <o11.19> PCI2C1: I2C interface 1 power/clock enable
+// <o11.21> PCSSP0: SSP interface 0 power/clock enable
+// <o11.22> PCTIM2: Timer 2 power/clock enable
+// <o11.23> PCTIM3: Timer 3 power/clock enable
+// <o11.24> PCUART2: UART 2 power/clock enable
+// <o11.25> PCUART3: UART 3 power/clock enable
+// <o11.26> PCI2C2: I2C interface 2 power/clock enable
+// <o11.27> PCI2S: I2S interface power/clock enable
+// <o11.29> PCGPDMA: GP DMA function power/clock enable
+// <o11.30> PCENET: Ethernet block power/clock enable
+// <o11.31> PCUSB: USB interface power/clock enable
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
+// <0=> CPU clock
+// <1=> Main oscillator
+// <2=> Internal RC oscillator
+// <3=> USB clock
+// <4=> RTC oscillator
+// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
+// <1-16><#-1>
+// <o12.8> CLKOUT_EN: CLKOUT enable control
+// </h>
+//
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00050063
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKCFG_Val 0x00000003
+#define USBCLKCFG_Val 0x00000000
+#define PCLKSEL0_Val 0x00000000
+#define PCLKSEL1_Val 0x00000000
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000000
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x00004000
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x00000030))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (PLL0_SETUP) /* if PLL0 is used */
+ #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
+ #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
+ #endif
+#endif
+
+#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
+ #error "CCLKCFG: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
+ #error "USBCLKCFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
+ #error "PCLKSEL0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
+ #error "PCLKSEL1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), 0x10100821))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
+ #error "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
+#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
+
+
+/* F_cco0 = (2 * M * F_in) / N */
+#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
+#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
+#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+ #endif
+ #else
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #endif
+ #endif
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = (IRC_OSC *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = (OSC_CLK *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = (RTC_CLK *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
+ }
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+
+#if (PLL0_SETUP)
+ LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
+
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
+#else
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+#endif
+
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
+#endif
+}
diff --git a/TP2_bpsk_demod/.cproject b/TP2_bpsk_demod/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..727c8b133d1cac1403c0342906b529ec05295a91
--- /dev/null
+++ b/TP2_bpsk_demod/.cproject
@@ -0,0 +1,233 @@
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+ <option id="com.crt.advproject.link.gcc.multicore.slave.849177108" superClass="com.crt.advproject.link.gcc.multicore.slave"/>
+ <inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1207060680" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
+ <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
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+ </inputType>
+ </tool>
+ <tool id="com.crt.advproject.tool.debug.release.339400228" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.release"/>
+ </toolChain>
+ </folderInfo>
+ <sourceEntries>
+ <entry excluding="processing_solution.s|main_solution.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
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+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="TP2.com.crt.advproject.projecttype.exe.1564122844" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="com.crt.config">
+ <projectStorage><?xml version="1.0" encoding="UTF-8"?>
+<TargetConfig>
+<Properties property_2="LPC175x_6x_512.cfx" property_3="NXP" property_4="LPC1769" property_count="5" version="100300"/>
+<infoList vendor="NXP">
+<info chip="LPC1769" flash_driver="LPC175x_6x_512.cfx" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml" stub="crt_emu_cm3_nxp">
+<chip>
+<name>LPC1769</name>
+<family>LPC17xx</family>
+<vendor>NXP (formerly Philips)</vendor>
+<reset board="None" core="Real" sys="Real"/>
+<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
+<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
+<memory id="RAM" type="RAM"/>
+<memory id="Periph" is_volatile="true" type="Peripheral"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/>
+<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
+<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
+<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
+<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
+</chip>
+<processor>
+<name gcc_name="cortex-m3">Cortex-M3</name>
+<family>Cortex-M</family>
+</processor>
+</info>
+</infoList>
+</TargetConfig></projectStorage>
+ </storageModule>
+ <storageModule moduleId="refreshScope"/>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+ <storageModule moduleId="com.crt.advproject"/>
+ <storageModule moduleId="openCmsis"/>
+</cproject>
\ No newline at end of file
diff --git a/TP2_bpsk_demod/.project b/TP2_bpsk_demod/.project
new file mode 100644
index 0000000000000000000000000000000000000000..6c4d830f96eda8f6a9dd478f23cc37c19576e51a
--- /dev/null
+++ b/TP2_bpsk_demod/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>TP2_bpsk_demod</name>
+ <comment></comment>
+ <projects>
+ <project>CMSISv2p00_LPC17xx</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/TP2_bpsk_demod/.project~ b/TP2_bpsk_demod/.project~
new file mode 100644
index 0000000000000000000000000000000000000000..c29adf40c88f68491f2ed2bffe4dfab60435c79c
--- /dev/null
+++ b/TP2_bpsk_demod/.project~
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>TP22</name>
+ <comment></comment>
+ <projects>
+ <project>CMSISv2p00_LPC17xx</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/TP2_bpsk_demod/.settings/language.settings.xml b/TP2_bpsk_demod/.settings/language.settings.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2e56cdfb49f07969ac2fabc067feb1a88e0310ec
--- /dev/null
+++ b/TP2_bpsk_demod/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="com.crt.advproject.config.exe.debug.215110136" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="173379824774954439" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+ <configuration id="com.crt.advproject.config.exe.release.888357251" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="173378930678947018" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+</project>
\ No newline at end of file
diff --git a/TP2_bpsk_demod/.settings/org.eclipse.core.resources.prefs b/TP2_bpsk_demod/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..99f26c0203a7844de00dbfc56e6a35d8ed3c022c
--- /dev/null
+++ b/TP2_bpsk_demod/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_portable/MemMang/heap_2.su b/TP2_bpsk_demod/Debug/FreeRTOS_portable/MemMang/heap_2.su
new file mode 100644
index 0000000000000000000000000000000000000000..1ee219ac18b7e2d1f3022c3e3838fd3aeebce235
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_portable/MemMang/heap_2.su
@@ -0,0 +1,4 @@
+heap_2.c:154:7:pvPortMalloc 48 static
+heap_2.c:244:6:vPortFree 32 static
+heap_2.c:269:8:xPortGetFreeHeapSize 4 static
+heap_2.c:275:6:vPortInitialiseBlocks 4 static
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_portable/MemMang/subdir.mk b/TP2_bpsk_demod/Debug/FreeRTOS_portable/MemMang/subdir.mk
new file mode 100644
index 0000000000000000000000000000000000000000..9c2ac3298e2248ea77420d6aeed9c19568dd259c
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_portable/MemMang/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../FreeRTOS_portable/MemMang/heap_2.c
+
+OBJS += \
+./FreeRTOS_portable/MemMang/heap_2.o
+
+C_DEPS += \
+./FreeRTOS_portable/MemMang/heap_2.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+FreeRTOS_portable/MemMang/%.o: ../FreeRTOS_portable/MemMang/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -D__USE_CMSIS=CMSISv2p00_LPC17xx -DDEBUG -D__CODE_RED -DPACK_STRUCT_END=__attribute\(\(packed\)\) -DGCC_ARMCM3 -I../src -I"C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\inc" -I../FreeRTOS_include -I../FreeRTOS_portable -O0 -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_portable/port.su b/TP2_bpsk_demod/Debug/FreeRTOS_portable/port.su
new file mode 100644
index 0000000000000000000000000000000000000000..b85097ecfc06d9a5088a1e67939aed30072449ff
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_portable/port.su
@@ -0,0 +1,11 @@
+port.c:114:17:pxPortInitialiseStack 24 static
+port.c:132:6:vPortSVCHandler 0 static
+port.c:151:6:vPortStartFirstTask 0 static
+port.c:168:15:xPortStartScheduler 8 static
+port.c:189:6:vPortEndScheduler 4 static
+port.c:196:6:vPortYieldFromISR 4 static
+port.c:203:6:vPortEnterCritical 4 static
+port.c:210:6:vPortExitCritical 4 static
+port.c:220:6:xPortPendSVHandler 0 static
+port.c:255:6:xPortSysTickHandler 16 static
+port.c:276:6:prvSetupTimerInterrupt 4 static
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_portable/subdir.mk b/TP2_bpsk_demod/Debug/FreeRTOS_portable/subdir.mk
new file mode 100644
index 0000000000000000000000000000000000000000..6435c95b17b65b5dd46094cea7d539451b5e8b2d
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_portable/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../FreeRTOS_portable/port.c
+
+OBJS += \
+./FreeRTOS_portable/port.o
+
+C_DEPS += \
+./FreeRTOS_portable/port.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+FreeRTOS_portable/%.o: ../FreeRTOS_portable/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -D__USE_CMSIS=CMSISv2p00_LPC17xx -DDEBUG -D__CODE_RED -DPACK_STRUCT_END=__attribute\(\(packed\)\) -DGCC_ARMCM3 -I../src -I"C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\inc" -I../FreeRTOS_include -I../FreeRTOS_portable -O0 -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_src/croutine.su b/TP2_bpsk_demod/Debug/FreeRTOS_src/croutine.su
new file mode 100644
index 0000000000000000000000000000000000000000..93ba1af986c3dff8c1dd37f3ede82993eaf932e6
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_src/croutine.su
@@ -0,0 +1,7 @@
+croutine.c:131:22:xCoRoutineCreate 32 static
+croutine.c:188:6:vCoRoutineAddToDelayedList 24 static
+croutine.c:226:13:prvCheckPendingReadyList 16 static
+croutine.c:249:13:prvCheckDelayedList 16 static
+croutine.c:307:6:vCoRoutineSchedule 16 static
+croutine.c:337:13:prvInitialiseCoRoutineLists 16 static
+croutine.c:357:22:xCoRoutineRemoveFromEventList 24 static
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_src/list.su b/TP2_bpsk_demod/Debug/FreeRTOS_src/list.su
new file mode 100644
index 0000000000000000000000000000000000000000..27b9673007d2cc866f17f2f8b417fab90a30081f
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_src/list.su
@@ -0,0 +1,5 @@
+list.c:69:6:vListInitialise 16 static
+list.c:89:6:vListInitialiseItem 16 static
+list.c:96:6:vListInsertEnd 24 static
+list.c:119:6:vListInsert 24 static
+list.c:176:6:vListRemove 24 static
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_src/queue.su b/TP2_bpsk_demod/Debug/FreeRTOS_src/queue.su
new file mode 100644
index 0000000000000000000000000000000000000000..1156afc5f3029f9558ceadd34cc7f7d7076ecb58
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_src/queue.su
@@ -0,0 +1,20 @@
+queue.c:252:14:xQueueCreate 32 static
+queue.c:354:16:xQueueGiveMutexRecursive 32 static
+queue.c:403:16:xQueueTakeMutexRecursive 32 static
+queue.c:443:15:xQueueCreateCountingSemaphore 24 static
+queue.c:467:22:xQueueGenericSend 40 static
+queue.c:792:22:xQueueGenericSendFromISR 32 static
+queue.c:849:22:xQueueGenericReceive 40 static
+queue.c:999:22:xQueueReceiveFromISR 32 static
+queue.c:1054:24:uxQueueMessagesWaiting 24 static
+queue.c:1068:24:uxQueueMessagesWaitingFromISR 24 static
+queue.c:1080:6:vQueueDelete 16 static
+queue.c:1091:13:prvCopyDataToQueue 24 static
+queue.c:1129:13:prvCopyDataFromQueue 16 static
+queue.c:1143:13:prvUnlockQueue 16 static
+queue.c:1207:29:prvIsQueueEmpty 24 static
+queue.c:1219:22:xQueueIsQueueEmptyFromISR 24 static
+queue.c:1230:29:prvIsQueueFull 24 static
+queue.c:1242:22:xQueueIsQueueFullFromISR 24 static
+queue.c:1467:7:vQueueAddToRegistry 24 static
+queue.c:1490:14:vQueueUnregisterQueue 24 static
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_src/subdir.mk b/TP2_bpsk_demod/Debug/FreeRTOS_src/subdir.mk
new file mode 100644
index 0000000000000000000000000000000000000000..1ff38f55515bce28e4f363dcbf5dc345ea2e8b79
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_src/subdir.mk
@@ -0,0 +1,36 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../FreeRTOS_src/croutine.c \
+../FreeRTOS_src/list.c \
+../FreeRTOS_src/queue.c \
+../FreeRTOS_src/tasks.c \
+../FreeRTOS_src/timers.c
+
+OBJS += \
+./FreeRTOS_src/croutine.o \
+./FreeRTOS_src/list.o \
+./FreeRTOS_src/queue.o \
+./FreeRTOS_src/tasks.o \
+./FreeRTOS_src/timers.o
+
+C_DEPS += \
+./FreeRTOS_src/croutine.d \
+./FreeRTOS_src/list.d \
+./FreeRTOS_src/queue.d \
+./FreeRTOS_src/tasks.d \
+./FreeRTOS_src/timers.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+FreeRTOS_src/%.o: ../FreeRTOS_src/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -D__USE_CMSIS=CMSISv2p00_LPC17xx -DDEBUG -D__CODE_RED -DPACK_STRUCT_END=__attribute\(\(packed\)\) -DGCC_ARMCM3 -I../src -I"C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\inc" -I../FreeRTOS_include -I../FreeRTOS_portable -O0 -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_src/tasks.su b/TP2_bpsk_demod/Debug/FreeRTOS_src/tasks.su
new file mode 100644
index 0000000000000000000000000000000000000000..3d49d266e5b386336d19ea7631fc21af5e580be3
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/FreeRTOS_src/tasks.su
@@ -0,0 +1,33 @@
+tasks.c:439:22:xTaskGenericCreate 48 static
+tasks.c:608:7:vTaskDelete 24 static
+tasks.c:674:7:vTaskDelayUntil 32 static
+tasks.c:739:7:vTaskDelay 24 static
+tasks.c:785:25:uxTaskPriorityGet 24 static
+tasks.c:807:7:vTaskPrioritySet 32 static
+tasks.c:915:7:vTaskSuspend 24 static
+tasks.c:979:23:xTaskIsTaskSuspended 24 static
+tasks.c:1013:7:vTaskResume 24 static
+tasks.c:1058:16:xTaskResumeFromISR 24 static
+tasks.c:1099:6:vTaskStartScheduler 32 static
+tasks.c:1153:6:vTaskEndScheduler 8 static
+tasks.c:1164:6:vTaskSuspendAll 4 static
+tasks.c:1172:22:xTaskResumeAll 24 static
+tasks.c:1259:14:xTaskGetTickCount 16 static
+tasks.c:1274:14:xTaskGetTickCountFromISR 16 static
+tasks.c:1287:24:uxTaskGetNumberOfTasks 4 static
+tasks.c:1478:6:vTaskIncrementTick 24 static
+tasks.c:1693:6:vTaskSwitchContext 16 static
+tasks.c:1754:6:vTaskPlaceOnEventList 24 static
+tasks.c:1836:22:xTaskRemoveFromEventList 24 static
+tasks.c:1887:6:vTaskSetTimeOutState 16 static
+tasks.c:1895:15:xTaskCheckForTimeOut 24 static
+tasks.c:1941:6:vTaskMissedYield 4 static
+tasks.c:1957:8:prvIdleTask 16 static
+tasks.c:2022:13:prvInitialiseTCBVariables 24 static
+tasks.c:2108:13:prvInitialiseTaskLists 16 static
+tasks.c:2140:13:prvCheckTasksWaitingTermination 16 static
+tasks.c:2175:13:prvAddCurrentTaskToDelayedList 16 static
+tasks.c:2201:16:prvAllocateTCBAndStack 24 static
+tasks.c:2337:24:usTaskCheckFreeStackSpace 16 static
+tasks.c:2357:25:uxTaskGetStackHighWaterMark 32 static
+tasks.c:2385:14:prvDeleteTCB 16 static
diff --git a/TP2_bpsk_demod/Debug/FreeRTOS_src/timers.su b/TP2_bpsk_demod/Debug/FreeRTOS_src/timers.su
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/TP2_bpsk_demod/Debug/TP2_bpsk_demod.map b/TP2_bpsk_demod/Debug/TP2_bpsk_demod.map
new file mode 100644
index 0000000000000000000000000000000000000000..04bac94f9db4e6df046205a1c7acbdd99aec8a0b
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/TP2_bpsk_demod.map
@@ -0,0 +1,1367 @@
+Archive member included to satisfy reference by file (symbol)
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ ./src/bpsk_demod.o (ethernet_init)
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o) (rx_eth)
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ ./src/cr_startup_lpc175x_6x.o (SystemInit)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(_cr__main.o)
+ ./src/cr_startup_lpc175x_6x.o (__main)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ ./src/bpsk_demod.o (memset)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(ceil.o)
+ ./src/processing.o (ceil)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(cos.o)
+ ./src/processing.o (cos)
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+ ./src/debug.o (fclose)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fflush.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fclose.o) (fflush)
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+ ./src/processing.o (floor)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fopen.o)
+ ./src/debug.o (fopen)
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+ ./src/debug.o (fprintf)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(freopen.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fopen.o) (freopen)
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+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_istty.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_istty.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_istty.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_open.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_open.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_open.o)
+ .text.__sys_open
+ 0x00000000 0xc c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_open.o)
+ .ARM.attributes
+ 0x00000000 0x1b c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_open.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_remove.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_remove.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_remove.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_rename.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_rename.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_rename.o)
+ .text.__sys_rename
+ 0x00000000 0xc c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_rename.o)
+ .ARM.attributes
+ 0x00000000 0x1b c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_rename.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_seek.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_seek.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_seek.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_tmpnam.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_tmpnam.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_tmpnam.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_write.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_write.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_write.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+ 0x2007fd18 __user_heap_base = __end_bss_RAM2
+LOAD ./src/bpsk_demod.o
+LOAD ./src/cr_startup_lpc175x_6x.o
+LOAD ./src/debug.o
+LOAD ./src/mod_sig.o
+LOAD ./src/processing.o
+LOAD ./src/utils.o
+LOAD C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a
+LOAD C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp\libcr_eabihelpers.a
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp\libgcc.a
+END GROUP
+ 0x00000000 __base_MFlash512 = 0x0
+ 0x00000000 __base_Flash = 0x0
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x00080000 __top_Flash = 0x80000
+ 0x10000000 __base_RamLoc32 = 0x10000000
+ 0x10000000 __base_RAM = 0x10000000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x10008000 __top_RAM = 0x10008000
+ 0x2007c000 __base_RamAHB32 = 0x2007c000
+ 0x2007c000 __base_RAM2 = 0x2007c000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+ 0x20084000 __top_RAM2 = 0x20084000
+
+.text 0x00000000 0x39c8
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc175x_6x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x76e0 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x40 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x39c8 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x3d18 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000040 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0xc0c SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007fd18 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x12c ./src/cr_startup_lpc175x_6x.o
+ 0x000000f4 data_init
+ 0x00000136 bss_init
+ 0x0000016c ResetISR
+ 0x000001e4 NMI_Handler
+ 0x000001ea HardFault_Handler
+ 0x000001f0 MemManage_Handler
+ 0x000001f6 BusFault_Handler
+ 0x000001fc UsageFault_Handler
+ 0x00000202 SVC_Handler
+ 0x00000208 DebugMon_Handler
+ 0x0000020e PendSV_Handler
+ 0x00000214 SysTick_Handler
+ 0x0000021a EINT3_IRQHandler
+ 0x0000021a CANActivity_IRQHandler
+ 0x0000021a TIMER3_IRQHandler
+ 0x0000021a UART0_IRQHandler
+ 0x0000021a UART1_IRQHandler
+ 0x0000021a EINT2_IRQHandler
+ 0x0000021a USBActivity_IRQHandler
+ 0x0000021a IntDefaultHandler
+ 0x0000021a PLL0_IRQHandler
+ 0x0000021a I2C0_IRQHandler
+ 0x0000021a I2C1_IRQHandler
+ 0x0000021a SSP0_IRQHandler
+ 0x0000021a I2S_IRQHandler
+ 0x0000021a I2C2_IRQHandler
+ 0x0000021a RTC_IRQHandler
+ 0x0000021a TIMER0_IRQHandler
+ 0x0000021a SPI_IRQHandler
+ 0x0000021a RIT_IRQHandler
+ 0x0000021a EINT1_IRQHandler
+ 0x0000021a TIMER1_IRQHandler
+ 0x0000021a UART2_IRQHandler
+ 0x0000021a ADC_IRQHandler
+ 0x0000021a SSP1_IRQHandler
+ 0x0000021a USB_IRQHandler
+ 0x0000021a BOD_IRQHandler
+ 0x0000021a PLL1_IRQHandler
+ 0x0000021a WDT_IRQHandler
+ 0x0000021a PWM1_IRQHandler
+ 0x0000021a QEI_IRQHandler
+ 0x0000021a EINT0_IRQHandler
+ 0x0000021a CAN_IRQHandler
+ 0x0000021a DMA_IRQHandler
+ 0x0000021a TIMER2_IRQHandler
+ 0x0000021a UART3_IRQHandler
+ 0x0000021a MCPWM_IRQHandler
+ *(.text*)
+ .text.main 0x00000220 0x16c ./src/bpsk_demod.o
+ 0x00000220 main
+ .text.round 0x0000038c 0x7a ./src/processing.o
+ 0x0000038c round
+ .text.fir 0x00000406 0x7e ./src/processing.o
+ 0x00000406 fir
+ *fill* 0x00000484 0x4 ff
+ .text.init_cos_sin
+ 0x00000488 0x110 ./src/processing.o
+ 0x00000488 init_cos_sin
+ .text.demod 0x00000598 0x6a ./src/processing.o
+ 0x00000598 demod
+ *fill* 0x00000602 0x2 ff
+ .text.dpsk_demod
+ 0x00000604 0x128 ./src/processing.o
+ 0x00000604 dpsk_demod
+ .text.NVIC_EnableIRQ
+ 0x0000072c 0x30 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .text.ENET_IRQHandler
+ 0x0000075c 0xa8 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ 0x0000075c ENET_IRQHandler
+ .text.ethernet_init
+ 0x00000804 0x48 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ 0x00000804 ethernet_init
+ .text.rec_eth 0x0000084c 0x58 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ 0x0000084c rec_eth
+ .text.WriteToPHY
+ 0x000008a4 0x4e C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ 0x000008a4 WriteToPHY
+ .text.ReadFromPHY
+ 0x000008f2 0x5e C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ 0x000008f2 ReadFromPHY
+ .text.init_eth_mac
+ 0x00000950 0x3a8 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ 0x00000950 init_eth_mac
+ .text.SystemInit
+ 0x00000cf8 0xdc C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x00000cf8 SystemInit
+ .text.__main 0x00000dd4 0xe c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(_cr__main.o)
+ 0x00000dd4 __CR_SEMIHOST
+ 0x00000dd4 __main
+ .text.memset 0x00000de2 0x4 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ 0x00000de2 memset
+ *fill* 0x00000de6 0x2 ff
+ .text.ceil 0x00000de8 0x88 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(ceil.o)
+ 0x00000de8 ceil
+ .text.cos 0x00000e70 0x60 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(cos.o)
+ 0x00000e70 cos
+ .text.fclose 0x00000ed0 0x58 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fclose.o)
+ 0x00000ed0 fclose
+ .text.fflush 0x00000f28 0x44 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fflush.o)
+ 0x00000f28 fflush
+ .text.floor 0x00000f6c 0x8c c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(floor.o)
+ 0x00000f6c floor
+ .text.fp_round
+ 0x00000ff8 0x4c c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
+ .text.pr_dec.constprop.1
+ 0x00001044 0x26 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
+ *fill* 0x0000106a 0x2 ff
+ .text.sprintf 0x0000106c 0x6c c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
+ 0x0000106c sprintf
+ .text.fp_display
+ 0x000010d8 0x948 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
+ .text.vsnprintf
+ 0x00001a20 0x68 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
+ 0x00001a20 vsnprintf
+ .text.printf 0x00001a88 0x54 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
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+ 0x2007fc38 demod_phase
+ .data.$RAM2 0x2007fcd8 0x40 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ 0x2007fcd8 rx_eth
+ 0x2007fcf8 tx_eth
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ 0x2007fd18 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_data_RAM2 = .)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ 0x10000000 . = ALIGN (0x4)
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x40 load address 0x000076e0
+ FILL mask 0xff
+ 0x10000000 _data = .
+ *(vtable)
+ *(.ramfunc*)
+ *(CodeQuickAccess)
+ *(DataQuickAccess)
+ *(RamFunction)
+ *(.data*)
+ .data.fir_filter
+ 0x10000000 0x34 ./src/bpsk_demod.o
+ 0x10000000 fir_filter
+ .data.rx_index
+ 0x10000034 0x4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ 0x10000034 rx_index
+ .data.TxIntDone
+ 0x10000038 0x1 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ *fill* 0x10000039 0x3 ff
+ .data.old_rx_index.5370
+ 0x1000003c 0x4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ 0x10000040 . = ALIGN (0x4)
+ 0x10000040 _edata = .
+
+.igot.plt 0x10000040 0x0 load address 0x00007720
+ .igot.plt 0x10000040 0x0 ./src/bpsk_demod.o
+
+.bss_RAM2 0x2007fd18 0x0
+ 0x2007fd18 . = ALIGN (0x4)
+ [!provide] PROVIDE (__start_bss_RAM2 = .)
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ 0x2007fd18 . = ALIGN ((. != 0x0)?0x4:0x1)
+ 0x2007fd18 PROVIDE (__end_bss_RAM2 = .)
+
+.bss 0x10000040 0xc0c
+ 0x10000040 . = ALIGN (0x4)
+ 0x10000040 _bss = .
+ *(.bss*)
+ .bss.calc_duration_tot
+ 0x10000040 0x4 ./src/bpsk_demod.o
+ 0x10000040 calc_duration_tot
+ .bss.rx_irq_callback
+ 0x10000044 0x4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .bss.max_len_tx
+ 0x10000048 0x4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .bss.errno 0x1000004c 0x4 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(errno.o)
+ 0x1000004c errno
+ .bss.__end_of_heap
+ 0x10000050 0x4 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__init_alloc.o)
+ 0x10000050 __end_of_heap
+ .bss.__heaps 0x10000054 0x4 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__init_alloc.o)
+ 0x10000054 __heaps
+ .bss.__Ciob 0x10000058 0x1e0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__ciob.o)
+ 0x10000058 __Ciob
+ *(COMMON)
+ COMMON 0x10000238 0x9e0 ./src/bpsk_demod.o
+ 0x10000238 tmp
+ 0x1000023c demod_data
+ 0x100002a8 calc_duration_us
+ 0x100002ac duration_tot
+ 0x100002b0 rx_dat
+ 0x100002b4 stat
+ 0x10000c14 start
+ COMMON 0x10000c18 0x34 ./src/processing.o
+ 0x10000c18 bits
+ 0x10000c40 cos_table6
+ 0x10000c48 sin_table4
+ 0x10000c4c . = ALIGN (0x4)
+ 0x10000c4c _ebss = .
+ [!provide] PROVIDE (end = .)
+
+.noinit_RAM2 0x2007fd18 0x0
+ 0x2007fd18 . = ALIGN (0x4)
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ 0x2007fd18 . = ALIGN (0x4)
+
+.noinit 0x10000c4c 0x0
+ 0x10000c4c . = ALIGN (0x4)
+ 0x10000c4c _noinit = .
+ *(.noinit*)
+ 0x10000c4c . = ALIGN (0x4)
+ 0x10000c4c _end_noinit = .
+ 0x10000c4c PROVIDE (_pvHeapStart = DEFINED (__user_heap_base)?__user_heap_base:.)
+ 0x10008000 PROVIDE (_vStackTop = DEFINED (__user_stack_top)?__user_stack_top:(__top_RamLoc32 - 0x0))
+ 0xefff74de PROVIDE (__valid_user_code_checksum = (0x0 - ((((((_vStackTop + (ResetISR + 0x1)) + (NMI_Handler + 0x1)) + (HardFault_Handler + 0x1)) + (DEFINED (MemManage_Handler)?MemManage_Handler:0x0 + 0x1)) + (DEFINED (BusFault_Handler)?BusFault_Handler:0x0 + 0x1)) + (DEFINED (UsageFault_Handler)?UsageFault_Handler:0x0 + 0x1))))
+ 0x00000000 _image_start = LOADADDR (.text)
+ 0x00007720 _image_end = (LOADADDR (.data) + SIZEOF (.data))
+ 0x00007720 _image_size = (_image_end - _image_start)
+OUTPUT(TP2_bpsk_demod.axf elf32-littlearm)
+
+.debug_info 0x00000000 0x290d
+ .debug_info 0x00000000 0x93a ./src/bpsk_demod.o
+ .debug_info 0x0000093a 0x276 ./src/cr_startup_lpc175x_6x.o
+ .debug_info 0x00000bb0 0x4b0 ./src/processing.o
+ .debug_info 0x00001060 0xa2b C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_info 0x00001a8b 0xb05 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_info 0x00002590 0x37d C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_abbrev 0x00000000 0x99e
+ .debug_abbrev 0x00000000 0x1b7 ./src/bpsk_demod.o
+ .debug_abbrev 0x000001b7 0x12a ./src/cr_startup_lpc175x_6x.o
+ .debug_abbrev 0x000002e1 0x16f ./src/processing.o
+ .debug_abbrev 0x00000450 0x246 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_abbrev 0x00000696 0x1ec C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_abbrev 0x00000882 0x11c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_aranges 0x00000000 0x188
+ .debug_aranges
+ 0x00000000 0x20 ./src/bpsk_demod.o
+ .debug_aranges
+ 0x00000020 0x80 ./src/cr_startup_lpc175x_6x.o
+ .debug_aranges
+ 0x000000a0 0x40 ./src/processing.o
+ .debug_aranges
+ 0x000000e0 0x40 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_aranges
+ 0x00000120 0x40 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_aranges
+ 0x00000160 0x28 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_ranges 0x00000000 0x128
+ .debug_ranges 0x00000000 0x10 ./src/bpsk_demod.o
+ .debug_ranges 0x00000010 0x70 ./src/cr_startup_lpc175x_6x.o
+ .debug_ranges 0x00000080 0x30 ./src/processing.o
+ .debug_ranges 0x000000b0 0x30 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_ranges 0x000000e0 0x30 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_ranges 0x00000110 0x18 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_macro 0x00000000 0x4881
+ .debug_macro 0x00000000 0x129 ./src/bpsk_demod.o
+ .debug_macro 0x00000129 0xaa8 ./src/bpsk_demod.o
+ .debug_macro 0x00000bd1 0x82 ./src/bpsk_demod.o
+ .debug_macro 0x00000c53 0x1c ./src/bpsk_demod.o
+ .debug_macro 0x00000c6f 0x2e ./src/bpsk_demod.o
+ .debug_macro 0x00000c9d 0x10 ./src/bpsk_demod.o
+ .debug_macro 0x00000cad 0x12e ./src/bpsk_demod.o
+ .debug_macro 0x00000ddb 0x5b3 ./src/bpsk_demod.o
+ .debug_macro 0x0000138e 0x18 ./src/bpsk_demod.o
+ .debug_macro 0x000013a6 0x7af ./src/bpsk_demod.o
+ .debug_macro 0x00001b55 0x2c7 ./src/bpsk_demod.o
+ .debug_macro 0x00001e1c 0xa0 ./src/bpsk_demod.o
+ .debug_macro 0x00001ebc 0x22 ./src/bpsk_demod.o
+ .debug_macro 0x00001ede 0xc4 ./src/bpsk_demod.o
+ .debug_macro 0x00001fa2 0x22 ./src/bpsk_demod.o
+ .debug_macro 0x00001fc4 0x549 ./src/bpsk_demod.o
+ .debug_macro 0x0000250d 0x10 ./src/bpsk_demod.o
+ .debug_macro 0x0000251d 0x1c ./src/bpsk_demod.o
+ .debug_macro 0x00002539 0x28 ./src/bpsk_demod.o
+ .debug_macro 0x00002561 0x1c ./src/bpsk_demod.o
+ .debug_macro 0x0000257d 0xc2 ./src/bpsk_demod.o
+ .debug_macro 0x0000263f 0x16 ./src/bpsk_demod.o
+ .debug_macro 0x00002655 0x1d ./src/cr_startup_lpc175x_6x.o
+ .debug_macro 0x00002672 0xdb ./src/processing.o
+ .debug_macro 0x0000274d 0x9a ./src/processing.o
+ .debug_macro 0x000027e7 0xdd C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_macro 0x000028c4 0xa78 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_macro 0x0000333c 0x12d C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_macro 0x00003469 0x28 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_macro 0x00003491 0x9a C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_macro 0x0000352b 0x7c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_macro 0x000035a7 0x5b2 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_macro 0x00003b59 0xc1 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_macro 0x00003c1a 0xa0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_macro 0x00003cba 0x12b C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .debug_macro 0x00003de5 0xa9c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_line 0x00000000 0x1549
+ .debug_line 0x00000000 0x3c1 ./src/bpsk_demod.o
+ .debug_line 0x000003c1 0x160 ./src/cr_startup_lpc175x_6x.o
+ .debug_line 0x00000521 0x52d ./src/processing.o
+ .debug_line 0x00000a4e 0x31f C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_line 0x00000d6d 0x3b0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_line 0x0000111d 0x42c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_str 0x00000000 0xbe2e
+ .debug_str 0x00000000 0xad8b ./src/bpsk_demod.o
+ 0xae49 (size before relaxing)
+ .debug_str 0x0000ad8b 0x1d6 ./src/cr_startup_lpc175x_6x.o
+ 0x2fcb (size before relaxing)
+ .debug_str 0x0000af61 0xa7 ./src/processing.o
+ 0x93d2 (size before relaxing)
+ .debug_str 0x0000b008 0x754 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ 0xa753 (size before relaxing)
+ .debug_str 0x0000b75c 0x2a0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ 0xa434 (size before relaxing)
+ .debug_str 0x0000b9fc 0x432 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x89cd (size before relaxing)
+
+.comment 0x00000000 0xf3
+ .comment 0x00000000 0x75 ./src/bpsk_demod.o
+ 0x76 (size before relaxing)
+ .comment 0x00000075 0x76 ./src/cr_startup_lpc175x_6x.o
+ .comment 0x00000075 0x76 ./src/processing.o
+ .comment 0x00000075 0x7e C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ 0x7f (size before relaxing)
+ .comment 0x000000f3 0x7f C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .comment 0x000000f3 0x76 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(_cr__main.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(ceil.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(cos.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fclose.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fflush.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(floor.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fseek.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(ftell.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(initio.o)
+ .comment 0x000000f3 0x76 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(printf.o)
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+ .debug_frame 0x00000278 0xd0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethernet_mgt.o)
+ .debug_frame 0x00000348 0xcc C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\TP2_bpsk_demod\Debug\libMylab_lib.a(ethmac.o)
+ .debug_frame 0x00000414 0x3c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\ptr_new\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
diff --git a/TP2_bpsk_demod/Debug/TP2_bpsk_mod.axf b/TP2_bpsk_demod/Debug/TP2_bpsk_mod.axf
new file mode 100644
index 0000000000000000000000000000000000000000..2888ad89bcfdbb1515f3925c66c9b737bc9e3624
Binary files /dev/null and b/TP2_bpsk_demod/Debug/TP2_bpsk_mod.axf differ
diff --git a/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug.ld b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug.ld
new file mode 100644
index 0000000000000000000000000000000000000000..e38d1a15b0c1f8a11673b0e4f63c96e006f504b2
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug.ld
@@ -0,0 +1,180 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2020
+ * Generated linker script file for LPC1769
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v11.0.1 [Build 2563] [2019-09-01] on 13 janv. 2020 15:30:45
+ */
+
+INCLUDE "TP2_recepteur_son_Debug_library.ld"
+INCLUDE "TP2_recepteur_son_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ } > MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamAHB32 AT>MFlash512
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) :
+ {
+ . = ALIGN(4) ;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 :
+ {
+ . = ALIGN(4) ;
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss :
+ {
+ . = ALIGN(4) ;
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) :
+ {
+ . = ALIGN(4) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4) ;
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_library.ld b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_library.ld
new file mode 100644
index 0000000000000000000000000000000000000000..f8218430104f7640f99bf82d8dd306a955765f0a
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_library.ld
@@ -0,0 +1,17 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2020
+ * Generated linker script file for LPC1769
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v11.0.1 [Build 2563] [2019-09-01] on 13 janv. 2020 15:30:45
+ */
+
+GROUP (
+ "libcr_semihost.a"
+ "libcr_c.a"
+ "libcr_eabihelpers.a"
+ "libgcc.a"
+)
diff --git a/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_memory.ld b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_memory.ld
new file mode 100644
index 0000000000000000000000000000000000000000..58e7d532443518b9bd2ff5d3f345f04a4207cb56
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_memory.ld
@@ -0,0 +1,32 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2020
+ * Generated linker script file for LPC1769
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v11.0.1 [Build 2563] [2019-09-01] on 13 janv. 2020 15:30:45
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
diff --git a/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_old.ld b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_old.ld
new file mode 100644
index 0000000000000000000000000000000000000000..eeb4c11c72cfeb848b6fea51833d08ea628355e0
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/TP2_recepteur_son_Debug_old.ld
@@ -0,0 +1,155 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from generic_c.ld (8.0.0 ())
+ * By LPCXpresso v8.0.0 [Build 526] [2015-11-23] on Wed May 17 19:26:18 CEST 2017
+ */
+
+
+INCLUDE "TP2_recepteur_son_Debug_library.ld"
+INCLUDE "TP2_recepteur_son_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+}
diff --git a/TP2_bpsk_demod/Debug/code_optimization.axf b/TP2_bpsk_demod/Debug/code_optimization.axf
new file mode 100644
index 0000000000000000000000000000000000000000..8bee2bf6657dbb934f9924cb352496ef3f7ba602
Binary files /dev/null and b/TP2_bpsk_demod/Debug/code_optimization.axf differ
diff --git a/TP2_bpsk_demod/Debug/code_optimization.map b/TP2_bpsk_demod/Debug/code_optimization.map
new file mode 100644
index 0000000000000000000000000000000000000000..b1407c535fd97b17b7def56c43f2fca3c0b2c24c
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/code_optimization.map
@@ -0,0 +1,1013 @@
+Archive member included to satisfy reference by file (symbol)
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ ./src/cr_startup_lpc175x_6x.o (SystemInit)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(_cr__main.o)
+ ./src/cr_startup_lpc175x_6x.o (__main)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(cos.o)
+ ./src/main.o (cos)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o)
+ ./src/main.o (printf)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(initio.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(_cr__main.o) (_initio)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(printf.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o) (__vfprintf)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(setvbuf.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(initio.o) (setvbuf)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(strlen.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(printf.o) (strlen)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o) (memset)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(_deferredlazyseek.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(fpprintf.o) (__flsbuf)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(_fdopen.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(initio.o) (_fdopen)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(_fflush.o)
+ c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(_deferredlazyseek.o) (_fflush)
+c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(_frexpl.o)
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+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_tmpnam.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_tmpnam.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_tmpnam.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_write.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_write.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_write.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+ 0x2007c000 __user_heap_base = __end_bss_RAM2
+LOAD ./src/cr_startup_lpc175x_6x.o
+LOAD ./src/main.o
+LOAD ./src/processing.o
+LOAD ./src/sig.o
+LOAD C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp\libcr_eabihelpers.a
+LOAD c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp\libgcc.a
+END GROUP
+ 0x00000000 __base_MFlash512 = 0x0
+ 0x00000000 __base_Flash = 0x0
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x00080000 __top_Flash = 0x80000
+ 0x10000000 __base_RamLoc32 = 0x10000000
+ 0x10000000 __base_RAM = 0x10000000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x10008000 __top_RAM = 0x10008000
+ 0x2007c000 __base_RamAHB32 = 0x2007c000
+ 0x2007c000 __base_RAM2 = 0x2007c000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+ 0x20084000 __top_RAM2 = 0x20084000
+
+.text 0x00000000 0x3f30
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc175x_6x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x3f30 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x3f30 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x1ec SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x12c ./src/cr_startup_lpc175x_6x.o
+ 0x000000f4 data_init
+ 0x00000136 bss_init
+ 0x0000016c ResetISR
+ 0x000001e4 NMI_Handler
+ 0x000001ea HardFault_Handler
+ 0x000001f0 MemManage_Handler
+ 0x000001f6 BusFault_Handler
+ 0x000001fc UsageFault_Handler
+ 0x00000202 SVC_Handler
+ 0x00000208 DebugMon_Handler
+ 0x0000020e PendSV_Handler
+ 0x00000214 SysTick_Handler
+ 0x0000021a EINT3_IRQHandler
+ 0x0000021a CANActivity_IRQHandler
+ 0x0000021a TIMER3_IRQHandler
+ 0x0000021a UART0_IRQHandler
+ 0x0000021a UART1_IRQHandler
+ 0x0000021a EINT2_IRQHandler
+ 0x0000021a USBActivity_IRQHandler
+ 0x0000021a IntDefaultHandler
+ 0x0000021a PLL0_IRQHandler
+ 0x0000021a I2C0_IRQHandler
+ 0x0000021a I2C1_IRQHandler
+ 0x0000021a SSP0_IRQHandler
+ 0x0000021a I2S_IRQHandler
+ 0x0000021a I2C2_IRQHandler
+ 0x0000021a RTC_IRQHandler
+ 0x0000021a TIMER0_IRQHandler
+ 0x0000021a SPI_IRQHandler
+ 0x0000021a RIT_IRQHandler
+ 0x0000021a EINT1_IRQHandler
+ 0x0000021a TIMER1_IRQHandler
+ 0x0000021a UART2_IRQHandler
+ 0x0000021a ADC_IRQHandler
+ 0x0000021a SSP1_IRQHandler
+ 0x0000021a USB_IRQHandler
+ 0x0000021a BOD_IRQHandler
+ 0x0000021a PLL1_IRQHandler
+ 0x0000021a WDT_IRQHandler
+ 0x0000021a PWM1_IRQHandler
+ 0x0000021a QEI_IRQHandler
+ 0x0000021a EINT0_IRQHandler
+ 0x0000021a CAN_IRQHandler
+ 0x0000021a DMA_IRQHandler
+ 0x0000021a TIMER2_IRQHandler
+ 0x0000021a UART3_IRQHandler
+ 0x0000021a MCPWM_IRQHandler
+ 0x0000021a ENET_IRQHandler
+ *(.text*)
+ .text.ex1 0x00000220 0x15c ./src/main.o
+ 0x00000220 ex1
+ *fill* 0x0000037c 0x4 ff
+ .text.ex2 0x00000380 0x138 ./src/main.o
+ 0x00000380 ex2
+ .text.main 0x000004b8 0x12 ./src/main.o
+ 0x000004b8 main
+ *fill* 0x000004ca 0x2 ff
+ .text.SystemInit
+ 0x000004cc 0xdc C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x000004cc SystemInit
+ .text.__main 0x000005a8 0xe c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(_cr__main.o)
+ 0x000005a8 __CR_SEMIHOST
+ 0x000005a8 __main
+ *fill* 0x000005b6 0x2 ff
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+ 0x000005b8 cos
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+ .text.pr_dec.constprop.1
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+ *fill* 0x0000068a 0x2 ff
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+ 0x0000068c sprintf
+ .text.fp_display
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+ .text.vsnprintf
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+ 0x00001040 vsnprintf
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+ 0x000010a8 printf
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+ 0x000010fc _initio
+ .text.__vfprintf
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+ 0x00001174 __vfprintf
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+ 0x00001d88 strlen
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+ 0x00001dd4 memset
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+ 0x00001e18 __flsbuf
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+ 0x00001f58 _fdopen
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+ 0x00000678 0x1b c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_istty.o)
+ .ARM.attributes
+ 0x00000693 0x1b c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_remove.o)
+ .ARM.attributes
+ 0x000006ae 0x1b c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_seek.o)
+ .ARM.attributes
+ 0x000006c9 0x1b c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_tmpnam.o)
+ .ARM.attributes
+ 0x000006e4 0x1b c:/nxp/mcuxpressoide_11.0.1_2563/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.0.1.201907311258/tools/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_semihost.a(__sys_write.o)
+
+.debug_frame 0x00000000 0x22c
+ .debug_frame 0x00000000 0x170 ./src/cr_startup_lpc175x_6x.o
+ .debug_frame 0x00000170 0x80 ./src/main.o
+ .debug_frame 0x000001f0 0x3c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
diff --git a/TP2_bpsk_demod/Debug/makefile b/TP2_bpsk_demod/Debug/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..ebc66c4b41714192bf241f0c4b14f91d313e1ce9
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/makefile
@@ -0,0 +1,49 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all: code_optimization.axf
+
+# Tool invocations
+code_optimization.axf: $(OBJS) $(USER_OBJS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Linker'
+ arm-none-eabi-gcc -nostdlib -L"C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug" -Xlinker -Map="code_optimization.map" -Xlinker --defsym=__user_heap_base=__end_bss_RAM2 -Xlinker --gc-sections -mcpu=cortex-m3 -mthumb -T "TP2_recepteur_son_Debug.ld" -o "code_optimization.axf" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+ $(MAKE) --no-print-directory post-build
+
+# Other Targets
+clean:
+ -$(RM) $(EXECUTABLES)$(OBJS)$(C_DEPS) code_optimization.axf
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size "code_optimization.axf"; # arm-none-eabi-objcopy -O binary "code_optimization.axf" "code_optimization.bin" ; checksum -p LPC1769 -d "code_optimization.bin";
+ -@echo ' '
+
+.PHONY: all clean dependents post-build
+
+-include ../makefile.targets
diff --git a/TP2_bpsk_demod/Debug/objects.mk b/TP2_bpsk_demod/Debug/objects.mk
new file mode 100644
index 0000000000000000000000000000000000000000..70f403d35b58b80be90d40fe1ce72037b290d48a
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS := -lCMSISv2p00_LPC17xx
+
diff --git a/TP2_bpsk_demod/Debug/sources.mk b/TP2_bpsk_demod/Debug/sources.mk
new file mode 100644
index 0000000000000000000000000000000000000000..2cc4ffba0948b388b04e3155f014047ab0417a1d
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/sources.mk
@@ -0,0 +1,18 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+OBJ_SRCS :=
+S_SRCS :=
+ASM_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+O_SRCS :=
+EXECUTABLES :=
+OBJS :=
+C_DEPS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
diff --git a/TP2_bpsk_demod/Debug/src/bpsk_demod.su b/TP2_bpsk_demod/Debug/src/bpsk_demod.su
new file mode 100644
index 0000000000000000000000000000000000000000..1bbd1fea9f6df60ab84c00d2c806759c8ced5e52
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/bpsk_demod.su
@@ -0,0 +1 @@
+bpsk_demod.c:57:5:main 32 static
diff --git a/TP2_bpsk_demod/Debug/src/cat.d b/TP2_bpsk_demod/Debug/src/cat.d
new file mode 100644
index 0000000000000000000000000000000000000000..43284d261af8ae45f5cd036bb418f69246d2db92
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/cat.d
@@ -0,0 +1,65 @@
+src/cat.o src/cat.d: ../src/cat.c ../src/dtmf_detection.h \
+ ../src/objects.h ../src/debug.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h \
+ ../FreeRTOS_include/FreeRTOS.h ../FreeRTOS_include/projdefs.h \
+ ../src/FreeRTOSConfig.h ../FreeRTOS_include/portable.h \
+ ../FreeRTOS_portable/portmacro.h ../FreeRTOS_include/mpu_wrappers.h \
+ ../FreeRTOS_include/task.h ../FreeRTOS_include/list.h \
+ ../FreeRTOS_include/queue.h ../FreeRTOS_include/semphr.h \
+ ../FreeRTOS_include/queue.h ../src/dtmf_detection.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h \
+ ../src/semaphores.h
+
+../src/dtmf_detection.h:
+
+../src/objects.h:
+
+../src/debug.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h:
+
+../FreeRTOS_include/FreeRTOS.h:
+
+../FreeRTOS_include/projdefs.h:
+
+../src/FreeRTOSConfig.h:
+
+../FreeRTOS_include/portable.h:
+
+../FreeRTOS_portable/portmacro.h:
+
+../FreeRTOS_include/mpu_wrappers.h:
+
+../FreeRTOS_include/task.h:
+
+../FreeRTOS_include/list.h:
+
+../FreeRTOS_include/queue.h:
+
+../FreeRTOS_include/semphr.h:
+
+../FreeRTOS_include/queue.h:
+
+../src/dtmf_detection.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h:
+
+../src/semaphores.h:
diff --git a/TP2_bpsk_demod/Debug/src/cat.o b/TP2_bpsk_demod/Debug/src/cat.o
new file mode 100644
index 0000000000000000000000000000000000000000..6a14c921f68eef79ff571722ee50f2e72b1105c2
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/cat.o differ
diff --git a/TP2_bpsk_demod/Debug/src/cr_startup_lpc17.su b/TP2_bpsk_demod/Debug/src/cr_startup_lpc17.su
new file mode 100644
index 0000000000000000000000000000000000000000..48b4e73eed30e327e3caf8cf5d64404b5f7b4c29
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/cr_startup_lpc17.su
@@ -0,0 +1,10 @@
+cr_startup_lpc17.c:220:6:data_init 40 static
+cr_startup_lpc17.c:229:6:bss_init 24 static
+cr_startup_lpc17.c:264:1:ResetISR 24 static
+cr_startup_lpc17.c:344:6:NMI_Handler 4 static
+cr_startup_lpc17.c:352:6:HardFault_Handler 4 static
+cr_startup_lpc17.c:359:6:MemManage_Handler 4 static
+cr_startup_lpc17.c:366:6:BusFault_Handler 4 static
+cr_startup_lpc17.c:373:6:UsageFault_Handler 4 static
+cr_startup_lpc17.c:381:6:DebugMon_Handler 4 static
+cr_startup_lpc17.c:395:6:IntDefaultHandler 4 static
diff --git a/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.d b/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.d
new file mode 100644
index 0000000000000000000000000000000000000000..f77cbd4abad2ce1b198bac637d891975acdf7d09
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.d
@@ -0,0 +1,2 @@
+src/cr_startup_lpc175x_6x.o src/cr_startup_lpc175x_6x.d: \
+ ../src/cr_startup_lpc175x_6x.c
diff --git a/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.o b/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.o
new file mode 100644
index 0000000000000000000000000000000000000000..816d607254719ed0cbb104be000f8cf1a6150691
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.o differ
diff --git a/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.su b/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.su
new file mode 100644
index 0000000000000000000000000000000000000000..f580aac27e582476eabd9014f47b3b8054a138c7
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/cr_startup_lpc175x_6x.su
@@ -0,0 +1,13 @@
+cr_startup_lpc175x_6x.c:233:6:data_init 40 static
+cr_startup_lpc175x_6x.c:242:6:bss_init 24 static
+cr_startup_lpc175x_6x.c:268:1:ResetISR 24 static
+cr_startup_lpc175x_6x.c:325:6:NMI_Handler 4 static
+cr_startup_lpc175x_6x.c:330:6:HardFault_Handler 4 static
+cr_startup_lpc175x_6x.c:335:6:MemManage_Handler 4 static
+cr_startup_lpc175x_6x.c:340:6:BusFault_Handler 4 static
+cr_startup_lpc175x_6x.c:345:6:UsageFault_Handler 4 static
+cr_startup_lpc175x_6x.c:350:6:SVC_Handler 4 static
+cr_startup_lpc175x_6x.c:355:6:DebugMon_Handler 4 static
+cr_startup_lpc175x_6x.c:360:6:PendSV_Handler 4 static
+cr_startup_lpc175x_6x.c:365:6:SysTick_Handler 4 static
+cr_startup_lpc175x_6x.c:376:6:IntDefaultHandler 4 static
diff --git a/TP2_bpsk_demod/Debug/src/debug.su b/TP2_bpsk_demod/Debug/src/debug.su
new file mode 100644
index 0000000000000000000000000000000000000000..14ef6cc96fe032ed7236e967e08c67ec9e2b5f10
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/debug.su
@@ -0,0 +1 @@
+debug.c:15:6:int2file 56 static
diff --git a/TP2_bpsk_demod/Debug/src/demodulator.d b/TP2_bpsk_demod/Debug/src/demodulator.d
new file mode 100644
index 0000000000000000000000000000000000000000..71cdec94ac7f2ea69b4eccfc951f72b3c3d92e4d
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/demodulator.d
@@ -0,0 +1,57 @@
+src/demodulator.o src/demodulator.d: ../src/demodulator.c \
+ ../src/demodulator.h ../src/gpio.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/adc.h \
+ ../src/debug.h ../FreeRTOS_include/FreeRTOS.h \
+ ../FreeRTOS_include/projdefs.h ../src/FreeRTOSConfig.h \
+ ../FreeRTOS_include/portable.h ../FreeRTOS_portable/portmacro.h \
+ ../FreeRTOS_include/mpu_wrappers.h ../FreeRTOS_include/task.h \
+ ../FreeRTOS_include/list.h ../FreeRTOS_include/queue.h \
+ ../FreeRTOS_include/semphr.h ../FreeRTOS_include/queue.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ledrgb_dma.h
+
+../src/demodulator.h:
+
+../src/gpio.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/adc.h:
+
+../src/debug.h:
+
+../FreeRTOS_include/FreeRTOS.h:
+
+../FreeRTOS_include/projdefs.h:
+
+../src/FreeRTOSConfig.h:
+
+../FreeRTOS_include/portable.h:
+
+../FreeRTOS_portable/portmacro.h:
+
+../FreeRTOS_include/mpu_wrappers.h:
+
+../FreeRTOS_include/task.h:
+
+../FreeRTOS_include/list.h:
+
+../FreeRTOS_include/queue.h:
+
+../FreeRTOS_include/semphr.h:
+
+../FreeRTOS_include/queue.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ledrgb_dma.h:
diff --git a/TP2_bpsk_demod/Debug/src/demodulator.o b/TP2_bpsk_demod/Debug/src/demodulator.o
new file mode 100644
index 0000000000000000000000000000000000000000..ac06e1ceb6e79121690b6dfe3ec90b7e9241e1e5
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/demodulator.o differ
diff --git a/TP2_bpsk_demod/Debug/src/gpio.su b/TP2_bpsk_demod/Debug/src/gpio.su
new file mode 100644
index 0000000000000000000000000000000000000000..49045240f639573f43d4e2aede83c044df379e60
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/gpio.su
@@ -0,0 +1,5 @@
+core_cm3.h:928:22:NVIC_EnableIRQ 16 static
+gpio.c:22:6:EINT3_IRQHandler 16 static
+gpio.c:33:6:init_gpio 32 static
+gpio.c:62:6:set_gpio 24 static
+gpio.c:70:6:get_gpio 16 static
diff --git a/TP2_bpsk_demod/Debug/src/main.d b/TP2_bpsk_demod/Debug/src/main.d
new file mode 100644
index 0000000000000000000000000000000000000000..66999b8dbc177d87694a3dd1e103ed7519e0eb6a
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/main.d
@@ -0,0 +1,3 @@
+src/main.o src/main.d: ../src/main.c ../src/config_LPC1769.h
+
+../src/config_LPC1769.h:
diff --git a/TP2_bpsk_demod/Debug/src/main.o b/TP2_bpsk_demod/Debug/src/main.o
new file mode 100644
index 0000000000000000000000000000000000000000..039888ddfd135731461872d637a75164192651e9
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/main.o differ
diff --git a/TP2_bpsk_demod/Debug/src/main.su b/TP2_bpsk_demod/Debug/src/main.su
new file mode 100644
index 0000000000000000000000000000000000000000..3c8b66d9cf3800f02764bb19011278a9a1d56670
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/main.su
@@ -0,0 +1,3 @@
+main.c:17:6:ex1 64 static
+main.c:54:6:ex2 312 static
+main.c:79:5:main 8 static
diff --git a/TP2_bpsk_demod/Debug/src/main_solution.su b/TP2_bpsk_demod/Debug/src/main_solution.su
new file mode 100644
index 0000000000000000000000000000000000000000..c12890fcf2db8c0413cc8fe1180a5f124981d7b0
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/main_solution.su
@@ -0,0 +1,3 @@
+main_solution.c:39:6:ex1 64 static
+main_solution.c:88:6:ex2 312 static
+main_solution.c:118:5:main 8 static
diff --git a/TP2_bpsk_demod/Debug/src/mod_sig.su b/TP2_bpsk_demod/Debug/src/mod_sig.su
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/TP2_bpsk_demod/Debug/src/mouse.d b/TP2_bpsk_demod/Debug/src/mouse.d
new file mode 100644
index 0000000000000000000000000000000000000000..ddfde1b9b7a83b9e89aec7c40fb0c60cd78c2fea
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/mouse.d
@@ -0,0 +1,68 @@
+src/mouse.o src/mouse.d: ../src/mouse.c ../FreeRTOS_include/FreeRTOS.h \
+ ../FreeRTOS_include/projdefs.h ../src/FreeRTOSConfig.h \
+ ../FreeRTOS_include/portable.h ../FreeRTOS_portable/portmacro.h \
+ ../FreeRTOS_include/mpu_wrappers.h ../FreeRTOS_include/task.h \
+ ../FreeRTOS_include/list.h ../FreeRTOS_include/queue.h \
+ ../FreeRTOS_include/semphr.h ../FreeRTOS_include/queue.h ../src/mouse.h \
+ ../src/objects.h ../src/gpio.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h \
+ ../src/debug.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/custom_rand.h \
+ ../src/semaphores.h
+
+../FreeRTOS_include/FreeRTOS.h:
+
+../FreeRTOS_include/projdefs.h:
+
+../src/FreeRTOSConfig.h:
+
+../FreeRTOS_include/portable.h:
+
+../FreeRTOS_portable/portmacro.h:
+
+../FreeRTOS_include/mpu_wrappers.h:
+
+../FreeRTOS_include/task.h:
+
+../FreeRTOS_include/list.h:
+
+../FreeRTOS_include/queue.h:
+
+../FreeRTOS_include/semphr.h:
+
+../FreeRTOS_include/queue.h:
+
+../src/mouse.h:
+
+../src/objects.h:
+
+../src/gpio.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h:
+
+../src/debug.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/custom_rand.h:
+
+../src/semaphores.h:
diff --git a/TP2_bpsk_demod/Debug/src/mouse.o b/TP2_bpsk_demod/Debug/src/mouse.o
new file mode 100644
index 0000000000000000000000000000000000000000..2404287448b9f5e6691fe2cf010eb624cf7a6b92
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/mouse.o differ
diff --git a/TP2_bpsk_demod/Debug/src/processing.o b/TP2_bpsk_demod/Debug/src/processing.o
new file mode 100644
index 0000000000000000000000000000000000000000..47f89e44adb8689a53b8e37cabbde47573cf50a1
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/processing.o differ
diff --git a/TP2_bpsk_demod/Debug/src/processing.su b/TP2_bpsk_demod/Debug/src/processing.su
new file mode 100644
index 0000000000000000000000000000000000000000..d5dc71c0e9695c20a43b9c801768673fc7bdfe48
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/processing.su
@@ -0,0 +1,5 @@
+processing.c:19:8:round 24 static
+processing.c:31:6:fir 40 static
+processing.c:51:6:init_cos_sin 24 static
+processing.c:63:6:demod 32 static
+processing.c:75:6:dpsk_demod 32 static
diff --git a/TP2_bpsk_demod/Debug/src/sig.d b/TP2_bpsk_demod/Debug/src/sig.d
new file mode 100644
index 0000000000000000000000000000000000000000..a74559da34d86d47c4844a141ad3a3d3c569ba61
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/sig.d
@@ -0,0 +1 @@
+src/sig.o src/sig.d: ../src/sig.c
diff --git a/TP2_bpsk_demod/Debug/src/sig.o b/TP2_bpsk_demod/Debug/src/sig.o
new file mode 100644
index 0000000000000000000000000000000000000000..d14f3c6193a679c8a26e18d91f6a9ff73b194d5a
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/sig.o differ
diff --git a/TP2_bpsk_demod/Debug/src/sig.su b/TP2_bpsk_demod/Debug/src/sig.su
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/TP2_bpsk_demod/Debug/src/subdir.mk b/TP2_bpsk_demod/Debug/src/subdir.mk
new file mode 100644
index 0000000000000000000000000000000000000000..14ea6d6276cc45410e50db8a79d612f131f34d9e
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/subdir.mk
@@ -0,0 +1,41 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+S_SRCS += \
+../src/processing.s
+
+C_SRCS += \
+../src/cr_startup_lpc175x_6x.c \
+../src/main.c \
+../src/sig.c
+
+OBJS += \
+./src/cr_startup_lpc175x_6x.o \
+./src/main.o \
+./src/processing.o \
+./src/sig.o
+
+C_DEPS += \
+./src/cr_startup_lpc175x_6x.d \
+./src/main.d \
+./src/sig.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -D__USE_CMSIS=CMSISv2p00_LPC17xx -DDEBUG -D__CODE_RED -DPACK_STRUCT_END=__attribute\(\(packed\)\) -DGCC_ARMCM3 -I../src -I"C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc" -I../FreeRTOS_include -I../FreeRTOS_portable -O0 -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+src/%.o: ../src/%.s
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU Assembler'
+ arm-none-eabi-gcc -c -x assembler-with-cpp -DDEBUG -D__CODE_RED -D__REDLIB__ -g3 -mcpu=cortex-m3 -mthumb -D__REDLIB__ -specs=redlib.specs -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/TP2_bpsk_demod/Debug/src/timer.d b/TP2_bpsk_demod/Debug/src/timer.d
new file mode 100644
index 0000000000000000000000000000000000000000..16d3ee16c451a96894d6ba5bed930d1955bdda07
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/timer.d
@@ -0,0 +1,54 @@
+src/timer.o src/timer.d: ../src/timer.c \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h \
+ ../src/timer.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\lib_tool\inc/read_mic.h \
+ ../src/sin_detector.h ../src/semaphores.h ../FreeRTOS_include/FreeRTOS.h \
+ ../FreeRTOS_include/projdefs.h ../src/FreeRTOSConfig.h \
+ ../FreeRTOS_include/portable.h ../FreeRTOS_portable/portmacro.h \
+ ../FreeRTOS_include/mpu_wrappers.h ../FreeRTOS_include/task.h \
+ ../FreeRTOS_include/list.h ../FreeRTOS_include/queue.h \
+ ../FreeRTOS_include/semphr.h ../FreeRTOS_include/queue.h
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h:
+
+../src/timer.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\lib_tool\inc/read_mic.h:
+
+../src/sin_detector.h:
+
+../src/semaphores.h:
+
+../FreeRTOS_include/FreeRTOS.h:
+
+../FreeRTOS_include/projdefs.h:
+
+../src/FreeRTOSConfig.h:
+
+../FreeRTOS_include/portable.h:
+
+../FreeRTOS_portable/portmacro.h:
+
+../FreeRTOS_include/mpu_wrappers.h:
+
+../FreeRTOS_include/task.h:
+
+../FreeRTOS_include/list.h:
+
+../FreeRTOS_include/queue.h:
+
+../FreeRTOS_include/semphr.h:
+
+../FreeRTOS_include/queue.h:
diff --git a/TP2_bpsk_demod/Debug/src/tp2_cat_and_mouse.d b/TP2_bpsk_demod/Debug/src/tp2_cat_and_mouse.d
new file mode 100644
index 0000000000000000000000000000000000000000..0e073755ca0449936b20820b5547c9b5d4dab0fd
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/tp2_cat_and_mouse.d
@@ -0,0 +1,80 @@
+src/tp2_cat_and_mouse.o src/tp2_cat_and_mouse.d: \
+ ../src/tp2_cat_and_mouse.c ../src/dtmf_detection.h ../src/objects.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ethmac.h \
+ ../FreeRTOS_include/FreeRTOS.h ../FreeRTOS_include/projdefs.h \
+ ../src/FreeRTOSConfig.h ../FreeRTOS_include/portable.h \
+ ../FreeRTOS_portable/portmacro.h ../FreeRTOS_include/mpu_wrappers.h \
+ ../FreeRTOS_include/task.h ../FreeRTOS_include/list.h \
+ ../FreeRTOS_include/queue.h ../FreeRTOS_include/semphr.h \
+ ../FreeRTOS_include/queue.h ../src/cat.h ../src/mouse.h ../src/gpio.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h \
+ ../src/debug.h ../src/traces_ref.h ../src/trace_mgt.h \
+ ../src/FreeRTOSConfig.h \
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/custom_rand.h
+
+../src/dtmf_detection.h:
+
+../src/objects.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ethmac.h:
+
+../FreeRTOS_include/FreeRTOS.h:
+
+../FreeRTOS_include/projdefs.h:
+
+../src/FreeRTOSConfig.h:
+
+../FreeRTOS_include/portable.h:
+
+../FreeRTOS_portable/portmacro.h:
+
+../FreeRTOS_include/mpu_wrappers.h:
+
+../FreeRTOS_include/task.h:
+
+../FreeRTOS_include/list.h:
+
+../FreeRTOS_include/queue.h:
+
+../FreeRTOS_include/semphr.h:
+
+../FreeRTOS_include/queue.h:
+
+../src/cat.h:
+
+../src/mouse.h:
+
+../src/gpio.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h:
+
+../src/debug.h:
+
+../src/traces_ref.h:
+
+../src/trace_mgt.h:
+
+../src/FreeRTOSConfig.h:
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/custom_rand.h:
diff --git a/TP2_bpsk_demod/Debug/src/tp2_cat_and_mouse.o b/TP2_bpsk_demod/Debug/src/tp2_cat_and_mouse.o
new file mode 100644
index 0000000000000000000000000000000000000000..3859edf271b054c4114396813073f49a39085d29
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/tp2_cat_and_mouse.o differ
diff --git a/TP2_bpsk_demod/Debug/src/tp2_son.d b/TP2_bpsk_demod/Debug/src/tp2_son.d
new file mode 100644
index 0000000000000000000000000000000000000000..c5da9897ce9424a639d7d8c9959cc90ffce3b576
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/tp2_son.d
@@ -0,0 +1,63 @@
+src/tp2_son.o src/tp2_son.d: ../src/tp2_son.c ../src/demodulator.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ethmac.h \
+ ../FreeRTOS_include/FreeRTOS.h ../FreeRTOS_include/projdefs.h \
+ ../src/FreeRTOSConfig.h ../FreeRTOS_include/portable.h \
+ ../FreeRTOS_portable/portmacro.h ../FreeRTOS_include/mpu_wrappers.h \
+ ../FreeRTOS_include/task.h ../FreeRTOS_include/list.h \
+ ../FreeRTOS_include/queue.h ../FreeRTOS_include/semphr.h \
+ ../FreeRTOS_include/queue.h ../src/gpio.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h \
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h \
+ ../src/debug.h
+
+../src/demodulator.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ethmac.h:
+
+../FreeRTOS_include/FreeRTOS.h:
+
+../FreeRTOS_include/projdefs.h:
+
+../src/FreeRTOSConfig.h:
+
+../FreeRTOS_include/portable.h:
+
+../FreeRTOS_portable/portmacro.h:
+
+../FreeRTOS_include/mpu_wrappers.h:
+
+../FreeRTOS_include/task.h:
+
+../FreeRTOS_include/list.h:
+
+../FreeRTOS_include/queue.h:
+
+../FreeRTOS_include/semphr.h:
+
+../FreeRTOS_include/queue.h:
+
+../src/gpio.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cm3.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmInstr.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/core_cmFunc.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/lcd.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/ssp.h:
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\w_exercices\MyLab_lib\inc/fonts.h:
+
+../src/debug.h:
diff --git a/TP2_bpsk_demod/Debug/src/tp2_son.o b/TP2_bpsk_demod/Debug/src/tp2_son.o
new file mode 100644
index 0000000000000000000000000000000000000000..902441d77383ae7e964c8fb61bb50ec18bafb4f7
Binary files /dev/null and b/TP2_bpsk_demod/Debug/src/tp2_son.o differ
diff --git a/TP2_bpsk_demod/Debug/src/trace_mgt.su b/TP2_bpsk_demod/Debug/src/trace_mgt.su
new file mode 100644
index 0000000000000000000000000000000000000000..b4c8c2e227cad473418480283802df5901a863e8
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/trace_mgt.su
@@ -0,0 +1 @@
+trace_mgt.c:46:6:write_trace 16 static
diff --git a/TP2_bpsk_demod/Debug/src/uart.su b/TP2_bpsk_demod/Debug/src/uart.su
new file mode 100644
index 0000000000000000000000000000000000000000..e21e32a074433d1b7d70cfd41df6253313e35bfd
--- /dev/null
+++ b/TP2_bpsk_demod/Debug/src/uart.su
@@ -0,0 +1,2 @@
+uart.c:20:6:uart0_init 24 static
+uart.c:44:6:uart0_send 16 static
diff --git a/TP2_bpsk_demod/code_optimization LinkServer Debug.launch b/TP2_bpsk_demod/code_optimization LinkServer Debug.launch
new file mode 100644
index 0000000000000000000000000000000000000000..a63335e24c37fa403164a12bc1ea9c5874be5cf8
--- /dev/null
+++ b/TP2_bpsk_demod/code_optimization LinkServer Debug.launch
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
+<stringAttribute key=".gdbinit" value=""/>
+<booleanAttribute key="attach" value="false"/>
+<stringAttribute key="bootrom.stall" value=""/>
+<stringAttribute key="com.crt.ctrlcenter.OFSemuDetails" value="LinkServer"/>
+<booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
+<stringAttribute key="com.crt.ctrlcenter.currentWireType" value="SWD"/>
+<booleanAttribute key="com.crt.ctrlcenter.mainBreakIsHardware" value="true"/>
+<stringAttribute key="com.crt.ctrlcenter.serialNumber" value="LinkServerNXPNXP CMSIS-DAPUNKNOWN_SERIAL"/>
+<mapAttribute key="com.crt.ctrlcenter.symbolsGroupSettings"/>
+<intAttribute key="com.crt.ctrlcenter.version" value="6"/>
+<stringAttribute key="com.nxp.mcuxpresso.flash.base.address" value="0x0"/>
+<booleanAttribute key="com.nxp.mcuxpresso.flash.clear.console" value="true"/>
+<booleanAttribute key="com.nxp.mcuxpresso.flash.confirm" value="false"/>
+<stringAttribute key="com.nxp.mcuxpresso.flash.erase.algorithm" value="Mass erase"/>
+<stringAttribute key="com.nxp.mcuxpresso.flash.executable" value="axf"/>
+<stringAttribute key="com.nxp.mcuxpresso.flash.program.action" value="Program"/>
+<booleanAttribute key="com.nxp.mcuxpresso.flash.reset.target" value="true"/>
+<stringAttribute key="com.nxp.mcuxpresso.ide.probe.manufacturer" value="NXP"/>
+<stringAttribute key="com.nxp.mcuxpresso.ide.probe.name" value="NXP CMSIS-DAP"/>
+<stringAttribute key="com.nxp.mcuxpresso.ide.probe.type" value="LinkServer"/>
+<stringAttribute key="debug.level" value="2"/>
+<stringAttribute key="emu.speed" value=""/>
+<stringAttribute key="flash.driver.reset" value=""/>
+<stringAttribute key="internal.connect.script" value=""/>
+<booleanAttribute key="internal.has_swo" value="true"/>
+<stringAttribute key="internal.prelaunch.command" value=""/>
+<stringAttribute key="internal.reset.script" value=""/>
+<stringAttribute key="internal.resethandling" value="VECTRESET"/>
+<stringAttribute key="internal.semihost" value="On"/>
+<stringAttribute key="internal.wirespeed" value=""/>
+<stringAttribute key="internal.wiretype" value="SWD*,JTAG"/>
+<stringAttribute key="launch.config.handler" value="com.crt.ctrlcenter.launch.CRTLaunchConfigHandler"/>
+<booleanAttribute key="mem.access" value="false"/>
+<stringAttribute key="misc.options" value=""/>
+<stringAttribute key="ondisconnect" value="cont"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set non-stop on set pagination off set mi-async set remotetimeout 60000 ##target_extended_remote## set mem inaccessible-by-default ${mem.access} mon ondisconnect ${ondisconnect} set arm force-mode thumb ${load} 	"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=" ${run} 	"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.EXTERNAL_CONSOLE" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=""/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\code_optimization.axf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="code_optimization"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.215110136"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/code_optimization"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<mapAttribute key="org.eclipse.debug.core.preferred_launchers">
+<mapEntry key="[debug]" value="com.crt.dsfdebug.dsf.MCULaunch"/>
+</mapAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="com.crt.dsfdebug.dsf.override.CRTProcessFactory"/>
+<booleanAttribute key="redlink.enable.rangestepping" value="true"/>
+<stringAttribute key="run" value="cont"/>
+<booleanAttribute key="vector.catch" value="false"/>
+</launchConfiguration>
diff --git a/TP2_bpsk_demod/src/config_LPC1769.h b/TP2_bpsk_demod/src/config_LPC1769.h
new file mode 100644
index 0000000000000000000000000000000000000000..dd2af594df51d4946ecafa2f817f86c06cfd125d
--- /dev/null
+++ b/TP2_bpsk_demod/src/config_LPC1769.h
@@ -0,0 +1,186 @@
+/*
+===============================================================================
+ Name : config_LPC1769.h
+ Author : D. Bechevet, F. Vannel, A. Lescourt
+ Copyright : HES-SO hepia
+ Year : 2013-2014
+===============================================================================
+*/
+
+#ifndef CONFIG_LPC1769_H_
+#define CONFIG_LPC1769_H_
+
+typedef unsigned char BOOL;
+typedef unsigned char UINT8;
+typedef signed char INT8;
+typedef unsigned short UINT16;
+typedef signed short INT16;
+typedef unsigned long UINT32;
+typedef signed long INT32;
+
+#ifndef TRUE
+ #define TRUE 0x1
+#endif
+#ifndef FALSE
+ #define FALSE 0x0
+#endif
+
+// GPIO
+#define FIO0DIR (*((volatile unsigned long *) 0x2009C000))
+#define FIO0MASK (*((volatile unsigned long *) 0x2009C010))
+#define FIO0PIN (*((volatile unsigned long *) 0x2009C014))
+#define FIO0SET (*((volatile unsigned long *) 0x2009C018))
+#define FIO0CLR (*((volatile unsigned long *) 0x2009C01C))
+#define FIO0PIN2 (*((volatile unsigned long *) 0x2009C016))
+
+#define FIO1DIR (*((volatile unsigned long *) 0x2009C020))
+#define FIO1MASK (*((volatile unsigned long *) 0x2009C030))
+#define FIO1PIN (*((volatile unsigned long *) 0x2009C034))
+#define FIO1SET (*((volatile unsigned long *) 0x2009C038))
+#define FIO1CLR (*((volatile unsigned long *) 0x2009C03C))
+
+#define FIO2DIR (*((volatile unsigned long *) 0x2009C040))
+#define FIO2MASK (*((volatile unsigned long *) 0x2009C050))
+#define FIO2PIN (*((volatile unsigned long *) 0x2009C054))
+#define FIO2SET (*((volatile unsigned long *) 0x2009C058))
+#define FIO2CLR (*((volatile unsigned long *) 0x2009C05C))
+#define FIO2PIN1 (*((volatile unsigned long *) 0x2009C055))
+
+#define FIO3DIR (*((volatile unsigned long *) 0x2009C060))
+#define FIO3MASK (*((volatile unsigned long *) 0x2009C070))
+#define FIO3PIN (*((volatile unsigned long *) 0x2009C074))
+#define FIO3SET (*((volatile unsigned long *) 0x2009C078))
+#define FIO3CLR (*((volatile unsigned long *) 0x2009C07C))
+
+#define FIO4DIR (*((volatile unsigned long *) 0x2009C080))
+#define FIO4MASK (*((volatile unsigned long *) 0x2009C090))
+#define FIO4PIN (*((volatile unsigned long *) 0x2009C094))
+#define FIO4SET (*((volatile unsigned long *) 0x2009C098))
+#define FIO4CLR (*((volatile unsigned long *) 0x2009C09C))
+
+// GPIO Interrupt register map
+#define IO0IntEnR (*((volatile unsigned long *) 0x40028090))
+#define IO0IntEnF (*((volatile unsigned long *) 0x40028094))
+#define IO0IntStatR (*((volatile unsigned long *) 0x40028084))
+#define IO0IntStatF (*((volatile unsigned long *) 0x40028088))
+#define IO0IntClr (*((volatile unsigned long *) 0x4002808C))
+
+#define IO2IntEnR (*((volatile unsigned long *) 0x400280B0))
+#define IO2IntEnF (*((volatile unsigned long *) 0x400280B4))
+#define IO2IntStatR (*((volatile unsigned long *) 0x400280A4))
+#define IO2IntStatF (*((volatile unsigned long *) 0x400280A8))
+#define IO2IntClr (*((volatile unsigned long *) 0x400280AC))
+
+#define IOIntStatus (*((volatile unsigned long *) 0x40028080))
+
+//TIMER
+#define T0IR (*((volatile unsigned long *) 0x40004000))
+#define T0TCR (*((volatile unsigned long *) 0x40004004))
+#define T0TC (*((volatile unsigned long *) 0x40004008))
+#define T0PR (*((volatile unsigned long *) 0x4000400C))
+#define T0PC (*((volatile unsigned long *) 0x40004010))
+#define T0MCR (*((volatile unsigned long *) 0x40004014))
+#define T0MR0 (*((volatile unsigned long *) 0x40004018))
+#define T0MR1 (*((volatile unsigned long *) 0x4000401C))
+#define T0MR2 (*((volatile unsigned long *) 0x40004020))
+#define T0MR3 (*((volatile unsigned long *) 0x40004024))
+#define T0CCR (*((volatile unsigned long *) 0x40004028))
+#define T0CR0 (*((volatile unsigned long *) 0x4000402C))
+#define T0CR1 (*((volatile unsigned long *) 0x40004030))
+#define T0EMR (*((volatile unsigned long *) 0x4000403C))
+#define T0CTCR (*((volatile unsigned long *) 0x40004070))
+
+#define T1IR (*((volatile unsigned long *) 0x40008000))
+#define T1TCR (*((volatile unsigned long *) 0x40008004))
+#define T1TC (*((volatile unsigned long *) 0x40008008))
+#define T1PR (*((volatile unsigned long *) 0x4000800C))
+#define T1PC (*((volatile unsigned long *) 0x40008010))
+#define T1MCR (*((volatile unsigned long *) 0x40008014))
+#define T1MR0 (*((volatile unsigned long *) 0x40008018))
+#define T1MR1 (*((volatile unsigned long *) 0x4000801C))
+#define T1MR2 (*((volatile unsigned long *) 0x40008020))
+#define T1MR3 (*((volatile unsigned long *) 0x40008024))
+#define T1CCR (*((volatile unsigned long *) 0x40008028))
+#define T1CR0 (*((volatile unsigned long *) 0x4000802C))
+#define T1CR1 (*((volatile unsigned long *) 0x40008030))
+#define T1EMR (*((volatile unsigned long *) 0x4000803C))
+#define T1CTCR (*((volatile unsigned long *) 0x40008070))
+
+#define T2IR (*((volatile unsigned long *) 0x40090000))
+#define T2TCR (*((volatile unsigned long *) 0x40090004))
+#define T2TC (*((volatile unsigned long *) 0x40090008))
+#define T2PR (*((volatile unsigned long *) 0x4009000C))
+#define T2PC (*((volatile unsigned long *) 0x40090010))
+#define T2MCR (*((volatile unsigned long *) 0x40090014))
+#define T2MR0 (*((volatile unsigned long *) 0x40090018))
+#define T2MR1 (*((volatile unsigned long *) 0x4009001C))
+#define T2MR2 (*((volatile unsigned long *) 0x40090020))
+#define T2MR3 (*((volatile unsigned long *) 0x40090024))
+#define T2CCR (*((volatile unsigned long *) 0x40090028))
+#define T2CR0 (*((volatile unsigned long *) 0x4009002C))
+#define T2CR1 (*((volatile unsigned long *) 0x40090030))
+#define T2EMR (*((volatile unsigned long *) 0x4009003C))
+#define T2CTCR (*((volatile unsigned long *) 0x40090070))
+
+#define T3IR (*((volatile unsigned long *) 0x40094000))
+#define T3TCR (*((volatile unsigned long *) 0x40094004))
+#define T3TC (*((volatile unsigned long *) 0x40094008))
+#define T3PR (*((volatile unsigned long *) 0x4009400C))
+#define T3PC (*((volatile unsigned long *) 0x40094010))
+#define T3MCR (*((volatile unsigned long *) 0x40094014))
+#define T3MR0 (*((volatile unsigned long *) 0x40094018))
+#define T3MR1 (*((volatile unsigned long *) 0x4009401C))
+#define T3MR2 (*((volatile unsigned long *) 0x40094020))
+#define T3MR3 (*((volatile unsigned long *) 0x40094024))
+#define T3CCR (*((volatile unsigned long *) 0x40094028))
+#define T3CR0 (*((volatile unsigned long *) 0x4009402C))
+#define T3CR1 (*((volatile unsigned long *) 0x40094030))
+#define T3EMR (*((volatile unsigned long *) 0x4009403C))
+#define T3CTCR (*((volatile unsigned long *) 0x40094070))
+
+//NVIC
+#define ISER0 (*((volatile unsigned long *) 0xE000E100))
+#define ICER0 (*((volatile unsigned long *) 0xE000E180))
+#define ISPR0 (*((volatile unsigned long *) 0xE000E200))
+#define ICPR0 (*((volatile unsigned long *) 0xE000E280))
+#define IABR0 (*((volatile unsigned long *) 0xE000E300))
+
+#define ISER1 (*((volatile unsigned long *) 0xE000E104))
+#define ICER1 (*((volatile unsigned long *) 0xE000E184))
+#define ISPR1 (*((volatile unsigned long *) 0xE000E204))
+#define ICPR1 (*((volatile unsigned long *) 0xE000E284))
+#define IABR1 (*((volatile unsigned long *) 0xE000E304))
+
+#define IPR0 (*((volatile unsigned long *) 0xE000E400))
+#define IPR1 (*((volatile unsigned long *) 0xE000E404))
+#define IPR2 (*((volatile unsigned long *) 0xE000E408))
+#define IPR3 (*((volatile unsigned long *) 0xE000E40C))
+#define IPR4 (*((volatile unsigned long *) 0xE000E410))
+#define IPR5 (*((volatile unsigned long *) 0xE000E414))
+#define IPR6 (*((volatile unsigned long *) 0xE000E418))
+#define IPR7 (*((volatile unsigned long *) 0xE000E41C))
+#define IPR8 (*((volatile unsigned long *) 0xE000E420))
+
+#define STIR (*((volatile unsigned long *) 0xE000EF00))
+
+#define CLKSRCSEL (*((volatile unsigned long *) 0x400FC10C))
+#define SCS (*((volatile unsigned long *) 0x400FC1A0))
+
+#define PCLKSEL0 (*((volatile unsigned long *) 0x400FC1A8))
+
+#define PCONP (*((volatile unsigned long *) 0x400FC0C4))
+
+#define DMACConfig (*((volatile unsigned long *) 0x50004030))
+#define DMACC0SrcAddr (*((volatile unsigned long *) 0x50004100))
+#define DMACC0DestAddr (*((volatile unsigned long *) 0x50004104))
+#define DMACC0Control (*((volatile unsigned long *) 0x5000410C))
+#define DMACC0Config (*((volatile unsigned long *) 0x50004110))
+#define DMAREQSEL (*((volatile unsigned long *) 0x400FC1C4))
+
+
+
+
+
+void init(void);
+
+#endif /* CONFIG_LPC1769_H_ */
diff --git a/TP2_bpsk_demod/src/cr_startup_lpc175x_6x.c b/TP2_bpsk_demod/src/cr_startup_lpc175x_6x.c
new file mode 100644
index 0000000000000000000000000000000000000000..8aaeb4742568d1b138f5263a2995f740b7e9c4cf
--- /dev/null
+++ b/TP2_bpsk_demod/src/cr_startup_lpc175x_6x.c
@@ -0,0 +1,378 @@
+//*****************************************************************************
+// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
+//
+// Version : 150706
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2014-2015
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products. This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+// Declaration of external SystemInit function
+extern void SystemInit(void);
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
+#if defined (__USE_LPCOPEN)
+void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
+#else
+void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
+#endif
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+//
+// External declaration for LPC MCU vector table checksum from Linker Script
+//
+//*****************************************************************************
+WEAK extern void __valid_user_code_checksum();
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((used,section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM3
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ __valid_user_code_checksum, // LPC MCU Checksum
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC17
+ WDT_IRQHandler, // 16, 0x40 - WDT
+ TIMER0_IRQHandler, // 17, 0x44 - TIMER0
+ TIMER1_IRQHandler, // 18, 0x48 - TIMER1
+ TIMER2_IRQHandler, // 19, 0x4c - TIMER2
+ TIMER3_IRQHandler, // 20, 0x50 - TIMER3
+ UART0_IRQHandler, // 21, 0x54 - UART0
+ UART1_IRQHandler, // 22, 0x58 - UART1
+ UART2_IRQHandler, // 23, 0x5c - UART2
+ UART3_IRQHandler, // 24, 0x60 - UART3
+ PWM1_IRQHandler, // 25, 0x64 - PWM1
+ I2C0_IRQHandler, // 26, 0x68 - I2C0
+ I2C1_IRQHandler, // 27, 0x6c - I2C1
+ I2C2_IRQHandler, // 28, 0x70 - I2C2
+ SPI_IRQHandler, // 29, 0x74 - SPI
+ SSP0_IRQHandler, // 30, 0x78 - SSP0
+ SSP1_IRQHandler, // 31, 0x7c - SSP1
+ PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
+ RTC_IRQHandler, // 33, 0x84 - RTC
+ EINT0_IRQHandler, // 34, 0x88 - EINT0
+ EINT1_IRQHandler, // 35, 0x8c - EINT1
+ EINT2_IRQHandler, // 36, 0x90 - EINT2
+ EINT3_IRQHandler, // 37, 0x94 - EINT3
+ ADC_IRQHandler, // 38, 0x98 - ADC
+ BOD_IRQHandler, // 39, 0x9c - BOD
+ USB_IRQHandler, // 40, 0xA0 - USB
+ CAN_IRQHandler, // 41, 0xa4 - CAN
+ DMA_IRQHandler, // 42, 0xa8 - GP DMA
+ I2S_IRQHandler, // 43, 0xac - I2S
+#if defined (__USE_LPCOPEN)
+ ETH_IRQHandler, // 44, 0xb0 - Ethernet
+#else
+ ENET_IRQHandler, // 44, 0xb0 - Ethernet
+#endif
+ RIT_IRQHandler, // 45, 0xb4 - RITINT
+ MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
+ QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
+ PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
+ USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
+ CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
+};
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void
+ResetISR(void) {
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+ SystemInit();
+#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{ while(1) {}
+}
diff --git a/TP2_bpsk_demod/src/main.c b/TP2_bpsk_demod/src/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..699972773d2d197253c2138f3548c18ee628cd7f
--- /dev/null
+++ b/TP2_bpsk_demod/src/main.c
@@ -0,0 +1,85 @@
+/**
+ * Name : main.c
+ * Date : 2019
+ * Description : Code to be optimised
+ */
+
+#include <cr_section_macros.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <math.h>
+#include "config_LPC1769.h"
+
+uint32_t sum_asm(int8_t *, int len);
+extern int8_t sig[2*1920]; // signal sample
+
+void ex1()
+{
+ int i;
+ double sum;
+ uint32_t start, calc_duration_us[4]={0,0,0,0};
+ int32_t sum_fx=0, sum_fx_asm;
+
+ T0TCR=1; // start timer 0 for time measurements
+
+ start=T0TC;
+ sum=0;
+ for (i=0; i<2*1920; i++) // calculates the sum of squares / 4
+ {
+ sum+=(float)sig[i]*(float)sig[i]/4.;
+ }
+ calc_duration_us[0]=(T0TC-start)/25;
+
+ start=T0TC;
+ // algo improved (without changing variable types), result in sum
+ calc_duration_us[1]=(T0TC-start)/25;
+
+ start=T0TC;
+ // algo improved using integers, result in sum_fx
+ calc_duration_us[2]=(T0TC-start)/25;
+
+ start=T0TC;
+ // algo improved using integers and assembly, result in sum_fx_asm
+ calc_duration_us[3]=(T0TC-start)/25;
+
+ printf("EX1 results: %.0f, %ld, %ld\n", sum, sum_fx, sum_fx_asm);
+
+ for (i=0; i<4; i++)
+ printf("Duration: %d [us]\n", calc_duration_us[i]);
+}
+
+#define PI 3.14159265359
+
+void ex2()
+{
+ int i;
+ uint32_t sum_fx=0, start, calc_duration_us[2]={0,0};
+ int32_t cos_table[64];
+ double sum=0;
+
+ start=T0TC;
+ for (i=0; i<2*1920; i++) // calculates the sum of the signal elements / 4
+ {
+ sum+=(double)sig[i]*cos(2*PI*(float)i/64.);
+ }
+ calc_duration_us[0]=(T0TC-start)/25;
+
+ // intialisation of cos_table (out of time calculation loop)
+ start=T0TC;
+ // optimised version with integers using cos_table[]
+ calc_duration_us[1]=(T0TC-start)/25;
+
+ // note: 1% of error is admitted on integer version
+ printf("EX2 results: %.0f, %ld\n", sum, sum_fx);
+ printf("Duration: %d, %d [us]\n", calc_duration_us[0], calc_duration_us[1]);
+}
+
+
+int main(void)
+{
+ ex1();
+ ex2();
+
+ return 1;
+}
diff --git a/TP2_bpsk_demod/src/processing.s b/TP2_bpsk_demod/src/processing.s
new file mode 100644
index 0000000000000000000000000000000000000000..4f5f76547a6d09dd56d24b7c78b8ca5463e6e761
--- /dev/null
+++ b/TP2_bpsk_demod/src/processing.s
@@ -0,0 +1,24 @@
+#ifdef __USE_CMSIS
+#include "LPC17xx.h"
+#endif
+
+.section .text,"ax"
+.cpu cortex-m3
+.thumb
+.syntax unified
+
+.global sum_asm
+
+/*****************************************************
+ * function : sum elements of a 8 bits vector
+ * R0: A pointer on vector to sum
+ * R1: vector size
+ * return value : sum(A)
+ *****************************************************/
+.thumb_func
+sum_asm:
+
+ bx lr
+
+
+.ltorg
diff --git a/TP2_bpsk_demod/src/sig.c b/TP2_bpsk_demod/src/sig.c
new file mode 100644
index 0000000000000000000000000000000000000000..cce4a60c8e541754d39d2b1809a0151c2bfa422c
--- /dev/null
+++ b/TP2_bpsk_demod/src/sig.c
@@ -0,0 +1,390 @@
+#include <stdint.h>
+
+// signal sample
+
+const int8_t sig[2*1920]=
+{8,11,-5,-20,-12,14,37,-28,22,
+-9,-64,-35,-22,-53,-3,-13,-44,6,32,
+-26,13,1,-1,-29,-14,3,-10,1,32,
+-35,-20,-9,22,22,24,13,4,-62,-15,
+21,-24,-35,2,9,54,9,19,-19,9,
+33,42,-23,-21,28,20,19,-27,22,-23,
+-17,3,7,-11,-62,2,34,-11,-40,-26,
+-6,-22,37,17,-31,-11,0,-5,-16,-38,
+4,-1,40,4,-5,-37,7,4,58,14,
+-12,-53,-16,63,-56,-10,27,12,19,40,
+9,-38,6,-32,-14,-7,2,28,33,42,
+-47,-4,23,-25,-46,-46,-23,43,3,22,
+-6,-10,14,29,-11,-5,33,39,38,11,
+-15,-18,-32,-32,53,-51,-53,-18,46,-13,
+8,-35,-26,3,37,-5,17,30,-11,1,
+50,-30,-35,28,26,36,-44,-28,7,31,
+8,28,-21,-11,3,-11,-65,10,13,28,
+0,8,-39,-46,45,28,-16,-24,-13,-39,
+39,13,62,11,-19,-18,-55,18,65,69,
+-36,5,-3,14,-5,-18,-40,44,12,55,
+-15,-63,-27,-20,-15,-20,14,-28,-29,7,
+74,33,-19,3,-16,-14,0,31,20,-14,
+28,-19,-34,-3,-9,38,45,40,32,-20,
+-21,-1,65,-14,-28,-29,35,-6,16,17,
+9,16,3,25,19,-22,-42,18,-15,-6,
+38,38,15,17,16,17,1,6,-15,-7,
+37,-6,-2,-4,35,-21,19,17,27,5,
+10,19,17,-12,-59,-40,-12,34,-1,-2,
+2,-2,23,15,0,-16,-19,-25,-23,8,
+-39,-52,7,15,-2,54,4,-28,-69,-32,
+-26,-29,61,-62,-74,26,79,29,0,18,
+-7,-51,-3,-12,-6,14,-30,25,-36,2,
+-18,2,38,19,49,6,-25,-17,34,25,
+-21,-3,-29,54,4,-6,16,48,-17,49,
+-56,-5,-5,-18,-14,-10,9,-4,-22,-18,
+-7,10,24,-66,-56,-19,-21,-37,4,16,
+12,-17,22,-46,-6,-21,34,73,-43,-2,
+-49,-6,-33,10,5,-49,-9,-15,47,31,
+-2,-4,-20,-11,-5,-17,-13,12,64,-18,
+10,-16,16,-25,29,-39,0,-65,0,-20,
+33,1,8,-27,-38,6,-40,23,-31,-14,
+-9,4,-13,-67,-40,13,-15,-44,-14,15,
+39,39,71,-27,-20,5,-26,36,1,36,
+-25,-2,10,-3,16,-12,-12,-3,-70,-22,
+11,-22,-28,-3,113,5,-28,-9,-45,10,
+10,13,24,24,-37,36,-32,22,-8,3,
+14,13,13,-15,-22,39,24,-3,-31,12,
+19,-5,18,12,9,-44,-56,15,42,10,
+-2,20,8,-43,-28,12,-5,-27,16,-23,
+-15,-13,30,47,-13,22,-6,-36,-31,35,
+19,21,-15,-20,-5,-29,10,-20,21,-1,
+4,-53,-5,-34,31,-24,-6,-29,-2,-9,
+-18,58,47,-1,-3,-23,6,-10,-23,-1,
+52,-13,-27,24,-9,28,23,-60,-21,-23,
+-22,-35,22,21,-43,-4,35,52,4,-6,
+-20,34,23,2,-48,23,26,-7,-47,14,
+-47,16,48,28,-5,16,25,25,7,20,
+-34,-9,-10,33,-21,-21,-9,-30,-4,5,
+12,53,13,-19,-19,55,0,20,-63,-32,
+-52,35,-7,6,13,-47,-3,22,18,9,
+-12,-30,-10,-3,-14,-22,-13,17,-19,-67,
+-14,-11,26,45,-4,-9,-16,-18,-28,10,
+0,31,2,23,2,-37,-35,14,-42,24,
+70,24,32,-34,-13,-42,-33,3,5,25,
+-62,-6,36,-4,58,3,-14,-4,-1,50,
+31,-2,-28,-4,-17,-56,-20,-5,-30,30,
+25,-37,-58,-36,10,-23,-31,-22,22,10,
+14,4,8,-10,-43,-36,39,-3,2,12,
+40,-27,-48,-5,63,28,-5,-31,-33,-40,
+-1,47,43,-31,-54,14,64,-24,43,14,
+1,-40,22,25,-4,5,40,-14,-70,-44,
+-22,24,64,39,58,-11,12,-40,21,-20,
+44,19,50,12,28,15,-26,-54,-33,-14,
+11,34,29,-34,-12,4,45,16,12,-21,
+15,-13,23,-3,-50,-11,30,-19,-41,-29,
+35,10,1,-38,16,-26,-13,45,58,-20,
+-36,-3,51,38,0,6,8,-28,9,-3,
+17,-53,-23,-26,33,28,29,-18,-4,-4,
+-33,6,-14,-42,-1,-50,26,1,-33,-24,
+-23,-23,-6,21,0,13,9,-30,-20,-62,
+-23,2,-9,81,-12,-49,-88,-10,45,19,
+-51,-70,-9,-48,24,10,11,-22,-18,-5,
+29,-88,-12,62,64,-1,-17,-1,48,67,
+-24,24,-61,-51,-14,40,11,29,-28,-30,
+1,-30,28,15,-9,-7,3,0,-19,-28,
+63,19,-82,-66,-16,-37,-17,32,23,2,
+-31,31,-38,10,14,4,8,22,-14,4,
+-19,6,5,34,-13,-6,31,-8,-20,-17,
+-14,-42,15,52,-20,-50,-10,16,-13,-6,
+25,28,-16,5,1,-13,-4,18,26,-30,
+-33,-54,34,45,-12,7,-12,-10,-50,11,
+32,-32,-13,21,-19,-7,12,14,2,16,
+20,26,-35,16,87,82,-16,35,1,-16,
+-9,5,20,-8,8,-26,-34,60,2,-9,
+19,-6,15,-17,14,28,8,26,-57,-25,
+18,8,6,-35,4,-10,-45,9,-8,1,
+23,-6,15,19,-19,-28,-41,8,-3,38,
+68,5,52,-14,-16,22,-22,-11,-22,-17,
+17,-2,13,41,-11,10,29,-42,7,-19,
+26,57,-10,-69,-24,0,-11,7,-11,-13,
+-45,-4,25,33,7,-32,10,29,15,6,
+45,31,-19,-28,-32,8,31,15,-54,6,
+56,40,3,-30,-24,-41,10,5,-4,22,
+-3,0,14,33,26,-11,-28,-9,49,2,
+-35,-2,52,-14,-36,-7,-9,23,23,4,
+20,11,-13,-19,53,5,-6,34,-15,-31,
+-40,-16,-6,8,34,-5,-10,10,35,-26,
+21,8,-19,-30,-19,60,8,5,-4,0,
+26,-24,-16,-3,8,29,-11,-10,-53,18,
+34,10,-29,34,38,34,-14,66,28,-1,
+-22,-17,-10,-16,-16,5,22,12,-21,-60,
+-63,-7,-7,-60,-9,6,102,36,6,-8,
+-56,-5,-23,13,40,38,-23,-8,72,11,
+14,-6,25,-16,9,-14,-7,18,16,38,
+-42,-64,4,17,-8,6,22,-12,-15,20,
+35,-13,-29,-24,38,-53,11,-4,-60,-12,
+27,29,45,45,48,-29,-27,17,44,-66,
+-15,-77,-33,10,20,-17,13,-5,2,11,
+-5,-24,66,52,15,-2,-49,-7,-25,0,
+9,5,-26,17,-3,27,2,8,10,-30,
+-2,-61,-21,-3,30,2,-49,-23,-19,-5,
+31,-3,-43,-8,10,51,18,23,36,-2,
+-30,-59,-19,-10,-45,19,8,-1,-1,-33,
+-23,15,7,26,38,4,66,51,-29,-53,
+-12,11,9,0,10,-13,-14,-48,14,6,
+22,29,38,-65,-18,6,-10,-8,-8,10,
+16,20,-19,-21,46,19,-11,-66,-8,20,
+5,-7,-19,-31,49,-31,10,34,32,8,
+-7,-13,24,-43,-43,19,34,-6,-52,-14,
+6,20,24,18,-11,-15,-25,-10,10,19,
+-5,-16,22,6,5,-15,12,-34,-8,11,
+-21,-52,-6,11,4,-11,26,19,-24,17,
+2,6,-14,4,15,-17,-21,-60,-43,42,
+14,20,26,2,-11,12,37,7,-56,18,
+-26,29,-4,2,0,23,5,14,-2,2,
+-14,-2,45,-27,-22,-23,43,32,25,22,
+-77,-2,36,-6,-5,8,-10,20,-3,-51,
+-25,12,30,-21,19,-48,-12,-23,43,8,
+-37,-43,-37,-20,8,-4,58,-20,-22,1,
+1,15,-48,7,11,41,-13,21,54,23,
+34,-2,35,-50,-2,54,38,-21,-49,24,
+44,59,-28,-25,-45,20,-22,17,-6,6,
+33,-18,-8,-44,-2,42,9,41,-16,-13,
+-68,25,44,11,-28,-63,-33,-10,-6,28,
+-3,24,-16,12,28,27,47,-7,-56,10,
+11,-10,-19,-20,-3,5,7,57,36,-26,
+-25,6,-7,29,-32,-25,-2,-6,-23,-10,
+-1,-20,45,22,-32,-18,55,77,19,-28,
+13,-32,-28,50,11,10,-34,6,3,29,
+26,17,-15,-4,-24,10,-18,-51,-2,-4,
+-44,16,20,-40,-28,-32,34,25,5,67,
+-40,24,-37,34,-20,39,15,-5,-32,-61,
+29,11,11,46,-5,7,6,49,-6,-1,
+-4,-72,-17,27,-4,6,21,-40,23,5,
+4,-11,3,-34,42,13,50,46,0,13,
+-14,-39,5,35,-23,-60,-29,-6,10,-10,
+-3,-10,8,18,22,13,11,27,37,2,
+-46,-14,-8,49,54,-15,-57,0,22,-17,
+16,-37,8,-15,28,14,26,-8,20,4,
+-37,5,37,-18,-24,34,76,26,-28,-4,
+-30,-15,6,32,34,46,-36,2,-14,33,
+8,15,40,22,26,-28,19,42,59,-31,
+-36,-1,19,2,-3,35,-15,-17,7,-7,
+0,-15,49,-42,14,9,-15,30,-2,-8,
+35,-8,-5,-41,6,-5,20,2,-54,-22,
+7,15,16,-23,-31,-33,2,-17,64,20,
+-1,-4,-44,-55,-4,59,18,3,1,0,
+-21,34,4,2,-11,15,-14,18,18,23,
+-2,21,0,15,-20,37,25,-17,13,9,
+53,-8,-68,-69,-18,34,7,71,39,-16,
+-11,14,53,-4,-8,-16,19,26,15,-14,
+-58,-4,24,-60,-70,-7,34,78,21,-44,
+-33,-18,-46,-2,7,7,11,31,57,16,
+48,-29,9,-4,-44,48,15,1,-3,-40,
+56,41,14,-10,-27,-15,-75,85,-28,-15,
+-21,8,-28,5,-23,11,10,19,7,-29,
+2,-19,61,22,-59,-56,-11,29,10,-12,
+33,-9,-3,-24,23,-4,-35,26,31,16,
+36,-45,-44,9,-39,0,14,30,17,11,
+-11,-15,56,-39,-15,-33,-7,15,-38,17,
+-26,-20,0,-31,-23,-2,20,36,21,10,
+50,-20,-27,27,51,17,-52,-14,53,34,
+-13,2,-1,18,-14,-10,-42,6,13,-19,
+-30,-29,0,6,-24,-15,26,-9,42,-46,
+0,-22,-26,-20,52,-13,21,19,22,-2,
+-1,2,-35,5,2,37,-39,-11,14,-34,
+-53,-86,-9,-26,14,14,27,-16,-33,-48,
+3,18,33,-40,-39,-5,-37,-38,1,-8,
+-26,-14,-52,38,41,17,12,-57,17,-5,
+6,31,5,-9,-3,29,3,16,-40,-24,
+38,2,74,1,11,14,64,0,-45,-52,
+16,-44,32,36,47,11,-20,42,6,-11,
+37,-19,-6,-11,13,12,-51,-16,10,56,
+51,62,-14,-15,9,16,8,22,-39,-25,
+38,-19,5,-36,51,14,6,-28,-20,-10,
+45,3,-20,-18,17,-38,9,1,-4,14,
+-49,-38,57,6,-3,23,-24,18,-32,47,
+-17,6,-25,-5,-26,-9,-21,-17,-61,-9,
+7,43,-24,-12,-24,-16,-3,22,14,-23,
+13,22,-2,28,20,29,0,28,8,1,
+59,12,23,21,-11,-55,-12,15,47,21,
+43,-55,34,-11,45,9,-55,-5,4,11,
+-38,-20,45,38,-1,-19,-26,-29,41,-14,
+-2,-54,-33,18,54,21,-5,9,4,-24,
+20,23,20,34,21,-35,-43,-31,40,29,
+27,17,10,-21,8,-6,42,-6,-15,-66,
+-44,-7,-5,0,17,8,44,-9,4,20,
+27,-6,-14,28,60,9,-48,-46,6,4,
+30,33,-7,-13,-35,25,-25,-13,-35,-35,
+10,-16,-10,8,-12,-11,5,-4,-67,0,
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