From 785a840278781966e2a9737ff51997c629e52a19 Mon Sep 17 00:00:00 2001
From: iliya <iliya.saroukha@hes-so.ch>
Date: Wed, 15 Nov 2023 14:13:21 +0100
Subject: [PATCH] feat: init labo ex dma
---
CMSISv2p00_LPC17xx/.gitignore | 1 +
.../.settings/language.settings.xml | 6 +-
.../Debug/libCMSISv2p00_LPC17xx.a | Bin 82860 -> 90608 bytes
CMSISv2p00_LPC17xx/Debug/makefile | 110 +-
CMSISv2p00_LPC17xx/Debug/sources.mk | 32 +-
CMSISv2p00_LPC17xx/Debug/src/core_cm3.d | 2 +-
CMSISv2p00_LPC17xx/Debug/src/core_cm3.o | Bin 27204 -> 30832 bytes
CMSISv2p00_LPC17xx/Debug/src/subdir.mk | 53 +-
CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d | 21 +-
CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o | Bin 55324 -> 59444 bytes
.../.settings/language.settings.xml | 4 +-
labo4.1_DMA_new/.cproject | 432 ++++++
labo4.1_DMA_new/.project | 27 +
.../.settings/language.settings.xml | 25 +
.../org.eclipse.core.resources.prefs | 2 +
labo4.1_DMA_new/Debug/labo4.1_DMA.map | 467 +++++++
labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf | Bin 0 -> 127100 bytes
labo4.1_DMA_new/Debug/labo4.1_DMA_new.map | 458 ++++++
labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld | 203 +++
.../Debug/labo4_1_DMA_Debug_library.ld | 16 +
.../Debug/labo4_1_DMA_Debug_memory.ld | 32 +
.../Debug/labo4_1_DMA_new_Debug.ld | 200 +++
.../Debug/labo4_1_DMA_new_Debug_library.ld | 15 +
.../Debug/labo4_1_DMA_new_Debug_memory.ld | 31 +
labo4.1_DMA_new/Debug/labo6_DMA.map | 440 ++++++
labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld | 158 +++
.../Debug/labo6_DMA_Debug_library.ld | 14 +
.../Debug/labo6_DMA_Debug_memory.ld | 31 +
labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld | 163 +++
labo4.1_DMA_new/Debug/labo7_DMA.axf | Bin 0 -> 192267 bytes
labo4.1_DMA_new/Debug/labo7_DMA.map | 404 ++++++
labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld | 155 +++
labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld | 14 +
labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld | 25 +
labo4.1_DMA_new/Debug/labo_DMA.axf | Bin 0 -> 192043 bytes
labo4.1_DMA_new/Debug/labo_DMA.map | 403 ++++++
labo4.1_DMA_new/Debug/labo_DMA_Debug.ld | 154 ++
labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld | 13 +
labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld | 21 +
labo4.1_DMA_new/Debug/makefile | 60 +
labo4.1_DMA_new/Debug/objects.mk | 8 +
labo4.1_DMA_new/Debug/sources.mk | 18 +
labo4.1_DMA_new/Debug/src/config_LPC1769.su | 1 +
.../Debug/src/cr_startup_lpc176x.d | 1 +
.../Debug/src/cr_startup_lpc176x.o | Bin 0 -> 26828 bytes
.../Debug/src/cr_startup_lpc176x.su | 13 +
labo4.1_DMA_new/Debug/src/crp.d | 1 +
labo4.1_DMA_new/Debug/src/crp.o | Bin 0 -> 20676 bytes
labo4.1_DMA_new/Debug/src/crp.su | 0
labo4.1_DMA_new/Debug/src/dma.d | 13 +
labo4.1_DMA_new/Debug/src/dma.o | Bin 0 -> 61376 bytes
labo4.1_DMA_new/Debug/src/dma.su | 3 +
labo4.1_DMA_new/Debug/src/dmatest.d | 12 +
labo4.1_DMA_new/Debug/src/dmatest.o | Bin 0 -> 59640 bytes
labo4.1_DMA_new/Debug/src/dmatest.su | 4 +
labo4.1_DMA_new/Debug/src/subdir.mk | 47 +
.../labo4.1_DMA_new LinkServer Debug.launch | 99 ++
labo4.1_DMA_new/labo6_DMA Debug.launch | 22 +
labo4.1_DMA_new/labo6_DMA Release.launch | 18 +
labo4.1_DMA_new/src/cr_startup_lpc176x.c | 421 ++++++
labo4.1_DMA_new/src/crp.c | 38 +
labo4.1_DMA_new/src/dma.c | 50 +
labo4.1_DMA_new/src/dma.h | 36 +
labo4.1_DMA_new/src/dmatest.c | 80 ++
.../CMSISv2p00_LPC17xx/.cproject | 510 +++++++
.../CMSISv2p00_LPC17xx/.project | 81 ++
.../.settings/language.settings.xml | 25 +
.../Debug/libCMSISv2p00_LPC17xx.a | Bin 0 -> 90076 bytes
.../CMSISv2p00_LPC17xx/Debug/makefile | 60 +
.../CMSISv2p00_LPC17xx/Debug/objects.mk | 8 +
.../CMSISv2p00_LPC17xx/Debug/sources.mk | 18 +
.../CMSISv2p00_LPC17xx/Debug/src/core_cm3.d | 1 +
.../CMSISv2p00_LPC17xx/Debug/src/core_cm3.o | Bin 0 -> 30504 bytes
.../CMSISv2p00_LPC17xx/Debug/src/core_cm3.su | 0
.../CMSISv2p00_LPC17xx/Debug/src/subdir.mk | 34 +
.../Debug/src/system_LPC17xx.d | 8 +
.../Debug/src/system_LPC17xx.o | Bin 0 -> 59240 bytes
.../Debug/src/system_LPC17xx.su | 2 +
.../docs/CMSIS END USER LICENCE AGREEMENT.pdf | Bin 0 -> 51511 bytes
.../CMSISv2p00_LPC17xx/docs/cmsis_readme.txt | 44 +
.../CMSISv2p00_LPC17xx/history.txt | 12 +
.../CMSISv2p00_LPC17xx/inc/LPC17xx.h | 1035 ++++++++++++++
.../CMSISv2p00_LPC17xx/inc/core_cm3.h | 1236 +++++++++++++++++
.../CMSISv2p00_LPC17xx/inc/core_cmFunc.h | 844 +++++++++++
.../CMSISv2p00_LPC17xx/inc/core_cmInstr.h | 775 +++++++++++
.../CMSISv2p00_LPC17xx/inc/system_LPC17xx.h | 64 +
.../CMSISv2p00_LPC17xx/src/core_cm3.c | 339 +++++
.../CMSISv2p00_LPC17xx/src/system_LPC17xx.c | 532 +++++++
.../labo4.1_DMA_new/.cproject | 432 ++++++
.../labo4.1_DMA_new/.project | 27 +
.../.settings/language.settings.xml | 25 +
.../labo4.1_DMA_new/Debug/labo4.1_DMA.map | 467 +++++++
.../labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf | Bin 0 -> 124768 bytes
.../labo4.1_DMA_new/Debug/labo4.1_DMA_new.map | 450 ++++++
.../Debug/labo4_1_DMA_Debug.ld | 203 +++
.../Debug/labo4_1_DMA_Debug_library.ld | 16 +
.../Debug/labo4_1_DMA_Debug_memory.ld | 32 +
.../Debug/labo4_1_DMA_new_Debug.ld | 201 +++
.../Debug/labo4_1_DMA_new_Debug_library.ld | 16 +
.../Debug/labo4_1_DMA_new_Debug_memory.ld | 32 +
.../labo4.1_DMA_new/Debug/labo6_DMA.map | 440 ++++++
.../labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld | 158 +++
.../Debug/labo6_DMA_Debug_library.ld | 14 +
.../Debug/labo6_DMA_Debug_memory.ld | 31 +
.../Debug/labo6_DMA_Debug_old.ld | 163 +++
.../labo4.1_DMA_new/Debug/labo7_DMA.axf | Bin 0 -> 192267 bytes
.../labo4.1_DMA_new/Debug/labo7_DMA.map | 404 ++++++
.../labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld | 155 +++
.../Debug/labo7_DMA_Debug_lib.ld | 14 +
.../Debug/labo7_DMA_Debug_mem.ld | 25 +
.../labo4.1_DMA_new/Debug/labo_DMA.axf | Bin 0 -> 192043 bytes
.../labo4.1_DMA_new/Debug/labo_DMA.map | 403 ++++++
.../labo4.1_DMA_new/Debug/labo_DMA_Debug.ld | 154 ++
.../Debug/labo_DMA_Debug_lib.ld | 13 +
.../Debug/labo_DMA_Debug_mem.ld | 21 +
.../labo4.1_DMA_new/Debug/makefile | 60 +
.../labo4.1_DMA_new/Debug/objects.mk | 8 +
.../labo4.1_DMA_new/Debug/sources.mk | 18 +
.../Debug/src/config_LPC1769.su | 1 +
.../Debug/src/cr_startup_lpc176x.d | 1 +
.../Debug/src/cr_startup_lpc176x.o | Bin 0 -> 27024 bytes
.../Debug/src/cr_startup_lpc176x.su | 13 +
.../labo4.1_DMA_new/Debug/src/crp.d | 1 +
.../labo4.1_DMA_new/Debug/src/crp.o | Bin 0 -> 20332 bytes
.../labo4.1_DMA_new/Debug/src/crp.su | 0
.../labo4.1_DMA_new/Debug/src/dma.d | 13 +
.../labo4.1_DMA_new/Debug/src/dma.o | Bin 0 -> 58004 bytes
.../labo4.1_DMA_new/Debug/src/dma.su | 2 +
.../labo4.1_DMA_new/Debug/src/dmatest.d | 12 +
.../labo4.1_DMA_new/Debug/src/dmatest.o | Bin 0 -> 59224 bytes
.../labo4.1_DMA_new/Debug/src/dmatest.su | 4 +
.../labo4.1_DMA_new/Debug/src/subdir.mk | 47 +
.../labo4.1_DMA_new/labo6_DMA Debug.launch | 22 +
.../labo4.1_DMA_new/labo6_DMA Release.launch | 18 +
.../labo4.1_DMA_new/src/cr_startup_lpc176x.c | 421 ++++++
.../labo4.1_DMA_new/src/crp.c | 38 +
.../labo4.1_DMA_new/src/dma.c | 40 +
.../labo4.1_DMA_new/src/dma.h | 36 +
.../labo4.1_DMA_new/src/dmatest.c | 80 ++
139 files changed, 15328 insertions(+), 108 deletions(-)
create mode 100644 CMSISv2p00_LPC17xx/.gitignore
create mode 100644 labo4.1_DMA_new/.cproject
create mode 100644 labo4.1_DMA_new/.project
create mode 100644 labo4.1_DMA_new/.settings/language.settings.xml
create mode 100644 labo4.1_DMA_new/.settings/org.eclipse.core.resources.prefs
create mode 100644 labo4.1_DMA_new/Debug/labo4.1_DMA.map
create mode 100755 labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf
create mode 100644 labo4.1_DMA_new/Debug/labo4.1_DMA_new.map
create mode 100644 labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld
create mode 100644 labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld
create mode 100644 labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld
create mode 100644 labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld
create mode 100644 labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld
create mode 100644 labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld
create mode 100644 labo4.1_DMA_new/Debug/labo6_DMA.map
create mode 100644 labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld
create mode 100644 labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld
create mode 100644 labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld
create mode 100644 labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld
create mode 100644 labo4.1_DMA_new/Debug/labo7_DMA.axf
create mode 100644 labo4.1_DMA_new/Debug/labo7_DMA.map
create mode 100644 labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld
create mode 100644 labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld
create mode 100644 labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld
create mode 100644 labo4.1_DMA_new/Debug/labo_DMA.axf
create mode 100644 labo4.1_DMA_new/Debug/labo_DMA.map
create mode 100644 labo4.1_DMA_new/Debug/labo_DMA_Debug.ld
create mode 100644 labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld
create mode 100644 labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld
create mode 100644 labo4.1_DMA_new/Debug/makefile
create mode 100644 labo4.1_DMA_new/Debug/objects.mk
create mode 100644 labo4.1_DMA_new/Debug/sources.mk
create mode 100644 labo4.1_DMA_new/Debug/src/config_LPC1769.su
create mode 100644 labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d
create mode 100644 labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.o
create mode 100644 labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su
create mode 100644 labo4.1_DMA_new/Debug/src/crp.d
create mode 100644 labo4.1_DMA_new/Debug/src/crp.o
create mode 100644 labo4.1_DMA_new/Debug/src/crp.su
create mode 100644 labo4.1_DMA_new/Debug/src/dma.d
create mode 100644 labo4.1_DMA_new/Debug/src/dma.o
create mode 100644 labo4.1_DMA_new/Debug/src/dma.su
create mode 100644 labo4.1_DMA_new/Debug/src/dmatest.d
create mode 100644 labo4.1_DMA_new/Debug/src/dmatest.o
create mode 100644 labo4.1_DMA_new/Debug/src/dmatest.su
create mode 100644 labo4.1_DMA_new/Debug/src/subdir.mk
create mode 100644 labo4.1_DMA_new/labo4.1_DMA_new LinkServer Debug.launch
create mode 100644 labo4.1_DMA_new/labo6_DMA Debug.launch
create mode 100644 labo4.1_DMA_new/labo6_DMA Release.launch
create mode 100644 labo4.1_DMA_new/src/cr_startup_lpc176x.c
create mode 100644 labo4.1_DMA_new/src/crp.c
create mode 100644 labo4.1_DMA_new/src/dma.c
create mode 100644 labo4.1_DMA_new/src/dma.h
create mode 100644 labo4.1_DMA_new/src/dmatest.c
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.cproject
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.project
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.settings/language.settings.xml
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/makefile
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/objects.mk
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/sources.mk
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.su
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.su
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/docs/cmsis_readme.txt
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/history.txt
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/LPC17xx.h
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cm3.h
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/core_cm3.c
create mode 100644 labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/.cproject
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/.project
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/.settings/language.settings.xml
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA.map
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA_new.map
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA.map
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA.axf
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA.map
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA.axf
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA.map
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/makefile
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/objects.mk
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/sources.mk
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/config_LPC1769.su
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.o
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.d
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.o
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.su
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.d
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.o
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.su
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.d
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.o
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.su
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/subdir.mk
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Debug.launch
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Release.launch
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/cr_startup_lpc176x.c
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/crp.c
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.c
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.h
create mode 100644 labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dmatest.c
diff --git a/CMSISv2p00_LPC17xx/.gitignore b/CMSISv2p00_LPC17xx/.gitignore
new file mode 100644
index 0000000..f240e72
--- /dev/null
+++ b/CMSISv2p00_LPC17xx/.gitignore
@@ -0,0 +1 @@
+Debug/
diff --git a/CMSISv2p00_LPC17xx/.settings/language.settings.xml b/CMSISv2p00_LPC17xx/.settings/language.settings.xml
index f50a266..a6ba73f 100644
--- a/CMSISv2p00_LPC17xx/.settings/language.settings.xml
+++ b/CMSISv2p00_LPC17xx/.settings/language.settings.xml
@@ -3,8 +3,8 @@
<configuration id="com.crt.advproject.config.lib.debug.1814355025" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
- <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
- <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="227759477465743802" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1278103089121256333" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
@@ -15,7 +15,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
- <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="234512289041408538" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1284855900696921069" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
diff --git a/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a b/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a
index 19a1e00e3178e911307cbd9c5ea9c4ac0345b32a..a4742592d3e8b98c1fbf22f273324af36b58aa38 100644
GIT binary patch
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diff --git a/CMSISv2p00_LPC17xx/Debug/makefile b/CMSISv2p00_LPC17xx/Debug/makefile
index d573372..2002ae8 100644
--- a/CMSISv2p00_LPC17xx/Debug/makefile
+++ b/CMSISv2p00_LPC17xx/Debug/makefile
@@ -1,50 +1,60 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
--include ../makefile.init
-
-RM := rm -rf
-
-# All of the sources participating in the build are defined here
--include sources.mk
--include src/subdir.mk
--include subdir.mk
--include objects.mk
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-endif
-
--include ../makefile.defs
-
-# Add inputs and outputs from these tool invocations to the build variables
-
-# All Target
-all: libCMSISv2p00_LPC17xx.a
-
-# Tool invocations
-libCMSISv2p00_LPC17xx.a: $(OBJS) $(USER_OBJS)
- @echo 'Building target: $@'
- @echo 'Invoking: MCU Archiver'
- arm-none-eabi-ar -r "libCMSISv2p00_LPC17xx.a" $(OBJS) $(USER_OBJS) $(LIBS)
- @echo 'Finished building target: $@'
- @echo ' '
- $(MAKE) --no-print-directory post-build
-
-# Other Targets
-clean:
- -$(RM) $(OBJS)$(ARCHIVES)$(C_DEPS) libCMSISv2p00_LPC17xx.a
- -@echo ' '
-
-post-build:
- -@echo 'Performing post-build steps'
- -arm-none-eabi-size libCMSISv2p00_LPC17xx.a ; # arm-none-eabi-objdump -h -S libCMSISv2p00_LPC17xx.a >libCMSISv2p00_LPC17xx.lss
- -@echo ' '
-
-.PHONY: all clean dependents
-.SECONDARY: post-build
-
--include ../makefile.targets
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := CMSISv2p00_LPC17xx
+BUILD_ARTIFACT_EXTENSION := a
+BUILD_ARTIFACT_PREFIX := lib
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all:
+ +@$(MAKE) --no-print-directory main-build && $(MAKE) --no-print-directory post-build
+
+# Main-build Target
+main-build: libCMSISv2p00_LPC17xx.a
+
+# Tool invocations
+libCMSISv2p00_LPC17xx.a: $(OBJS) $(USER_OBJS) makefile $(OPTIONAL_TOOL_DEPS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Archiver'
+ arm-none-eabi-ar -r "libCMSISv2p00_LPC17xx.a" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) libCMSISv2p00_LPC17xx.a
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size libCMSISv2p00_LPC17xx.a ; # arm-none-eabi-objdump -h -S libCMSISv2p00_LPC17xx.a >libCMSISv2p00_LPC17xx.lss
+ -@echo ' '
+
+.PHONY: all clean dependents main-build post-build
+
+-include ../makefile.targets
diff --git a/CMSISv2p00_LPC17xx/Debug/sources.mk b/CMSISv2p00_LPC17xx/Debug/sources.mk
index b73fb96..52857d9 100644
--- a/CMSISv2p00_LPC17xx/Debug/sources.mk
+++ b/CMSISv2p00_LPC17xx/Debug/sources.mk
@@ -1,18 +1,18 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-OBJ_SRCS :=
-S_SRCS :=
-ASM_SRCS :=
-C_SRCS :=
-S_UPPER_SRCS :=
-O_SRCS :=
-OBJS :=
-ARCHIVES :=
-C_DEPS :=
-
-# Every subdirectory with source files must be described here
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ASM_SRCS :=
+C_SRCS :=
+OBJ_SRCS :=
+O_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+ARCHIVES :=
+C_DEPS :=
+OBJS :=
+
+# Every subdirectory with source files must be described here
SUBDIRS := \
src \
-
+
diff --git a/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d b/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
index d76bd14..dc66f06 100644
--- a/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
+++ b/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
@@ -1 +1 @@
-src/core_cm3.o src/core_cm3.d: ../src/core_cm3.c
+src/core_cm3.o src/core_cm3.d: ../src/core_cm3.c
diff --git a/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o b/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o
index 128ee21e8a72ab6654e4428f1e17a9df5dd4b2d0..e9e546d1e35e666b8ef75b6deca5df2d86263065 100644
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diff --git a/CMSISv2p00_LPC17xx/Debug/src/subdir.mk b/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
index fe6f04c..f2f8505 100644
--- a/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
+++ b/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
@@ -1,27 +1,34 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../src/core_cm3.c \
-../src/system_LPC17xx.c
-
-OBJS += \
-./src/core_cm3.o \
-./src/system_LPC17xx.o
-
+../src/system_LPC17xx.c
+
C_DEPS += \
./src/core_cm3.d \
-./src/system_LPC17xx.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-src/%.o: ../src/%.c
- @echo 'Building file: $<'
- @echo 'Invoking: MCU C Compiler'
- arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I../inc -O0 -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m3 -mthumb -D__REDLIB__ -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
- @echo 'Finished building: $<'
- @echo ' '
-
-
+./src/system_LPC17xx.d
+
+OBJS += \
+./src/core_cm3.o \
+./src/system_LPC17xx.o
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.c src/subdir.mk
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I../inc -O0 -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fmerge-constants -fmacro-prefix-map="$(<D)/"= -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
+clean: clean-src
+
+clean-src:
+ -$(RM) ./src/core_cm3.d ./src/core_cm3.o ./src/system_LPC17xx.d ./src/system_LPC17xx.o
+
+.PHONY: clean-src
+
diff --git a/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d b/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
index a132246..30469e0 100644
--- a/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
+++ b/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
@@ -1,13 +1,8 @@
-src/system_LPC17xx.o src/system_LPC17xx.d: ../src/system_LPC17xx.c \
- ../inc/LPC17xx.h ../inc/core_cm3.h ../inc/core_cmInstr.h \
- ../inc/core_cmFunc.h ../inc/system_LPC17xx.h
-
-../inc/LPC17xx.h:
-
-../inc/core_cm3.h:
-
-../inc/core_cmInstr.h:
-
-../inc/core_cmFunc.h:
-
-../inc/system_LPC17xx.h:
+src/system_LPC17xx.o src/system_LPC17xx.d: ../src/system_LPC17xx.c \
+ ../inc/LPC17xx.h ../inc/core_cm3.h ../inc/core_cmInstr.h \
+ ../inc/core_cmFunc.h ../inc/system_LPC17xx.h
+../inc/LPC17xx.h:
+../inc/core_cm3.h:
+../inc/core_cmInstr.h:
+../inc/core_cmFunc.h:
+../inc/system_LPC17xx.h:
diff --git a/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o b/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o
index 1478507dc774750d650918f90db6ee713abe2462..6a2b8f93459c0527f2bdff4b9bfa438b33b425ce 100644
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diff --git a/TP2_bpsk_demod/.settings/language.settings.xml b/TP2_bpsk_demod/.settings/language.settings.xml
index 2e56cdf..7e54123 100644
--- a/TP2_bpsk_demod/.settings/language.settings.xml
+++ b/TP2_bpsk_demod/.settings/language.settings.xml
@@ -4,7 +4,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
- <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="173379824774954439" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1223723436430466970" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
@@ -15,7 +15,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
- <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="173378930678947018" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1223722542334459549" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
diff --git a/labo4.1_DMA_new/.cproject b/labo4.1_DMA_new/.cproject
new file mode 100644
index 0000000..ffc8711
--- /dev/null
+++ b/labo4.1_DMA_new/.cproject
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.crt.advproject.config.exe.debug.759137190">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.759137190" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+ <folderInfo id="com.crt.advproject.config.exe.debug.759137190." name="/" resourcePath="">
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+<infoList vendor="NXP">
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+<chip>
+<name>LPC1769</name>
+<family>LPC17xx</family>
+<vendor>NXP (formerly Philips)</vendor>
+<reset board="None" core="Real" sys="Real"/>
+<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
+<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
+<memory id="RAM" type="RAM"/>
+<memory id="Periph" is_volatile="true" type="Peripheral"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/>
+<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
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+<processor>
+<name gcc_name="cortex-m3">Cortex-M3</name>
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diff --git a/labo4.1_DMA_new/.project b/labo4.1_DMA_new/.project
new file mode 100644
index 0000000..668034c
--- /dev/null
+++ b/labo4.1_DMA_new/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>labo4.1_DMA_new</name>
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diff --git a/labo4.1_DMA_new/.settings/language.settings.xml b/labo4.1_DMA_new/.settings/language.settings.xml
new file mode 100644
index 0000000..394c5b0
--- /dev/null
+++ b/labo4.1_DMA_new/.settings/language.settings.xml
@@ -0,0 +1,25 @@
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+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1223723436430466970" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+ <configuration id="com.crt.advproject.config.exe.release.1841072117" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1223722542334459549" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+</project>
\ No newline at end of file
diff --git a/labo4.1_DMA_new/.settings/org.eclipse.core.resources.prefs b/labo4.1_DMA_new/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000..99f26c0
--- /dev/null
+++ b/labo4.1_DMA_new/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8
diff --git a/labo4.1_DMA_new/Debug/labo4.1_DMA.map b/labo4.1_DMA_new/Debug/labo4.1_DMA.map
new file mode 100644
index 0000000..1c663f4
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4.1_DMA.map
@@ -0,0 +1,467 @@
+Archive member included to satisfy reference by file (symbol)
+
+c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ ./src/dmatest.o (memset)
+c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest.o
+src2 0x400 ./src/dmatest.o
+src3 0x400 ./src/dmatest.o
+i 0x4 ./src/dmatest.o
+src1 0x1000 ./src/dmatest.o
+LLI 0x20 ./src/dmatest.o
+
+Discarded input sections
+
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .text 0x00000000 0x0 ./src/config_LPC1769.o
+ .data 0x00000000 0x0 ./src/config_LPC1769.o
+ .bss 0x00000000 0x0 ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .group 0x00000000 0xc ./src/crp.o
+ .group 0x00000000 0xc ./src/crp.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .debug_macro 0x00000000 0xaa2 ./src/crp.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .text 0x00000000 0x0 ./src/dma.o
+ .data 0x00000000 0x0 ./src/dma.o
+ .bss 0x00000000 0x0 ./src/dma.o
+ .bss.DMAErrCount
+ 0x00000000 0x4 ./src/dma.o
+ .debug_macro 0x00000000 0xaa2 ./src/dma.o
+ .debug_macro 0x00000000 0x10 ./src/dma.o
+ .debug_macro 0x00000000 0x12e ./src/dma.o
+ .debug_macro 0x00000000 0x5b3 ./src/dma.o
+ .debug_macro 0x00000000 0x331 ./src/dma.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .text 0x00000000 0x0 ./src/dmatest.o
+ .data 0x00000000 0x0 ./src/dmatest.o
+ .bss 0x00000000 0x0 ./src/dmatest.o
+ .debug_macro 0x00000000 0xaa2 ./src/dmatest.o
+ .debug_macro 0x00000000 0x10 ./src/dmatest.o
+ .debug_macro 0x00000000 0x12e ./src/dmatest.o
+ .debug_macro 0x00000000 0x5b3 ./src/dmatest.o
+ .debug_macro 0x00000000 0x52 ./src/dmatest.o
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x34 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/config_LPC1769.o
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma.o
+LOAD ./src/dmatest.o
+START GROUP
+LOAD c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a
+LOAD c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a
+LOAD c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libgcc.a
+END GROUP
+ 0x00000000 __base_MFlash512 = 0x0
+ 0x00000000 __base_Flash = 0x0
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x00080000 __top_Flash = 0x80000
+ 0x10000000 __base_RamLoc32 = 0x10000000
+ 0x10000000 __base_RAM = 0x10000000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x10008000 __top_RAM = 0x10008000
+ 0x2007c000 __base_RamAHB32 = 0x2007c000
+ 0x2007c000 __base_RAM2 = 0x2007c000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+ 0x20084000 __top_RAM2 = 0x20084000
+
+.text 0x00000000 0x550
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x550 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x550 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x2828 SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x74 ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 PWM1_IRQHandler
+ 0x00000106 I2C1_IRQHandler
+ 0x00000106 EINT2_IRQHandler
+ 0x00000106 UART1_IRQHandler
+ 0x00000106 EINT3_IRQHandler
+ 0x00000106 CANActivity_IRQHandler
+ 0x00000106 TIMER3_IRQHandler
+ 0x00000106 UART0_IRQHandler
+ 0x00000106 MCPWM_IRQHandler
+ 0x00000106 I2C0_IRQHandler
+ 0x00000106 IntDefaultHandler
+ 0x00000106 RIT_IRQHandler
+ 0x00000106 CAN_IRQHandler
+ 0x00000106 PLL1_IRQHandler
+ 0x00000106 SSP0_IRQHandler
+ 0x00000106 I2S_IRQHandler
+ 0x00000106 I2C2_IRQHandler
+ 0x00000106 RTC_IRQHandler
+ 0x00000106 TIMER0_IRQHandler
+ 0x00000106 SPI_IRQHandler
+ 0x00000106 UART3_IRQHandler
+ 0x00000106 EINT1_IRQHandler
+ 0x00000106 TIMER1_IRQHandler
+ 0x00000106 UART2_IRQHandler
+ 0x00000106 ADC_IRQHandler
+ 0x00000106 SSP1_IRQHandler
+ 0x00000106 USB_IRQHandler
+ 0x00000106 BOD_IRQHandler
+ 0x00000106 USBActivity_IRQHandler
+ 0x00000106 WDT_IRQHandler
+ 0x00000106 PLL0_IRQHandler
+ 0x00000106 QEI_IRQHandler
+ 0x00000106 EINT0_IRQHandler
+ 0x00000106 TIMER2_IRQHandler
+ 0x00000106 ENET_IRQHandler
+ 0x00000108 data_init
+ 0x0000011a bss_init
+ 0x0000012a ResetISR
+ 0x000002fc . = 0x2fc
+ *fill* 0x00000168 0x194 ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__ = .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__ = .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.init 0x00000300 0x38 ./src/config_LPC1769.o
+ 0x00000300 init
+ .text.DMA_IRQHandler
+ 0x00000338 0xc ./src/dma.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x00000344 0x28 ./src/dma.o
+ 0x00000344 DMA_Init
+ .text.single_copy
+ 0x0000036c 0x68 ./src/dmatest.o
+ 0x0000036c single_copy
+ .text.LLI_copy
+ 0x000003d4 0xcc ./src/dmatest.o
+ 0x000003d4 LLI_copy
+ .text.check_res
+ 0x000004a0 0x3c ./src/dmatest.o
+ 0x000004a0 check_res
+ .text.main 0x000004dc 0x38 ./src/dmatest.o
+ 0x000004dc main
+ .text.memset 0x00000514 0x4 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ 0x00000514 memset
+ .text.__weak_main
+ 0x00000518 0x4 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ 0x00000518 __weak_main
+ 0x00000518 __main
+ .text.__aeabi_memset_lowlevel
+ 0x0000051c 0x32 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ 0x0000051c __aeabi_lowlevel_memset
+ *(.rodata .rodata.* .constdata .constdata.*)
+ 0x00000550 . = ALIGN (0x4)
+ *fill* 0x0000054e 0x2 ff
+
+.glue_7 0x00000550 0x0
+ .glue_7 0x00000550 0x0 linker stubs
+
+.glue_7t 0x00000550 0x0
+ .glue_7t 0x00000550 0x0 linker stubs
+
+.vfp11_veneer 0x00000550 0x0
+ .vfp11_veneer 0x00000550 0x0 linker stubs
+
+.v4_bx 0x00000550 0x0
+ .v4_bx 0x00000550 0x0 linker stubs
+
+.iplt 0x00000550 0x0
+ .iplt 0x00000550 0x0 ./src/config_LPC1769.o
+
+.rel.dyn 0x00000550 0x0
+ .rel.iplt 0x00000550 0x0 ./src/config_LPC1769.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM.exidx 0x00000550 0x0
+ 0x00000550 __exidx_start = .
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x00000550 __exidx_end = .
+ 0x00000550 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x00000550
+ FILL mask 0xff
+ [!provide] PROVIDE (__start_data_RAM2 = .)
+ [!provide] PROVIDE (__start_data_RamAHB32 = .)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ 0x2007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_data_RAM2 = .)
+ [!provide] PROVIDE (__end_data_RamAHB32 = .)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ 0x10000000 _start_uninit_RESERVED = .
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x00000550
+ FILL mask 0xff
+ 0x10000000 _data = .
+ [!provide] PROVIDE (__start_data_RAM = .)
+ [!provide] PROVIDE (__start_data_RamLoc32 = .)
+ *(vtable)
+ *(.ramfunc*)
+ *(CodeQuickAccess)
+ *(DataQuickAccess)
+ *(RamFunction)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+ [!provide] PROVIDE (__end_data_RAM = .)
+ [!provide] PROVIDE (__end_data_RamLoc32 = .)
+
+.igot.plt 0x10000000 0x0 load address 0x00000550
+ .igot.plt 0x10000000 0x0 ./src/config_LPC1769.o
+
+.bss_RAM2 0x2007c000 0x0
+ [!provide] PROVIDE (__start_bss_RAM2 = .)
+ [!provide] PROVIDE (__start_bss_RamAHB32 = .)
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ 0x2007c000 . = ALIGN ((. != 0x0)?0x4:0x1)
+ [!provide] PROVIDE (__end_bss_RAM2 = .)
+ [!provide] PROVIDE (__end_bss_RamAHB32 = .)
+
+.bss 0x10000000 0x2828
+ 0x10000000 _bss = .
+ [!provide] PROVIDE (__start_bss_RAM = .)
+ [!provide] PROVIDE (__start_bss_RamLoc32 = .)
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma.o
+ 0x10000000 DMATCCount
+ *(COMMON)
+ COMMON 0x10000004 0x2824 ./src/dmatest.o
+ 0x10000004 dest
+ 0x10001004 src2
+ 0x10001404 src3
+ 0x10001804 i
+ 0x10001808 src1
+ 0x10002808 LLI
+ 0x10002828 . = ALIGN (0x4)
+ 0x10002828 _ebss = .
+ [!provide] PROVIDE (__end_bss_RAM = .)
+ [!provide] PROVIDE (__end_bss_RamLoc32 = .)
+ [!provide] PROVIDE (end = .)
+
+.noinit_RAM2 0x2007c000 0x0
+ [!provide] PROVIDE (__start_noinit_RAM2 = .)
+ [!provide] PROVIDE (__start_noinit_RamAHB32 = .)
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ 0x2007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_noinit_RAM2 = .)
+ [!provide] PROVIDE (__end_noinit_RamAHB32 = .)
+
+.noinit 0x10002828 0x0
+ 0x10002828 _noinit = .
+ [!provide] PROVIDE (__start_noinit_RAM = .)
+ [!provide] PROVIDE (__start_noinit_RamLoc32 = .)
+ *(.noinit*)
+ 0x10002828 . = ALIGN (0x4)
+ 0x10002828 _end_noinit = .
+ [!provide] PROVIDE (__end_noinit_RAM = .)
+ [!provide] PROVIDE (__end_noinit_RamLoc32 = .)
+ [!provide] PROVIDE (_pvHeapStart = DEFINED (__user_heap_base)?__user_heap_base:.)
+ 0x10008000 PROVIDE (_vStackTop = DEFINED (__user_stack_top)?__user_stack_top:(__top_RamLoc32 - 0x0))
+ [!provide] PROVIDE (__valid_user_code_checksum = (0x0 - ((((((_vStackTop + (ResetISR + 0x1)) + (NMI_Handler + 0x1)) + (HardFault_Handler + 0x1)) + (DEFINED (MemManage_Handler)?MemManage_Handler:0x0 + 0x1)) + (DEFINED (BusFault_Handler)?BusFault_Handler:0x0 + 0x1)) + (DEFINED (UsageFault_Handler)?UsageFault_Handler:0x0 + 0x1))))
+ 0x00000000 _image_start = LOADADDR (.text)
+ 0x00000550 _image_end = (LOADADDR (.data) + SIZEOF (.data))
+ 0x00000550 _image_size = (_image_end - _image_start)
+OUTPUT(labo4.1_DMA.axf elf32-littlearm)
+LOAD linker stubs
+
+.debug_info 0x00000000 0x731
+ .debug_info 0x00000000 0xba ./src/config_LPC1769.o
+ .debug_info 0x000000ba 0x2e3 ./src/cr_startup_lpc176x.o
+ .debug_info 0x0000039d 0x40 ./src/crp.o
+ .debug_info 0x000003dd 0x148 ./src/dma.o
+ .debug_info 0x00000525 0x20c ./src/dmatest.o
+
+.debug_abbrev 0x00000000 0x44b
+ .debug_abbrev 0x00000000 0x8b ./src/config_LPC1769.o
+ .debug_abbrev 0x0000008b 0x156 ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x000001e1 0x38 ./src/crp.o
+ .debug_abbrev 0x00000219 0xf2 ./src/dma.o
+ .debug_abbrev 0x0000030b 0x140 ./src/dmatest.o
+
+.debug_aranges 0x00000000 0x118
+ .debug_aranges
+ 0x00000000 0x20 ./src/config_LPC1769.o
+ .debug_aranges
+ 0x00000020 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x000000a0 0x18 ./src/crp.o
+ .debug_aranges
+ 0x000000b8 0x28 ./src/dma.o
+ .debug_aranges
+ 0x000000e0 0x38 ./src/dmatest.o
+
+.debug_ranges 0x00000000 0xc0
+ .debug_ranges 0x00000000 0x10 ./src/config_LPC1769.o
+ .debug_ranges 0x00000010 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000080 0x18 ./src/dma.o
+ .debug_ranges 0x00000098 0x28 ./src/dmatest.o
+
+.debug_macro 0x00000000 0x2461
+ .debug_macro 0x00000000 0x4b ./src/config_LPC1769.o
+ .debug_macro 0x0000004b 0xaa2 ./src/config_LPC1769.o
+ .debug_macro 0x00000aed 0x10 ./src/config_LPC1769.o
+ .debug_macro 0x00000afd 0x12e ./src/config_LPC1769.o
+ .debug_macro 0x00000c2b 0x5b3 ./src/config_LPC1769.o
+ .debug_macro 0x000011de 0x331 ./src/config_LPC1769.o
+ .debug_macro 0x0000150f 0x1d ./src/cr_startup_lpc176x.o
+ .debug_macro 0x0000152c 0xaa8 ./src/cr_startup_lpc176x.o
+ .debug_macro 0x00001fd4 0x1a ./src/crp.o
+ .debug_macro 0x00001fee 0x34 ./src/crp.o
+ .debug_macro 0x00002022 0x54 ./src/dma.o
+ .debug_macro 0x00002076 0x52 ./src/dma.o
+ .debug_macro 0x000020c8 0x62 ./src/dmatest.o
+ .debug_macro 0x0000212a 0x337 ./src/dmatest.o
+
+.debug_line 0x00000000 0x997
+ .debug_line 0x00000000 0x1b6 ./src/config_LPC1769.o
+ .debug_line 0x000001b6 0x26f ./src/cr_startup_lpc176x.o
+ .debug_line 0x00000425 0xb1 ./src/crp.o
+ .debug_line 0x000004d6 0x1a3 ./src/dma.o
+ .debug_line 0x00000679 0x31e ./src/dmatest.o
+
+.debug_str 0x00000000 0x638e
+ .debug_str 0x00000000 0x5db0 ./src/config_LPC1769.o
+ 0x5e2e (size before relaxing)
+ .debug_str 0x00005db0 0x2c2 ./src/cr_startup_lpc176x.o
+ 0x2f8a (size before relaxing)
+ .debug_str 0x00006072 0xe9 ./src/crp.o
+ 0x2e80 (size before relaxing)
+ .debug_str 0x0000615b 0x192 ./src/dma.o
+ 0x5fa3 (size before relaxing)
+ .debug_str 0x000062ed 0xa1 ./src/dmatest.o
+ 0x6018 (size before relaxing)
+
+.comment 0x00000000 0x4c
+ .comment 0x00000000 0x4c ./src/config_LPC1769.o
+ 0x4d (size before relaxing)
+ .comment 0x0000004c 0x4d ./src/cr_startup_lpc176x.o
+ .comment 0x0000004c 0x4d ./src/crp.o
+ .comment 0x0000004c 0x4d ./src/dma.o
+ .comment 0x0000004c 0x4d ./src/dmatest.o
+ .comment 0x0000004c 0x4d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .comment 0x0000004c 0x4d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x2b
+ .ARM.attributes
+ 0x00000000 0x2d ./src/config_LPC1769.o
+ .ARM.attributes
+ 0x0000002d 0x2d ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x0000005a 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x0000008d 0x2d ./src/dma.o
+ .ARM.attributes
+ 0x000000ba 0x2d ./src/dmatest.o
+ .ARM.attributes
+ 0x000000e7 0x2d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000114 0x2d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000141 0x1b c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x208
+ .debug_frame 0x00000000 0x30 ./src/config_LPC1769.o
+ .debug_frame 0x00000030 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x00000124 0x58 ./src/dma.o
+ .debug_frame 0x0000017c 0x8c ./src/dmatest.o
+
+.debug_loc 0x00000000 0x16a
+ .debug_loc 0x00000000 0x16a ./src/cr_startup_lpc176x.o
diff --git a/labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf b/labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf
new file mode 100755
index 0000000000000000000000000000000000000000..c8a29e2213e2f4ac2b2894829ec7c4775d17fd5c
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diff --git a/labo4.1_DMA_new/Debug/labo4.1_DMA_new.map b/labo4.1_DMA_new/Debug/labo4.1_DMA_new.map
new file mode 100644
index 0000000..24f30df
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4.1_DMA_new.map
@@ -0,0 +1,458 @@
+Archive member included to satisfy reference by file (symbol)
+
+/opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o)
+ ./src/dmatest.o (memset)
+/opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+/opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Discarded input sections
+
+ .group 0x0000000000000000 0xc ./src/cr_startup_lpc176x.o
+ .text 0x0000000000000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x0000000000000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x0000000000000000 0x0 ./src/cr_startup_lpc176x.o
+ .group 0x0000000000000000 0xc ./src/crp.o
+ .group 0x0000000000000000 0xc ./src/crp.o
+ .text 0x0000000000000000 0x0 ./src/crp.o
+ .data 0x0000000000000000 0x0 ./src/crp.o
+ .bss 0x0000000000000000 0x0 ./src/crp.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dma.o
+ .text 0x0000000000000000 0x0 ./src/dma.o
+ .data 0x0000000000000000 0x0 ./src/dma.o
+ .bss 0x0000000000000000 0x0 ./src/dma.o
+ .bss.DMAErrCount
+ 0x0000000000000000 0x4 ./src/dma.o
+ .debug_macro 0x0000000000000000 0xaae ./src/dma.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .group 0x0000000000000000 0xc ./src/dmatest.o
+ .text 0x0000000000000000 0x0 ./src/dmatest.o
+ .data 0x0000000000000000 0x0 ./src/dmatest.o
+ .bss 0x0000000000000000 0x0 ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0xaae ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x10 ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x12e ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x5b3 ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x52 ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x1c ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x2e ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x18 ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x7af ./src/dmatest.o
+ .debug_macro 0x0000000000000000 0x2c7 ./src/dmatest.o
+ .text 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o)
+ .data 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o)
+ .bss 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o)
+ .text 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(__weak__main.o)
+ .data 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(__weak__main.o)
+ .bss 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(__weak__main.o)
+ .text 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ .data 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ .bss 0x0000000000000000 0x0 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x0000000000000000 0x34 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x0000000000000000 0x1c /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x0000000000000000 0x8 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x0000000000000000 0xa /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x0000000000000000 0x0000000000080000 xr
+RamLoc32 0x0000000010000000 0x0000000000008000 xrw
+RamAHB32 0x000000002007c000 0x0000000000008000 xrw
+*default* 0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma.o
+LOAD ./src/dmatest.o
+LOAD /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a
+LOAD /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a
+LOAD /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libgcc.a
+END GROUP
+ 0x0000000000000000 __base_MFlash512 = 0x0
+ 0x0000000000000000 __base_Flash = 0x0
+ 0x0000000000080000 __top_MFlash512 = 0x80000
+ 0x0000000000080000 __top_Flash = 0x80000
+ 0x0000000010000000 __base_RamLoc32 = 0x10000000
+ 0x0000000010000000 __base_RAM = 0x10000000
+ 0x0000000010008000 __top_RamLoc32 = 0x10008000
+ 0x0000000010008000 __top_RAM = 0x10008000
+ 0x000000002007c000 __base_RamAHB32 = 0x2007c000
+ 0x000000002007c000 __base_RAM2 = 0x2007c000
+ 0x0000000020084000 __top_RamAHB32 = 0x20084000
+ 0x0000000020084000 __top_RAM2 = 0x20084000
+
+.text 0x0000000000000000 0x5c4
+ FILL mask 0xff
+ 0x0000000000000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x0000000000000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x0000000000000000 g_pfnVectors
+ 0x00000000000000cc . = ALIGN (0x4)
+ 0x00000000000000cc __section_table_start = .
+ 0x00000000000000cc __data_section_table = .
+ 0x00000000000000cc 0x4 LONG 0x5c4 LOADADDR (.data)
+ 0x00000000000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x00000000000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x00000000000000d8 0x4 LONG 0x5c4 LOADADDR (.data_RAM2)
+ 0x00000000000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x00000000000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x00000000000000e4 __data_section_table_end = .
+ 0x00000000000000e4 __bss_section_table = .
+ 0x00000000000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x00000000000000e8 0x4 LONG 0x2828 SIZEOF (.bss)
+ 0x00000000000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x00000000000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x00000000000000f4 __bss_section_table_end = .
+ 0x00000000000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x00000000000000f4 0x74 ./src/cr_startup_lpc176x.o
+ 0x00000000000000f4 NMI_Handler
+ 0x00000000000000f6 HardFault_Handler
+ 0x00000000000000f8 MemManage_Handler
+ 0x00000000000000fa BusFault_Handler
+ 0x00000000000000fc UsageFault_Handler
+ 0x00000000000000fe SVC_Handler
+ 0x0000000000000100 DebugMon_Handler
+ 0x0000000000000102 PendSV_Handler
+ 0x0000000000000104 SysTick_Handler
+ 0x0000000000000106 TIMER2_IRQHandler
+ 0x0000000000000106 RIT_IRQHandler
+ 0x0000000000000106 I2C0_IRQHandler
+ 0x0000000000000106 USBActivity_IRQHandler
+ 0x0000000000000106 PWM1_IRQHandler
+ 0x0000000000000106 I2C1_IRQHandler
+ 0x0000000000000106 EINT2_IRQHandler
+ 0x0000000000000106 UART1_IRQHandler
+ 0x0000000000000106 EINT3_IRQHandler
+ 0x0000000000000106 CANActivity_IRQHandler
+ 0x0000000000000106 TIMER3_IRQHandler
+ 0x0000000000000106 UART0_IRQHandler
+ 0x0000000000000106 IntDefaultHandler
+ 0x0000000000000106 PLL0_IRQHandler
+ 0x0000000000000106 CAN_IRQHandler
+ 0x0000000000000106 PLL1_IRQHandler
+ 0x0000000000000106 SSP0_IRQHandler
+ 0x0000000000000106 I2S_IRQHandler
+ 0x0000000000000106 I2C2_IRQHandler
+ 0x0000000000000106 RTC_IRQHandler
+ 0x0000000000000106 TIMER0_IRQHandler
+ 0x0000000000000106 SPI_IRQHandler
+ 0x0000000000000106 EINT1_IRQHandler
+ 0x0000000000000106 TIMER1_IRQHandler
+ 0x0000000000000106 UART2_IRQHandler
+ 0x0000000000000106 ADC_IRQHandler
+ 0x0000000000000106 SSP1_IRQHandler
+ 0x0000000000000106 USB_IRQHandler
+ 0x0000000000000106 BOD_IRQHandler
+ 0x0000000000000106 WDT_IRQHandler
+ 0x0000000000000106 QEI_IRQHandler
+ 0x0000000000000106 EINT0_IRQHandler
+ 0x0000000000000106 UART3_IRQHandler
+ 0x0000000000000106 MCPWM_IRQHandler
+ 0x0000000000000106 ENET_IRQHandler
+ 0x0000000000000108 data_init
+ 0x000000000000011a bss_init
+ 0x000000000000012a ResetISR
+ 0x00000000000002fc . = 0x2fc
+ *fill* 0x0000000000000168 0x194 ff
+ 0x00000000000002fc PROVIDE (__CRP_WORD_START__ = .)
+ *(.crp)
+ .crp 0x00000000000002fc 0x4 ./src/crp.o
+ 0x00000000000002fc CRP_WORD
+ 0x0000000000000300 PROVIDE (__CRP_WORD_END__ = .)
+ 0x0000000000000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.NVIC_EnableIRQ
+ 0x0000000000000300 0x30 ./src/dma.o
+ .text.DMA_IRQHandler
+ 0x0000000000000330 0xc ./src/dma.o
+ 0x0000000000000330 DMA_IRQHandler
+ .text.DMA_Init
+ 0x000000000000033c 0xa4 ./src/dma.o
+ 0x000000000000033c DMA_Init
+ .text.single_copy
+ 0x00000000000003e0 0x68 ./src/dmatest.o
+ 0x00000000000003e0 single_copy
+ .text.LLI_copy
+ 0x0000000000000448 0xcc ./src/dmatest.o
+ 0x0000000000000448 LLI_copy
+ .text.check_res
+ 0x0000000000000514 0x3c ./src/dmatest.o
+ 0x0000000000000514 check_res
+ .text.main 0x0000000000000550 0x38 ./src/dmatest.o
+ 0x0000000000000550 main
+ .text.memset 0x0000000000000588 0x4 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o)
+ 0x0000000000000588 memset
+ .text.__weak_main
+ 0x000000000000058c 0x4 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(__weak__main.o)
+ 0x000000000000058c __main
+ 0x000000000000058c __weak_main
+ .text.__aeabi_memset_lowlevel
+ 0x0000000000000590 0x32 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+ 0x0000000000000590 __aeabi_lowlevel_memset
+ *(.rodata .rodata.* .constdata .constdata.*)
+ 0x00000000000005c4 . = ALIGN (0x4)
+ *fill* 0x00000000000005c2 0x2 ff
+
+.glue_7 0x00000000000005c4 0x0
+ .glue_7 0x00000000000005c4 0x0 linker stubs
+
+.glue_7t 0x00000000000005c4 0x0
+ .glue_7t 0x00000000000005c4 0x0 linker stubs
+
+.vfp11_veneer 0x00000000000005c4 0x0
+ .vfp11_veneer 0x00000000000005c4 0x0 linker stubs
+
+.v4_bx 0x00000000000005c4 0x0
+ .v4_bx 0x00000000000005c4 0x0 linker stubs
+
+.iplt 0x00000000000005c4 0x0
+ .iplt 0x00000000000005c4 0x0 ./src/cr_startup_lpc176x.o
+
+.rel.dyn 0x00000000000005c4 0x0
+ .rel.iplt 0x00000000000005c4 0x0 ./src/cr_startup_lpc176x.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM.exidx 0x00000000000005c4 0x0
+ 0x00000000000005c4 __exidx_start = .
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x00000000000005c4 __exidx_end = .
+ 0x00000000000005c4 _etext = .
+
+.data_RAM2 0x000000002007c000 0x0 load address 0x00000000000005c4
+ FILL mask 0xff
+ [!provide] PROVIDE (__start_data_RAM2 = .)
+ [!provide] PROVIDE (__start_data_RamAHB32 = .)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ 0x000000002007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_data_RAM2 = .)
+ [!provide] PROVIDE (__end_data_RamAHB32 = .)
+
+.uninit_RESERVED
+ 0x0000000010000000 0x0
+ 0x0000000010000000 _start_uninit_RESERVED = .
+ *(.bss.$RESERVED*)
+ 0x0000000010000000 . = ALIGN (0x4)
+ 0x0000000010000000 _end_uninit_RESERVED = .
+
+.data 0x0000000010000000 0x0 load address 0x00000000000005c4
+ FILL mask 0xff
+ 0x0000000010000000 _data = .
+ [!provide] PROVIDE (__start_data_RAM = .)
+ [!provide] PROVIDE (__start_data_RamLoc32 = .)
+ *(vtable)
+ *(.ramfunc*)
+ *(CodeQuickAccess)
+ *(DataQuickAccess)
+ *(RamFunction)
+ *(.data*)
+ 0x0000000010000000 . = ALIGN (0x4)
+ 0x0000000010000000 _edata = .
+ [!provide] PROVIDE (__end_data_RAM = .)
+ [!provide] PROVIDE (__end_data_RamLoc32 = .)
+
+.igot.plt 0x0000000010000000 0x0 load address 0x00000000000005c4
+ .igot.plt 0x0000000010000000 0x0 ./src/cr_startup_lpc176x.o
+
+.bss_RAM2 0x000000002007c000 0x0
+ [!provide] PROVIDE (__start_bss_RAM2 = .)
+ [!provide] PROVIDE (__start_bss_RamAHB32 = .)
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ 0x000000002007c000 . = ALIGN ((. != 0x0)?0x4:0x1)
+ [!provide] PROVIDE (__end_bss_RAM2 = .)
+ [!provide] PROVIDE (__end_bss_RamAHB32 = .)
+
+.bss 0x0000000010000000 0x2828
+ 0x0000000010000000 _bss = .
+ [!provide] PROVIDE (__start_bss_RAM = .)
+ [!provide] PROVIDE (__start_bss_RamLoc32 = .)
+ *(.bss*)
+ .bss.DMATCCount
+ 0x0000000010000000 0x4 ./src/dma.o
+ 0x0000000010000000 DMATCCount
+ .bss.LLI 0x0000000010000004 0x20 ./src/dmatest.o
+ 0x0000000010000004 LLI
+ .bss.src3 0x0000000010000024 0x400 ./src/dmatest.o
+ 0x0000000010000024 src3
+ .bss.i 0x0000000010000424 0x4 ./src/dmatest.o
+ 0x0000000010000424 i
+ .bss.src1 0x0000000010000428 0x1000 ./src/dmatest.o
+ 0x0000000010000428 src1
+ .bss.dest 0x0000000010001428 0x1000 ./src/dmatest.o
+ 0x0000000010001428 dest
+ .bss.src2 0x0000000010002428 0x400 ./src/dmatest.o
+ 0x0000000010002428 src2
+ *(COMMON)
+ 0x0000000010002828 . = ALIGN (0x4)
+ 0x0000000010002828 _ebss = .
+ [!provide] PROVIDE (__end_bss_RAM = .)
+ [!provide] PROVIDE (__end_bss_RamLoc32 = .)
+ [!provide] PROVIDE (end = .)
+
+.noinit_RAM2 0x000000002007c000 0x0
+ [!provide] PROVIDE (__start_noinit_RAM2 = .)
+ [!provide] PROVIDE (__start_noinit_RamAHB32 = .)
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ 0x000000002007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_noinit_RAM2 = .)
+ [!provide] PROVIDE (__end_noinit_RamAHB32 = .)
+
+.noinit 0x0000000010002828 0x0
+ 0x0000000010002828 _noinit = .
+ [!provide] PROVIDE (__start_noinit_RAM = .)
+ [!provide] PROVIDE (__start_noinit_RamLoc32 = .)
+ *(.noinit*)
+ 0x0000000010002828 . = ALIGN (0x4)
+ 0x0000000010002828 _end_noinit = .
+ [!provide] PROVIDE (__end_noinit_RAM = .)
+ [!provide] PROVIDE (__end_noinit_RamLoc32 = .)
+ [!provide] PROVIDE (_pvHeapStart = DEFINED (__user_heap_base)?__user_heap_base:.)
+ 0x0000000010008000 PROVIDE (_vStackTop = DEFINED (__user_stack_top)?__user_stack_top:(__top_RamLoc32 - 0x0))
+ [!provide] PROVIDE (__valid_user_code_checksum = (0x0 - ((((((_vStackTop + (ResetISR + 0x1)) + (NMI_Handler + 0x1)) + (HardFault_Handler + 0x1)) + (DEFINED (MemManage_Handler)?MemManage_Handler:0x0 + 0x1)) + (DEFINED (BusFault_Handler)?BusFault_Handler:0x0 + 0x1)) + (DEFINED (UsageFault_Handler)?UsageFault_Handler:0x0 + 0x1))))
+ 0x0000000000000000 _image_start = LOADADDR (.text)
+ 0x00000000000005c4 _image_end = (LOADADDR (.data) + SIZEOF (.data))
+ 0x00000000000005c4 _image_size = (_image_end - _image_start)
+OUTPUT(labo4.1_DMA_new.axf elf32-littlearm)
+LOAD linker stubs
+
+.debug_info 0x0000000000000000 0xbdd
+ .debug_info 0x0000000000000000 0x2c6 ./src/cr_startup_lpc176x.o
+ .debug_info 0x00000000000002c6 0x41 ./src/crp.o
+ .debug_info 0x0000000000000307 0x6be ./src/dma.o
+ .debug_info 0x00000000000009c5 0x218 ./src/dmatest.o
+
+.debug_abbrev 0x0000000000000000 0x4af
+ .debug_abbrev 0x0000000000000000 0x177 ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x0000000000000177 0x37 ./src/crp.o
+ .debug_abbrev 0x00000000000001ae 0x1a4 ./src/dma.o
+ .debug_abbrev 0x0000000000000352 0x15d ./src/dmatest.o
+
+.debug_loclists
+ 0x0000000000000000 0xe8
+ .debug_loclists
+ 0x0000000000000000 0xe8 ./src/cr_startup_lpc176x.o
+
+.debug_aranges 0x0000000000000000 0x100
+ .debug_aranges
+ 0x0000000000000000 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x0000000000000080 0x18 ./src/crp.o
+ .debug_aranges
+ 0x0000000000000098 0x30 ./src/dma.o
+ .debug_aranges
+ 0x00000000000000c8 0x38 ./src/dmatest.o
+
+.debug_rnglists
+ 0x0000000000000000 0xa1
+ .debug_rnglists
+ 0x0000000000000000 0x5b ./src/cr_startup_lpc176x.o
+ .debug_rnglists
+ 0x000000000000005b 0x20 ./src/dma.o
+ .debug_rnglists
+ 0x000000000000007b 0x26 ./src/dmatest.o
+
+.debug_macro 0x0000000000000000 0x28f8
+ .debug_macro 0x0000000000000000 0x1d ./src/cr_startup_lpc176x.o
+ .debug_macro 0x000000000000001d 0xab4 ./src/cr_startup_lpc176x.o
+ .debug_macro 0x0000000000000ad1 0x1a ./src/crp.o
+ .debug_macro 0x0000000000000aeb 0xaae ./src/crp.o
+ .debug_macro 0x0000000000001599 0x34 ./src/crp.o
+ .debug_macro 0x00000000000015cd 0x7e ./src/dma.o
+ .debug_macro 0x000000000000164b 0x1c ./src/dma.o
+ .debug_macro 0x0000000000001667 0x2e ./src/dma.o
+ .debug_macro 0x0000000000001695 0x10 ./src/dma.o
+ .debug_macro 0x00000000000016a5 0x12e ./src/dma.o
+ .debug_macro 0x00000000000017d3 0x5b3 ./src/dma.o
+ .debug_macro 0x0000000000001d86 0x18 ./src/dma.o
+ .debug_macro 0x0000000000001d9e 0x7af ./src/dma.o
+ .debug_macro 0x000000000000254d 0x2c7 ./src/dma.o
+ .debug_macro 0x0000000000002814 0x52 ./src/dma.o
+ .debug_macro 0x0000000000002866 0x92 ./src/dmatest.o
+
+.debug_line 0x0000000000000000 0x8bc
+ .debug_line 0x0000000000000000 0x258 ./src/cr_startup_lpc176x.o
+ .debug_line 0x0000000000000258 0xa4 ./src/crp.o
+ .debug_line 0x00000000000002fc 0x26e ./src/dma.o
+ .debug_line 0x000000000000056a 0x352 ./src/dmatest.o
+
+.debug_str 0x0000000000000000 0x8f12
+ .debug_str 0x0000000000000000 0x2f81 ./src/cr_startup_lpc176x.o
+ 0x2f94 (size before relaxing)
+ .debug_str 0x0000000000002f81 0x1b5 ./src/crp.o
+ 0x2e93 (size before relaxing)
+ .debug_str 0x0000000000003136 0x5d5e ./src/dma.o
+ 0x8b79 (size before relaxing)
+ .debug_str 0x0000000000008e94 0x7e ./src/dmatest.o
+ 0x874f (size before relaxing)
+
+.comment 0x0000000000000000 0x45
+ .comment 0x0000000000000000 0x45 ./src/cr_startup_lpc176x.o
+ 0x46 (size before relaxing)
+ .comment 0x0000000000000045 0x46 ./src/crp.o
+ .comment 0x0000000000000045 0x46 ./src/dma.o
+ .comment 0x0000000000000045 0x46 ./src/dmatest.o
+ .comment 0x0000000000000045 0x46 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o)
+ .comment 0x0000000000000045 0x46 /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x0000000000000000 0x2b
+ .ARM.attributes
+ 0x0000000000000000 0x2d ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x000000000000002d 0x2d ./src/crp.o
+ .ARM.attributes
+ 0x000000000000005a 0x2d ./src/dma.o
+ .ARM.attributes
+ 0x0000000000000087 0x2d ./src/dmatest.o
+ .ARM.attributes
+ 0x00000000000000b4 0x2d /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000000000000e1 0x2d /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x000000000000010e 0x1b /opt/mcuxpresso-ide/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.8.0.202306131047/tools/bin/../lib/gcc/arm-none-eabi/12.2.1/thumb/v7-m/nofp/libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x0000000000000000 0x1fc
+ .debug_frame 0x0000000000000000 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x00000000000000f4 0x7c ./src/dma.o
+ .debug_frame 0x0000000000000170 0x8c ./src/dmatest.o
diff --git a/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld b/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld
new file mode 100644
index 0000000..60863d7
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld
@@ -0,0 +1,203 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2022
+ * Generated linker script file for LPC1769
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.3.0 [Build 5222] [2021-01-11] on 23 nov. 2022 16:02:28
+ */
+
+INCLUDE "labo4_1_DMA_Debug_library.ld"
+INCLUDE "labo4_1_DMA_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ /* Code Read Protection data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protection */
+ } > MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+
+ .ARM.exidx : ALIGN(4)
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > MFlash512
+
+ _etext = .;
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ PROVIDE(__start_data_RamAHB32 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ PROVIDE(__end_data_RamAHB32 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32 AT> RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ PROVIDE(__start_data_RAM = .) ;
+ PROVIDE(__start_data_RamLoc32 = .) ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ PROVIDE(__end_data_RAM = .) ;
+ PROVIDE(__end_data_RamLoc32 = .) ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ PROVIDE(__start_bss_RamAHB32 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ PROVIDE(__end_bss_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM = .) ;
+ PROVIDE(__start_bss_RamLoc32 = .) ;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(__end_bss_RAM = .) ;
+ PROVIDE(__end_bss_RamLoc32 = .) ;
+ PROVIDE(end = .);
+ } > RamLoc32 AT> RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM2 = .) ;
+ PROVIDE(__start_noinit_RamAHB32 = .) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM2 = .) ;
+ PROVIDE(__end_noinit_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM = .) ;
+ PROVIDE(__start_noinit_RamLoc32 = .) ;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM = .) ;
+ PROVIDE(__end_noinit_RamLoc32 = .) ;
+ } > RamLoc32 AT> RamLoc32
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld b/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld
new file mode 100644
index 0000000..6e4a567
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld
@@ -0,0 +1,16 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2022
+ * Generated linker script file for LPC1769
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.3.0 [Build 5222] [2021-01-11] on 23 nov. 2022 16:02:28
+ */
+
+GROUP (
+ "libcr_c.a"
+ "libcr_eabihelpers.a"
+ "libgcc.a"
+)
diff --git a/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld b/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld
new file mode 100644
index 0000000..ff5f730
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld
@@ -0,0 +1,32 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2022
+ * Generated linker script file for LPC1769
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.3.0 [Build 5222] [2021-01-11] on 23 nov. 2022 16:02:28
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
diff --git a/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld b/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld
new file mode 100644
index 0000000..af059fb
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld
@@ -0,0 +1,200 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2023 NXP
+ * Generated linker script file for LPC1769
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.8.0 [Build 1165] [2023-07-26] on 15 Nov 2023, 14:07:03
+ */
+
+INCLUDE "labo4_1_DMA_new_Debug_library.ld"
+INCLUDE "labo4_1_DMA_new_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ /* Code Read Protection data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protection */
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+
+ .ARM.exidx : ALIGN(4)
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > MFlash512
+
+ _etext = .;
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ PROVIDE(__start_data_RamAHB32 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ PROVIDE(__end_data_RamAHB32 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32 AT> RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ PROVIDE(__start_data_RAM = .) ;
+ PROVIDE(__start_data_RamLoc32 = .) ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ PROVIDE(__end_data_RAM = .) ;
+ PROVIDE(__end_data_RamLoc32 = .) ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ PROVIDE(__start_bss_RamAHB32 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ PROVIDE(__end_bss_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss (NOLOAD) : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM = .) ;
+ PROVIDE(__start_bss_RamLoc32 = .) ;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(__end_bss_RAM = .) ;
+ PROVIDE(__end_bss_RamLoc32 = .) ;
+ PROVIDE(end = .);
+ } > RamLoc32 AT> RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM2 = .) ;
+ PROVIDE(__start_noinit_RamAHB32 = .) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM2 = .) ;
+ PROVIDE(__end_noinit_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM = .) ;
+ PROVIDE(__start_noinit_RamLoc32 = .) ;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM = .) ;
+ PROVIDE(__end_noinit_RamLoc32 = .) ;
+ } > RamLoc32 AT> RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld b/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld
new file mode 100644
index 0000000..f6dd191
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld
@@ -0,0 +1,15 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2023 NXP
+ * Generated linker script file for LPC1769
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.8.0 [Build 1165] [2023-07-26] on 15 Nov 2023, 14:07:03
+ */
+
+GROUP (
+ "libcr_c.a"
+ "libcr_eabihelpers.a"
+ "libgcc.a"
+)
diff --git a/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld b/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld
new file mode 100644
index 0000000..29824ac
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld
@@ -0,0 +1,31 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2023 NXP
+ * Generated linker script file for LPC1769
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.8.0 [Build 1165] [2023-07-26] on 15 Nov 2023, 14:07:03
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
diff --git a/labo4.1_DMA_new/Debug/labo6_DMA.map b/labo4.1_DMA_new/Debug/labo6_DMA.map
new file mode 100644
index 0000000..d3cae22
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo6_DMA.map
@@ -0,0 +1,440 @@
+Archive member included because of file (symbol)
+
+c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ ./src/dmatest_corrige.o (memset)
+c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest_corrige.o
+delta_t_ref 0x4 ./src/dmatest_corrige.o
+src2 0x400 ./src/dmatest_corrige.o
+t_start 0x4 ./src/dmatest_corrige.o
+src3 0x400 ./src/dmatest_corrige.o
+i 0x4 ./src/dmatest_corrige.o
+delta_t 0x4 ./src/dmatest_corrige.o
+src1 0x1000 ./src/dmatest_corrige.o
+LLI 0x20 ./src/dmatest_corrige.o
+
+Discarded input sections
+
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .text 0x00000000 0x0 ./src/config_LPC1769.o
+ .data 0x00000000 0x0 ./src/config_LPC1769.o
+ .bss 0x00000000 0x0 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .group 0x00000000 0x8 ./src/crp.o
+ .group 0x00000000 0x8 ./src/crp.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .debug_macro 0x00000000 0x86e ./src/crp.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .text 0x00000000 0x0 ./src/dma_corrige.o
+ .data 0x00000000 0x0 ./src/dma_corrige.o
+ .bss 0x00000000 0x0 ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x86e ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x10 ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x12d ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x5b2 ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x331 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 ./src/dmatest_corrige.o
+ .data 0x00000000 0x0 ./src/dmatest_corrige.o
+ .bss 0x00000000 0x0 ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x86e ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x10 ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x12d ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x5b2 ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x52 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x34 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/config_LPC1769.o
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma_corrige.o
+LOAD ./src/dmatest_corrige.o
+START GROUP
+LOAD c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a
+LOAD c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a
+END GROUP
+ 0x00000000 __base_MFlash512 = 0x0
+ 0x00000000 __base_Flash = 0x0
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x00080000 __top_Flash = 0x80000
+ 0x10000000 __base_RamLoc32 = 0x10000000
+ 0x10000000 __base_RAM = 0x10000000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x10008000 __top_RAM = 0x10008000
+ 0x2007c000 __base_RamAHB32 = 0x2007c000
+ 0x2007c000 __base_RAM2 = 0x2007c000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+ 0x20084000 __top_RAM2 = 0x20084000
+
+.text 0x00000000 0x6b8
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x6b8 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x6b8 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x2838 SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x7c ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 PWM1_IRQHandler
+ 0x00000106 I2C1_IRQHandler
+ 0x00000106 EINT2_IRQHandler
+ 0x00000106 UART1_IRQHandler
+ 0x00000106 EINT3_IRQHandler
+ 0x00000106 CANActivity_IRQHandler
+ 0x00000106 TIMER3_IRQHandler
+ 0x00000106 UART0_IRQHandler
+ 0x00000106 MCPWM_IRQHandler
+ 0x00000106 I2C0_IRQHandler
+ 0x00000106 IntDefaultHandler
+ 0x00000106 RIT_IRQHandler
+ 0x00000106 CAN_IRQHandler
+ 0x00000106 PLL1_IRQHandler
+ 0x00000106 SSP0_IRQHandler
+ 0x00000106 I2S_IRQHandler
+ 0x00000106 I2C2_IRQHandler
+ 0x00000106 RTC_IRQHandler
+ 0x00000106 TIMER0_IRQHandler
+ 0x00000106 SPI_IRQHandler
+ 0x00000106 UART3_IRQHandler
+ 0x00000106 EINT1_IRQHandler
+ 0x00000106 TIMER1_IRQHandler
+ 0x00000106 UART2_IRQHandler
+ 0x00000106 ADC_IRQHandler
+ 0x00000106 SSP1_IRQHandler
+ 0x00000106 USB_IRQHandler
+ 0x00000106 BOD_IRQHandler
+ 0x00000106 USBActivity_IRQHandler
+ 0x00000106 WDT_IRQHandler
+ 0x00000106 PLL0_IRQHandler
+ 0x00000106 QEI_IRQHandler
+ 0x00000106 EINT0_IRQHandler
+ 0x00000106 TIMER2_IRQHandler
+ 0x00000106 ENET_IRQHandler
+ 0x00000108 data_init
+ 0x0000011e bss_init
+ 0x00000130 ResetISR
+ 0x000002fc . = 0x2fc
+ *fill* 0x00000170 0x18c ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__, .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__, .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.init 0x00000300 0x38 ./src/config_LPC1769.o
+ 0x00000300 init
+ .text.DMA_IRQHandler
+ 0x00000338 0x60 ./src/dma_corrige.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x00000398 0x9c ./src/dma_corrige.o
+ 0x00000398 DMA_Init
+ .text.single_copy
+ 0x00000434 0xbc ./src/dmatest_corrige.o
+ 0x00000434 single_copy
+ .text.LLI_copy
+ 0x000004f0 0x108 ./src/dmatest_corrige.o
+ 0x000004f0 LLI_copy
+ .text.check_res
+ 0x000005f8 0x40 ./src/dmatest_corrige.o
+ 0x000005f8 check_res
+ .text.main 0x00000638 0x44 ./src/dmatest_corrige.o
+ 0x00000638 main
+ .text.memset 0x0000067c 0x4 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x0000067c memset
+ .text.__weak_main
+ 0x00000680 0x4 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ 0x00000680 __weak_main
+ 0x00000680 __main
+ .text.__aeabi_memset_lowlevel
+ 0x00000684 0x32 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ 0x00000684 __aeabi_lowlevel_memset
+ *(.rodata .rodata.* .constdata .constdata.*)
+ 0x000006b8 . = ALIGN (0x4)
+ *fill* 0x000006b6 0x2 ff
+
+.glue_7 0x000006b8 0x0
+ .glue_7 0x00000000 0x0 linker stubs
+
+.glue_7t 0x000006b8 0x0
+ .glue_7t 0x00000000 0x0 linker stubs
+
+.vfp11_veneer 0x000006b8 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x000006b8 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+
+.iplt 0x000006b8 0x0
+ .iplt 0x00000000 0x0 ./src/config_LPC1769.o
+
+.rel.dyn 0x000006b8 0x0
+ .rel.iplt 0x00000000 0x0 ./src/config_LPC1769.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ 0x000006b8 __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x000006b8 __exidx_end = .
+ 0x000006b8 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x000006b8
+ FILL mask 0xff
+ 0x2007c000 PROVIDE (__start_data_RAM2, .)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+ 0x2007c000 PROVIDE (__end_data_RAM2, .)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x000006b8
+ FILL mask 0xff
+ 0x10000000 _data = .
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+
+.igot.plt 0x10000000 0x0 load address 0x000006b8
+ .igot.plt 0x00000000 0x0 ./src/config_LPC1769.o
+
+.bss_RAM2 0x2007c000 0x0
+ 0x2007c000 PROVIDE (__start_bss_RAM2, .)
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ 0x2007c000 . = ALIGN ((. != 0x0)?0x4:0x1)
+ 0x2007c000 PROVIDE (__end_bss_RAM2, .)
+
+.bss 0x10000000 0x2838
+ 0x10000000 _bss = .
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma_corrige.o
+ 0x10000000 DMATCCount
+ .bss.DMAErrCount
+ 0x10000004 0x4 ./src/dma_corrige.o
+ 0x10000004 DMAErrCount
+ *(COMMON)
+ COMMON 0x10000008 0x2830 ./src/dmatest_corrige.o
+ 0x10000008 dest
+ 0x10001008 delta_t_ref
+ 0x1000100c src2
+ 0x1000140c t_start
+ 0x10001410 src3
+ 0x10001810 i
+ 0x10001814 delta_t
+ 0x10001818 src1
+ 0x10002818 LLI
+ 0x10002838 . = ALIGN (0x4)
+ 0x10002838 _ebss = .
+ 0x10002838 PROVIDE (end, .)
+
+.noinit_RAM2 0x2007c000 0x0
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.noinit 0x10002838 0x0
+ 0x10002838 _noinit = .
+ *(.noinit*)
+ 0x10002838 . = ALIGN (0x4)
+ 0x10002838 _end_noinit = .
+ 0x10002838 PROVIDE (_pvHeapStart, DEFINED (__user_heap_base)?__user_heap_base:.)
+ 0x10008000 PROVIDE (_vStackTop, DEFINED (__user_stack_top)?__user_stack_top:(__top_RamLoc32 - 0x0))
+ 0xefff79f2 PROVIDE (__valid_user_code_checksum, (0x0 - ((((((_vStackTop + (ResetISR + 0x1)) + (NMI_Handler + 0x1)) + (HardFault_Handler + 0x1)) + (DEFINED (MemManage_Handler)?MemManage_Handler:0x0 + 0x1)) + (DEFINED (BusFault_Handler)?BusFault_Handler:0x0 + 0x1)) + (DEFINED (UsageFault_Handler)?UsageFault_Handler:0x0 + 0x1))))
+OUTPUT(labo6_DMA.axf elf32-littlearm)
+
+.debug_info 0x00000000 0x644
+ .debug_info 0x00000000 0x81 ./src/config_LPC1769.o
+ .debug_info 0x00000081 0x26f ./src/cr_startup_lpc176x.o
+ .debug_info 0x000002f0 0x3f ./src/crp.o
+ .debug_info 0x0000032f 0x11a ./src/dma_corrige.o
+ .debug_info 0x00000449 0x1fb ./src/dmatest_corrige.o
+
+.debug_abbrev 0x00000000 0x341
+ .debug_abbrev 0x00000000 0x45 ./src/config_LPC1769.o
+ .debug_abbrev 0x00000045 0x120 ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x00000165 0x36 ./src/crp.o
+ .debug_abbrev 0x0000019b 0xa2 ./src/dma_corrige.o
+ .debug_abbrev 0x0000023d 0x104 ./src/dmatest_corrige.o
+
+.debug_aranges 0x00000000 0x118
+ .debug_aranges
+ 0x00000000 0x20 ./src/config_LPC1769.o
+ .debug_aranges
+ 0x00000020 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x000000a0 0x18 ./src/crp.o
+ .debug_aranges
+ 0x000000b8 0x28 ./src/dma_corrige.o
+ .debug_aranges
+ 0x000000e0 0x38 ./src/dmatest_corrige.o
+
+.debug_ranges 0x00000000 0xc0
+ .debug_ranges 0x00000000 0x10 ./src/config_LPC1769.o
+ .debug_ranges 0x00000010 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000080 0x18 ./src/dma_corrige.o
+ .debug_ranges 0x00000098 0x28 ./src/dmatest_corrige.o
+
+.debug_macro 0x00000000 0x1ff7
+ .debug_macro 0x00000000 0x4b ./src/config_LPC1769.o
+ .debug_macro 0x0000004b 0x86e ./src/config_LPC1769.o
+ .debug_macro 0x000008b9 0x10 ./src/config_LPC1769.o
+ .debug_macro 0x000008c9 0x12d ./src/config_LPC1769.o
+ .debug_macro 0x000009f6 0x5b2 ./src/config_LPC1769.o
+ .debug_macro 0x00000fa8 0x331 ./src/config_LPC1769.o
+ .debug_macro 0x000012d9 0x1d ./src/cr_startup_lpc176x.o
+ .debug_macro 0x000012f6 0x874 ./src/cr_startup_lpc176x.o
+ .debug_macro 0x00001b6a 0x1a ./src/crp.o
+ .debug_macro 0x00001b84 0x34 ./src/crp.o
+ .debug_macro 0x00001bb8 0x54 ./src/dma_corrige.o
+ .debug_macro 0x00001c0c 0x52 ./src/dma_corrige.o
+ .debug_macro 0x00001c5e 0x62 ./src/dmatest_corrige.o
+ .debug_macro 0x00001cc0 0x337 ./src/dmatest_corrige.o
+
+.debug_line 0x00000000 0x58d
+ .debug_line 0x00000000 0x122 ./src/config_LPC1769.o
+ .debug_line 0x00000122 0xbc ./src/cr_startup_lpc176x.o
+ .debug_line 0x000001de 0x78 ./src/crp.o
+ .debug_line 0x00000256 0x141 ./src/dma_corrige.o
+ .debug_line 0x00000397 0x1f6 ./src/dmatest_corrige.o
+
+.debug_str 0x00000000 0x5ac2
+ .debug_str 0x00000000 0x54d4 ./src/config_LPC1769.o
+ 0x5552 (size before relaxing)
+ .debug_str 0x000054d4 0x29f ./src/cr_startup_lpc176x.o
+ 0x263f (size before relaxing)
+ .debug_str 0x00005773 0xe9 ./src/crp.o
+ 0x2540 (size before relaxing)
+ .debug_str 0x0000585c 0x1a1 ./src/dma_corrige.o
+ 0x56d6 (size before relaxing)
+ .debug_str 0x000059fd 0xc5 ./src/dmatest_corrige.o
+ 0x5769 (size before relaxing)
+
+.comment 0x00000000 0xe0
+ .comment 0x00000000 0x70 ./src/config_LPC1769.o
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 ./src/cr_startup_lpc176x.o
+ .comment 0x00000000 0x71 ./src/crp.o
+ .comment 0x00000000 0x71 ./src/dma_corrige.o
+ .comment 0x00000000 0x71 ./src/dmatest_corrige.o
+ .comment 0x00000070 0x70 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x31
+ .ARM.attributes
+ 0x00000000 0x33 ./src/config_LPC1769.o
+ .ARM.attributes
+ 0x00000033 0x33 ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x00000066 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x00000099 0x33 ./src/dma_corrige.o
+ .ARM.attributes
+ 0x000000cc 0x33 ./src/dmatest_corrige.o
+ .ARM.attributes
+ 0x000000ff 0x33 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000132 0x33 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000165 0x21 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x20c
+ .debug_frame 0x00000000 0x30 ./src/config_LPC1769.o
+ .debug_frame 0x00000030 0xf0 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x00000120 0x60 ./src/dma_corrige.o
+ .debug_frame 0x00000180 0x8c ./src/dmatest_corrige.o
+
+.debug_loc 0x00000000 0x1be
+ .debug_loc 0x00000000 0x1be ./src/cr_startup_lpc176x.o
diff --git a/labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld b/labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld
new file mode 100644
index 0000000..5965732
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld
@@ -0,0 +1,158 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * LPCXpresso v8.0.0 [Build 526] [2015-11-23] on 19 janv. 2017 07:46:59
+ */
+
+INCLUDE "labo6_DMA_Debug_library.ld"
+INCLUDE "labo6_DMA_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* DATA section for RamAHB32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamAHB32
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+}
\ No newline at end of file
diff --git a/labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld b/labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld
new file mode 100644
index 0000000..af97581
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld
@@ -0,0 +1,14 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * LPCXpresso v8.0.0 [Build 526] [2015-11-23] on 19 janv. 2017 07:46:59
+ */
+
+GROUP (
+ libcr_c.a
+ libcr_eabihelpers.a
+)
diff --git a/labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld b/labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld
new file mode 100644
index 0000000..247ebe9
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld
@@ -0,0 +1,31 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.23
+ * LPCXpresso v8.0.0 [Build 526] [2015-11-23] on 19 janv. 2017 07:46:59
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
diff --git a/labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld b/labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld
new file mode 100644
index 0000000..a0693af
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld
@@ -0,0 +1,163 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from generic_c.ld (8.0.0 ())
+ * By LPCXpresso v8.0.0 [Build 526] [2015-11-23] on Thu Jan 19 07:46:58 CET 2017
+ */
+
+
+INCLUDE "labo6_DMA_Debug_library.ld"
+INCLUDE "labo6_DMA_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+}
diff --git a/labo4.1_DMA_new/Debug/labo7_DMA.axf b/labo4.1_DMA_new/Debug/labo7_DMA.axf
new file mode 100644
index 0000000000000000000000000000000000000000..3afac83f168d619448067e191671069e2206e77d
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diff --git a/labo4.1_DMA_new/Debug/labo7_DMA.map b/labo4.1_DMA_new/Debug/labo7_DMA.map
new file mode 100644
index 0000000..7971490
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo7_DMA.map
@@ -0,0 +1,404 @@
+Archive member included because of file (symbol)
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ ./src/cr_startup_lpc176x.o (SystemInit)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ ./src/dmatest_corrige.o (memset)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o) (__aeabi_uldivmod)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest_corrige.o
+src2 0x400 ./src/dmatest_corrige.o
+src3 0x400 ./src/dmatest_corrige.o
+i 0x4 ./src/dmatest_corrige.o
+src1 0x1000 ./src/dmatest_corrige.o
+LLI 0x20 ./src/dmatest_corrige.o
+
+Discarded input sections
+
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .text 0x00000000 0x0 ./src/dma_corrige.o
+ .data 0x00000000 0x0 ./src/dma_corrige.o
+ .bss 0x00000000 0x0 ./src/dma_corrige.o
+ .text 0x00000000 0x0 ./src/dmatest_corrige.o
+ .data 0x00000000 0x0 ./src/dmatest_corrige.o
+ .bss 0x00000000 0x0 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data 0x00000000 0x0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .bss 0x00000000 0x0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text.SystemCoreClockUpdate
+ 0x00000000 0xcc C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data.SystemCoreClock
+ 0x00000000 0x4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldivmod
+ 0x00000000 0x26 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uldivmod
+ 0x00000000 0x174 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x26 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma_corrige.o
+LOAD ./src/dmatest_corrige.o
+LOAD C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a
+LOAD c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a
+END GROUP
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+
+.text 0x00000000 0x898
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x898 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x898 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x282c SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x78 ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 data_init
+ 0x00000118 bss_init
+ 0x00000128 ResetISR
+ 0x00000168 UART1_IRQHandler
+ 0x00000168 EINT3_IRQHandler
+ 0x00000168 CANActivity_IRQHandler
+ 0x00000168 TIMER3_IRQHandler
+ 0x00000168 UART0_IRQHandler
+ 0x00000168 EINT2_IRQHandler
+ 0x00000168 I2C1_IRQHandler
+ 0x00000168 IntDefaultHandler
+ 0x00000168 PLL0_IRQHandler
+ 0x00000168 PWM1_IRQHandler
+ 0x00000168 PLL1_IRQHandler
+ 0x00000168 SSP0_IRQHandler
+ 0x00000168 I2S_IRQHandler
+ 0x00000168 I2C2_IRQHandler
+ 0x00000168 RTC_IRQHandler
+ 0x00000168 TIMER0_IRQHandler
+ 0x00000168 SPI_IRQHandler
+ 0x00000168 USBActivity_IRQHandler
+ 0x00000168 EINT1_IRQHandler
+ 0x00000168 TIMER1_IRQHandler
+ 0x00000168 UART2_IRQHandler
+ 0x00000168 ADC_IRQHandler
+ 0x00000168 SSP1_IRQHandler
+ 0x00000168 USB_IRQHandler
+ 0x00000168 BOD_IRQHandler
+ 0x00000168 I2C0_IRQHandler
+ 0x00000168 WDT_IRQHandler
+ 0x00000168 RIT_IRQHandler
+ 0x00000168 QEI_IRQHandler
+ 0x00000168 EINT0_IRQHandler
+ 0x00000168 CAN_IRQHandler
+ 0x00000168 TIMER2_IRQHandler
+ 0x00000168 UART3_IRQHandler
+ 0x00000168 MCPWM_IRQHandler
+ 0x00000168 ENET_IRQHandler
+ 0x000002fc . = 0x2fc
+ *fill* 0x0000016c 0x190 ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__, .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__, .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.NVIC_EnableIRQ
+ 0x00000300 0x38 ./src/dma_corrige.o
+ .text.DMA_IRQHandler
+ 0x00000338 0x7c ./src/dma_corrige.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x000003b4 0xc0 ./src/dma_corrige.o
+ 0x000003b4 DMA_Init
+ .text.single_copy
+ 0x00000474 0xa8 ./src/dmatest_corrige.o
+ 0x00000474 single_copy
+ .text.LLI_copy
+ 0x0000051c 0x1e4 ./src/dmatest_corrige.o
+ 0x0000051c LLI_copy
+ .text.check_res
+ 0x00000700 0x4c ./src/dmatest_corrige.o
+ 0x00000700 check_res
+ .text.main 0x0000074c 0x3c ./src/dmatest_corrige.o
+ 0x0000074c main
+ .text.SystemInit
+ 0x00000788 0xe4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x00000788 SystemInit
+ .text.memset 0x0000086c 0x4 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x0000086c memset
+ .text.__weak_main
+ 0x00000870 0x4 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ 0x00000870 __weak_main
+ 0x00000870 __main
+ .text.__aeabi_memset_lowlevel
+ 0x00000874 0x24 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ 0x00000874 __aeabi_lowlevel_memset
+ *(.rodata .rodata.*)
+ 0x00000898 . = ALIGN (0x4)
+
+.glue_7 0x00000898 0x0
+ .glue_7 0x00000000 0x0 linker stubs
+
+.glue_7t 0x00000898 0x0
+ .glue_7t 0x00000000 0x0 linker stubs
+
+.vfp11_veneer 0x00000898 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x00000898 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ 0x00000898 __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x00000898 __exidx_end = .
+ 0x00000898 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x00000898
+ FILL mask 0xff
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x00000898
+ FILL mask 0xff
+ 0x10000000 _data = .
+ *(vtable)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+
+.bss_RAM2 0x2007c000 0x0
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.bss 0x10000000 0x282c
+ 0x10000000 _bss = .
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma_corrige.o
+ 0x10000000 DMATCCount
+ .bss.DMAErrCount
+ 0x10000004 0x4 ./src/dma_corrige.o
+ 0x10000004 DMAErrCount
+ *(COMMON)
+ COMMON 0x10000008 0x2824 ./src/dmatest_corrige.o
+ 0x10000008 dest
+ 0x10001008 src2
+ 0x10001408 src3
+ 0x10001808 i
+ 0x1000180c src1
+ 0x1000280c LLI
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _ebss = .
+ 0x1000282c PROVIDE (end, .)
+
+.noinit_RAM2 0x2007c000 0x0
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.noinit 0x1000282c 0x0
+ 0x1000282c _noinit = .
+ *(.noinit*)
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _end_noinit = .
+ 0x1000282c PROVIDE (_pvHeapStart, .)
+ 0x10008000 PROVIDE (_vStackTop, (__top_RamLoc32 - 0x0))
+OUTPUT(labo7_DMA.axf elf32-littlearm)
+
+.debug_info 0x00000000 0xd1b
+ .debug_info 0x00000000 0x2dd ./src/cr_startup_lpc176x.o
+ .debug_info 0x000002dd 0x48 ./src/crp.o
+ .debug_info 0x00000325 0x400 ./src/dma_corrige.o
+ .debug_info 0x00000725 0x267 ./src/dmatest_corrige.o
+ .debug_info 0x0000098c 0x38f C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_abbrev 0x00000000 0x4a9
+ .debug_abbrev 0x00000000 0x12b ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x0000012b 0x39 ./src/crp.o
+ .debug_abbrev 0x00000164 0x144 ./src/dma_corrige.o
+ .debug_abbrev 0x000002a8 0x11e ./src/dmatest_corrige.o
+ .debug_abbrev 0x000003c6 0xe3 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_loc 0x00000000 0x286
+ .debug_loc 0x00000000 0x102 ./src/cr_startup_lpc176x.o
+ .debug_loc 0x00000102 0xa8 ./src/dma_corrige.o
+ .debug_loc 0x000001aa 0xbc ./src/dmatest_corrige.o
+ .debug_loc 0x00000266 0x20 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_aranges 0x00000000 0x110
+ .debug_aranges
+ 0x00000000 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x00000080 0x30 ./src/dma_corrige.o
+ .debug_aranges
+ 0x000000b0 0x38 ./src/dmatest_corrige.o
+ .debug_aranges
+ 0x000000e8 0x28 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_ranges 0x00000000 0xd0
+ .debug_ranges 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000070 0x20 ./src/dma_corrige.o
+ .debug_ranges 0x00000090 0x28 ./src/dmatest_corrige.o
+ .debug_ranges 0x000000b8 0x18 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_line 0x00000000 0x1114
+ .debug_line 0x00000000 0x3da ./src/cr_startup_lpc176x.o
+ .debug_line 0x000003da 0xac ./src/crp.o
+ .debug_line 0x00000486 0x406 ./src/dma_corrige.o
+ .debug_line 0x0000088c 0x49c ./src/dmatest_corrige.o
+ .debug_line 0x00000d28 0x3ec C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_macinfo 0x00000000 0x22317
+ .debug_macinfo
+ 0x00000000 0x3d45 ./src/cr_startup_lpc176x.o
+ .debug_macinfo
+ 0x00003d45 0x238b ./src/crp.o
+ .debug_macinfo
+ 0x000060d0 0x9e68 ./src/dma_corrige.o
+ .debug_macinfo
+ 0x0000ff38 0x9eae ./src/dmatest_corrige.o
+ .debug_macinfo
+ 0x00019de6 0x8531 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_str 0x00000000 0x792
+ .debug_str 0x00000000 0x263 ./src/cr_startup_lpc176x.o
+ 0x28b (size before relaxing)
+ .debug_str 0x00000263 0x16 ./src/crp.o
+ 0xb8 (size before relaxing)
+ .debug_str 0x00000279 0x2db ./src/dma_corrige.o
+ 0x3f6 (size before relaxing)
+ .debug_str 0x00000554 0x88 ./src/dmatest_corrige.o
+ 0x1c4 (size before relaxing)
+ .debug_str 0x000005dc 0x1b6 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x2c8 (size before relaxing)
+
+.comment 0x00000000 0x70
+ .comment 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 ./src/crp.o
+ .comment 0x00000000 0x71 ./src/dma_corrige.o
+ .comment 0x00000000 0x71 ./src/dmatest_corrige.o
+ .comment 0x00000000 0x71 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x31
+ .ARM.attributes
+ 0x00000000 0x33 ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x00000033 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x00000066 0x33 ./src/dma_corrige.o
+ .ARM.attributes
+ 0x00000099 0x33 ./src/dmatest_corrige.o
+ .ARM.attributes
+ 0x000000cc 0x33 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .ARM.attributes
+ 0x000000ff 0x33 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000132 0x33 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000165 0x21 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .ARM.attributes
+ 0x00000186 0x21 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x218
+ .debug_frame 0x00000000 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x000000f4 0x68 ./src/dma_corrige.o
+ .debug_frame 0x0000015c 0x80 ./src/dmatest_corrige.o
+ .debug_frame 0x000001dc 0x3c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
diff --git a/labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld b/labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld
new file mode 100644
index 0000000..fb58006
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld
@@ -0,0 +1,155 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2015
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC1769
+ * Created from generic_c.ld (LPCXpresso v6.0 (4 [Build 159] [2013-10-09] ))
+ * By LPCXpresso v6.0.4 [Build 159] [2013-10-09] on Wed Dec 16 18:24:34 CET 2015
+ */
+
+
+INCLUDE "labo7_DMA_Debug_lib.ld"
+INCLUDE "labo7_DMA_Debug_mem.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamAHB32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}
diff --git a/labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld b/labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld
new file mode 100644
index 0000000..e88af09
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld
@@ -0,0 +1,14 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2015
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC1769
+ * Created from LibIncTemplate.ld (LPCXpresso v6.0 (4 [Build 159] [2013-10-09] ))
+ * By LPCXpresso v6.0.4 [Build 159] [2013-10-09] on Wed Dec 16 18:24:34 CET 2015
+ */
+
+
+ GROUP(
+ libcr_c.a
+ libcr_eabihelpers.a
+ )
diff --git a/labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld b/labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld
new file mode 100644
index 0000000..37ce01f
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld
@@ -0,0 +1,25 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2015
+ * (c) NXP Semiconductors 2013-2015
+ * Linker script memory definitions
+ * Created from LinkMemoryTemplate
+ * By LPCXpresso v6.0.4 [Build 159] [2013-10-09] on Wed Dec 16 18:24:34 CET 2015)
+*/
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc32 = 0x10000000 + 0x8000;
+ __top_RamAHB32 = 0x2007c000 + 0x8000;
+
+
+
diff --git a/labo4.1_DMA_new/Debug/labo_DMA.axf b/labo4.1_DMA_new/Debug/labo_DMA.axf
new file mode 100644
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diff --git a/labo4.1_DMA_new/Debug/labo_DMA.map b/labo4.1_DMA_new/Debug/labo_DMA.map
new file mode 100644
index 0000000..d34e2ea
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo_DMA.map
@@ -0,0 +1,403 @@
+Archive member included because of file (symbol)
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ ./src/cr_startup_lpc176x.o (SystemInit)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ ./src/dmatest_corrige.o (memset)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o) (__aeabi_uldivmod)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest_corrige.o
+src2 0x400 ./src/dmatest_corrige.o
+src3 0x400 ./src/dmatest_corrige.o
+i 0x4 ./src/dmatest_corrige.o
+src1 0x1000 ./src/dmatest_corrige.o
+LLI 0x20 ./src/dmatest_corrige.o
+
+Discarded input sections
+
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .text 0x00000000 0x0 ./src/dma_corrige.o
+ .data 0x00000000 0x0 ./src/dma_corrige.o
+ .bss 0x00000000 0x0 ./src/dma_corrige.o
+ .text 0x00000000 0x0 ./src/dmatest_corrige.o
+ .data 0x00000000 0x0 ./src/dmatest_corrige.o
+ .bss 0x00000000 0x0 ./src/dmatest_corrige.o
+ .text.single_copy
+ 0x00000000 0xc4 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data 0x00000000 0x0 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .bss 0x00000000 0x0 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text.SystemCoreClockUpdate
+ 0x00000000 0xcc C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data.SystemCoreClock
+ 0x00000000 0x4 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldivmod
+ 0x00000000 0x26 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uldivmod
+ 0x00000000 0x174 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x26 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma_corrige.o
+LOAD ./src/dmatest_corrige.o
+LOAD C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a
+LOAD c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a
+END GROUP
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+
+.text 0x00000000 0x7f8
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x7f8 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x7f8 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x282c SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x78 ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 data_init
+ 0x00000118 bss_init
+ 0x00000128 ResetISR
+ 0x00000168 UART1_IRQHandler
+ 0x00000168 EINT3_IRQHandler
+ 0x00000168 CANActivity_IRQHandler
+ 0x00000168 TIMER3_IRQHandler
+ 0x00000168 UART0_IRQHandler
+ 0x00000168 EINT2_IRQHandler
+ 0x00000168 I2C1_IRQHandler
+ 0x00000168 IntDefaultHandler
+ 0x00000168 PLL0_IRQHandler
+ 0x00000168 PWM1_IRQHandler
+ 0x00000168 PLL1_IRQHandler
+ 0x00000168 SSP0_IRQHandler
+ 0x00000168 I2S_IRQHandler
+ 0x00000168 I2C2_IRQHandler
+ 0x00000168 RTC_IRQHandler
+ 0x00000168 TIMER0_IRQHandler
+ 0x00000168 SPI_IRQHandler
+ 0x00000168 USBActivity_IRQHandler
+ 0x00000168 EINT1_IRQHandler
+ 0x00000168 TIMER1_IRQHandler
+ 0x00000168 UART2_IRQHandler
+ 0x00000168 ADC_IRQHandler
+ 0x00000168 SSP1_IRQHandler
+ 0x00000168 USB_IRQHandler
+ 0x00000168 BOD_IRQHandler
+ 0x00000168 I2C0_IRQHandler
+ 0x00000168 WDT_IRQHandler
+ 0x00000168 RIT_IRQHandler
+ 0x00000168 QEI_IRQHandler
+ 0x00000168 EINT0_IRQHandler
+ 0x00000168 CAN_IRQHandler
+ 0x00000168 TIMER2_IRQHandler
+ 0x00000168 UART3_IRQHandler
+ 0x00000168 MCPWM_IRQHandler
+ 0x00000168 ENET_IRQHandler
+ 0x000002fc . = 0x2fc
+ *fill* 0x0000016c 0x190 ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__, .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__, .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.NVIC_EnableIRQ
+ 0x00000300 0x38 ./src/dma_corrige.o
+ .text.DMA_IRQHandler
+ 0x00000338 0x94 ./src/dma_corrige.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x000003cc 0xa4 ./src/dma_corrige.o
+ 0x000003cc DMA_Init
+ .text.LLI_copy
+ 0x00000470 0x200 ./src/dmatest_corrige.o
+ 0x00000470 LLI_copy
+ .text.check_res
+ 0x00000670 0x4c ./src/dmatest_corrige.o
+ 0x00000670 check_res
+ .text.main 0x000006bc 0x2c ./src/dmatest_corrige.o
+ 0x000006bc main
+ .text.SystemInit
+ 0x000006e8 0xe4 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x000006e8 SystemInit
+ .text.memset 0x000007cc 0x4 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x000007cc memset
+ .text.__weak_main
+ 0x000007d0 0x4 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ 0x000007d0 __weak_main
+ 0x000007d0 __main
+ .text.__aeabi_memset_lowlevel
+ 0x000007d4 0x24 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ 0x000007d4 __aeabi_lowlevel_memset
+ *(.rodata .rodata.*)
+ 0x000007f8 . = ALIGN (0x4)
+
+.glue_7 0x000007f8 0x0
+ .glue_7 0x00000000 0x0 linker stubs
+
+.glue_7t 0x000007f8 0x0
+ .glue_7t 0x00000000 0x0 linker stubs
+
+.vfp11_veneer 0x000007f8 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x000007f8 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ 0x000007f8 __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x000007f8 __exidx_end = .
+ 0x000007f8 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x000007f8
+ FILL mask 0xff
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x000007f8
+ FILL mask 0xff
+ 0x10000000 _data = .
+ *(vtable)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+
+.bss_RAM2 0x2007c000 0x0
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.bss 0x10000000 0x282c
+ 0x10000000 _bss = .
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma_corrige.o
+ 0x10000000 DMATCCount
+ .bss.DMAErrCount
+ 0x10000004 0x4 ./src/dma_corrige.o
+ 0x10000004 DMAErrCount
+ *(COMMON)
+ COMMON 0x10000008 0x2824 ./src/dmatest_corrige.o
+ 0x10000008 dest
+ 0x10001008 src2
+ 0x10001408 src3
+ 0x10001808 i
+ 0x1000180c src1
+ 0x1000280c LLI
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _ebss = .
+ 0x1000282c PROVIDE (end, .)
+
+.noinit_RAM2 0x2007c000 0x0
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.noinit 0x1000282c 0x0
+ 0x1000282c _noinit = .
+ *(.noinit*)
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _end_noinit = .
+ 0x1000282c PROVIDE (_pvHeapStart, .)
+ 0x10008000 PROVIDE (_vStackTop, (__top_RamLoc32 - 0x0))
+OUTPUT(labo_DMA.axf elf32-littlearm)
+
+.debug_info 0x00000000 0xd1b
+ .debug_info 0x00000000 0x2dd ./src/cr_startup_lpc176x.o
+ .debug_info 0x000002dd 0x48 ./src/crp.o
+ .debug_info 0x00000325 0x400 ./src/dma_corrige.o
+ .debug_info 0x00000725 0x267 ./src/dmatest_corrige.o
+ .debug_info 0x0000098c 0x38f C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_abbrev 0x00000000 0x4a9
+ .debug_abbrev 0x00000000 0x12b ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x0000012b 0x39 ./src/crp.o
+ .debug_abbrev 0x00000164 0x144 ./src/dma_corrige.o
+ .debug_abbrev 0x000002a8 0x11e ./src/dmatest_corrige.o
+ .debug_abbrev 0x000003c6 0xe3 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_loc 0x00000000 0x286
+ .debug_loc 0x00000000 0x102 ./src/cr_startup_lpc176x.o
+ .debug_loc 0x00000102 0xa8 ./src/dma_corrige.o
+ .debug_loc 0x000001aa 0xbc ./src/dmatest_corrige.o
+ .debug_loc 0x00000266 0x20 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_aranges 0x00000000 0x110
+ .debug_aranges
+ 0x00000000 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x00000080 0x30 ./src/dma_corrige.o
+ .debug_aranges
+ 0x000000b0 0x38 ./src/dmatest_corrige.o
+ .debug_aranges
+ 0x000000e8 0x28 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_ranges 0x00000000 0xd0
+ .debug_ranges 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000070 0x20 ./src/dma_corrige.o
+ .debug_ranges 0x00000090 0x28 ./src/dmatest_corrige.o
+ .debug_ranges 0x000000b8 0x18 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_line 0x00000000 0x110e
+ .debug_line 0x00000000 0x3d8 ./src/cr_startup_lpc176x.o
+ .debug_line 0x000003d8 0xad ./src/crp.o
+ .debug_line 0x00000485 0x403 ./src/dma_corrige.o
+ .debug_line 0x00000888 0x495 ./src/dmatest_corrige.o
+ .debug_line 0x00000d1d 0x3f1 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_macinfo 0x00000000 0x22317
+ .debug_macinfo
+ 0x00000000 0x3d45 ./src/cr_startup_lpc176x.o
+ .debug_macinfo
+ 0x00003d45 0x238b ./src/crp.o
+ .debug_macinfo
+ 0x000060d0 0x9e68 ./src/dma_corrige.o
+ .debug_macinfo
+ 0x0000ff38 0x9eae ./src/dmatest_corrige.o
+ .debug_macinfo
+ 0x00019de6 0x8531 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_str 0x00000000 0x783
+ .debug_str 0x00000000 0x25b ./src/cr_startup_lpc176x.o
+ 0x283 (size before relaxing)
+ .debug_str 0x0000025b 0x16 ./src/crp.o
+ 0xb0 (size before relaxing)
+ .debug_str 0x00000271 0x2db ./src/dma_corrige.o
+ 0x3ee (size before relaxing)
+ .debug_str 0x0000054c 0x88 ./src/dmatest_corrige.o
+ 0x1bc (size before relaxing)
+ .debug_str 0x000005d4 0x1af C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x2c1 (size before relaxing)
+
+.comment 0x00000000 0x70
+ .comment 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 ./src/crp.o
+ .comment 0x00000000 0x71 ./src/dma_corrige.o
+ .comment 0x00000000 0x71 ./src/dmatest_corrige.o
+ .comment 0x00000000 0x71 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x31
+ .ARM.attributes
+ 0x00000000 0x33 ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x00000033 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x00000066 0x33 ./src/dma_corrige.o
+ .ARM.attributes
+ 0x00000099 0x33 ./src/dmatest_corrige.o
+ .ARM.attributes
+ 0x000000cc 0x33 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .ARM.attributes
+ 0x000000ff 0x33 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000132 0x33 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000165 0x21 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .ARM.attributes
+ 0x00000186 0x21 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x218
+ .debug_frame 0x00000000 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x000000f4 0x68 ./src/dma_corrige.o
+ .debug_frame 0x0000015c 0x80 ./src/dmatest_corrige.o
+ .debug_frame 0x000001dc 0x3c C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
diff --git a/labo4.1_DMA_new/Debug/labo_DMA_Debug.ld b/labo4.1_DMA_new/Debug/labo_DMA_Debug.ld
new file mode 100644
index 0000000..46f8ad1
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo_DMA_Debug.ld
@@ -0,0 +1,154 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2015
+ * Generated linker script file for LPC1769
+ * Created from generic_c.ld (vLPCXpresso v5.2 (6 [Build 2137] [2013-07-08] ))
+ * By LPCXpresso v5.2.6 [Build 2137] [2013-07-08] on Fri Jan 09 22:38:35 CET 2015
+ */
+
+
+INCLUDE "labo_DMA_Debug_lib.ld"
+INCLUDE "labo_DMA_Debug_mem.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamAHB32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}
diff --git a/labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld b/labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld
new file mode 100644
index 0000000..2e8b5b9
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld
@@ -0,0 +1,13 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2015
+ * Generated linker script file for LPC1769
+ * Created from LibIncTemplate.ld (vLPCXpresso v5.2 (6 [Build 2137] [2013-07-08] ))
+ * By LPCXpresso v5.2.6 [Build 2137] [2013-07-08] on Fri Jan 09 22:38:35 CET 2015
+ */
+
+
+ GROUP(
+ libcr_c.a
+ libcr_eabihelpers.a
+ )
diff --git a/labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld b/labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld
new file mode 100644
index 0000000..de3f6c5
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld
@@ -0,0 +1,21 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2015
+ * Linker script memory definitions
+ * Created from LinkMemoryTemplate
+ * By LPCXpresso v5.2.6 [Build 2137] [2013-07-08] on Fri Jan 09 22:38:35 CET 2015)
+*/
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc32 = 0x10000000 + 0x8000;
+ __top_RamAHB32 = 0x2007c000 + 0x8000;
+
diff --git a/labo4.1_DMA_new/Debug/makefile b/labo4.1_DMA_new/Debug/makefile
new file mode 100644
index 0000000..ec1ba87
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/makefile
@@ -0,0 +1,60 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := labo4.1_DMA_new
+BUILD_ARTIFACT_EXTENSION := axf
+BUILD_ARTIFACT_PREFIX :=
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all:
+ +@$(MAKE) --no-print-directory main-build && $(MAKE) --no-print-directory post-build
+
+# Main-build Target
+main-build: labo4.1_DMA_new.axf
+
+# Tool invocations
+labo4.1_DMA_new.axf: $(OBJS) $(USER_OBJS) makefile $(OPTIONAL_TOOL_DEPS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Linker'
+ arm-none-eabi-gcc -nostdlib -L"/home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/Debug" -Xlinker -Map="labo4.1_DMA_new.map" -Xlinker --gc-sections -mcpu=cortex-m3 -mthumb -T labo4_1_DMA_new_Debug.ld -o "labo4.1_DMA_new.axf" $(OBJS) $(USER_OBJS) $(LIBS) -lCMSISv2p00_LPC17xx
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) labo4.1_DMA_new.axf
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size "labo4.1_DMA_new.axf"; # arm-none-eabi-objcopy -O binary "labo4.1_DMA_new.axf" "labo4.1_DMA_new.bin" ; checksum -p LPC1769 -d "labo4.1_DMA_new.bin";
+ -@echo ' '
+
+.PHONY: all clean dependents main-build post-build
+
+-include ../makefile.targets
diff --git a/labo4.1_DMA_new/Debug/objects.mk b/labo4.1_DMA_new/Debug/objects.mk
new file mode 100644
index 0000000..dc31e16
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/labo4.1_DMA_new/Debug/sources.mk b/labo4.1_DMA_new/Debug/sources.mk
new file mode 100644
index 0000000..6b18dbc
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/sources.mk
@@ -0,0 +1,18 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ASM_SRCS :=
+C_SRCS :=
+OBJ_SRCS :=
+O_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+C_DEPS :=
+EXECUTABLES :=
+OBJS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
diff --git a/labo4.1_DMA_new/Debug/src/config_LPC1769.su b/labo4.1_DMA_new/Debug/src/config_LPC1769.su
new file mode 100644
index 0000000..ef495e2
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/config_LPC1769.su
@@ -0,0 +1 @@
+config_LPC1769.c:4:6:init 4 static
diff --git a/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d b/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d
new file mode 100644
index 0000000..e517810
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d
@@ -0,0 +1 @@
+src/cr_startup_lpc176x.o: ../src/cr_startup_lpc176x.c
diff --git a/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.o b/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.o
new file mode 100644
index 0000000000000000000000000000000000000000..2fcc5e81a92b80eca6af761a423c6308a573fd2f
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diff --git a/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su b/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su
new file mode 100644
index 0000000..1946209
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su
@@ -0,0 +1,13 @@
+../src/cr_startup_lpc176x.c:346:6:NMI_Handler 0 static
+../src/cr_startup_lpc176x.c:353:6:HardFault_Handler 0 static
+../src/cr_startup_lpc176x.c:360:6:MemManage_Handler 0 static
+../src/cr_startup_lpc176x.c:367:6:BusFault_Handler 0 static
+../src/cr_startup_lpc176x.c:374:6:UsageFault_Handler 0 static
+../src/cr_startup_lpc176x.c:381:6:SVC_Handler 0 static
+../src/cr_startup_lpc176x.c:388:6:DebugMon_Handler 0 static
+../src/cr_startup_lpc176x.c:395:6:PendSV_Handler 0 static
+../src/cr_startup_lpc176x.c:402:6:SysTick_Handler 0 static
+../src/cr_startup_lpc176x.c:416:6:IntDefaultHandler 0 static
+../src/cr_startup_lpc176x.c:216:6:data_init 8 static
+../src/cr_startup_lpc176x.c:225:6:bss_init 0 static
+../src/cr_startup_lpc176x.c:271:1:ResetISR 16 static
diff --git a/labo4.1_DMA_new/Debug/src/crp.d b/labo4.1_DMA_new/Debug/src/crp.d
new file mode 100644
index 0000000..e2ac2b2
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/crp.d
@@ -0,0 +1 @@
+src/crp.o src/crp.d: ../src/crp.c
diff --git a/labo4.1_DMA_new/Debug/src/crp.o b/labo4.1_DMA_new/Debug/src/crp.o
new file mode 100644
index 0000000000000000000000000000000000000000..2d87517f774c7ff05cef5993ea01e7bb1189dbb1
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diff --git a/labo4.1_DMA_new/Debug/src/crp.su b/labo4.1_DMA_new/Debug/src/crp.su
new file mode 100644
index 0000000..e69de29
diff --git a/labo4.1_DMA_new/Debug/src/dma.d b/labo4.1_DMA_new/Debug/src/dma.d
new file mode 100644
index 0000000..6e353db
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/dma.d
@@ -0,0 +1,13 @@
+src/dma.o src/dma.d: ../src/dma.c \
+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/LPC17xx.h \
+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/core_cm3.h \
+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/core_cmInstr.h \
+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/core_cmFunc.h \
+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h \
+ ../src/dma.h
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+/home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/core_cmFunc.h:
+/home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h:
+../src/dma.h:
diff --git a/labo4.1_DMA_new/Debug/src/dma.o b/labo4.1_DMA_new/Debug/src/dma.o
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diff --git a/labo4.1_DMA_new/Debug/src/dma.su b/labo4.1_DMA_new/Debug/src/dma.su
new file mode 100644
index 0000000..007d558
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/dma.su
@@ -0,0 +1,3 @@
+/home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/core_cm3.h:928:22:NVIC_EnableIRQ 16 static
+../src/dma.c:16:6:DMA_IRQHandler 4 static
+../src/dma.c:35:6:DMA_Init 24 static
diff --git a/labo4.1_DMA_new/Debug/src/dmatest.d b/labo4.1_DMA_new/Debug/src/dmatest.d
new file mode 100644
index 0000000..b5a6d95
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/dmatest.d
@@ -0,0 +1,12 @@
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+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/core_cmInstr.h \
+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/core_cmFunc.h \
+ /home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
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diff --git a/labo4.1_DMA_new/Debug/src/dmatest.su b/labo4.1_DMA_new/Debug/src/dmatest.su
new file mode 100644
index 0000000..e7a27aa
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/dmatest.su
@@ -0,0 +1,4 @@
+../src/dmatest.c:17:6:single_copy 8 static
+../src/dmatest.c:30:6:LLI_copy 8 static
+../src/dmatest.c:52:5:check_res 16 static
+../src/dmatest.c:67:5:main 8 static
diff --git a/labo4.1_DMA_new/Debug/src/subdir.mk b/labo4.1_DMA_new/Debug/src/subdir.mk
new file mode 100644
index 0000000..2ccfefc
--- /dev/null
+++ b/labo4.1_DMA_new/Debug/src/subdir.mk
@@ -0,0 +1,47 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../src/cr_startup_lpc176x.c \
+../src/crp.c \
+../src/dma.c \
+../src/dmatest.c
+
+C_DEPS += \
+./src/cr_startup_lpc176x.d \
+./src/crp.d \
+./src/dma.d \
+./src/dmatest.d
+
+OBJS += \
+./src/cr_startup_lpc176x.o \
+./src/crp.o \
+./src/dma.o \
+./src/dmatest.o
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/cr_startup_lpc176x.o: ../src/cr_startup_lpc176x.c src/subdir.mk
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I"/home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc" -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fmerge-constants -fmacro-prefix-map="$(<D)/"= -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+src/%.o: ../src/%.c src/subdir.mk
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I"/home/iliya/isc/pro/labo/CMSISv2p00_LPC17xx/inc" -O0 -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fmerge-constants -fmacro-prefix-map="$(<D)/"= -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
+clean: clean-src
+
+clean-src:
+ -$(RM) ./src/cr_startup_lpc176x.d ./src/cr_startup_lpc176x.o ./src/crp.d ./src/crp.o ./src/dma.d ./src/dma.o ./src/dmatest.d ./src/dmatest.o
+
+.PHONY: clean-src
+
diff --git a/labo4.1_DMA_new/labo4.1_DMA_new LinkServer Debug.launch b/labo4.1_DMA_new/labo4.1_DMA_new LinkServer Debug.launch
new file mode 100644
index 0000000..f3af3f4
--- /dev/null
+++ b/labo4.1_DMA_new/labo4.1_DMA_new LinkServer Debug.launch
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
+ <stringAttribute key=".gdbinit" value=""/>
+ <booleanAttribute key="attach" value="false"/>
+ <booleanAttribute key="boot.config.enable" value="false"/>
+ <stringAttribute key="boot.configuration.control" value=""/>
+ <stringAttribute key="bootrom.stall" value=""/>
+ <stringAttribute key="com.crt.ctrlcenter.OFSemuDetails" value="LinkServer"/>
+ <booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
+ <stringAttribute key="com.crt.ctrlcenter.currentWireType" value="SWD"/>
+ <booleanAttribute key="com.crt.ctrlcenter.mainBreakIsHardware" value="true"/>
+ <stringAttribute key="com.crt.ctrlcenter.serialNumber" value="LinkServerNXP SemiconductorsLPC11U3x CMSIS-DAP v1.0.40102C036"/>
+ <mapAttribute key="com.crt.ctrlcenter.symbolsGroupSettings"/>
+ <intAttribute key="com.crt.ctrlcenter.version" value="6"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.base.address" value="0x0"/>
+ <booleanAttribute key="com.nxp.mcuxpresso.flash.clear.console" value="true"/>
+ <booleanAttribute key="com.nxp.mcuxpresso.flash.confirm" value="false"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.erase.algorithm" value="Mass erase"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.executable" value="axf"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.program.action" value="Program"/>
+ <booleanAttribute key="com.nxp.mcuxpresso.flash.reset.target" value="true"/>
+ <stringAttribute key="com.nxp.mcuxpresso.ide.probe.manufacturer" value="NXP Semiconductors"/>
+ <stringAttribute key="com.nxp.mcuxpresso.ide.probe.name" value="LPC11U3x CMSIS-DAP v1.0.4"/>
+ <stringAttribute key="com.nxp.mcuxpresso.ide.probe.type" value="LinkServer"/>
+ <stringAttribute key="debug.level" value="2"/>
+ <stringAttribute key="emu.speed" value=""/>
+ <stringAttribute key="flash.driver.reset" value=""/>
+ <stringAttribute key="gdbserver.host" value="localhost"/>
+ <stringAttribute key="gdbserver.port" value="10989"/>
+ <booleanAttribute key="gdbserver.start" value="true"/>
+ <stringAttribute key="internal.connect.script" value=""/>
+ <booleanAttribute key="internal.has_swo" value="true"/>
+ <stringAttribute key="internal.prelaunch.command" value=""/>
+ <stringAttribute key="internal.reset.script" value=""/>
+ <stringAttribute key="internal.resethandling" value="VECTRESET"/>
+ <stringAttribute key="internal.semihost" value="On"/>
+ <stringAttribute key="internal.wirespeed" value=""/>
+ <stringAttribute key="internal.wiretype" value="SWD*,JTAG"/>
+ <stringAttribute key="isp.control" value="xxxx"/>
+ <stringAttribute key="launch.config.handler" value="com.crt.ctrlcenter.launch.CRTLaunchConfigHandler"/>
+ <booleanAttribute key="mem.access" value="false"/>
+ <stringAttribute key="misc.options" value=""/>
+ <stringAttribute key="ondisconnect" value="cont"/>
+ <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="0"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set non-stop on set pagination off set mi-async set remotetimeout 60000 ##target_extended_remote## set mem inaccessible-by-default ${mem.access} mon ondisconnect ${ondisconnect} set arm force-mode thumb ${load} 	"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+ <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="10989"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=" ${run} 	"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.EXTERNAL_CONSOLE" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=""/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+ <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+ <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
+ <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+ <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/labo4.1_DMA_new.axf"/>
+ <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="labo4.1_DMA_new"/>
+ <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.759137190"/>
+ <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
+ <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+ <listEntry value="/labo4.1_DMA_new"/>
+ </listAttribute>
+ <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+ <listEntry value="4"/>
+ </listAttribute>
+ <mapAttribute key="org.eclipse.debug.core.preferred_launchers">
+ <mapEntry key="[debug]" value="com.nxp.mcuxpresso.core.debug.support.linkserver.launch.LinkServerGdbLaunch"/>
+ </mapAttribute>
+ <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><memoryBlockExpressionList context="reserved-for-future-use"/>"/>
+ <stringAttribute key="process_factory_id" value="com.nxp.mcuxpresso.core.debug.override.MCXProcessFactory"/>
+ <booleanAttribute key="redlink.disable.preconnect.script" value="false"/>
+ <booleanAttribute key="redlink.enable.flashhashing" value="true"/>
+ <booleanAttribute key="redlink.enable.rangestepping" value="true"/>
+ <stringAttribute key="run" value="cont"/>
+ <booleanAttribute key="vector.catch" value="false"/>
+</launchConfiguration>
diff --git a/labo4.1_DMA_new/labo6_DMA Debug.launch b/labo4.1_DMA_new/labo6_DMA Debug.launch
new file mode 100644
index 0000000..159c237
--- /dev/null
+++ b/labo4.1_DMA_new/labo6_DMA Debug.launch
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
+<stringAttribute key="LAUNCH_ID.OFSemuDetails" value="LPC-Link (HID)"/>
+<booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
+<stringAttribute key="com.crt.ctrlcenter.currentWireType" value="SWD"/>
+<stringAttribute key="com.crt.ctrlcenter.targetbase" value="NXP LPC17xx"/>
+<stringAttribute key="com.crt.ctrlcenter.targetconfig" value="<?xml version="1.0" encoding="UTF-8"?> <config chipvendor="NXP" genname="NXP LPC17xx" id="config.gdb.stub"><parameters><params><param default="true" description="Vector catch" name="Vector catch" value="false" var="vector.catch"><enum value="True"/> <enum value="False"/> </param> </params> <initValue value="false" var="vector.catch"/> <params><param default="On" description="Enablement of semihosting support" name="Semihosting support" value="On" var="internal.semihost"><enum value="On"/> <enum value="Off"/> <enum value="Auto"/> </param> </params> <params><param default="" description="Maximum wire speed in KHz (leave blank to Auto-detect). Not all values are supported by all targets" name="Maximum wire speed" probe="^(?!Redlink Server$).*$" type="nullString" value="" var="emu.speed"><enum value=""/> <enum value="30000"/> <enum value="15000"/> <enum value="10000"/> <enum value="7500"/> <enum value="6000"/> <enum value="5000"/> <enum value="3750"/> <enum value="3000"/> <enum value="2500"/> <enum value="2000"/> <enum value="1500"/> <enum value="1250"/> <enum value="1200"/> <enum value="1000"/> <enum value="750"/> <enum value="600"/> <enum value="500"/> <enum value="400"/> <enum value="300"/> <enum value="250"/> <enum value="200"/> <enum value="150"/> </param> </params> <params><param content="serverScript" description="Connect script" name="Connect Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.connect.script"/> <param content="serverScript" description="Reset script" name="Reset Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.reset.script"/> <param default="" description="Select the reset handling type for this debug connection" name="Reset Handling" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="VECTRESET" var="internal.resethandling"><enum value="SYSRESETREQ"/> <enum value="VECTRESET"/> <enum value="Default"/> <enum value=""/> </param> <param default="" description="Additional options" name="Additional options" value="" var="misc.options"/> <param default="2" description="Set stub debug level (1-4)" name="Debug Level " value="2" var="debug.level"/> <param default="False" description="when True, attach to running target only (without loading image)" name="Attach only" required="true" value="False" var="attach"><enum value="True"/> <enum value="False"/> </param> <param default="True" description="Deprecated. Functionality superseded by &apos;Attach only&apos;" name="Load image" type="boolean" value="True" var="load"><enum value="True"/> <enum value="False"/> </param> <param default="cont" description="Run, continue or (do nothing)" name="Run/Continue image" value="cont" var="run"><enum value="run"/> <enum value="cont"/> <enum value=""/> </param> <param default="off" description="If on is specified, make the debugger treat unknown memory as non-existent and refuse \naccesses to such memory. If off is specified, treat the memory as RAM" name="Memory Access Checking" value="off" var="mem.access"><enum value="on"/> <enum value="off"/> </param> <param default="cont" description="choose the disconnect behavior for the target" name="Disconnect behavior" value="cont" var="ondisconnect"><enum value="nochange"/> <enum value="stop"/> <enum value="cont"/> <enum value="run_cont"/> </param> <param default="" description="Command to run before starting the debugger" name="Pre launch command" value="" var="internal.prelaunch.command"/> <param default="" description="Target Wirespeed in Hz" name="Wirespeed (Hz)" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="" var="internal.wirespeed"/> </params> <initvalue value="VECTRESET" var="internal.resethandling"/> <params><param default="SWD" description="Internal wiretypes" mode="hidden" name="Wiretype" probe="NEVER" value="SWD*,JTAG" var="internal.wiretype"></param> <param default="false" description="Chip supports SWO" mode="hidden" name="Has SWO" probe="NEVER" value="true" var="internal.has_swo"></param> </params> <initvalue value="SWD*,JTAG" var="internal.wiretype"/> <initvalue value="true" var="internal.has_swo"/> </parameters> <script emulators="${gdb.stub} -mi -info-emu" silent="false" swv="true" type="init">set remotetimeout 60000&#x0A;##target_extended_remote##&#x0A;set mem inaccessible-by-default ${mem.access}&#x0A;mon ondisconnect ${ondisconnect}&#x0A;set arm force-mode thumb&#x0A;${load}</script> <script silent="false" type="run">${run}</script> </config> "/>
+<intAttribute key="com.crt.ctrlcenter.version" value="3"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.GDB_INIT" value=""/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\labo6_DMA.axf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="labo6_DMA"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.759137190"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/labo4.1_DMA_new/labo6_DMA Release.launch b/labo4.1_DMA_new/labo6_DMA Release.launch
new file mode 100644
index 0000000..3c50751
--- /dev/null
+++ b/labo4.1_DMA_new/labo6_DMA Release.launch
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
+<booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
+<stringAttribute key="com.crt.ctrlcenter.targetbase" value="NXP LPC17xx"/>
+<stringAttribute key="com.crt.ctrlcenter.targetconfig" value="<?xml version="1.0" encoding="UTF-8"?> <config chipvendor="NXP" genname="NXP LPC17xx" id="config.gdb.stub"><parameters><params><param default="true" description="Vector catch" name="Vector catch" value="false" var="vector.catch"><enum value="True"/> <enum value="False"/> </param> </params> <initValue value="false" var="vector.catch"/> <params><param default="On" description="Enablement of semihosting support" name="Semihosting support" value="On" var="internal.semihost"><enum value="On"/> <enum value="Off"/> <enum value="Auto"/> </param> </params> <params><param default="" description="Maximum wire speed in KHz (leave blank to Auto-detect). Not all values are supported by all targets" name="Maximum wire speed" probe="^(?!Redlink Server$).*$" type="nullString" value="" var="emu.speed"><enum value=""/> <enum value="30000"/> <enum value="15000"/> <enum value="10000"/> <enum value="7500"/> <enum value="6000"/> <enum value="5000"/> <enum value="3750"/> <enum value="3000"/> <enum value="2500"/> <enum value="2000"/> <enum value="1500"/> <enum value="1250"/> <enum value="1200"/> <enum value="1000"/> <enum value="750"/> <enum value="600"/> <enum value="500"/> <enum value="400"/> <enum value="300"/> <enum value="250"/> <enum value="200"/> <enum value="150"/> </param> </params> <params><param content="serverScript" description="Connect script" name="Connect Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.connect.script"/> <param content="serverScript" description="Reset script" name="Reset Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.reset.script"/> <param default="" description="Select the reset handling type for this debug connection" name="Reset Handling" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="VECTRESET" var="internal.resethandling"><enum value="SYSRESETREQ"/> <enum value="VECTRESET"/> <enum value="Default"/> <enum value=""/> </param> <param default="" description="Additional options" name="Additional options" value="" var="misc.options"/> <param default="2" description="Set stub debug level (1-4)" name="Debug Level " value="2" var="debug.level"/> <param default="False" description="when True, attach to running target only (without loading image)" name="Attach only" required="true" value="False" var="attach"><enum value="True"/> <enum value="False"/> </param> <param default="True" description="Deprecated. Functionality superseded by &apos;Attach only&apos;" name="Load image" type="boolean" value="True" var="load"><enum value="True"/> <enum value="False"/> </param> <param default="cont" description="Run, continue or (do nothing)" name="Run/Continue image" value="cont" var="run"><enum value="run"/> <enum value="cont"/> <enum value=""/> </param> <param default="off" description="If on is specified, make the debugger treat unknown memory as non-existent and refuse \naccesses to such memory. If off is specified, treat the memory as RAM" name="Memory Access Checking" value="off" var="mem.access"><enum value="on"/> <enum value="off"/> </param> <param default="cont" description="choose the disconnect behavior for the target" name="Disconnect behavior" value="cont" var="ondisconnect"><enum value="nochange"/> <enum value="stop"/> <enum value="cont"/> <enum value="run_cont"/> </param> <param default="" description="Command to run before starting the debugger" name="Pre launch command" value="" var="internal.prelaunch.command"/> <param default="" description="Target Wirespeed in Hz" name="Wirespeed (Hz)" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="" var="internal.wirespeed"/> </params> <initvalue value="VECTRESET" var="internal.resethandling"/> <params><param default="SWD" description="Internal wiretypes" mode="hidden" name="Wiretype" probe="NEVER" value="SWD*,JTAG" var="internal.wiretype"></param> <param default="false" description="Chip supports SWO" mode="hidden" name="Has SWO" probe="NEVER" value="true" var="internal.has_swo"></param> </params> <initvalue value="SWD*,JTAG" var="internal.wiretype"/> <initvalue value="true" var="internal.has_swo"/> </parameters> <script emulators="${gdb.stub} -mi -info-emu" silent="false" swv="true" type="init">set remotetimeout 60000&#x0A;##target_extended_remote##&#x0A;set mem inaccessible-by-default ${mem.access}&#x0A;mon ondisconnect ${ondisconnect}&#x0A;set arm force-mode thumb&#x0A;${load}</script> <script silent="false" type="run">${run}</script> </config> "/>
+<intAttribute key="com.crt.ctrlcenter.version" value="3"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.GDB_INIT" value=""/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release\labo6_DMA.axf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="labo6_DMA"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.release.1841072117"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
+</launchConfiguration>
diff --git a/labo4.1_DMA_new/src/cr_startup_lpc176x.c b/labo4.1_DMA_new/src/cr_startup_lpc176x.c
new file mode 100644
index 0000000..d847441
--- /dev/null
+++ b/labo4.1_DMA_new/src/cr_startup_lpc176x.c
@@ -0,0 +1,421 @@
+//*****************************************************************************
+// +--+
+// | ++----+
+// +-++ |
+// | |
+// +-+--+ |
+// | +--+--+
+// +----+ Copyright (c) 2009-12 Code Red Technologies Ltd.
+//
+// Microcontroller Startup code for use with Red Suite
+//
+// Version : 120126
+//
+// Software License Agreement
+//
+// The software is owned by Code Red Technologies and/or its suppliers, and is
+// protected under applicable copyright laws. All rights are reserved. Any
+// use in violation of the foregoing restrictions may subject the user to criminal
+// sanctions under applicable laws, as well as to civil liability for the breach
+// of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
+// CODE RED TECHNOLOGIES LTD.
+//
+//*****************************************************************************
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+// Code Red - if CMSIS is being used, then SystemInit() routine
+// will be called by startup code rather than in application's main()
+#if defined (__USE_CMSIS)
+#include "system_LPC17xx.h"
+#endif
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM3
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC17
+ WDT_IRQHandler, // 16, 0x40 - WDT
+ TIMER0_IRQHandler, // 17, 0x44 - TIMER0
+ TIMER1_IRQHandler, // 18, 0x48 - TIMER1
+ TIMER2_IRQHandler, // 19, 0x4c - TIMER2
+ TIMER3_IRQHandler, // 20, 0x50 - TIMER3
+ UART0_IRQHandler, // 21, 0x54 - UART0
+ UART1_IRQHandler, // 22, 0x58 - UART1
+ UART2_IRQHandler, // 23, 0x5c - UART2
+ UART3_IRQHandler, // 24, 0x60 - UART3
+ PWM1_IRQHandler, // 25, 0x64 - PWM1
+ I2C0_IRQHandler, // 26, 0x68 - I2C0
+ I2C1_IRQHandler, // 27, 0x6c - I2C1
+ I2C2_IRQHandler, // 28, 0x70 - I2C2
+ SPI_IRQHandler, // 29, 0x74 - SPI
+ SSP0_IRQHandler, // 30, 0x78 - SSP0
+ SSP1_IRQHandler, // 31, 0x7c - SSP1
+ PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
+ RTC_IRQHandler, // 33, 0x84 - RTC
+ EINT0_IRQHandler, // 34, 0x88 - EINT0
+ EINT1_IRQHandler, // 35, 0x8c - EINT1
+ EINT2_IRQHandler, // 36, 0x90 - EINT2
+ EINT3_IRQHandler, // 37, 0x94 - EINT3
+ ADC_IRQHandler, // 38, 0x98 - ADC
+ BOD_IRQHandler, // 39, 0x9c - BOD
+ USB_IRQHandler, // 40, 0xA0 - USB
+ CAN_IRQHandler, // 41, 0xa4 - CAN
+ DMA_IRQHandler, // 42, 0xa8 - GP DMA
+ I2S_IRQHandler, // 43, 0xac - I2S
+ ENET_IRQHandler, // 44, 0xb0 - Ethernet
+ RIT_IRQHandler, // 45, 0xb4 - RITINT
+ MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
+ QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
+ PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
+ USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
+ CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
+};
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+#ifndef USE_OLD_STYLE_DATA_BSS_INIT
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+#else
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the load address, execution address and length of the RW data section and
+// the execution and length of the BSS (zero initialized) section.
+// Note that these symbols are not normally used by the managed linker script
+// mechanism in Red Suite/LPCXpresso 3.6 (Windows) and LPCXpresso 3.8 (Linux).
+// They are provide here simply so this startup code can be used with earlier
+// versions of Red Suite which do not support the more advanced managed linker
+// script mechanism introduced in the above version. To enable their use,
+// define "USE_OLD_STYLE_DATA_BSS_INIT".
+//*****************************************************************************
+extern unsigned int _etext;
+extern unsigned int _data;
+extern unsigned int _edata;
+extern unsigned int _bss;
+extern unsigned int _ebss;
+#endif
+
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void
+ResetISR(void) {
+
+#ifndef USE_OLD_STYLE_DATA_BSS_INIT
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+#else
+ // Use Old Style Data and BSS section initialization.
+ // This will only initialize a single RAM bank.
+ unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen;
+
+ // Copy the data segment from flash to SRAM.
+ LoadAddr = &_etext;
+ ExeAddr = &_data;
+ EndAddr = &_edata;
+ SectionLen = (void*)EndAddr - (void*)ExeAddr;
+ data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
+ // Zero fill the bss segment
+ ExeAddr = &_bss;
+ EndAddr = &_ebss;
+ SectionLen = (void*)EndAddr - (void*)ExeAddr;
+ bss_init ((unsigned int)ExeAddr, SectionLen);
+#endif
+
+#ifdef __USE_CMSIS
+ SystemInit();
+#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{
+ while(1)
+ {
+ }
+}
diff --git a/labo4.1_DMA_new/src/crp.c b/labo4.1_DMA_new/src/crp.c
new file mode 100644
index 0000000..fa9a0d5
--- /dev/null
+++ b/labo4.1_DMA_new/src/crp.c
@@ -0,0 +1,38 @@
+//*****************************************************************************
+// crp.c
+//
+// Source file to create CRP word expected by LPCXpresso IDE linker
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products. This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__CODE_RED)
+#include <NXP/crp.h>
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+#endif
diff --git a/labo4.1_DMA_new/src/dma.c b/labo4.1_DMA_new/src/dma.c
new file mode 100644
index 0000000..dc1312a
--- /dev/null
+++ b/labo4.1_DMA_new/src/dma.c
@@ -0,0 +1,50 @@
+/****************************************************************************
+ DMA driver
+****************************************************************************/
+
+#include "LPC17xx.h"
+#include "dma.h"
+
+/* to be incremented when terminal count reached */
+volatile uint32_t DMATCCount = 0;
+/* to be incremented if an error occurred during transfer */
+volatile uint32_t DMAErrCount = 0;
+
+/******************************************************************************
+* Descriptions: DMA interrupt handler
+******************************************************************************/
+void DMA_IRQHandler (void)
+{
+ /*...*/
+}
+
+
+/******************************************************************************
+* Function name: DMA_Init
+*
+* Description: initialise DMA 0 channel for 32 bits access with increment on
+* source and destination addresses
+*
+* parameters:
+* src: source address
+* dest: destination address
+* len: number of words to transfer
+* LLI: pointer on LLI structure if used or 0
+*
+******************************************************************************/
+void DMA_Init(uint32_t *src, uint32_t *dest, uint32_t len, uint32_t LLI)
+{
+ LPC_SC->PCONP |= (1 << 29); /* Enable GPDMA clock */
+ LPC_GPDMACH0->DMACCConfig |= (1 << 0); // Enabling channel 0 (bit 1 is associated with endianness [by default val = 0] => little-endian)
+ LPC_GPDMA->DMACIntTCClear |= (1 << 0); // Clears the channels terminal count interrupt
+ LPC_GPDMA->DMACIntErrClr |= (1 << 0); // Clears the channels error interrupt
+ LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)src;
+ LPC_GPDMACH0->DMACCDestAddr = (uint32_t)dest;
+ LPC_GPDMACH0->DMACCLLI = LLI;
+ LPC_GPDMACH0->DMACCControl |= (len & 0xFFF); // Setting transfer size
+ LPC_GPDMACH0->DMACCControl |= (1 << 12); // Burst size of 4 for src
+ LPC_GPDMACH0->DMACCControl |= (1 << 15); // Burst size of 4 for dst
+ LPC_GPDMACH0->DMACCControl |= (1 << 31); // Enabling interrupt on terminal count
+ NVIC_EnableIRQ(DMA_IRQn);
+ /*...*/
+}
diff --git a/labo4.1_DMA_new/src/dma.h b/labo4.1_DMA_new/src/dma.h
new file mode 100644
index 0000000..3381a2c
--- /dev/null
+++ b/labo4.1_DMA_new/src/dma.h
@@ -0,0 +1,36 @@
+/****************************************************************************
+ DMA constants definition
+****************************************************************************/
+#ifndef __DMA_H
+#define __DMA_H
+
+#define DMA_SRC 0x2007C000
+#define DMA_DST 0x20080000
+#define DMA_SIZE 0x1000
+
+#define M2M 0x00
+#define M2P 0x01
+#define P2M 0x02
+#define P2P 0x03
+
+#define BURST4 0x04
+#define WORD32_TRANSFER 0x2
+#define INCREMENT 1
+#define TERMINAL_INTERRUPT 0x80000000
+
+#define DMA_CFG ((BURST4 << 12) | (BURST4 << 15) \
+ | (WORD32_TRANSFER << 18) | (WORD32_TRANSFER << 21) | (INCREMENT << 26) | (INCREMENT << 27) | \
+ TERMINAL_INTERRUPT)
+
+void DMA_Init(uint32_t *src, uint32_t *dest, uint32_t len, uint32_t LLI);
+
+typedef struct
+{
+ volatile uint32_t DMACCSrcAddr;
+ volatile uint32_t DMACCDestAddr;
+ volatile uint32_t DMACCLLI;
+ volatile uint32_t DMACCControl;
+} GPDMALLI_t;
+
+#endif
+
diff --git a/labo4.1_DMA_new/src/dmatest.c b/labo4.1_DMA_new/src/dmatest.c
new file mode 100644
index 0000000..c8339c6
--- /dev/null
+++ b/labo4.1_DMA_new/src/dmatest.c
@@ -0,0 +1,80 @@
+/****************************************************************************
+ Single DMA transfer and DMA with LLI transfer
+****************************************************************************/
+#include <string.h>
+#include <stdint.h>
+#include "dma.h"
+#include "LPC17xx.h"
+
+extern volatile uint32_t DMATCCount;
+
+GPDMALLI_t LLI[2];
+uint32_t src3[DMA_SIZE/16], i;
+uint32_t src1[DMA_SIZE/4], dest[DMA_SIZE/4];
+uint32_t src2[DMA_SIZE/16];
+
+// copy 1 source buffers in 1 destination buffer with DMA
+void single_copy()
+{
+ for (i = 0; i < DMA_SIZE/4; i++)
+ {
+ src1[i] = i;
+ dest[i] = 0; // clear destination vector
+ }
+ DMA_Init(src1, dest, DMA_SIZE/4, 0);
+
+ while (!DMATCCount); /* Wait until DMA is done */
+}
+
+// copy 3 source buffers in 1 destination buffer with DMA linked lists
+void LLI_copy()
+{
+ DMATCCount = 0;
+ for (i = 0; i < DMA_SIZE/8; i++)
+ {
+ src1[i] = i;
+ dest[i] = dest[i+DMA_SIZE/8] = 0; // clear destination vector
+ }
+ for (i = 0; i < DMA_SIZE/16; i++)
+ {
+ src2[i] = i + DMA_SIZE/8;
+ src3[i] = i + DMA_SIZE/8 + DMA_SIZE/16;
+ }
+
+ /*...*/
+
+ DMA_Init(src1, dest, DMA_SIZE/8, (uint32_t)&LLI[0]);
+
+ while (DMATCCount < 3); /* Wait until DMA is done (3 interrupts here) */
+}
+
+/* Verify copy result */
+int check_res()
+{
+ int i;
+
+ for (i = 0; i < DMA_SIZE/4; i++)
+ {
+ if (dest[i]!=i)
+ {
+ return 1; // error
+ }
+ }
+ return 0;
+}
+
+
+int main (void)
+{
+ memset(LLI, 0, sizeof(GPDMALLI_t)*2);
+
+ single_copy();
+ if (check_res())
+ while(1); // error
+ LLI_copy();
+ if (check_res())
+ while(1); // error
+
+ while (1); /* Done here, never exit from main for easier debugging. */
+}
+
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.cproject b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.cproject
new file mode 100644
index 0000000..788ef8d
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.cproject
@@ -0,0 +1,510 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.crt.advproject.config.lib.debug.1814355025">
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+ <externalSetting>
+ <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/CMSISv2p00_LPC17xx"/>
+ <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/CMSISv2p00_LPC17xx/Debug"/>
+ <entry flags="RESOLVED" kind="libraryFile" name="CMSISv2p00_LPC17xx" srcPrefixMapping="" srcRootPath=""/>
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+ </externalSettings>
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diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.project b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.project
new file mode 100644
index 0000000..5cd9643
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.project
@@ -0,0 +1,81 @@
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+ <value></value>
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+ <value>true</value>
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+ <dictionary>
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+ <value>all</value>
+ </dictionary>
+ <dictionary>
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+ <value></value>
+ </dictionary>
+ <dictionary>
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+ <value>make</value>
+ </dictionary>
+ <dictionary>
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+ <value>${workspace_loc:/CMSISv2p00_LPC17xx/Debug}</value>
+ </dictionary>
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+ <value>clean</value>
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diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.settings/language.settings.xml b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.settings/language.settings.xml
new file mode 100644
index 0000000..d3aa711
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/.settings/language.settings.xml
@@ -0,0 +1,25 @@
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+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1932461160191779786" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+ <configuration id="com.crt.advproject.config.lib.release.1079171862" name="Release">
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+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
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+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+</project>
\ No newline at end of file
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/libCMSISv2p00_LPC17xx.a
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diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/makefile b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/makefile
new file mode 100644
index 0000000..632bb01
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/makefile
@@ -0,0 +1,60 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := CMSISv2p00_LPC17xx
+BUILD_ARTIFACT_EXTENSION := a
+BUILD_ARTIFACT_PREFIX := lib
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all:
+ +@$(MAKE) --no-print-directory main-build && $(MAKE) --no-print-directory post-build
+
+# Main-build Target
+main-build: libCMSISv2p00_LPC17xx.a
+
+# Tool invocations
+libCMSISv2p00_LPC17xx.a: $(OBJS) $(USER_OBJS) makefile $(OPTIONAL_TOOL_DEPS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Archiver'
+ arm-none-eabi-ar -r "libCMSISv2p00_LPC17xx.a" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) libCMSISv2p00_LPC17xx.a
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size libCMSISv2p00_LPC17xx.a ; # arm-none-eabi-objdump -h -S libCMSISv2p00_LPC17xx.a >libCMSISv2p00_LPC17xx.lss
+ -@echo ' '
+
+.PHONY: all clean dependents main-build post-build
+
+-include ../makefile.targets
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/objects.mk b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/objects.mk
new file mode 100644
index 0000000..dc31e16
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/sources.mk b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/sources.mk
new file mode 100644
index 0000000..ad6c692
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/sources.mk
@@ -0,0 +1,18 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ASM_SRCS :=
+C_SRCS :=
+OBJ_SRCS :=
+O_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+ARCHIVES :=
+C_DEPS :=
+OBJS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
new file mode 100644
index 0000000..d76bd14
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.d
@@ -0,0 +1 @@
+src/core_cm3.o src/core_cm3.d: ../src/core_cm3.c
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.o
new file mode 100644
index 0000000000000000000000000000000000000000..31dd02d8f6cfecf495556c15dbaca10b6bc1058f
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literal 0
HcmV?d00001
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.su b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/core_cm3.su
new file mode 100644
index 0000000..e69de29
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/subdir.mk b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
new file mode 100644
index 0000000..2d446c7
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/subdir.mk
@@ -0,0 +1,34 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../src/core_cm3.c \
+../src/system_LPC17xx.c
+
+C_DEPS += \
+./src/core_cm3.d \
+./src/system_LPC17xx.d
+
+OBJS += \
+./src/core_cm3.o \
+./src/system_LPC17xx.o
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.c src/subdir.mk
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I../inc -O0 -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fmerge-constants -fmacro-prefix-map="$(<D)/"= -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
+clean: clean-src
+
+clean-src:
+ -$(RM) ./src/core_cm3.d ./src/core_cm3.o ./src/system_LPC17xx.d ./src/system_LPC17xx.o
+
+.PHONY: clean-src
+
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
new file mode 100644
index 0000000..c9e1188
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.d
@@ -0,0 +1,8 @@
+src/system_LPC17xx.o src/system_LPC17xx.d: ../src/system_LPC17xx.c \
+ ../inc/LPC17xx.h ../inc/core_cm3.h ../inc/core_cmInstr.h \
+ ../inc/core_cmFunc.h ../inc/system_LPC17xx.h
+../inc/LPC17xx.h:
+../inc/core_cm3.h:
+../inc/core_cmInstr.h:
+../inc/core_cmFunc.h:
+../inc/system_LPC17xx.h:
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.o
new file mode 100644
index 0000000000000000000000000000000000000000..1ec628d39ff0a4c3b5e1cedcefa1dda43568055f
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diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.su b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.su
new file mode 100644
index 0000000..1b9d658
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/Debug/src/system_LPC17xx.su
@@ -0,0 +1,2 @@
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+../src/system_LPC17xx.c:475:6:SystemInit 0 static
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/docs/CMSIS END USER LICENCE AGREEMENT.pdf
new file mode 100644
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HcmV?d00001
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/docs/cmsis_readme.txt b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/docs/cmsis_readme.txt
new file mode 100644
index 0000000..316499c
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/docs/cmsis_readme.txt
@@ -0,0 +1,44 @@
+CMSIS : Cortex Microcontroller Software Interface Standard
+==========================================================
+
+Introduction
+~~~~~~~~~~~~
+CMSIS defines for a Cortex-M Microcontroller System:
+
+ * A common way to access peripheral registers and a
+ common way to define exception vectors.
+ * The register names of the Core Peripherals and the
+ names of the Core Exception Vectors.
+ * An device independent interface for RTOS Kernels
+ including a debug channel.
+
+By using CMSIS compliant software components, the user can
+easier re-use template code. CMSIS is intended to enable the
+combination of software components from multiple middleware
+vendors.
+
+This project contains appropriate files for this MCU family
+taken from CMSIS. A full copy of the CMSIS files, together
+with additional information on CMSIS can be found at:
+
+ http://www.onarm.com/
+ http://www.arm.com/
+
+Documentation
+~~~~~~~~~~~~~
+The standard CMSIS documentation can be found within the
+Code Red IDE help system, via:
+
+Help -> Help Contents -> Code Red Product Documentation -> CMSIS
+
+More information on the use of CMSIS within the Code Red IDE
+can be found in the Support area of the Code Red website at
+
+ http://www.code-red-tech.com/
+
+At the time of writing, the CMSIS FAQ can be found directly
+at:
+
+ http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS
+
+
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/history.txt b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/history.txt
new file mode 100644
index 0000000..42ca3af
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/history.txt
@@ -0,0 +1,12 @@
+History of updates to CMSISv2p00_LPC17xx
+========================================
+
+7 March 2011
+------------
+LPC17xx CMSIS 2.0 library project using ARM
+Cortex-M3 CMSIS files as supplied in ARM's CMSIS 2.0
+December 2010 release, together with device/board
+specific files from NXP (as previously supplied in
+CMSISv1p30_LPC17xx library project, dated 24 Aug 2010).
+
+Note files are built -Os for both Debug and Release
\ No newline at end of file
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/LPC17xx.h b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/LPC17xx.h
new file mode 100644
index 0000000..8c4050b
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/LPC17xx.h
@@ -0,0 +1,1035 @@
+/**************************************************************************//**
+ * @file LPC17xx.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * NXP LPC17xx Device Series
+ * @version: V1.09
+ * @date: 17. March 2010
+
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ SPI_IRQn = 13, /*!< SPI Interrupt */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /* USB Activity interrupt */
+ CANActivity_IRQn = 34, /* CAN Activity interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system_LPC17xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON;
+ __IO uint32_t PLL1CFG;
+ __I uint32_t PLL1STAT;
+ __O uint32_t PLL1FEED;
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ __IO uint32_t CANSLEEPCLR;
+ __IO uint32_t CANWAKEFLAGS;
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ uint32_t RESERVED5;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ __IO uint32_t DMAREQSEL;
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+ __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ union {
+ __IO uint32_t FIODIR;
+ struct {
+ __IO uint16_t FIODIRL;
+ __IO uint16_t FIODIRH;
+ };
+ struct {
+ __IO uint8_t FIODIR0;
+ __IO uint8_t FIODIR1;
+ __IO uint8_t FIODIR2;
+ __IO uint8_t FIODIR3;
+ };
+ };
+ uint32_t RESERVED0[3];
+ union {
+ __IO uint32_t FIOMASK;
+ struct {
+ __IO uint16_t FIOMASKL;
+ __IO uint16_t FIOMASKH;
+ };
+ struct {
+ __IO uint8_t FIOMASK0;
+ __IO uint8_t FIOMASK1;
+ __IO uint8_t FIOMASK2;
+ __IO uint8_t FIOMASK3;
+ };
+ };
+ union {
+ __IO uint32_t FIOPIN;
+ struct {
+ __IO uint16_t FIOPINL;
+ __IO uint16_t FIOPINH;
+ };
+ struct {
+ __IO uint8_t FIOPIN0;
+ __IO uint8_t FIOPIN1;
+ __IO uint8_t FIOPIN2;
+ __IO uint8_t FIOPIN3;
+ };
+ };
+ union {
+ __IO uint32_t FIOSET;
+ struct {
+ __IO uint16_t FIOSETL;
+ __IO uint16_t FIOSETH;
+ };
+ struct {
+ __IO uint8_t FIOSET0;
+ __IO uint8_t FIOSET1;
+ __IO uint8_t FIOSET2;
+ __IO uint8_t FIOSET3;
+ };
+ };
+ union {
+ __O uint32_t FIOCLR;
+ struct {
+ __O uint16_t FIOCLRL;
+ __O uint16_t FIOCLRH;
+ };
+ struct {
+ __O uint8_t FIOCLR0;
+ __O uint8_t FIOCLR1;
+ __O uint8_t FIOCLR2;
+ __O uint8_t FIOCLR3;
+ };
+ };
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART0_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __IO uint32_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __IO uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t RICOMPVAL;
+ __IO uint32_t RIMASK;
+ __IO uint8_t RICTRL;
+ uint8_t RESERVED0[3];
+ __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t MCCON;
+ __O uint32_t MCCON_SET;
+ __O uint32_t MCCON_CLR;
+ __I uint32_t MCCAPCON;
+ __O uint32_t MCCAPCON_SET;
+ __O uint32_t MCCAPCON_CLR;
+ __IO uint32_t MCTIM0;
+ __IO uint32_t MCTIM1;
+ __IO uint32_t MCTIM2;
+ __IO uint32_t MCPER0;
+ __IO uint32_t MCPER1;
+ __IO uint32_t MCPER2;
+ __IO uint32_t MCPW0;
+ __IO uint32_t MCPW1;
+ __IO uint32_t MCPW2;
+ __IO uint32_t MCDEADTIME;
+ __IO uint32_t MCCCP;
+ __IO uint32_t MCCR0;
+ __IO uint32_t MCCR1;
+ __IO uint32_t MCCR2;
+ __I uint32_t MCINTEN;
+ __O uint32_t MCINTEN_SET;
+ __O uint32_t MCINTEN_CLR;
+ __I uint32_t MCCNTCON;
+ __O uint32_t MCCNTCON_SET;
+ __O uint32_t MCCNTCON_CLR;
+ __I uint32_t MCINTFLAG;
+ __O uint32_t MCINTFLAG_SET;
+ __O uint32_t MCINTFLAG_CLR;
+ __O uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t QEICON;
+ __I uint32_t QEISTAT;
+ __IO uint32_t QEICONF;
+ __I uint32_t QEIPOS;
+ __IO uint32_t QEIMAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP;
+ __IO uint32_t QEILOAD;
+ __I uint32_t QEITIME;
+ __I uint32_t QEIVEL;
+ __I uint32_t QEICAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTER;
+ uint32_t RESERVED0[998];
+ __O uint32_t QEIIEC;
+ __O uint32_t QEIIES;
+ __I uint32_t QEIINTSTAT;
+ __I uint32_t QEIIE;
+ __O uint32_t QEICLR;
+ __O uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+ __IO uint32_t FCANIE;
+ __IO uint32_t FCANIC0;
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_GPIO_BASE (0x2009C000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
+#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+
+#endif // __LPC17xx_H__
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cm3.h b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cm3.h
new file mode 100644
index 0000000..6b019a4
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cm3.h
@@ -0,0 +1,1236 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V2.01
+ * @date 06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M3
+
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+ It consists of:
+
+ - Cortex-M Core Register Definitions
+ - Cortex-M functions
+ - Cortex-M instructions
+
+ The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+ access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
+ List of Lint messages which will be suppressed and not shown:
+ - not yet checked
+ .
+ Note: To re-enable a Message, insert a space before 'lint' *
+
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core
+ - Cortex-M core Revision Number
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+#include <stdint.h> /*!< standard types definitions */
+#include "core_cmInstr.h" /*!< Core Instruction Access */
+#include "core_cmFunc.h" /*!< Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE CMSIS Core
+ Type definitions for the Cortex-M Core Registers
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC CMSIS NVIC
+ Type definitions for the Cortex-M NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB CMSIS SCB
+ Type definitions for the Cortex-M System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick CMSIS SysTick
+ Type definitions for the Cortex-M System Timer Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM CMSIS ITM
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_InterruptType CMSIS Interrupt Type
+ Type definitions for the Cortex-M Interrupt Type Register
+ @{
+ */
+
+/** \brief Structure type to access the Interrupt Type Register.
+ */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
+#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
+#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
+
+/*@}*/ /* end of group CMSIS_InterruptType */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU CMSIS MPU
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug
+ Type definitions for the Cortex-M Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ This function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ This function gets the priority grouping from NVIC Interrupt Controller.
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+ \return Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ This function enables a device specific interupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ This function disables a device specific interupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ This function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Number of the interrupt for get pending
+ \return 0 Interrupt status is not pending
+ \return 1 Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ This function sets the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ This function clears the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ This function reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Number of the interrupt for get active
+ \return 0 Interrupt status is not active
+ \return 1 Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ This function sets the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ Note: The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Number of the interrupt for set priority
+ \param [in] priority Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ This function reads the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ The returned priority value is automatically aligned to the implemented
+ priority bits of the microcontroller.
+
+ \param [in] IRQn Number of the interrupt for get priority
+ \return Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ This function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The returned priority value can be used for NVIC_SetPriority(...) function
+
+ \param [in] PriorityGroup Used priority group
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)
+ \param [in] SubPriority Sub priority value (starting from 0)
+ \return Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ This function decodes an interrupt priority value with the given priority group to
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The priority value can be retrieved with NVIC_GetPriority(...) function
+
+ \param [in] Priority Priority value
+ \param [in] PriorityGroup Used priority group
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)
+ \param [out] pSubPriority Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ This function initialises the system tick timer and its interrupt and start the system tick timer.
+ Counter is in free running mode to generate periodical interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief ITM Send Character
+
+ This function transmits a character via the ITM channel 0.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \param [in] ch Character to transmit
+ \return Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ This function inputs a character via external variable ITM_RxBuffer.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \return Received character
+ \return -1 No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ This function checks external variable ITM_RxBuffer whether a character is available or not.
+ It returns '1' if a character is available and '0' if no character is available.
+
+ \return 0 No character available
+ \return 1 Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*lint -restore */
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmFunc.h b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
new file mode 100644
index 0000000..1ff04d9
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
@@ -0,0 +1,844 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V2.01
+ * @date 06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H__
+#define __CORE_CMFUNC_H__
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_CONTROL(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_CONTROL(uint32_t control);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_IPSR(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_APSR(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_xPSR(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_PSP(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_PSP(uint32_t topOfProcStack);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_MSP(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_MSP(uint32_t topOfMainStack);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_PRIMASK(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_PRIMASK(uint32_t priMask);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+#endif /* __ARMCC_VERSION */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_BASEPRI(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_BASEPRI(uint32_t basePri);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+#if (__ARMCC_VERSION < 400000)
+extern uint32_t __get_FAULTMASK(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __set_FAULTMASK(uint32_t faultMask);
+#else /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+#endif /* __ARMCC_VERSION */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+ #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+#pragma diag_suppress=Pe940
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_irq __enable_interrupt
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_irq __disable_interrupt
+
+
+/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
+/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+static uint32_t __get_IPSR(void)
+{
+ __ASM("mrs r0, ipsr");
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+static uint32_t __get_APSR(void)
+{
+ __ASM("mrs r0, apsr");
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+static uint32_t __get_xPSR(void)
+{
+ __ASM("mrs r0, psr"); // assembler does not know "xpsr"
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+static uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+static void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+static uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+static void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+}
+
+
+/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
+/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+static __INLINE void __enable_fault_irq(void)
+{
+ __ASM ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+static __INLINE void __disable_fault_irq(void)
+{
+ __ASM ("cpsid f");
+}
+
+
+/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
+/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
+/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
+/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+static uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM("vmrs r0, fpscr");
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+static void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM("vmsr fpscr, r0");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H__ */
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmInstr.h b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
new file mode 100644
index 0000000..95ce06c
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
@@ -0,0 +1,775 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V2.01
+ * @date 06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H__
+#define __CORE_CMINSTR_H__
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern uint32_t __REV16(uint32_t value);
+#else /* (__ARMCC_VERSION >= 400677) */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern int32_t __REVSH(int32_t value);
+#else /* (__ARMCC_VERSION >= 400677) */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __CLREX(void);
+#else /* (__ARMCC_VERSION >= 400000) */
+#define __CLREX __clrex
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#include <intrinsics.h> /* IAR Intrinsics */
+
+#pragma diag_suppress=Pe940
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __no_operation
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+static __INLINE void __WFI(void)
+{
+ __ASM ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+static __INLINE void __WFE(void)
+{
+ __ASM ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+static __INLINE void __SEV(void)
+{
+ __ASM ("sev");
+}
+
+
+/* intrinsic void __ISB(void) (see intrinsics.h) */
+/* intrinsic void __DSB(void) (see intrinsics.h) */
+/* intrinsic void __DMB(void) (see intrinsics.h) */
+/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
+/* intrinsic __SSAT (see intrinsics.h) */
+/* intrinsic __USAT (see intrinsics.h) */
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static uint32_t __REV16(uint32_t value)
+{
+ __ASM("rev16 r0, r0");
+}
+
+
+/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+static uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+static uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
+static uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+static __INLINE void __CLREX(void)
+{
+ __ASM ("clrex");
+}
+
+/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#pragma diag_default=Pe940
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H__ */
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
new file mode 100644
index 0000000..e58767e
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/inc/system_LPC17xx.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC17xx.h
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC17xx Device Series
+ * @version V1.02
+ * @date 08. September 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC17xx_H */
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/core_cm3.c b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/core_cm3.c
new file mode 100644
index 0000000..fd052ce
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/core_cm3.c
@@ -0,0 +1,339 @@
+/**************************************************************************//**
+ * @file core_cm3.c
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version V2.00
+ * @date 13. September 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ########################## Core Instruction Access ######################### */
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __CLREX(void)
+{
+ clrex
+}
+#endif /* __ARMCC_VERSION */
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_IPSR(void)
+{
+ mrs r0, ipsr
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_APSR(void)
+{
+ mrs r0, apsr
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_xPSR(void)
+{
+ mrs r0, xpsr
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask Register.
+
+ \return Fault Mask value
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+/** \brief Set the Fault Mask
+
+ This function assigns the given value to the Fault Mask Register.
+
+ \param [in] faultMask Fault Mask value value to set
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
diff --git a/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/system_LPC17xx.c b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
new file mode 100644
index 0000000..b9d674a
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
@@ -0,0 +1,532 @@
+/**************************************************************************//**
+ * @file system_LPC17xx.c
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC17xx Device Series
+ * @version V1.08
+ * @date 12. May 2010
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC17xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS)
+// <o1.4> OSCRANGE: Main Oscillator Range Select
+// <0=> 1 MHz to 20 MHz
+// <1=> 15 MHz to 24 MHz
+// <e1.5> OSCEN: Main Oscillator Enable
+// </e>
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL)
+// <o2.0..1> CLKSRC: PLL Clock Source Selection
+// <0=> Internal RC oscillator
+// <1=> Main oscillator
+// <2=> RTC oscillator
+// </h>
+//
+// <e3> PLL0 Configuration (Main PLL)
+// <h> PLL0 Configuration Register (PLL0CFG)
+// <i> F_cco0 = (2 * M * F_in) / N
+// <i> F_in must be in the range of 32 kHz to 50 MHz
+// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+// <o4.0..14> MSEL: PLL Multiplier Selection
+// <6-32768><#-1>
+// <i> M Value
+// <o4.16..23> NSEL: PLL Divider Selection
+// <1-256><#-1>
+// <i> N Value
+// </h>
+// </e>
+//
+// <e5> PLL1 Configuration (USB PLL)
+// <h> PLL1 Configuration Register (PLL1CFG)
+// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
+// <i> F_cco1 = F_osc * M * 2 * P
+// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
+// <o6.0..4> MSEL: PLL Multiplier Selection
+// <1-32><#-1>
+// <i> M Value (for USB maximum value is 4)
+// <o6.5..6> PSEL: PLL Divider Selection
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// <i> P Value
+// </h>
+// </e>
+//
+// <h> CPU Clock Configuration Register (CCLKCFG)
+// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
+// <1-256><#-1>
+// </h>
+//
+// <h> USB Clock Configuration Register (USBCLKCFG)
+// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
+// <0-15>
+// <i> Divide is USBSEL + 1
+// </h>
+//
+// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
+// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// </h>
+//
+// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
+// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP)
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
+// <o11.3> PCUART0: UART 0 power/clock enable
+// <o11.4> PCUART1: UART 1 power/clock enable
+// <o11.6> PCPWM1: PWM 1 power/clock enable
+// <o11.7> PCI2C0: I2C interface 0 power/clock enable
+// <o11.8> PCSPI: SPI interface power/clock enable
+// <o11.9> PCRTC: RTC power/clock enable
+// <o11.10> PCSSP1: SSP interface 1 power/clock enable
+// <o11.12> PCAD: A/D converter power/clock enable
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable
+// <o11.15> PCGPIO: GPIOs power/clock enable
+// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
+// <o11.17> PCMC: Motor control PWM power/clock enable
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
+// <o11.19> PCI2C1: I2C interface 1 power/clock enable
+// <o11.21> PCSSP0: SSP interface 0 power/clock enable
+// <o11.22> PCTIM2: Timer 2 power/clock enable
+// <o11.23> PCTIM3: Timer 3 power/clock enable
+// <o11.24> PCUART2: UART 2 power/clock enable
+// <o11.25> PCUART3: UART 3 power/clock enable
+// <o11.26> PCI2C2: I2C interface 2 power/clock enable
+// <o11.27> PCI2S: I2S interface power/clock enable
+// <o11.29> PCGPDMA: GP DMA function power/clock enable
+// <o11.30> PCENET: Ethernet block power/clock enable
+// <o11.31> PCUSB: USB interface power/clock enable
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
+// <0=> CPU clock
+// <1=> Main oscillator
+// <2=> Internal RC oscillator
+// <3=> USB clock
+// <4=> RTC oscillator
+// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
+// <1-16><#-1>
+// <o12.8> CLKOUT_EN: CLKOUT enable control
+// </h>
+//
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00050063
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKCFG_Val 0x00000003
+#define USBCLKCFG_Val 0x00000000
+#define PCLKSEL0_Val 0x00000000
+#define PCLKSEL1_Val 0x00000000
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000000
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x00004000
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x00000030))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (PLL0_SETUP) /* if PLL0 is used */
+ #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
+ #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
+ #endif
+#endif
+
+#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
+ #error "CCLKCFG: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
+ #error "USBCLKCFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
+ #error "PCLKSEL0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
+ #error "PCLKSEL1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), 0x10100821))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
+ #error "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
+#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
+
+
+/* F_cco0 = (2 * M * F_in) / N */
+#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
+#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
+#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+ #endif
+ #else
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #endif
+ #endif
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = (IRC_OSC *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = (OSC_CLK *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = (RTC_CLK *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
+ }
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+
+#if (PLL0_SETUP)
+ LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
+
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
+#else
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+#endif
+
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
+#endif
+}
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.cproject b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.cproject
new file mode 100644
index 0000000..ffc8711
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.cproject
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+ <externalSettings/>
+ <extensions>
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+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+ <projectStorage><?xml version="1.0" encoding="UTF-8"?>
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+<infoList vendor="NXP">
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+<chip>
+<name>LPC1769</name>
+<family>LPC17xx</family>
+<vendor>NXP (formerly Philips)</vendor>
+<reset board="None" core="Real" sys="Real"/>
+<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
+<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
+<memory id="RAM" type="RAM"/>
+<memory id="Periph" is_volatile="true" type="Peripheral"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/>
+<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
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+</chip>
+<processor>
+<name gcc_name="cortex-m3">Cortex-M3</name>
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\ No newline at end of file
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.project b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.project
new file mode 100644
index 0000000..668034c
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>labo4.1_DMA_new</name>
+ <comment></comment>
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+ <project>CMSISv2p00_LPC17xx</project>
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+ <triggers>full,incremental,</triggers>
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+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.settings/language.settings.xml b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.settings/language.settings.xml
new file mode 100644
index 0000000..1723fa1
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/.settings/language.settings.xml
@@ -0,0 +1,25 @@
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+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1882102844081049178" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+ <configuration id="com.crt.advproject.config.exe.release.1841072117" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="1882102961924684189" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+</project>
\ No newline at end of file
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA.map b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA.map
new file mode 100644
index 0000000..1c663f4
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA.map
@@ -0,0 +1,467 @@
+Archive member included to satisfy reference by file (symbol)
+
+c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ ./src/dmatest.o (memset)
+c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest.o
+src2 0x400 ./src/dmatest.o
+src3 0x400 ./src/dmatest.o
+i 0x4 ./src/dmatest.o
+src1 0x1000 ./src/dmatest.o
+LLI 0x20 ./src/dmatest.o
+
+Discarded input sections
+
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/config_LPC1769.o
+ .text 0x00000000 0x0 ./src/config_LPC1769.o
+ .data 0x00000000 0x0 ./src/config_LPC1769.o
+ .bss 0x00000000 0x0 ./src/config_LPC1769.o
+ .group 0x00000000 0xc ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .group 0x00000000 0xc ./src/crp.o
+ .group 0x00000000 0xc ./src/crp.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .debug_macro 0x00000000 0xaa2 ./src/crp.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .text 0x00000000 0x0 ./src/dma.o
+ .data 0x00000000 0x0 ./src/dma.o
+ .bss 0x00000000 0x0 ./src/dma.o
+ .bss.DMAErrCount
+ 0x00000000 0x4 ./src/dma.o
+ .debug_macro 0x00000000 0xaa2 ./src/dma.o
+ .debug_macro 0x00000000 0x10 ./src/dma.o
+ .debug_macro 0x00000000 0x12e ./src/dma.o
+ .debug_macro 0x00000000 0x5b3 ./src/dma.o
+ .debug_macro 0x00000000 0x331 ./src/dma.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .text 0x00000000 0x0 ./src/dmatest.o
+ .data 0x00000000 0x0 ./src/dmatest.o
+ .bss 0x00000000 0x0 ./src/dmatest.o
+ .debug_macro 0x00000000 0xaa2 ./src/dmatest.o
+ .debug_macro 0x00000000 0x10 ./src/dmatest.o
+ .debug_macro 0x00000000 0x12e ./src/dmatest.o
+ .debug_macro 0x00000000 0x5b3 ./src/dmatest.o
+ .debug_macro 0x00000000 0x52 ./src/dmatest.o
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x34 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/config_LPC1769.o
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma.o
+LOAD ./src/dmatest.o
+START GROUP
+LOAD c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a
+LOAD c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a
+LOAD c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libgcc.a
+END GROUP
+ 0x00000000 __base_MFlash512 = 0x0
+ 0x00000000 __base_Flash = 0x0
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x00080000 __top_Flash = 0x80000
+ 0x10000000 __base_RamLoc32 = 0x10000000
+ 0x10000000 __base_RAM = 0x10000000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x10008000 __top_RAM = 0x10008000
+ 0x2007c000 __base_RamAHB32 = 0x2007c000
+ 0x2007c000 __base_RAM2 = 0x2007c000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+ 0x20084000 __top_RAM2 = 0x20084000
+
+.text 0x00000000 0x550
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x550 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x550 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x2828 SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x74 ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 PWM1_IRQHandler
+ 0x00000106 I2C1_IRQHandler
+ 0x00000106 EINT2_IRQHandler
+ 0x00000106 UART1_IRQHandler
+ 0x00000106 EINT3_IRQHandler
+ 0x00000106 CANActivity_IRQHandler
+ 0x00000106 TIMER3_IRQHandler
+ 0x00000106 UART0_IRQHandler
+ 0x00000106 MCPWM_IRQHandler
+ 0x00000106 I2C0_IRQHandler
+ 0x00000106 IntDefaultHandler
+ 0x00000106 RIT_IRQHandler
+ 0x00000106 CAN_IRQHandler
+ 0x00000106 PLL1_IRQHandler
+ 0x00000106 SSP0_IRQHandler
+ 0x00000106 I2S_IRQHandler
+ 0x00000106 I2C2_IRQHandler
+ 0x00000106 RTC_IRQHandler
+ 0x00000106 TIMER0_IRQHandler
+ 0x00000106 SPI_IRQHandler
+ 0x00000106 UART3_IRQHandler
+ 0x00000106 EINT1_IRQHandler
+ 0x00000106 TIMER1_IRQHandler
+ 0x00000106 UART2_IRQHandler
+ 0x00000106 ADC_IRQHandler
+ 0x00000106 SSP1_IRQHandler
+ 0x00000106 USB_IRQHandler
+ 0x00000106 BOD_IRQHandler
+ 0x00000106 USBActivity_IRQHandler
+ 0x00000106 WDT_IRQHandler
+ 0x00000106 PLL0_IRQHandler
+ 0x00000106 QEI_IRQHandler
+ 0x00000106 EINT0_IRQHandler
+ 0x00000106 TIMER2_IRQHandler
+ 0x00000106 ENET_IRQHandler
+ 0x00000108 data_init
+ 0x0000011a bss_init
+ 0x0000012a ResetISR
+ 0x000002fc . = 0x2fc
+ *fill* 0x00000168 0x194 ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__ = .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__ = .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.init 0x00000300 0x38 ./src/config_LPC1769.o
+ 0x00000300 init
+ .text.DMA_IRQHandler
+ 0x00000338 0xc ./src/dma.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x00000344 0x28 ./src/dma.o
+ 0x00000344 DMA_Init
+ .text.single_copy
+ 0x0000036c 0x68 ./src/dmatest.o
+ 0x0000036c single_copy
+ .text.LLI_copy
+ 0x000003d4 0xcc ./src/dmatest.o
+ 0x000003d4 LLI_copy
+ .text.check_res
+ 0x000004a0 0x3c ./src/dmatest.o
+ 0x000004a0 check_res
+ .text.main 0x000004dc 0x38 ./src/dmatest.o
+ 0x000004dc main
+ .text.memset 0x00000514 0x4 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ 0x00000514 memset
+ .text.__weak_main
+ 0x00000518 0x4 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ 0x00000518 __weak_main
+ 0x00000518 __main
+ .text.__aeabi_memset_lowlevel
+ 0x0000051c 0x32 c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ 0x0000051c __aeabi_lowlevel_memset
+ *(.rodata .rodata.* .constdata .constdata.*)
+ 0x00000550 . = ALIGN (0x4)
+ *fill* 0x0000054e 0x2 ff
+
+.glue_7 0x00000550 0x0
+ .glue_7 0x00000550 0x0 linker stubs
+
+.glue_7t 0x00000550 0x0
+ .glue_7t 0x00000550 0x0 linker stubs
+
+.vfp11_veneer 0x00000550 0x0
+ .vfp11_veneer 0x00000550 0x0 linker stubs
+
+.v4_bx 0x00000550 0x0
+ .v4_bx 0x00000550 0x0 linker stubs
+
+.iplt 0x00000550 0x0
+ .iplt 0x00000550 0x0 ./src/config_LPC1769.o
+
+.rel.dyn 0x00000550 0x0
+ .rel.iplt 0x00000550 0x0 ./src/config_LPC1769.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM.exidx 0x00000550 0x0
+ 0x00000550 __exidx_start = .
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x00000550 __exidx_end = .
+ 0x00000550 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x00000550
+ FILL mask 0xff
+ [!provide] PROVIDE (__start_data_RAM2 = .)
+ [!provide] PROVIDE (__start_data_RamAHB32 = .)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ 0x2007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_data_RAM2 = .)
+ [!provide] PROVIDE (__end_data_RamAHB32 = .)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ 0x10000000 _start_uninit_RESERVED = .
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x00000550
+ FILL mask 0xff
+ 0x10000000 _data = .
+ [!provide] PROVIDE (__start_data_RAM = .)
+ [!provide] PROVIDE (__start_data_RamLoc32 = .)
+ *(vtable)
+ *(.ramfunc*)
+ *(CodeQuickAccess)
+ *(DataQuickAccess)
+ *(RamFunction)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+ [!provide] PROVIDE (__end_data_RAM = .)
+ [!provide] PROVIDE (__end_data_RamLoc32 = .)
+
+.igot.plt 0x10000000 0x0 load address 0x00000550
+ .igot.plt 0x10000000 0x0 ./src/config_LPC1769.o
+
+.bss_RAM2 0x2007c000 0x0
+ [!provide] PROVIDE (__start_bss_RAM2 = .)
+ [!provide] PROVIDE (__start_bss_RamAHB32 = .)
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ 0x2007c000 . = ALIGN ((. != 0x0)?0x4:0x1)
+ [!provide] PROVIDE (__end_bss_RAM2 = .)
+ [!provide] PROVIDE (__end_bss_RamAHB32 = .)
+
+.bss 0x10000000 0x2828
+ 0x10000000 _bss = .
+ [!provide] PROVIDE (__start_bss_RAM = .)
+ [!provide] PROVIDE (__start_bss_RamLoc32 = .)
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma.o
+ 0x10000000 DMATCCount
+ *(COMMON)
+ COMMON 0x10000004 0x2824 ./src/dmatest.o
+ 0x10000004 dest
+ 0x10001004 src2
+ 0x10001404 src3
+ 0x10001804 i
+ 0x10001808 src1
+ 0x10002808 LLI
+ 0x10002828 . = ALIGN (0x4)
+ 0x10002828 _ebss = .
+ [!provide] PROVIDE (__end_bss_RAM = .)
+ [!provide] PROVIDE (__end_bss_RamLoc32 = .)
+ [!provide] PROVIDE (end = .)
+
+.noinit_RAM2 0x2007c000 0x0
+ [!provide] PROVIDE (__start_noinit_RAM2 = .)
+ [!provide] PROVIDE (__start_noinit_RamAHB32 = .)
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ 0x2007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_noinit_RAM2 = .)
+ [!provide] PROVIDE (__end_noinit_RamAHB32 = .)
+
+.noinit 0x10002828 0x0
+ 0x10002828 _noinit = .
+ [!provide] PROVIDE (__start_noinit_RAM = .)
+ [!provide] PROVIDE (__start_noinit_RamLoc32 = .)
+ *(.noinit*)
+ 0x10002828 . = ALIGN (0x4)
+ 0x10002828 _end_noinit = .
+ [!provide] PROVIDE (__end_noinit_RAM = .)
+ [!provide] PROVIDE (__end_noinit_RamLoc32 = .)
+ [!provide] PROVIDE (_pvHeapStart = DEFINED (__user_heap_base)?__user_heap_base:.)
+ 0x10008000 PROVIDE (_vStackTop = DEFINED (__user_stack_top)?__user_stack_top:(__top_RamLoc32 - 0x0))
+ [!provide] PROVIDE (__valid_user_code_checksum = (0x0 - ((((((_vStackTop + (ResetISR + 0x1)) + (NMI_Handler + 0x1)) + (HardFault_Handler + 0x1)) + (DEFINED (MemManage_Handler)?MemManage_Handler:0x0 + 0x1)) + (DEFINED (BusFault_Handler)?BusFault_Handler:0x0 + 0x1)) + (DEFINED (UsageFault_Handler)?UsageFault_Handler:0x0 + 0x1))))
+ 0x00000000 _image_start = LOADADDR (.text)
+ 0x00000550 _image_end = (LOADADDR (.data) + SIZEOF (.data))
+ 0x00000550 _image_size = (_image_end - _image_start)
+OUTPUT(labo4.1_DMA.axf elf32-littlearm)
+LOAD linker stubs
+
+.debug_info 0x00000000 0x731
+ .debug_info 0x00000000 0xba ./src/config_LPC1769.o
+ .debug_info 0x000000ba 0x2e3 ./src/cr_startup_lpc176x.o
+ .debug_info 0x0000039d 0x40 ./src/crp.o
+ .debug_info 0x000003dd 0x148 ./src/dma.o
+ .debug_info 0x00000525 0x20c ./src/dmatest.o
+
+.debug_abbrev 0x00000000 0x44b
+ .debug_abbrev 0x00000000 0x8b ./src/config_LPC1769.o
+ .debug_abbrev 0x0000008b 0x156 ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x000001e1 0x38 ./src/crp.o
+ .debug_abbrev 0x00000219 0xf2 ./src/dma.o
+ .debug_abbrev 0x0000030b 0x140 ./src/dmatest.o
+
+.debug_aranges 0x00000000 0x118
+ .debug_aranges
+ 0x00000000 0x20 ./src/config_LPC1769.o
+ .debug_aranges
+ 0x00000020 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x000000a0 0x18 ./src/crp.o
+ .debug_aranges
+ 0x000000b8 0x28 ./src/dma.o
+ .debug_aranges
+ 0x000000e0 0x38 ./src/dmatest.o
+
+.debug_ranges 0x00000000 0xc0
+ .debug_ranges 0x00000000 0x10 ./src/config_LPC1769.o
+ .debug_ranges 0x00000010 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000080 0x18 ./src/dma.o
+ .debug_ranges 0x00000098 0x28 ./src/dmatest.o
+
+.debug_macro 0x00000000 0x2461
+ .debug_macro 0x00000000 0x4b ./src/config_LPC1769.o
+ .debug_macro 0x0000004b 0xaa2 ./src/config_LPC1769.o
+ .debug_macro 0x00000aed 0x10 ./src/config_LPC1769.o
+ .debug_macro 0x00000afd 0x12e ./src/config_LPC1769.o
+ .debug_macro 0x00000c2b 0x5b3 ./src/config_LPC1769.o
+ .debug_macro 0x000011de 0x331 ./src/config_LPC1769.o
+ .debug_macro 0x0000150f 0x1d ./src/cr_startup_lpc176x.o
+ .debug_macro 0x0000152c 0xaa8 ./src/cr_startup_lpc176x.o
+ .debug_macro 0x00001fd4 0x1a ./src/crp.o
+ .debug_macro 0x00001fee 0x34 ./src/crp.o
+ .debug_macro 0x00002022 0x54 ./src/dma.o
+ .debug_macro 0x00002076 0x52 ./src/dma.o
+ .debug_macro 0x000020c8 0x62 ./src/dmatest.o
+ .debug_macro 0x0000212a 0x337 ./src/dmatest.o
+
+.debug_line 0x00000000 0x997
+ .debug_line 0x00000000 0x1b6 ./src/config_LPC1769.o
+ .debug_line 0x000001b6 0x26f ./src/cr_startup_lpc176x.o
+ .debug_line 0x00000425 0xb1 ./src/crp.o
+ .debug_line 0x000004d6 0x1a3 ./src/dma.o
+ .debug_line 0x00000679 0x31e ./src/dmatest.o
+
+.debug_str 0x00000000 0x638e
+ .debug_str 0x00000000 0x5db0 ./src/config_LPC1769.o
+ 0x5e2e (size before relaxing)
+ .debug_str 0x00005db0 0x2c2 ./src/cr_startup_lpc176x.o
+ 0x2f8a (size before relaxing)
+ .debug_str 0x00006072 0xe9 ./src/crp.o
+ 0x2e80 (size before relaxing)
+ .debug_str 0x0000615b 0x192 ./src/dma.o
+ 0x5fa3 (size before relaxing)
+ .debug_str 0x000062ed 0xa1 ./src/dmatest.o
+ 0x6018 (size before relaxing)
+
+.comment 0x00000000 0x4c
+ .comment 0x00000000 0x4c ./src/config_LPC1769.o
+ 0x4d (size before relaxing)
+ .comment 0x0000004c 0x4d ./src/cr_startup_lpc176x.o
+ .comment 0x0000004c 0x4d ./src/crp.o
+ .comment 0x0000004c 0x4d ./src/dma.o
+ .comment 0x0000004c 0x4d ./src/dmatest.o
+ .comment 0x0000004c 0x4d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .comment 0x0000004c 0x4d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x2b
+ .ARM.attributes
+ 0x00000000 0x2d ./src/config_LPC1769.o
+ .ARM.attributes
+ 0x0000002d 0x2d ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x0000005a 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x0000008d 0x2d ./src/dma.o
+ .ARM.attributes
+ 0x000000ba 0x2d ./src/dmatest.o
+ .ARM.attributes
+ 0x000000e7 0x2d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000114 0x2d c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000141 0x1b c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x208
+ .debug_frame 0x00000000 0x30 ./src/config_LPC1769.o
+ .debug_frame 0x00000030 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x00000124 0x58 ./src/dma.o
+ .debug_frame 0x0000017c 0x8c ./src/dmatest.o
+
+.debug_loc 0x00000000 0x16a
+ .debug_loc 0x00000000 0x16a ./src/cr_startup_lpc176x.o
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA_new.axf
new file mode 100644
index 0000000000000000000000000000000000000000..6e01b3f68d3e4046082f514f68a6b0740f71c3cd
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literal 0
HcmV?d00001
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA_new.map b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA_new.map
new file mode 100644
index 0000000..5ba75df
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4.1_DMA_new.map
@@ -0,0 +1,450 @@
+Archive member included to satisfy reference by file (symbol)
+
+c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ ./src/dmatest.o (memset)
+c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Discarded input sections
+
+ .group 0x00000000 0xc ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .group 0x00000000 0xc ./src/crp.o
+ .group 0x00000000 0xc ./src/crp.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .group 0x00000000 0xc ./src/dma.o
+ .text 0x00000000 0x0 ./src/dma.o
+ .data 0x00000000 0x0 ./src/dma.o
+ .bss 0x00000000 0x0 ./src/dma.o
+ .bss.DMAErrCount
+ 0x00000000 0x4 ./src/dma.o
+ .debug_macro 0x00000000 0xa72 ./src/dma.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .group 0x00000000 0xc ./src/dmatest.o
+ .text 0x00000000 0x0 ./src/dmatest.o
+ .data 0x00000000 0x0 ./src/dmatest.o
+ .bss 0x00000000 0x0 ./src/dmatest.o
+ .debug_macro 0x00000000 0xa72 ./src/dmatest.o
+ .debug_macro 0x00000000 0x10 ./src/dmatest.o
+ .debug_macro 0x00000000 0x12e ./src/dmatest.o
+ .debug_macro 0x00000000 0x5b3 ./src/dmatest.o
+ .debug_macro 0x00000000 0x52 ./src/dmatest.o
+ .debug_macro 0x00000000 0x1c ./src/dmatest.o
+ .debug_macro 0x00000000 0x2e ./src/dmatest.o
+ .debug_macro 0x00000000 0x18 ./src/dmatest.o
+ .debug_macro 0x00000000 0x7af ./src/dmatest.o
+ .debug_macro 0x00000000 0x2c7 ./src/dmatest.o
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x34 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma.o
+LOAD ./src/dmatest.o
+LOAD C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a
+LOAD c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a
+LOAD c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libgcc.a
+END GROUP
+ 0x00000000 __base_MFlash512 = 0x0
+ 0x00000000 __base_Flash = 0x0
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x00080000 __top_Flash = 0x80000
+ 0x10000000 __base_RamLoc32 = 0x10000000
+ 0x10000000 __base_RAM = 0x10000000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x10008000 __top_RAM = 0x10008000
+ 0x2007c000 __base_RamAHB32 = 0x2007c000
+ 0x2007c000 __base_RAM2 = 0x2007c000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+ 0x20084000 __top_RAM2 = 0x20084000
+
+.text 0x00000000 0x518
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x518 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x518 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x2828 SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x74 ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 PWM1_IRQHandler
+ 0x00000106 I2C1_IRQHandler
+ 0x00000106 EINT2_IRQHandler
+ 0x00000106 UART1_IRQHandler
+ 0x00000106 EINT3_IRQHandler
+ 0x00000106 CANActivity_IRQHandler
+ 0x00000106 TIMER3_IRQHandler
+ 0x00000106 UART0_IRQHandler
+ 0x00000106 MCPWM_IRQHandler
+ 0x00000106 I2C0_IRQHandler
+ 0x00000106 IntDefaultHandler
+ 0x00000106 RIT_IRQHandler
+ 0x00000106 CAN_IRQHandler
+ 0x00000106 PLL1_IRQHandler
+ 0x00000106 SSP0_IRQHandler
+ 0x00000106 I2S_IRQHandler
+ 0x00000106 I2C2_IRQHandler
+ 0x00000106 RTC_IRQHandler
+ 0x00000106 TIMER0_IRQHandler
+ 0x00000106 SPI_IRQHandler
+ 0x00000106 UART3_IRQHandler
+ 0x00000106 EINT1_IRQHandler
+ 0x00000106 TIMER1_IRQHandler
+ 0x00000106 UART2_IRQHandler
+ 0x00000106 ADC_IRQHandler
+ 0x00000106 SSP1_IRQHandler
+ 0x00000106 USB_IRQHandler
+ 0x00000106 BOD_IRQHandler
+ 0x00000106 USBActivity_IRQHandler
+ 0x00000106 WDT_IRQHandler
+ 0x00000106 PLL0_IRQHandler
+ 0x00000106 QEI_IRQHandler
+ 0x00000106 EINT0_IRQHandler
+ 0x00000106 TIMER2_IRQHandler
+ 0x00000106 ENET_IRQHandler
+ 0x00000108 data_init
+ 0x0000011a bss_init
+ 0x0000012a ResetISR
+ 0x000002fc . = 0x2fc
+ *fill* 0x00000168 0x194 ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__ = .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__ = .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.DMA_IRQHandler
+ 0x00000300 0xc ./src/dma.o
+ 0x00000300 DMA_IRQHandler
+ .text.DMA_Init
+ 0x0000030c 0x2c ./src/dma.o
+ 0x0000030c DMA_Init
+ .text.single_copy
+ 0x00000338 0x68 ./src/dmatest.o
+ 0x00000338 single_copy
+ .text.LLI_copy
+ 0x000003a0 0xcc ./src/dmatest.o
+ 0x000003a0 LLI_copy
+ .text.check_res
+ 0x0000046c 0x3c ./src/dmatest.o
+ 0x0000046c check_res
+ .text.main 0x000004a8 0x34 ./src/dmatest.o
+ 0x000004a8 main
+ .text.memset 0x000004dc 0x4 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ 0x000004dc memset
+ .text.__weak_main
+ 0x000004e0 0x4 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ 0x000004e0 __weak_main
+ 0x000004e0 __main
+ .text.__aeabi_memset_lowlevel
+ 0x000004e4 0x32 c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+ 0x000004e4 __aeabi_lowlevel_memset
+ *(.rodata .rodata.* .constdata .constdata.*)
+ 0x00000518 . = ALIGN (0x4)
+ *fill* 0x00000516 0x2 ff
+
+.glue_7 0x00000518 0x0
+ .glue_7 0x00000518 0x0 linker stubs
+
+.glue_7t 0x00000518 0x0
+ .glue_7t 0x00000518 0x0 linker stubs
+
+.vfp11_veneer 0x00000518 0x0
+ .vfp11_veneer 0x00000518 0x0 linker stubs
+
+.v4_bx 0x00000518 0x0
+ .v4_bx 0x00000518 0x0 linker stubs
+
+.iplt 0x00000518 0x0
+ .iplt 0x00000518 0x0 ./src/cr_startup_lpc176x.o
+
+.rel.dyn 0x00000518 0x0
+ .rel.iplt 0x00000518 0x0 ./src/cr_startup_lpc176x.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM.exidx 0x00000518 0x0
+ 0x00000518 __exidx_start = .
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x00000518 __exidx_end = .
+ 0x00000518 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x00000518
+ FILL mask 0xff
+ [!provide] PROVIDE (__start_data_RAM2 = .)
+ [!provide] PROVIDE (__start_data_RamAHB32 = .)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ 0x2007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_data_RAM2 = .)
+ [!provide] PROVIDE (__end_data_RamAHB32 = .)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ 0x10000000 _start_uninit_RESERVED = .
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x00000518
+ FILL mask 0xff
+ 0x10000000 _data = .
+ [!provide] PROVIDE (__start_data_RAM = .)
+ [!provide] PROVIDE (__start_data_RamLoc32 = .)
+ *(vtable)
+ *(.ramfunc*)
+ *(CodeQuickAccess)
+ *(DataQuickAccess)
+ *(RamFunction)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+ [!provide] PROVIDE (__end_data_RAM = .)
+ [!provide] PROVIDE (__end_data_RamLoc32 = .)
+
+.igot.plt 0x10000000 0x0 load address 0x00000518
+ .igot.plt 0x10000000 0x0 ./src/cr_startup_lpc176x.o
+
+.bss_RAM2 0x2007c000 0x0
+ [!provide] PROVIDE (__start_bss_RAM2 = .)
+ [!provide] PROVIDE (__start_bss_RamAHB32 = .)
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ 0x2007c000 . = ALIGN ((. != 0x0)?0x4:0x1)
+ [!provide] PROVIDE (__end_bss_RAM2 = .)
+ [!provide] PROVIDE (__end_bss_RamAHB32 = .)
+
+.bss 0x10000000 0x2828
+ 0x10000000 _bss = .
+ [!provide] PROVIDE (__start_bss_RAM = .)
+ [!provide] PROVIDE (__start_bss_RamLoc32 = .)
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma.o
+ 0x10000000 DMATCCount
+ .bss.LLI 0x10000004 0x20 ./src/dmatest.o
+ 0x10000004 LLI
+ .bss.src3 0x10000024 0x400 ./src/dmatest.o
+ 0x10000024 src3
+ .bss.i 0x10000424 0x4 ./src/dmatest.o
+ 0x10000424 i
+ .bss.src1 0x10000428 0x1000 ./src/dmatest.o
+ 0x10000428 src1
+ .bss.dest 0x10001428 0x1000 ./src/dmatest.o
+ 0x10001428 dest
+ .bss.src2 0x10002428 0x400 ./src/dmatest.o
+ 0x10002428 src2
+ *(COMMON)
+ 0x10002828 . = ALIGN (0x4)
+ 0x10002828 _ebss = .
+ [!provide] PROVIDE (__end_bss_RAM = .)
+ [!provide] PROVIDE (__end_bss_RamLoc32 = .)
+ [!provide] PROVIDE (end = .)
+
+.noinit_RAM2 0x2007c000 0x0
+ [!provide] PROVIDE (__start_noinit_RAM2 = .)
+ [!provide] PROVIDE (__start_noinit_RamAHB32 = .)
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ 0x2007c000 . = ALIGN (0x4)
+ [!provide] PROVIDE (__end_noinit_RAM2 = .)
+ [!provide] PROVIDE (__end_noinit_RamAHB32 = .)
+
+.noinit 0x10002828 0x0
+ 0x10002828 _noinit = .
+ [!provide] PROVIDE (__start_noinit_RAM = .)
+ [!provide] PROVIDE (__start_noinit_RamLoc32 = .)
+ *(.noinit*)
+ 0x10002828 . = ALIGN (0x4)
+ 0x10002828 _end_noinit = .
+ [!provide] PROVIDE (__end_noinit_RAM = .)
+ [!provide] PROVIDE (__end_noinit_RamLoc32 = .)
+ [!provide] PROVIDE (_pvHeapStart = DEFINED (__user_heap_base)?__user_heap_base:.)
+ 0x10008000 PROVIDE (_vStackTop = DEFINED (__user_stack_top)?__user_stack_top:(__top_RamLoc32 - 0x0))
+ [!provide] PROVIDE (__valid_user_code_checksum = (0x0 - ((((((_vStackTop + (ResetISR + 0x1)) + (NMI_Handler + 0x1)) + (HardFault_Handler + 0x1)) + (DEFINED (MemManage_Handler)?MemManage_Handler:0x0 + 0x1)) + (DEFINED (BusFault_Handler)?BusFault_Handler:0x0 + 0x1)) + (DEFINED (UsageFault_Handler)?UsageFault_Handler:0x0 + 0x1))))
+ 0x00000000 _image_start = LOADADDR (.text)
+ 0x00000518 _image_end = (LOADADDR (.data) + SIZEOF (.data))
+ 0x00000518 _image_size = (_image_end - _image_start)
+OUTPUT(labo4.1_DMA_new.axf elf32-littlearm)
+LOAD linker stubs
+
+.debug_info 0x00000000 0x879
+ .debug_info 0x00000000 0x2f0 ./src/cr_startup_lpc176x.o
+ .debug_info 0x000002f0 0x40 ./src/crp.o
+ .debug_info 0x00000330 0x375 ./src/dma.o
+ .debug_info 0x000006a5 0x1d4 ./src/dmatest.o
+
+.debug_abbrev 0x00000000 0x3c3
+ .debug_abbrev 0x00000000 0x161 ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x00000161 0x38 ./src/crp.o
+ .debug_abbrev 0x00000199 0x112 ./src/dma.o
+ .debug_abbrev 0x000002ab 0x118 ./src/dmatest.o
+
+.debug_loc 0x00000000 0x16a
+ .debug_loc 0x00000000 0x16a ./src/cr_startup_lpc176x.o
+
+.debug_aranges 0x00000000 0xf8
+ .debug_aranges
+ 0x00000000 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x00000080 0x18 ./src/crp.o
+ .debug_aranges
+ 0x00000098 0x28 ./src/dma.o
+ .debug_aranges
+ 0x000000c0 0x38 ./src/dmatest.o
+
+.debug_ranges 0x00000000 0xb0
+ .debug_ranges 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000070 0x18 ./src/dma.o
+ .debug_ranges 0x00000088 0x28 ./src/dmatest.o
+
+.debug_macro 0x00000000 0x2880
+ .debug_macro 0x00000000 0x1d ./src/cr_startup_lpc176x.o
+ .debug_macro 0x0000001d 0xa78 ./src/cr_startup_lpc176x.o
+ .debug_macro 0x00000a95 0x1a ./src/crp.o
+ .debug_macro 0x00000aaf 0xa72 ./src/crp.o
+ .debug_macro 0x00001521 0x34 ./src/crp.o
+ .debug_macro 0x00001555 0x7e ./src/dma.o
+ .debug_macro 0x000015d3 0x1c ./src/dma.o
+ .debug_macro 0x000015ef 0x2e ./src/dma.o
+ .debug_macro 0x0000161d 0x10 ./src/dma.o
+ .debug_macro 0x0000162d 0x12e ./src/dma.o
+ .debug_macro 0x0000175b 0x5b3 ./src/dma.o
+ .debug_macro 0x00001d0e 0x18 ./src/dma.o
+ .debug_macro 0x00001d26 0x7af ./src/dma.o
+ .debug_macro 0x000024d5 0x2c7 ./src/dma.o
+ .debug_macro 0x0000279c 0x52 ./src/dma.o
+ .debug_macro 0x000027ee 0x92 ./src/dmatest.o
+
+.debug_line 0x00000000 0x910
+ .debug_line 0x00000000 0x26f ./src/cr_startup_lpc176x.o
+ .debug_line 0x0000026f 0xb1 ./src/crp.o
+ .debug_line 0x00000320 0x23b ./src/dma.o
+ .debug_line 0x0000055b 0x3b5 ./src/dmatest.o
+
+.debug_str 0x00000000 0x8af0
+ .debug_str 0x00000000 0x2e99 ./src/cr_startup_lpc176x.o
+ 0x2eac (size before relaxing)
+ .debug_str 0x00002e99 0x1bf ./src/crp.o
+ 0x2db6 (size before relaxing)
+ .debug_str 0x00003058 0x59f7 ./src/dma.o
+ 0x8730 (size before relaxing)
+ .debug_str 0x00008a4f 0xa1 ./src/dmatest.o
+ 0x865b (size before relaxing)
+
+.comment 0x00000000 0x49
+ .comment 0x00000000 0x49 ./src/cr_startup_lpc176x.o
+ 0x4a (size before relaxing)
+ .comment 0x00000049 0x4a ./src/crp.o
+ .comment 0x00000049 0x4a ./src/dma.o
+ .comment 0x00000049 0x4a ./src/dmatest.o
+ .comment 0x00000049 0x4a c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .comment 0x00000049 0x4a c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x2b
+ .ARM.attributes
+ 0x00000000 0x2d ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x0000002d 0x2d ./src/crp.o
+ .ARM.attributes
+ 0x0000005a 0x2d ./src/dma.o
+ .ARM.attributes
+ 0x00000087 0x2d ./src/dmatest.o
+ .ARM.attributes
+ 0x000000b4 0x2d c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x000000e1 0x2d c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x0000010e 0x1b c:/nxp/mcuxpressoide_11.7.1_9221/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.7.1.202301190959/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7-m/nofp\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x1d8
+ .debug_frame 0x00000000 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x000000f4 0x58 ./src/dma.o
+ .debug_frame 0x0000014c 0x8c ./src/dmatest.o
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld
new file mode 100644
index 0000000..60863d7
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug.ld
@@ -0,0 +1,203 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2022
+ * Generated linker script file for LPC1769
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.3.0 [Build 5222] [2021-01-11] on 23 nov. 2022 16:02:28
+ */
+
+INCLUDE "labo4_1_DMA_Debug_library.ld"
+INCLUDE "labo4_1_DMA_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ /* Code Read Protection data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protection */
+ } > MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+
+ .ARM.exidx : ALIGN(4)
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > MFlash512
+
+ _etext = .;
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ PROVIDE(__start_data_RamAHB32 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ PROVIDE(__end_data_RamAHB32 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32 AT> RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ PROVIDE(__start_data_RAM = .) ;
+ PROVIDE(__start_data_RamLoc32 = .) ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ PROVIDE(__end_data_RAM = .) ;
+ PROVIDE(__end_data_RamLoc32 = .) ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ PROVIDE(__start_bss_RamAHB32 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ PROVIDE(__end_bss_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM = .) ;
+ PROVIDE(__start_bss_RamLoc32 = .) ;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(__end_bss_RAM = .) ;
+ PROVIDE(__end_bss_RamLoc32 = .) ;
+ PROVIDE(end = .);
+ } > RamLoc32 AT> RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM2 = .) ;
+ PROVIDE(__start_noinit_RamAHB32 = .) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM2 = .) ;
+ PROVIDE(__end_noinit_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM = .) ;
+ PROVIDE(__start_noinit_RamLoc32 = .) ;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM = .) ;
+ PROVIDE(__end_noinit_RamLoc32 = .) ;
+ } > RamLoc32 AT> RamLoc32
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld
new file mode 100644
index 0000000..6e4a567
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_library.ld
@@ -0,0 +1,16 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2022
+ * Generated linker script file for LPC1769
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.3.0 [Build 5222] [2021-01-11] on 23 nov. 2022 16:02:28
+ */
+
+GROUP (
+ "libcr_c.a"
+ "libcr_eabihelpers.a"
+ "libgcc.a"
+)
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld
new file mode 100644
index 0000000..ff5f730
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_Debug_memory.ld
@@ -0,0 +1,32 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2022
+ * Generated linker script file for LPC1769
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.3.0 [Build 5222] [2021-01-11] on 23 nov. 2022 16:02:28
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld
new file mode 100644
index 0000000..dadbdaa
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug.ld
@@ -0,0 +1,201 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2023
+ * Generated linker script file for LPC1769
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.7.1 [Build 9221] [2023-03-28] on 6 nov. 2023 Ã 20:24:23
+ */
+
+INCLUDE "labo4_1_DMA_new_Debug_library.ld"
+INCLUDE "labo4_1_DMA_new_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ /* Code Read Protection data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protection */
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+
+ .ARM.exidx : ALIGN(4)
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > MFlash512
+
+ _etext = .;
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ PROVIDE(__start_data_RamAHB32 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2)
+ *(.data.$RamAHB32)
+ *(.data.$RAM2.*)
+ *(.data.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ PROVIDE(__end_data_RamAHB32 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32 AT> RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ PROVIDE(__start_data_RAM = .) ;
+ PROVIDE(__start_data_RamLoc32 = .) ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ PROVIDE(__end_data_RAM = .) ;
+ PROVIDE(__end_data_RamLoc32 = .) ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ PROVIDE(__start_bss_RamAHB32 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamAHB32.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ PROVIDE(__end_bss_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM = .) ;
+ PROVIDE(__start_bss_RamLoc32 = .) ;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(__end_bss_RAM = .) ;
+ PROVIDE(__end_bss_RamLoc32 = .) ;
+ PROVIDE(end = .);
+ } > RamLoc32 AT> RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM2 = .) ;
+ PROVIDE(__start_noinit_RamAHB32 = .) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM2 = .) ;
+ PROVIDE(__end_noinit_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM = .) ;
+ PROVIDE(__start_noinit_RamLoc32 = .) ;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM = .) ;
+ PROVIDE(__end_noinit_RamLoc32 = .) ;
+ } > RamLoc32 AT> RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld
new file mode 100644
index 0000000..7b71b4e
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_library.ld
@@ -0,0 +1,16 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2023
+ * Generated linker script file for LPC1769
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.7.1 [Build 9221] [2023-03-28] on 6 nov. 2023 Ã 20:24:23
+ */
+
+GROUP (
+ "libcr_c.a"
+ "libcr_eabihelpers.a"
+ "libgcc.a"
+)
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld
new file mode 100644
index 0000000..ca05545
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo4_1_DMA_new_Debug_memory.ld
@@ -0,0 +1,32 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2023
+ * Generated linker script file for LPC1769
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.7.1 [Build 9221] [2023-03-28] on 6 nov. 2023 Ã 20:24:23
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA.map b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA.map
new file mode 100644
index 0000000..d3cae22
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA.map
@@ -0,0 +1,440 @@
+Archive member included because of file (symbol)
+
+c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ ./src/dmatest_corrige.o (memset)
+c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest_corrige.o
+delta_t_ref 0x4 ./src/dmatest_corrige.o
+src2 0x400 ./src/dmatest_corrige.o
+t_start 0x4 ./src/dmatest_corrige.o
+src3 0x400 ./src/dmatest_corrige.o
+i 0x4 ./src/dmatest_corrige.o
+delta_t 0x4 ./src/dmatest_corrige.o
+src1 0x1000 ./src/dmatest_corrige.o
+LLI 0x20 ./src/dmatest_corrige.o
+
+Discarded input sections
+
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/config_LPC1769.o
+ .text 0x00000000 0x0 ./src/config_LPC1769.o
+ .data 0x00000000 0x0 ./src/config_LPC1769.o
+ .bss 0x00000000 0x0 ./src/config_LPC1769.o
+ .group 0x00000000 0x8 ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .group 0x00000000 0x8 ./src/crp.o
+ .group 0x00000000 0x8 ./src/crp.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .debug_macro 0x00000000 0x86e ./src/crp.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dma_corrige.o
+ .text 0x00000000 0x0 ./src/dma_corrige.o
+ .data 0x00000000 0x0 ./src/dma_corrige.o
+ .bss 0x00000000 0x0 ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x86e ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x10 ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x12d ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x5b2 ./src/dma_corrige.o
+ .debug_macro 0x00000000 0x331 ./src/dma_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .group 0x00000000 0x8 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 ./src/dmatest_corrige.o
+ .data 0x00000000 0x0 ./src/dmatest_corrige.o
+ .bss 0x00000000 0x0 ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x86e ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x10 ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x12d ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x5b2 ./src/dmatest_corrige.o
+ .debug_macro 0x00000000 0x52 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x34 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/config_LPC1769.o
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma_corrige.o
+LOAD ./src/dmatest_corrige.o
+START GROUP
+LOAD c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a
+LOAD c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a
+END GROUP
+ 0x00000000 __base_MFlash512 = 0x0
+ 0x00000000 __base_Flash = 0x0
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x00080000 __top_Flash = 0x80000
+ 0x10000000 __base_RamLoc32 = 0x10000000
+ 0x10000000 __base_RAM = 0x10000000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x10008000 __top_RAM = 0x10008000
+ 0x2007c000 __base_RamAHB32 = 0x2007c000
+ 0x2007c000 __base_RAM2 = 0x2007c000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+ 0x20084000 __top_RAM2 = 0x20084000
+
+.text 0x00000000 0x6b8
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x6b8 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x6b8 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x2838 SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x7c ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 PWM1_IRQHandler
+ 0x00000106 I2C1_IRQHandler
+ 0x00000106 EINT2_IRQHandler
+ 0x00000106 UART1_IRQHandler
+ 0x00000106 EINT3_IRQHandler
+ 0x00000106 CANActivity_IRQHandler
+ 0x00000106 TIMER3_IRQHandler
+ 0x00000106 UART0_IRQHandler
+ 0x00000106 MCPWM_IRQHandler
+ 0x00000106 I2C0_IRQHandler
+ 0x00000106 IntDefaultHandler
+ 0x00000106 RIT_IRQHandler
+ 0x00000106 CAN_IRQHandler
+ 0x00000106 PLL1_IRQHandler
+ 0x00000106 SSP0_IRQHandler
+ 0x00000106 I2S_IRQHandler
+ 0x00000106 I2C2_IRQHandler
+ 0x00000106 RTC_IRQHandler
+ 0x00000106 TIMER0_IRQHandler
+ 0x00000106 SPI_IRQHandler
+ 0x00000106 UART3_IRQHandler
+ 0x00000106 EINT1_IRQHandler
+ 0x00000106 TIMER1_IRQHandler
+ 0x00000106 UART2_IRQHandler
+ 0x00000106 ADC_IRQHandler
+ 0x00000106 SSP1_IRQHandler
+ 0x00000106 USB_IRQHandler
+ 0x00000106 BOD_IRQHandler
+ 0x00000106 USBActivity_IRQHandler
+ 0x00000106 WDT_IRQHandler
+ 0x00000106 PLL0_IRQHandler
+ 0x00000106 QEI_IRQHandler
+ 0x00000106 EINT0_IRQHandler
+ 0x00000106 TIMER2_IRQHandler
+ 0x00000106 ENET_IRQHandler
+ 0x00000108 data_init
+ 0x0000011e bss_init
+ 0x00000130 ResetISR
+ 0x000002fc . = 0x2fc
+ *fill* 0x00000170 0x18c ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__, .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__, .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.init 0x00000300 0x38 ./src/config_LPC1769.o
+ 0x00000300 init
+ .text.DMA_IRQHandler
+ 0x00000338 0x60 ./src/dma_corrige.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x00000398 0x9c ./src/dma_corrige.o
+ 0x00000398 DMA_Init
+ .text.single_copy
+ 0x00000434 0xbc ./src/dmatest_corrige.o
+ 0x00000434 single_copy
+ .text.LLI_copy
+ 0x000004f0 0x108 ./src/dmatest_corrige.o
+ 0x000004f0 LLI_copy
+ .text.check_res
+ 0x000005f8 0x40 ./src/dmatest_corrige.o
+ 0x000005f8 check_res
+ .text.main 0x00000638 0x44 ./src/dmatest_corrige.o
+ 0x00000638 main
+ .text.memset 0x0000067c 0x4 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x0000067c memset
+ .text.__weak_main
+ 0x00000680 0x4 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ 0x00000680 __weak_main
+ 0x00000680 __main
+ .text.__aeabi_memset_lowlevel
+ 0x00000684 0x32 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ 0x00000684 __aeabi_lowlevel_memset
+ *(.rodata .rodata.* .constdata .constdata.*)
+ 0x000006b8 . = ALIGN (0x4)
+ *fill* 0x000006b6 0x2 ff
+
+.glue_7 0x000006b8 0x0
+ .glue_7 0x00000000 0x0 linker stubs
+
+.glue_7t 0x000006b8 0x0
+ .glue_7t 0x00000000 0x0 linker stubs
+
+.vfp11_veneer 0x000006b8 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x000006b8 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+
+.iplt 0x000006b8 0x0
+ .iplt 0x00000000 0x0 ./src/config_LPC1769.o
+
+.rel.dyn 0x000006b8 0x0
+ .rel.iplt 0x00000000 0x0 ./src/config_LPC1769.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ 0x000006b8 __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x000006b8 __exidx_end = .
+ 0x000006b8 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x000006b8
+ FILL mask 0xff
+ 0x2007c000 PROVIDE (__start_data_RAM2, .)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+ 0x2007c000 PROVIDE (__end_data_RAM2, .)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x000006b8
+ FILL mask 0xff
+ 0x10000000 _data = .
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+
+.igot.plt 0x10000000 0x0 load address 0x000006b8
+ .igot.plt 0x00000000 0x0 ./src/config_LPC1769.o
+
+.bss_RAM2 0x2007c000 0x0
+ 0x2007c000 PROVIDE (__start_bss_RAM2, .)
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ 0x2007c000 . = ALIGN ((. != 0x0)?0x4:0x1)
+ 0x2007c000 PROVIDE (__end_bss_RAM2, .)
+
+.bss 0x10000000 0x2838
+ 0x10000000 _bss = .
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma_corrige.o
+ 0x10000000 DMATCCount
+ .bss.DMAErrCount
+ 0x10000004 0x4 ./src/dma_corrige.o
+ 0x10000004 DMAErrCount
+ *(COMMON)
+ COMMON 0x10000008 0x2830 ./src/dmatest_corrige.o
+ 0x10000008 dest
+ 0x10001008 delta_t_ref
+ 0x1000100c src2
+ 0x1000140c t_start
+ 0x10001410 src3
+ 0x10001810 i
+ 0x10001814 delta_t
+ 0x10001818 src1
+ 0x10002818 LLI
+ 0x10002838 . = ALIGN (0x4)
+ 0x10002838 _ebss = .
+ 0x10002838 PROVIDE (end, .)
+
+.noinit_RAM2 0x2007c000 0x0
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.noinit 0x10002838 0x0
+ 0x10002838 _noinit = .
+ *(.noinit*)
+ 0x10002838 . = ALIGN (0x4)
+ 0x10002838 _end_noinit = .
+ 0x10002838 PROVIDE (_pvHeapStart, DEFINED (__user_heap_base)?__user_heap_base:.)
+ 0x10008000 PROVIDE (_vStackTop, DEFINED (__user_stack_top)?__user_stack_top:(__top_RamLoc32 - 0x0))
+ 0xefff79f2 PROVIDE (__valid_user_code_checksum, (0x0 - ((((((_vStackTop + (ResetISR + 0x1)) + (NMI_Handler + 0x1)) + (HardFault_Handler + 0x1)) + (DEFINED (MemManage_Handler)?MemManage_Handler:0x0 + 0x1)) + (DEFINED (BusFault_Handler)?BusFault_Handler:0x0 + 0x1)) + (DEFINED (UsageFault_Handler)?UsageFault_Handler:0x0 + 0x1))))
+OUTPUT(labo6_DMA.axf elf32-littlearm)
+
+.debug_info 0x00000000 0x644
+ .debug_info 0x00000000 0x81 ./src/config_LPC1769.o
+ .debug_info 0x00000081 0x26f ./src/cr_startup_lpc176x.o
+ .debug_info 0x000002f0 0x3f ./src/crp.o
+ .debug_info 0x0000032f 0x11a ./src/dma_corrige.o
+ .debug_info 0x00000449 0x1fb ./src/dmatest_corrige.o
+
+.debug_abbrev 0x00000000 0x341
+ .debug_abbrev 0x00000000 0x45 ./src/config_LPC1769.o
+ .debug_abbrev 0x00000045 0x120 ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x00000165 0x36 ./src/crp.o
+ .debug_abbrev 0x0000019b 0xa2 ./src/dma_corrige.o
+ .debug_abbrev 0x0000023d 0x104 ./src/dmatest_corrige.o
+
+.debug_aranges 0x00000000 0x118
+ .debug_aranges
+ 0x00000000 0x20 ./src/config_LPC1769.o
+ .debug_aranges
+ 0x00000020 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x000000a0 0x18 ./src/crp.o
+ .debug_aranges
+ 0x000000b8 0x28 ./src/dma_corrige.o
+ .debug_aranges
+ 0x000000e0 0x38 ./src/dmatest_corrige.o
+
+.debug_ranges 0x00000000 0xc0
+ .debug_ranges 0x00000000 0x10 ./src/config_LPC1769.o
+ .debug_ranges 0x00000010 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000080 0x18 ./src/dma_corrige.o
+ .debug_ranges 0x00000098 0x28 ./src/dmatest_corrige.o
+
+.debug_macro 0x00000000 0x1ff7
+ .debug_macro 0x00000000 0x4b ./src/config_LPC1769.o
+ .debug_macro 0x0000004b 0x86e ./src/config_LPC1769.o
+ .debug_macro 0x000008b9 0x10 ./src/config_LPC1769.o
+ .debug_macro 0x000008c9 0x12d ./src/config_LPC1769.o
+ .debug_macro 0x000009f6 0x5b2 ./src/config_LPC1769.o
+ .debug_macro 0x00000fa8 0x331 ./src/config_LPC1769.o
+ .debug_macro 0x000012d9 0x1d ./src/cr_startup_lpc176x.o
+ .debug_macro 0x000012f6 0x874 ./src/cr_startup_lpc176x.o
+ .debug_macro 0x00001b6a 0x1a ./src/crp.o
+ .debug_macro 0x00001b84 0x34 ./src/crp.o
+ .debug_macro 0x00001bb8 0x54 ./src/dma_corrige.o
+ .debug_macro 0x00001c0c 0x52 ./src/dma_corrige.o
+ .debug_macro 0x00001c5e 0x62 ./src/dmatest_corrige.o
+ .debug_macro 0x00001cc0 0x337 ./src/dmatest_corrige.o
+
+.debug_line 0x00000000 0x58d
+ .debug_line 0x00000000 0x122 ./src/config_LPC1769.o
+ .debug_line 0x00000122 0xbc ./src/cr_startup_lpc176x.o
+ .debug_line 0x000001de 0x78 ./src/crp.o
+ .debug_line 0x00000256 0x141 ./src/dma_corrige.o
+ .debug_line 0x00000397 0x1f6 ./src/dmatest_corrige.o
+
+.debug_str 0x00000000 0x5ac2
+ .debug_str 0x00000000 0x54d4 ./src/config_LPC1769.o
+ 0x5552 (size before relaxing)
+ .debug_str 0x000054d4 0x29f ./src/cr_startup_lpc176x.o
+ 0x263f (size before relaxing)
+ .debug_str 0x00005773 0xe9 ./src/crp.o
+ 0x2540 (size before relaxing)
+ .debug_str 0x0000585c 0x1a1 ./src/dma_corrige.o
+ 0x56d6 (size before relaxing)
+ .debug_str 0x000059fd 0xc5 ./src/dmatest_corrige.o
+ 0x5769 (size before relaxing)
+
+.comment 0x00000000 0xe0
+ .comment 0x00000000 0x70 ./src/config_LPC1769.o
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 ./src/cr_startup_lpc176x.o
+ .comment 0x00000000 0x71 ./src/crp.o
+ .comment 0x00000000 0x71 ./src/dma_corrige.o
+ .comment 0x00000000 0x71 ./src/dmatest_corrige.o
+ .comment 0x00000070 0x70 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x31
+ .ARM.attributes
+ 0x00000000 0x33 ./src/config_LPC1769.o
+ .ARM.attributes
+ 0x00000033 0x33 ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x00000066 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x00000099 0x33 ./src/dma_corrige.o
+ .ARM.attributes
+ 0x000000cc 0x33 ./src/dmatest_corrige.o
+ .ARM.attributes
+ 0x000000ff 0x33 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000132 0x33 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000165 0x21 c:/nxp/lpcxpresso_8.0.0_526/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.9.3/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x20c
+ .debug_frame 0x00000000 0x30 ./src/config_LPC1769.o
+ .debug_frame 0x00000030 0xf0 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x00000120 0x60 ./src/dma_corrige.o
+ .debug_frame 0x00000180 0x8c ./src/dmatest_corrige.o
+
+.debug_loc 0x00000000 0x1be
+ .debug_loc 0x00000000 0x1be ./src/cr_startup_lpc176x.o
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld
new file mode 100644
index 0000000..5965732
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug.ld
@@ -0,0 +1,158 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * LPCXpresso v8.0.0 [Build 526] [2015-11-23] on 19 janv. 2017 07:46:59
+ */
+
+INCLUDE "labo6_DMA_Debug_library.ld"
+INCLUDE "labo6_DMA_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* DATA section for RamAHB32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamAHB32
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+}
\ No newline at end of file
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld
new file mode 100644
index 0000000..af97581
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_library.ld
@@ -0,0 +1,14 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * LPCXpresso v8.0.0 [Build 526] [2015-11-23] on 19 janv. 2017 07:46:59
+ */
+
+GROUP (
+ libcr_c.a
+ libcr_eabihelpers.a
+)
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld
new file mode 100644
index 0000000..247ebe9
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_memory.ld
@@ -0,0 +1,31 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.23
+ * LPCXpresso v8.0.0 [Build 526] [2015-11-23] on 19 janv. 2017 07:46:59
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld
new file mode 100644
index 0000000..a0693af
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo6_DMA_Debug_old.ld
@@ -0,0 +1,163 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2017
+ * Generated linker script file for LPC1769
+ * Created from generic_c.ld (8.0.0 ())
+ * By LPCXpresso v8.0.0 [Build 526] [2015-11-23] on Thu Jan 19 07:46:58 CET 2017
+ */
+
+
+INCLUDE "labo6_DMA_Debug_library.ld"
+INCLUDE "labo6_DMA_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+}
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA.axf b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA.axf
new file mode 100644
index 0000000000000000000000000000000000000000..3afac83f168d619448067e191671069e2206e77d
GIT binary patch
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diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA.map b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA.map
new file mode 100644
index 0000000..7971490
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA.map
@@ -0,0 +1,404 @@
+Archive member included because of file (symbol)
+
+C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ ./src/cr_startup_lpc176x.o (SystemInit)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ ./src/dmatest_corrige.o (memset)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o) (__aeabi_uldivmod)
+c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest_corrige.o
+src2 0x400 ./src/dmatest_corrige.o
+src3 0x400 ./src/dmatest_corrige.o
+i 0x4 ./src/dmatest_corrige.o
+src1 0x1000 ./src/dmatest_corrige.o
+LLI 0x20 ./src/dmatest_corrige.o
+
+Discarded input sections
+
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .text 0x00000000 0x0 ./src/dma_corrige.o
+ .data 0x00000000 0x0 ./src/dma_corrige.o
+ .bss 0x00000000 0x0 ./src/dma_corrige.o
+ .text 0x00000000 0x0 ./src/dmatest_corrige.o
+ .data 0x00000000 0x0 ./src/dmatest_corrige.o
+ .bss 0x00000000 0x0 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data 0x00000000 0x0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .bss 0x00000000 0x0 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text.SystemCoreClockUpdate
+ 0x00000000 0xcc C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data.SystemCoreClock
+ 0x00000000 0x4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldivmod
+ 0x00000000 0x26 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uldivmod
+ 0x00000000 0x174 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x26 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma_corrige.o
+LOAD ./src/dmatest_corrige.o
+LOAD C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a
+LOAD c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a
+END GROUP
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+
+.text 0x00000000 0x898
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x898 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x898 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x282c SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x78 ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 data_init
+ 0x00000118 bss_init
+ 0x00000128 ResetISR
+ 0x00000168 UART1_IRQHandler
+ 0x00000168 EINT3_IRQHandler
+ 0x00000168 CANActivity_IRQHandler
+ 0x00000168 TIMER3_IRQHandler
+ 0x00000168 UART0_IRQHandler
+ 0x00000168 EINT2_IRQHandler
+ 0x00000168 I2C1_IRQHandler
+ 0x00000168 IntDefaultHandler
+ 0x00000168 PLL0_IRQHandler
+ 0x00000168 PWM1_IRQHandler
+ 0x00000168 PLL1_IRQHandler
+ 0x00000168 SSP0_IRQHandler
+ 0x00000168 I2S_IRQHandler
+ 0x00000168 I2C2_IRQHandler
+ 0x00000168 RTC_IRQHandler
+ 0x00000168 TIMER0_IRQHandler
+ 0x00000168 SPI_IRQHandler
+ 0x00000168 USBActivity_IRQHandler
+ 0x00000168 EINT1_IRQHandler
+ 0x00000168 TIMER1_IRQHandler
+ 0x00000168 UART2_IRQHandler
+ 0x00000168 ADC_IRQHandler
+ 0x00000168 SSP1_IRQHandler
+ 0x00000168 USB_IRQHandler
+ 0x00000168 BOD_IRQHandler
+ 0x00000168 I2C0_IRQHandler
+ 0x00000168 WDT_IRQHandler
+ 0x00000168 RIT_IRQHandler
+ 0x00000168 QEI_IRQHandler
+ 0x00000168 EINT0_IRQHandler
+ 0x00000168 CAN_IRQHandler
+ 0x00000168 TIMER2_IRQHandler
+ 0x00000168 UART3_IRQHandler
+ 0x00000168 MCPWM_IRQHandler
+ 0x00000168 ENET_IRQHandler
+ 0x000002fc . = 0x2fc
+ *fill* 0x0000016c 0x190 ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__, .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__, .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.NVIC_EnableIRQ
+ 0x00000300 0x38 ./src/dma_corrige.o
+ .text.DMA_IRQHandler
+ 0x00000338 0x7c ./src/dma_corrige.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x000003b4 0xc0 ./src/dma_corrige.o
+ 0x000003b4 DMA_Init
+ .text.single_copy
+ 0x00000474 0xa8 ./src/dmatest_corrige.o
+ 0x00000474 single_copy
+ .text.LLI_copy
+ 0x0000051c 0x1e4 ./src/dmatest_corrige.o
+ 0x0000051c LLI_copy
+ .text.check_res
+ 0x00000700 0x4c ./src/dmatest_corrige.o
+ 0x00000700 check_res
+ .text.main 0x0000074c 0x3c ./src/dmatest_corrige.o
+ 0x0000074c main
+ .text.SystemInit
+ 0x00000788 0xe4 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x00000788 SystemInit
+ .text.memset 0x0000086c 0x4 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x0000086c memset
+ .text.__weak_main
+ 0x00000870 0x4 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ 0x00000870 __weak_main
+ 0x00000870 __main
+ .text.__aeabi_memset_lowlevel
+ 0x00000874 0x24 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ 0x00000874 __aeabi_lowlevel_memset
+ *(.rodata .rodata.*)
+ 0x00000898 . = ALIGN (0x4)
+
+.glue_7 0x00000898 0x0
+ .glue_7 0x00000000 0x0 linker stubs
+
+.glue_7t 0x00000898 0x0
+ .glue_7t 0x00000000 0x0 linker stubs
+
+.vfp11_veneer 0x00000898 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x00000898 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ 0x00000898 __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x00000898 __exidx_end = .
+ 0x00000898 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x00000898
+ FILL mask 0xff
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x00000898
+ FILL mask 0xff
+ 0x10000000 _data = .
+ *(vtable)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+
+.bss_RAM2 0x2007c000 0x0
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.bss 0x10000000 0x282c
+ 0x10000000 _bss = .
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma_corrige.o
+ 0x10000000 DMATCCount
+ .bss.DMAErrCount
+ 0x10000004 0x4 ./src/dma_corrige.o
+ 0x10000004 DMAErrCount
+ *(COMMON)
+ COMMON 0x10000008 0x2824 ./src/dmatest_corrige.o
+ 0x10000008 dest
+ 0x10001008 src2
+ 0x10001408 src3
+ 0x10001808 i
+ 0x1000180c src1
+ 0x1000280c LLI
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _ebss = .
+ 0x1000282c PROVIDE (end, .)
+
+.noinit_RAM2 0x2007c000 0x0
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.noinit 0x1000282c 0x0
+ 0x1000282c _noinit = .
+ *(.noinit*)
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _end_noinit = .
+ 0x1000282c PROVIDE (_pvHeapStart, .)
+ 0x10008000 PROVIDE (_vStackTop, (__top_RamLoc32 - 0x0))
+OUTPUT(labo7_DMA.axf elf32-littlearm)
+
+.debug_info 0x00000000 0xd1b
+ .debug_info 0x00000000 0x2dd ./src/cr_startup_lpc176x.o
+ .debug_info 0x000002dd 0x48 ./src/crp.o
+ .debug_info 0x00000325 0x400 ./src/dma_corrige.o
+ .debug_info 0x00000725 0x267 ./src/dmatest_corrige.o
+ .debug_info 0x0000098c 0x38f C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_abbrev 0x00000000 0x4a9
+ .debug_abbrev 0x00000000 0x12b ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x0000012b 0x39 ./src/crp.o
+ .debug_abbrev 0x00000164 0x144 ./src/dma_corrige.o
+ .debug_abbrev 0x000002a8 0x11e ./src/dmatest_corrige.o
+ .debug_abbrev 0x000003c6 0xe3 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_loc 0x00000000 0x286
+ .debug_loc 0x00000000 0x102 ./src/cr_startup_lpc176x.o
+ .debug_loc 0x00000102 0xa8 ./src/dma_corrige.o
+ .debug_loc 0x000001aa 0xbc ./src/dmatest_corrige.o
+ .debug_loc 0x00000266 0x20 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_aranges 0x00000000 0x110
+ .debug_aranges
+ 0x00000000 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x00000080 0x30 ./src/dma_corrige.o
+ .debug_aranges
+ 0x000000b0 0x38 ./src/dmatest_corrige.o
+ .debug_aranges
+ 0x000000e8 0x28 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_ranges 0x00000000 0xd0
+ .debug_ranges 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000070 0x20 ./src/dma_corrige.o
+ .debug_ranges 0x00000090 0x28 ./src/dmatest_corrige.o
+ .debug_ranges 0x000000b8 0x18 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_line 0x00000000 0x1114
+ .debug_line 0x00000000 0x3da ./src/cr_startup_lpc176x.o
+ .debug_line 0x000003da 0xac ./src/crp.o
+ .debug_line 0x00000486 0x406 ./src/dma_corrige.o
+ .debug_line 0x0000088c 0x49c ./src/dmatest_corrige.o
+ .debug_line 0x00000d28 0x3ec C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_macinfo 0x00000000 0x22317
+ .debug_macinfo
+ 0x00000000 0x3d45 ./src/cr_startup_lpc176x.o
+ .debug_macinfo
+ 0x00003d45 0x238b ./src/crp.o
+ .debug_macinfo
+ 0x000060d0 0x9e68 ./src/dma_corrige.o
+ .debug_macinfo
+ 0x0000ff38 0x9eae ./src/dmatest_corrige.o
+ .debug_macinfo
+ 0x00019de6 0x8531 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_str 0x00000000 0x792
+ .debug_str 0x00000000 0x263 ./src/cr_startup_lpc176x.o
+ 0x28b (size before relaxing)
+ .debug_str 0x00000263 0x16 ./src/crp.o
+ 0xb8 (size before relaxing)
+ .debug_str 0x00000279 0x2db ./src/dma_corrige.o
+ 0x3f6 (size before relaxing)
+ .debug_str 0x00000554 0x88 ./src/dmatest_corrige.o
+ 0x1c4 (size before relaxing)
+ .debug_str 0x000005dc 0x1b6 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x2c8 (size before relaxing)
+
+.comment 0x00000000 0x70
+ .comment 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 ./src/crp.o
+ .comment 0x00000000 0x71 ./src/dma_corrige.o
+ .comment 0x00000000 0x71 ./src/dmatest_corrige.o
+ .comment 0x00000000 0x71 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x31
+ .ARM.attributes
+ 0x00000000 0x33 ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x00000033 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x00000066 0x33 ./src/dma_corrige.o
+ .ARM.attributes
+ 0x00000099 0x33 ./src/dmatest_corrige.o
+ .ARM.attributes
+ 0x000000cc 0x33 C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .ARM.attributes
+ 0x000000ff 0x33 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000132 0x33 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000165 0x21 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .ARM.attributes
+ 0x00000186 0x21 c:/nxp/lpcxpresso_6.0.4_159/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x218
+ .debug_frame 0x00000000 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x000000f4 0x68 ./src/dma_corrige.o
+ .debug_frame 0x0000015c 0x80 ./src/dmatest_corrige.o
+ .debug_frame 0x000001dc 0x3c C:\Users\pillouxv\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld
new file mode 100644
index 0000000..fb58006
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug.ld
@@ -0,0 +1,155 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2015
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC1769
+ * Created from generic_c.ld (LPCXpresso v6.0 (4 [Build 159] [2013-10-09] ))
+ * By LPCXpresso v6.0.4 [Build 159] [2013-10-09] on Wed Dec 16 18:24:34 CET 2015
+ */
+
+
+INCLUDE "labo7_DMA_Debug_lib.ld"
+INCLUDE "labo7_DMA_Debug_mem.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamAHB32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld
new file mode 100644
index 0000000..e88af09
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_lib.ld
@@ -0,0 +1,14 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2015
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC1769
+ * Created from LibIncTemplate.ld (LPCXpresso v6.0 (4 [Build 159] [2013-10-09] ))
+ * By LPCXpresso v6.0.4 [Build 159] [2013-10-09] on Wed Dec 16 18:24:34 CET 2015
+ */
+
+
+ GROUP(
+ libcr_c.a
+ libcr_eabihelpers.a
+ )
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld
new file mode 100644
index 0000000..37ce01f
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo7_DMA_Debug_mem.ld
@@ -0,0 +1,25 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2015
+ * (c) NXP Semiconductors 2013-2015
+ * Linker script memory definitions
+ * Created from LinkMemoryTemplate
+ * By LPCXpresso v6.0.4 [Build 159] [2013-10-09] on Wed Dec 16 18:24:34 CET 2015)
+*/
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc32 = 0x10000000 + 0x8000;
+ __top_RamAHB32 = 0x2007c000 + 0x8000;
+
+
+
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA.axf b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA.axf
new file mode 100644
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diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA.map b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA.map
new file mode 100644
index 0000000..d34e2ea
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA.map
@@ -0,0 +1,403 @@
+Archive member included because of file (symbol)
+
+C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ ./src/cr_startup_lpc176x.o (SystemInit)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ ./src/dmatest_corrige.o (memset)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ ./src/cr_startup_lpc176x.o (__main)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o) (__aeabi_uldivmod)
+c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o) (__aeabi_lowlevel_memset)
+
+Allocating common symbols
+Common symbol size file
+
+dest 0x1000 ./src/dmatest_corrige.o
+src2 0x400 ./src/dmatest_corrige.o
+src3 0x400 ./src/dmatest_corrige.o
+i 0x4 ./src/dmatest_corrige.o
+src1 0x1000 ./src/dmatest_corrige.o
+LLI 0x20 ./src/dmatest_corrige.o
+
+Discarded input sections
+
+ .text 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .data 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .bss 0x00000000 0x0 ./src/cr_startup_lpc176x.o
+ .text 0x00000000 0x0 ./src/crp.o
+ .data 0x00000000 0x0 ./src/crp.o
+ .bss 0x00000000 0x0 ./src/crp.o
+ .text 0x00000000 0x0 ./src/dma_corrige.o
+ .data 0x00000000 0x0 ./src/dma_corrige.o
+ .bss 0x00000000 0x0 ./src/dma_corrige.o
+ .text 0x00000000 0x0 ./src/dmatest_corrige.o
+ .data 0x00000000 0x0 ./src/dmatest_corrige.o
+ .bss 0x00000000 0x0 ./src/dmatest_corrige.o
+ .text.single_copy
+ 0x00000000 0xc4 ./src/dmatest_corrige.o
+ .text 0x00000000 0x0 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data 0x00000000 0x0 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .bss 0x00000000 0x0 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text.SystemCoreClockUpdate
+ 0x00000000 0xcc C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .data.SystemCoreClock
+ 0x00000000 0x4 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidiv
+ 0x00000000 0x10 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uidivmod
+ 0x00000000 0x16 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldivmod
+ 0x00000000 0x26 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_uldivmod
+ 0x00000000 0x174 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_idiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text.__aeabi_division_ldiv0
+ 0x00000000 0x2 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .text 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .data 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .bss 0x00000000 0x0 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memcpy
+ 0x00000000 0x26 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memmove
+ 0x00000000 0x1c c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memclr
+ 0x00000000 0x8 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ .text.__aeabi_memset
+ 0x00000000 0xa c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+MFlash512 0x00000000 0x00080000 xr
+RamLoc32 0x10000000 0x00008000 xrw
+RamAHB32 0x2007c000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/cr_startup_lpc176x.o
+LOAD ./src/crp.o
+LOAD ./src/dma_corrige.o
+LOAD ./src/dmatest_corrige.o
+LOAD C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a
+START GROUP
+LOAD c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a
+LOAD c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a
+END GROUP
+ 0x00080000 __top_MFlash512 = 0x80000
+ 0x10008000 __top_RamLoc32 = 0x10008000
+ 0x20084000 __top_RamAHB32 = 0x20084000
+
+.text 0x00000000 0x7f8
+ FILL mask 0xff
+ 0x00000000 __vectors_start__ = ABSOLUTE (.)
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xcc ./src/cr_startup_lpc176x.o
+ 0x00000000 g_pfnVectors
+ 0x000000cc . = ALIGN (0x4)
+ 0x000000cc __section_table_start = .
+ 0x000000cc __data_section_table = .
+ 0x000000cc 0x4 LONG 0x7f8 LOADADDR (.data)
+ 0x000000d0 0x4 LONG 0x10000000 ADDR (.data)
+ 0x000000d4 0x4 LONG 0x0 SIZEOF (.data)
+ 0x000000d8 0x4 LONG 0x7f8 LOADADDR (.data_RAM2)
+ 0x000000dc 0x4 LONG 0x2007c000 ADDR (.data_RAM2)
+ 0x000000e0 0x4 LONG 0x0 SIZEOF (.data_RAM2)
+ 0x000000e4 __data_section_table_end = .
+ 0x000000e4 __bss_section_table = .
+ 0x000000e4 0x4 LONG 0x10000000 ADDR (.bss)
+ 0x000000e8 0x4 LONG 0x282c SIZEOF (.bss)
+ 0x000000ec 0x4 LONG 0x2007c000 ADDR (.bss_RAM2)
+ 0x000000f0 0x4 LONG 0x0 SIZEOF (.bss_RAM2)
+ 0x000000f4 __bss_section_table_end = .
+ 0x000000f4 __section_table_end = .
+ *(.after_vectors*)
+ .after_vectors
+ 0x000000f4 0x78 ./src/cr_startup_lpc176x.o
+ 0x000000f4 NMI_Handler
+ 0x000000f6 HardFault_Handler
+ 0x000000f8 MemManage_Handler
+ 0x000000fa BusFault_Handler
+ 0x000000fc UsageFault_Handler
+ 0x000000fe SVC_Handler
+ 0x00000100 DebugMon_Handler
+ 0x00000102 PendSV_Handler
+ 0x00000104 SysTick_Handler
+ 0x00000106 data_init
+ 0x00000118 bss_init
+ 0x00000128 ResetISR
+ 0x00000168 UART1_IRQHandler
+ 0x00000168 EINT3_IRQHandler
+ 0x00000168 CANActivity_IRQHandler
+ 0x00000168 TIMER3_IRQHandler
+ 0x00000168 UART0_IRQHandler
+ 0x00000168 EINT2_IRQHandler
+ 0x00000168 I2C1_IRQHandler
+ 0x00000168 IntDefaultHandler
+ 0x00000168 PLL0_IRQHandler
+ 0x00000168 PWM1_IRQHandler
+ 0x00000168 PLL1_IRQHandler
+ 0x00000168 SSP0_IRQHandler
+ 0x00000168 I2S_IRQHandler
+ 0x00000168 I2C2_IRQHandler
+ 0x00000168 RTC_IRQHandler
+ 0x00000168 TIMER0_IRQHandler
+ 0x00000168 SPI_IRQHandler
+ 0x00000168 USBActivity_IRQHandler
+ 0x00000168 EINT1_IRQHandler
+ 0x00000168 TIMER1_IRQHandler
+ 0x00000168 UART2_IRQHandler
+ 0x00000168 ADC_IRQHandler
+ 0x00000168 SSP1_IRQHandler
+ 0x00000168 USB_IRQHandler
+ 0x00000168 BOD_IRQHandler
+ 0x00000168 I2C0_IRQHandler
+ 0x00000168 WDT_IRQHandler
+ 0x00000168 RIT_IRQHandler
+ 0x00000168 QEI_IRQHandler
+ 0x00000168 EINT0_IRQHandler
+ 0x00000168 CAN_IRQHandler
+ 0x00000168 TIMER2_IRQHandler
+ 0x00000168 UART3_IRQHandler
+ 0x00000168 MCPWM_IRQHandler
+ 0x00000168 ENET_IRQHandler
+ 0x000002fc . = 0x2fc
+ *fill* 0x0000016c 0x190 ff
+ 0x000002fc PROVIDE (__CRP_WORD_START__, .)
+ *(.crp)
+ .crp 0x000002fc 0x4 ./src/crp.o
+ 0x000002fc CRP_WORD
+ 0x00000300 PROVIDE (__CRP_WORD_END__, .)
+ 0x00000001 ASSERT (! ((__CRP_WORD_START__ == __CRP_WORD_END__)), Linker CRP Enabled, but no CRP_WORD provided within application)
+ *(.text*)
+ .text.NVIC_EnableIRQ
+ 0x00000300 0x38 ./src/dma_corrige.o
+ .text.DMA_IRQHandler
+ 0x00000338 0x94 ./src/dma_corrige.o
+ 0x00000338 DMA_IRQHandler
+ .text.DMA_Init
+ 0x000003cc 0xa4 ./src/dma_corrige.o
+ 0x000003cc DMA_Init
+ .text.LLI_copy
+ 0x00000470 0x200 ./src/dmatest_corrige.o
+ 0x00000470 LLI_copy
+ .text.check_res
+ 0x00000670 0x4c ./src/dmatest_corrige.o
+ 0x00000670 check_res
+ .text.main 0x000006bc 0x2c ./src/dmatest_corrige.o
+ 0x000006bc main
+ .text.SystemInit
+ 0x000006e8 0xe4 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x000006e8 SystemInit
+ .text.memset 0x000007cc 0x4 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ 0x000007cc memset
+ .text.__weak_main
+ 0x000007d0 0x4 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ 0x000007d0 __weak_main
+ 0x000007d0 __main
+ .text.__aeabi_memset_lowlevel
+ 0x000007d4 0x24 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+ 0x000007d4 __aeabi_lowlevel_memset
+ *(.rodata .rodata.*)
+ 0x000007f8 . = ALIGN (0x4)
+
+.glue_7 0x000007f8 0x0
+ .glue_7 0x00000000 0x0 linker stubs
+
+.glue_7t 0x000007f8 0x0
+ .glue_7t 0x00000000 0x0 linker stubs
+
+.vfp11_veneer 0x000007f8 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x000007f8 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ 0x000007f8 __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x000007f8 __exidx_end = .
+ 0x000007f8 _etext = .
+
+.data_RAM2 0x2007c000 0x0 load address 0x000007f8
+ FILL mask 0xff
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.uninit_RESERVED
+ 0x10000000 0x0
+ *(.bss.$RESERVED*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _end_uninit_RESERVED = .
+
+.data 0x10000000 0x0 load address 0x000007f8
+ FILL mask 0xff
+ 0x10000000 _data = .
+ *(vtable)
+ *(.data*)
+ 0x10000000 . = ALIGN (0x4)
+ 0x10000000 _edata = .
+
+.bss_RAM2 0x2007c000 0x0
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.bss 0x10000000 0x282c
+ 0x10000000 _bss = .
+ *(.bss*)
+ .bss.DMATCCount
+ 0x10000000 0x4 ./src/dma_corrige.o
+ 0x10000000 DMATCCount
+ .bss.DMAErrCount
+ 0x10000004 0x4 ./src/dma_corrige.o
+ 0x10000004 DMAErrCount
+ *(COMMON)
+ COMMON 0x10000008 0x2824 ./src/dmatest_corrige.o
+ 0x10000008 dest
+ 0x10001008 src2
+ 0x10001408 src3
+ 0x10001808 i
+ 0x1000180c src1
+ 0x1000280c LLI
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _ebss = .
+ 0x1000282c PROVIDE (end, .)
+
+.noinit_RAM2 0x2007c000 0x0
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ 0x2007c000 . = ALIGN (0x4)
+
+.noinit 0x1000282c 0x0
+ 0x1000282c _noinit = .
+ *(.noinit*)
+ 0x1000282c . = ALIGN (0x4)
+ 0x1000282c _end_noinit = .
+ 0x1000282c PROVIDE (_pvHeapStart, .)
+ 0x10008000 PROVIDE (_vStackTop, (__top_RamLoc32 - 0x0))
+OUTPUT(labo_DMA.axf elf32-littlearm)
+
+.debug_info 0x00000000 0xd1b
+ .debug_info 0x00000000 0x2dd ./src/cr_startup_lpc176x.o
+ .debug_info 0x000002dd 0x48 ./src/crp.o
+ .debug_info 0x00000325 0x400 ./src/dma_corrige.o
+ .debug_info 0x00000725 0x267 ./src/dmatest_corrige.o
+ .debug_info 0x0000098c 0x38f C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_abbrev 0x00000000 0x4a9
+ .debug_abbrev 0x00000000 0x12b ./src/cr_startup_lpc176x.o
+ .debug_abbrev 0x0000012b 0x39 ./src/crp.o
+ .debug_abbrev 0x00000164 0x144 ./src/dma_corrige.o
+ .debug_abbrev 0x000002a8 0x11e ./src/dmatest_corrige.o
+ .debug_abbrev 0x000003c6 0xe3 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_loc 0x00000000 0x286
+ .debug_loc 0x00000000 0x102 ./src/cr_startup_lpc176x.o
+ .debug_loc 0x00000102 0xa8 ./src/dma_corrige.o
+ .debug_loc 0x000001aa 0xbc ./src/dmatest_corrige.o
+ .debug_loc 0x00000266 0x20 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_aranges 0x00000000 0x110
+ .debug_aranges
+ 0x00000000 0x80 ./src/cr_startup_lpc176x.o
+ .debug_aranges
+ 0x00000080 0x30 ./src/dma_corrige.o
+ .debug_aranges
+ 0x000000b0 0x38 ./src/dmatest_corrige.o
+ .debug_aranges
+ 0x000000e8 0x28 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_ranges 0x00000000 0xd0
+ .debug_ranges 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ .debug_ranges 0x00000070 0x20 ./src/dma_corrige.o
+ .debug_ranges 0x00000090 0x28 ./src/dmatest_corrige.o
+ .debug_ranges 0x000000b8 0x18 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_line 0x00000000 0x110e
+ .debug_line 0x00000000 0x3d8 ./src/cr_startup_lpc176x.o
+ .debug_line 0x000003d8 0xad ./src/crp.o
+ .debug_line 0x00000485 0x403 ./src/dma_corrige.o
+ .debug_line 0x00000888 0x495 ./src/dmatest_corrige.o
+ .debug_line 0x00000d1d 0x3f1 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_macinfo 0x00000000 0x22317
+ .debug_macinfo
+ 0x00000000 0x3d45 ./src/cr_startup_lpc176x.o
+ .debug_macinfo
+ 0x00003d45 0x238b ./src/crp.o
+ .debug_macinfo
+ 0x000060d0 0x9e68 ./src/dma_corrige.o
+ .debug_macinfo
+ 0x0000ff38 0x9eae ./src/dmatest_corrige.o
+ .debug_macinfo
+ 0x00019de6 0x8531 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+
+.debug_str 0x00000000 0x783
+ .debug_str 0x00000000 0x25b ./src/cr_startup_lpc176x.o
+ 0x283 (size before relaxing)
+ .debug_str 0x0000025b 0x16 ./src/crp.o
+ 0xb0 (size before relaxing)
+ .debug_str 0x00000271 0x2db ./src/dma_corrige.o
+ 0x3ee (size before relaxing)
+ .debug_str 0x0000054c 0x88 ./src/dmatest_corrige.o
+ 0x1bc (size before relaxing)
+ .debug_str 0x000005d4 0x1af C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ 0x2c1 (size before relaxing)
+
+.comment 0x00000000 0x70
+ .comment 0x00000000 0x70 ./src/cr_startup_lpc176x.o
+ 0x71 (size before relaxing)
+ .comment 0x00000000 0x71 ./src/crp.o
+ .comment 0x00000000 0x71 ./src/dma_corrige.o
+ .comment 0x00000000 0x71 ./src/dmatest_corrige.o
+ .comment 0x00000000 0x71 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .comment 0x00000000 0x71 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+
+.ARM.attributes
+ 0x00000000 0x31
+ .ARM.attributes
+ 0x00000000 0x33 ./src/cr_startup_lpc176x.o
+ .ARM.attributes
+ 0x00000033 0x33 ./src/crp.o
+ .ARM.attributes
+ 0x00000066 0x33 ./src/dma_corrige.o
+ .ARM.attributes
+ 0x00000099 0x33 ./src/dmatest_corrige.o
+ .ARM.attributes
+ 0x000000cc 0x33 C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
+ .ARM.attributes
+ 0x000000ff 0x33 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(memset.o)
+ .ARM.attributes
+ 0x00000132 0x33 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/../../../../arm-none-eabi/lib/armv7-m\libcr_c.a(__weak__main.o)
+ .ARM.attributes
+ 0x00000165 0x21 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(division.o)
+ .ARM.attributes
+ 0x00000186 0x21 c:/nxp/lpcxpresso_5.2.6_2137/lpcxpresso/tools/bin/../lib/gcc/arm-none-eabi/4.6.2/armv7-m\libcr_eabihelpers.a(memcpy.o)
+
+.debug_frame 0x00000000 0x218
+ .debug_frame 0x00000000 0xf4 ./src/cr_startup_lpc176x.o
+ .debug_frame 0x000000f4 0x68 ./src/dma_corrige.o
+ .debug_frame 0x0000015c 0x80 ./src/dmatest_corrige.o
+ .debug_frame 0x000001dc 0x3c C:\Users\Vincent\Documents\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug\libCMSISv2p00_LPC17xx.a(system_LPC17xx.o)
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug.ld
new file mode 100644
index 0000000..46f8ad1
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug.ld
@@ -0,0 +1,154 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2015
+ * Generated linker script file for LPC1769
+ * Created from generic_c.ld (vLPCXpresso v5.2 (6 [Build 2137] [2013-07-08] ))
+ * By LPCXpresso v5.2.6 [Build 2137] [2013-07-08] on Fri Jan 09 22:38:35 CET 2015
+ */
+
+
+INCLUDE "labo_DMA_Debug_lib.ld"
+INCLUDE "labo_DMA_Debug_mem.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ /* Code Read Protect data */
+ . = 0x000002FC ;
+ PROVIDE(__CRP_WORD_START__ = .) ;
+ KEEP(*(.crp))
+ PROVIDE(__CRP_WORD_END__ = .) ;
+ ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
+ /* End of Code Read Protect */
+
+ } >MFlash512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamAHB32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlash512
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld
new file mode 100644
index 0000000..2e8b5b9
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_lib.ld
@@ -0,0 +1,13 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2015
+ * Generated linker script file for LPC1769
+ * Created from LibIncTemplate.ld (vLPCXpresso v5.2 (6 [Build 2137] [2013-07-08] ))
+ * By LPCXpresso v5.2.6 [Build 2137] [2013-07-08] on Fri Jan 09 22:38:35 CET 2015
+ */
+
+
+ GROUP(
+ libcr_c.a
+ libcr_eabihelpers.a
+ )
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld
new file mode 100644
index 0000000..de3f6c5
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/labo_DMA_Debug_mem.ld
@@ -0,0 +1,21 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2015
+ * Linker script memory definitions
+ * Created from LinkMemoryTemplate
+ * By LPCXpresso v5.2.6 [Build 2137] [2013-07-08] on Fri Jan 09 22:38:35 CET 2015)
+*/
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc32 = 0x10000000 + 0x8000;
+ __top_RamAHB32 = 0x2007c000 + 0x8000;
+
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/makefile b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/makefile
new file mode 100644
index 0000000..9604a22
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/makefile
@@ -0,0 +1,60 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := labo4.1_DMA_new
+BUILD_ARTIFACT_EXTENSION := axf
+BUILD_ARTIFACT_PREFIX :=
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all:
+ +@$(MAKE) --no-print-directory main-build && $(MAKE) --no-print-directory post-build
+
+# Main-build Target
+main-build: labo4.1_DMA_new.axf
+
+# Tool invocations
+labo4.1_DMA_new.axf: $(OBJS) $(USER_OBJS) makefile $(OPTIONAL_TOOL_DEPS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Linker'
+ arm-none-eabi-gcc -nostdlib -L"C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\Debug" -Xlinker -Map="labo4.1_DMA_new.map" -Xlinker --gc-sections -mcpu=cortex-m3 -mthumb -T labo4_1_DMA_new_Debug.ld -o "labo4.1_DMA_new.axf" $(OBJS) $(USER_OBJS) $(LIBS) -lCMSISv2p00_LPC17xx
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) labo4.1_DMA_new.axf
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size "labo4.1_DMA_new.axf"; # arm-none-eabi-objcopy -O binary "labo4.1_DMA_new.axf" "labo4.1_DMA_new.bin" ; checksum -p LPC1769 -d "labo4.1_DMA_new.bin";
+ -@echo ' '
+
+.PHONY: all clean dependents main-build post-build
+
+-include ../makefile.targets
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/objects.mk b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/objects.mk
new file mode 100644
index 0000000..dc31e16
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/sources.mk b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/sources.mk
new file mode 100644
index 0000000..19839d5
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/sources.mk
@@ -0,0 +1,18 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ASM_SRCS :=
+C_SRCS :=
+OBJ_SRCS :=
+O_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+C_DEPS :=
+EXECUTABLES :=
+OBJS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/config_LPC1769.su b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/config_LPC1769.su
new file mode 100644
index 0000000..ef495e2
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/config_LPC1769.su
@@ -0,0 +1 @@
+config_LPC1769.c:4:6:init 4 static
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d
new file mode 100644
index 0000000..84ce6d0
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.d
@@ -0,0 +1 @@
+src/cr_startup_lpc176x.o: ../src/cr_startup_lpc176x.c
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.o b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.o
new file mode 100644
index 0000000000000000000000000000000000000000..1d1f5d253d824d6bffea65c6248d463e5d5c67de
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diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su
new file mode 100644
index 0000000..4939545
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/cr_startup_lpc176x.su
@@ -0,0 +1,13 @@
+../src/cr_startup_lpc176x.c:346:6:NMI_Handler 0 static
+../src/cr_startup_lpc176x.c:353:6:HardFault_Handler 0 static
+../src/cr_startup_lpc176x.c:360:6:MemManage_Handler 0 static
+../src/cr_startup_lpc176x.c:367:6:BusFault_Handler 0 static
+../src/cr_startup_lpc176x.c:374:6:UsageFault_Handler 0 static
+../src/cr_startup_lpc176x.c:381:6:SVC_Handler 0 static
+../src/cr_startup_lpc176x.c:388:6:DebugMon_Handler 0 static
+../src/cr_startup_lpc176x.c:395:6:PendSV_Handler 0 static
+../src/cr_startup_lpc176x.c:402:6:SysTick_Handler 0 static
+../src/cr_startup_lpc176x.c:416:6:IntDefaultHandler 0 static
+../src/cr_startup_lpc176x.c:216:6:data_init 8 static
+../src/cr_startup_lpc176x.c:225:6:bss_init 0 static
+../src/cr_startup_lpc176x.c:271:1:ResetISR 16 static
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.d b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.d
new file mode 100644
index 0000000..2548921
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.d
@@ -0,0 +1 @@
+src/crp.o src/crp.d: ../src/crp.c
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.o b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.o
new file mode 100644
index 0000000000000000000000000000000000000000..d5bbc38772a1c7fdd9a28d247d660cf7eac4d6ec
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diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.su b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/crp.su
new file mode 100644
index 0000000..e69de29
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.d b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.d
new file mode 100644
index 0000000..6c76c86
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.d
@@ -0,0 +1,13 @@
+src/dma.o src/dma.d: ../src/dma.c \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h \
+ ../src/dma.h
+C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
+C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/core_cm3.h:
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+C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h:
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diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.o b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.o
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diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.su b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.su
new file mode 100644
index 0000000..60bd963
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dma.su
@@ -0,0 +1,2 @@
+../src/dma.c:16:6:DMA_IRQHandler 4 static
+../src/dma.c:35:6:DMA_Init 24 static
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.d b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.d
new file mode 100644
index 0000000..177ba17
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.d
@@ -0,0 +1,12 @@
+src/dmatest.o src/dmatest.d: ../src/dmatest.c ../src/dma.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/LPC17xx.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/core_cm3.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/core_cmInstr.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/core_cmFunc.h \
+ C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/system_LPC17xx.h
+../src/dma.h:
+C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc/LPC17xx.h:
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diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.o b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.o
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literal 0
HcmV?d00001
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.su b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.su
new file mode 100644
index 0000000..764c89d
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/dmatest.su
@@ -0,0 +1,4 @@
+../src/dmatest.c:17:6:single_copy 8 static
+../src/dmatest.c:30:6:LLI_copy 8 static
+../src/dmatest.c:52:5:check_res 16 static
+../src/dmatest.c:67:5:main 8 static
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/subdir.mk b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/subdir.mk
new file mode 100644
index 0000000..d282bd8
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/Debug/src/subdir.mk
@@ -0,0 +1,47 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../src/cr_startup_lpc176x.c \
+../src/crp.c \
+../src/dma.c \
+../src/dmatest.c
+
+C_DEPS += \
+./src/cr_startup_lpc176x.d \
+./src/crp.d \
+./src/dma.d \
+./src/dmatest.d
+
+OBJS += \
+./src/cr_startup_lpc176x.o \
+./src/crp.o \
+./src/dma.o \
+./src/dmatest.o
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/cr_startup_lpc176x.o: ../src/cr_startup_lpc176x.c src/subdir.mk
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I"C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc" -Os -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fmerge-constants -fmacro-prefix-map="$(<D)/"= -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+src/%.o: ../src/%.c src/subdir.mk
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -D__REDLIB__ -DDEBUG -D__CODE_RED -I"C:\Users\vincent.pilloux\Documents\Hepia\LPCXpresso_5.2.6_2137\pro\CMSISv2p00_LPC17xx\inc" -O0 -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fmerge-constants -fmacro-prefix-map="$(<D)/"= -mcpu=cortex-m3 -mthumb -D__REDLIB__ -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
+clean: clean-src
+
+clean-src:
+ -$(RM) ./src/cr_startup_lpc176x.d ./src/cr_startup_lpc176x.o ./src/crp.d ./src/crp.o ./src/dma.d ./src/dma.o ./src/dmatest.d ./src/dmatest.o
+
+.PHONY: clean-src
+
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Debug.launch b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Debug.launch
new file mode 100644
index 0000000..159c237
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Debug.launch
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
+<stringAttribute key="LAUNCH_ID.OFSemuDetails" value="LPC-Link (HID)"/>
+<booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
+<stringAttribute key="com.crt.ctrlcenter.currentWireType" value="SWD"/>
+<stringAttribute key="com.crt.ctrlcenter.targetbase" value="NXP LPC17xx"/>
+<stringAttribute key="com.crt.ctrlcenter.targetconfig" value="<?xml version="1.0" encoding="UTF-8"?> <config chipvendor="NXP" genname="NXP LPC17xx" id="config.gdb.stub"><parameters><params><param default="true" description="Vector catch" name="Vector catch" value="false" var="vector.catch"><enum value="True"/> <enum value="False"/> </param> </params> <initValue value="false" var="vector.catch"/> <params><param default="On" description="Enablement of semihosting support" name="Semihosting support" value="On" var="internal.semihost"><enum value="On"/> <enum value="Off"/> <enum value="Auto"/> </param> </params> <params><param default="" description="Maximum wire speed in KHz (leave blank to Auto-detect). Not all values are supported by all targets" name="Maximum wire speed" probe="^(?!Redlink Server$).*$" type="nullString" value="" var="emu.speed"><enum value=""/> <enum value="30000"/> <enum value="15000"/> <enum value="10000"/> <enum value="7500"/> <enum value="6000"/> <enum value="5000"/> <enum value="3750"/> <enum value="3000"/> <enum value="2500"/> <enum value="2000"/> <enum value="1500"/> <enum value="1250"/> <enum value="1200"/> <enum value="1000"/> <enum value="750"/> <enum value="600"/> <enum value="500"/> <enum value="400"/> <enum value="300"/> <enum value="250"/> <enum value="200"/> <enum value="150"/> </param> </params> <params><param content="serverScript" description="Connect script" name="Connect Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.connect.script"/> <param content="serverScript" description="Reset script" name="Reset Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.reset.script"/> <param default="" description="Select the reset handling type for this debug connection" name="Reset Handling" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="VECTRESET" var="internal.resethandling"><enum value="SYSRESETREQ"/> <enum value="VECTRESET"/> <enum value="Default"/> <enum value=""/> </param> <param default="" description="Additional options" name="Additional options" value="" var="misc.options"/> <param default="2" description="Set stub debug level (1-4)" name="Debug Level " value="2" var="debug.level"/> <param default="False" description="when True, attach to running target only (without loading image)" name="Attach only" required="true" value="False" var="attach"><enum value="True"/> <enum value="False"/> </param> <param default="True" description="Deprecated. Functionality superseded by &apos;Attach only&apos;" name="Load image" type="boolean" value="True" var="load"><enum value="True"/> <enum value="False"/> </param> <param default="cont" description="Run, continue or (do nothing)" name="Run/Continue image" value="cont" var="run"><enum value="run"/> <enum value="cont"/> <enum value=""/> </param> <param default="off" description="If on is specified, make the debugger treat unknown memory as non-existent and refuse \naccesses to such memory. If off is specified, treat the memory as RAM" name="Memory Access Checking" value="off" var="mem.access"><enum value="on"/> <enum value="off"/> </param> <param default="cont" description="choose the disconnect behavior for the target" name="Disconnect behavior" value="cont" var="ondisconnect"><enum value="nochange"/> <enum value="stop"/> <enum value="cont"/> <enum value="run_cont"/> </param> <param default="" description="Command to run before starting the debugger" name="Pre launch command" value="" var="internal.prelaunch.command"/> <param default="" description="Target Wirespeed in Hz" name="Wirespeed (Hz)" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="" var="internal.wirespeed"/> </params> <initvalue value="VECTRESET" var="internal.resethandling"/> <params><param default="SWD" description="Internal wiretypes" mode="hidden" name="Wiretype" probe="NEVER" value="SWD*,JTAG" var="internal.wiretype"></param> <param default="false" description="Chip supports SWO" mode="hidden" name="Has SWO" probe="NEVER" value="true" var="internal.has_swo"></param> </params> <initvalue value="SWD*,JTAG" var="internal.wiretype"/> <initvalue value="true" var="internal.has_swo"/> </parameters> <script emulators="${gdb.stub} -mi -info-emu" silent="false" swv="true" type="init">set remotetimeout 60000&#x0A;##target_extended_remote##&#x0A;set mem inaccessible-by-default ${mem.access}&#x0A;mon ondisconnect ${ondisconnect}&#x0A;set arm force-mode thumb&#x0A;${load}</script> <script silent="false" type="run">${run}</script> </config> "/>
+<intAttribute key="com.crt.ctrlcenter.version" value="3"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.GDB_INIT" value=""/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\labo6_DMA.axf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="labo6_DMA"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.759137190"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Release.launch b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Release.launch
new file mode 100644
index 0000000..3c50751
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/labo6_DMA Release.launch
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
+<booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
+<stringAttribute key="com.crt.ctrlcenter.targetbase" value="NXP LPC17xx"/>
+<stringAttribute key="com.crt.ctrlcenter.targetconfig" value="<?xml version="1.0" encoding="UTF-8"?> <config chipvendor="NXP" genname="NXP LPC17xx" id="config.gdb.stub"><parameters><params><param default="true" description="Vector catch" name="Vector catch" value="false" var="vector.catch"><enum value="True"/> <enum value="False"/> </param> </params> <initValue value="false" var="vector.catch"/> <params><param default="On" description="Enablement of semihosting support" name="Semihosting support" value="On" var="internal.semihost"><enum value="On"/> <enum value="Off"/> <enum value="Auto"/> </param> </params> <params><param default="" description="Maximum wire speed in KHz (leave blank to Auto-detect). Not all values are supported by all targets" name="Maximum wire speed" probe="^(?!Redlink Server$).*$" type="nullString" value="" var="emu.speed"><enum value=""/> <enum value="30000"/> <enum value="15000"/> <enum value="10000"/> <enum value="7500"/> <enum value="6000"/> <enum value="5000"/> <enum value="3750"/> <enum value="3000"/> <enum value="2500"/> <enum value="2000"/> <enum value="1500"/> <enum value="1250"/> <enum value="1200"/> <enum value="1000"/> <enum value="750"/> <enum value="600"/> <enum value="500"/> <enum value="400"/> <enum value="300"/> <enum value="250"/> <enum value="200"/> <enum value="150"/> </param> </params> <params><param content="serverScript" description="Connect script" name="Connect Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.connect.script"/> <param content="serverScript" description="Reset script" name="Reset Script" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" required="false" type="nullString" var="internal.reset.script"/> <param default="" description="Select the reset handling type for this debug connection" name="Reset Handling" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="VECTRESET" var="internal.resethandling"><enum value="SYSRESETREQ"/> <enum value="VECTRESET"/> <enum value="Default"/> <enum value=""/> </param> <param default="" description="Additional options" name="Additional options" value="" var="misc.options"/> <param default="2" description="Set stub debug level (1-4)" name="Debug Level " value="2" var="debug.level"/> <param default="False" description="when True, attach to running target only (without loading image)" name="Attach only" required="true" value="False" var="attach"><enum value="True"/> <enum value="False"/> </param> <param default="True" description="Deprecated. Functionality superseded by &apos;Attach only&apos;" name="Load image" type="boolean" value="True" var="load"><enum value="True"/> <enum value="False"/> </param> <param default="cont" description="Run, continue or (do nothing)" name="Run/Continue image" value="cont" var="run"><enum value="run"/> <enum value="cont"/> <enum value=""/> </param> <param default="off" description="If on is specified, make the debugger treat unknown memory as non-existent and refuse \naccesses to such memory. If off is specified, treat the memory as RAM" name="Memory Access Checking" value="off" var="mem.access"><enum value="on"/> <enum value="off"/> </param> <param default="cont" description="choose the disconnect behavior for the target" name="Disconnect behavior" value="cont" var="ondisconnect"><enum value="nochange"/> <enum value="stop"/> <enum value="cont"/> <enum value="run_cont"/> </param> <param default="" description="Command to run before starting the debugger" name="Pre launch command" value="" var="internal.prelaunch.command"/> <param default="" description="Target Wirespeed in Hz" name="Wirespeed (Hz)" probe="(?i)(Redlink\s+Server|CMSIS-DAP)" value="" var="internal.wirespeed"/> </params> <initvalue value="VECTRESET" var="internal.resethandling"/> <params><param default="SWD" description="Internal wiretypes" mode="hidden" name="Wiretype" probe="NEVER" value="SWD*,JTAG" var="internal.wiretype"></param> <param default="false" description="Chip supports SWO" mode="hidden" name="Has SWO" probe="NEVER" value="true" var="internal.has_swo"></param> </params> <initvalue value="SWD*,JTAG" var="internal.wiretype"/> <initvalue value="true" var="internal.has_swo"/> </parameters> <script emulators="${gdb.stub} -mi -info-emu" silent="false" swv="true" type="init">set remotetimeout 60000&#x0A;##target_extended_remote##&#x0A;set mem inaccessible-by-default ${mem.access}&#x0A;mon ondisconnect ${ondisconnect}&#x0A;set arm force-mode thumb&#x0A;${load}</script> <script silent="false" type="run">${run}</script> </config> "/>
+<intAttribute key="com.crt.ctrlcenter.version" value="3"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.GDB_INIT" value=""/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release\labo6_DMA.axf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="labo6_DMA"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.release.1841072117"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
+</launchConfiguration>
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/cr_startup_lpc176x.c b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/cr_startup_lpc176x.c
new file mode 100644
index 0000000..d847441
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/cr_startup_lpc176x.c
@@ -0,0 +1,421 @@
+//*****************************************************************************
+// +--+
+// | ++----+
+// +-++ |
+// | |
+// +-+--+ |
+// | +--+--+
+// +----+ Copyright (c) 2009-12 Code Red Technologies Ltd.
+//
+// Microcontroller Startup code for use with Red Suite
+//
+// Version : 120126
+//
+// Software License Agreement
+//
+// The software is owned by Code Red Technologies and/or its suppliers, and is
+// protected under applicable copyright laws. All rights are reserved. Any
+// use in violation of the foregoing restrictions may subject the user to criminal
+// sanctions under applicable laws, as well as to civil liability for the breach
+// of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
+// CODE RED TECHNOLOGIES LTD.
+//
+//*****************************************************************************
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+// Code Red - if CMSIS is being used, then SystemInit() routine
+// will be called by startup code rather than in application's main()
+#if defined (__USE_CMSIS)
+#include "system_LPC17xx.h"
+#endif
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM3
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC17
+ WDT_IRQHandler, // 16, 0x40 - WDT
+ TIMER0_IRQHandler, // 17, 0x44 - TIMER0
+ TIMER1_IRQHandler, // 18, 0x48 - TIMER1
+ TIMER2_IRQHandler, // 19, 0x4c - TIMER2
+ TIMER3_IRQHandler, // 20, 0x50 - TIMER3
+ UART0_IRQHandler, // 21, 0x54 - UART0
+ UART1_IRQHandler, // 22, 0x58 - UART1
+ UART2_IRQHandler, // 23, 0x5c - UART2
+ UART3_IRQHandler, // 24, 0x60 - UART3
+ PWM1_IRQHandler, // 25, 0x64 - PWM1
+ I2C0_IRQHandler, // 26, 0x68 - I2C0
+ I2C1_IRQHandler, // 27, 0x6c - I2C1
+ I2C2_IRQHandler, // 28, 0x70 - I2C2
+ SPI_IRQHandler, // 29, 0x74 - SPI
+ SSP0_IRQHandler, // 30, 0x78 - SSP0
+ SSP1_IRQHandler, // 31, 0x7c - SSP1
+ PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
+ RTC_IRQHandler, // 33, 0x84 - RTC
+ EINT0_IRQHandler, // 34, 0x88 - EINT0
+ EINT1_IRQHandler, // 35, 0x8c - EINT1
+ EINT2_IRQHandler, // 36, 0x90 - EINT2
+ EINT3_IRQHandler, // 37, 0x94 - EINT3
+ ADC_IRQHandler, // 38, 0x98 - ADC
+ BOD_IRQHandler, // 39, 0x9c - BOD
+ USB_IRQHandler, // 40, 0xA0 - USB
+ CAN_IRQHandler, // 41, 0xa4 - CAN
+ DMA_IRQHandler, // 42, 0xa8 - GP DMA
+ I2S_IRQHandler, // 43, 0xac - I2S
+ ENET_IRQHandler, // 44, 0xb0 - Ethernet
+ RIT_IRQHandler, // 45, 0xb4 - RITINT
+ MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
+ QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
+ PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
+ USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
+ CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
+};
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+#ifndef USE_OLD_STYLE_DATA_BSS_INIT
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+#else
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the load address, execution address and length of the RW data section and
+// the execution and length of the BSS (zero initialized) section.
+// Note that these symbols are not normally used by the managed linker script
+// mechanism in Red Suite/LPCXpresso 3.6 (Windows) and LPCXpresso 3.8 (Linux).
+// They are provide here simply so this startup code can be used with earlier
+// versions of Red Suite which do not support the more advanced managed linker
+// script mechanism introduced in the above version. To enable their use,
+// define "USE_OLD_STYLE_DATA_BSS_INIT".
+//*****************************************************************************
+extern unsigned int _etext;
+extern unsigned int _data;
+extern unsigned int _edata;
+extern unsigned int _bss;
+extern unsigned int _ebss;
+#endif
+
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void
+ResetISR(void) {
+
+#ifndef USE_OLD_STYLE_DATA_BSS_INIT
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+#else
+ // Use Old Style Data and BSS section initialization.
+ // This will only initialize a single RAM bank.
+ unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen;
+
+ // Copy the data segment from flash to SRAM.
+ LoadAddr = &_etext;
+ ExeAddr = &_data;
+ EndAddr = &_edata;
+ SectionLen = (void*)EndAddr - (void*)ExeAddr;
+ data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
+ // Zero fill the bss segment
+ ExeAddr = &_bss;
+ EndAddr = &_ebss;
+ SectionLen = (void*)EndAddr - (void*)ExeAddr;
+ bss_init ((unsigned int)ExeAddr, SectionLen);
+#endif
+
+#ifdef __USE_CMSIS
+ SystemInit();
+#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{
+ while(1)
+ {
+ }
+}
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/crp.c b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/crp.c
new file mode 100644
index 0000000..fa9a0d5
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/crp.c
@@ -0,0 +1,38 @@
+//*****************************************************************************
+// crp.c
+//
+// Source file to create CRP word expected by LPCXpresso IDE linker
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products. This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__CODE_RED)
+#include <NXP/crp.h>
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+#endif
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.c b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.c
new file mode 100644
index 0000000..0acee6c
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.c
@@ -0,0 +1,40 @@
+/****************************************************************************
+ DMA driver
+****************************************************************************/
+
+#include "LPC17xx.h"
+#include "dma.h"
+
+/* to be incremented when terminal count reached */
+volatile uint32_t DMATCCount = 0;
+/* to be incremented if an error occurred during transfer */
+volatile uint32_t DMAErrCount = 0;
+
+/******************************************************************************
+* Descriptions: DMA interrupt handler
+******************************************************************************/
+void DMA_IRQHandler (void)
+{
+ /*...*/
+}
+
+
+/******************************************************************************
+* Function name: DMA_Init
+*
+* Description: initialise DMA 0 channel for 32 bits access with increment on
+* source and destination addresses
+*
+* parameters:
+* src: source address
+* dest: destination address
+* len: number of words to transfer
+* LLI: pointer on LLI structure if used or 0
+*
+******************************************************************************/
+void DMA_Init(uint32_t *src, uint32_t *dest, uint32_t len, uint32_t LLI)
+{
+ LPC_SC->PCONP |= (1 << 29); /* Enable GPDMA clock */
+
+ /*...*/
+}
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.h b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.h
new file mode 100644
index 0000000..3381a2c
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dma.h
@@ -0,0 +1,36 @@
+/****************************************************************************
+ DMA constants definition
+****************************************************************************/
+#ifndef __DMA_H
+#define __DMA_H
+
+#define DMA_SRC 0x2007C000
+#define DMA_DST 0x20080000
+#define DMA_SIZE 0x1000
+
+#define M2M 0x00
+#define M2P 0x01
+#define P2M 0x02
+#define P2P 0x03
+
+#define BURST4 0x04
+#define WORD32_TRANSFER 0x2
+#define INCREMENT 1
+#define TERMINAL_INTERRUPT 0x80000000
+
+#define DMA_CFG ((BURST4 << 12) | (BURST4 << 15) \
+ | (WORD32_TRANSFER << 18) | (WORD32_TRANSFER << 21) | (INCREMENT << 26) | (INCREMENT << 27) | \
+ TERMINAL_INTERRUPT)
+
+void DMA_Init(uint32_t *src, uint32_t *dest, uint32_t len, uint32_t LLI);
+
+typedef struct
+{
+ volatile uint32_t DMACCSrcAddr;
+ volatile uint32_t DMACCDestAddr;
+ volatile uint32_t DMACCLLI;
+ volatile uint32_t DMACCControl;
+} GPDMALLI_t;
+
+#endif
+
diff --git a/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dmatest.c b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dmatest.c
new file mode 100644
index 0000000..c8339c6
--- /dev/null
+++ b/labo4.1_dma.zip_expanded/labo4.1_DMA_new/src/dmatest.c
@@ -0,0 +1,80 @@
+/****************************************************************************
+ Single DMA transfer and DMA with LLI transfer
+****************************************************************************/
+#include <string.h>
+#include <stdint.h>
+#include "dma.h"
+#include "LPC17xx.h"
+
+extern volatile uint32_t DMATCCount;
+
+GPDMALLI_t LLI[2];
+uint32_t src3[DMA_SIZE/16], i;
+uint32_t src1[DMA_SIZE/4], dest[DMA_SIZE/4];
+uint32_t src2[DMA_SIZE/16];
+
+// copy 1 source buffers in 1 destination buffer with DMA
+void single_copy()
+{
+ for (i = 0; i < DMA_SIZE/4; i++)
+ {
+ src1[i] = i;
+ dest[i] = 0; // clear destination vector
+ }
+ DMA_Init(src1, dest, DMA_SIZE/4, 0);
+
+ while (!DMATCCount); /* Wait until DMA is done */
+}
+
+// copy 3 source buffers in 1 destination buffer with DMA linked lists
+void LLI_copy()
+{
+ DMATCCount = 0;
+ for (i = 0; i < DMA_SIZE/8; i++)
+ {
+ src1[i] = i;
+ dest[i] = dest[i+DMA_SIZE/8] = 0; // clear destination vector
+ }
+ for (i = 0; i < DMA_SIZE/16; i++)
+ {
+ src2[i] = i + DMA_SIZE/8;
+ src3[i] = i + DMA_SIZE/8 + DMA_SIZE/16;
+ }
+
+ /*...*/
+
+ DMA_Init(src1, dest, DMA_SIZE/8, (uint32_t)&LLI[0]);
+
+ while (DMATCCount < 3); /* Wait until DMA is done (3 interrupts here) */
+}
+
+/* Verify copy result */
+int check_res()
+{
+ int i;
+
+ for (i = 0; i < DMA_SIZE/4; i++)
+ {
+ if (dest[i]!=i)
+ {
+ return 1; // error
+ }
+ }
+ return 0;
+}
+
+
+int main (void)
+{
+ memset(LLI, 0, sizeof(GPDMALLI_t)*2);
+
+ single_copy();
+ if (check_res())
+ while(1); // error
+ LLI_copy();
+ if (check_res())
+ while(1); // error
+
+ while (1); /* Done here, never exit from main for easier debugging. */
+}
+
--
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