diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2.vhd b/ips/hw/scalp_hl2/src/hdl/scalp_hl2.vhd
index 4eb6709d3ccb9b1ebbd9a7b8a8b28a4bb135b594..ade87d8f922c1117dfe72a8f95e54d7e53fb0746 100644
--- a/ips/hw/scalp_hl2/src/hdl/scalp_hl2.vhd
+++ b/ips/hw/scalp_hl2/src/hdl/scalp_hl2.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.2
 -- Description: scalp_hl2
 --
--- Last update: 2020/12/16 16:24:47
+-- Last update: 2020/12/17 11:55:23
 --
 ---------------------------------------------------------------------------------
 
@@ -303,7 +303,7 @@ architecture arch of scalp_hl2 is
     signal s_idl_value : std_logic_vector((C_REG_IDL_SIZE*G_PORT_COUNT)-1 downto 0);
     signal s_chan_en   : std_logic_vector((C_REG_EN_SIZE*G_PORT_COUNT)-1 downto 0);
 
-    -- AXI4-full <-> BRAM interface/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/ips/hw/scalp_hl2_uart/src/hdl
+    -- AXI4-full <-> BRAM
     signal s_axi_bram_rdata : std_logic_vector(31 downto 0);
     signal s_axi_bram_addr  : std_logic_vector(16 downto 0);
     signal s_axi_bram_wdata : std_logic_vector(31 downto 0);
@@ -438,7 +438,7 @@ scalp_hl2_ctrl_inst : scalp_hl2_ctrl
         i_clk          => AXI_ACLK,
         i_nrst         => AXI_ARESETN,
 
-        -- Config registers/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/ips/hw/scalp_hl2_uart/src/hdl
+        -- Config registers
         ir_mab_clk     => s_mab_clk,
         ir_break_clk   => s_break_clk,
         ir_bit_clk     => s_bit_clk,