From 0f7bc8c153c6d1bfba2548660bb96e3c5d0e6f09 Mon Sep 17 00:00:00 2001
From: Quentin Berthet <quentin.berthet@hesge.ch>
Date: Thu, 17 Dec 2020 16:42:39 +0100
Subject: [PATCH] Change project type from IPS to PERIPHERAL
---
ips/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd | 34 ---
.../drivers/scalp_hl2_v1_0/src/scalp_hl2.c | 23 ++
.../drivers/scalp_hl2_v1_0/src/scalp_hl2.h | 25 ++
.../hw/scalp_hl2/src/hdl/scalp_hl2.vhd | 0
.../scalp_hl2/src/hdl/scalp_hl2_S00_AXI.vhd | 0
.../scalp_hl2/src/hdl/scalp_hl2_S01_AXI.vhd | 0
.../hw/scalp_hl2/src/hdl/scalp_hl2_bram.vhd | 0
.../hw/scalp_hl2/src/hdl/scalp_hl2_ctrl.vhd | 0
.../hw/scalp_hl2/src/hdl/scalp_hl2_pkg.vhd | 0
.../hw/scalp_hl2/src/hdl/scalp_hl2_uart.vhd | 0
.../ip_core/blk_mem_gen_0/blk_mem_gen_0.xci | 0
.../hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd | 230 ++++++++++++++++++
.../vivado/scalp_hl2/2019.2/lin64/.gitignore | 23 ++
.../2019.2/lin64/.scripts/.prompt_colors.tcl | 47 ++++
.../lin64/.scripts/clean_prj_scalp_hl2.sh | 40 +++
.../lin64/.scripts/create_prj_scalp_hl2.sh | 27 ++
.../lin64/.scripts/create_prj_scalp_hl2.tcl | 154 ++++++++++++
.../lin64/.scripts/open_prj_scalp_hl2.sh | 25 ++
.../scalp_hl2/2019.2/lin64/.scripts/utils.tcl | 62 +++++
.../vivado/scalp_hl2/2019.2/lin64/setup.sh | 30 +++
.../2019.2/src/ipi_tcl/scalp_hl2_ipi.tcl | 0
tools/config/scalp_hl2.json | 5 +-
22 files changed, 688 insertions(+), 37 deletions(-)
delete mode 100644 ips/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd
create mode 100644 peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.c
create mode 100644 peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.h
rename {ips => peripherals}/hw/scalp_hl2/src/hdl/scalp_hl2.vhd (100%)
rename {ips => peripherals}/hw/scalp_hl2/src/hdl/scalp_hl2_S00_AXI.vhd (100%)
rename {ips => peripherals}/hw/scalp_hl2/src/hdl/scalp_hl2_S01_AXI.vhd (100%)
rename {ips => peripherals}/hw/scalp_hl2/src/hdl/scalp_hl2_bram.vhd (100%)
rename {ips => peripherals}/hw/scalp_hl2/src/hdl/scalp_hl2_ctrl.vhd (100%)
rename {ips => peripherals}/hw/scalp_hl2/src/hdl/scalp_hl2_pkg.vhd (100%)
rename {ips => peripherals}/hw/scalp_hl2/src/hdl/scalp_hl2_uart.vhd (100%)
rename {ips => peripherals}/hw/scalp_hl2/src/ip_core/blk_mem_gen_0/blk_mem_gen_0.xci (100%)
create mode 100644 peripherals/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd
create mode 100644 peripherals/vivado/scalp_hl2/2019.2/lin64/.gitignore
create mode 100644 peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/.prompt_colors.tcl
create mode 100755 peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/clean_prj_scalp_hl2.sh
create mode 100755 peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.sh
create mode 100644 peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.tcl
create mode 100755 peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/open_prj_scalp_hl2.sh
create mode 100644 peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/utils.tcl
create mode 100755 peripherals/vivado/scalp_hl2/2019.2/lin64/setup.sh
create mode 100644 peripherals/vivado/scalp_hl2/2019.2/src/ipi_tcl/scalp_hl2_ipi.tcl
diff --git a/ips/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd b/ips/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd
deleted file mode 100644
index dffe3d9..0000000
--- a/ips/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd
+++ /dev/null
@@ -1,34 +0,0 @@
-----------------------------------------------------------------------------------
--- _ _
--- | |_ ___ _ __(_)__ _
--- | ' \/ -_) '_ \ / _` |
--- |_||_\___| .__/_\__,_|
--- |_|
---
-----------------------------------------------------------------------------------
---
--- Company: hepia
--- Author: Quentin Berthet <quentin.berthet@hesge.ch
---
--- Module Name: tb_scalp_hl2 - arch
--- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
--- Tool version: 2019.2
--- Description: Testbench for scalp_hl2
---
--- Last update: 2020-12-16 16:20:38
---
----------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity tb_scalp_hl2 is
-end tb_scalp_hl2;
-
-
-architecture behavioral of tb_scalp_hl2 is
-
-begin
-
-end behavioral;
diff --git a/peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.c b/peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.c
new file mode 100644
index 0000000..c223ad5
--- /dev/null
+++ b/peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.c
@@ -0,0 +1,23 @@
+/*********************************************************************************
+ * _ _
+ * | |_ ___ _ __(_)__ _
+ * | ' \/ -_) '_ \ / _` |
+ * |_||_\___| .__/_\__,_|
+ * |_|
+ *
+ *********************************************************************************
+ *
+ * Company: hepia
+ * Author: Quentin Berthet <quentin.berthet@hesge.ch
+ *
+ * Project Name: scalp_hl2
+ * Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+ * Tool version: 2019.2
+ * Description: scalp_hl2 software driver source file
+ *
+ * Last update: 2020-12-17 16:43:02
+ *
+ ********************************************************************************/
+
+#include "scalp_hl2.h"
+
diff --git a/peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.h b/peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.h
new file mode 100644
index 0000000..364d9e7
--- /dev/null
+++ b/peripherals/hw/scalp_hl2/drivers/scalp_hl2_v1_0/src/scalp_hl2.h
@@ -0,0 +1,25 @@
+/*********************************************************************************
+ * _ _
+ * | |_ ___ _ __(_)__ _
+ * | ' \/ -_) '_ \ / _` |
+ * |_||_\___| .__/_\__,_|
+ * |_|
+ *
+ *********************************************************************************
+ *
+ * Company: hepia
+ * Author: Quentin Berthet <quentin.berthet@hesge.ch
+ *
+ * Project Name: scalp_hl2
+ * Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+ * Tool version: 2019.2
+ * Description: scalp_hl2 software driver header file
+ *
+ * Last update: 2020-12-17 16:43:02
+ *
+ ********************************************************************************/
+
+#ifndef SCALP_HL2_H
+#define SCALP_HL2_H
+
+#endif // SCALP_HL2_H
diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2.vhd b/peripherals/hw/scalp_hl2/src/hdl/scalp_hl2.vhd
similarity index 100%
rename from ips/hw/scalp_hl2/src/hdl/scalp_hl2.vhd
rename to peripherals/hw/scalp_hl2/src/hdl/scalp_hl2.vhd
diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2_S00_AXI.vhd b/peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_S00_AXI.vhd
similarity index 100%
rename from ips/hw/scalp_hl2/src/hdl/scalp_hl2_S00_AXI.vhd
rename to peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_S00_AXI.vhd
diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2_S01_AXI.vhd b/peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_S01_AXI.vhd
similarity index 100%
rename from ips/hw/scalp_hl2/src/hdl/scalp_hl2_S01_AXI.vhd
rename to peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_S01_AXI.vhd
diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2_bram.vhd b/peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_bram.vhd
similarity index 100%
rename from ips/hw/scalp_hl2/src/hdl/scalp_hl2_bram.vhd
rename to peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_bram.vhd
diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2_ctrl.vhd b/peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_ctrl.vhd
similarity index 100%
rename from ips/hw/scalp_hl2/src/hdl/scalp_hl2_ctrl.vhd
rename to peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_ctrl.vhd
diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2_pkg.vhd b/peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_pkg.vhd
similarity index 100%
rename from ips/hw/scalp_hl2/src/hdl/scalp_hl2_pkg.vhd
rename to peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_pkg.vhd
diff --git a/ips/hw/scalp_hl2/src/hdl/scalp_hl2_uart.vhd b/peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_uart.vhd
similarity index 100%
rename from ips/hw/scalp_hl2/src/hdl/scalp_hl2_uart.vhd
rename to peripherals/hw/scalp_hl2/src/hdl/scalp_hl2_uart.vhd
diff --git a/ips/hw/scalp_hl2/src/ip_core/blk_mem_gen_0/blk_mem_gen_0.xci b/peripherals/hw/scalp_hl2/src/ip_core/blk_mem_gen_0/blk_mem_gen_0.xci
similarity index 100%
rename from ips/hw/scalp_hl2/src/ip_core/blk_mem_gen_0/blk_mem_gen_0.xci
rename to peripherals/hw/scalp_hl2/src/ip_core/blk_mem_gen_0/blk_mem_gen_0.xci
diff --git a/peripherals/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd b/peripherals/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd
new file mode 100644
index 0000000..8f9f1ee
--- /dev/null
+++ b/peripherals/hw/scalp_hl2/src/sim/tb_scalp_hl2.vhd
@@ -0,0 +1,230 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Quentin Berthet <quentin.berthet@hesge.ch
+--
+-- Module Name: tb_scalp_hl2 - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: Testbench for scalp_hl2
+--
+-- Last update: 2020-12-17 16:43:02
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_hl2 is
+end tb_scalp_hl2;
+
+
+architecture behavioral of tb_scalp_hl2 is
+
+ constant C_S00_AXI_DATA_WIDTH : integer := 32;
+ constant C_S00_AXI_ADDR_WIDTH : integer := 5;
+
+ component scalp_hl2 is
+ generic (
+ C_S00_AXI_DATA_WIDTH : integer;
+ C_S00_AXI_ADDR_WIDTH : integer
+ );
+ port (
+ s00_axi_aclk : in std_logic;
+ s00_axi_aresetn : in std_logic;
+ s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+ s00_axi_awprot : in std_logic_vector(2 downto 0);
+ s00_axi_awvalid : in std_logic;
+ s00_axi_awready : out std_logic;
+ s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+ s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
+ s00_axi_wvalid : in std_logic;
+ s00_axi_wready : out std_logic;
+ s00_axi_bresp : out std_logic_vector(1 downto 0);
+ s00_axi_bvalid : out std_logic;
+ s00_axi_bready : in std_logic;
+ s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+ s00_axi_arprot : in std_logic_vector(2 downto 0);
+ s00_axi_arvalid : in std_logic;
+ s00_axi_arready : out std_logic;
+ s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+ s00_axi_rresp : out std_logic_vector(1 downto 0);
+ s00_axi_rvalid : out std_logic;
+ s00_axi_rready : in std_logic
+ );
+ end component scalp_hl2;
+
+ signal s00_axi_aclk : std_logic := '1';
+ signal s00_axi_aresetn : std_logic := '0';
+
+ signal s00_axi_awaddr : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal s00_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
+ signal s00_axi_awvalid : std_logic := '0';
+ signal s00_axi_awready : std_logic;
+ signal s00_axi_wdata : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal s00_axi_wstrb : std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0) := (others => '0');
+ signal s00_axi_wvalid : std_logic := '0';
+ signal s00_axi_wready : std_logic;
+ signal s00_axi_bresp : std_logic_vector(1 downto 0);
+ signal s00_axi_bvalid : std_logic;
+ signal s00_axi_bready : std_logic := '0';
+ signal s00_axi_araddr : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal s00_axi_arprot : std_logic_vector(2 downto 0) := (others => '0');
+ signal s00_axi_arvalid : std_logic := '0';
+ signal s00_axi_arready : std_logic;
+ signal s00_axi_rdata : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+ signal s00_axi_rresp : std_logic_vector(1 downto 0);
+ signal s00_axi_rvalid : std_logic;
+ signal s00_axi_rready : std_logic := '0';
+
+ constant s00_axi_aclk_period : time := 10 ns;
+
+ -- Registers offset
+ constant DATA_0_REG_OFFSET : integer := 0; -- Data 0 register
+ constant DATA_1_REG_OFFSET : integer := 4; -- Data 1 register
+
+ -- Data read from registers
+ signal rd_data : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
+
+begin
+
+ scalp_hl2_i : entity work.scalp_hl2
+ generic map (
+ C_S00_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
+ C_S00_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
+ )
+ port map (
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_awaddr => s00_axi_awaddr,
+ s00_axi_awprot => s00_axi_awprot,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_wdata => s00_axi_wdata,
+ s00_axi_wstrb => s00_axi_wstrb,
+ s00_axi_wvalid => s00_axi_wvalid,
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_bresp => s00_axi_bresp,
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_araddr => s00_axi_araddr,
+ s00_axi_arprot => s00_axi_arprot,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_rdata => s00_axi_rdata,
+ s00_axi_rresp => s00_axi_rresp,
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_rready => s00_axi_rready
+ );
+
+
+ s00_axi_aclk <= not s00_axi_aclk after s00_axi_aclk_period / 2;
+
+
+ waveform_proc : process
+
+ ---------------------------------------------------------------------------------
+ -- Write a value in an AXI register
+ ---------------------------------------------------------------------------------
+ procedure write_reg(
+ reg_offset : integer;
+ wr_data : std_logic_vector((C_S00_AXI_DATA_WIDTH-1) downto 0)
+ ) is
+ begin
+
+ s00_axi_awaddr <= std_logic_vector(to_unsigned(reg_offset, C_S00_AXI_ADDR_WIDTH));
+ s00_axi_awvalid <= '1';
+ s00_axi_wdata <= wr_data;
+ s00_axi_wvalid <= '1';
+ s00_axi_wstrb <= (others => '1');
+ if s00_axi_awready = '0' then
+ wait until s00_axi_awready = '1';
+ end if;
+ if s00_axi_wready = '0' then
+ wait until s00_axi_wready = '1';
+ end if;
+ wait for s00_axi_aclk_period;
+ s00_axi_wvalid <= '0';
+ s00_axi_awvalid <= '0';
+
+ if s00_axi_bvalid = '0' then
+ wait until s00_axi_bvalid = '1';
+ end if;
+ wait for s00_axi_aclk_period;
+ s00_axi_bready <= '1';
+ wait for s00_axi_aclk_period;
+ s00_axi_bready <= '0';
+
+ end procedure write_reg;
+
+ ---------------------------------------------------------------------------------
+ -- Read a value from an AXI register
+ ---------------------------------------------------------------------------------
+ procedure read_reg(
+ reg_offset : in integer;
+ signal rd_data : out std_logic_vector((C_S00_AXI_DATA_WIDTH-1) downto 0)
+ ) is
+ begin
+
+ s00_axi_araddr <= std_logic_vector(to_unsigned(reg_offset, C_S00_AXI_ADDR_WIDTH));
+ s00_axi_arvalid <= '1';
+ if s00_axi_arready = '0' then
+ wait until s00_axi_arready = '1';
+ end if;
+ if s00_axi_rvalid = '0' then
+ wait until s00_axi_rvalid = '1';
+ end if;
+ wait for s00_axi_aclk_period;
+ s00_axi_arvalid <= '0';
+ s00_axi_rready <= '1';
+ rd_data <= s00_axi_rdata;
+ wait for s00_axi_aclk_period;
+ s00_axi_rready <= '0';
+
+ end procedure read_reg;
+
+ begin
+
+ -- hold reset
+ s00_axi_aresetn <= '0';
+ wait for s00_axi_aclk_period * 10;
+ s00_axi_aresetn <= '1';
+
+ -- Write in register 0
+ report "Write Data 0 register" severity note;
+ write_reg(DATA_0_REG_OFFSET, X"CAFEFACE");
+ wait for s00_axi_aclk_period * 4;
+
+ -- Read and check register 0
+ report "Read Data 0 register" severity note;
+ read_reg(DATA_0_REG_OFFSET, rd_data);
+ assert rd_data = X"CAFEFACE" report "# Error reading Data 0" severity failure;
+ wait for s00_axi_aclk_period * 20;
+
+
+ -- Write in register 1
+ report "Write Data 1 register" severity note;
+ write_reg(DATA_1_REG_OFFSET, X"DEADBEEF");
+ wait for s00_axi_aclk_period * 4;
+
+ -- Read and check register 1
+ report "Read Data 1 register" severity note;
+ read_reg(DATA_1_REG_OFFSET, rd_data);
+ assert rd_data = X"DEADBEEF" report "# Error reading Data 1" severity failure;
+ wait for s00_axi_aclk_period * 20;
+
+ assert false report "-- Simulation completed successfully --" severity failure;
+
+ wait;
+
+ end process waveform_proc;
+
+end behavioral;
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/.gitignore b/peripherals/vivado/scalp_hl2/2019.2/lin64/.gitignore
new file mode 100644
index 0000000..1100cb7
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/.gitignore
@@ -0,0 +1,23 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Git ignore file
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_hl2
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/.prompt_colors.tcl b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000..783d670
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Console color print utility
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/clean_prj_scalp_hl2.sh b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/clean_prj_scalp_hl2.sh
new file mode 100755
index 0000000..f00819c
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/clean_prj_scalp_hl2.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Cleanup project directory
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_hl2/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.sh b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.sh
new file mode 100755
index 0000000..4d29431
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_hl2.tcl -notrace
+echo "> Done"
+
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.tcl b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.tcl
new file mode 100644
index 0000000..5edd0d6
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/create_prj_scalp_hl2.tcl
@@ -0,0 +1,154 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script for re-creating Vivado project 'scalp_hl2'
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_hl2"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set hdl_src_dir "${src_dir}/hdl"
+ set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ set hdl_src_dir "${comp_src_dir}/hdl"
+ set sim_src_dir "${comp_src_dir}/sim"
+}
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+ add_files -norecurse $hdl_src_file_list
+} else {
+ print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
+ # add IPs source files
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # add IPs source files
+ read_ip $comp_src_dir/ip_core/blk_mem_gen_0/blk_mem_gen_0.xci
+
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+ add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+ update_compile_order -fileset sim_1
+ print_status "Add simulation sources" "OK"
+} else {
+ print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for simulation sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/open_prj_scalp_hl2.sh b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/open_prj_scalp_hl2.sh
new file mode 100755
index 0000000..2d1e45c
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/open_prj_scalp_hl2.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_hl2/scalp_hl2.xpr
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/utils.tcl b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000..813b794
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/peripherals/vivado/scalp_hl2/2019.2/lin64/setup.sh b/peripherals/vivado/scalp_hl2/2019.2/lin64/setup.sh
new file mode 100755
index 0000000..48a3d0f
--- /dev/null
+++ b/peripherals/vivado/scalp_hl2/2019.2/lin64/setup.sh
@@ -0,0 +1,30 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Quentin Berthet <quentin.berthet@hesge.ch
+#
+# Project Name: scalp_hl2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2020-12-17 17:13:44
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_hl2.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_hl2.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_hl2.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_hl2.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_hl2.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_hl2.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_scalp_hl2.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_hl2.sh && cd ..'
diff --git a/peripherals/vivado/scalp_hl2/2019.2/src/ipi_tcl/scalp_hl2_ipi.tcl b/peripherals/vivado/scalp_hl2/2019.2/src/ipi_tcl/scalp_hl2_ipi.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/tools/config/scalp_hl2.json b/tools/config/scalp_hl2.json
index 83fbc8f..596a939 100644
--- a/tools/config/scalp_hl2.json
+++ b/tools/config/scalp_hl2.json
@@ -6,10 +6,9 @@
"project" : {
"name" : "scalp_hl2",
"type" : "COMP_PRJ_TYPE",
- "category" : "IPS",
+ "category" : "PERIPHERALS",
"vivado_version" : "2019.2",
- "target_language" : "VHDL",
- "vhdl_version" : "VHDL 2008"
+ "target_language" : "VHDL"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
--
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