From 1680a27cba60f5bfe111d25c11d9abc21de0f71b Mon Sep 17 00:00:00 2001 From: "joachim.schmidt" <joachim.schmidt@hesge.ch> Date: Mon, 21 Sep 2020 11:04:56 +0200 Subject: [PATCH] Delete vivado project. --- .../aurora_drp_pkg.cache/wt/webtalk_pa.xml | 40 ---- .../lin64/aurora_drp_pkg/aurora_drp_pkg.xpr | 192 ------------------ 2 files changed, 232 deletions(-) delete mode 100644 packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.cache/wt/webtalk_pa.xml delete mode 100644 packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.cache/wt/webtalk_pa.xml b/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.cache/wt/webtalk_pa.xml deleted file mode 100644 index a04ac1b..0000000 --- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.cache/wt/webtalk_pa.xml +++ /dev/null @@ -1,40 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" ?> -<document> -<!--The data in this file is primarily intended for consumption by Xilinx tools. -The structure and the elements are likely to change over the next few releases. -This means code written to parse this file will need to be revisited each subsequent release.--> -<application name="pa" timeStamp="Mon Sep 21 10:59:22 2020"> -<section name="Project Information" visible="false"> -<property name="ProjectID" value="7b4885f2b9e8426fb39a5571b8d7fbac" type="ProjectID"/> -<property name="ProjectIteration" value="1" type="ProjectIteration"/> -</section> -<section name="PlanAhead Usage" visible="true"> -<item name="Project Data"> -<property name="SrcSetCount" value="1" type="SrcSetCount"/> -<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> -<property name="DesignMode" value="RTL" type="DesignMode"/> -<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/> -<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> -</item> -<item name="Java Command Handlers"> -<property name="FileExit" value="1" type="JavaHandler"/> -</item> -<item name="Gui Handlers"> -<property name="BaseDialog_OK" value="1" type="GuiHandlerData"/> -<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="10" type="GuiHandlerData"/> -<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/> -<property name="MainMenuMgr_EXPORT" value="2" type="GuiHandlerData"/> -<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/> -<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/> -<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/> -<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/> -<property name="PACommandNames_EXIT" value="1" type="GuiHandlerData"/> -</item> -<item name="Other"> -<property name="GuiMode" value="159" type="GuiMode"/> -<property name="BatchMode" value="0" type="BatchMode"/> -<property name="TclMode" value="149" type="TclMode"/> -</item> -</section> -</application> -</document> diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr b/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr deleted file mode 100644 index 54e6c0c..0000000 --- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr +++ /dev/null @@ -1,192 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2019.2 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> - -<Project Version="7" Minor="44" Path="/home/jo/Documents/Projets/Hepia/scalp_firmware/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr"> - <DefaultLaunch Dir="$PRUNDIR"/> - <Configuration> - <Option Name="Id" Val="05f42d69fe654438b814471c264b24b2"/> - <Option Name="Part" Val="xc7z015clg485-2"/> - <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> - <Option Name="CompiledLibDirXSim" Val=""/> - <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> - <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> - <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/> - <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> - <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> - <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> - <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> - <Option Name="TargetLanguage" Val="VHDL"/> - <Option Name="BoardPart" Val=""/> - <Option Name="ActiveSimSet" Val="sim_1"/> - <Option Name="DefaultLib" Val="xil_defaultlib"/> - <Option Name="ProjectType" Val="Default"/> - <Option Name="IPRepoPath" Val="$PPRDIR/../../../../../hw"/> - <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> - <Option Name="IPCachePermission" Val="read"/> - <Option Name="IPCachePermission" Val="write"/> - <Option Name="EnableCoreContainer" Val="FALSE"/> - <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> - <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> - <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> - <Option Name="EnableBDX" Val="FALSE"/> - <Option Name="WTXSimLaunchSim" Val="0"/> - <Option Name="WTModelSimLaunchSim" Val="0"/> - <Option Name="WTQuestaLaunchSim" Val="0"/> - <Option Name="WTIesLaunchSim" Val="0"/> - <Option Name="WTVcsLaunchSim" Val="0"/> - <Option Name="WTRivieraLaunchSim" Val="0"/> - <Option Name="WTActivehdlLaunchSim" Val="0"/> - <Option Name="WTXSimExportSim" Val="0"/> - <Option Name="WTModelSimExportSim" Val="0"/> - <Option Name="WTQuestaExportSim" Val="0"/> - <Option Name="WTIesExportSim" Val="0"/> - <Option Name="WTVcsExportSim" Val="0"/> - <Option Name="WTRivieraExportSim" Val="0"/> - <Option Name="WTActivehdlExportSim" Val="0"/> - <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> - <Option Name="XSimRadix" Val="hex"/> - <Option Name="XSimTimeUnit" Val="ns"/> - <Option Name="XSimArrayDisplayLimit" Val="1024"/> - <Option Name="XSimTraceLimit" Val="65536"/> - <Option Name="SimTypes" Val="rtl"/> - <Option Name="SimTypes" Val="bfm"/> - <Option Name="SimTypes" Val="tlm"/> - <Option Name="SimTypes" Val="tlm_dpi"/> - <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> - <Option Name="DcpsUptoDate" Val="TRUE"/> - </Configuration> - <FileSets Version="1" Minor="31"> - <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> - <Filter Type="Srcs"/> - <File Path="$PPRDIR/../../../../../hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd"> - <FileInfo SFType="VHDL2008"> - <Attr Name="AutoDisabled" Val="1"/> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="simulation"/> - </FileInfo> - </File> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopModule" Val="aurora_drp_pkg"/> - </Config> - </FileSet> - <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> - <Filter Type="Constrs"/> - <Config> - <Option Name="ConstrsType" Val="XDC"/> - </Config> - </FileSet> - <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> - <File Path="$PPRDIR/../../../../../hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd"> - <FileInfo SFType="VHDL2008"> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="simulation"/> - </FileInfo> - </File> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopModule" Val="tb_aurora_drp_pkg"/> - <Option Name="TopLib" Val="xil_defaultlib"/> - <Option Name="TopAutoSet" Val="TRUE"/> - <Option Name="TransportPathDelay" Val="0"/> - <Option Name="TransportIntDelay" Val="0"/> - <Option Name="SelectedSimModel" Val="rtl"/> - <Option Name="SrcSet" Val="sources_1"/> - </Config> - </FileSet> - <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1"> - <Filter Type="Utils"/> - <Config> - <Option Name="TopAutoSet" Val="TRUE"/> - </Config> - </FileSet> - </FileSets> - <Simulators> - <Simulator Name="XSim"> - <Option Name="Description" Val="Vivado Simulator"/> - <Option Name="CompiledLib" Val="0"/> - </Simulator> - <Simulator Name="ModelSim"> - <Option Name="Description" Val="ModelSim Simulator"/> - </Simulator> - <Simulator Name="Questa"> - <Option Name="Description" Val="Questa Advanced Simulator"/> - </Simulator> - <Simulator Name="IES"> - <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/> - </Simulator> - <Simulator Name="Xcelium"> - <Option Name="Description" Val="Xcelium Parallel Simulator"/> - </Simulator> - <Simulator Name="VCS"> - <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> - </Simulator> - <Simulator Name="Riviera"> - <Option Name="Description" Val="Riviera-PRO Simulator"/> - </Simulator> - </Simulators> - <Runs Version="1" Minor="11"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> - <Step Id="synth_design"/> - </Strategy> - <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - <RQSFiles/> - </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> - <Step Id="init_design"/> - <Step Id="opt_design"/> - <Step Id="power_opt_design"/> - <Step Id="place_design"/> - <Step Id="post_place_power_opt_design"/> - <Step Id="phys_opt_design" EnableStepBool="1"/> - <Step Id="route_design"/> - <Step Id="post_route_phys_opt_design"/> - <Step Id="write_bitstream"/> - </Strategy> - <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - <RQSFiles/> - </Run> - </Runs> - <Board/> - <DashboardSummary Version="1" Minor="0"> - <Dashboards> - <Dashboard Name="default_dashboard"> - <Gadgets> - <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> - </Gadget> - <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> - </Gadget> - <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> - </Gadget> - <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> - </Gadget> - <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> - <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> - <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> - <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> - </Gadget> - <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> - </Gadget> - </Gadgets> - </Dashboard> - <CurrentDashboard>default_dashboard</CurrentDashboard> - </Dashboards> - </DashboardSummary> -</Project> -- GitLab