diff --git a/tools/config/phy_aurora.json b/tools/config/phy_aurora.json
new file mode 100644
index 0000000000000000000000000000000000000000..37d71f408cb11b1d4ce9c41be0a7b25dd82171b7
--- /dev/null
+++ b/tools/config/phy_aurora.json
@@ -0,0 +1,17 @@
+{
+    "author" : {
+        "name"  : "Joachim Schmidt",
+        "email" : "<joachim.schmidt@hesge.ch>"
+    },
+    "project" : {
+        "name"            : "phy_aurora",
+        "type"            : "COMP_PRJ_TYPE",
+        "category"        : "IPS",
+        "vivado_version"  : "2019.2",
+        "target_language" : "VHDL"
+    },
+    "hardware": {
+        "part_name": "xc7k325tffg900-2",
+        "board_name": "SCALP"
+    }
+}
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
new file mode 100644
index 0000000000000000000000000000000000000000..747420d17d14474c85bbacc658a39df436b56e7c
--- /dev/null
+++ b/tools/config/scalp_firmware.json
@@ -0,0 +1,17 @@
+{
+    "author" : {
+        "name"  : "Joachim Schmidt",
+        "email" : "<joachim.schmidt@hesge.ch>"
+    },
+    "project" : {
+        "name"            : "scalp_firmware",
+        "type"            : "DESIGN_PRJ_TYPE",
+        "category"        : "DESIGNS",
+        "vivado_version"  : "2019.2",
+        "target_language" : "VHDL"
+    },
+    "hardware" : {
+        "part_name"  : "xc7z015clg485-2",
+        "board_name" : "SCALP"
+    }
+}