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Commit 53fc6fb8 authored by joachim.schmidt's avatar joachim.schmidt
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Creation of a design type project.

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designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc 0 → 100644
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############################################################################
# Programmable Logic placement constraints #
############################################################################
##### USB interface (bank 13) #####
# USB_VBUS_PWRFAULT_i
set_property PACKAGE_PIN AA19 [get_ports UsbVbusPwrFaultxSI]
set_property IOSTANDARD LVCMOS25 [get_ports UsbVbusPwrFaultxSI]
##### PLL interface (banks 35 and 34) #####
# PLL_2V5_CLKuWire_o
set_property PACKAGE_PIN G8 [get_ports Pll2V5ClkuWirexCO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkuWirexCO]
# PLL_2V5_DATAuWire_o
set_property PACKAGE_PIN G7 [get_ports Pll2V5DatauWirexSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5DatauWirexSO]
# PLL_2V5_LEuWire_o
set_property PACKAGE_PIN G6 [get_ports Pll2V5LEuWirexSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LEuWirexSO]
# PLL_2V5_GOE_o
set_property PACKAGE_PIN F6 [get_ports Pll2V5GOExSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5GOExSO]
# PLL_2V5_LD_i
set_property PACKAGE_PIN H6 [get_ports Pll2V5LDxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LDxSI]
# PLL_2V5_SYNC_n_o
set_property PACKAGE_PIN H5 [get_ports Pll2V5SyncxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5SyncxSO]
# PLL_2V5_CLKIN0_LOS_i (bank 34)
set_property PACKAGE_PIN J3 [get_ports Pll2V5ClkIn0LOSxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn0LOSxSI]
# PLL_2V5_CLKIN1_LOS_i (bank 34)
set_property PACKAGE_PIN K2 [get_ports Pll2V5ClkIn1LOSxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
##### GTP interfaces (bank 112) #####
set_property PACKAGE_PIN "U9" [get_ports "GTPRefClk0PxCI"]
set_property PACKAGE_PIN "V9" [get_ports "GTPRefClk0NxCI"]
set_property PACKAGE_PIN "U5" [get_ports "GTPRefClk1PxCI"]
set_property PACKAGE_PIN "V5" [get_ports "GTPRefClk1NxCI"]
set_property PACKAGE_PIN "Y8" [get_ports "GTPFromNorthNxSI"]
set_property PACKAGE_PIN "W8" [get_ports "GTPFromNorthPxSI"]
set_property PACKAGE_PIN "Y4" [get_ports "GTPToNorthNxSO"]
set_property PACKAGE_PIN "W4" [get_ports "GTPToNorthPxSO"]
set_property PACKAGE_PIN "AB7" [get_ports "GTPFromSouthNxSI"]
set_property PACKAGE_PIN "AA7" [get_ports "GTPFromSouthPxSI"]
set_property PACKAGE_PIN "AB3" [get_ports "GTPToSouthNxSO"]
set_property PACKAGE_PIN "AA3" [get_ports "GTPToSouthPxSO"]
set_property PACKAGE_PIN "AA9" [get_ports "GTPFromEastPxSI"]
set_property PACKAGE_PIN "AB9" [get_ports "GTPFromEastNxSI"]
set_property PACKAGE_PIN "AA5" [get_ports "GTPToEastPxSO"]
set_property PACKAGE_PIN "AB5" [get_ports "GTPToEastNxSO"]
set_property PACKAGE_PIN "W6" [get_ports "GTPFromWestPxSI"]
set_property PACKAGE_PIN "Y6" [get_ports "GTPFromWestNxSI"]
set_property PACKAGE_PIN "W2" [get_ports "GTPToWestPxSO"]
set_property PACKAGE_PIN "Y2" [get_ports "GTPToWestNxSO"]
##### LVDS links towards edge connectors #####
# North (bank 35)
set_property PACKAGE_PIN "E8" [get_ports "LVDS2V5North7PxSIO"]
set_property PACKAGE_PIN "D8" [get_ports "LVDS2V5North7NxSIO"]
set_property PACKAGE_PIN "D7" [get_ports "LVDS2V5North6PxSIO"]
set_property PACKAGE_PIN "D6" [get_ports "LVDS2V5North6NxSIO"]
set_property PACKAGE_PIN "C8" [get_ports "LVDS2V5North5PxSIO"]
set_property PACKAGE_PIN "B8" [get_ports "LVDS2V5North5NxSIO"]
set_property PACKAGE_PIN "B7" [get_ports "LVDS2V5North4PxSIO"]
set_property PACKAGE_PIN "B6" [get_ports "LVDS2V5North4NxSIO"]
set_property PACKAGE_PIN "A7" [get_ports "LVDS2V5North3PxSIO"]
set_property PACKAGE_PIN "A6" [get_ports "LVDS2V5North3NxSIO"]
set_property PACKAGE_PIN "A5" [get_ports "LVDS2V5North2PxSIO"]
set_property PACKAGE_PIN "A4" [get_ports "LVDS2V5North2NxSIO"]
set_property PACKAGE_PIN "B2" [get_ports "LVDS2V5North1PxSIO"]
set_property PACKAGE_PIN "B1" [get_ports "LVDS2V5North1NxSIO"]
set_property PACKAGE_PIN "A2" [get_ports "LVDS2V5North0PxSIO"]
set_property PACKAGE_PIN "A1" [get_ports "LVDS2V5North0NxSIO"]
# South (bank 13)
set_property PACKAGE_PIN "V15" [get_ports "LVDS2V5South7PxSIO"]
set_property PACKAGE_PIN "W15" [get_ports "LVDS2V5South7NxSIO"]
set_property PACKAGE_PIN "AB13" [get_ports "LVDS2V5South6PxSIO"]
set_property PACKAGE_PIN "AB14" [get_ports "LVDS2V5South6NxSIO"]
set_property PACKAGE_PIN "V13" [get_ports "LVDS2V5South5PxSIO"]
set_property PACKAGE_PIN "V14" [get_ports "LVDS2V5South5NxSIO"]
set_property PACKAGE_PIN "Y12" [get_ports "LVDS2V5South4PxSIO"]
set_property PACKAGE_PIN "Y13" [get_ports "LVDS2V5South4NxSIO"]
set_property PACKAGE_PIN "AA12" [get_ports "LVDS2V5South3PxSIO"]
set_property PACKAGE_PIN "AB12" [get_ports "LVDS2V5South3NxSIO"]
set_property PACKAGE_PIN "W12" [get_ports "LVDS2V5South2PxSIO"]
set_property PACKAGE_PIN "W13" [get_ports "LVDS2V5South2NxSIO"]
set_property PACKAGE_PIN "AA11" [get_ports "LVDS2V5South1PxSIO"]
set_property PACKAGE_PIN "AB11" [get_ports "LVDS2V5South1NxSIO"]
set_property PACKAGE_PIN "V11" [get_ports "LVDS2V5South0PxSIO"]
set_property PACKAGE_PIN "W11" [get_ports "LVDS2V5South0NxSIO"]
# East (bank 13)
set_property PACKAGE_PIN "V16" [get_ports "LVDS2V5East7PxSIO"]
set_property PACKAGE_PIN "W16" [get_ports "LVDS2V5East7NxSIO"]
set_property PACKAGE_PIN "W17" [get_ports "LVDS2V5East6PxSIO"]
set_property PACKAGE_PIN "Y17" [get_ports "LVDS2V5East6NxSIO"]
set_property PACKAGE_PIN "U13" [get_ports "LVDS2V5East5PxSIO"]
set_property PACKAGE_PIN "U14" [get_ports "LVDS2V5East5NxSIO"]
set_property PACKAGE_PIN "V18" [get_ports "LVDS2V5East4PxSIO"]
set_property PACKAGE_PIN "W18" [get_ports "LVDS2V5East4NxSIO"]
set_property PACKAGE_PIN "U11" [get_ports "LVDS2V5East3PxSIO"]
set_property PACKAGE_PIN "U12" [get_ports "LVDS2V5East3NxSIO"]
set_property PACKAGE_PIN "U19" [get_ports "LVDS2V5East2PxSIO"]
set_property PACKAGE_PIN "V19" [get_ports "LVDS2V5East2NxSIO"]
set_property PACKAGE_PIN "R17" [get_ports "LVDS2V5East1PxSIO"]
set_property PACKAGE_PIN "T17" [get_ports "LVDS2V5East1NxSIO"]
set_property PACKAGE_PIN "U17" [get_ports "LVDS2V5East0PxSIO"]
set_property PACKAGE_PIN "U18" [get_ports "LVDS2V5East0NxSIO"]
# West (bank 35)
set_property PACKAGE_PIN "H4" [get_ports "LVDS2V5West7PxSIO"]
set_property PACKAGE_PIN "H3" [get_ports "LVDS2V5West7NxSIO"]
set_property PACKAGE_PIN "H1" [get_ports "LVDS2V5West6PxSIO"]
set_property PACKAGE_PIN "G1" [get_ports "LVDS2V5West6NxSIO"]
set_property PACKAGE_PIN "G3" [get_ports "LVDS2V5West5PxSIO"]
set_property PACKAGE_PIN "G2" [get_ports "LVDS2V5West5NxSIO"]
set_property PACKAGE_PIN "F2" [get_ports "LVDS2V5West4PxSIO"]
set_property PACKAGE_PIN "F1" [get_ports "LVDS2V5West4NxSIO"]
set_property PACKAGE_PIN "G4" [get_ports "LVDS2V5West3PxSIO"]
set_property PACKAGE_PIN "F4" [get_ports "LVDS2V5West3NxSIO"]
set_property PACKAGE_PIN "E2" [get_ports "LVDS2V5West2PxSIO"]
set_property PACKAGE_PIN "D2" [get_ports "LVDS2V5West2NxSIO"]
set_property PACKAGE_PIN "E4" [get_ports "LVDS2V5West1PxSIO"]
set_property PACKAGE_PIN "E3" [get_ports "LVDS2V5West1NxSIO"]
set_property PACKAGE_PIN "D1" [get_ports "LVDS2V5West0PxSIO"]
set_property PACKAGE_PIN "C1" [get_ports "LVDS2V5West0NxSIO"]
##### LVDS links towards top-bottom connectors #####
# Top (bank 34)
set_property PACKAGE_PIN "J8" [get_ports "LVDS2V5Top7PxSIO"]
set_property PACKAGE_PIN "K8" [get_ports "LVDS2V5Top7NxSIO"]
set_property PACKAGE_PIN "K7" [get_ports "LVDS2V5Top6PxSIO"]
set_property PACKAGE_PIN "L7" [get_ports "LVDS2V5Top6NxSIO"]
set_property PACKAGE_PIN "N8" [get_ports "LVDS2V5Top5PxSIO"]
set_property PACKAGE_PIN "P8" [get_ports "LVDS2V5Top5NxSIO"]
set_property PACKAGE_PIN "M8" [get_ports "LVDS2V5Top4PxSIO"]
set_property PACKAGE_PIN "M7" [get_ports "LVDS2V5Top4NxSIO"]
set_property PACKAGE_PIN "L6" [get_ports "LVDS2V5Top3PxSIO"]
set_property PACKAGE_PIN "M6" [get_ports "LVDS2V5Top3NxSIO"]
set_property PACKAGE_PIN "J7" [get_ports "LVDS2V5Top2PxSIO"]
set_property PACKAGE_PIN "J6" [get_ports "LVDS2V5Top2NxSIO"]
set_property PACKAGE_PIN "J5" [get_ports "LVDS2V5Top1PxSIO"]
set_property PACKAGE_PIN "K5" [get_ports "LVDS2V5Top1NxSIO"]
set_property PACKAGE_PIN "J2" [get_ports "LVDS2V5Top0PxSIO"]
set_property PACKAGE_PIN "J1" [get_ports "LVDS2V5Top0NxSIO"]
# Bottom (bank 34)
set_property PACKAGE_PIN "N6" [get_ports "LVDS2V5Bottom7PxSIO"]
set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
set_property PACKAGE_PIN "P6" [get_ports "LVDS2V5Bottom6PxSIO"]
set_property PACKAGE_PIN "P5" [get_ports "LVDS2V5Bottom6NxSIO"]
set_property PACKAGE_PIN "R5" [get_ports "LVDS2V5Bottom5PxSIO"]
set_property PACKAGE_PIN "R4" [get_ports "LVDS2V5Bottom5NxSIO"]
set_property PACKAGE_PIN "R3" [get_ports "LVDS2V5Bottom4PxSIO"]
set_property PACKAGE_PIN "R2" [get_ports "LVDS2V5Bottom4NxSIO"]
set_property PACKAGE_PIN "P3" [get_ports "LVDS2V5Bottom3PxSIO"]
set_property PACKAGE_PIN "P2" [get_ports "LVDS2V5Bottom3NxSIO"]
set_property PACKAGE_PIN "N1" [get_ports "LVDS2V5Bottom2PxSIO"]
set_property PACKAGE_PIN "P1" [get_ports "LVDS2V5Bottom2NxSIO"]
set_property PACKAGE_PIN "N4" [get_ports "LVDS2V5Bottom1PxSIO"]
set_property PACKAGE_PIN "N3" [get_ports "LVDS2V5Bottom1NxSIO"]
set_property PACKAGE_PIN "M2" [get_ports "LVDS2V5Bottom0PxSIO"]
set_property PACKAGE_PIN "M1" [get_ports "LVDS2V5Bottom0NxSIO"]
##### RGB LEDs (banks 34 and 13) #####
# LED1_2V5_R_o (bank 34)
set_property PACKAGE_PIN "L2" [get_ports "Led12V5RxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led12V5RxSO"]
# LED1_2V5_G_o (bank 34)
set_property PACKAGE_PIN "L1" [get_ports "Led12V5GxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led12V5GxSO"]
# LED1_2V5_B_o (bank 34)
set_property PACKAGE_PIN "R8" [get_ports "Led12V5BxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led12V5BxSO"]
# LED2_2V5_R_o (bank 13)
set_property PACKAGE_PIN "T16" [get_ports "Led22V5RxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led22V5RxSO"]
# LED2_2V5_G_o (bank 13)
set_property PACKAGE_PIN "U16" [get_ports "Led22V5GxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led22V5GxSO"]
# LED2_2V5_B_o (bank 13)
set_property PACKAGE_PIN "AA20" [get_ports "Led22V5BxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led22V5BxSO"]
##### Self reset (bank 34) #####
set_property PACKAGE_PIN "H8" [get_ports "SelfRstxRNO"]
set_property iostandard "LVCMOS25" [get_ports "SelfRstxRNO"]
##### Clock dedicated pins (Multi-region) #####
# Bank 35
set_property PACKAGE_PIN "D5" [get_ports "PLLClk2V5LocalPxCI"]
set_property PACKAGE_PIN "C4" [get_ports "PLLClk2V5LocalNxCI"]
set_property PACKAGE_PIN "B4" [get_ports "PLLClk2V5NorthPxCI"]
set_property PACKAGE_PIN "B3" [get_ports "PLLClk2V5NorthNxCI"]
# Bank 34
set_property PACKAGE_PIN "T2" [get_ports "PLLClk2V5TopxCI"]
set_property PACKAGE_PIN "L5" [get_ports "PLLClk2V5BottomxCI"]
# Bank 13
set_property PACKAGE_PIN "Y14" [get_ports "PLLClk2V5SouthPxCI"]
set_property PACKAGE_PIN "Y15" [get_ports "PLLClk2V5SouthNxCI"]
set_property PACKAGE_PIN "Y18" [get_ports "Clk2V5RecoveryPxCO"]
set_property PACKAGE_PIN "Y19" [get_ports "Clk2V5RecoveryNxCO"]
##### Clock dedicated pins (Single-region) #####
# Bank 35
set_property PACKAGE_PIN "C6" [get_ports "Clk2V5NorthPxCI"]
set_property PACKAGE_PIN "C5" [get_ports "Clk2V5NorthNxCI"]
set_property PACKAGE_PIN "D3" [get_ports "Clk2V5WestPxCI"]
set_property PACKAGE_PIN "C3" [get_ports "Clk2V5WestNxCI"]
# Bank 34
set_property PACKAGE_PIN "K4" [get_ports "Clk2V5TopPxCI"]
set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
set_property PACKAGE_PIN "U2" [get_ports "Clk2V5BottomPxCI"]
set_property PACKAGE_PIN "U1" [get_ports "Clk2V5BottomNxCI"]
# Bank 13
set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
set_property PACKAGE_PIN "AA16" [get_ports "Clk2V5EastPxCI"]
set_property PACKAGE_PIN "AA17" [get_ports "Clk2V5EastNxCI"]
##### Clock outputs #####
## Bank 35
set_property PACKAGE_PIN "F7" [get_ports "Clk2V5NorthPxCO"]
set_property PACKAGE_PIN "E7" [get_ports "Clk2V5NorthNxCO"]
set_property PACKAGE_PIN "F5" [get_ports "Clk2V5WestPxCO"]
set_property PACKAGE_PIN "E5" [get_ports "Clk2V5WestNxCO"]
# Bank 34
set_property PACKAGE_PIN "P7" [get_ports "Clk2V5TopPxCO"]
set_property PACKAGE_PIN "R7" [get_ports "Clk2V5TopNxCO"]
set_property PACKAGE_PIN "M4" [get_ports "Clk2V5BottomPxCO"]
set_property PACKAGE_PIN "M3" [get_ports "Clk2V5BottomNxCO"]
# Bank 13
set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
set_property PACKAGE_PIN "AB21" [get_ports "Clk2V5EastPxCO"]
set_property PACKAGE_PIN "AB22" [get_ports "Clk2V5EastNxCO"]
############################################################################
# Other constraints #
############################################################################
##### Operating conditions (for XPE report) #####
# Extended grade (as for -2 speed grade) and maximum consumption estimation
set_operating_conditions -grade extended -process maximum
# 4'' by 4'' PCB, no heatsink, no air flow
set_operating_conditions -airflow 0 -heatsink none -board small
designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc 0 → 100644
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############################################################################
# Timing constraints #
############################################################################
##### PS_CLK (125 MHz) #####
create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
##### GTP reference clocks (125 MHz) #####
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0xC]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk1xC]
##### Clocks from PLLs (125 MHz) #####
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Local}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_North}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_South}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Top}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Bottom}]
##### Clocks from neighbours (125 MHz) #####
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_North}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_South}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_East}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_West}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Top}]
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Bottom}]
designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd 0 → 100644
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----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: scalp_firmware - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: scalp_firmware
--
-- Last update: 2020-09-03
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Aurora packages
use work.aurora_status_pkg.all;
use work.aurora_drp_pkg.all;
-- Axi4 packages
use work.axi4_pkg.all;
entity scalp_firmware is
generic (
C_USE_IBERT : boolean := false;
C_DEBUG_MODE : boolean := false);
port (
-----------------------------------------------------------------------
-- Names defined and not described in the constraint file.
-----------------------------------------------------------------------
-- Zynq FIXED_IO
PSClkxCIO : inout std_logic;
PSSRstxRNIO : inout std_logic;
PSPorxSNIO : inout std_logic;
-- DDR interface
DDRClkNxCIO : inout std_logic;
DDRClkPxCIO : inout std_logic;
DDRDRstxRNIO : inout std_logic;
DDRCasNxSIO : inout std_logic;
DDRCkexSIO : inout std_logic;
DDRCsNxSIO : inout std_logic;
DDROdtxSIO : inout std_logic;
DDRRasNxSIO : inout std_logic;
DDRWexSNIO : inout std_logic;
DDRBankAddrxDIO : inout std_logic_vector(2 downto 0);
DDRAddrxDIO : inout std_logic_vector(14 downto 0);
DDRVrNxSIO : inout std_logic;
DDRVrPxSIO : inout std_logic;
DDRDmxDIO : inout std_logic_vector(3 downto 0);
DDRDqxDIO : inout std_logic_vector(31 downto 0);
DDRDqsNxDIO : inout std_logic_vector(3 downto 0);
DDRDqsPxDIO : inout std_logic_vector(3 downto 0);
-- MIO Interface
MIOxDIO : inout std_logic_vector(53 downto 0);
-----------------------------------------------------------------------
-- USB signals
UsbVbusPwrFaultxSI : in std_logic;
-- PLL interface
Pll2V5ClkuWirexCO : out std_logic; -- Clock (from SPI1_SCLK)
Pll2V5DatauWirexSO : out std_logic; -- Data (from SPI1_MOSI)
Pll2V5LEuWirexSO : out std_logic; -- Latch enable (from SPI1_SS)
Pll2V5GOExSO : out std_logic; -- Global Output Enable
Pll2V5LDxSI : in std_logic; -- Lock Detect
Pll2V5SyncxSO : out std_logic; -- Sync
Pll2V5ClkIn0LOSxSI : in std_logic; -- FPGA clock Loss of Sync
Pll2V5ClkIn1LOSxSI : in std_logic; -- External oscillator Loss of Sync
-- GTP interfaces
-- Clocks
GTPRefClk0PxCI : in std_logic;
GTPRefClk0NxCI : in std_logic;
GTPRefClk1PxCI : in std_logic;
GTPRefClk1NxCI : in std_logic;
-- North
GTPFromNorthPxSI : in std_logic;
GTPFromNorthNxSI : in std_logic;
GTPToNorthPxSO : out std_logic;
GTPToNorthNxSO : out std_logic;
-- South
GTPFromSouthPxSI : in std_logic;
GTPFromSouthNxSI : in std_logic;
GTPToSouthPxSO : out std_logic;
GTPToSouthNxSO : out std_logic;
-- East
GTPFromEastPxSI : in std_logic;
GTPFromEastNxSI : in std_logic;
GTPToEastPxSO : out std_logic;
GTPToEastNxSO : out std_logic;
-- West
GTPFromWestPxSI : in std_logic;
GTPFromWestNxSI : in std_logic;
GTPToWestPxSO : out std_logic;
GTPToWestNxSO : out std_logic;
-- LVDS links towards edge connectors
-- North
LVDS2V5North0PxSIO : inout std_logic;
LVDS2V5North0NxSIO : inout std_logic;
LVDS2V5North1PxSIO : inout std_logic;
LVDS2V5North1NxSIO : inout std_logic;
LVDS2V5North2PxSIO : inout std_logic;
LVDS2V5North2NxSIO : inout std_logic;
LVDS2V5North3PxSIO : inout std_logic;
LVDS2V5North3NxSIO : inout std_logic;
LVDS2V5North4PxSIO : inout std_logic;
LVDS2V5North4NxSIO : inout std_logic;
LVDS2V5North5PxSIO : inout std_logic;
LVDS2V5North5NxSIO : inout std_logic;
LVDS2V5North6PxSIO : inout std_logic;
LVDS2V5North6NxSIO : inout std_logic;
LVDS2V5North7PxSIO : inout std_logic;
LVDS2V5North7NxSIO : inout std_logic;
-- South
LVDS2V5South0PxSIO : inout std_logic;
LVDS2V5South0NxSIO : inout std_logic;
LVDS2V5South1PxSIO : inout std_logic;
LVDS2V5South1NxSIO : inout std_logic;
LVDS2V5South2PxSIO : inout std_logic;
LVDS2V5South2NxSIO : inout std_logic;
LVDS2V5South3PxSIO : inout std_logic;
LVDS2V5South3NxSIO : inout std_logic;
LVDS2V5South4PxSIO : inout std_logic;
LVDS2V5South4NxSIO : inout std_logic;
LVDS2V5South5PxSIO : inout std_logic;
LVDS2V5South5NxSIO : inout std_logic;
LVDS2V5South6PxSIO : inout std_logic;
LVDS2V5South6NxSIO : inout std_logic;
LVDS2V5South7PxSIO : inout std_logic;
LVDS2V5South7NxSIO : inout std_logic;
-- East
LVDS2V5East0PxSIO : inout std_logic;
LVDS2V5East0NxSIO : inout std_logic;
LVDS2V5East1PxSIO : inout std_logic;
LVDS2V5East1NxSIO : inout std_logic;
LVDS2V5East2PxSIO : inout std_logic;
LVDS2V5East2NxSIO : inout std_logic;
LVDS2V5East3PxSIO : inout std_logic;
LVDS2V5East3NxSIO : inout std_logic;
LVDS2V5East4PxSIO : inout std_logic;
LVDS2V5East4NxSIO : inout std_logic;
LVDS2V5East5PxSIO : inout std_logic;
LVDS2V5East5NxSIO : inout std_logic;
LVDS2V5East6PxSIO : inout std_logic;
LVDS2V5East6NxSIO : inout std_logic;
LVDS2V5East7PxSIO : inout std_logic;
LVDS2V5East7NxSIO : inout std_logic;
-- West
LVDS2V5West0PxSIO : inout std_logic;
LVDS2V5West0NxSIO : inout std_logic;
LVDS2V5West1PxSIO : inout std_logic;
LVDS2V5West1NxSIO : inout std_logic;
LVDS2V5West2PxSIO : inout std_logic;
LVDS2V5West2NxSIO : inout std_logic;
LVDS2V5West3PxSIO : inout std_logic;
LVDS2V5West3NxSIO : inout std_logic;
LVDS2V5West4PxSIO : inout std_logic;
LVDS2V5West4NxSIO : inout std_logic;
LVDS2V5West5PxSIO : inout std_logic;
LVDS2V5West5NxSIO : inout std_logic;
LVDS2V5West6PxSIO : inout std_logic;
LVDS2V5West6NxSIO : inout std_logic;
LVDS2V5West7PxSIO : inout std_logic;
LVDS2V5West7NxSIO : inout std_logic;
-- LVDS links towards top-bottom connectors
-- Top
LVDS2V5Top0PxSIO : inout std_logic;
LVDS2V5Top0NxSIO : inout std_logic;
LVDS2V5Top1PxSIO : inout std_logic;
LVDS2V5Top1NxSIO : inout std_logic;
LVDS2V5Top2PxSIO : inout std_logic;
LVDS2V5Top2NxSIO : inout std_logic;
LVDS2V5Top3PxSIO : inout std_logic;
LVDS2V5Top3NxSIO : inout std_logic;
LVDS2V5Top4PxSIO : inout std_logic;
LVDS2V5Top4NxSIO : inout std_logic;
LVDS2V5Top5PxSIO : inout std_logic;
LVDS2V5Top5NxSIO : inout std_logic;
LVDS2V5Top6PxSIO : inout std_logic;
LVDS2V5Top6NxSIO : inout std_logic;
LVDS2V5Top7PxSIO : inout std_logic;
LVDS2V5Top7NxSIO : inout std_logic;
-- Bottom
LVDS2V5Bottom0PxSIO : inout std_logic;
LVDS2V5Bottom0NxSIO : inout std_logic;
LVDS2V5Bottom1PxSIO : inout std_logic;
LVDS2V5Bottom1NxSIO : inout std_logic;
LVDS2V5Bottom2PxSIO : inout std_logic;
LVDS2V5Bottom2NxSIO : inout std_logic;
LVDS2V5Bottom3PxSIO : inout std_logic;
LVDS2V5Bottom3NxSIO : inout std_logic;
LVDS2V5Bottom4PxSIO : inout std_logic;
LVDS2V5Bottom4NxSIO : inout std_logic;
LVDS2V5Bottom5PxSIO : inout std_logic;
LVDS2V5Bottom5NxSIO : inout std_logic;
LVDS2V5Bottom6PxSIO : inout std_logic;
LVDS2V5Bottom6NxSIO : inout std_logic;
LVDS2V5Bottom7PxSIO : inout std_logic;
LVDS2V5Bottom7NxSIO : inout std_logic;
-- RGB LEDs
Led12V5RxSO : out std_logic;
Led12V5GxSO : out std_logic;
Led12V5BxSO : out std_logic;
Led22V5RxSO : out std_logic;
Led22V5GxSO : out std_logic;
Led22V5BxSO : out std_logic;
-- Self reset (connected to PS_SRSTB)
SelfRstxRNO : out std_logic;
-- Clocks from PLLs (connected to MRCC pins)
-- Local
PLLClk2V5LocalPxCI : in std_logic;
PLLClk2V5LocalNxCI : in std_logic;
-- North
PLLClk2V5NorthPxCI : in std_logic;
PLLClk2V5NorthNxCI : in std_logic;
-- South
PLLClk2V5SouthPxCI : in std_logic;
PLLClk2V5SouthNxCI : in std_logic;
-- Top
PLLClk2V5TopxCI : in std_logic; -- Single-ended
-- Bottom
PLLClk2V5BottomxCI : in std_logic; -- Single-ended
-- Clocks to/from neighbours
-- North
Clk2V5NorthPxCI : in std_logic;
Clk2V5NorthNxCI : in std_logic;
Clk2V5NorthPxCO : out std_logic;
Clk2V5NorthNxCO : out std_logic;
-- South
Clk2V5SouthPxCI : in std_logic;
Clk2V5SouthNxCI : in std_logic;
Clk2V5SouthPxCO : out std_logic;
Clk2V5SouthNxCO : out std_logic;
-- East
Clk2V5EastPxCI : in std_logic;
Clk2V5EastNxCI : in std_logic;
Clk2V5EastPxCO : out std_logic;
Clk2V5EastNxCO : out std_logic;
-- West
Clk2V5WestPxCI : in std_logic;
Clk2V5WestNxCI : in std_logic;
Clk2V5WestPxCO : out std_logic;
Clk2V5WestNxCO : out std_logic;
-- Top
Clk2V5TopPxCI : in std_logic;
Clk2V5TopNxCI : in std_logic;
Clk2V5TopPxCO : out std_logic;
Clk2V5TopNxCO : out std_logic;
-- Bottom
Clk2V5BottomPxCI : in std_logic;
Clk2V5BottomNxCI : in std_logic;
Clk2V5BottomPxCO : out std_logic;
Clk2V5BottomNxCO : out std_logic;
-- Recovery
Clk2V5RecoveryPxCO : out std_logic;
Clk2V5RecoveryNxCO : out std_logic);
end scalp_firmware;
architecture arch of scalp_firmware is
-- Constantes
constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
-- Signals
-- Clocks
-- Processing system clock
signal PSSysClkxC : std_logic := '0';
-- GTP Clocks
signal GTPRefClk0xC : std_logic := '0';
signal GTPRefClk1xC : std_logic := '0';
-- Resets
-- Processing system reset
signal PSSysResetxR : std_logic_vector((C_PS_SYS_RESET_SIZE - 1) downto 0) := (others => '0');
-- Attributes
attribute mark_debug : string;
attribute keep : string;
begin
ProcessingSystemxB : block is
begin -- block ProcessingSystemxB
ZynqxI : entity work.scalp_firmware_ps
port map (
-- Processor interface
FIXED_IO_ps_clk => PSClkxCIO,
FIXED_IO_ps_porb => PSPorxSNIO,
FIXED_IO_ps_srstb => PSSRstxRNIO,
FclkClk0xCO => PSSysClkxC,
FclkReset0xRO => PSSysResetxR,
-- DDR interface
DDR_addr => DDRAddrxDIO,
DDR_ba => DDRBankAddrxDIO,
DDR_cas_n => DDRCasNxSIO,
DDR_ck_n => DDRClkNxCIO,
DDR_ck_p => DDRClkPxCIO,
DDR_cke => DDRCkexSIO,
DDR_cs_n => DDRCsNxSIO,
DDR_dm => DDRDmxDIO,
DDR_dq => DDRDqxDIO,
DDR_dqs_n => DDRDqsNxDIO,
DDR_dqs_p => DDRDqsPxDIO,
DDR_odt => DDROdtxSIO,
DDR_ras_n => DDRRasNxSIO,
DDR_reset_n => DDRDRstxRNIO,
DDR_we_n => DDRWexSNIO,
FIXED_IO_ddr_vrn => DDRVrNxSIO,
FIXED_IO_ddr_vrp => DDRVrPxSIO,
-- USB interface
Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
-- SPI1 used as uWire master. Clk, Data and LE signals are outputs
-- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
Spi1MOSIxSO => Pll2V5DatauWirexSO,
Spi1SSxSO => Pll2V5LEuWirexSO,
Spi1SclkxCO => Pll2V5ClkuWirexCO,
-- MIO
FIXED_IO_mio => MIOxDIO);
end block ProcessingSystemxB;
ProgrammableLogicxB : block is
begin -- block ProgrammableLogicxB
InputClocksxB : block is
begin -- block InputClocksxB
-- GTP Clocks buffers
IBufDSGTPRefClk0xI : IBUFDS_GTE2
port map (
I => GTPRefClk0PxCI,
IB => GTPRefClk0NxCI,
CEB => '0',
O => GTPRefClk0xC,
ODIV2 => open);
IBufDSGTPRefClk1xI : IBUFDS_GTE2
port map (
I => GTPRefClk1PxCI,
IB => GTPRefClk1NxCI,
CEB => '0',
O => GTPRefClk1xC,
ODIV2 => open);
end block InputClocksxB;
end block ProgrammableLogicxB;
end arch;
designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl 0 → 100644
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− 0
View file @ 53fc6fb8
designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd 0 → 100644
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View file @ 53fc6fb8
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: tb_scalp_firmware - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: Testbench for scalp_firmware
--
-- Last update: 2020-09-03 11:28:21
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_scalp_firmware is
end tb_scalp_firmware;
architecture behavioral of tb_scalp_firmware is
begin
end behavioral;
vivado_prj_creator @ 1f1e1cb3
Subproject commit 1f1e1cb37b458cfec770896d1f3237d1edbae830
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