diff --git a/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd b/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3fd74db2d6f90792a6f25a0e92c4060c76e8d38a
--- /dev/null
+++ b/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
@@ -0,0 +1,69 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: aurora_drp_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: DRP interface control signals for the Aurora phy.
+--
+-- Last update: 2020-09-03
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package aurora_drp_pkg is
+
+ constant C_DRP_ADDR_SIZE : integer := 11;
+ constant C_DRP_DATA_SIZE : integer := 16;
+ constant C_DRP_SEL_SIZE : integer := 2;
+ constant C_DRP_SEL_NORTH : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "00";
+ constant C_DRP_SEL_EAST : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "01";
+ constant C_DRP_SEL_SOUTH : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "10";
+ constant C_DRP_SEL_WEST : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "11";
+
+ -- DRP Ports
+ -- Master To Slave
+ type t_drpm2s is record
+ DrpClkxC : std_logic;
+ DrpAddrxD : std_ulogic_vector((C_DRP_ADDR_SIZE - 1) downto 0);
+ DrpDIxD : std_ulogic_vector((C_DRP_DATA_SIZE - 1) downto 0);
+ DrpEnxS : std_ulogic;
+ DrpWExS : std_ulogic;
+ end record t_drpm2s;
+
+ -- Slave To Master
+ type t_drps2m is record
+ DrpDOxD : std_ulogic_vector((C_DRP_DATA_SIZE - 1) downto 0);
+ DrpRdyxS : std_ulogic;
+ end record t_drps2m;
+
+ type t_drp is record
+ M2S : t_drpm2s;
+ S2M : t_drps2m;
+ end record t_drp;
+
+ constant C_NO_DRP_M2S : t_drpm2s := (DrpClkxC => '0',
+ DrpAddrxD => (others => '0'),
+ DrpDIxD => (others => '0'),
+ DrpEnxS => '0',
+ DrpWExS => '0');
+
+ constant C_NO_DRP_S2M : t_drps2m := (DrpDOxD => (others => '0'),
+ DrpRdyxS => '0');
+
+ constant C_NO_DRP : t_drp := (M2S => C_NO_DRP_M2S,
+ S2M => C_NO_DRP_S2M);
+
+end package aurora_drp_pkg;
diff --git a/packages/hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd b/packages/hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d292767b1e074b8675c200dcd5df592e5041a8bb
--- /dev/null
+++ b/packages/hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: tb_aurora_drp_pkg - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: Testbench for package aurora_drp_pkg
+--
+-- Last update: 2020-09-21 10:54:03
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_aurora_drp_pkg is
+end tb_aurora_drp_pkg;
+
+
+architecture behavioral of tb_aurora_drp_pkg is
+
+begin
+
+end behavioral;
diff --git a/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..479d5a295206ce552acfc3683401f5e0f297ceeb
--- /dev/null
+++ b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
@@ -0,0 +1,176 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: aurora_status_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: Control and status signals for the Aurora phy.
+--
+-- Last update: 2020-09-03
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+package aurora_status_pkg is
+
+ -- Constants
+
+ constant C_GTP_VECTOR_SIZE : integer := 1;
+ constant C_LANEUP_SIZE : integer := 1;
+ constant C_LOOPBACK_SIZE : integer := 3;
+ constant C_NB_GTP_CORE : integer := 4;
+ constant C_NUM_PLL : integer := 1;
+ constant C_GTP_NORTH_ID : integer := 0;
+ constant C_GTP_EAST_ID : integer := 1;
+ constant C_GTP_SOUTH_ID : integer := 2;
+ constant C_GTP_WEST_ID : integer := 3;
+
+ -- Types
+
+ type t_aurora_gtp_diff_io_rx is record
+ RXPxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+ RXNxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+ end record t_aurora_gtp_diff_io_rx;
+
+ type t_aurora_gtp_diff_io_tx is record
+ TXPxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+ TXNxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+ end record t_aurora_gtp_diff_io_tx;
+
+ constant C_AURORA_NO_GTP_DIFF_IO_RX : t_aurora_gtp_diff_io_rx := (RXPxD => (others => '0'),
+ RXNxD => (others => '0'));
+
+ constant C_AURORA_NO_GTP_DIFF_IO_TX : t_aurora_gtp_diff_io_tx := (TXPxD => (others => '0'),
+ TXNxD => (others => '0'));
+
+ type t_gtp_diff_ref_clk is record
+ ClkPxC : std_ulogic;
+ ClkNxC : std_ulogic;
+ end record t_gtp_diff_ref_clk;
+
+ constant C_NO_GTP_DIFF_REF_CLK : t_gtp_diff_ref_clk := (ClkPxC => '0',
+ ClkNxC => '0');
+
+ type t_aurora_control is record
+ LoopbackxD : std_ulogic_vector((C_LOOPBACK_SIZE - 1) downto 0);
+ PowerDownxS : std_ulogic;
+ GTPRefClkSrcxS : std_ulogic;
+ InitClkLockedxS : std_ulogic;
+ end record t_aurora_control;
+
+ constant C_MGTREFCLK0_SRC : std_ulogic := '0';
+ constant C_MGTREFCLK1_SRC : std_ulogic := '1';
+
+ constant C_AURORA_NO_CONTROL : t_aurora_control := (LoopbackxD => (others => '0'),
+ PowerDownxS => '1',
+ GTPRefClkSrcxS => C_MGTREFCLK0_SRC,
+ InitClkLockedxS => '0');
+
+ type t_laneup_vector is array (0 to (C_NB_GTP_CORE - 1)) of std_ulogic_vector((C_LANEUP_SIZE - 1) downto 0);
+
+ type t_aurora_status is record
+ HardErrxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ SoftErrxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ FrameErrxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ LaneUpxD : t_laneup_vector;
+ ChannelUpxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ RXResetDoneOutxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ TXResetDoneOutxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ TXLockxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ PllNotLockedxS : std_ulogic;
+ end record t_aurora_status;
+
+ constant C_AURORA_NO_STATUS : t_aurora_status := (HardErrxD => (others => '0'),
+ SoftErrxD => (others => '0'),
+ FrameErrxD => (others => '0'),
+ LaneUpxD => (others => (others => '0')),
+ ChannelUpxD => (others => '0'),
+ RXResetDoneOutxD => (others => '0'),
+ TXResetDoneOutxD => (others => '0'),
+ TXLockxD => (others => '0'),
+ PllNotLockedxS => '1');
+
+ constant C_AURORA_STATUS_OK : t_aurora_status := (HardErrxD => (others => '0'),
+ SoftErrxD => (others => '0'),
+ FrameErrxD => (others => '0'),
+ LaneUpxD => (others => (others => '1')),
+ ChannelUpxD => (others => '1'),
+ RXResetDoneOutxD => (others => '1'),
+ TXResetDoneOutxD => (others => '1'),
+ TXLockxD => (others => '1'),
+ PllNotLockedxS => '1');
+
+ type t_aurora_crc is record
+ CRCPassFailxSN : std_ulogic;
+ CRCValidxS : std_ulogic;
+ end record t_aurora_crc;
+
+ constant C_AURORA_NO_CRC : t_aurora_crc := (CRCPassFailxSN => '0',
+ CRCValidxS => '0');
+
+ constant C_AURORA_CRC_OK : t_aurora_crc := (CRCPassFailxSN => '1',
+ CRCValidxS => '1');
+
+ constant C_AURORA_CRC_NO_OK : t_aurora_crc := (CRCPassFailxSN => '0',
+ CRCValidxS => '1');
+
+ type t_aurora_slave_clk is record
+ InitClkxC : std_ulogic;
+ DrpClkxC : std_ulogic;
+ GTClkxC : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+ GTClkLockedxD : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+ end record t_aurora_slave_clk;
+
+ constant C_AURORA_NO_SLAVE_CLK : t_aurora_slave_clk := (InitClkxC => '0',
+ DrpClkxC => '0',
+ GTClkxC => (others => '0'),
+ GTClkLockedxD => (others => '0'));
+
+ type t_aurora_master_clk is record
+ InitClkxC : std_ulogic;
+ UserClkxC : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+ SyncClkxC : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+ PllNotLockedxD : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+ end record t_aurora_master_clk;
+
+ constant C_AURORA_NO_MASTER_CLK : t_aurora_master_clk := (InitClkxC => '0',
+ UserClkxC => (others => '0'),
+ SyncClkxC => (others => '0'),
+ PllNotLockedxD => (others => '0'));
+
+ -- Functions
+
+ function std_bool (exp_in : in boolean) return std_ulogic;
+
+end package aurora_status_pkg;
+
+-- Functions definitions
+
+package body aurora_status_pkg is
+
+ function std_bool (exp_in : in boolean)
+ return std_ulogic is
+ begin -- function std_bool
+
+ if exp_in = true then
+ return '1';
+ else
+ return '0';
+ end if;
+
+ end function std_bool;
+
+end package body aurora_status_pkg;
diff --git a/packages/hw/aurora_status_pkg/src/sim/tb_aurora_status_pkg.vhd b/packages/hw/aurora_status_pkg/src/sim/tb_aurora_status_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bc5629363fb1099677bf11b4567ad1f324546c90
--- /dev/null
+++ b/packages/hw/aurora_status_pkg/src/sim/tb_aurora_status_pkg.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: tb_aurora_status_pkg - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: Testbench for package aurora_status_pkg
+--
+-- Last update: 2020-09-21 10:57:55
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_aurora_status_pkg is
+end tb_aurora_status_pkg;
+
+
+architecture behavioral of tb_aurora_status_pkg is
+
+begin
+
+end behavioral;
diff --git a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c241510cfa03792e570ec44f685feb95d91da7b3
--- /dev/null
+++ b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
@@ -0,0 +1,146 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: axi4_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: AXI4 format bus signals.
+--
+-- Last update: 2020-09-03
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package axi4_pkg is
+
+ constant C_AXI4_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_KEEP_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_UFC_DATA_SIZE : integer range 0 to 32 := 3;
+ constant C_AXI4_NFC_DATA_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_DEST_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_STRB_SIZE : integer range 0 to 32 := C_AXI4_KEEP_SIZE; -- Same as Keep
+ constant C_AXI4_USER_SIZE : integer range 0 to 32 := 32;
+
+ -- AXI4 Framing
+ -- Master to Slave
+ type t_axi4m2s is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_DATA_SIZE - 1));
+ KeepxD : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+ LastxS : std_ulogic;
+ ValidxS : std_ulogic;
+ -- Not Necessary
+ IdxS : std_ulogic;
+ DestxD : std_ulogic_vector(0 to (C_AXI4_DEST_SIZE - 1));
+ StrbxD : std_ulogic_vector(0 to (C_AXI4_STRB_SIZE - 1));
+ UserxD : std_ulogic_vector(0 to (C_AXI4_USER_SIZE - 1));
+ end record t_axi4m2s;
+
+ -- Slave to Master
+ type t_axi4s2m is record
+ ReadyxS : std_ulogic;
+ end record t_axi4s2m;
+
+ constant C_NO_AXI4_M2S : t_axi4m2s := (DataxD => (others => '0'),
+ KeepxD => (others => '0'),
+ LastxS => '0',
+ ValidxS => '0',
+ IdxS => '0',
+ DestxD => (others => '0'),
+ StrbxD => (others => '0'),
+ UserxD => (others => '0'));
+ constant C_NO_AXI4_S2M : t_axi4s2m := (ReadyxS => '0');
+
+ -- Non-Generic Vector of AXI4 Framing Bus
+ ---------------------------------------------------------------------------
+ -- constant C_SIM_VIVADO_VECTOR_SIZE : integer := 6;
+ -- type t_axi4m2s_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4m2s;
+ -- type t_axi4s2m_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4s2m;
+
+ -- constant C_NO_SIM_AXISM2S_VECTOR : t_axi4m2s_vector := (others => C_NO_AXI4_M2S);
+ -- constant C_NO_SIM_AXISS2M_VECTOR : t_axi4s2m_vector := (others => C_NO_AXI4_S2M);
+ -- -- Generic Vector of AXI4 Framing Bus Vector
+ -- type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+ -- type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+ ---------------------------------------------------------------------------
+ -- Generic Vector of AXI4 Framing Bus
+ type t_axi4m2s_vector is array (natural range <>) of t_axi4m2s;
+ type t_axi4s2m_vector is array (natural range <>) of t_axi4s2m;
+
+ -- Generic Vector of AXI4 Framing Bus Vector
+ type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+ type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+
+ -- AXI4 UFC
+ -- Master to Slave
+ type t_axi4ufcm2s is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_DATA_SIZE - 1));
+ KeepxD : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+ ValidxS : std_ulogic;
+ end record t_axi4ufcm2s;
+
+ -- Slave to Master
+ type t_axi4ufcs2m is record
+ ReadyxS : std_ulogic;
+ end record t_axi4ufcs2m;
+
+ constant C_NO_AXI4_UFC_M2S : t_axi4ufcm2s := (DataxD => (others => '0'),
+ KeepxD => (others => '0'),
+ ValidxS => '0');
+ constant C_NO_AXI4_UFC_S2M : t_axi4ufcs2m := (ReadyxS => '0');
+
+ -- AXI4 NFC
+ -- Master to Slave
+ type t_axi4nfcm2s is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_NFC_DATA_SIZE - 1));
+ ValidxS : std_ulogic;
+ end record t_axi4nfcm2s;
+
+ -- Slave to Master
+ type t_axi4nfcs2m is record
+ ReadyxS : std_ulogic;
+ end record t_axi4nfcs2m;
+
+ constant C_NO_AXI4_NFC_M2S : t_axi4nfcm2s := (DataxD => (others => '0'),
+ ValidxS => '0');
+ constant C_NO_AXI4_NFC_S2M : t_axi4nfcs2m := (ReadyxS => '0');
+
+ -- AXI4 Functions
+ -- OR reduce from t_axi4s2m_vector
+ function or_reduce_t_axi4s2m_vector (
+ signal VectorxD : t_axi4s2m_vector)
+ return t_axi4s2m;
+
+end package axi4_pkg;
+
+package body axi4_pkg is
+
+ -- AXI4 Functions
+ -- OR reduce from t_axi4s2m_vector
+ function or_reduce_t_axi4s2m_vector (
+ signal VectorxD : t_axi4s2m_vector)
+ return t_axi4s2m is
+ variable ResultxS : t_axi4s2m := C_NO_AXI4_S2M;
+ begin -- function or_reduce_t_axi4s2m_vector
+ for i in VectorxD'range loop
+ ResultxS.ReadyxS := ResultxS.ReadyxS or VectorxD(i).ReadyxS;
+ end loop; -- i
+
+ return ResultxS;
+ end function or_reduce_t_axi4s2m_vector;
+
+end package body axi4_pkg;
diff --git a/packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd b/packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..10ef16668b02b5e75f77c1aa96b0b37a6c38303f
--- /dev/null
+++ b/packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: tb_axi4_pkg - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: Testbench for package axi4_pkg
+--
+-- Last update: 2020-09-21 10:58:57
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_axi4_pkg is
+end tb_axi4_pkg;
+
+
+architecture behavioral of tb_axi4_pkg is
+
+begin
+
+end behavioral;
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..08a5516659fe09a24d8bd9034e6d652abab7f575
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,37 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_drp_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Console color print utility
+#
+# Last update: 2020-09-21 10:54:03
+#
+##################################################################################
+
+# Text attributes
+set RESET [exec tput sgr0]
+set BOLD [exec tput bold]
+set ITALIC [exec tput sitm]
+set BLINK [exec tput blink]
+set HIGHL [exec tput smso]
+
+# Text colors
+set RED [exec tput setaf 1]
+set GREEN [exec tput setaf 2]
+set YELLOW [exec tput setaf 3]
+set BLUE [exec tput setaf 4]
+set MAGENTA [exec tput setaf 5]
+set CYAN [exec tput setaf 6]
+set WHITE [exec tput setaf 7]
+
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..55c73e8d4ac77e0ca181bd43ea79a031af4bc014
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_drp_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Cleanup project directory
+#
+# Last update: 2020-09-21 10:54:03
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/aurora_drp_pkg/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..eb2b8a8b32b19656098988f181f35b19e29061e0
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_drp_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-21 10:54:03
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_aurora_drp_pkg.tcl -notrace
+echo "> Done"
+
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e850aed406b79b055945ab127c1ed12d67bbb803
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl
@@ -0,0 +1,137 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_drp_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script for re-creating Vivado project 'aurora_drp_pkg'
+#
+# Last update: 2020-09-21 10:54:03
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "aurora_drp_pkg"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../packages/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+#set_property board_part SCALP [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add HDL sources
+ set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ # add IPs source file
+ #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ # add the project component
+ set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add IPs source file
+ #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e253c86f114284e752119124c4686f19e34c9d2e
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_drp_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-21 10:54:03
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../aurora_drp_pkg/aurora_drp_pkg.xpr
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/utils.tcl b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9d5808634218e7e41199e22439759b3067c8abb9
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_drp_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2020-09-21 10:54:03
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.cache/wt/webtalk_pa.xml b/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..a04ac1bf6e2c01a5ccb75f3005be0ffa80b3a2a4
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.cache/wt/webtalk_pa.xml
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Mon Sep 21 10:59:22 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="7b4885f2b9e8426fb39a5571b8d7fbac" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="FileExit" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_OK" value="1" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="10" type="GuiHandlerData"/>
+<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_EXPORT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_EXIT" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="159" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="149" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr b/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr
new file mode 100644
index 0000000000000000000000000000000000000000..54e6c0c152b4f71fa4ca40f6550287a4f285a4fe
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr
@@ -0,0 +1,192 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2019.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="44" Path="/home/jo/Documents/Projets/Hepia/scalp_firmware/packages/vivado/aurora_drp_pkg/2019.2/lin64/aurora_drp_pkg/aurora_drp_pkg.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="05f42d69fe654438b814471c264b24b2"/>
+ <Option Name="Part" Val="xc7z015clg485-2"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../../../../../hw"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../../../../../hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="aurora_drp_pkg"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+ <File Path="$PPRDIR/../../../../../hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="tb_aurora_drp_pkg"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="IES">
+ <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="11">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design" EnableStepBool="1"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/setup.sh b/packages/vivado/aurora_drp_pkg/2019.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..376e6a013cc20f13e13cabeb41e75aa20b54a8ce
--- /dev/null
+++ b/packages/vivado/aurora_drp_pkg/2019.2/lin64/setup.sh
@@ -0,0 +1,30 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_drp_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2020-09-21 10:54:03
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_aurora_drp_pkg.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_aurora_drp_pkg.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_aurora_drp_pkg.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_aurora_drp_pkg.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_aurora_drp_pkg.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_aurora_drp_pkg.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_aurora_drp_pkg.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_aurora_drp_pkg.sh && cd ..'
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl b/packages/vivado/aurora_drp_pkg/2019.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..88f94eba1e05c38a13a9b7c5cbba8e98f7be0ef4
--- /dev/null
+++ b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,37 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_status_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Console color print utility
+#
+# Last update: 2020-09-21 10:57:55
+#
+##################################################################################
+
+# Text attributes
+set RESET [exec tput sgr0]
+set BOLD [exec tput bold]
+set ITALIC [exec tput sitm]
+set BLINK [exec tput blink]
+set HIGHL [exec tput smso]
+
+# Text colors
+set RED [exec tput setaf 1]
+set GREEN [exec tput setaf 2]
+set YELLOW [exec tput setaf 3]
+set BLUE [exec tput setaf 4]
+set MAGENTA [exec tput setaf 5]
+set CYAN [exec tput setaf 6]
+set WHITE [exec tput setaf 7]
+
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..1b2cde12534dfb83bda1a84c3b48907b2b5e682d
--- /dev/null
+++ b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_status_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Cleanup project directory
+#
+# Last update: 2020-09-21 10:57:55
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/aurora_status_pkg/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.sh b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b5daffb88036da10d7c0cf7895cc67f11cb2f239
--- /dev/null
+++ b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_status_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-21 10:57:55
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_aurora_status_pkg.tcl -notrace
+echo "> Done"
+
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e04df11efc263f57a56a715e54cc6b6bc022df31
--- /dev/null
+++ b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl
@@ -0,0 +1,137 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_status_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script for re-creating Vivado project 'aurora_status_pkg'
+#
+# Last update: 2020-09-21 10:57:55
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "aurora_status_pkg"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../packages/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part SCALP [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add HDL sources
+ set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ # add IPs source file
+ #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ # add the project component
+ set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add IPs source file
+ #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/open_prj_aurora_status_pkg.sh b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/open_prj_aurora_status_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..6b75e75f38be9349fc045cca8c876147bb52ab4e
--- /dev/null
+++ b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/open_prj_aurora_status_pkg.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_status_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-21 10:57:55
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../aurora_status_pkg/aurora_status_pkg.xpr
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/utils.tcl b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cdb1be0320a8685ba5adac67cdfbd0c8e609af22
--- /dev/null
+++ b/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_status_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2020-09-21 10:57:55
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/setup.sh b/packages/vivado/aurora_status_pkg/2019.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..35e817598765200dbcb762fb158724247833aea6
--- /dev/null
+++ b/packages/vivado/aurora_status_pkg/2019.2/lin64/setup.sh
@@ -0,0 +1,30 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: aurora_status_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2020-09-21 10:57:55
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_aurora_status_pkg.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_aurora_status_pkg.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_aurora_status_pkg.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_aurora_status_pkg.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_aurora_status_pkg.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_aurora_status_pkg.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_aurora_status_pkg.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_aurora_status_pkg.sh && cd ..'
diff --git a/packages/vivado/aurora_status_pkg/2019.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl b/packages/vivado/aurora_status_pkg/2019.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..908374b77b4874fa351d1482b6d0a9d36e0cb3af
--- /dev/null
+++ b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,37 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: axi4_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Console color print utility
+#
+# Last update: 2020-09-21 10:58:57
+#
+##################################################################################
+
+# Text attributes
+set RESET [exec tput sgr0]
+set BOLD [exec tput bold]
+set ITALIC [exec tput sitm]
+set BLINK [exec tput blink]
+set HIGHL [exec tput smso]
+
+# Text colors
+set RED [exec tput setaf 1]
+set GREEN [exec tput setaf 2]
+set YELLOW [exec tput setaf 3]
+set BLUE [exec tput setaf 4]
+set MAGENTA [exec tput setaf 5]
+set CYAN [exec tput setaf 6]
+set WHITE [exec tput setaf 7]
+
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/clean_prj_axi4_pkg.sh b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/clean_prj_axi4_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c53b314651c2a29b6823d5ea97bacbc4ac6a43b9
--- /dev/null
+++ b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/clean_prj_axi4_pkg.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: axi4_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Cleanup project directory
+#
+# Last update: 2020-09-21 10:58:57
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/axi4_pkg/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.sh b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..010a8a8675d95e5fdcae48ade492d78f94f90b97
--- /dev/null
+++ b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: axi4_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-21 10:58:57
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_axi4_pkg.tcl -notrace
+echo "> Done"
+
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.tcl b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3f3e315085d2344c34a31ce6b206f048817a8b8c
--- /dev/null
+++ b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.tcl
@@ -0,0 +1,137 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: axi4_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script for re-creating Vivado project 'axi4_pkg'
+#
+# Last update: 2020-09-21 10:58:57
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "axi4_pkg"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../packages/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part SCALP [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add HDL sources
+ set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ # add IPs source file
+ #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ # add the project component
+ set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add IPs source file
+ #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/open_prj_axi4_pkg.sh b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/open_prj_axi4_pkg.sh
new file mode 100755
index 0000000000000000000000000000000000000000..19d51ed64d8ff09959dd85c126f0a0813586f513
--- /dev/null
+++ b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/open_prj_axi4_pkg.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: axi4_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-21 10:58:57
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../axi4_pkg/axi4_pkg.xpr
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/utils.tcl b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3ab94a59d72a4dee12a6e4d0d06323a6aa8520e9
--- /dev/null
+++ b/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: axi4_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2020-09-21 10:58:57
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/setup.sh b/packages/vivado/axi4_pkg/2019.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..6ad920bddd32778fd9ebb25d8bd689ac75f86a10
--- /dev/null
+++ b/packages/vivado/axi4_pkg/2019.2/lin64/setup.sh
@@ -0,0 +1,30 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: axi4_pkg
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2020-09-21 10:58:57
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_axi4_pkg.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_axi4_pkg.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_axi4_pkg.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_axi4_pkg.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_axi4_pkg.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_axi4_pkg.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_axi4_pkg.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_axi4_pkg.sh && cd ..'
diff --git a/packages/vivado/axi4_pkg/2019.2/src/ipi_tcl/axi4_pkg_ipi.tcl b/packages/vivado/axi4_pkg/2019.2/src/ipi_tcl/axi4_pkg_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/tools/config/aurora_drp_pkg.json b/tools/config/aurora_drp_pkg.json
new file mode 100644
index 0000000000000000000000000000000000000000..ea5bc7f915e44206f432a91f15b8416e2f642794
--- /dev/null
+++ b/tools/config/aurora_drp_pkg.json
@@ -0,0 +1,18 @@
+{
+ "author": {
+ "name": "Joachim Schmidt",
+ "email": "<joachim.schmidt@hesge.ch>"
+ },
+ "project": {
+ "name": "aurora_drp_pkg",
+ "type": "COMP_PRJ_TYPE",
+ "category": "PACKAGES",
+ "vivado_version": "2019.2",
+ "target_language": "VHDL",
+ "vhdl_version": "VHDL 2008"
+ },
+ "hardware": {
+ "part_name": "xc7z015clg485-2",
+ "board_name": "SCALP"
+ }
+}
diff --git a/tools/config/aurora_status_pkg.json b/tools/config/aurora_status_pkg.json
new file mode 100644
index 0000000000000000000000000000000000000000..1686a856f8641dadaf45f3092439084e19b229b3
--- /dev/null
+++ b/tools/config/aurora_status_pkg.json
@@ -0,0 +1,18 @@
+{
+ "author": {
+ "name": "Joachim Schmidt",
+ "email": "<joachim.schmidt@hesge.ch>"
+ },
+ "project": {
+ "name": "aurora_status_pkg",
+ "type": "COMP_PRJ_TYPE",
+ "category": "PACKAGES",
+ "vivado_version": "2019.2",
+ "target_language": "VHDL",
+ "vhdl_version": "VHDL 2008"
+ },
+ "hardware": {
+ "part_name": "xc7z015clg485-2",
+ "board_name": "SCALP"
+ }
+}
diff --git a/tools/config/axi4_pkg.json b/tools/config/axi4_pkg.json
new file mode 100644
index 0000000000000000000000000000000000000000..497e54185ecd78aac992b2e6c98d3bd63166466c
--- /dev/null
+++ b/tools/config/axi4_pkg.json
@@ -0,0 +1,18 @@
+{
+ "author": {
+ "name": "Joachim Schmidt",
+ "email": "<joachim.schmidt@hesge.ch>"
+ },
+ "project": {
+ "name": "axi4_pkg",
+ "type": "COMP_PRJ_TYPE",
+ "category": "PACKAGES",
+ "vivado_version": "2019.2",
+ "target_language": "VHDL",
+ "vhdl_version": "VHDL 2008"
+ },
+ "hardware": {
+ "part_name": "xc7z015clg485-2",
+ "board_name": "SCALP"
+ }
+}
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
index 1e8d8d5a22bcb9ee9885bc461e80f21af1fd26a7..28f7adeb19e778009fa164b2cc63769df49678d5 100644
--- a/tools/config/scalp_firmware.json
+++ b/tools/config/scalp_firmware.json
@@ -14,5 +14,15 @@
"hardware" : {
"part_name" : "xc7z015clg485-2",
"board_name" : "SCALP"
+ },
+ "components" : {
+ "packages" : {
+ "aurora_drp_pkg" : "true",
+ "aurora_status_pkg" : "true",
+ "axi4_pkg" : "true"
+ },
+ "soc" : {
+ "scalp_zynqps" : "true"
+ }
}
}