diff --git a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
index e9010e62cb1c62babee9310df8877b965680a849..a5aed655008803e650c9cda7c49855491652e7d1 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: scalp_firmware
--
--- Last update: 2020-11-10
+-- Last update: 2020-11-25
--
---------------------------------------------------------------------------------
@@ -36,8 +36,9 @@ use unisim.vcomponents.all;
entity scalp_firmware is
generic (
- C_USE_IBERT : boolean := false;
- C_DEBUG_MODE : boolean := false);
+ C_USE_IBERT : boolean := false;
+ C_DEBUG_MODE : boolean := false;
+ C_RX_FIFO_MODE : boolean := true);
port (
-----------------------------------------------------------------------
@@ -278,338 +279,258 @@ architecture arch of scalp_firmware is
component scalp_aurora_phy is
generic (
- C_DEBUG_MODE : boolean);
+ C_DEBUG_MODE : boolean;
+ C_RX_FIFO_MODE : boolean);
port (
- GTRefClkxCI : in t_gt_ref_slave_clk;
- AuroraClkxCI : in t_aurora_slave_clk;
- AuroraClkxCO : out t_aurora_master_clk;
- AuroraResetxRI : in t_aurora_slave_reset;
- AuroraResetxRO : out t_aurora_master_link_reset;
- GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
- GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
- GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
- GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
- GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
- GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
- GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
- GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
- NorthRXM2SxDO : out t_axi4m2s;
- NorthTXM2SxDI : in t_axi4m2s;
- NorthTXS2MxDO : out t_axi4s2m;
- EastRXM2SxDO : out t_axi4m2s;
- EastTXM2SxDI : in t_axi4m2s;
- EastTXS2MxDO : out t_axi4s2m;
- SouthRXM2SxDO : out t_axi4m2s;
- SouthTXM2SxDI : in t_axi4m2s;
- SouthTXS2MxDO : out t_axi4s2m;
- WestRXM2SxDO : out t_axi4m2s;
- WestTXM2SxDI : in t_axi4m2s;
- WestTXS2MxDO : out t_axi4s2m;
- NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- NorthRXNFCM2SxDO : out t_axi4nfcm2s;
- NorthTXNFCM2SxDI : in t_axi4nfcm2s;
- NorthTXNFCS2MxDO : out t_axi4nfcs2m;
- EastRXNFCM2SxDO : out t_axi4nfcm2s;
- EastTXNFCM2SxDI : in t_axi4nfcm2s;
- EastTXNFCS2MxDO : out t_axi4nfcs2m;
- SouthRXNFCM2SxDO : out t_axi4nfcm2s;
- SouthTXNFCM2SxDI : in t_axi4nfcm2s;
- SouthTXNFCS2mxDO : out t_axi4nfcs2m;
- WestRXNFCM2SxDO : out t_axi4nfcm2s;
- WestTXNFCM2SxDI : in t_axi4nfcm2s;
- WestTXNFCS2MxDO : out t_axi4nfcs2m;
- AuroraCtrlxDI : in t_aurora_control;
- AuroraStatusxDO : out t_aurora_status;
- AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
- AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0));
+ GTRefClkxCI : in t_gt_ref_slave_clk;
+ AuroraClkxCI : in t_aurora_slave_clk;
+ AuroraClkxCO : out t_aurora_master_clk;
+ AuroraResetxRI : in t_aurora_slave_reset;
+ AuroraResetxRO : out t_aurora_master_link_reset;
+ RXResetxRI : in t_rx_reset;
+ RXFifoResetDonexDO : out t_rx_fifo_reset_done;
+ GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
+ NorthRXM2SxDO : out t_axi4m2s;
+ NorthRXS2MxDI : in t_axi4s2m;
+ NorthTXM2SxDI : in t_axi4m2s;
+ NorthTXS2MxDO : out t_axi4s2m;
+ EastRXM2SxDO : out t_axi4m2s;
+ EastRXS2MxDI : in t_axi4s2m;
+ EastTXM2SxDI : in t_axi4m2s;
+ EastTXS2MxDO : out t_axi4s2m;
+ SouthRXM2SxDO : out t_axi4m2s;
+ SouthRXS2MxDI : in t_axi4s2m;
+ SouthTXM2SxDI : in t_axi4m2s;
+ SouthTXS2MxDO : out t_axi4s2m;
+ WestRXM2SxDO : out t_axi4m2s;
+ WestRXS2MxDI : in t_axi4s2m;
+ WestTXM2SxDI : in t_axi4m2s;
+ WestTXS2MxDO : out t_axi4s2m;
+ NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ NorthRXNFCM2SxDO : out t_axi4nfcm2s;
+ NorthTXNFCM2SxDI : in t_axi4nfcm2s;
+ NorthTXNFCS2MxDO : out t_axi4nfcs2m;
+ EastRXNFCM2SxDO : out t_axi4nfcm2s;
+ EastTXNFCM2SxDI : in t_axi4nfcm2s;
+ EastTXNFCS2MxDO : out t_axi4nfcs2m;
+ SouthRXNFCM2SxDO : out t_axi4nfcm2s;
+ SouthTXNFCM2SxDI : in t_axi4nfcm2s;
+ SouthTXNFCS2mxDO : out t_axi4nfcs2m;
+ WestRXNFCM2SxDO : out t_axi4nfcm2s;
+ WestTXNFCM2SxDI : in t_axi4nfcm2s;
+ WestTXNFCS2MxDO : out t_axi4nfcs2m;
+ AuroraCtrlxDI : in t_aurora_control;
+ AuroraStatusxDO : out t_aurora_status;
+ AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
+ AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0);
+ NorthRXFifoStatusxDO : out t_axi4fifo_status;
+ EastRXFifoStatusxDO : out t_axi4fifo_status;
+ SouthRXFifoStatusxDO : out t_axi4fifo_status;
+ WestRXFifoStatusxDO : out t_axi4fifo_status;
+ AxisFifoErrorxDO : out t_axi4fifo_error);
end component scalp_aurora_phy;
-- Signals
-- Clocks
-- Processing system clock
- signal PSSysClkxC : std_logic := '0';
+ signal PSSysClkxC : std_logic := '0';
-- GTP Clocks
-- signal GTPRefClk0xC : std_logic := '0';
-- signal GTPRefClk1xC : std_logic := '0';
- signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
- signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
-- Resets
-- Processing system reset
- signal PSSysResetxR : std_logic := '0';
+ signal PSSysResetxR : std_logic := '0';
-- Scalp Aurora Phy
- signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
- signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
- signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
- signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
- signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
- signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
- signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
- signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
- signal NorthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal EastFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal SouthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal WestFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
+ signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
+ signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
+ signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
+ signal RXResetxR : t_rx_reset := C_NO_RX_RESET;
+ signal RXFifoResetDonexD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal RXFifoResetDoneDelayedxD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
+ signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
+ signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
+ signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal NorthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal EastRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal SouthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal WestRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal AxisFifoErrorxD : t_axi4fifo_error := C_NO_AXI4_FIFO_ERROR;
-- Scalp Axi Lite interface and IRQ
- signal InterruptxS : std_ulogic := '0';
- signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RdValidxS : std_ulogic := '0';
- signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WrValidxS : std_ulogic := '0';
+ signal InterruptxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
-- Zynq Reg Bank
- type t_status_send_word is (E_IDLE, E_SEND);
-
- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
- signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
- signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
- --
- signal NorthNativeSlavexD : t_native_fifo_slave;
- signal NorthNativeMasterxD : t_native_fifo_master;
- signal EastNativeSlavexD : t_native_fifo_slave;
- signal EastNativeMasterxD : t_native_fifo_master;
- signal SouthNativeSlavexD : t_native_fifo_slave;
- signal SouthNativeMasterxD : t_native_fifo_master;
- signal WestNativeSlavexD : t_native_fifo_slave;
- signal WestNativeMasterxD : t_native_fifo_master;
+ -- type t_status_send_word is (E_IDLE, E_SEND);
+
+ -- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- --
+ -- signal NorthNativeSlavexD : t_native_fifo_slave;
+ -- signal NorthNativeMasterxD : t_native_fifo_master;
+ -- signal EastNativeSlavexD : t_native_fifo_slave;
+ -- signal EastNativeMasterxD : t_native_fifo_master;
+ -- signal SouthNativeSlavexD : t_native_fifo_slave;
+ -- signal SouthNativeMasterxD : t_native_fifo_master;
+ -- signal WestNativeSlavexD : t_native_fifo_slave;
+ -- signal WestNativeMasterxD : t_native_fifo_master;
--
-- signal InterruptRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- signal InterruptRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- North
- signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- East
- signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- South
- signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- West
- signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- Debug
-- signal CntRstxR : std_ulogic := '0';
- signal ClkEnxS : std_ulogic := '0';
- signal DataCounterxD : std_ulogic_vector(31 downto 0) := (others => '0');
+ signal ClkEnxS : std_ulogic := '0';
+ signal NorthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal NorthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal EastDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal EastDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal SouthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal SouthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal WestDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal WestDataCounterxDP : unsigned(31 downto 0) := (others => '0');
--
- signal DebugCounterResetxR : std_ulogic := '0';
- signal DebugRXFifoResetxR : std_ulogic := '0';
- signal DebugBackPressureResetxR : std_ulogic := '0';
+ signal DebugCounterResetxR : t_if_common_reset := C_NO_IF_COMMON_RESET;
+ signal DebugRXFifoResetxR : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
+ signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
- -- Resets
- -- attribute mark_debug of PSSysResetxR : signal is "true";
- -- attribute keep of PSSysResetxR : signal is "true";
- -- attribute mark_debug of AuroraResetSlavexR : signal is "true";
- -- attribute keep of AuroraResetSlavexR : signal is "true";
- -- attribute mark_debug of AuroraResetMasterLinkxR : signal is "true";
- -- attribute keep of AuroraResetMasterLinkxR : signal is "true";
- -- Aurora
- attribute mark_debug of NorthFifoStatusxD : signal is "true";
- attribute keep of NorthFifoStatusxD : signal is "true";
- attribute mark_debug of EastFifoStatusxD : signal is "true";
- attribute keep of EastFifoStatusxD : signal is "true";
- attribute mark_debug of SouthFifoStatusxD : signal is "true";
- attribute keep of SouthFifoStatusxD : signal is "true";
- attribute mark_debug of WestFifoStatusxD : signal is "true";
- attribute keep of WestFifoStatusxD : signal is "true";
- -- attribute mark_debug of NorthRXM2SxD : signal is "true";
- -- attribute keep of NorthRXM2SxD : signal is "true";
- -- attribute mark_debug of NorthRXFromFifoS2MxD : signal is "true";
- -- attribute keep of NorthRXFromFifoS2MxD : signal is "true";
- -- attribute mark_debug of NorthRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute keep of NorthRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute mark_debug of NorthRXfromPhyTXfromFifoS2MxD : signal is "true";
- -- attribute keep of NorthRXfromPhyTXfromFifoS2MxD : signal is "true";
- -- attribute mark_debug of EastFifoStatusxD : signal is "true";
- -- attribute keep of EastFifoStatusxD : signal is "true";
- -- attribute mark_debug of EastRXM2SxD : signal is "true";
- -- attribute keep of EastRXM2SxD : signal is "true";
- -- attribute mark_debug of EastRXFromFifoS2MxD : signal is "true";
- -- attribute keep of EastRXFromFifoS2MxD : signal is "true";
- -- attribute mark_debug of EastRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute keep of EastRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute mark_debug of EastRXfromPhyTXfromFifoS2MxD : signal is "true";
- -- attribute keep of EastRXfromPhyTXfromFifoS2MxD : signal is "true";
- -- attribute mark_debug of SouthFifoStatusxD : signal is "true";
- -- attribute keep of SouthFifoStatusxD : signal is "true";
- -- attribute mark_debug of SouthRXM2SxD : signal is "true";
- -- attribute keep of SouthRXM2SxD : signal is "true";
- -- attribute mark_debug of SouthRXFromFifoS2MxD : signal is "true";
- -- attribute keep of SouthRXFromFifoS2MxD : signal is "true";
- -- attribute mark_debug of SouthRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute keep of SouthRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute mark_debug of SouthRXfromPhyTXfromFifoS2MxD : signal is "true";
- -- attribute keep of SouthRXfromPhyTXfromFifoS2MxD : signal is "true";
- -- attribute mark_debug of WestFifoStatusxD : signal is "true";
- -- attribute keep of WestFifoStatusxD : signal is "true";
- -- attribute mark_debug of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
- -- attribute mark_debug of WestRXFromFifoS2MxD : signal is "true";
- -- attribute keep of WestRXFromFifoS2MxD : signal is "true";
- -- attribute mark_debug of WestRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute keep of WestRXfromPhyTXfromFifoM2SxD : signal is "true";
- -- attribute mark_debug of WestRXfromPhyTXfromFifoS2MxD : signal is "true";
- -- attribute keep of WestRXfromPhyTXfromFifoS2MxD : signal is "true";
- --
- attribute mark_debug of NorthRXM2SxD : signal is "true";
- attribute keep of NorthRXM2SxD : signal is "true";
- attribute mark_debug of NorthTXM2SxD : signal is "true";
- attribute keep of NorthTXM2SxD : signal is "true";
- attribute mark_debug of NorthTXS2MxD : signal is "true";
- attribute keep of NorthTXS2MxD : signal is "true";
- attribute mark_debug of EastRXM2SxD : signal is "true";
- attribute keep of EastRXM2SxD : signal is "true";
- attribute mark_debug of EastTXM2SxD : signal is "true";
- attribute keep of EastTXM2SxD : signal is "true";
- attribute mark_debug of EastTXS2MxD : signal is "true";
- attribute keep of EastTXS2MxD : signal is "true";
- attribute mark_debug of SouthRXM2SxD : signal is "true";
- attribute keep of SouthRXM2SxD : signal is "true";
- attribute mark_debug of SouthTXM2SxD : signal is "true";
- attribute keep of SouthTXM2SxD : signal is "true";
- attribute mark_debug of SouthTXS2MxD : signal is "true";
- attribute keep of SouthTXS2MxD : signal is "true";
- attribute mark_debug of WestRXM2SxD : signal is "true";
- attribute keep of WestRXM2SxD : signal is "true";
- attribute mark_debug of WestTXM2SxD : signal is "true";
- attribute keep of WestTXM2SxD : signal is "true";
- attribute mark_debug of WestTXS2MxD : signal is "true";
- attribute keep of WestTXS2MxD : signal is "true";
- attribute mark_debug of NorthRXNFCM2SxD : signal is "true";
- attribute keep of NorthRXNFCM2SxD : signal is "true";
- attribute mark_debug of NorthTXNFCM2SxD : signal is "true";
- attribute keep of NorthTXNFCM2SxD : signal is "true";
- attribute mark_debug of NorthTXNFCS2MxD : signal is "true";
- attribute keep of NorthTXNFCS2MxD : signal is "true";
- attribute mark_debug of EastRXNFCM2SxD : signal is "true";
- attribute keep of EastRXNFCM2SxD : signal is "true";
- attribute mark_debug of EastTXNFCM2SxD : signal is "true";
- attribute keep of EastTXNFCM2SxD : signal is "true";
- attribute mark_debug of EastTXNFCS2MxD : signal is "true";
- attribute keep of EastTXNFCS2MxD : signal is "true";
- attribute mark_debug of SouthRXNFCM2SxD : signal is "true";
- attribute keep of SouthRXNFCM2SxD : signal is "true";
- attribute mark_debug of SouthTXNFCM2SxD : signal is "true";
- attribute keep of SouthTXNFCM2SxD : signal is "true";
- attribute mark_debug of SouthTXNFCS2mxD : signal is "true";
- attribute keep of SouthTXNFCS2mxD : signal is "true";
- attribute mark_debug of WestRXNFCM2SxD : signal is "true";
- attribute keep of WestRXNFCM2SxD : signal is "true";
- attribute mark_debug of WestTXNFCM2SxD : signal is "true";
- attribute keep of WestTXNFCM2SxD : signal is "true";
- attribute mark_debug of WestTXNFCS2MxD : signal is "true";
- attribute keep of WestTXNFCS2MxD : signal is "true";
- attribute mark_debug of AuroraCtrlxD : signal is "true";
- attribute keep of AuroraCtrlxD : signal is "true";
- attribute mark_debug of AuroraStatusxD : signal is "true";
- attribute keep of AuroraStatusxD : signal is "true";
- -- attribute mark_debug of NorthTXM2SxD : signal is "true";
- -- attribute keep of NorthTXM2SxD : signal is "true";
- -- attribute mark_debug of EastTXM2SxD : signal is "true";
- -- attribute keep of EastTXM2SxD : signal is "true";
- -- attribute mark_debug of SouthTXM2SxD : signal is "true";
- -- attribute keep of SouthTXM2SxD : signal is "true";
- -- attribute mark_debug of WestTXM2SxD : signal is "true";
- -- attribute keep of WestTXM2SxD : signal is "true";
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
+ -- North
+ attribute mark_debug of NorthRXM2SxD : signal is "true";
+ attribute keep of NorthRXM2SxD : signal is "true";
+ attribute mark_debug of NorthRXS2MxD : signal is "true";
+ attribute keep of NorthRXS2MxD : signal is "true";
+ -- East
+ -- attribute keep of EastRXM2SxD : signal is "true";
+ -- attribute keep of EastRXM2SxD : signal is "true";
+ -- attribute keep of EastRXS2MxD : signal is "true";
+ -- attribute keep of EastRXS2MxD : signal is "true";
+ -- South
+ attribute mark_debug of SouthRXM2SxD : signal is "true";
+ attribute keep of SouthRXM2SxD : signal is "true";
+ attribute mark_debug of SouthRXS2MxD : signal is "true";
+ attribute keep of SouthRXS2MxD : signal is "true";
+ -- West
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXS2MxD : signal is "true";
+ -- attribute keep of WestRXS2MxD : signal is "true";
begin
@@ -733,6 +654,9 @@ begin
end block PllClocksxB;
GTPhyxB : block is
+
+ constant C_RX_FIFO_RST_DONE_DLY_TICKS : integer := 100;
+
begin -- block GTPhyxB
-- GTP
@@ -761,474 +685,114 @@ begin
end block CtrlxB;
- ScalpAuroraPyhxI : entity work.scalp_aurora_phy
+ ScalpAuroraPhyxI : entity work.scalp_aurora_phy
generic map (
- C_DEBUG_MODE => C_DEBUG_MODE)
+ C_DEBUG_MODE => C_DEBUG_MODE,
+ C_RX_FIFO_MODE => C_RX_FIFO_MODE,
+ C_RX_FIFO_RST_DONE_DLY_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
port map (
+ -- Clocks
-- GTP Ref Clocks
- GTRefClkxCI => GTRefClk0xC,
+ GTRefClkxCI => GTRefClk0xC,
-- Aurora System and GTP Clocks
- AuroraClkxCI => AuroraClkSlavexC,
- AuroraClkxCO => AuroraClkMasterxC,
+ AuroraClkxCI => AuroraClkSlavexC,
+ AuroraClkxCO => AuroraClkMasterxC,
+ -- Reset
-- Aurora Reset
- AuroraResetxRI => AuroraResetSlavexR,
- AuroraResetxRO => AuroraResetMasterLinkxR,
+ AuroraResetxRI => AuroraResetSlavexR,
+ AuroraResetxRO => AuroraResetMasterLinkxR,
+ -- RX Fifo and Back Pressure Reset
+ RXResetxRI => RXResetxR,
+ RXFifoResetDonexDO => RXFifoResetDonexD,
+ RXFifoResetDoneDelayedxDO => RXFifoResetDoneDelayedxD,
+ -- Back Pressure Reset
-- GTP Serial IO
-- North
- GTPFromNorthxDI => GTPFromNorthxD,
- GTPToNorthxDO => GTPToNorthxD,
+ GTPFromNorthxDI => GTPFromNorthxD,
+ GTPToNorthxDO => GTPToNorthxD,
-- East
- GTPFromEastxDI => GTPFromEastxD,
- GTPToEastxDO => GTPToEastxD,
+ GTPFromEastxDI => GTPFromEastxD,
+ GTPToEastxDO => GTPToEastxD,
-- South
- GTPFromSouthxDI => GTPFromSouthxD,
- GTPToSouthxDO => GTPToSouthxD,
+ GTPFromSouthxDI => GTPFromSouthxD,
+ GTPToSouthxDO => GTPToSouthxD,
-- West
- GTPFromWestxDI => GTPFromWestxD,
- GTPToWestxDO => GTPToWestxD,
+ GTPFromWestxDI => GTPFromWestxD,
+ GTPToWestxDO => GTPToWestxD,
-- Axi4 Framing Interface
-- North
- NorthRXM2SxDO => NorthRXM2SxD,
- NorthTXM2SxDI => NorthTXM2SxD,
- NorthTXS2MxDO => NorthTXS2MxD,
+ NorthRXM2SxDO => NorthRXM2SxD,
+ NorthRXS2MxDI => NorthRXS2MxD,
+ NorthTXM2SxDI => NorthTXM2SxD,
+ NorthTXS2MxDO => NorthTXS2MxD,
-- East
- EastRXM2SxDO => EastRXM2SxD,
- EastTXM2SxDI => EastTXM2SxD,
- EastTXS2MxDO => EastTXS2MxD,
+ EastRXM2SxDO => EastRXM2SxD,
+ EastRXS2MxDI => EastRXS2MxD,
+ EastTXM2SxDI => EastTXM2SxD,
+ EastTXS2MxDO => EastTXS2MxD,
-- South
- SouthRXM2SxDO => SouthRXM2SxD,
- SouthTXM2SxDI => SouthTXM2SxD,
- SouthTXS2MxDO => SouthTXS2MxD,
+ SouthRXM2SxDO => SouthRXM2SxD,
+ SouthRXS2MxDI => SouthRXS2MxD,
+ SouthTXM2SxDI => SouthTXM2SxD,
+ SouthTXS2MxDO => SouthTXS2MxD,
-- West
- WestRXM2SxDO => WestRXM2SxD,
- WestTXM2SxDI => WestTXM2SxD,
- WestTXS2MxDO => WestTXS2MxD,
+ WestRXM2SxDO => WestRXM2SxD,
+ WestRXS2MxDI => WestRXS2MxD,
+ WestTXM2SxDI => WestTXM2SxD,
+ WestTXS2MxDO => WestTXS2MxD,
-- Axi4 Framing UFC Interface
-- North
- NorthRXUFCM2SxDO => NorthRXUFCM2SxD,
- NorthTXUFCM2SxDI => NorthTXUFCM2SxD,
- NorthTXUFCS2MxDO => NorthTXUFCS2MxD,
+ NorthRXUFCM2SxDO => NorthRXUFCM2SxD,
+ NorthTXUFCM2SxDI => NorthTXUFCM2SxD,
+ NorthTXUFCS2MxDO => NorthTXUFCS2MxD,
-- East
- EastRXUFCM2SxDO => EastRXUFCM2SxD,
- EastTXUFCM2SxDI => EastTXUFCM2SxD,
- EastTXUFCS2MxDO => EastTXUFCS2MxD,
+ EastRXUFCM2SxDO => EastRXUFCM2SxD,
+ EastTXUFCM2SxDI => EastTXUFCM2SxD,
+ EastTXUFCS2MxDO => EastTXUFCS2MxD,
-- South
- SouthRXUFCM2SxDO => SouthRXUFCM2SxD,
- SouthTXUFCM2SxDI => SouthTXUFCM2SxD,
- SouthTXUFCS2MxDO => SouthTXUFCS2MxD,
+ SouthRXUFCM2SxDO => SouthRXUFCM2SxD,
+ SouthTXUFCM2SxDI => SouthTXUFCM2SxD,
+ SouthTXUFCS2MxDO => SouthTXUFCS2MxD,
-- West
- WestRXUFCM2SxDO => WestRXUFCM2SxD,
- WestTXUFCM2SxDI => WestTXUFCM2SxD,
- WestTXUFCS2MxDO => WestTXUFCS2MxD,
+ WestRXUFCM2SxDO => WestRXUFCM2SxD,
+ WestTXUFCM2SxDI => WestTXUFCM2SxD,
+ WestTXUFCS2MxDO => WestTXUFCS2MxD,
-- Axi4 Framing NFC Interface
+ -- The NFC interface is not available when the
+ -- constant C_RX_FIFO_MODE is set to TRUE.
-- North
- NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
- NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
- NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
+ NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
+ NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
+ NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
-- East
- EastRXNFCM2SxDO => EastRXNFCM2SxD,
- EastTXNFCM2SxDI => EastTXNFCM2SxD,
- EastTXNFCS2MxDO => EastTXNFCS2MxD,
+ EastRXNFCM2SxDO => EastRXNFCM2SxD,
+ EastTXNFCM2SxDI => EastTXNFCM2SxD,
+ EastTXNFCS2MxDO => EastTXNFCS2MxD,
-- South
- SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
- SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
- SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
+ SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
+ SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
+ SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
-- West
- WestRXNFCM2SxDO => WestRXNFCM2SxD,
- WestTXNFCM2SxDI => WestTXNFCM2SxD,
- WestTXNFCS2MxDO => WestTXNFCS2MxD,
+ WestRXNFCM2SxDO => WestRXNFCM2SxD,
+ WestTXNFCM2SxDI => WestTXNFCM2SxD,
+ WestTXNFCS2MxDO => WestTXNFCS2MxD,
-- Aurora Ctrl + Status
- AuroraCtrlxDI => AuroraCtrlxD,
- AuroraStatusxDO => AuroraStatusxD,
+ AuroraCtrlxDI => AuroraCtrlxD,
+ AuroraStatusxDO => AuroraStatusxD,
-- DRP Port
- AuroraDRPM2SxDI => (others => C_NO_DRP_M2S),
- AuroraDRPS2MxDO => open);
-
- RXFifoxB : block is
-
- signal RXFifoRstxRAN : std_ulogic := '0';
-
- begin -- block RXFifoxB
-
- RXFifoRstxAS : RXFifoRstxRAN <= (not AuroraClkMasterxC.PllNotLockedxS) and (not DebugRXFifoResetxR);
-
- ScalpAuroraPhyRXFifoxI : entity work.scalp_aurora_phy_rx_fifo
- port map (
- -- Clocks and reset
- RXClkxCI => AuroraClkMasterxC.UserClkxC,
- TXClkxCI => AuroraClkMasterxC.UserClkxC,
- RXRstxRANI => RXFifoRstxRAN,
- -- North
- -- Fifo RX Side
- NorthRXM2SxDI => NorthRXM2SxD,
- NorthRXS2MxDO => NorthRXFromFifoS2MxD,
- -- Fifo TX Side
- NorthTXM2SxDO => NorthRXfromPhyTXfromFifoM2SxD,
- NorthTXS2MxDI => NorthRXfromPhyTXfromFifoS2MxD,
- NorthFifoStatusxDO => NorthFifoStatusxD,
- -- East
- -- Fifo RX Side
- EastRXM2SxDI => EastRXM2SxD,
- EastRXS2MxDO => EastRXFromFifoS2MxD,
- -- Fifo TX Side
- EastTXM2SxDO => EastRXfromPhyTXfromFifoM2SxD,
- EastTXS2MxDI => EastRXfromPhyTXfromFifoS2MxD,
- EastFifoStatusxDO => EastFifoStatusxD,
- -- South
- -- Fifo RX Side
- SouthRXM2SxDI => SouthRXM2SxD,
- SouthRXS2MxDO => SouthRXFromFifoS2MxD,
- -- Fifo TX Side
- SouthTXM2SxDO => SouthRXfromPhyTXfromFifoM2SxD,
- SouthTXS2MxDI => SouthRXfromPhyTXfromFifoS2MxD,
- SouthFifoStatusxDO => SouthFifoStatusxD,
- -- West
- -- Fifo RX Side
- WestRXM2SxDI => WestRXM2SxD,
- WestRXS2MxDO => WestRXFromFifoS2MxD,
- -- Fifo TX Side
- WestTXM2SxDO => WestRXfromPhyTXfromFifoM2SxD,
- WestTXS2MxDI => WestRXfromPhyTXfromFifoS2MxD,
- WestFifoStatusxDO => WestFifoStatusxD);
-
- end block RXFifoxB;
-
- BackPressurexB : block is
-
- signal BackPressureResetxR : std_ulogic := '0';
- -- North
- signal NorthProgFullxSN : std_ulogic := '0';
- signal NorthProgFullxSP : std_ulogic := '0';
- signal NorthProgEmptyxSN : std_ulogic := '0';
- signal NorthProgEmptyxSP : std_ulogic := '0';
- signal NorthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal NorthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal NorthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthNFCValidxSN : std_ulogic := '0';
- signal NorthNFCValidxSP : std_ulogic := '0';
- -- East
- signal EastProgFullxSN : std_ulogic := '0';
- signal EastProgFullxSP : std_ulogic := '0';
- signal EastProgEmptyxSN : std_ulogic := '0';
- signal EastProgEmptyxSP : std_ulogic := '0';
- signal EastNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal EastNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal EastNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastNFCValidxSN : std_ulogic := '0';
- signal EastNFCValidxSP : std_ulogic := '0';
- -- South
- signal SouthProgFullxSN : std_ulogic := '0';
- signal SouthProgFullxSP : std_ulogic := '0';
- signal SouthProgEmptyxSN : std_ulogic := '0';
- signal SouthProgEmptyxSP : std_ulogic := '0';
- signal SouthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal SouthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal SouthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthNFCValidxSN : std_ulogic := '0';
- signal SouthNFCValidxSP : std_ulogic := '0';
- -- West
- signal WestProgFullxSN : std_ulogic := '0';
- signal WestProgFullxSP : std_ulogic := '0';
- signal WestProgEmptyxSN : std_ulogic := '0';
- signal WestProgEmptyxSP : std_ulogic := '0';
- signal WestNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal WestNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal WestNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestNFCValidxSN : std_ulogic := '0';
- signal WestNFCValidxSP : std_ulogic := '0';
-
- -- Attributes
- attribute mark_debug : string;
- attribute keep : string;
- --
- attribute mark_debug of BackPressureResetxR : signal is "true";
- attribute keep of BackPressureResetxR : signal is "true";
- --
- attribute mark_debug of NorthNFCStatexDP : signal is "true";
- attribute keep of NorthNFCStatexDP : signal is "true";
- attribute mark_debug of NorthNFCDataxDP : signal is "true";
- attribute keep of NorthNFCDataxDP : signal is "true";
- attribute mark_debug of NorthNFCValidxSP : signal is "true";
- attribute keep of NorthNFCValidxSP : signal is "true";
- --
- attribute mark_debug of EastNFCStatexDP : signal is "true";
- attribute keep of EastNFCStatexDP : signal is "true";
- attribute mark_debug of EastNFCDataxDP : signal is "true";
- attribute keep of EastNFCDataxDP : signal is "true";
- attribute mark_debug of EastNFCValidxSP : signal is "true";
- attribute keep of EastNFCValidxSP : signal is "true";
- --
- attribute mark_debug of SouthNFCStatexDP : signal is "true";
- attribute keep of SouthNFCStatexDP : signal is "true";
- attribute mark_debug of SouthNFCDataxDP : signal is "true";
- attribute keep of SouthNFCDataxDP : signal is "true";
- attribute mark_debug of SouthNFCValidxSP : signal is "true";
- attribute keep of SouthNFCValidxSP : signal is "true";
- --
- attribute mark_debug of WestNFCStatexDP : signal is "true";
- attribute keep of WestNFCStatexDP : signal is "true";
- attribute mark_debug of WestNFCDataxDP : signal is "true";
- attribute keep of WestNFCDataxDP : signal is "true";
- attribute mark_debug of WestNFCValidxSP : signal is "true";
- attribute keep of WestNFCValidxSP : signal is "true";
-
- begin -- block BackPressurexB
-
- BackPressureResetxAS : BackPressureResetxR <= AuroraClkMasterxC.PllNotLockedxS or
- DebugBackPressureResetxR;
- -- NFC Data and valid signals
- NorthNFCDataxAS : NorthTXNFCM2SxD.DataxD <= NorthNFCDataxDP;
- NorthNFCValidxAS : NorthTXNFCM2SxD.ValidxS <= NorthNFCValidxSP;
- NorthProgFullxAS : NorthProgFullxSN <= NorthFifoStatusxD.ProgFullxS;
- NorthProgEmptyxAS : NorthProgEmptyxSN <= NorthFifoStatusxD.ProgEmptyxS;
- EastNFCDataxAS : EastTXNFCM2SxD.DataxD <= EastNFCDataxDP;
- EastNFCValidxAS : EastTXNFCM2SxD.ValidxS <= EastNFCValidxSP;
- SouthNFCDataxAS : SouthTXNFCM2SxD.DataxD <= SouthNFCDataxDP;
- SouthNFCValidxAS : SouthTXNFCM2SxD.ValidxS <= SouthNFCValidxSP;
- WestNFCDataxAS : WestTXNFCM2SxD.DataxD <= WestNFCDataxDP;
- WestNFCValidxAS : WestTXNFCM2SxD.ValidxS <= WestNFCValidxSP;
-
- UpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
- BackPressureResetxR) is
- begin -- process UpdateRegxP
- if BackPressureResetxR = '1' then
- NorthProgFullxSP <= '0';
- NorthProgEmptyxSP <= '0';
- NorthNFCStatexDP <= C_NFC_IDLE;
- NorthNFCDataxDP <= (others => '0');
- NorthNFCValidxSP <= '0';
- EastProgFullxSP <= '0';
- EastProgEmptyxSP <= '0';
- EastNFCStatexDP <= C_NFC_IDLE;
- EastNFCDataxDP <= (others => '0');
- EastNFCValidxSP <= '0';
- SouthProgFullxSP <= '0';
- SouthProgEmptyxSP <= '0';
- SouthNFCStatexDP <= C_NFC_IDLE;
- SouthNFCDataxDP <= (others => '0');
- SouthNFCValidxSP <= '0';
- WestProgFullxSP <= '0';
- WestProgEmptyxSP <= '0';
- WestNFCStatexDP <= C_NFC_IDLE;
- WestNFCDataxDP <= (others => '0');
- WestNFCValidxSP <= '0';
- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- NorthProgFullxSP <= NorthProgFullxSN;
- NorthProgEmptyxSP <= NorthProgEmptyxSN;
- NorthNFCStatexDP <= NorthNFCStatexDN;
- NorthNFCDataxDP <= NorthNFCDataxDN;
- NorthNFCValidxSP <= NorthNFCValidxSN;
- EastProgFullxSP <= EastProgFullxSN;
- EastProgEmptyxSP <= EastProgEmptyxSN;
- EastNFCStatexDP <= EastNFCStatexDN;
- EastNFCDataxDP <= EastNFCDataxDN;
- EastNFCValidxSP <= EastNFCValidxSN;
- SouthProgFullxSP <= SouthProgFullxSN;
- SouthProgEmptyxSP <= SouthProgEmptyxSN;
- SouthNFCStatexDP <= SouthNFCStatexDN;
- SouthNFCDataxDP <= SouthNFCDataxDN;
- SouthNFCValidxSP <= SouthNFCValidxSN;
- WestProgFullxSP <= WestProgFullxSN;
- WestProgEmptyxSP <= WestProgEmptyxSN;
- WestNFCStatexDP <= WestNFCStatexDN;
- WestNFCDataxDP <= WestNFCDataxDN;
- WestNFCValidxSP <= WestNFCValidxSN;
- end if;
- end process UpdateRegxP;
-
- NorthNFCStatexP : process (NorthNFCDataxDP, NorthNFCStatexDP,
- NorthNFCValidxSP, NorthProgEmptyxSN,
- NorthProgEmptyxSP, NorthProgFullxSN,
- NorthProgFullxSP,
- NorthTXNFCS2MxD.ReadyxS) is
- begin -- process NorthNFCStatexP
- -- Default values
- NorthNFCStatexDN <= NorthNFCStatexDP;
- NorthNFCDataxDN <= NorthNFCDataxDP;
- NorthNFCValidxSN <= NorthNFCValidxSP;
-
- case NorthNFCStatexDP is
- when C_NFC_IDLE =>
- NorthNFCStatexDN <= C_NFC_IS_XON;
- when C_NFC_IS_XON =>
- if NorthProgFullxSP = '0' and NorthProgFullxSN = '1' then --or
- --(NorthRXFromFifoS2MxD.ReadyxS = '0') then
- NorthNFCDataxDN <= C_NFC_XOFF;
- NorthNFCValidxSN <= '1';
- NorthNFCStatexDN <= C_NFC_SEND_XOFF;
- end if;
-
- when C_NFC_IS_XOFF =>
- if NorthProgEmptyxSP = '0' and NorthProgEmptyxSN = '1' then -- and
- --(NorthRXFromFifoS2MxD.ReadyxS = '1') then
- NorthNFCDataxDN <= C_NFC_XON;
- NorthNFCValidxSN <= '1';
- NorthNFCStatexDN <= C_NFC_SEND_XON;
- end if;
-
- when C_NFC_SEND_XON =>
- if NorthTXNFCS2MxD.ReadyxS = '1' then
- NorthNFCValidxSN <= '0';
- NorthNFCStatexDN <= C_NFC_IS_XON;
- end if;
-
- when C_NFC_SEND_XOFF =>
- if NorthTXNFCS2MxD.ReadyxS = '1' then
- NorthNFCValidxSN <= '0';
- NorthNFCStatexDN <= C_NFC_IS_XOFF;
- end if;
-
- when others => null;
- end case;
-
- end process NorthNFCStatexP;
-
- EastNFCStatexP : process (EastNFCDataxDP, EastNFCStatexDP,
- EastNFCValidxSP, EastProgEmptyxSN,
- EastProgEmptyxSP, EastProgFullxSN,
- EastProgFullxSP,
- EastTXNFCS2MxD.ReadyxS) is
- begin -- process EastNFCStatexP
- -- Default values
- EastNFCStatexDN <= EastNFCStatexDP;
- EastNFCDataxDN <= EastNFCDataxDP;
- EastNFCValidxSN <= EastNFCValidxSP;
-
- case EastNFCStatexDP is
- when C_NFC_IDLE =>
- EastNFCStatexDN <= C_NFC_IS_XON;
- when C_NFC_IS_XON =>
- if EastProgFullxSP = '0' and EastProgFullxSN = '1' then --or
- --(EastRXFromFifoS2MxD.ReadyxS = '0') then
- EastNFCDataxDN <= C_NFC_XOFF;
- EastNFCValidxSN <= '1';
- EastNFCStatexDN <= C_NFC_SEND_XOFF;
- end if;
-
- when C_NFC_IS_XOFF =>
- if EastProgEmptyxSP = '0' and EastProgEmptyxSN = '1' then -- and
- --(EastRXFromFifoS2MxD.ReadyxS = '1') then
- EastNFCDataxDN <= C_NFC_XON;
- EastNFCValidxSN <= '1';
- EastNFCStatexDN <= C_NFC_SEND_XON;
- end if;
-
- when C_NFC_SEND_XON =>
- if EastTXNFCS2MxD.ReadyxS = '1' then
- EastNFCValidxSN <= '0';
- EastNFCStatexDN <= C_NFC_IS_XON;
- end if;
-
- when C_NFC_SEND_XOFF =>
- if EastTXNFCS2MxD.ReadyxS = '1' then
- EastNFCValidxSN <= '0';
- EastNFCStatexDN <= C_NFC_IS_XOFF;
- end if;
-
- when others => null;
- end case;
-
- end process EastNFCStatexP;
-
- SouthNFCStatexP : process (SouthNFCDataxDP, SouthNFCStatexDP,
- SouthNFCValidxSP, SouthProgEmptyxSN,
- SouthProgEmptyxSP, SouthProgFullxSN,
- SouthProgFullxSP,
- SouthTXNFCS2MxD.ReadyxS) is
- begin -- process SouthNFCStatexP
- -- Default values
- SouthNFCStatexDN <= SouthNFCStatexDP;
- SouthNFCDataxDN <= SouthNFCDataxDP;
- SouthNFCValidxSN <= SouthNFCValidxSP;
-
- case SouthNFCStatexDP is
- when C_NFC_IDLE =>
- SouthNFCStatexDN <= C_NFC_IS_XON;
- when C_NFC_IS_XON =>
- if SouthProgFullxSP = '0' and SouthProgFullxSN = '1' then -- or
- --(SouthRXFromFifoS2MxD.ReadyxS = '0') then
- SouthNFCDataxDN <= C_NFC_XOFF;
- SouthNFCValidxSN <= '1';
- SouthNFCStatexDN <= C_NFC_SEND_XOFF;
- end if;
-
- when C_NFC_IS_XOFF =>
- if SouthProgEmptyxSP = '0' and SouthProgEmptyxSN = '1' then -- and
- --(SouthRXFromFifoS2MxD.ReadyxS = '1') then
- SouthNFCDataxDN <= C_NFC_XON;
- SouthNFCValidxSN <= '1';
- SouthNFCStatexDN <= C_NFC_SEND_XON;
- end if;
-
- when C_NFC_SEND_XON =>
- if SouthTXNFCS2MxD.ReadyxS = '1' then
- SouthNFCValidxSN <= '0';
- SouthNFCStatexDN <= C_NFC_IS_XON;
- end if;
-
- when C_NFC_SEND_XOFF =>
- if SouthTXNFCS2MxD.ReadyxS = '1' then
- SouthNFCValidxSN <= '0';
- SouthNFCStatexDN <= C_NFC_IS_XOFF;
- end if;
-
- when others => null;
- end case;
-
- end process SouthNFCStatexP;
-
- WestNFCStatexP : process (WestNFCDataxDP, WestNFCStatexDP,
- WestNFCValidxSP, WestProgEmptyxSN,
- WestProgEmptyxSP, WestProgFullxSN,
- WestProgFullxSP,
- WestTXNFCS2MxD.ReadyxS) is
- begin -- process WestNFCStatexP
- -- Default values
- WestNFCStatexDN <= WestNFCStatexDP;
- WestNFCDataxDN <= WestNFCDataxDP;
- WestNFCValidxSN <= WestNFCValidxSP;
-
- case WestNFCStatexDP is
- when C_NFC_IDLE =>
- WestNFCStatexDN <= C_NFC_IS_XON;
- when C_NFC_IS_XON =>
- if WestProgFullxSP = '0' and WestProgFullxSN = '1' then --or
- --(WestRXFromFifoS2MxD.ReadyxS = '0') then
- WestNFCDataxDN <= C_NFC_XOFF;
- WestNFCValidxSN <= '1';
- WestNFCStatexDN <= C_NFC_SEND_XOFF;
- end if;
-
- when C_NFC_IS_XOFF =>
- if WestProgEmptyxSP = '0' and WestProgEmptyxSN = '1' then -- and
- --(WestRXFromFifoS2MxD.ReadyxS = '1') then
- WestNFCDataxDN <= C_NFC_XON;
- WestNFCValidxSN <= '1';
- WestNFCStatexDN <= C_NFC_SEND_XON;
- end if;
-
- when C_NFC_SEND_XON =>
- if WestTXNFCS2MxD.ReadyxS = '1' then
- WestNFCValidxSN <= '0';
- WestNFCStatexDN <= C_NFC_IS_XON;
- end if;
-
- when C_NFC_SEND_XOFF =>
- if WestTXNFCS2MxD.ReadyxS = '1' then
- WestNFCValidxSN <= '0';
- WestNFCStatexDN <= C_NFC_IS_XOFF;
- end if;
-
- when others => null;
- end case;
-
- end process WestNFCStatexP;
-
- end block BackPressurexB;
+ AuroraDRPM2SxDI => AuroraDRPM2SxD,
+ AuroraDRPS2MxDO => AuroraDRPS2MxD,
+ -- RX Fifo Status
+ -- North
+ NorthRXFifoStatusxDO => NorthRXFifoStatusxD,
+ -- East
+ EastRXFifoStatusxDO => EastRXFifoStatusxD,
+ -- South
+ SouthRXFifoStatusxDO => SouthRXFifoStatusxD,
+ -- West
+ WestRXFifoStatusxDO => WestRXFifoStatusxD,
+ -- Axis Fifo Error
+ AxisFifoErrorxDO => AxisFifoErrorxD);
end block GTPhyxB;
@@ -1580,66 +1144,214 @@ begin
-- end block ZynqRegBankxB;
DebugxB : block is
- begin -- block DebugxB
- ClkEnxAS : ClkEnxS <= not AuroraClkMasterxC.PllNotLockedxS;
+ -- RX Fifo reset 196 cycles
+ constant C_RX_FIFO_RST_DLY_TICKS : integer := 200;
+
+ type t_read_phy_states is (E_READ_PHY_IDLE, E_READ_PHY_S0, E_READ_PHY_S1, E_READ_PHY_S2);
+ type t_write_phy_states is (E_WRITE_PHY_IDLE, E_WRITE_PHY_W0, E_WRITE_PHY_W1,
+ E_WRITE_PHY_W2, E_WRITE_PHY_W3, E_WRITE_PHY_W4,
+ E_WRITE_PHY_W5, E_WRITE_PHY_W6, E_WRITE_PHY_W7);
+
-- North
- NorthTXDataxAS : NorthTXM2SxD.DataxD <= DataCounterxD;
- NorthTXKeepxAS : NorthTXM2SxD.KeepxD <= (others => '1');
- NorthTXLastxAS : NorthTXM2SxD.LastxS <= '0';
- NorthTXValidxAS : NorthTXM2SxD.ValidxS <= not DebugCounterResetxR;
- -- East
- EastTXDataxAS : EastTXM2SxD.DataxD <= DataCounterxD;
- EastTXKeepxAS : EastTXM2SxD.KeepxD <= (others => '1');
- EastTXLastxAS : EastTXM2SxD.LastxS <= '0';
- EastTXValidxAS : EastTXM2SxD.ValidxS <= not DebugCounterResetxR;
+ signal NorthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ signal NorthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ signal NorthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ signal NorthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- East
+ signal EastReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ signal EastReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ signal EastWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ signal EastWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
-- South
- SouthTXDataxAS : SouthTXM2SxD.DataxD <= DataCounterxD;
- SouthTXKeepxAS : SouthTXM2SxD.KeepxD <= (others => '1');
- SouthTXLastxAS : SouthTXM2SxD.LastxS <= '0';
- SouthTXValidxAS : SouthTXM2SxD.ValidxS <= not DebugCounterResetxR;
+ signal SouthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ signal SouthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ signal SouthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ signal SouthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
-- West
- WestTXDataxAS : WestTXM2SxD.DataxD <= DataCounterxD;
- WestTXKeepxAS : WestTXM2SxD.KeepxD <= (others => '1');
- WestTXLastxAS : WestTXM2SxD.LastxS <= '0';
- WestTXValidxAS : WestTXM2SxD.ValidxS <= not DebugCounterResetxR;
+ signal WestReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ signal WestReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ signal WestWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ signal WestWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
+
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ attribute mark_debug of NorthWritePhyStatexDP : signal is "true";
+ attribute keep of NorthWritePhyStatexDP : signal is "true";
+ -- attribute mark_debug of EastWritePhyStatexDP : signal is "true";
+ -- attribute keep of EastWritePhyStatexDP : signal is "true";
+ attribute mark_debug of SouthWritePhyStatexDP : signal is "true";
+ attribute keep of SouthWritePhyStatexDP : signal is "true";
+ -- attribute mark_debug of WestWritePhyStatexDP : signal is "true";
+ -- attribute keep of WestWritePhyStatexDP : signal is "true";
- DataCounterxI : entity work.data_counter
- port map (
- clk => AuroraClkMasterxC.UserClkxC,
- ce => ClkEnxS,
- sclr => DebugCounterResetxR,
- q => DataCounterxD);
+ begin -- block DebugxB
+
+ -- RX Fifo reset 196 cycles
+ -- Clock and Resets
+ -- RX Fifo
+ NorthFifoResetxAS : RXResetxR.FifoResetxR.NorthxR <=
+ '1' when
+ (DebugRXFifoResetxR.NorthxR = '1') or
+ (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ '0';
+ EastFifoResetxAS : RXResetxR.FifoResetxR.EastxR <=
+ '1' when
+ (DebugRXFifoResetxR.EastxR = '1') or
+ (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ '0';
+ SouthFifoResetxAS : RXResetxR.FifoResetxR.SouthxR <=
+ '1' when
+ (DebugRXFifoResetxR.SouthxR = '1') or
+ (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ '0';
+ WestFifoResetxAS : RXResetxR.FifoResetxR.WestxR <=
+ '1' when
+ (DebugRXFifoResetxR.WestxR = '1') or
+ (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ '0';
+ -- Back pressure
+ NorthBackPressureResetxAS : RXResetxR.BackPressureResetxR.NorthxR <=
+ '1' when
+ (DebugBackPressureResetxR.NorthxR = '1') or
+ (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ (RXFifoResetDonexD.NorthxS = '0') or
+ (RXFifoResetDoneDelayedxD.NorthxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ '0';
+ EastBackPressureResetxAS : RXResetxR.BackPressureResetxR.EastxR <=
+ '1' when
+ (DebugBackPressureResetxR.EastxR = '1') or
+ (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ (RXFifoResetDonexD.EastxS = '0') or
+ (RXFifoResetDoneDelayedxD.EastxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ '0';
+ SouthBackPressureResetxAS : RXResetxR.BackPressureResetxR.SouthxR <=
+ '1' when
+ (DebugBackPressureResetxR.SouthxR = '1') or
+ (RXFifoResetDonexD.SouthxS = '0') or
+ (RXFifoResetDoneDelayedxD.SouthxS = '0') or
+ (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ '0';
+ WestBackPressureResetxAS : RXResetxR.BackPressureResetxR.WestxR <=
+ '1' when
+ (DebugBackPressureResetxR.WestxR = '1') or
+ (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ (RXFifoResetDonexD.WestxS = '0') or
+ (RXFifoResetDoneDelayedxD.WestxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ '0';
+
+ NorthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ AuroraStatusxD.ChannelUpxD(0),
+ AuroraStatusxD.LaneUpxD(0)(0),
+ DebugCounterResetxR.NorthxR,
+ RXFifoResetDoneDelayedxD.NorthxS,
+ RXFifoResetDonexD.NorthxS) is
+ begin -- process NorthUpdateRegxP
+ if (DebugCounterResetxR.NorthxR = '1') or
+ (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(0) = '0') or
+ (RXFifoResetDonexD.NorthxS = '0') or
+ (RXFifoResetDoneDelayedxD.NorthxS = '0') then
+ NorthReadPhyStatexDP <= E_READ_PHY_IDLE;
+ NorthWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ NorthDataCounterxDP <= (others => '0');
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ NorthReadPhyStatexDP <= NorthReadPhyStatexDN;
+ NorthWritePhyStatexDP <= NorthWritePhyStatexDN;
+ NorthDataCounterxDP <= NorthDataCounterxDN;
+ end if;
+ end process NorthUpdateRegxP;
+
+ EastUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ AuroraStatusxD.ChannelUpxD(1),
+ AuroraStatusxD.LaneUpxD(1)(0),
+ DebugCounterResetxR.EastxR,
+ RXFifoResetDoneDelayedxD.EastxS,
+ RXFifoResetDonexD.EastxS) is
+ begin -- process EastUpdateRegxP
+ if (DebugCounterResetxR.EastxR = '1') or
+ (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(1) = '0') or
+ (RXFifoResetDonexD.EastxS = '0') or
+ (RXFifoResetDoneDelayedxD.EastxS = '0') then
+ EastReadPhyStatexDP <= E_READ_PHY_IDLE;
+ EastWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ EastDataCounterxDP <= (others => '0');
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ EastReadPhyStatexDP <= EastReadPhyStatexDN;
+ EastWritePhyStatexDP <= EastWritePhyStatexDN;
+ EastDataCounterxDP <= EastDataCounterxDN;
+ end if;
+ end process EastUpdateRegxP;
+
+ SouthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ AuroraStatusxD.ChannelUpxD(2),
+ AuroraStatusxD.LaneUpxD(2)(0),
+ DebugCounterResetxR.SouthxR,
+ RXFifoResetDoneDelayedxD.SouthxS,
+ RXFifoResetDonexD.SouthxS) is
+ begin -- process SouthUpdateRegxP
+ if (DebugCounterResetxR.SouthxR = '1') or
+ (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(2) = '0') or
+ (RXFifoResetDonexD.SouthxS = '0') or
+ (RXFifoResetDoneDelayedxD.SouthxS = '0') then
+ SouthReadPhyStatexDP <= E_READ_PHY_IDLE;
+ SouthWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ SouthDataCounterxDP <= (others => '0');
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ SouthReadPhyStatexDP <= SouthReadPhyStatexDN;
+ SouthWritePhyStatexDP <= SouthWritePhyStatexDN;
+ SouthDataCounterxDP <= SouthDataCounterxDN;
+ end if;
+ end process SouthUpdateRegxP;
+
+ WestUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ AuroraStatusxD.ChannelUpxD(3),
+ AuroraStatusxD.LaneUpxD(3)(0),
+ DebugCounterResetxR.WestxR,
+ RXFifoResetDoneDelayedxD.WestxS,
+ RXFifoResetDonexD.WestxS) is
+ begin -- process WestUpdateRegxP
+ if (DebugCounterResetxR.WestxR = '1') or
+ (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(3) = '0') or
+ (RXFifoResetDonexD.WestxS = '0') or
+ (RXFifoResetDoneDelayedxD.WestxS = '0') then
+ WestReadPhyStatexDP <= E_READ_PHY_IDLE;
+ WestWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ WestDataCounterxDP <= (others => '0');
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ WestReadPhyStatexDP <= WestReadPhyStatexDN;
+ WestWritePhyStatexDP <= WestWritePhyStatexDN;
+ WestDataCounterxDP <= WestDataCounterxDN;
+ end if;
+ end process WestUpdateRegxP;
VioUserResetsxI : entity work.vio_user_resets
port map (
- clk => AuroraClkMasterxC.UserClkxC,
- probe_out0(0) => DebugCounterResetxR,
- probe_out1(0) => DebugRXFifoResetxR,
- probe_out2(0) => DebugBackPressureResetxR,
- probe_out3 => open,
- probe_out4 => open);
-
- -- VioAxiCntCtrlxI : entity work.vio_axi_cnt_ctrl
- -- port map (
- -- clk => AuroraClkMasterxC.UserClkxC,
- -- -- North
- -- probe_in0 => NorthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- -- probe_in1(0) => NorthRXfromPhyTXfromFifoM2SxD.ValidxS,
- -- probe_in2(0) => '0', --NorthTXS2MxD.ReadyxS,
- -- -- East
- -- probe_in3 => EastRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- -- probe_in4(0) => EastRXfromPhyTXfromFifoM2SxD.ValidxS,
- -- probe_in5(0) => '0', --EastTXS2MxD.ReadyxS,
- -- -- South
- -- probe_in6 => SouthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- -- probe_in7(0) => SouthRXfromPhyTXfromFifoM2SxD.ValidxS,
- -- probe_in8(0) => '0', --SouthTXS2MxD.ReadyxS,
- -- -- West
- -- probe_in9 => WestRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- -- probe_in10(0) => WestRXfromPhyTXfromFifoM2SxD.ValidxS,
- -- probe_in11(0) => '0', --WestTXS2MxD.ReadyxS,
- -- probe_out0(0) => open); --CntRstxR);
+ clk => AuroraClkMasterxC.UserClkxC,
+ probe_out0(0) => DebugCounterResetxR.NorthxR,
+ probe_out1(0) => DebugCounterResetxR.EastxR,
+ probe_out2(0) => DebugCounterResetxR.SouthxR,
+ probe_out3(0) => DebugCounterResetxR.WestxR,
+ probe_out4(0) => DebugBackPressureResetxR.NorthxR,
+ probe_out5(0) => DebugBackPressureResetxR.EastxR,
+ probe_out6(0) => DebugBackPressureResetxR.SouthxR,
+ probe_out7(0) => DebugBackPressureResetxR.WestxR,
+ probe_out8(0) => DebugRXFifoResetxR.NorthxR,
+ probe_out9(0) => DebugRXFifoResetxR.EastxR,
+ probe_out10(0) => DebugRXFifoResetxR.SouthxR,
+ probe_out11(0) => DebugRXFifoResetxR.WestxR);
VioStatusxI : entity work.vio_status
port map (
@@ -1677,6 +1389,379 @@ begin
probe_in26(0) => AuroraStatusxD.RXResetDoneOutxD(3),
probe_in27(0) => AuroraStatusxD.TXResetDoneOutxD(3));
+ NorthWriteTXPhyxP : process (NorthDataCounterxDP,
+ NorthTXS2MxD.ReadyxS,
+ NorthWritePhyStatexDP) is
+ begin -- process NorthWriteTXPhyxP
+ -- Default values
+ NorthWritePhyStatexDN <= NorthWritePhyStatexDP;
+ NorthDataCounterxDN <= NorthDataCounterxDP;
+ NorthTXM2SxD.DataxD <= (others => '0');
+ NorthTXM2SxD.KeepxD <= (others => '1');
+ NorthTXM2SxD.ValidxS <= '0';
+ NorthTXM2SxD.LastxS <= '0';
+
+ case NorthWritePhyStatexDP is
+ when E_WRITE_PHY_IDLE =>
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ when E_WRITE_PHY_W0 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W1;
+ end if;
+
+ when E_WRITE_PHY_W1 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W2;
+ end if;
+
+ when E_WRITE_PHY_W2 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W3;
+ end if;
+
+ when E_WRITE_PHY_W3 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W4;
+ end if;
+
+ when E_WRITE_PHY_W4 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W5;
+ end if;
+
+ when E_WRITE_PHY_W5 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W6;
+ end if;
+ when E_WRITE_PHY_W6 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W7;
+ end if;
+
+ when E_WRITE_PHY_W7 =>
+ NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ NorthTXM2SxD.ValidxS <= '1';
+ NorthTXM2SxD.LastxS <= '1';
+
+ if NorthTXS2MxD.ReadyxS = '1' then
+ NorthWritePhyStatexDN <= E_WRITE_PHY_W0;
+ NorthDataCounterxDN <= NorthDataCounterxDP + 1;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process NorthWriteTXPhyxP;
+
+ EastWriteTXPhyxP : process (EastDataCounterxDP,
+ EastTXS2MxD.ReadyxS,
+ EastWritePhyStatexDP) is
+ begin -- process EastWriteTXPhyxP
+ -- Default values
+ EastWritePhyStatexDN <= EastWritePhyStatexDP;
+ EastDataCounterxDN <= EastDataCounterxDP;
+ EastTXM2SxD.DataxD <= (others => '0');
+ EastTXM2SxD.KeepxD <= (others => '1');
+ EastTXM2SxD.ValidxS <= '0';
+ EastTXM2SxD.LastxS <= '0';
+
+ case EastWritePhyStatexDP is
+ when E_WRITE_PHY_IDLE =>
+ EastWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ when E_WRITE_PHY_W0 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W1;
+ end if;
+
+ when E_WRITE_PHY_W1 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W2;
+ end if;
+
+ when E_WRITE_PHY_W2 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W3;
+ end if;
+
+ when E_WRITE_PHY_W3 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W4;
+ end if;
+
+ when E_WRITE_PHY_W4 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W5;
+ end if;
+
+ when E_WRITE_PHY_W5 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W6;
+ end if;
+
+ when E_WRITE_PHY_W6 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W7;
+ end if;
+
+ when E_WRITE_PHY_W7 =>
+ EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ EastTXM2SxD.ValidxS <= '1';
+ EastTXM2SxD.LastxS <= '1';
+
+ if EastTXS2MxD.ReadyxS = '1' then
+ EastWritePhyStatexDN <= E_WRITE_PHY_W0;
+ EastDataCounterxDN <= EastDataCounterxDP + 1;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process EastWriteTXPhyxP;
+
+ SouthWriteTXPhyxP : process (SouthDataCounterxDP,
+ SouthTXS2MxD.ReadyxS,
+ SouthWritePhyStatexDP) is
+ begin -- process SouthWriteTXPhyxP
+ -- Default values
+ SouthWritePhyStatexDN <= SouthWritePhyStatexDP;
+ SouthDataCounterxDN <= SouthDataCounterxDP;
+ SouthTXM2SxD.DataxD <= (others => '0');
+ SouthTXM2SxD.KeepxD <= (others => '1');
+ SouthTXM2SxD.ValidxS <= '0';
+ SouthTXM2SxD.LastxS <= '0';
+
+ case SouthWritePhyStatexDP is
+ when E_WRITE_PHY_IDLE =>
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ when E_WRITE_PHY_W0 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W1;
+ end if;
+
+ when E_WRITE_PHY_W1 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W2;
+ end if;
+
+ when E_WRITE_PHY_W2 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W3;
+ end if;
+
+ when E_WRITE_PHY_W3 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W4;
+ end if;
+
+ when E_WRITE_PHY_W4 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W5;
+ end if;
+
+ when E_WRITE_PHY_W5 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W6;
+ end if;
+
+ when E_WRITE_PHY_W6 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W7;
+ end if;
+
+ when E_WRITE_PHY_W7 =>
+ SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ SouthTXM2SxD.ValidxS <= '1';
+ SouthTXM2SxD.LastxS <= '1';
+
+ if SouthTXS2MxD.ReadyxS = '1' then
+ SouthWritePhyStatexDN <= E_WRITE_PHY_W0;
+ SouthDataCounterxDN <= SouthDataCounterxDP + 1;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process SouthWriteTXPhyxP;
+
+ WestWriteTXPhyxP : process (WestDataCounterxDP,
+ WestTXS2MxD.ReadyxS,
+ WestWritePhyStatexDP) is
+ begin -- process WestWriteTXPhyxP
+ -- Default values
+ WestWritePhyStatexDN <= WestWritePhyStatexDP;
+ WestDataCounterxDN <= WestDataCounterxDP;
+ WestTXM2SxD.DataxD <= (others => '0');
+ WestTXM2SxD.KeepxD <= (others => '1');
+ WestTXM2SxD.ValidxS <= '0';
+ WestTXM2SxD.LastxS <= '0';
+
+ case WestWritePhyStatexDP is
+ when E_WRITE_PHY_IDLE =>
+ WestWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ when E_WRITE_PHY_W0 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W1;
+ end if;
+
+ when E_WRITE_PHY_W1 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W2;
+ end if;
+
+ when E_WRITE_PHY_W2 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W3;
+ end if;
+
+ when E_WRITE_PHY_W3 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W4;
+ end if;
+
+ when E_WRITE_PHY_W4 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W5;
+ end if;
+
+ when E_WRITE_PHY_W5 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W6;
+ end if;
+
+ when E_WRITE_PHY_W6 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W7;
+ end if;
+
+ when E_WRITE_PHY_W7 =>
+ WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ WestTXM2SxD.ValidxS <= '1';
+ WestTXM2SxD.LastxS <= '1';
+
+ if WestTXS2MxD.ReadyxS = '1' then
+ WestWritePhyStatexDN <= E_WRITE_PHY_W0;
+ WestDataCounterxDN <= WestDataCounterxDP + 1;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process WestWriteTXPhyxP;
+
+ -- NorthReadRXPhyxP : process (NorthRXM2SxD.ValidxS, ReadPhyStatexDP) is
+ -- begin -- process NorthReadRXPhyxP
+ -- -- Default value
+ -- ReadPhyStatexDN <= ReadPhyStatexDP;
+ -- NorthRXS2MxD.ReadyxS <= '0';
+
+ -- case ReadPhyStatexDP is
+ -- when E_READ_PHY_IDLE =>
+ -- ReadPhyStatexDN <= E_READ_PHY_S0;
+ -- when E_READ_PHY_S0 =>
+ -- if NorthRXM2SxD.ValidxS = '1' then
+ -- ReadPhyStatexDN <= E_READ_PHY_S1;
+ -- end if;
+ -- when E_READ_PHY_S1 =>
+ -- if NorthRXM2SxD.ValidxS = '1' then
+ -- ReadPhyStatexDN <= E_READ_PHY_S2;
+ -- end if;
+ -- when E_READ_PHY_S2 =>
+ -- if NorthRXM2SxD.ValidxS = '1' then
+ -- NorthRXS2MxD.ReadyxS <= '1';
+ -- ReadPhyStatexDN <= E_READ_PHY_S0;
+ -- end if;
+ -- when others => null;
+ -- end case;
+ -- end process NorthReadRXPhyxP;
+
end block DebugxB;
end block ProgrammableLogicxB;
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
index 7a9f8ca18026cf73405faa252061f128a1cb16b6..30a18dd36a31b3a037c3ad05af5bbc4f35c57454 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: scalp_aurora_phy
--
--- Last update: 2020-10-13
+-- Last update: 2020-11-25
--
---------------------------------------------------------------------------------
@@ -37,576 +37,1298 @@ use work.aurora_drp_pkg.all;
entity scalp_aurora_phy is
generic (
- C_DEBUG_MODE : boolean := false);
+ C_DEBUG_MODE : boolean := false;
+ C_RX_FIFO_MODE : boolean := true;
+ C_RX_FIFO_RST_DONE_DLY_TICKS : integer := 100);
port (
+ -- Clocks
-- GTP Ref Clocks
- GTRefClkxCI : in t_gt_ref_slave_clk;
+ GTRefClkxCI : in t_gt_ref_slave_clk;
-- Aurora System and GTP Clocks
- AuroraClkxCI : in t_aurora_slave_clk;
- AuroraClkxCO : out t_aurora_master_clk;
+ AuroraClkxCI : in t_aurora_slave_clk;
+ AuroraClkxCO : out t_aurora_master_clk;
+ -- Reset
-- Aurora Reset
- AuroraResetxRI : in t_aurora_slave_reset;
- AuroraResetxRO : out t_aurora_master_link_reset;
+ AuroraResetxRI : in t_aurora_slave_reset;
+ AuroraResetxRO : out t_aurora_master_link_reset;
+ -- RX Fifo and Back Pressure Reset
+ RXResetxRI : in t_rx_reset;
+ RXFifoResetDonexDO : out t_rx_fifo_reset_done;
+ RXFifoResetDoneDelayedxDO : out t_rx_fifo_reset_done;
+ -- Back Pressure Reset
-- GTP Serial IO
-- North
- GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
- GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
-- East
- GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
- GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
-- South
- GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
- GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
-- West
- GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
- GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
-- Axi4 Framing Interface
-- North
- NorthRXM2SxDO : out t_axi4m2s;
- NorthTXM2SxDI : in t_axi4m2s;
- NorthTXS2MxDO : out t_axi4s2m;
+ NorthRXM2SxDO : out t_axi4m2s;
+ NorthRXS2MxDI : in t_axi4s2m;
+ NorthTXM2SxDI : in t_axi4m2s;
+ NorthTXS2MxDO : out t_axi4s2m;
-- East
- EastRXM2SxDO : out t_axi4m2s;
- EastTXM2SxDI : in t_axi4m2s;
- EastTXS2MxDO : out t_axi4s2m;
+ EastRXM2SxDO : out t_axi4m2s;
+ EastRXS2MxDI : in t_axi4s2m;
+ EastTXM2SxDI : in t_axi4m2s;
+ EastTXS2MxDO : out t_axi4s2m;
-- South
- SouthRXM2SxDO : out t_axi4m2s;
- SouthTXM2SxDI : in t_axi4m2s;
- SouthTXS2MxDO : out t_axi4s2m;
+ SouthRXM2SxDO : out t_axi4m2s;
+ SouthRXS2MxDI : in t_axi4s2m;
+ SouthTXM2SxDI : in t_axi4m2s;
+ SouthTXS2MxDO : out t_axi4s2m;
-- West
- WestRXM2SxDO : out t_axi4m2s;
- WestTXM2SxDI : in t_axi4m2s;
- WestTXS2MxDO : out t_axi4s2m;
+ WestRXM2SxDO : out t_axi4m2s;
+ WestRXS2MxDI : in t_axi4s2m;
+ WestTXM2SxDI : in t_axi4m2s;
+ WestTXS2MxDO : out t_axi4s2m;
-- Axi4 Framing UFC Interface
-- North
- NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
-- East
- EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
-- South
- SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
-- West
- WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ -- Axi4 Framing NFC Interface
+ -- North
+ NorthRXNFCM2SxDO : out t_axi4nfcm2s;
+ NorthTXNFCM2SxDI : in t_axi4nfcm2s;
+ NorthTXNFCS2MxDO : out t_axi4nfcs2m;
+ -- East
+ EastRXNFCM2SxDO : out t_axi4nfcm2s;
+ EastTXNFCM2SxDI : in t_axi4nfcm2s;
+ EastTXNFCS2MxDO : out t_axi4nfcs2m;
+ -- South
+ SouthRXNFCM2SxDO : out t_axi4nfcm2s;
+ SouthTXNFCM2SxDI : in t_axi4nfcm2s;
+ SouthTXNFCS2mxDO : out t_axi4nfcs2m;
+ -- West
+ WestRXNFCM2SxDO : out t_axi4nfcm2s;
+ WestTXNFCM2SxDI : in t_axi4nfcm2s;
+ WestTXNFCS2MxDO : out t_axi4nfcs2m;
-- Aurora Ctrl + Status
- AuroraCtrlxDI : in t_aurora_control;
- AuroraStatusxDO : out t_aurora_status;
+ AuroraCtrlxDI : in t_aurora_control;
+ AuroraStatusxDO : out t_aurora_status;
-- DRP Port
- AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
- AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0));
+ AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
+ AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0);
+ -- RX Fifo Status
+ -- North
+ NorthRXFifoStatusxDO : out t_axi4fifo_status;
+ -- East
+ EastRXFifoStatusxDO : out t_axi4fifo_status;
+ -- South
+ SouthRXFifoStatusxDO : out t_axi4fifo_status;
+ -- West
+ WestRXFifoStatusxDO : out t_axi4fifo_status;
+ -- Axis Fifo Error
+ AxisFifoErrorxDO : out t_axi4fifo_error);
end scalp_aurora_phy;
architecture arch of scalp_aurora_phy is
- constant C_SIM_GTRESET_SPEEDUP : string := "false";
- constant C_NUM_PLL : integer := 1;
-
- component reset_logic is
- port (
- UserClkxCI : in std_logic;
- InitClkxCI : in std_logic;
- ResetxRI : in std_logic;
- GTResetxRI : in std_logic;
- SystemResetxRO : out std_logic;
- GTResetxRO : out std_logic);
- end component reset_logic;
-
- component clock_module is
- generic (
- C_NUM_PLL : integer);
- port (
- InitClkxCI : in std_logic;
- InitClkxCO : out std_logic;
- GTClkxCI : in std_logic_vector((C_NUM_PLL - 1) downto 0);
- GTClkLockedxDI : in std_logic_vector((C_NUM_PLL - 1) downto 0);
- UserClkxCO : out std_logic_vector((C_NUM_PLL - 1) downto 0);
- SyncClkxCO : out std_logic_vector((C_NUM_PLL - 1) downto 0);
- PLLNotLockedxDO : out std_logic_vector((C_NUM_PLL - 1) downto 0));
- end component clock_module;
-
- component gt_common is
- generic (
- C_SIM_GTRESET_SPEEDUP : string);
- port (
- GT0GTRefClk0xCI : in std_logic;
- GT0PLL0LockxSO : out std_logic;
- GT0PLL1LockxSO : out std_logic;
- GT0PLL0LockDetClkxCI : in std_logic;
- GT0PLL0RefClkLostxSO : out std_logic;
- GT0PLL0ClkxCO : out std_logic;
- GT0PLL1ClkxCO : out std_logic;
- GT0PLL0RefClkxCO : out std_logic;
- GT0PLL1RefClkxCO : out std_logic;
- GT0PLL0ResetxRI : in std_logic);
- end component gt_common;
-
- -- From Aurora Clock Module
- signal AuroraSlaveClkxC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
- signal AuroraMasterClkxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
- -- From GT Common Module
- signal GTCommonSlaveClkxC : t_gt_common_slave_clk := C_GT_COMMON_NO_SLAVE_CLK;
- signal GTCommonMasterClkxC : t_gt_common_master_clk := C_GT_COMMON_NO_MASTER_CLK;
- -- From Aurora Reset Logic
- signal AuroraSlaveResetxR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
- signal AuroraMasterResetxR : t_aurora_master_reset := C_AURORA_NO_MASTER_RESET;
- -- From Aurora Core
- signal AuroraMasterLinkResetxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
- signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
- signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
- signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
- signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal GTRefClkxC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal AuroraClkInxC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
+ signal AuroraClkOutxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
+ signal AuroraResetInxR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
+ signal AuroraResetOutxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
+ signal RXResetxR : t_rx_reset := C_NO_RX_RESET;
+ signal RXFifoRstxRAN : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
+ signal RXFifoResetDonexD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal RXFifoResetDoneDelayedxD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCS2mxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
+ signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
+ signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
+ signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal NorthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal EastRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal SouthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal WestRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal NorthFifoRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthFifoTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastFifoRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastFifoTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthFifoRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthFifoTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestFifoRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestFifoTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ attribute mark_debug of RXFifoResetDonexD : signal is "true";
+ attribute keep of RXFifoResetDonexD : signal is "true";
+ attribute mark_debug of RXFifoResetDoneDelayedxD : signal is "true";
+ attribute keep of RXFifoResetDoneDelayedxD : signal is "true";
+ -- North
+ attribute mark_debug of NorthTXM2SxD : signal is "true";
+ attribute keep of NorthTXM2SxD : signal is "true";
+ attribute mark_debug of NorthTXS2MxD : signal is "true";
+ attribute keep of NorthTXS2MxD : signal is "true";
+ attribute mark_debug of NorthRXM2SxD : signal is "true";
+ attribute keep of NorthRXM2SxD : signal is "true";
+ attribute mark_debug of NorthTXNFCM2SxD : signal is "true";
+ attribute keep of NorthTXNFCM2SxD : signal is "true";
+ attribute mark_debug of NorthTXNFCS2MxD : signal is "true";
+ attribute keep of NorthTXNFCS2MxD : signal is "true";
+ attribute mark_debug of NorthRXNFCM2SxD : signal is "true";
+ attribute keep of NorthRXNFCM2SxD : signal is "true";
+ -- East
+ -- attribute mark_debug of EastTXM2SxD : signal is "true";
+ -- attribute keep of EastTXM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXS2MxD : signal is "true";
+ -- attribute keep of EastTXS2MxD : signal is "true";
+ -- attribute mark_debug of EastRXM2SxD : signal is "true";
+ -- attribute keep of EastRXM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXNFCM2SxD : signal is "true";
+ -- attribute keep of EastTXNFCM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXNFCS2MxD : signal is "true";
+ -- attribute keep of EastTXNFCS2MxD : signal is "true";
+ -- attribute mark_debug of EastRXNFCM2SxD : signal is "true";
+ -- attribute keep of EastRXNFCM2SxD : signal is "true";
+ -- South
+ attribute mark_debug of SouthTXM2SxD : signal is "true";
+ attribute keep of SouthTXM2SxD : signal is "true";
+ attribute mark_debug of SouthTXS2MxD : signal is "true";
+ attribute keep of SouthTXS2MxD : signal is "true";
+ attribute mark_debug of SouthRXM2SxD : signal is "true";
+ attribute keep of SouthRXM2SxD : signal is "true";
+ attribute mark_debug of SouthTXNFCM2SxD : signal is "true";
+ attribute keep of SouthTXNFCM2SxD : signal is "true";
+ attribute mark_debug of SouthTXNFCS2MxD : signal is "true";
+ attribute keep of SouthTXNFCS2MxD : signal is "true";
+ attribute mark_debug of SouthRXNFCM2SxD : signal is "true";
+ attribute keep of SouthRXNFCM2SxD : signal is "true";
+ -- West
+ -- attribute mark_debug of WestTXM2SxD : signal is "true";
+ -- attribute keep of WestTXM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXS2MxD : signal is "true";
+ -- attribute keep of WestTXS2MxD : signal is "true";
+ -- attribute mark_debug of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXNFCM2SxD : signal is "true";
+ -- attribute keep of WestTXNFCM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXNFCS2MxD : signal is "true";
+ -- attribute keep of WestTXNFCS2MxD : signal is "true";
+ -- attribute mark_debug of WestRXNFCM2SxD : signal is "true";
+ -- attribute keep of WestRXNFCM2SxD : signal is "true";
begin
- ClocksIOxB : block is
- begin -- block ClocksIOxB
-
- AuroraClkSlaveInitClkxAS : AuroraSlaveClkxC.InitClkxC <= AuroraClkxCI.InitClkxC;
- AuroraClkSlavexDrpClkxAS : AuroraSlaveClkxC.DrpClkxC <= AuroraClkxCI.DrpClkxC;
- AuroraClkMasterInitClkxAS : AuroraClkxCO.InitClkxC <= AuroraMasterClkxC.InitClkxC;
- AuroraClkMasterUserClkxAS : AuroraClkxCO.UserClkxC <= AuroraMasterClkxC.UserClkxC;
- AuroraClkMasterPllNotLockedxAS : AuroraClkxCO.PLLNotLockedxS <= AuroraMasterClkxC.PllNotLockedxS;
-
- end block ClocksIOxB;
-
- ResetIOxB : block is
- begin -- block ResetIOxB
-
- GT0GTRefClk0xAS : GTCommonSlaveClkxC.GTRefClkxC <= GTRefClkxCI.GTRefClkxC;
- GT0PLL0LockDetClkxAS : GTCommonSlaveClkxC.GTPLL0LockDetClkxC <= AuroraMasterClkxC.InitClkxC;
- AuroraSlaveResetResetxAS : AuroraSlaveResetxR.ResetxR <= AuroraResetxRI.ResetxR;
- AuroraSlaveResetGTResetxAS : AuroraSlaveResetxR.GTResetxR <= AuroraResetxRI.GTResetxR;
- AuroraMasterLinkResetSystemResetxAS : AuroraResetxRO.SystemResetxR <= AuroraMasterLinkResetxR.SystemResetxR;
- AuroraMasterLinkResetLinkResetxAS : AuroraResetxRO.LinkResetxR <= AuroraMasterLinkResetxR.LinkResetxR;
-
- end block ResetIOxB;
-
- SignalsIOxB : block is
- begin -- block SignalsIOxB
-
- -- Axi4 Framing
- NorthRXM2SxAS : NorthRXM2SxDO <= NorthRXM2SxD;
- NorthTXM2SxAS : NorthTXM2SxD <= NorthTXM2SxDI;
- NorthTXS2MxAS : NorthTXS2MxDO <= NorthTXS2MxD;
- EastRXM2SxAS : EastRXM2SxDO <= EastRXM2SxD;
- EastTXM2SxAS : EastTXM2SxD <= EastTXM2SxDI;
- EastTXS2MxAS : EastTXS2MxDO <= EastTXS2MxD;
- SouthRXM2SxAS : SouthRXM2SxDO <= SouthRXM2SxD;
- SouthTXM2SxAS : SouthTXM2SxD <= SouthTXM2SxDI;
- SouthTXS2MxAS : SouthTXS2MxDO <= SouthTXS2MxD;
- WestRXM2SxAS : WestRXM2SxDO <= WestRXM2SxD;
- WestTXM2SxAS : WestTXM2SxD <= WestTXM2SxDI;
- WestTXS2MxAS : WestTXS2MxDO <= WestTXS2MxD;
- -- Axi4 Framing UFC
- NorthRXUFCM2SxAS : NorthRXUFCM2SxDO <= NorthRXUFCM2SxD;
- NorthTXUFCM2SxAS : NorthTXUFCM2SxD <= NorthTXUFCM2SxDI;
- NorthTXUFCS2MxAS : NorthTXUFCS2MxDO <= NorthTXUFCS2MxD;
- EastRXUFCM2SxAS : EastRXUFCM2SxDO <= EastRXUFCM2SxD;
- EastTXUFCM2SxAS : EastTXUFCM2SxD <= EastTXUFCM2SxDI;
- EastTXUFCS2MxAS : EastTXUFCS2MxDO <= EastTXUFCS2MxD;
- SouthRXUFCM2SxAS : SouthRXUFCM2SxDO <= SouthRXUFCM2SxD;
- SouthTXUFCM2SxAS : SouthTXUFCM2SxD <= SouthTXUFCM2SxDI;
- SouthTXUFCS2MxAS : SouthTXUFCS2MxDO <= SouthTXUFCS2MxD;
- WestRXUFCM2SxAS : WestRXUFCM2SxDO <= WestRXUFCM2SxD;
- WestTXUFCM2SxAS : WestTXUFCM2SxD <= WestTXUFCM2SxDI;
- WestTXUFCS2MxAS : WestTXUFCS2MxDO <= WestTXUFCS2MxD;
- -- GTP Serial IO
- GTPFromNorthxAS : GTPFromNorthxD <= GTPFromNorthxDI;
- GTPToNorthxAS : GTPToNorthxDO <= GTPToNorthxD;
- GTPFromEastxAS : GTPFromEastxD <= GTPFromEastxDI;
- GTPToEastxAS : GTPToEastxDO <= GTPToEastxD;
- GTPFromSouthxAS : GTPFromSouthxD <= GTPFromSouthxDI;
- GTPToSouthxAS : GTPToSouthxDO <= GTPToSouthxD;
- GTPFromWestxAS : GTPFromWestxD <= GTPFromWestxDI;
- GTPToWestxAS : GTPToWestxDO <= GTPToWestxD;
- -- Aurora Ctrl + Status
- AuroraCtrlxAS : AuroraCtrlxD <= AuroraCtrlxDI;
- AuroraStatusxAS : AuroraStatusxDO <= AuroraStatusxD;
- -- Aurora DRP Port
- AuroraDRPM2SxAS : AuroraDRPM2SxD <= AuroraDRPM2SxDI;
- AuroraDRPS2MxAS : AuroraDRPS2MxDO <= AuroraDRPS2MxD;
+ EntityIOxB : block is
+ begin -- block EntityIOxB
- end block SignalsIOxB;
+ ClockxB : block is
+ begin -- block ClockxB
- ClkRstxB : block is
- begin -- block ClkRstxB
+ GTRefClkxAS : GTRefClkxC <= GTRefClkxCI;
+ AuroraClkInxAS : AuroraClkInxC <= AuroraClkxCI;
+ AuroraClkOutxAS : AuroraClkxCO <= AuroraClkOutxC;
- AuroraResetLogicxI : entity work.reset_logic
- port map (
- UserClkxCI => AuroraMasterClkxC.UserClkxC,
- InitClkxCI => AuroraMasterClkxC.InitClkxC,
- ResetxRI => AuroraSlaveResetxR.ResetxR, -- Sync on UserClk
- GTResetxRI => AuroraSlaveResetxR.GTResetxR, -- Sync on InitClk
- SystemResetxRO => AuroraMasterResetxR.SystemResetxR,
- GTResetxRO => AuroraMasterResetxR.GTResetxR);
-
- AuroraClockModulexI : entity work.clock_module
- generic map (
- C_NUM_PLL => C_NUM_PLL)
- port map (
- -- Slave
- InitClkxCI => AuroraSlaveClkxC.InitClkxC,
- GTClkxCI(0) => AuroraSlaveClkxC.GTClkxC,
- GTClkLockedxDI(0) => AuroraSlaveClkxC.GTClkLockedxS,
- -- Master
- InitClkxCO => AuroraMasterClkxC.InitClkxC,
- UserClkxCO(0) => AuroraMasterClkxC.UserClkxC,
- SyncClkxCO(0) => AuroraMasterClkxC.SyncClkxC,
- PLLNotLockedxDO(0) => AuroraMasterClkxC.PllNotLockedxS);
-
- GTCommonxI : entity work.gt_common
+ end block ClockxB;
+
+ ResetxB : block is
+ begin -- block ResetxB
+
+ AuroraResetInxAS : AuroraResetInxR <= AuroraResetxRI;
+ AuroraResetOutxAS : AuroraResetxRO <= AuroraResetOutxR;
+ RXResetxAS : RXResetxR <= RXResetxRI;
+ RXFifoResetDonexAS : RXFifoResetDonexDO <= RXFifoResetDonexD;
+ RXFifoResetDoneDelayedxAS : RXFifoResetDoneDelayedxDO <= RXFifoResetDoneDelayedxD;
+
+ end block ResetxB;
+
+ GTPxB : block is
+ begin -- block GTPxB
+
+ -- North
+ GTPFromNorthxAS : GTPFromNorthxD <= GTPFromNorthxDI;
+ GTPToNorthxAS : GTPToNorthxDO <= GTPToNorthxD;
+ -- East
+ GTPFromEastxAS : GTPFromEastxD <= GTPFromEastxDI;
+ GTPToEastxAS : GTPToEastxDO <= GTPToEastxD;
+ -- South
+ GTPFromSouthxAS : GTPFromSouthxD <= GTPFromSouthxDI;
+ GTPToSouthxAS : GTPToSouthxDO <= GTPToSouthxD;
+ -- West
+ GTPFromWestxAS : GTPFromWestxD <= GTPFromWestxDI;
+ GTPToWestxAS : GTPToWestxDO <= GTPToWestxD;
+
+ end block GTPxB;
+
+ TXxB : block is
+ begin -- block TXxB
+
+ AXIxB : block is
+ begin -- block AXIxB
+
+ -- North
+ NorthTXM2SxAS : NorthTXM2SxD <= NorthTXM2SxDI;
+ NorthTXS2MxAS : NorthTXS2MxDO <= NorthTXS2MxD;
+ -- East
+ EastTXM2SxAS : EastTXM2SxD <= EastTXM2SxDI;
+ EastTXS2MxAS : EastTXS2MxDO <= EastTXS2MxD;
+ -- South
+ SouthTXM2SxAS : SouthTXM2SxD <= SouthTXM2SxDI;
+ SouthTXS2MxAS : SouthTXS2MxDO <= SouthTXS2MxD;
+ -- West
+ WestTXM2SxAS : WestTXM2SxD <= WestTXM2SxDI;
+ WestTXS2MxAS : WestTXS2MxDO <= WestTXS2MxD;
+
+ end block AXIxB;
+
+ UFCxB : block is
+ begin -- block UFCxB
+
+ -- North
+ NorthTXUFCM2SxAS : NorthTXUFCM2SxD <= NorthTXUFCM2SxDI;
+ NorthTXUFCS2MxAS : NorthTXUFCS2MxDO <= NorthTXUFCS2MxD;
+ -- East
+ EastTXUFCM2SxAS : EastTXUFCM2SxD <= EastTXUFCM2SxDI;
+ EastTXUFCS2MxAS : EastTXUFCS2MxDO <= EastTXUFCS2MxD;
+ -- South
+ SouthTXUFCM2SxAS : SouthTXUFCM2SxD <= SouthTXUFCM2SxDI;
+ SouthTXUFCS2MxAS : SouthTXUFCS2MxDO <= SouthTXUFCS2MxD;
+ -- West
+ WestTXUFCM2SxAS : WestTXUFCM2SxD <= WestTXUFCM2SxDI;
+ WestTXUFCS2MxAS : WestTXUFCS2MxDO <= WestTXUFCS2MxD;
+
+ end block UFCxB;
+
+ end block TXxB;
+
+ RXxB : block is
+ begin -- block RXxB
+
+ UFCxB : block is
+ begin -- block UFCxB
+
+ -- North
+ NorthRXUFCM2SxAS : NorthRXUFCM2SxDO <= NorthRXUFCM2SxD;
+ -- East
+ EastRXUFCM2SxAS : EastRXUFCM2SxDO <= EastRXUFCM2SxD;
+ -- East
+ SouthRXUFCM2SxAS : SouthRXUFCM2SxDO <= SouthRXUFCM2SxD;
+ -- West
+ WestRXUFCM2SxAS : WestRXUFCM2SxDO <= WestRXUFCM2SxD;
+
+ end block UFCxB;
+
+ end block RXxB;
+
+ CtrlStatusxB : block is
+ begin -- block CtrlStatusxB
+
+ AuroraCtrlxAS : AuroraCtrlxD <= AuroraCtrlxDI;
+ AuroraStatusxAS : AuroraStatusxDO <= AuroraStatusxD;
+
+ end block CtrlStatusxB;
+
+ DRPxB : block is
+ begin -- block DRPxB
+
+ AuroraDRPM2SxAS : AuroraDRPM2SxD <= AuroraDRPM2SxDI;
+ AuroraDRPS2MxAS : AuroraDRPS2MxDO <= AuroraDRPS2MxD;
+
+ end block DRPxB;
+
+ end block EntityIOxB;
+
+ ScalpAuroraPhyxB : block is
+ begin -- block ScalpAuroraPhyxB
+
+ ScalpAuroraPhyWrapperxI : entity work.scalp_aurora_phy_wrapper
generic map (
- C_SIM_GTRESET_SPEEDUP => C_SIM_GTRESET_SPEEDUP)
+ C_DEBUG_MODE => C_DEBUG_MODE)
port map (
- -- Slave
- GT0GTRefClk0xCI => GTCommonSlaveClkxC.GTRefClkxC,
- GT0PLL0LockDetClkxCI => GTCommonSlaveClkxC.GTPLL0LockDetClkxC,
- GT0PLL0ResetxRI => GTCommonSlaveClkxC.CommonResetxR,
- -- Master
- GT0PLL0ClkxCO => GTCommonMasterClkxC.GTPLL0ClkxCO,
- GT0PLL1ClkxCO => GTCommonMasterClkxC.GTPLL1ClkxCO,
- GT0PLL0RefClkxCO => GTCommonMasterClkxC.GTPLL0RefClkxC,
- GT0PLL1RefClkxCO => GTCommonMasterClkxC.GTPLL1RefClkxC,
- GT0PLL0LockxSO => GTCommonMasterClkxC.GTPLL0LockxS,
- GT0PLL1LockxSO => GTCommonMasterClkxC.GTPLL1LockxS,
- GT0PLL0RefClkLostxSO => GTCommonMasterClkxC.GTPLL0RefClkLostxS);
+ GTRefClkxCI => GTRefClkxC,
+ AuroraClkxCI => AuroraClkInxC,
+ AuroraClkxCO => AuroraClkOutxC,
+ AuroraResetxRI => AuroraResetInxR,
+ AuroraResetxRO => AuroraResetOutxR,
+ GTPFromNorthxDI => GTPFromNorthxD,
+ GTPToNorthxDO => GTPToNorthxD,
+ GTPFromEastxDI => GTPFromEastxD,
+ GTPToEastxDO => GTPToEastxD,
+ GTPFromSouthxDI => GTPFromSouthxD,
+ GTPToSouthxDO => GTPToSouthxD,
+ GTPFromWestxDI => GTPFromWestxD,
+ GTPToWestxDO => GTPToWestxD,
+ NorthRXM2SxDO => NorthRXM2SxD,
+ NorthTXM2SxDI => NorthTXM2SxD,
+ NorthTXS2MxDO => NorthTXS2MxD,
+ EastRXM2SxDO => EastRXM2SxD,
+ EastTXM2SxDI => EastTXM2SxD,
+ EastTXS2MxDO => EastTXS2MxD,
+ SouthRXM2SxDO => SouthRXM2SxD,
+ SouthTXM2SxDI => SouthTXM2SxD,
+ SouthTXS2MxDO => SouthTXS2MxD,
+ WestRXM2SxDO => WestRXM2SxD,
+ WestTXM2SxDI => WestTXM2SxD,
+ WestTXS2MxDO => WestTXS2MxD,
+ NorthRXUFCM2SxDO => NorthRXUFCM2SxD,
+ NorthTXUFCM2SxDI => NorthTXUFCM2SxD,
+ NorthTXUFCS2MxDO => NorthTXUFCS2MxD,
+ EastRXUFCM2SxDO => EastRXUFCM2SxD,
+ EastTXUFCM2SxDI => EastTXUFCM2SxD,
+ EastTXUFCS2MxDO => EastTXUFCS2MxD,
+ SouthRXUFCM2SxDO => SouthRXUFCM2SxD,
+ SouthTXUFCM2SxDI => SouthTXUFCM2SxD,
+ SouthTXUFCS2MxDO => SouthTXUFCS2MxD,
+ WestRXUFCM2SxDO => WestRXUFCM2SxD,
+ WestTXUFCM2SxDI => WestTXUFCM2SxD,
+ WestTXUFCS2MxDO => WestTXUFCS2MxD,
+ NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
+ NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
+ NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
+ EastRXNFCM2SxDO => EastRXNFCM2SxD,
+ EastTXNFCM2SxDI => EastTXNFCM2SxD,
+ EastTXNFCS2MxDO => EastTXNFCS2MxD,
+ SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
+ SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
+ SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
+ WestRXNFCM2SxDO => WestRXNFCM2SxD,
+ WestTXNFCM2SxDI => WestTXNFCM2SxD,
+ WestTXNFCS2MxDO => WestTXNFCS2MxD,
+ AuroraCtrlxDI => AuroraCtrlxD,
+ AuroraStatusxDO => AuroraStatusxD,
+ AuroraDRPM2SxDI => AuroraDRPM2SxD,
+ AuroraDRPS2MxDO => AuroraDRPS2MxD);
- end block ClkRstxB;
+ end block ScalpAuroraPhyxB;
- -- Aurora GT Phy
+ RXModexB : block is
+ begin -- block RXModexB
- AuroraGTPhyxB : block is
- begin -- block AuroraGTPhyxB
+ RXFifoModexG : if C_RX_FIFO_MODE = false generate
- -- North Channel
+ EntityIOxB : block is
+ begin -- block EntityIOxB
- NorthChannelxI : entity work.north_channel
- port map (
- -- Clocks and Locked
- -- Slave
- gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
- quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
- tx_out_clk => AuroraSlaveClkxC.GTClkxC, -- Only North
- tx_lock => AuroraSlaveClkxC.GTClkLockedxS, -- Only North
- drpclk_in => AuroraSlaveClkxC.DrpClkxC,
- init_clk_in => AuroraMasterClkxC.InitClkxC,
- -- Master
- user_clk => AuroraMasterClkxC.UserClkxC,
- sync_clk => AuroraMasterClkxC.SyncClkxC,
- pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
- -- GT0
- gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
- gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
- gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
- gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
- gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
- gt_common_reset_out => GTCommonSlaveClkxC.CommonResetxR, -- Only North
- -- Reset
- reset => AuroraMasterResetxR.SystemResetxR,
- gt_reset => AuroraMasterResetxR.GTResetxR,
- link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(0),
- sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(0),
- -- TX
- s_axi_tx_tdata => NorthTXM2SxD.DataxD,
- s_axi_tx_tkeep => NorthTXM2SxD.KeepxD,
- s_axi_tx_tlast => NorthTXM2SxD.LastxS,
- s_axi_tx_tvalid => NorthTXM2SxD.ValidxS,
- s_axi_tx_tready => NorthTXS2MxD.ReadyxS,
- -- RX
- m_axi_rx_tdata => NorthRXM2SxD.DataxD,
- m_axi_rx_tkeep => NorthRXM2SxD.KeepxD,
- m_axi_rx_tlast => NorthRXM2SxD.LastxS,
- m_axi_rx_tvalid => NorthRXM2SxD.ValidxS,
- -- TX UFC
- s_axi_ufc_tx_tvalid => NorthTXUFCM2SxD.ValidxS,
- s_axi_ufc_tx_tdata => NorthTXUFCM2SxD.DataxD, -- 3 bits
- s_axi_ufc_tx_tready => NorthTXUFCS2MxD.ReadyxS,
- -- RX UFC
- m_axi_ufc_rx_tdata => NorthRXUFCM2SxD.DataxD, -- 32 bits
- m_axi_ufc_rx_tkeep => NorthRXUFCM2SxD.KeepxD,
- m_axi_ufc_rx_tlast => NorthRXUFCM2SxD.LastxS,
- m_axi_ufc_rx_tvalid => NorthRXUFCM2SxD.ValidxS,
- -- GTP
- txp => GTPToNorthxD.TXPxD,
- txn => GTPToNorthxD.TXNxD,
- rxp => GTPFromNorthxD.RXPxD,
- rxn => GTPFromNorthxD.RXNxD,
- -- Status
- hard_err => AuroraStatusxD.HardErrxD(0),
- soft_err => AuroraStatusxD.SoftErrxD(0),
- frame_err => AuroraStatusxD.FrameErrxD(0),
- channel_up => AuroraStatusxD.ChannelUpxD(0),
- lane_up => AuroraStatusxD.LaneUpxD(0),
- tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(0),
- rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(0),
- -- Ctrl
- loopback => AuroraCtrlxD.LoopbackxD,
- power_down => AuroraCtrlxD.PowerDownxS,
- -- DRP
- drpen_in => AuroraDRPM2SxD(0).DrpEnxS,
- drpwe_in => AuroraDRPM2SxD(0).DrpWExS,
- drpaddr_in => AuroraDRPM2SxD(0).DrpAddrxD,
- drpdi_in => AuroraDRPM2SxD(0).DrpDIxD,
- drprdy_out => AuroraDRPS2MxD(0).DrpRdyxS,
- drpdo_out => AuroraDRPS2MxD(0).DrpDOxD);
-
- -- East Channel
-
- EastChannelxI : entity work.east_channel
- port map (
- -- Clocks and Locked
- -- Slave
- gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
- quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
- tx_out_clk => open,
- tx_lock => open,
- drpclk_in => AuroraSlaveClkxC.DrpClkxC,
- init_clk_in => AuroraMasterClkxC.InitClkxC,
- -- Master
- user_clk => AuroraMasterClkxC.UserClkxC,
- sync_clk => AuroraMasterClkxC.SyncClkxC,
- pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
- -- GT0
- gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
- gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
- gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
- gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
- gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
- gt_common_reset_out => open,
- -- Reset
- reset => AuroraMasterResetxR.SystemResetxR,
- gt_reset => AuroraMasterResetxR.GTResetxR,
- link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(1),
- sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(1),
- -- TX
- s_axi_tx_tdata => EastTXM2SxD.DataxD,
- s_axi_tx_tkeep => EastTXM2SxD.KeepxD,
- s_axi_tx_tlast => EastTXM2SxD.LastxS,
- s_axi_tx_tvalid => EastTXM2SxD.ValidxS,
- s_axi_tx_tready => EastTXS2MxD.ReadyxS,
- -- RX
- m_axi_rx_tdata => EastRXM2SxD.DataxD,
- m_axi_rx_tkeep => EastRXM2SxD.KeepxD,
- m_axi_rx_tlast => EastRXM2SxD.LastxS,
- m_axi_rx_tvalid => EastRXM2SxD.ValidxS,
- -- TX UFC
- s_axi_ufc_tx_tvalid => EastTXUFCM2SxD.ValidxS,
- s_axi_ufc_tx_tdata => EastTXUFCM2SxD.DataxD, -- 3 bits
- s_axi_ufc_tx_tready => EastTXUFCS2MxD.ReadyxS,
- -- RX UFC
- m_axi_ufc_rx_tdata => EastRXUFCM2SxD.DataxD, -- 32 bits
- m_axi_ufc_rx_tkeep => EastRXUFCM2SxD.KeepxD,
- m_axi_ufc_rx_tlast => EastRXUFCM2SxD.LastxS,
- m_axi_ufc_rx_tvalid => EastRXUFCM2SxD.ValidxS,
- -- GTP
- txp => GTPToEastxD.TXPxD,
- txn => GTPToEastxD.TXNxD,
- rxp => GTPFromEastxD.RXPxD,
- rxn => GTPFromEastxD.RXNxD,
- -- Status
- hard_err => AuroraStatusxD.HardErrxD(1),
- soft_err => AuroraStatusxD.SoftErrxD(1),
- frame_err => AuroraStatusxD.FrameErrxD(1),
- channel_up => AuroraStatusxD.ChannelUpxD(1),
- lane_up => AuroraStatusxD.LaneUpxD(1),
- tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(1),
- rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(1),
- -- Ctrl
- loopback => AuroraCtrlxD.LoopbackxD,
- power_down => AuroraCtrlxD.PowerDownxS,
- -- DRP
- drpen_in => AuroraDRPM2SxD(1).DrpEnxS,
- drpwe_in => AuroraDRPM2SxD(1).DrpWExS,
- drpaddr_in => AuroraDRPM2SxD(1).DrpAddrxD,
- drpdi_in => AuroraDRPM2SxD(1).DrpDIxD,
- drprdy_out => AuroraDRPS2MxD(1).DrpRdyxS,
- drpdo_out => AuroraDRPS2MxD(1).DrpDOxD);
-
- -- South Channel
-
- SouthChannelxI : entity work.south_channel
- port map (
- -- Clocks and Locked
- -- Slave
- gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
- quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
- tx_out_clk => open,
- tx_lock => open,
- drpclk_in => AuroraSlaveClkxC.DrpClkxC,
- init_clk_in => AuroraMasterClkxC.InitClkxC,
- -- Master
- user_clk => AuroraMasterClkxC.UserClkxC,
- sync_clk => AuroraMasterClkxC.SyncClkxC,
- pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
- -- GT0
- gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
- gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
- gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
- gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
- gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
- gt_common_reset_out => open,
- -- Reset
- reset => AuroraMasterResetxR.SystemResetxR,
- gt_reset => AuroraMasterResetxR.GTResetxR,
- link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(2),
- sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(2),
- -- TX
- s_axi_tx_tdata => SouthTXM2SxD.DataxD,
- s_axi_tx_tkeep => SouthTXM2SxD.KeepxD,
- s_axi_tx_tlast => SouthTXM2SxD.LastxS,
- s_axi_tx_tvalid => SouthTXM2SxD.ValidxS,
- s_axi_tx_tready => SouthTXS2MxD.ReadyxS,
- -- RX
- m_axi_rx_tdata => SouthRXM2SxD.DataxD,
- m_axi_rx_tkeep => SouthRXM2SxD.KeepxD,
- m_axi_rx_tlast => SouthRXM2SxD.LastxS,
- m_axi_rx_tvalid => SouthRXM2SxD.ValidxS,
- -- TX UFC
- s_axi_ufc_tx_tvalid => SouthTXUFCM2SxD.ValidxS,
- s_axi_ufc_tx_tdata => SouthTXUFCM2SxD.DataxD, -- 3 bits
- s_axi_ufc_tx_tready => SouthTXUFCS2MxD.ReadyxS,
- -- RX UFC
- m_axi_ufc_rx_tdata => SouthRXUFCM2SxD.DataxD, -- 32 bits
- m_axi_ufc_rx_tkeep => SouthRXUFCM2SxD.KeepxD,
- m_axi_ufc_rx_tlast => SouthRXUFCM2SxD.LastxS,
- m_axi_ufc_rx_tvalid => SouthRXUFCM2SxD.ValidxS,
- -- GTP
- txp => GTPToSouthxD.TXPxD,
- txn => GTPToSouthxD.TXNxD,
- rxp => GTPFromSouthxD.RXPxD,
- rxn => GTPFromSouthxD.RXNxD,
- -- Status
- hard_err => AuroraStatusxD.HardErrxD(2),
- soft_err => AuroraStatusxD.SoftErrxD(2),
- frame_err => AuroraStatusxD.FrameErrxD(2),
- channel_up => AuroraStatusxD.ChannelUpxD(2),
- lane_up => AuroraStatusxD.LaneUpxD(2),
- tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(2),
- rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(2),
- -- Ctrl
- loopback => AuroraCtrlxD.LoopbackxD,
- power_down => AuroraCtrlxD.PowerDownxS,
- -- DRP
- drpen_in => AuroraDRPM2SxD(2).DrpEnxS,
- drpwe_in => AuroraDRPM2SxD(2).DrpWExS,
- drpaddr_in => AuroraDRPM2SxD(2).DrpAddrxD,
- drpdi_in => AuroraDRPM2SxD(2).DrpDIxD,
- drprdy_out => AuroraDRPS2MxD(2).DrpRdyxS,
- drpdo_out => AuroraDRPS2MxD(2).DrpDOxD);
-
- -- West Channel
-
- WestChannelxI : entity work.west_channel
- port map (
- -- Clocks and Locked
- -- Slave
- gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
- quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
- tx_out_clk => open,
- tx_lock => open,
- drpclk_in => AuroraSlaveClkxC.DrpClkxC,
- init_clk_in => AuroraMasterClkxC.InitClkxC,
- -- Master
- user_clk => AuroraMasterClkxC.UserClkxC,
- sync_clk => AuroraMasterClkxC.SyncClkxC,
- pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
- -- GT0
- gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
- gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
- gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
- gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
- gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
- gt_common_reset_out => open,
- -- Reset
- reset => AuroraMasterResetxR.SystemResetxR,
- gt_reset => AuroraMasterResetxR.GTResetxR,
- link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(3),
- sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(3),
- -- TX
- s_axi_tx_tdata => WestTXM2SxD.DataxD,
- s_axi_tx_tkeep => WestTXM2SxD.KeepxD,
- s_axi_tx_tlast => WestTXM2SxD.LastxS,
- s_axi_tx_tvalid => WestTXM2SxD.ValidxS,
- s_axi_tx_tready => WestTXS2MxD.ReadyxS,
- -- RX
- m_axi_rx_tdata => WestRXM2SxD.DataxD,
- m_axi_rx_tkeep => WestRXM2SxD.KeepxD,
- m_axi_rx_tlast => WestRXM2SxD.LastxS,
- m_axi_rx_tvalid => WestRXM2SxD.ValidxS,
- -- TX UFC
- s_axi_ufc_tx_tvalid => WestTXUFCM2SxD.ValidxS,
- s_axi_ufc_tx_tdata => WestTXUFCM2SxD.DataxD, -- 3 bits
- s_axi_ufc_tx_tready => WestTXUFCS2MxD.ReadyxS,
- -- RX UFC
- m_axi_ufc_rx_tdata => WestRXUFCM2SxD.DataxD, -- 32 bits
- m_axi_ufc_rx_tkeep => WestRXUFCM2SxD.KeepxD,
- m_axi_ufc_rx_tlast => WestRXUFCM2SxD.LastxS,
- m_axi_ufc_rx_tvalid => WestRXUFCM2SxD.ValidxS,
- -- GTP
- txp => GTPToWestxD.TXPxD,
- txn => GTPToWestxD.TXNxD,
- rxp => GTPFromWestxD.RXPxD,
- rxn => GTPFromWestxD.RXNxD,
- -- Status
- hard_err => AuroraStatusxD.HardErrxD(3),
- soft_err => AuroraStatusxD.SoftErrxD(3),
- frame_err => AuroraStatusxD.FrameErrxD(3),
- channel_up => AuroraStatusxD.ChannelUpxD(3),
- lane_up => AuroraStatusxD.LaneUpxD(3),
- tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(3),
- rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(3),
- -- Ctrl
- loopback => AuroraCtrlxD.LoopbackxD,
- power_down => AuroraCtrlxD.PowerDownxS,
- -- DRP
- drpen_in => AuroraDRPM2SxD(3).DrpEnxS,
- drpwe_in => AuroraDRPM2SxD(3).DrpWExS,
- drpaddr_in => AuroraDRPM2SxD(3).DrpAddrxD,
- drpdi_in => AuroraDRPM2SxD(3).DrpDIxD,
- drprdy_out => AuroraDRPS2MxD(3).DrpRdyxS,
- drpdo_out => AuroraDRPS2MxD(3).DrpDOxD);
-
- end block AuroraGTPhyxB;
+ TXxB : block is
+ begin -- block TXxB
+
+ NFCxB : block is
+ begin -- block NFCxB
+
+ -- North
+ NorthTXNFCM2SxAS : NorthTXNFCM2SxD <= NorthTXNFCM2SxDI;
+ NorthTXNFCS2MxAS : NorthTXNFCS2MxDO <= NorthTXNFCS2MxD;
+ -- East
+ EastTXNFCM2SxAS : EastTXNFCM2SxD <= EastTXNFCM2SxDI;
+ EastTXNFCS2MxAS : EastTXNFCS2MxDO <= EastTXNFCS2MxD;
+ -- South
+ SouthTXNFCM2SxAS : SouthTXNFCM2SxD <= SouthTXNFCM2SxDI;
+ SouthTXNFCS2MxAS : SouthTXNFCS2MxDO <= SouthTXNFCS2MxD;
+ -- West
+ WestTXNFCM2SxAS : WestTXNFCM2SxD <= WestTXNFCM2SxDI;
+ WestTXNFCS2MxAS : WestTXNFCS2MxDO <= WestTXNFCS2MxD;
+
+ end block NFCxB;
+
+ end block TXxB;
+
+ RXxB : block is
+ begin -- block RXxB
+
+ AXIxB : block is
+ begin -- block AXIxB
+
+ -- North
+ NorthRXM2SxAS : NorthRXM2SxDO <= NorthRXM2SxD;
+ -- East
+ EastRXM2SxAS : EastRXM2SxDO <= EastRXM2SxD;
+ -- South
+ SouthRXM2SxAS : SouthRXM2SxDO <= SouthRXM2SxD;
+ -- West
+ WestRXM2SxAS : WestRXM2SxDO <= WestRXM2SxD;
+
+ end block AXIxB;
+
+ NFCxB : block is
+ begin -- block NFCxB
+
+ -- North
+ NorthRXNFCM2SxAS : NorthRXNFCM2SxDO <= NorthRXNFCM2SxD;
+ -- East
+ EastRXNFCM2SxAS : EastRXNFCM2SxDO <= EastRXNFCM2SxD;
+ -- South
+ SouthRXNFCM2SxAS : SouthRXNFCM2SxDO <= SouthRXNFCM2SxD;
+ -- West
+ WestRXNFCM2SxAS : WestRXNFCM2SxDO <= WestRXNFCM2SxD;
+
+ end block NFCxB;
+
+ end block RXxB;
+
+ RXFifoStatusxB : block is
+ begin -- block RXFifoStatusxB
+
+ NorthRXFifoStatusxAS : NorthRXFifoStatusxDO <= C_NO_AXI4_FIFO_STATUS;
+ EastRXFifoStatusxAS : EastRXFifoStatusxDO <= C_NO_AXI4_FIFO_STATUS;
+ SouthRXFifoStatusxAS : SouthRXFifoStatusxDO <= C_NO_AXI4_FIFO_STATUS;
+ WestRXFifoStatusxAS : WestRXFifoStatusxDO <= C_NO_AXI4_FIFO_STATUS;
+ AxisFifoErrorxAS : AxisFifoErrorxDO <= C_NO_AXI4_FIFO_ERROR;
+
+ end block RXFifoStatusxB;
+
+ end block EntityIOxB;
+
+ elsif C_RX_FIFO_MODE = true generate
+
+ EntityIOxB : block is
+ begin -- block EntityIOxB
+
+ -- North
+ NorthRXNFCM2SxAS : NorthRXNFCM2SxDO <= C_NO_AXI4_NFC_M2S;
+ NorthTXNFCS2MxAS : NorthTXNFCS2MxDO <= C_NO_AXI4_NFC_S2M;
+ -- East
+ EastRXNFCM2SxAS : EastRXNFCM2SxDO <= C_NO_AXI4_NFC_M2S;
+ EastTXNFCS2MxAS : EastTXNFCS2MxDO <= C_NO_AXI4_NFC_S2M;
+ -- South
+ SouthRXNFCM2SxAS : SouthRXNFCM2SxDO <= C_NO_AXI4_NFC_M2S;
+ SouthTXNFCS2MxAS : SouthTXNFCS2MxDO <= C_NO_AXI4_NFC_S2M;
+ -- West
+ WestRXNFCM2SxAS : WestRXNFCM2SxDO <= C_NO_AXI4_NFC_M2S;
+ WestTXNFCS2MxAS : WestTXNFCS2MxDO <= C_NO_AXI4_NFC_S2M;
+
+ end block EntityIOxB;
+
+ RXFifoxB : block is
+ begin -- block RXFifoxB
+
+ NorthRXFifoRstxAS : RXFifoRstxRAN.NorthxR <= (not AuroraClkOutxC.PllNotLockedxS) and
+ (not RXResetxR.FifoResetxR.NorthxR);
+ EastRXFifoRstxAS : RXFifoRstxRAN.EastxR <= (not AuroraClkOutxC.PllNotLockedxS) and
+ (not RXResetxR.FifoResetxR.EastxR);
+ SouthRXFifoRstxAS : RXFifoRstxRAN.SouthxR <= (not AuroraClkOutxC.PllNotLockedxS) and
+ (not RXResetxR.FifoResetxR.SouthxR);
+ WestRXFifoRstxAS : RXFifoRstxRAN.WestxR <= (not AuroraClkOutxC.PllNotLockedxS) and
+ (not RXResetxR.FifoResetxR.WestxR);
+ -- North
+ NorthRXM2SxAS : NorthRXM2SxDO <= NorthFifoTXM2SxD;
+ NorthRXS2MxAS : NorthFifoTXS2MxD <= NorthRXS2MxDI;
+ NorthRXFifoStatusxAS : NorthRXFifoStatusxDO <= NorthRXFifoStatusxD;
+ -- East
+ EastRXM2SxAS : EastRXM2SxDO <= EastFifoTXM2SxD;
+ EastRXS2MxAS : EastFifoTXS2MxD <= EastRXS2MxDI;
+ EastRXFifoStatusxAS : EastRXFifoStatusxDO <= EastRXFifoStatusxD;
+ -- South
+ SouthRXM2SxAS : SouthRXM2SxDO <= SouthFifoTXM2SxD;
+ SouthRXS2MxAS : SouthFifoTXS2MxD <= SouthRXS2MxDI;
+ SouthRXFifoStatusxAS : SouthRXFifoStatusxDO <= SouthRXFifoStatusxD;
+ -- West
+ WestRXM2SxAS : WestRXM2SxDO <= WestFifoTXM2SxD;
+ WestRXS2MxAS : WestFifoTXS2MxD <= WestRXS2MxDI;
+ WestRXFifoStatusxAS : WestRXFifoStatusxDO <= WestRXFifoStatusxD;
+
+ ScalpAuroraPhyRxFifoxI : entity work.scalp_aurora_phy_rx_fifo
+ port map (
+ -- Clocks and Reset
+ RXClkxCI => AuroraClkOutxC.UserClkxC,
+ TXClkxCI => AuroraClkOutxC.UserClkxC,
+ RXRstxRANI => RXFifoRstxRAN,
+ -- North
+ -- Fifo RX Side
+ NorthRXM2SxDI => NorthRXM2SxD,
+ NorthRXS2MxDO => NorthFifoRXS2MxD,
+ -- Fifo TX Side
+ NorthTXM2SxDO => NorthFifoTXM2SxD,
+ NorthTXS2MxDI => NorthFifoTXS2MxD,
+ NorthFifoStatusxDO => NorthRXFifoStatusxD,
+ -- East
+ -- Fifo RX Side
+ EastRXM2SxDI => EastRXM2SxD,
+ EastRXS2MxDO => EastFifoRXS2MxD,
+ -- Fifo TX Side
+ EastTXM2SxDO => EastFifoTXM2SxD,
+ EastTXS2MxDI => EastFifoTXS2MxD,
+ EastFifoStatusxDO => EastRXFifoStatusxD,
+ -- South
+ -- Fifo RX Side
+ SouthRXM2SxDI => SouthRXM2SxD,
+ SouthRXS2MxDO => SouthFifoRXS2MxD,
+ -- Fifo TX Side
+ SouthTXM2SxDO => SouthFifoTXM2SxD,
+ SouthTXS2MxDI => SouthFifoTXS2MxD,
+ SouthFifoStatusxDO => SouthRXFifoStatusxD,
+ -- West
+ -- Fifo RX Side
+ WestRXM2SxDI => WestRXM2SxD,
+ WestRXS2MxDO => WestFifoRXS2MxD,
+ -- Fifo TX Side
+ WestTXM2SxDO => WestFifoTXM2SxD,
+ WestTXS2MxDI => WestFifoTXS2MxD,
+ WestFifoStatusxDO => WestRXFifoStatusxD);
+
+ end block RXFifoxB;
+
+ RXFifoResetDonexB : block is
+
+ signal NorthRXFifoResetDoneStatexDN : t_rx_fifo_reset_done_states := E_RESET;
+ signal NorthRXFifoResetDoneStatexDP : t_rx_fifo_reset_done_states := E_RESET;
+ signal EastRXFifoResetDoneStatexDN : t_rx_fifo_reset_done_states := E_RESET;
+ signal EastRXFifoResetDoneStatexDP : t_rx_fifo_reset_done_states := E_RESET;
+ signal SouthRXFifoResetDoneStatexDN : t_rx_fifo_reset_done_states := E_RESET;
+ signal SouthRXFifoResetDoneStatexDP : t_rx_fifo_reset_done_states := E_RESET;
+ signal WestRXFifoResetDoneStatexDN : t_rx_fifo_reset_done_states := E_RESET;
+ signal WestRXFifoResetDoneStatexDP : t_rx_fifo_reset_done_states := E_RESET;
+ signal AuroraPllLockedxS : std_ulogic := '0';
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ attribute mark_debug of NorthRXFifoResetDoneStatexDP : signal is "true";
+ attribute keep of NorthRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute mark_debug of EastRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute keep of EastRXFifoResetDoneStatexDP : signal is "true";
+ attribute mark_debug of SouthRXFifoResetDoneStatexDP : signal is "true";
+ attribute keep of SouthRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute mark_debug of WestRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute keep of WestRXFifoResetDoneStatexDP : signal is "true";
+
+ begin -- block RXFifoResetDonexB
+
+ AuroraPllLockedxAS : AuroraPllLockedxS <= not AuroraClkOutxC.PllNotLockedxS;
+
+ NorthRXFifoResetDoneDelayxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkOutxC.UserClkxC,
+ PllLockedxSI => AuroraPllLockedxS,
+ ResetxRI => RXFifoResetDonexD.NorthxS,
+ ResetDelayedxRO => RXFifoResetDoneDelayedxD.NorthxS);
+
+ EastRXFifoResetDoneDelayxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkOutxC.UserClkxC,
+ PllLockedxSI => AuroraPllLockedxS,
+ ResetxRI => RXFifoResetDonexD.EastxS,
+ ResetDelayedxRO => RXFifoResetDoneDelayedxD.EastxS);
+
+ SouthRXFifoResetDoneDelayxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkOutxC.UserClkxC,
+ PllLockedxSI => AuroraPllLockedxS,
+ ResetxRI => RXFifoResetDonexD.SouthxS,
+ ResetDelayedxRO => RXFifoResetDoneDelayedxD.SouthxS);
+
+ WestRXFifoResetDoneDelayxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkOutxC.UserClkxC,
+ PllLockedxSI => AuroraPllLockedxS,
+ ResetxRI => RXFifoResetDonexD.WestxS,
+ ResetDelayedxRO => RXFifoResetDoneDelayedxD.WestxS);
+
+ NorthUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ RXFifoRstxRAN.NorthxR) is
+ begin -- process NorthUpdateRegxP
+ if RXFifoRstxRAN.NorthxR = '0' then
+ NorthRXFifoResetDoneStatexDP <= E_RESET;
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ NorthRXFifoResetDoneStatexDP <= NorthRXFifoResetDoneStatexDN;
+ end if;
+ end process NorthUpdateRegxP;
+
+ EastUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ RXFifoRstxRAN.EastxR) is
+ begin -- process EastUpdateRegxP
+ if RXFifoRstxRAN.EastxR = '0' then
+ EastRXFifoResetDoneStatexDP <= E_RESET;
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ EastRXFifoResetDoneStatexDP <= EastRXFifoResetDoneStatexDN;
+ end if;
+
+ end process EastUpdateRegxP;
+
+ SouthUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ RXFifoRstxRAN.SouthxR) is
+ begin -- process SouthUpdateRegxP
+ if RXFifoRstxRAN.SouthxR = '0' then
+ SouthRXFifoResetDoneStatexDP <= E_RESET;
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ SouthRXFifoResetDoneStatexDP <= SouthRXFifoResetDoneStatexDN;
+ end if;
+
+ end process SouthUpdateRegxP;
+
+ WestUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ RXFifoRstxRAN.WestxR) is
+ begin -- process WestUpdateRegxP
+ if RXFifoRstxRAN.WestxR = '0' then
+ WestRXFifoResetDoneStatexDP <= E_RESET;
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ WestRXFifoResetDoneStatexDP <= WestRXFifoResetDoneStatexDN;
+ end if;
+
+ end process WestUpdateRegxP;
+
+ NorthRXFifoResetDonexP : process (NorthRXFifoResetDoneStatexDP,
+ NorthRXFifoStatusxD.ProgEmptyxS,
+ NorthRXFifoStatusxD.ProgFullxS) is
+ begin -- process NorthRXFifoResetDonexP
+ -- Default values
+ NorthRXFifoResetDoneStatexDN <= NorthRXFifoResetDoneStatexDP;
+ RXFifoResetDonexD.NorthxS <= '0';
+
+ case NorthRXFifoResetDoneStatexDP is
+ when E_RESET =>
+ NorthRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+
+ when E_WAIT_DONE =>
+ if (NorthRXFifoStatusxD.ProgFullxS = '1') and
+ (NorthRXFifoStatusxD.ProgEmptyxS = '1') then
+ NorthRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+ else
+ RXFifoResetDonexD.NorthxS <= '1';
+ NorthRXFifoResetDoneStatexDN <= E_IS_DONE;
+ end if;
+
+ when E_IS_DONE =>
+ RXFifoResetDonexD.NorthxS <= '1';
+
+ when others => null;
+ end case;
+ end process NorthRXFifoResetDonexP;
+
+ EastRXFifoResetDonexP : process (EastRXFifoResetDoneStatexDP,
+ EastRXFifoStatusxD.ProgEmptyxS,
+ EastRXFifoStatusxD.ProgFullxS) is
+ begin -- process EastRXFifoResetDonexP
+ -- Default values
+ EastRXFifoResetDoneStatexDN <= EastRXFifoResetDoneStatexDP;
+ RXFifoResetDonexD.EastxS <= '0';
+
+ case EastRXFifoResetDoneStatexDP is
+ when E_RESET =>
+ EastRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+
+ when E_WAIT_DONE =>
+ if (EastRXFifoStatusxD.ProgFullxS = '1') and
+ (EastRXFifoStatusxD.ProgEmptyxS = '1') then
+ EastRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+ else
+ RXFifoResetDonexD.EastxS <= '1';
+ EastRXFifoResetDoneStatexDN <= E_IS_DONE;
+ end if;
+
+ when E_IS_DONE =>
+ RXFifoResetDonexD.EastxS <= '1';
+
+ when others => null;
+ end case;
+ end process EastRXFifoResetDonexP;
+
+ SouthRXFifoResetDonexP : process (SouthRXFifoResetDoneStatexDP,
+ SouthRXFifoStatusxD.ProgEmptyxS,
+ SouthRXFifoStatusxD.ProgFullxS) is
+ begin -- process SouthRXFifoResetDonexP
+ -- Default values
+ SouthRXFifoResetDoneStatexDN <= SouthRXFifoResetDoneStatexDP;
+ RXFifoResetDonexD.SouthxS <= '0';
+
+ case SouthRXFifoResetDoneStatexDP is
+ when E_RESET =>
+ SouthRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+
+ when E_WAIT_DONE =>
+ if (SouthRXFifoStatusxD.ProgFullxS = '1') and
+ (SouthRXFifoStatusxD.ProgEmptyxS = '1') then
+ SouthRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+ else
+ RXFifoResetDonexD.SouthxS <= '1';
+ SouthRXFifoResetDoneStatexDN <= E_IS_DONE;
+ end if;
+
+ when E_IS_DONE =>
+ RXFifoResetDonexD.SouthxS <= '1';
+
+ when others => null;
+ end case;
+ end process SouthRXFifoResetDonexP;
+
+ WestRXFifoResetDonexP : process (WestRXFifoResetDoneStatexDP,
+ WestRXFifoStatusxD.ProgEmptyxS,
+ WestRXFifoStatusxD.ProgFullxS) is
+ begin -- process WestRXFifoResetDonexP
+ -- Default values
+ WestRXFifoResetDoneStatexDN <= WestRXFifoResetDoneStatexDP;
+ RXFifoResetDonexD.WestxS <= '0';
+
+ case WestRXFifoResetDoneStatexDP is
+ when E_RESET =>
+ WestRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+
+ when E_WAIT_DONE =>
+ if (WestRXFifoStatusxD.ProgFullxS = '1') and
+ (WestRXFifoStatusxD.ProgEmptyxS = '1') then
+ WestRXFifoResetDoneStatexDN <= E_WAIT_DONE;
+ else
+ RXFifoResetDonexD.WestxS <= '1';
+ WestRXFifoResetDoneStatexDN <= E_IS_DONE;
+ end if;
+
+ when E_IS_DONE =>
+ RXFifoResetDonexD.WestxS <= '1';
+
+ when others => null;
+ end case;
+ end process WestRXFifoResetDonexP;
+
+ end block RXFifoResetDonexB;
+
+ RXBackPressurexB : block is
+
+ signal BackPressureRstxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
+ -- North
+ signal NorthProgFullxSN : std_ulogic := '0';
+ signal NorthProgFullxSP : std_ulogic := '0';
+ signal NorthProgEmptyxSN : std_ulogic := '0';
+ signal NorthProgEmptyxSP : std_ulogic := '0';
+ signal NorthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal NorthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal NorthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthNFCValidxSN : std_ulogic := '0';
+ signal NorthNFCValidxSP : std_ulogic := '0';
+ -- East
+ signal EastProgFullxSN : std_ulogic := '0';
+ signal EastProgFullxSP : std_ulogic := '0';
+ signal EastProgEmptyxSN : std_ulogic := '0';
+ signal EastProgEmptyxSP : std_ulogic := '0';
+ signal EastNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal EastNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal EastNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastNFCValidxSN : std_ulogic := '0';
+ signal EastNFCValidxSP : std_ulogic := '0';
+ -- South
+ signal SouthProgFullxSN : std_ulogic := '0';
+ signal SouthProgFullxSP : std_ulogic := '0';
+ signal SouthProgEmptyxSN : std_ulogic := '0';
+ signal SouthProgEmptyxSP : std_ulogic := '0';
+ signal SouthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal SouthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal SouthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthNFCValidxSN : std_ulogic := '0';
+ signal SouthNFCValidxSP : std_ulogic := '0';
+ -- West
+ signal WestProgFullxSN : std_ulogic := '0';
+ signal WestProgFullxSP : std_ulogic := '0';
+ signal WestProgEmptyxSN : std_ulogic := '0';
+ signal WestProgEmptyxSP : std_ulogic := '0';
+ signal WestNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal WestNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal WestNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestNFCValidxSN : std_ulogic := '0';
+ signal WestNFCValidxSP : std_ulogic := '0';
+ -- Fifo Error
+ signal AxisFifoErrorxDN : t_axi4fifo_error := C_NO_AXI4_FIFO_ERROR;
+ signal AxisFifoErrorxDP : t_axi4fifo_error := C_NO_AXI4_FIFO_ERROR;
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ -- North
+ attribute mark_debug of NorthNFCStatexDP : signal is "true";
+ attribute keep of NorthNFCStatexDP : signal is "true";
+ attribute mark_debug of NorthProgFullxSP : signal is "true";
+ attribute keep of NorthProgFullxSP : signal is "true";
+ attribute mark_debug of NorthProgEmptyxSP : signal is "true";
+ attribute keep of NorthProgEmptyxSP : signal is "true";
+ -- East
+ -- attribute mark_debug of EastNFCStatexDP : signal is "true";
+ -- attribute keep of EastNFCStatexDP : signal is "true";
+ -- attribute mark_debug of EastProgFullxSP : signal is "true";
+ -- attribute keep of EastProgFullxSP : signal is "true";
+ -- attribute mark_debug of EastProgEmptyxSP : signal is "true";
+ -- attribute keep of EastProgEmptyxSP : signal is "true";
+ -- South
+ attribute mark_debug of SouthNFCStatexDP : signal is "true";
+ attribute keep of SouthNFCStatexDP : signal is "true";
+ attribute mark_debug of SouthProgFullxSP : signal is "true";
+ attribute keep of SouthProgFullxSP : signal is "true";
+ attribute mark_debug of SouthProgEmptyxSP : signal is "true";
+ attribute keep of SouthProgEmptyxSP : signal is "true";
+ -- West
+ -- attribute mark_debug of WestNFCStatexDP : signal is "true";
+ -- attribute keep of WestNFCStatexDP : signal is "true";
+ -- attribute mark_debug of WestProgFullxSP : signal is "true";
+ -- attribute keep of WestProgFullxSP : signal is "true";
+ -- attribute mark_debug of WestProgEmptyxSP : signal is "true";
+ -- attribute keep of WestProgEmptyxSP : signal is "true";
+
+ begin -- block RXBackPressurexB
+
+ NorthBackPressureRstxAS : BackPressureRstxR.NorthxR <= AuroraClkOutxC.PllNotLockedxS or
+ RXResetxR.BackPressureResetxR.NorthxR;
+ EastBackPressureRstxAS : BackPressureRstxR.EastxR <= AuroraClkOutxC.PllNotLockedxS or
+ RXResetxR.BackPressureResetxR.EastxR;
+ SouthBackPressureRstxAS : BackPressureRstxR.SouthxR <= AuroraClkOutxC.PllNotLockedxS or
+ RXResetxR.BackPressureResetxR.SouthxR;
+ WestBackPressureRstxAS : BackPressureRstxR.WestxR <= AuroraClkOutxC.PllNotLockedxS or
+ RXResetxR.BackPressureResetxR.WestxR;
+ -- NFC Data and valid signals
+ NorthNFCDataxAS : NorthTXNFCM2SxD.DataxD <= NorthNFCDataxDP;
+ NorthNFCValidxAS : NorthTXNFCM2SxD.ValidxS <= NorthNFCValidxSP;
+ NorthProgFullxAS : NorthProgFullxSN <= NorthRXFifoStatusxD.ProgFullxS;
+ NorthProgEmptyxAS : NorthProgEmptyxSN <= NorthRXFifoStatusxD.ProgEmptyxS;
+ EastNFCDataxAS : EastTXNFCM2SxD.DataxD <= EastNFCDataxDP;
+ EastNFCValidxAS : EastTXNFCM2SxD.ValidxS <= EastNFCValidxSP;
+ EastProgFullxAS : EastProgFullxSN <= EastRXFifoStatusxD.ProgFullxS;
+ EastProgEmptyxAS : EastProgEmptyxSN <= EastRXFifoStatusxD.ProgEmptyxS;
+ SouthNFCDataxAS : SouthTXNFCM2SxD.DataxD <= SouthNFCDataxDP;
+ SouthNFCValidxAS : SouthTXNFCM2SxD.ValidxS <= SouthNFCValidxSP;
+ SouthProgFullxAS : SouthProgFullxSN <= SouthRXFifoStatusxD.ProgFullxS;
+ SouthProgEmptyxAS : SouthProgEmptyxSN <= SouthRXFifoStatusxD.ProgEmptyxS;
+ WestNFCDataxAS : WestTXNFCM2SxD.DataxD <= WestNFCDataxDP;
+ WestNFCValidxAS : WestTXNFCM2SxD.ValidxS <= WestNFCValidxSP;
+ WestProgFullxAS : WestProgFullxSN <= WestRXFifoStatusxD.ProgFullxS;
+ WestProgEmptyxAS : WestProgEmptyxSN <= WestRXFifoStatusxD.ProgEmptyxS;
+ Axi4FifoErrorxAS : AxisFifoErrorxDO <= AxisFifoErrorxDP;
+
+ NorthUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ BackPressureRstxR.NorthxR) is
+ begin -- process NorthUpdateRegxP
+ if BackPressureRstxR.NorthxR = '1' then
+ NorthProgFullxSP <= '0';
+ NorthProgEmptyxSP <= '0';
+ NorthNFCStatexDP <= C_NFC_IDLE;
+ NorthNFCDataxDP <= (others => '0');
+ NorthNFCValidxSP <= '0';
+ AxisFifoErrorxDP.NorthCounterxD <= (others => '0');
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ NorthProgFullxSP <= NorthProgFullxSN;
+ NorthProgEmptyxSP <= NorthProgEmptyxSN;
+ NorthNFCStatexDP <= NorthNFCStatexDN;
+ NorthNFCDataxDP <= NorthNFCDataxDN;
+ NorthNFCValidxSP <= NorthNFCValidxSN;
+ AxisFifoErrorxDP.NorthCounterxD <= AxisFifoErrorxDN.NorthCounterxD;
+ end if;
+ end process NorthUpdateRegxP;
+
+ EastUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ BackPressureRstxR.EastxR) is
+ begin -- process EastUpdateRegxP
+ if BackPressureRstxR.EastxR = '1' then
+ EastProgFullxSP <= '0';
+ EastProgEmptyxSP <= '0';
+ EastNFCStatexDP <= C_NFC_IDLE;
+ EastNFCDataxDP <= (others => '0');
+ EastNFCValidxSP <= '0';
+ AxisFifoErrorxDP.EastCounterxD <= (others => '0');
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ EastProgFullxSP <= EastProgFullxSN;
+ EastProgEmptyxSP <= EastProgEmptyxSN;
+ EastNFCStatexDP <= EastNFCStatexDN;
+ EastNFCDataxDP <= EastNFCDataxDN;
+ EastNFCValidxSP <= EastNFCValidxSN;
+ AxisFifoErrorxDP.EastCounterxD <= AxisFifoErrorxDN.EastCounterxD;
+ end if;
+ end process EastUpdateRegxP;
+
+ SouthUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ BackPressureRstxR.SouthxR) is
+ begin -- process SouthUpdateRegxP
+ if BackPressureRstxR.SouthxR = '1' then
+ SouthProgFullxSP <= '0';
+ SouthProgEmptyxSP <= '0';
+ SouthNFCStatexDP <= C_NFC_IDLE;
+ SouthNFCDataxDP <= (others => '0');
+ SouthNFCValidxSP <= '0';
+ AxisFifoErrorxDP.SouthCounterxD <= (others => '0');
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ SouthProgFullxSP <= SouthProgFullxSN;
+ SouthProgEmptyxSP <= SouthProgEmptyxSN;
+ SouthNFCStatexDP <= SouthNFCStatexDN;
+ SouthNFCDataxDP <= SouthNFCDataxDN;
+ SouthNFCValidxSP <= SouthNFCValidxSN;
+ AxisFifoErrorxDP.SouthCounterxD <= AxisFifoErrorxDN.SouthCounterxD;
+ end if;
+ end process SouthUpdateRegxP;
+
+ WestUpdateRegxP : process (AuroraClkOutxC.UserClkxC,
+ BackPressureRstxR.WestxR) is
+ begin -- process WestUpdateRegxP
+ if BackPressureRstxR.WestxR = '1' then
+ WestProgFullxSP <= '0';
+ WestProgEmptyxSP <= '0';
+ WestNFCStatexDP <= C_NFC_IDLE;
+ WestNFCDataxDP <= (others => '0');
+ WestNFCValidxSP <= '0';
+ AxisFifoErrorxDP.WestCounterxD <= (others => '0');
+ elsif rising_edge(AuroraClkOutxC.UserClkxC) then
+ WestProgFullxSP <= WestProgFullxSN;
+ WestProgEmptyxSP <= WestProgEmptyxSN;
+ WestNFCStatexDP <= WestNFCStatexDN;
+ WestNFCDataxDP <= WestNFCDataxDN;
+ WestNFCValidxSP <= WestNFCValidxSN;
+ AxisFifoErrorxDP.WestCounterxD <= AxisFifoErrorxDN.WestCounterxD;
+ end if;
+ end process WestUpdateRegxP;
+
+ NorthErrorCounterxP : process (AxisFifoErrorxDP.NorthCounterxD,
+ NorthFifoRXS2MxD.ReadyxS,
+ NorthProgFullxSN,
+ NorthProgFullxSP) is
+ begin -- process NorthErrorCounterxP
+ -- Default values
+ AxisFifoErrorxDN.NorthCounterxD <= AxisFifoErrorxDP.NorthCounterxD;
+
+ if ((NorthProgFullxSP = '0' and NorthProgFullxSN = '0') or
+ (NorthProgFullxSP = '0' and NorthProgFullxSN = '1')) and
+ NorthFifoRXS2MxD.ReadyxS = '0' then
+ AxisFifoErrorxDN.NorthCounterxD <= AxisFifoErrorxDP.NorthCounterxD + 1;
+ end if;
+ end process NorthErrorCounterxP;
+
+ NorthNFCStatexP : process (NorthNFCDataxDP, NorthNFCStatexDP,
+ NorthNFCValidxSP, NorthProgEmptyxSN,
+ NorthProgEmptyxSP, NorthProgFullxSN,
+ NorthProgFullxSP,
+ NorthTXNFCS2MxD.ReadyxS) is
+ begin -- process NorthNFCStatexP
+ -- Default values
+ NorthNFCStatexDN <= NorthNFCStatexDP;
+ NorthNFCDataxDN <= NorthNFCDataxDP;
+ NorthNFCValidxSN <= NorthNFCValidxSP;
+
+ case NorthNFCStatexDP is
+ when C_NFC_IDLE =>
+ if (NorthProgFullxSP = '0' and NorthProgFullxSN = '0') then
+ NorthNFCStatexDN <= C_NFC_IS_XON;
+ else
+ NorthNFCDataxDN <= C_NFC_XOFF;
+ NorthNFCValidxSN <= '1';
+ NorthNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XON =>
+ if (NorthProgFullxSP = '0' and NorthProgFullxSN = '1') or
+ (NorthProgFullxSP = '1' and NorthProgFullxSN = '1') then
+ NorthNFCDataxDN <= C_NFC_XOFF;
+ NorthNFCValidxSN <= '1';
+ NorthNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if ((NorthProgEmptyxSP = '0' and NorthProgEmptyxSN = '1') or
+ (NorthProgEmptyxSP = '1' and NorthProgEmptyxSN = '1')) and
+ (NorthProgFullxSP = '0' and NorthProgFullxSN = '0') then
+ NorthNFCDataxDN <= C_NFC_XON;
+ NorthNFCValidxSN <= '1';
+ NorthNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if NorthTXNFCS2MxD.ReadyxS = '1' then
+ NorthNFCValidxSN <= '0';
+ NorthNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if NorthTXNFCS2MxD.ReadyxS = '1' then
+ NorthNFCValidxSN <= '0';
+ NorthNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process NorthNFCStatexP;
+
+ EastErrorCounterxP : process (AxisFifoErrorxDP.EastCounterxD,
+ EastFifoRXS2MxD.ReadyxS,
+ EastProgFullxSN, EastProgFullxSP) is
+ begin -- process EastErrorCounterxP
+ -- Default values
+ AxisFifoErrorxDN.EastCounterxD <= AxisFifoErrorxDP.EastCounterxD;
+
+ if ((EastProgFullxSP = '0' and EastProgFullxSN = '0') or
+ (EastProgFullxSP = '0' and EastProgFullxSN = '1')) and
+ EastFifoRXS2MxD.ReadyxS = '0' then
+ AxisFifoErrorxDN.EastCounterxD <= AxisFifoErrorxDP.EastCounterxD + 1;
+ end if;
+ end process EastErrorCounterxP;
+
+ EastNFCStatexP : process (EastNFCDataxDP, EastNFCStatexDP,
+ EastNFCValidxSP, EastProgEmptyxSN,
+ EastProgEmptyxSP, EastProgFullxSN,
+ EastProgFullxSP,
+ EastTXNFCS2MxD.ReadyxS) is
+ begin -- process EastNFCStatexP
+ -- Default values
+ EastNFCStatexDN <= EastNFCStatexDP;
+ EastNFCDataxDN <= EastNFCDataxDP;
+ EastNFCValidxSN <= EastNFCValidxSP;
+
+ case EastNFCStatexDP is
+ when C_NFC_IDLE =>
+ if (EastProgFullxSP = '0' and EastProgFullxSN = '0') then
+ EastNFCStatexDN <= C_NFC_IS_XON;
+ else
+ EastNFCDataxDN <= C_NFC_XOFF;
+ EastNFCValidxSN <= '1';
+ EastNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XON =>
+ if (EastProgFullxSP = '0' and EastProgFullxSN = '1') or
+ (EastProgFullxSP = '1' and EastProgFullxSN = '1') then
+ EastNFCDataxDN <= C_NFC_XOFF;
+ EastNFCValidxSN <= '1';
+ EastNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if ((EastProgEmptyxSP = '0' and EastProgEmptyxSN = '1') or
+ (EastProgEmptyxSP = '1' and EastProgEmptyxSN = '1')) and
+ (EastProgFullxSP = '0' and EastProgFullxSN = '0') then
+ EastNFCDataxDN <= C_NFC_XON;
+ EastNFCValidxSN <= '1';
+ EastNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if EastTXNFCS2MxD.ReadyxS = '1' then
+ EastNFCValidxSN <= '0';
+ EastNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if EastTXNFCS2MxD.ReadyxS = '1' then
+ EastNFCValidxSN <= '0';
+ EastNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process EastNFCStatexP;
+
+ SouthErrorCounterxP : process (AxisFifoErrorxDP.SouthCounterxD,
+ SouthFifoRXS2MxD.ReadyxS,
+ SouthProgFullxSN,
+ SouthProgFullxSP) is
+ begin -- process SouthErrorCounterxP
+ -- Default values
+ AxisFifoErrorxDN.SouthCounterxD <= AxisFifoErrorxDP.SouthCounterxD;
+
+ if ((SouthProgFullxSP = '0' and SouthProgFullxSN = '0') or
+ (SouthProgFullxSP = '0' and SouthProgFullxSN = '1')) and
+ SouthFifoRXS2MxD.ReadyxS = '0' then
+ AxisFifoErrorxDN.SouthCounterxD <= AxisFifoErrorxDP.SouthCounterxD + 1;
+ end if;
+ end process SouthErrorCounterxP;
+
+ SouthNFCStatexP : process (SouthNFCDataxDP, SouthNFCStatexDP,
+ SouthNFCValidxSP, SouthProgEmptyxSN,
+ SouthProgEmptyxSP, SouthProgFullxSN,
+ SouthProgFullxSP,
+ SouthTXNFCS2MxD.ReadyxS) is
+ begin -- process SouthNFCStatexP
+ -- Default values
+ SouthNFCStatexDN <= SouthNFCStatexDP;
+ SouthNFCDataxDN <= SouthNFCDataxDP;
+ SouthNFCValidxSN <= SouthNFCValidxSP;
+
+ case SouthNFCStatexDP is
+ when C_NFC_IDLE =>
+ if (SouthProgFullxSP = '0' and SouthProgFullxSN = '0') then
+ SouthNFCStatexDN <= C_NFC_IS_XON;
+ else
+ SouthNFCDataxDN <= C_NFC_XOFF;
+ SouthNFCValidxSN <= '1';
+ SouthNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XON =>
+ if (SouthProgFullxSP = '0' and SouthProgFullxSN = '1') or
+ (SouthProgFullxSP = '1' and SouthProgFullxSN = '1') then
+ SouthNFCDataxDN <= C_NFC_XOFF;
+ SouthNFCValidxSN <= '1';
+ SouthNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if ((SouthProgEmptyxSP = '0' and SouthProgEmptyxSN = '1') or
+ (SouthProgEmptyxSP = '1' and SouthProgEmptyxSN = '1')) and
+ (SouthProgFullxSP = '0' and SouthProgFullxSN = '0') then
+ SouthNFCDataxDN <= C_NFC_XON;
+ SouthNFCValidxSN <= '1';
+ SouthNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if SouthTXNFCS2MxD.ReadyxS = '1' then
+ SouthNFCValidxSN <= '0';
+ SouthNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if SouthTXNFCS2MxD.ReadyxS = '1' then
+ SouthNFCValidxSN <= '0';
+ SouthNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process SouthNFCStatexP;
+
+ WestErrorCounterxP : process (AxisFifoErrorxDP.WestCounterxD,
+ WestFifoRXS2MxD.ReadyxS,
+ WestProgFullxSN, WestProgFullxSP) is
+ begin -- process WestErrorCounterxP
+ -- Default values
+ AxisFifoErrorxDN.WestCounterxD <= AxisFifoErrorxDP.WestCounterxD;
+
+ if ((WestProgFullxSP = '0' and WestProgFullxSN = '0') or
+ (WestProgFullxSP = '0' and WestProgFullxSN = '1')) and
+ WestFifoRXS2MxD.ReadyxS = '0' then
+ AxisFifoErrorxDN.WestCounterxD <= AxisFifoErrorxDP.WestCounterxD + 1;
+ end if;
+ end process WestErrorCounterxP;
+
+ WestNFCStatexP : process (WestNFCDataxDP, WestNFCStatexDP,
+ WestNFCValidxSP, WestProgEmptyxSN,
+ WestProgEmptyxSP, WestProgFullxSN,
+ WestProgFullxSP,
+ WestTXNFCS2MxD.ReadyxS) is
+ begin -- process WestNFCStatexP
+ -- Default values
+ WestNFCStatexDN <= WestNFCStatexDP;
+ WestNFCDataxDN <= WestNFCDataxDP;
+ WestNFCValidxSN <= WestNFCValidxSP;
+
+ case WestNFCStatexDP is
+ when C_NFC_IDLE =>
+ if (WestProgFullxSP = '0' and WestProgFullxSN = '0') then
+ WestNFCStatexDN <= C_NFC_IS_XON;
+ else
+ WestNFCDataxDN <= C_NFC_XOFF;
+ WestNFCValidxSN <= '1';
+ WestNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XON =>
+ if (WestProgFullxSP = '0' and WestProgFullxSN = '1') or
+ (WestProgFullxSP = '1' and WestProgFullxSN = '1') then
+ WestNFCDataxDN <= C_NFC_XOFF;
+ WestNFCValidxSN <= '1';
+ WestNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if ((WestProgEmptyxSP = '0' and WestProgEmptyxSN = '1') or
+ (WestProgEmptyxSP = '1' and WestProgEmptyxSN = '1')) and
+ (WestProgFullxSP = '0' and WestProgFullxSN = '0') then
+ WestNFCDataxDN <= C_NFC_XON;
+ WestNFCValidxSN <= '1';
+ WestNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if WestTXNFCS2MxD.ReadyxS = '1' then
+ WestNFCValidxSN <= '0';
+ WestNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if WestTXNFCS2MxD.ReadyxS = '1' then
+ WestNFCValidxSN <= '0';
+ WestNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process WestNFCStatexP;
+
+ end block RXBackPressurexB;
+
+ end generate RXFifoModexG;
+
+ end block RXModexB;
end arch;
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy_wrapper.vhd b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7fb810aea59a564be92840aafe3146db3b81db87
--- /dev/null
+++ b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy_wrapper.vhd
@@ -0,0 +1,682 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_aurora_phy_wrapper - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: scalp_aurora_phy_wrapper
+--
+-- Last update: 2020-11-10
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_misc.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.axi4_pkg.all;
+use work.aurora_status_pkg.all;
+use work.aurora_drp_pkg.all;
+
+entity scalp_aurora_phy_wrapper is
+
+ generic (
+ C_DEBUG_MODE : boolean := false);
+
+ port (
+ -- GTP Ref Clocks
+ GTRefClkxCI : in t_gt_ref_slave_clk;
+ -- Aurora System and GTP Clocks
+ AuroraClkxCI : in t_aurora_slave_clk;
+ AuroraClkxCO : out t_aurora_master_clk;
+ -- Aurora Reset
+ AuroraResetxRI : in t_aurora_slave_reset;
+ AuroraResetxRO : out t_aurora_master_link_reset;
+ -- GTP Serial IO
+ -- North
+ GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
+ -- East
+ GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
+ -- South
+ GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
+ -- West
+ GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
+ -- Axi4 Framing Interface
+ -- North
+ NorthRXM2SxDO : out t_axi4m2s;
+ NorthTXM2SxDI : in t_axi4m2s;
+ NorthTXS2MxDO : out t_axi4s2m;
+ -- East
+ EastRXM2SxDO : out t_axi4m2s;
+ EastTXM2SxDI : in t_axi4m2s;
+ EastTXS2MxDO : out t_axi4s2m;
+ -- South
+ SouthRXM2SxDO : out t_axi4m2s;
+ SouthTXM2SxDI : in t_axi4m2s;
+ SouthTXS2MxDO : out t_axi4s2m;
+ -- West
+ WestRXM2SxDO : out t_axi4m2s;
+ WestTXM2SxDI : in t_axi4m2s;
+ WestTXS2MxDO : out t_axi4s2m;
+ -- Axi4 Framing UFC Interface
+ -- North
+ NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ -- East
+ EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ -- South
+ SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ -- West
+ WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ -- Axi4 Framing NFC Interface
+ -- North
+ NorthRXNFCM2SxDO : out t_axi4nfcm2s;
+ NorthTXNFCM2SxDI : in t_axi4nfcm2s;
+ NorthTXNFCS2MxDO : out t_axi4nfcs2m;
+ -- East
+ EastRXNFCM2SxDO : out t_axi4nfcm2s;
+ EastTXNFCM2SxDI : in t_axi4nfcm2s;
+ EastTXNFCS2MxDO : out t_axi4nfcs2m;
+ -- South
+ SouthRXNFCM2SxDO : out t_axi4nfcm2s;
+ SouthTXNFCM2SxDI : in t_axi4nfcm2s;
+ SouthTXNFCS2mxDO : out t_axi4nfcs2m;
+ -- West
+ WestRXNFCM2SxDO : out t_axi4nfcm2s;
+ WestTXNFCM2SxDI : in t_axi4nfcm2s;
+ WestTXNFCS2MxDO : out t_axi4nfcs2m;
+ -- Aurora Ctrl + Status
+ AuroraCtrlxDI : in t_aurora_control;
+ AuroraStatusxDO : out t_aurora_status;
+ -- DRP Port
+ AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
+ AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0));
+
+end scalp_aurora_phy_wrapper;
+
+
+architecture arch of scalp_aurora_phy_wrapper is
+
+ constant C_SIM_GTRESET_SPEEDUP : string := "false";
+ constant C_NUM_PLL : integer := 1;
+
+ component reset_logic is
+ port (
+ UserClkxCI : in std_logic;
+ InitClkxCI : in std_logic;
+ ResetxRI : in std_logic;
+ GTResetxRI : in std_logic;
+ SystemResetxRO : out std_logic;
+ GTResetxRO : out std_logic);
+ end component reset_logic;
+
+ component clock_module is
+ generic (
+ C_NUM_PLL : integer);
+ port (
+ InitClkxCI : in std_logic;
+ InitClkxCO : out std_logic;
+ GTClkxCI : in std_logic_vector((C_NUM_PLL - 1) downto 0);
+ GTClkLockedxDI : in std_logic_vector((C_NUM_PLL - 1) downto 0);
+ UserClkxCO : out std_logic_vector((C_NUM_PLL - 1) downto 0);
+ SyncClkxCO : out std_logic_vector((C_NUM_PLL - 1) downto 0);
+ PLLNotLockedxDO : out std_logic_vector((C_NUM_PLL - 1) downto 0));
+ end component clock_module;
+
+ component gt_common is
+ generic (
+ C_SIM_GTRESET_SPEEDUP : string);
+ port (
+ GT0GTRefClk0xCI : in std_logic;
+ GT0PLL0LockxSO : out std_logic;
+ GT0PLL1LockxSO : out std_logic;
+ GT0PLL0LockDetClkxCI : in std_logic;
+ GT0PLL0RefClkLostxSO : out std_logic;
+ GT0PLL0ClkxCO : out std_logic;
+ GT0PLL1ClkxCO : out std_logic;
+ GT0PLL0RefClkxCO : out std_logic;
+ GT0PLL1RefClkxCO : out std_logic;
+ GT0PLL0ResetxRI : in std_logic);
+ end component gt_common;
+
+ -- From Aurora Clock Module
+ signal AuroraSlaveClkxC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
+ signal AuroraMasterClkxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
+ -- From GT Common Module
+ signal GTCommonSlaveClkxC : t_gt_common_slave_clk := C_GT_COMMON_NO_SLAVE_CLK;
+ signal GTCommonMasterClkxC : t_gt_common_master_clk := C_GT_COMMON_NO_MASTER_CLK;
+ -- From Aurora Reset Logic
+ signal AuroraSlaveResetxR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
+ signal AuroraMasterResetxR : t_aurora_master_reset := C_AURORA_NO_MASTER_RESET;
+ -- From Aurora Core
+ signal AuroraMasterLinkResetxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
+ signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
+ signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
+ signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
+ signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+
+begin
+
+ ClocksIOxB : block is
+ begin -- block ClocksIOxB
+
+ AuroraClkSlaveInitClkxAS : AuroraSlaveClkxC.InitClkxC <= AuroraClkxCI.InitClkxC;
+ AuroraClkSlavexDrpClkxAS : AuroraSlaveClkxC.DrpClkxC <= AuroraClkxCI.DrpClkxC;
+ AuroraClkMasterInitClkxAS : AuroraClkxCO.InitClkxC <= AuroraMasterClkxC.InitClkxC;
+ AuroraClkMasterUserClkxAS : AuroraClkxCO.UserClkxC <= AuroraMasterClkxC.UserClkxC;
+ AuroraClkMasterPllNotLockedxAS : AuroraClkxCO.PLLNotLockedxS <= AuroraMasterClkxC.PllNotLockedxS;
+
+ end block ClocksIOxB;
+
+ ResetIOxB : block is
+ begin -- block ResetIOxB
+
+ GT0GTRefClk0xAS : GTCommonSlaveClkxC.GTRefClkxC <= GTRefClkxCI.GTRefClkxC;
+ GT0PLL0LockDetClkxAS : GTCommonSlaveClkxC.GTPLL0LockDetClkxC <= AuroraMasterClkxC.InitClkxC;
+ AuroraSlaveResetResetxAS : AuroraSlaveResetxR.ResetxR <= AuroraResetxRI.ResetxR;
+ AuroraSlaveResetGTResetxAS : AuroraSlaveResetxR.GTResetxR <= AuroraResetxRI.GTResetxR;
+ AuroraMasterLinkResetSystemResetxAS : AuroraResetxRO.SystemResetxR <= AuroraMasterLinkResetxR.SystemResetxR;
+ AuroraMasterLinkResetLinkResetxAS : AuroraResetxRO.LinkResetxR <= AuroraMasterLinkResetxR.LinkResetxR;
+
+ end block ResetIOxB;
+
+ SignalsIOxB : block is
+ begin -- block SignalsIOxB
+
+ -- Axi4 Framing
+ NorthRXM2SxAS : NorthRXM2SxDO <= NorthRXM2SxD;
+ NorthTXM2SxAS : NorthTXM2SxD <= NorthTXM2SxDI;
+ NorthTXS2MxAS : NorthTXS2MxDO <= NorthTXS2MxD;
+ EastRXM2SxAS : EastRXM2SxDO <= EastRXM2SxD;
+ EastTXM2SxAS : EastTXM2SxD <= EastTXM2SxDI;
+ EastTXS2MxAS : EastTXS2MxDO <= EastTXS2MxD;
+ SouthRXM2SxAS : SouthRXM2SxDO <= SouthRXM2SxD;
+ SouthTXM2SxAS : SouthTXM2SxD <= SouthTXM2SxDI;
+ SouthTXS2MxAS : SouthTXS2MxDO <= SouthTXS2MxD;
+ WestRXM2SxAS : WestRXM2SxDO <= WestRXM2SxD;
+ WestTXM2SxAS : WestTXM2SxD <= WestTXM2SxDI;
+ WestTXS2MxAS : WestTXS2MxDO <= WestTXS2MxD;
+ -- Axi4 Framing UFC
+ NorthRXUFCM2SxAS : NorthRXUFCM2SxDO <= NorthRXUFCM2SxD;
+ NorthTXUFCM2SxAS : NorthTXUFCM2SxD <= NorthTXUFCM2SxDI;
+ NorthTXUFCS2MxAS : NorthTXUFCS2MxDO <= NorthTXUFCS2MxD;
+ EastRXUFCM2SxAS : EastRXUFCM2SxDO <= EastRXUFCM2SxD;
+ EastTXUFCM2SxAS : EastTXUFCM2SxD <= EastTXUFCM2SxDI;
+ EastTXUFCS2MxAS : EastTXUFCS2MxDO <= EastTXUFCS2MxD;
+ SouthRXUFCM2SxAS : SouthRXUFCM2SxDO <= SouthRXUFCM2SxD;
+ SouthTXUFCM2SxAS : SouthTXUFCM2SxD <= SouthTXUFCM2SxDI;
+ SouthTXUFCS2MxAS : SouthTXUFCS2MxDO <= SouthTXUFCS2MxD;
+ WestRXUFCM2SxAS : WestRXUFCM2SxDO <= WestRXUFCM2SxD;
+ WestTXUFCM2SxAS : WestTXUFCM2SxD <= WestTXUFCM2SxDI;
+ WestTXUFCS2MxAS : WestTXUFCS2MxDO <= WestTXUFCS2MxD;
+ -- Axi4 Framing NFC
+ NorthRXNFCM2SxAS : NorthRXNFCM2SxDO <= NorthRXNFCM2SxD;
+ NorthTXNFCM2SxAS : NorthTXNFCM2SxD <= NorthTXNFCM2SxDI;
+ NorthTXNFCS2MxAS : NorthTXNFCS2MxDO <= NorthTXNFCS2MxD;
+ EastRXNFCM2SxAS : EastRXNFCM2SxDO <= EastRXNFCM2SxD;
+ EastTXNFCM2SxAS : EastTXNFCM2SxD <= EastTXNFCM2SxDI;
+ EastTXNFCS2MxAS : EastTXNFCS2MxDO <= EastTXNFCS2MxD;
+ SouthRXNFCM2SxAS : SouthRXNFCM2SxDO <= SouthRXNFCM2SxD;
+ SouthTXNFCM2SxAS : SouthTXNFCM2SxD <= SouthTXNFCM2SxDI;
+ SouthTXNFCS2MxAS : SouthTXNFCS2MxDO <= SouthTXNFCS2MxD;
+ WestRXNFCM2SxAS : WestRXNFCM2SxDO <= WestRXNFCM2SxD;
+ WestTXNFCM2SxAS : WestTXNFCM2SxD <= WestTXNFCM2SxDI;
+ WestTXNFCS2MxAS : WestTXNFCS2MxDO <= WestTXNFCS2MxD;
+ -- GTP Serial IO
+ GTPFromNorthxAS : GTPFromNorthxD <= GTPFromNorthxDI;
+ GTPToNorthxAS : GTPToNorthxDO <= GTPToNorthxD;
+ GTPFromEastxAS : GTPFromEastxD <= GTPFromEastxDI;
+ GTPToEastxAS : GTPToEastxDO <= GTPToEastxD;
+ GTPFromSouthxAS : GTPFromSouthxD <= GTPFromSouthxDI;
+ GTPToSouthxAS : GTPToSouthxDO <= GTPToSouthxD;
+ GTPFromWestxAS : GTPFromWestxD <= GTPFromWestxDI;
+ GTPToWestxAS : GTPToWestxDO <= GTPToWestxD;
+ -- Aurora Ctrl + Status
+ AuroraCtrlxAS : AuroraCtrlxD <= AuroraCtrlxDI;
+ AuroraStatusxAS : AuroraStatusxDO <= AuroraStatusxD;
+ -- Aurora DRP Port
+ AuroraDRPM2SxAS : AuroraDRPM2SxD <= AuroraDRPM2SxDI;
+ AuroraDRPS2MxAS : AuroraDRPS2MxDO <= AuroraDRPS2MxD;
+
+ end block SignalsIOxB;
+
+ ClkRstxB : block is
+ begin -- block ClkRstxB
+
+ AuroraResetLogicxI : entity work.reset_logic
+ port map (
+ UserClkxCI => AuroraMasterClkxC.UserClkxC,
+ InitClkxCI => AuroraMasterClkxC.InitClkxC,
+ ResetxRI => AuroraSlaveResetxR.ResetxR, -- Sync on UserClk
+ GTResetxRI => AuroraSlaveResetxR.GTResetxR, -- Sync on InitClk
+ SystemResetxRO => AuroraMasterResetxR.SystemResetxR,
+ GTResetxRO => AuroraMasterResetxR.GTResetxR);
+
+ AuroraClockModulexI : entity work.clock_module
+ generic map (
+ C_NUM_PLL => C_NUM_PLL)
+ port map (
+ -- Slave
+ InitClkxCI => AuroraSlaveClkxC.InitClkxC,
+ GTClkxCI(0) => AuroraSlaveClkxC.GTClkxC,
+ GTClkLockedxDI(0) => AuroraSlaveClkxC.GTClkLockedxS,
+ -- Master
+ InitClkxCO => AuroraMasterClkxC.InitClkxC,
+ UserClkxCO(0) => AuroraMasterClkxC.UserClkxC,
+ SyncClkxCO(0) => AuroraMasterClkxC.SyncClkxC,
+ PLLNotLockedxDO(0) => AuroraMasterClkxC.PllNotLockedxS);
+
+ GTCommonxI : entity work.gt_common
+ generic map (
+ C_SIM_GTRESET_SPEEDUP => C_SIM_GTRESET_SPEEDUP)
+ port map (
+ -- Slave
+ GT0GTRefClk0xCI => GTCommonSlaveClkxC.GTRefClkxC,
+ GT0PLL0LockDetClkxCI => GTCommonSlaveClkxC.GTPLL0LockDetClkxC,
+ GT0PLL0ResetxRI => GTCommonSlaveClkxC.CommonResetxR,
+ -- Master
+ GT0PLL0ClkxCO => GTCommonMasterClkxC.GTPLL0ClkxCO,
+ GT0PLL1ClkxCO => GTCommonMasterClkxC.GTPLL1ClkxCO,
+ GT0PLL0RefClkxCO => GTCommonMasterClkxC.GTPLL0RefClkxC,
+ GT0PLL1RefClkxCO => GTCommonMasterClkxC.GTPLL1RefClkxC,
+ GT0PLL0LockxSO => GTCommonMasterClkxC.GTPLL0LockxS,
+ GT0PLL1LockxSO => GTCommonMasterClkxC.GTPLL1LockxS,
+ GT0PLL0RefClkLostxSO => GTCommonMasterClkxC.GTPLL0RefClkLostxS);
+
+ end block ClkRstxB;
+
+ -- Aurora GT Phy
+
+ AuroraGTPhyxB : block is
+ begin -- block AuroraGTPhyxB
+
+ -- North Channel
+
+ NorthChannelxI : entity work.north_channel
+ port map (
+ -- Clocks and Locked
+ -- Slave
+ gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
+ quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
+ tx_out_clk => AuroraSlaveClkxC.GTClkxC, -- Only North
+ tx_lock => AuroraSlaveClkxC.GTClkLockedxS, -- Only North
+ drpclk_in => AuroraSlaveClkxC.DrpClkxC,
+ init_clk_in => AuroraMasterClkxC.InitClkxC,
+ -- Master
+ user_clk => AuroraMasterClkxC.UserClkxC,
+ sync_clk => AuroraMasterClkxC.SyncClkxC,
+ pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
+ -- GT0
+ gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
+ gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
+ gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
+ gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
+ gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
+ gt_common_reset_out => GTCommonSlaveClkxC.CommonResetxR, -- Only North
+ -- Reset
+ reset => AuroraMasterResetxR.SystemResetxR,
+ gt_reset => AuroraMasterResetxR.GTResetxR,
+ link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(0),
+ sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(0),
+ -- TX
+ s_axi_tx_tdata => NorthTXM2SxD.DataxD,
+ s_axi_tx_tkeep => NorthTXM2SxD.KeepxD,
+ s_axi_tx_tlast => NorthTXM2SxD.LastxS,
+ s_axi_tx_tvalid => NorthTXM2SxD.ValidxS,
+ s_axi_tx_tready => NorthTXS2MxD.ReadyxS,
+ -- RX
+ m_axi_rx_tdata => NorthRXM2SxD.DataxD,
+ m_axi_rx_tkeep => NorthRXM2SxD.KeepxD,
+ m_axi_rx_tlast => NorthRXM2SxD.LastxS,
+ m_axi_rx_tvalid => NorthRXM2SxD.ValidxS,
+ -- TX UFC
+ s_axi_ufc_tx_tvalid => NorthTXUFCM2SxD.ValidxS,
+ s_axi_ufc_tx_tdata => NorthTXUFCM2SxD.DataxD, -- 3 bits
+ s_axi_ufc_tx_tready => NorthTXUFCS2MxD.ReadyxS,
+ -- RX UFC
+ m_axi_ufc_rx_tdata => NorthRXUFCM2SxD.DataxD, -- 32 bits
+ m_axi_ufc_rx_tkeep => NorthRXUFCM2SxD.KeepxD,
+ m_axi_ufc_rx_tlast => NorthRXUFCM2SxD.LastxS,
+ m_axi_ufc_rx_tvalid => NorthRXUFCM2SxD.ValidxS,
+ -- TX NFC
+ s_axi_nfc_tx_tdata => NorthTXNFCM2SxD.DataxD,
+ s_axi_nfc_tx_tvalid => NorthTXNFCM2SxD.ValidxS,
+ s_axi_nfc_tx_tready => NorthTXNFCS2MxD.ReadyxS,
+ -- RX NFC
+ m_axi_nfc_rx_tdata => NorthRXNFCM2SxD.DataxD,
+ m_axi_nfc_rx_tvalid => NorthRXNFCM2SxD.ValidxS,
+ -- GTP
+ txp => GTPToNorthxD.TXPxD,
+ txn => GTPToNorthxD.TXNxD,
+ rxp => GTPFromNorthxD.RXPxD,
+ rxn => GTPFromNorthxD.RXNxD,
+ -- Status
+ hard_err => AuroraStatusxD.HardErrxD(0),
+ soft_err => AuroraStatusxD.SoftErrxD(0),
+ frame_err => AuroraStatusxD.FrameErrxD(0),
+ channel_up => AuroraStatusxD.ChannelUpxD(0),
+ lane_up => AuroraStatusxD.LaneUpxD(0),
+ tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(0),
+ rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(0),
+ -- Ctrl
+ loopback => AuroraCtrlxD.LoopbackxD,
+ power_down => AuroraCtrlxD.PowerDownxS,
+ -- DRP
+ drpen_in => AuroraDRPM2SxD(0).DrpEnxS,
+ drpwe_in => AuroraDRPM2SxD(0).DrpWExS,
+ drpaddr_in => AuroraDRPM2SxD(0).DrpAddrxD,
+ drpdi_in => AuroraDRPM2SxD(0).DrpDIxD,
+ drprdy_out => AuroraDRPS2MxD(0).DrpRdyxS,
+ drpdo_out => AuroraDRPS2MxD(0).DrpDOxD);
+
+ -- East Channel
+
+ EastChannelxI : entity work.east_channel
+ port map (
+ -- Clocks and Locked
+ -- Slave
+ gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
+ quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
+ tx_out_clk => open,
+ tx_lock => open,
+ drpclk_in => AuroraSlaveClkxC.DrpClkxC,
+ init_clk_in => AuroraMasterClkxC.InitClkxC,
+ -- Master
+ user_clk => AuroraMasterClkxC.UserClkxC,
+ sync_clk => AuroraMasterClkxC.SyncClkxC,
+ pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
+ -- GT0
+ gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
+ gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
+ gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
+ gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
+ gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
+ gt_common_reset_out => open,
+ -- Reset
+ reset => AuroraMasterResetxR.SystemResetxR,
+ gt_reset => AuroraMasterResetxR.GTResetxR,
+ link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(1),
+ sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(1),
+ -- TX
+ s_axi_tx_tdata => EastTXM2SxD.DataxD,
+ s_axi_tx_tkeep => EastTXM2SxD.KeepxD,
+ s_axi_tx_tlast => EastTXM2SxD.LastxS,
+ s_axi_tx_tvalid => EastTXM2SxD.ValidxS,
+ s_axi_tx_tready => EastTXS2MxD.ReadyxS,
+ -- RX
+ m_axi_rx_tdata => EastRXM2SxD.DataxD,
+ m_axi_rx_tkeep => EastRXM2SxD.KeepxD,
+ m_axi_rx_tlast => EastRXM2SxD.LastxS,
+ m_axi_rx_tvalid => EastRXM2SxD.ValidxS,
+ -- TX UFC
+ s_axi_ufc_tx_tvalid => EastTXUFCM2SxD.ValidxS,
+ s_axi_ufc_tx_tdata => EastTXUFCM2SxD.DataxD, -- 3 bits
+ s_axi_ufc_tx_tready => EastTXUFCS2MxD.ReadyxS,
+ -- RX UFC
+ m_axi_ufc_rx_tdata => EastRXUFCM2SxD.DataxD, -- 32 bits
+ m_axi_ufc_rx_tkeep => EastRXUFCM2SxD.KeepxD,
+ m_axi_ufc_rx_tlast => EastRXUFCM2SxD.LastxS,
+ m_axi_ufc_rx_tvalid => EastRXUFCM2SxD.ValidxS,
+ -- TX NFC
+ s_axi_nfc_tx_tdata => EastTXNFCM2SxD.DataxD,
+ s_axi_nfc_tx_tvalid => EastTXNFCM2SxD.ValidxS,
+ s_axi_nfc_tx_tready => EastTXNFCS2MxD.ReadyxS,
+ -- RX NFC
+ m_axi_nfc_rx_tdata => EastRXNFCM2SxD.DataxD,
+ m_axi_nfc_rx_tvalid => EastRXNFCM2SxD.ValidxS,
+ -- GTP
+ txp => GTPToEastxD.TXPxD,
+ txn => GTPToEastxD.TXNxD,
+ rxp => GTPFromEastxD.RXPxD,
+ rxn => GTPFromEastxD.RXNxD,
+ -- Status
+ hard_err => AuroraStatusxD.HardErrxD(1),
+ soft_err => AuroraStatusxD.SoftErrxD(1),
+ frame_err => AuroraStatusxD.FrameErrxD(1),
+ channel_up => AuroraStatusxD.ChannelUpxD(1),
+ lane_up => AuroraStatusxD.LaneUpxD(1),
+ tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(1),
+ rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(1),
+ -- Ctrl
+ loopback => AuroraCtrlxD.LoopbackxD,
+ power_down => AuroraCtrlxD.PowerDownxS,
+ -- DRP
+ drpen_in => AuroraDRPM2SxD(1).DrpEnxS,
+ drpwe_in => AuroraDRPM2SxD(1).DrpWExS,
+ drpaddr_in => AuroraDRPM2SxD(1).DrpAddrxD,
+ drpdi_in => AuroraDRPM2SxD(1).DrpDIxD,
+ drprdy_out => AuroraDRPS2MxD(1).DrpRdyxS,
+ drpdo_out => AuroraDRPS2MxD(1).DrpDOxD);
+
+ -- South Channel
+
+ SouthChannelxI : entity work.south_channel
+ port map (
+ -- Clocks and Locked
+ -- Slave
+ gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
+ quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
+ tx_out_clk => open,
+ tx_lock => open,
+ drpclk_in => AuroraSlaveClkxC.DrpClkxC,
+ init_clk_in => AuroraMasterClkxC.InitClkxC,
+ -- Master
+ user_clk => AuroraMasterClkxC.UserClkxC,
+ sync_clk => AuroraMasterClkxC.SyncClkxC,
+ pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
+ -- GT0
+ gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
+ gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
+ gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
+ gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
+ gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
+ gt_common_reset_out => open,
+ -- Reset
+ reset => AuroraMasterResetxR.SystemResetxR,
+ gt_reset => AuroraMasterResetxR.GTResetxR,
+ link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(2),
+ sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(2),
+ -- TX
+ s_axi_tx_tdata => SouthTXM2SxD.DataxD,
+ s_axi_tx_tkeep => SouthTXM2SxD.KeepxD,
+ s_axi_tx_tlast => SouthTXM2SxD.LastxS,
+ s_axi_tx_tvalid => SouthTXM2SxD.ValidxS,
+ s_axi_tx_tready => SouthTXS2MxD.ReadyxS,
+ -- RX
+ m_axi_rx_tdata => SouthRXM2SxD.DataxD,
+ m_axi_rx_tkeep => SouthRXM2SxD.KeepxD,
+ m_axi_rx_tlast => SouthRXM2SxD.LastxS,
+ m_axi_rx_tvalid => SouthRXM2SxD.ValidxS,
+ -- TX UFC
+ s_axi_ufc_tx_tvalid => SouthTXUFCM2SxD.ValidxS,
+ s_axi_ufc_tx_tdata => SouthTXUFCM2SxD.DataxD, -- 3 bits
+ s_axi_ufc_tx_tready => SouthTXUFCS2MxD.ReadyxS,
+ -- RX UFC
+ m_axi_ufc_rx_tdata => SouthRXUFCM2SxD.DataxD, -- 32 bits
+ m_axi_ufc_rx_tkeep => SouthRXUFCM2SxD.KeepxD,
+ m_axi_ufc_rx_tlast => SouthRXUFCM2SxD.LastxS,
+ m_axi_ufc_rx_tvalid => SouthRXUFCM2SxD.ValidxS,
+ -- TX NFC
+ s_axi_nfc_tx_tdata => SouthTXNFCM2SxD.DataxD,
+ s_axi_nfc_tx_tvalid => SouthTXNFCM2SxD.ValidxS,
+ s_axi_nfc_tx_tready => SouthTXNFCS2MxD.ReadyxS,
+ -- RX NFC
+ m_axi_nfc_rx_tdata => SouthRXNFCM2SxD.DataxD,
+ m_axi_nfc_rx_tvalid => SouthRXNFCM2SxD.ValidxS,
+ -- GTP
+ txp => GTPToSouthxD.TXPxD,
+ txn => GTPToSouthxD.TXNxD,
+ rxp => GTPFromSouthxD.RXPxD,
+ rxn => GTPFromSouthxD.RXNxD,
+ -- Status
+ hard_err => AuroraStatusxD.HardErrxD(2),
+ soft_err => AuroraStatusxD.SoftErrxD(2),
+ frame_err => AuroraStatusxD.FrameErrxD(2),
+ channel_up => AuroraStatusxD.ChannelUpxD(2),
+ lane_up => AuroraStatusxD.LaneUpxD(2),
+ tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(2),
+ rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(2),
+ -- Ctrl
+ loopback => AuroraCtrlxD.LoopbackxD,
+ power_down => AuroraCtrlxD.PowerDownxS,
+ -- DRP
+ drpen_in => AuroraDRPM2SxD(2).DrpEnxS,
+ drpwe_in => AuroraDRPM2SxD(2).DrpWExS,
+ drpaddr_in => AuroraDRPM2SxD(2).DrpAddrxD,
+ drpdi_in => AuroraDRPM2SxD(2).DrpDIxD,
+ drprdy_out => AuroraDRPS2MxD(2).DrpRdyxS,
+ drpdo_out => AuroraDRPS2MxD(2).DrpDOxD);
+
+ -- West Channel
+
+ WestChannelxI : entity work.west_channel
+ port map (
+ -- Clocks and Locked
+ -- Slave
+ gt_refclk1 => GTCommonSlaveClkxC.GTRefClkxC,
+ quad1_common_lock_in => GTCommonMasterClkxC.GTPLL0LockxS,
+ tx_out_clk => open,
+ tx_lock => open,
+ drpclk_in => AuroraSlaveClkxC.DrpClkxC,
+ init_clk_in => AuroraMasterClkxC.InitClkxC,
+ -- Master
+ user_clk => AuroraMasterClkxC.UserClkxC,
+ sync_clk => AuroraMasterClkxC.SyncClkxC,
+ pll_not_locked => AuroraMasterClkxC.PllNotLockedxS,
+ -- GT0
+ gt0_pll0outclk_in => GTCommonMasterClkxC.GTPLL0ClkxCO,
+ gt0_pll1outclk_in => GTCommonMasterClkxC.GTPLL1ClkxCO,
+ gt0_pll0outrefclk_in => GTCommonMasterClkxC.GTPLL0RefClkxC,
+ gt0_pll1outrefclk_in => GTCommonMasterClkxC.GTPLL1RefClkxC,
+ gt0_pll0refclklost_in => GTCommonMasterClkxC.GTPLL0RefClkLostxS,
+ gt_common_reset_out => open,
+ -- Reset
+ reset => AuroraMasterResetxR.SystemResetxR,
+ gt_reset => AuroraMasterResetxR.GTResetxR,
+ link_reset_out => AuroraMasterLinkResetxR.LinkResetxR(3),
+ sys_reset_out => AuroraMasterLinkResetxR.SystemResetxR(3),
+ -- TX
+ s_axi_tx_tdata => WestTXM2SxD.DataxD,
+ s_axi_tx_tkeep => WestTXM2SxD.KeepxD,
+ s_axi_tx_tlast => WestTXM2SxD.LastxS,
+ s_axi_tx_tvalid => WestTXM2SxD.ValidxS,
+ s_axi_tx_tready => WestTXS2MxD.ReadyxS,
+ -- RX
+ m_axi_rx_tdata => WestRXM2SxD.DataxD,
+ m_axi_rx_tkeep => WestRXM2SxD.KeepxD,
+ m_axi_rx_tlast => WestRXM2SxD.LastxS,
+ m_axi_rx_tvalid => WestRXM2SxD.ValidxS,
+ -- TX UFC
+ s_axi_ufc_tx_tvalid => WestTXUFCM2SxD.ValidxS,
+ s_axi_ufc_tx_tdata => WestTXUFCM2SxD.DataxD, -- 3 bits
+ s_axi_ufc_tx_tready => WestTXUFCS2MxD.ReadyxS,
+ -- RX UFC
+ m_axi_ufc_rx_tdata => WestRXUFCM2SxD.DataxD, -- 32 bits
+ m_axi_ufc_rx_tkeep => WestRXUFCM2SxD.KeepxD,
+ m_axi_ufc_rx_tlast => WestRXUFCM2SxD.LastxS,
+ m_axi_ufc_rx_tvalid => WestRXUFCM2SxD.ValidxS,
+ -- TX NFC
+ s_axi_nfc_tx_tdata => WestTXNFCM2SxD.DataxD,
+ s_axi_nfc_tx_tvalid => WestTXNFCM2SxD.ValidxS,
+ s_axi_nfc_tx_tready => WestTXNFCS2MxD.ReadyxS,
+ -- RX NFC
+ m_axi_nfc_rx_tdata => WestRXNFCM2SxD.DataxD,
+ m_axi_nfc_rx_tvalid => WestRXNFCM2SxD.ValidxS,
+ -- GTP
+ txp => GTPToWestxD.TXPxD,
+ txn => GTPToWestxD.TXNxD,
+ rxp => GTPFromWestxD.RXPxD,
+ rxn => GTPFromWestxD.RXNxD,
+ -- Status
+ hard_err => AuroraStatusxD.HardErrxD(3),
+ soft_err => AuroraStatusxD.SoftErrxD(3),
+ frame_err => AuroraStatusxD.FrameErrxD(3),
+ channel_up => AuroraStatusxD.ChannelUpxD(3),
+ lane_up => AuroraStatusxD.LaneUpxD(3),
+ tx_resetdone_out => AuroraStatusxD.TXResetDoneOutxD(3),
+ rx_resetdone_out => AuroraStatusxD.RXResetDoneOutxD(3),
+ -- Ctrl
+ loopback => AuroraCtrlxD.LoopbackxD,
+ power_down => AuroraCtrlxD.PowerDownxS,
+ -- DRP
+ drpen_in => AuroraDRPM2SxD(3).DrpEnxS,
+ drpwe_in => AuroraDRPM2SxD(3).DrpWExS,
+ drpaddr_in => AuroraDRPM2SxD(3).DrpAddrxD,
+ drpdi_in => AuroraDRPM2SxD(3).DrpDIxD,
+ drprdy_out => AuroraDRPS2MxD(3).DrpRdyxS,
+ drpdo_out => AuroraDRPS2MxD(3).DrpDOxD);
+
+ end block AuroraGTPhyxB;
+
+end arch;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
index 22da748bd7c397b297602ad7f0a605d22703b089..631b2201e5dd582fdb70146677874aeee77568b0 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
@@ -77,7 +77,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.LAYERED_METADATA">undef</spirit:configurableElementValue>
@@ -245,7 +245,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_init_clk">125.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_lane_width">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_line_rate">50000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc_mode">IMM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_frequency">125000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rembuswidthselect">2</spirit:configurableElementValue>
@@ -272,7 +272,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">east_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dataflow_config">Duplex</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.drp_freq">125.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtquadcnt">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
@@ -364,7 +364,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">east_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRP_FREQ">125</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dataflow_Config">Duplex</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_COUPLING">AC</spirit:configurableElementValue>
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
index 7a42055b953eea1f6ecfd54b94620eab924df8a2..7222490407409a8a54072b3ca47b97b6f77dcb54 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
@@ -77,7 +77,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.LAYERED_METADATA">undef</spirit:configurableElementValue>
@@ -245,7 +245,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_init_clk">125.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_lane_width">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_line_rate">50000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc_mode">IMM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_frequency">125000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rembuswidthselect">2</spirit:configurableElementValue>
@@ -272,7 +272,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">north_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dataflow_config">Duplex</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.drp_freq">125.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtquadcnt">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
@@ -364,7 +364,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">north_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRP_FREQ">125</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dataflow_Config">Duplex</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_COUPLING">AC</spirit:configurableElementValue>
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
index f36f95fc4003e0a475847c1eb14b267d1e65a838..00a1133a1520f5562e1d9450c11fa654e74ead9a 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
@@ -77,7 +77,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.LAYERED_METADATA">undef</spirit:configurableElementValue>
@@ -245,7 +245,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_init_clk">125.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_lane_width">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_line_rate">50000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc_mode">IMM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_frequency">125000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rembuswidthselect">2</spirit:configurableElementValue>
@@ -272,7 +272,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">south_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dataflow_config">Duplex</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.drp_freq">125.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtquadcnt">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
@@ -364,7 +364,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">south_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRP_FREQ">125</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dataflow_Config">Duplex</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_COUPLING">AC</spirit:configurableElementValue>
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
index d226a8227ad3a61a3818c17d0e3298a75d6e12e5..99ec90d4c97656a1c2eae9f0f513143c2db38371 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
@@ -77,7 +77,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.LAYERED_METADATA">undef</spirit:configurableElementValue>
@@ -245,7 +245,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_init_clk">125.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_lane_width">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_line_rate">50000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc_mode">IMM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_frequency">125000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rembuswidthselect">2</spirit:configurableElementValue>
@@ -272,7 +272,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">west_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dataflow_config">Duplex</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.drp_freq">125.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtquadcnt">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
@@ -364,7 +364,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">west_channel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRP_FREQ">125</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dataflow_Config">Duplex</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_COUPLING">AC</spirit:configurableElementValue>
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
index b7bff2d8a315cdebbaea08f0058891f0315cbb22..a02841eeb5dff42a8d391297e4d17d797e8eed2f 100644
--- a/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: scalp_aurora_phy_rx_fifo
--
--- Last update: 2020-11-07
+-- Last update: 2020-11-18
--
---------------------------------------------------------------------------------
@@ -24,6 +24,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi4_pkg.all;
+use work.aurora_status_pkg.all;
entity scalp_aurora_phy_rx_fifo is
@@ -31,7 +32,7 @@ entity scalp_aurora_phy_rx_fifo is
-- Clocks and Reset
RXClkxCI : in std_ulogic;
TXClkxCI : in std_ulogic;
- RXRstxRANI : in std_ulogic;
+ RXRstxRANI : in t_rx_fifo_reset;
-- North
-- RX Data
NorthRXM2SxDI : in t_axi4m2s;
@@ -96,7 +97,7 @@ architecture arch of scalp_aurora_phy_rx_fifo is
signal RXClkxC : std_ulogic := '0';
signal TXClkxC : std_ulogic := '0';
- signal RXRstxRAN : std_ulogic := '0';
+ signal RXRstxRAN : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
-- North
signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal NorthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
@@ -163,7 +164,7 @@ begin
NorthAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
- s_axis_aresetn => RXRstxRAN,
+ s_axis_aresetn => RXRstxRAN.NorthxR,
s_axis_aclk => RXClkxC,
s_axis_tdata => NorthRXM2SxD.DataxD,
s_axis_tkeep => NorthRXM2SxD.KeepxD,
@@ -186,7 +187,7 @@ begin
EastAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
- s_axis_aresetn => RXRstxRAN,
+ s_axis_aresetn => RXRstxRAN.EastxR,
s_axis_aclk => RXClkxC,
s_axis_tdata => EastRXM2SxD.DataxD,
s_axis_tkeep => EastRXM2SxD.KeepxD,
@@ -209,7 +210,7 @@ begin
SouthAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
- s_axis_aresetn => RXRstxRAN,
+ s_axis_aresetn => RXRstxRAN.SouthxR,
s_axis_aclk => RXClkxC,
s_axis_tdata => SouthRXM2SxD.DataxD,
s_axis_tkeep => SouthRXM2SxD.KeepxD,
@@ -232,7 +233,7 @@ begin
WestAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
- s_axis_aresetn => RXRstxRAN,
+ s_axis_aresetn => RXRstxRAN.WestxR,
s_axis_aclk => RXClkxC,
s_axis_tdata => WestRXM2SxD.DataxD,
s_axis_tkeep => WestRXM2SxD.KeepxD,
diff --git a/ips/hw/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci b/ips/hw/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci
new file mode 100644
index 0000000000000000000000000000000000000000..2025e0c9c1a39d0f1de6cf25371ea17511c8f284
--- /dev/null
+++ b/ips/hw/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci
@@ -0,0 +1,833 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>vio_user_resets</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_BUSIF"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_RESET"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_OUT">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN106_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN107_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN108_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN109_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN10_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN110_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN111_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN112_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN113_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN114_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN115_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN116_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN117_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN118_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN119_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN11_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN120_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN121_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN122_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN123_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN124_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN125_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN126_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN127_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN128_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN129_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN12_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN130_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN131_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN132_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN133_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN134_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN135_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN136_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN137_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN138_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN139_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN13_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN140_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN141_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN142_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN143_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN144_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN145_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN146_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN147_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN148_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN149_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN14_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN150_WIDTH">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_user_resets</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_OUT4_INIT_VAL" xilinx:valueSource="user"/>
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+</spirit:design>
diff --git a/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
index 52f9349ed0544c0280ef4bc3b061b7d380ce45a2..d2a4046c5363ddea024cb275ee5e51fd4fb57ffd 100644
--- a/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
+++ b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: Control and status signals for the Aurora phy.
--
--- Last update: 2020-10-06
+-- Last update: 2020-11-25
--
---------------------------------------------------------------------------------
@@ -209,6 +209,87 @@ package aurora_status_pkg is
constant C_AURORA_NO_MASTER_LINK_RESET : t_aurora_master_link_reset := (SystemResetxR => (others => '0'),
LinkResetxR => (others => '0'));
+ type t_rx_fifo_reset is record
+ NorthxR : std_ulogic;
+ EastxR : std_ulogic;
+ SouthxR : std_ulogic;
+ WestxR : std_ulogic;
+ end record t_rx_fifo_reset;
+
+ constant C_NO_RX_FIFO_RESET : t_rx_fifo_reset := (NorthxR => '0',
+ EastxR => '0',
+ SouthxR => '0',
+ WestxR => '0');
+
+ constant C_SET_RX_FIFO_RESET : t_rx_fifo_reset := (NorthxR => '1',
+ EastxR => '1',
+ SouthxR => '1',
+ WestxR => '1');
+
+ type t_rx_back_pressure_reset is record
+ NorthxR : std_ulogic;
+ EastxR : std_ulogic;
+ SouthxR : std_ulogic;
+ WestxR : std_ulogic;
+ end record t_rx_back_pressure_reset;
+
+ constant C_NO_RX_BACK_PRESSURE_RESET : t_rx_back_pressure_reset := (NorthxR => '0',
+ EastxR => '0',
+ SouthxR => '0',
+ WestxR => '0');
+
+ constant C_SET_RX_BACK_PRESSURE_RESET : t_rx_back_pressure_reset := (NorthxR => '1',
+ EastxR => '1',
+ SouthxR => '1',
+ WestxR => '1');
+
+ type t_rx_reset is record
+ FifoResetxR : t_rx_fifo_reset;
+ BackPressureResetxR : t_rx_back_pressure_reset;
+ end record t_rx_reset;
+
+ constant C_NO_RX_RESET : t_rx_reset := (FifoResetxR => C_NO_RX_FIFO_RESET,
+ BackPressureResetxR => C_NO_RX_BACK_PRESSURE_RESET);
+
+ constant C_SET_RX_RESET : t_rx_reset := (FifoResetxR => C_SET_RX_FIFO_RESET,
+ BackPressureResetxR => C_SET_RX_BACK_PRESSURE_RESET);
+
+ type t_if_common_reset is record
+ NorthxR : std_ulogic;
+ EastxR : std_ulogic;
+ SouthxR : std_ulogic;
+ WestxR : std_ulogic;
+ end record t_if_common_reset;
+
+ constant C_NO_IF_COMMON_RESET : t_if_common_reset := (NorthxR => '0',
+ EastxR => '0',
+ SouthxR => '0',
+ WestxR => '0');
+
+ constant C_SET_IF_COMMON_RESET : t_if_common_reset := (NorthxR => '1',
+ EastxR => '1',
+ SouthxR => '1',
+ WestxR => '1');
+
+ type t_rx_fifo_reset_done is record
+ NorthxS : std_ulogic;
+ EastxS : std_ulogic;
+ SouthxS : std_ulogic;
+ WestxS : std_ulogic;
+ end record t_rx_fifo_reset_done;
+
+ constant C_NO_RX_FIFO_RESET_DONE : t_rx_fifo_reset_done := (NorthxS => '0',
+ EastxS => '0',
+ SouthxS => '0',
+ WestxS => '0');
+
+ constant C_SET_RX_FIFO_RESET_DONE : t_rx_fifo_reset_done := (NorthxS => '1',
+ EastxS => '1',
+ SouthxS => '1',
+ WestxS => '1');
+
+ type t_rx_fifo_reset_done_states is (E_RESET, E_WAIT_DONE, E_IS_DONE);
+
-- Functions
function std_bool (exp_in : in boolean) return std_ulogic;
diff --git a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
index 88e0033df01efd4afaebbd2a9823acaaeaa28a9d..5f8cca7a2c416796deabe799eab2bbd9953a642d 100644
--- a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
+++ b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: AXI4 format bus signals.
--
--- Last update: 2020-10-12
+-- Last update: 2020-11-25
--
---------------------------------------------------------------------------------
@@ -131,6 +131,67 @@ package axi4_pkg is
ValidxS => '0');
constant C_NO_AXI4_NFC_S2M : t_axi4nfcs2m := (ReadyxS => '0');
+ -- NFC Codes
+ constant C_NFC_XON : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ constant C_NFC_XOFF : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '1');
+
+ type t_nfc_states is (C_NFC_IDLE, C_NFC_IS_XON, C_NFC_IS_XOFF, C_NFC_SEND_XON, C_NFC_SEND_XOFF);
+
+ -- Axis Fifo Status
+ type t_axi4fifo_status is record
+ WrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ ProgEmptyxS : std_ulogic;
+ ProgFullxS : std_ulogic;
+ end record t_axi4fifo_status;
+
+ constant C_NO_AXI4_FIFO_STATUS : t_axi4fifo_status := (WrDataCntxD => (others => '0'),
+ RdDataCntxD => (others => '0'),
+ ProgEmptyxS => '0',
+ ProgFullxS => '0');
+
+ -- Axis Fifo Error Counter
+ type t_axi4fifo_error is record
+ NorthCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ EastCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ SouthCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ WestCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ end record t_axi4fifo_error;
+
+ constant C_NO_AXI4_FIFO_ERROR : t_axi4fifo_error := (NorthCounterxD => (others => '0'),
+ EastCounterxD => (others => '0'),
+ SouthCounterxD => (others => '0'),
+ WestCounterxD => (others => '0'));
+
+ -- Native Fifo for Scalp packets
+ type t_native_fifo_slave is record
+ DataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ WrEnxS : std_ulogic;
+ RdEnxS : std_ulogic;
+ end record t_native_fifo_slave;
+
+ constant C_NO_NATIVE_FIFO_SLAVE : t_native_fifo_slave := (DataxD => (others => '0'),
+ WrEnxS => '0',
+ RdEnxS => '0');
+
+ type t_native_fifo_master is record
+ DataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ FullxS : std_ulogic;
+ EmptyxS : std_ulogic;
+ AlmostFullxS : std_ulogic;
+ AlmostEmptyxS : std_ulogic;
+ WrRstBusyxS : std_ulogic;
+ RdRstBusyxS : std_ulogic;
+ end record t_native_fifo_master;
+
+ constant C_NO_NATIVE_FIFO_MASTER : t_native_fifo_master := (DataxD => (others => '0'),
+ FullxS => '0',
+ EmptyxS => '0',
+ AlmostFullxS => '0',
+ AlmostEmptyxS => '0',
+ WrRstBusyxS => '0',
+ RdRstBusyxS => '0');
+
-- AXI4 Functions
-- OR reduce from t_axi4s2m_vector
function or_reduce_t_axi4s2m_vector (
diff --git a/tools/config/scalp_aurora_phy_rx_fifo.json b/tools/config/scalp_aurora_phy_rx_fifo.json
index 56c29acf823e0602249b989e36284e308a61884f..5766126fdef4406e6170357756166c5df974293c 100644
--- a/tools/config/scalp_aurora_phy_rx_fifo.json
+++ b/tools/config/scalp_aurora_phy_rx_fifo.json
@@ -16,7 +16,7 @@
"board_name" : "SCALP"
},
"components" : {
- "packages" : {
+ "packages" : {
"axi4_pkg" : "enable"
},
"ips" : {
diff --git a/tools/config/scalp_axi4lite.json b/tools/config/scalp_axi4lite.json
new file mode 100644
index 0000000000000000000000000000000000000000..0d1c171f5a6a9817c289bcfad68ca34424068a50
--- /dev/null
+++ b/tools/config/scalp_axi4lite.json
@@ -0,0 +1,31 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch"
+ },
+ "project" : {
+ "name" : "scalp_axi4lite",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "IPS",
+ "vivado_version" : "2019.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "SCALP"
+ },
+ "components" : {
+ "packages" : {
+ "axi4_pkg" : "enable"
+ },
+ "ips" : {
+ "scalp_axi4lite" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ }
+ }
+ }
+ }
+}
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
index ea992d0d8ef7a4dd1a598f0f993c689935afd5d4..3b4cf266a72ed1d633c3fb6368d92abc4e47a9fc 100644
--- a/tools/config/scalp_firmware.json
+++ b/tools/config/scalp_firmware.json
@@ -40,6 +40,13 @@
"west_channel" : "enable"
}
},
+ "scalp_aurora_phy_rx_fifo" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "axis_data_fifo" : "enable"
+ }
+ },
"scalp_design_aurora_clk" : {
"hdl" : "disable",
"xci" : {
@@ -49,9 +56,17 @@
"scalp_design_debug" : {
"hdl" : "disable",
"xci" : {
- "data_counter" : "enable",
- "vio_axi_cnt_ctrl" : "enable",
- "vio_status" : "enable"
+ "data_counter" : "disable",
+ "vio_axi_cnt_ctrl" : "disable",
+ "vio_status" : "enable",
+ "vio_user_resets" : "enable"
+ }
+ },
+ "scalp_packet_fifo_wrapper" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "scalp_packet_fifo" : "enable"
}
}
}
diff --git a/tools/config/scalp_packet_fifo_wrapper.json b/tools/config/scalp_packet_fifo_wrapper.json
new file mode 100644
index 0000000000000000000000000000000000000000..01437c76fde1832004878acf74f71e7b126f7f8a
--- /dev/null
+++ b/tools/config/scalp_packet_fifo_wrapper.json
@@ -0,0 +1,32 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch"
+ },
+ "project" : {
+ "name" : "scalp_packet_fifo_wrapper",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "IPS",
+ "vivado_version" : "2019.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "SCALP"
+ },
+ "components" : {
+ "packages" : {
+ "axi4_pkg" : "enable"
+ },
+ "ips" : {
+ "scalp_packet_fifo_wrapper" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "scalp_packet_fifo" : "enable"
+ }
+ }
+ }
+ }
+}