diff --git a/tools/config/scalp_aurora_phy.json b/tools/config/scalp_aurora_phy.json
index 06c46fed7e53561ad384e5371cbf58bda086acbb..ec66ad737e644999ce54b9e0e2395ef385d6d9e0 100644
--- a/tools/config/scalp_aurora_phy.json
+++ b/tools/config/scalp_aurora_phy.json
@@ -20,6 +20,18 @@
             "aurora_drp_pkg"    : "enable",
             "aurora_status_pkg" : "enable",
             "axi4_pkg"          : "enable"
-        }
+        },
+        "ips" : {
+            "scalp_aurora_phy" :
+            {
+                "hdl" : "enable",
+                "xci" : {
+                    "east_channel"  : "enable",
+                    "north_channel" : "enable",
+                    "south_channel" : "enable",
+                    "west_channel"  : "enable"
+                }
+            }
+        }        
     }
 }
diff --git a/tools/config/scalp_design_aurora_clk.json b/tools/config/scalp_design_aurora_clk.json
new file mode 100644
index 0000000000000000000000000000000000000000..bbab62e672180e0815e84e8071fd4079e0f0e4eb
--- /dev/null
+++ b/tools/config/scalp_design_aurora_clk.json
@@ -0,0 +1,29 @@
+{
+    "author" : {
+        "name"  : "Joachim Schmidt",
+        "email" : "<joachim.schmidt@hesge.ch"
+    },
+    "project" : {
+        "name"            : "scalp_design_aurora_clk",
+        "type"            : "COMP_PRJ_TYPE",
+        "category"        : "IPS",
+        "vivado_version"  : "2019.2",
+        "target_language" : "VHDL",
+        "vhdl_version"    : "VHDL 2008"
+    },
+    "hardware" : {
+        "part_name"  : "xc7z015clg485-2",
+        "board_name" : "SCALP"
+    },
+    "components" : {
+        "ips" : {
+            "scalp_design_aurora_clk" :
+            {
+                "hdl" : "enable",
+                "xci" : {
+                    "scalp_aurora_clk" : "enable"
+                }
+            }
+        }        
+    }
+}
diff --git a/tools/config/scalp_design_debug.json b/tools/config/scalp_design_debug.json
new file mode 100644
index 0000000000000000000000000000000000000000..513efe73513eaa0151a80335020f48bd703bb6b0
--- /dev/null
+++ b/tools/config/scalp_design_debug.json
@@ -0,0 +1,31 @@
+{
+    "author" : {
+        "name"  : "Joachim Schmidt",
+        "email" : "<joachim.schmidt@hesge.ch"
+    },
+    "project" : {
+        "name"            : "scalp_design_debug",
+        "type"            : "COMP_PRJ_TYPE",
+        "category"        : "IPS",
+        "vivado_version"  : "2019.2",
+        "target_language" : "VHDL",
+        "vhdl_version"    : "VHDL 2008"
+    },
+    "hardware" : {
+        "part_name"  : "xc7z015clg485-2",
+        "board_name" : "SCALP"
+    },
+    "components" : {
+        "ips" : {
+            "scalp_design_debug" :
+            {
+                "hdl" : "enable",
+                "xci" : {
+                    "data_counter"     : "enable",
+                    "vio_axi_cnt_ctrl" : "enable",
+                    "vio_status"       : "enable"
+                }
+            }
+        }        
+    }
+}
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
index b57d97c0b7374db673d72b9b1a3cd5314ba40aff..ea992d0d8ef7a4dd1a598f0f993c689935afd5d4 100644
--- a/tools/config/scalp_firmware.json
+++ b/tools/config/scalp_firmware.json
@@ -29,6 +29,31 @@
         },
         "soc" : {
             "scalp_zynqps" : "enable"
+        },
+        "ips" : {
+            "scalp_aurora_phy" : {
+                "hdl" : "enable",
+                "xci" : {
+                    "east_channel"  : "enable",
+                    "north_channel" : "enable",
+                    "south_channel" : "enable",
+                    "west_channel"  : "enable"
+                }
+            },
+            "scalp_design_aurora_clk" : {
+                "hdl" : "disable",
+                "xci" : {
+                    "scalp_aurora_clk" : "enable"
+                }
+            },
+            "scalp_design_debug" : {
+                "hdl" : "disable",
+                "xci" : {
+                    "data_counter"     : "enable",
+                    "vio_axi_cnt_ctrl" : "enable",
+                    "vio_status"       : "enable"
+                }
+            }
         }
     }
 }