From 77f1ab17860a8e00295932be69a67b1bebc5429b Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Tue, 13 Oct 2020 13:41:23 +0200
Subject: [PATCH] Added and modified new JSON configuration files.
---
tools/config/scalp_aurora_phy.json | 14 +++++++++-
tools/config/scalp_design_aurora_clk.json | 29 +++++++++++++++++++++
tools/config/scalp_design_debug.json | 31 +++++++++++++++++++++++
tools/config/scalp_firmware.json | 25 ++++++++++++++++++
4 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644 tools/config/scalp_design_aurora_clk.json
create mode 100644 tools/config/scalp_design_debug.json
diff --git a/tools/config/scalp_aurora_phy.json b/tools/config/scalp_aurora_phy.json
index 06c46fe..ec66ad7 100644
--- a/tools/config/scalp_aurora_phy.json
+++ b/tools/config/scalp_aurora_phy.json
@@ -20,6 +20,18 @@
"aurora_drp_pkg" : "enable",
"aurora_status_pkg" : "enable",
"axi4_pkg" : "enable"
- }
+ },
+ "ips" : {
+ "scalp_aurora_phy" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "east_channel" : "enable",
+ "north_channel" : "enable",
+ "south_channel" : "enable",
+ "west_channel" : "enable"
+ }
+ }
+ }
}
}
diff --git a/tools/config/scalp_design_aurora_clk.json b/tools/config/scalp_design_aurora_clk.json
new file mode 100644
index 0000000..bbab62e
--- /dev/null
+++ b/tools/config/scalp_design_aurora_clk.json
@@ -0,0 +1,29 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch"
+ },
+ "project" : {
+ "name" : "scalp_design_aurora_clk",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "IPS",
+ "vivado_version" : "2019.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "SCALP"
+ },
+ "components" : {
+ "ips" : {
+ "scalp_design_aurora_clk" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "scalp_aurora_clk" : "enable"
+ }
+ }
+ }
+ }
+}
diff --git a/tools/config/scalp_design_debug.json b/tools/config/scalp_design_debug.json
new file mode 100644
index 0000000..513efe7
--- /dev/null
+++ b/tools/config/scalp_design_debug.json
@@ -0,0 +1,31 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch"
+ },
+ "project" : {
+ "name" : "scalp_design_debug",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "IPS",
+ "vivado_version" : "2019.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "SCALP"
+ },
+ "components" : {
+ "ips" : {
+ "scalp_design_debug" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "data_counter" : "enable",
+ "vio_axi_cnt_ctrl" : "enable",
+ "vio_status" : "enable"
+ }
+ }
+ }
+ }
+}
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
index b57d97c..ea992d0 100644
--- a/tools/config/scalp_firmware.json
+++ b/tools/config/scalp_firmware.json
@@ -29,6 +29,31 @@
},
"soc" : {
"scalp_zynqps" : "enable"
+ },
+ "ips" : {
+ "scalp_aurora_phy" : {
+ "hdl" : "enable",
+ "xci" : {
+ "east_channel" : "enable",
+ "north_channel" : "enable",
+ "south_channel" : "enable",
+ "west_channel" : "enable"
+ }
+ },
+ "scalp_design_aurora_clk" : {
+ "hdl" : "disable",
+ "xci" : {
+ "scalp_aurora_clk" : "enable"
+ }
+ },
+ "scalp_design_debug" : {
+ "hdl" : "disable",
+ "xci" : {
+ "data_counter" : "enable",
+ "vio_axi_cnt_ctrl" : "enable",
+ "vio_status" : "enable"
+ }
+ }
}
}
}
--
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