diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
index 9bc9bba4ed461ba4dfe3e59f007b5baf62a3a071..7d608d02cd8553f297e9d6e792c2dfd38f7204e5 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Cleanup project directory
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
index a54cdbdbb40cad756113644bafcd723035b46089..b8f05723478981732e586ee9cfe6583b77802317 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Create Vivado project
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
index 2e61ff48014c713df71ccd053dfb1c45bf3b8e5e..76733a1ea5f1cc584c47ea1d1aa9f849ee03b0f2 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware'
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
@@ -65,15 +65,21 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
- add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
- add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
- add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
- #add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file
+ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
+ add_files -norecurse $vhdl_ips_file_list
+ foreach j $vhdl_ips_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
@@ -81,6 +87,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
+ read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
@@ -153,29 +160,6 @@ foreach j $vhdl_sim_file_list {
print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
- set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
- add_files -norecurse $vhdl_pkg_file_list
- foreach j $vhdl_pkg_file_list {
- set_property file_type {VHDL 2008} [get_files $j]
- print_status "VHDL 2008 mode configured for the file $j" "OK"
- set_property is_enabled true [get_files $j]
- }
- set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
- add_files -norecurse $vhdl_pkg_file_list
- foreach j $vhdl_pkg_file_list {
- set_property file_type {VHDL 2008} [get_files $j]
- print_status "VHDL 2008 mode configured for the file $j" "OK"
- set_property is_enabled true [get_files $j]
- }
- set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
- add_files -norecurse $vhdl_pkg_file_list
- foreach j $vhdl_pkg_file_list {
- set_property file_type {VHDL 2008} [get_files $j]
- print_status "VHDL 2008 mode configured for the file $j" "OK"
- set_property is_enabled true [get_files $j]
- }
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
@@ -197,20 +181,10 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
-}
print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK"
# Add SoC wrapper sources files
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
- set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
- add_files -norecurse $vhdl_soc_file_list
- foreach j $vhdl_soc_file_list {
- set_property file_type {VHDL 2008} [get_files $j]
- print_status "VHDL 2008 mode configured for the file $j" "OK"
- set_property is_enabled true [get_files $j]
- }
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
add_files -norecurse $vhdl_soc_file_list
foreach j $vhdl_soc_file_list {
@@ -218,7 +192,6 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
-}
print_status "Add SoC wrapper sources" "OK"
print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
index c603ed6d669e53b4f776e867f4fd2441a956ab0f..909d5734b09ed25be42158f1d480839ac8d6e256 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
index aa1d99c074dbfe6391a0fe82a542811956f017cd..a6d1f8bf6c29e7a61bbb57c90c4aca542245f4ad 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
index cea75de4d34d5ca84e7bad16182fc3f597b21450..378e1567c9eb8e4db2daba31a2c6658fe9d0a287 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Generate bitstream file
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
index bd726a00e30087802e09ac7704dc5f5d0af135ab..0b38b88c289475ae015e91839c496df2ee2ddc6a 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: TCL script used to generate bitstream file
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
index 10bf21bc64dbbf764fffa4ece6918cd4070ae6c2..2160b2fdc8e8396bca50286d4ab9658040ac9dbb 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Generate software application
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
index 0c4f3b4fd7cd790125b522907389d94fb5b7a422..99251d420e50a1f21b00ed6b48e786fac914e8c7 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: TCL script used to generate software application
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
index 442fe094a95c29872b8a754f91d011267f309992..577b49ef88e7b1c99eefff20ec04d577ce7e1b8f 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Load bitstream file
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
index a31e59d3b1b86ad0762eff4058be900c39843527..28e9e47a4d761d134400956118b6db5891ff5a91 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script used to load FPGA bitstream
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
index adc47441de30f13d4c3b8b3353ee50e84f364b60..07e5eb037e7f5420f53c67ba75df53f352a0bf22 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Load software application
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
index 40aeca5cdfc0ff81cf0e9f6751f3520f752f4a38..82206c5eaceec41fadfcf9d83276045e128d1758 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script used to load software application
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
index 80625ab9d17456394f305d9baa4e1c7540ca80e2..98c24899530d27f9eb0390725486c6a77367a398 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Create Vivado project
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
index 42d656f60e0c7f452f552bc14b02844d05982140..e6fb3e933f51f8681f077232529865e2fbd06ee8 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Project management utilities
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh b/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
index b7677afbcad154801e4d09e5283939611374c93e..ac7f44dd6a0c7607282ddd094a73f0d0924ec635 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
index 115fb1259c5070990163399c19260aa2a0f8d5b0..eeb0b8388dbcf2fba8aa515c005f858227e87c78 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: scalp_firmware
--
--- Last update: 2020-10-13
+-- Last update: 2020-11-07
--
---------------------------------------------------------------------------------
@@ -316,6 +316,18 @@ architecture arch of scalp_firmware is
WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ NorthRXNFCM2SxDO : out t_axi4nfcm2s;
+ NorthTXNFCM2SxDI : in t_axi4nfcm2s;
+ NorthTXNFCS2MxDO : out t_axi4nfcs2m;
+ EastRXNFCM2SxDO : out t_axi4nfcm2s;
+ EastTXNFCM2SxDI : in t_axi4nfcm2s;
+ EastTXNFCS2MxDO : out t_axi4nfcs2m;
+ SouthRXNFCM2SxDO : out t_axi4nfcm2s;
+ SouthTXNFCM2SxDI : in t_axi4nfcm2s;
+ SouthTXNFCS2mxDO : out t_axi4nfcs2m;
+ WestRXNFCM2SxDO : out t_axi4nfcm2s;
+ WestTXNFCM2SxDI : in t_axi4nfcm2s;
+ WestTXNFCS2MxDO : out t_axi4nfcs2m;
AuroraCtrlxDI : in t_aurora_control;
AuroraStatusxDO : out t_aurora_status;
AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
@@ -325,58 +337,86 @@ architecture arch of scalp_firmware is
-- Signals
-- Clocks
-- Processing system clock
- signal PSSysClkxC : std_logic := '0';
+ signal PSSysClkxC : std_logic := '0';
-- GTP Clocks
-- signal GTPRefClk0xC : std_logic := '0';
-- signal GTPRefClk1xC : std_logic := '0';
- signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
- signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
-- Resets
-- Processing system reset
- signal PSSysResetxR : std_logic := '0';
+ signal PSSysResetxR : std_logic := '0';
-- Scalp Aurora Phy
- signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
- signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
- signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
- signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
- signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
- signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
- signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
- signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
+ signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
+ signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
+ signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
+ signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
+ signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
+ signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
+ signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal NorthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal EastFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal SouthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal WestFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
-- Attributes
attribute mark_debug : string;
@@ -596,6 +636,23 @@ begin
WestRXUFCM2SxDO => WestRXUFCM2SxD,
WestTXUFCM2SxDI => WestTXUFCM2SxD,
WestTXUFCS2MxDO => WestTXUFCS2MxD,
+ -- Axi4 Framing NFC Interface
+ -- North
+ NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
+ NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
+ NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
+ -- East
+ EastRXNFCM2SxDO => EastRXNFCM2SxD,
+ EastTXNFCM2SxDI => EastTXNFCM2SxD,
+ EastTXNFCS2MxDO => EastTXNFCS2MxD,
+ -- South
+ SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
+ SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
+ SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
+ -- West
+ WestRXNFCM2SxDO => WestRXNFCM2SxD,
+ WestTXNFCM2SxDI => WestTXNFCM2SxD,
+ WestTXNFCS2MxDO => WestTXNFCS2MxD,
-- Aurora Ctrl + Status
AuroraCtrlxDI => AuroraCtrlxD,
AuroraStatusxDO => AuroraStatusxD,
@@ -603,6 +660,340 @@ begin
AuroraDRPM2SxDI => (others => C_NO_DRP_M2S),
AuroraDRPS2MxDO => open);
+ RXFifoxB : block is
+
+ signal RXFifoRstxRAN : std_ulogic := '0';
+
+ begin -- block RXFifoxB
+
+ RXFifoRstxAS : RXFifoRstxRAN <= not AuroraClkMasterxC.PllNotLockedxS;
+
+ ScalpAuroraPhyRXFifoxI : entity work.scalp_aurora_phy_rx_fifo
+ port map (
+ -- Clocks and reset
+ RXClkxCI => AuroraClkMasterxC.UserClkxC,
+ TXClkxCI => AuroraClkMasterxC.UserClkxC,
+ RXRstxRANI => RXFifoRstxRAN,
+ -- North
+ -- Fifo RX Side
+ NorthRXM2SxDI => NorthRXM2SxD,
+ NorthRXS2MxDO => NorthRXFromFifoS2MxD,
+ -- Fifo TX Side
+ NorthTXM2SxDO => NorthRXfromPhyTXfromFifoM2SxD,
+ NorthTXS2MxDI => NorthRXfromPhyTXfromFifoS2MxD,
+ NorthFifoStatusxDO => NorthFifoStatusxD,
+ -- East
+ -- Fifo RX Side
+ EastRXM2SxDI => EastRXM2SxD,
+ EastRXS2MxDO => EastRXFromFifoS2MxD,
+ -- Fifo TX Side
+ EastTXM2SxDO => EastRXfromPhyTXfromFifoM2SxD,
+ EastTXS2MxDI => EastRXfromPhyTXfromFifoS2MxD,
+ EastFifoStatusxDO => EastFifoStatusxD,
+ -- South
+ -- Fifo RX Side
+ SouthRXM2SxDI => SouthRXM2SxD,
+ SouthRXS2MxDO => SouthRXFromFifoS2MxD,
+ -- Fifo TX Side
+ SouthTXM2SxDO => SouthRXfromPhyTXfromFifoM2SxD,
+ SouthTXS2MxDI => SouthRXfromPhyTXfromFifoS2MxD,
+ SouthFifoStatusxDO => SouthFifoStatusxD,
+ -- West
+ -- Fifo RX Side
+ WestRXM2SxDI => WestRXM2SxD,
+ WestRXS2MxDO => WestRXFromFifoS2MxD,
+ -- Fifo TX Side
+ WestTXM2SxDO => WestRXfromPhyTXfromFifoM2SxD,
+ WestTXS2MxDI => WestRXfromPhyTXfromFifoS2MxD,
+ WestFifoStatusxDO => WestFifoStatusxD);
+
+ end block RXFifoxB;
+
+ BackPressurexB : block is
+
+ signal NorthSendXOFFxSN : std_ulogic := '0';
+ signal NorthSendXOFFxSP : std_ulogic := '0';
+ signal EastSendXOFFxSN : std_ulogic := '0';
+ signal EastSendXOFFxSP : std_ulogic := '0';
+ signal SouthSendXOFFxSN : std_ulogic := '0';
+ signal SouthSendXOFFxSP : std_ulogic := '0';
+ signal WestSendXOFFxSN : std_ulogic := '0';
+ signal WestSendXOFFxSP : std_ulogic := '0';
+ -- North
+ signal NorthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal NorthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal NorthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthNFCValidxSN : std_ulogic := '0';
+ signal NorthNFCValidxSP : std_ulogic := '0';
+ -- East
+ signal EastNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal EastNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal EastNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastNFCValidxSN : std_ulogic := '0';
+ signal EastNFCValidxSP : std_ulogic := '0';
+ -- South
+ signal SouthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal SouthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal SouthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthNFCValidxSN : std_ulogic := '0';
+ signal SouthNFCValidxSP : std_ulogic := '0';
+ -- West
+ signal WestNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal WestNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal WestNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestNFCValidxSN : std_ulogic := '0';
+ signal WestNFCValidxSP : std_ulogic := '0';
+
+ begin -- block BackPressurexB
+
+ NorthSendXONxAS : NorthSendXOFFxSN <= '1' when
+ (NorthRXFromFifoS2MxD.ReadyxS = '0') or
+ (NorthFifoStatusxD.ProgFullxS = '1') else
+ '0';
+ EastSendXONxAS : EastSendXOFFxSN <= '1' when
+ (EastRXFromFifoS2MxD.ReadyxS = '0') or
+ (EastFifoStatusxD.ProgFullxS = '1') else
+ '0';
+ SouthSendXONxAS : SouthSendXOFFxSN <= '1' when
+ (SouthRXFromFifoS2MxD.ReadyxS = '0') or
+ (SouthFifoStatusxD.ProgFullxS = '1') else
+ '0';
+ WestSendXONxAS : WestSendXOFFxSN <= '1' when
+ (WestRXFromFifoS2MxD.ReadyxS = '0') or
+ (WestFifoStatusxD.ProgFullxS = '1') else
+ '0';
+ -- NFC Data and valid signals
+ NorthNFCDataxAS : NorthTXNFCM2SxD.DataxD <= NorthNFCDataxDP;
+ NorthNFCValidxAS : NorthTXNFCM2SxD.ValidxS <= NorthNFCValidxSP;
+ EastNFCDataxAS : EastTXNFCM2SxD.DataxD <= EastNFCDataxDP;
+ EastNFCValidxAS : EastTXNFCM2SxD.ValidxS <= EastNFCValidxSP;
+ SouthNFCDataxAS : SouthTXNFCM2SxD.DataxD <= SouthNFCDataxDP;
+ SouthNFCValidxAS : SouthTXNFCM2SxD.ValidxS <= SouthNFCValidxSP;
+ WestNFCDataxAS : WestTXNFCM2SxD.DataxD <= WestNFCDataxDP;
+ WestNFCValidxAS : WestTXNFCM2SxD.ValidxS <= WestNFCValidxSP;
+
+ UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
+ AuroraClkMasterxC.UserClkxC) is
+ begin -- process UpdateRegxP
+ if not AuroraClkMasterxC.PllNotLockedxS then
+ NorthSendXOFFxSP <= '0';
+ EastSendXOFFxSP <= '0';
+ SouthSendXOFFxSP <= '0';
+ WestSendXOFFxSP <= '0';
+ NorthNFCStatexDP <= C_NFC_IDLE;
+ NorthNFCDataxDP <= (others => '0');
+ NorthNFCValidxSP <= '0';
+ EastNFCStatexDP <= C_NFC_IDLE;
+ EastNFCDataxDP <= (others => '0');
+ EastNFCValidxSP <= '0';
+ SouthNFCStatexDP <= C_NFC_IDLE;
+ SouthNFCDataxDP <= (others => '0');
+ SouthNFCValidxSP <= '0';
+ WestNFCStatexDP <= C_NFC_IDLE;
+ WestNFCDataxDP <= (others => '0');
+ WestNFCValidxSP <= '0';
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ NorthSendXOFFxSP <= NorthSendXOFFxSN;
+ EastSendXOFFxSP <= EastSendXOFFxSN;
+ SouthSendXOFFxSP <= SouthSendXOFFxSN;
+ WestSendXOFFxSP <= WestSendXOFFxSN;
+ NorthNFCStatexDP <= NorthNFCStatexDN;
+ NorthNFCDataxDP <= NorthNFCDataxDN;
+ NorthNFCValidxSP <= NorthNFCValidxSN;
+ EastNFCStatexDP <= EastNFCStatexDN;
+ EastNFCDataxDP <= EastNFCDataxDN;
+ EastNFCValidxSP <= EastNFCValidxSN;
+ SouthNFCStatexDP <= SouthNFCStatexDN;
+ SouthNFCDataxDP <= SouthNFCDataxDN;
+ SouthNFCValidxSP <= SouthNFCValidxSN;
+ WestNFCStatexDP <= WestNFCStatexDN;
+ WestNFCDataxDP <= WestNFCDataxDN;
+ WestNFCValidxSP <= WestNFCValidxSN;
+ end if;
+ end process UpdateRegxP;
+
+ NorthNFCStatexP : process (NorthNFCDataxDP, NorthNFCStatexDP,
+ NorthNFCValidxSP, NorthSendXOFFxSN,
+ NorthSendXOFFxSP,
+ NorthTXUFCS2MxD.ReadyxS) is
+ begin -- process NorthNFCStatexP
+ -- Default values
+ NorthNFCStatexDN <= NorthNFCStatexDP;
+ NorthNFCDataxDN <= NorthNFCDataxDP;
+ NorthNFCValidxSN <= NorthNFCValidxSP;
+
+ case NorthNFCStatexDP is
+ when C_NFC_IDLE =>
+ NorthNFCStatexDN <= C_NFC_IS_XON;
+ when C_NFC_IS_XON =>
+ if NorthSendXOFFxSP = '0' and NorthSendXOFFxSN = '1' then
+ NorthNFCDataxDN <= C_NFC_XOFF;
+ NorthNFCValidxSN <= '1';
+ NorthNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if NorthSendXOFFxSP = '1' and NorthSendXOFFxSN = '0' then
+ NorthNFCDataxDN <= C_NFC_XON;
+ NorthNFCValidxSN <= '1';
+ NorthNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if NorthTXUFCS2MxD.ReadyxS = '1' then
+ NorthNFCValidxSN <= '0';
+ NorthNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if NorthTXUFCS2MxD.ReadyxS = '1' then
+ NorthNFCValidxSN <= '0';
+ NorthNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process NorthNFCStatexP;
+
+ EastNFCStatexP : process (EastNFCDataxDP, EastNFCStatexDP,
+ EastNFCValidxSP, EastSendXOFFxSN,
+ EastSendXOFFxSP,
+ EastTXUFCS2MxD.ReadyxS) is
+ begin -- process EastNFCStatexP
+ -- Default values
+ EastNFCStatexDN <= EastNFCStatexDP;
+ EastNFCDataxDN <= EastNFCDataxDP;
+ EastNFCValidxSN <= EastNFCValidxSP;
+
+ case EastNFCStatexDP is
+ when C_NFC_IDLE =>
+ EastNFCStatexDN <= C_NFC_IS_XON;
+ when C_NFC_IS_XON =>
+ if EastSendXOFFxSP = '0' and EastSendXOFFxSN = '1' then
+ EastNFCDataxDN <= C_NFC_XOFF;
+ EastNFCValidxSN <= '1';
+ EastNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if EastSendXOFFxSP = '1' and EastSendXOFFxSN = '0' then
+ EastNFCDataxDN <= C_NFC_XON;
+ EastNFCValidxSN <= '1';
+ EastNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if EastTXUFCS2MxD.ReadyxS = '1' then
+ EastNFCValidxSN <= '0';
+ EastNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if EastTXUFCS2MxD.ReadyxS = '1' then
+ EastNFCValidxSN <= '0';
+ EastNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process EastNFCStatexP;
+
+ SouthNFCStatexP : process (SouthNFCDataxDP, SouthNFCStatexDP,
+ SouthNFCValidxSP, SouthSendXOFFxSN,
+ SouthSendXOFFxSP,
+ SouthTXUFCS2MxD.ReadyxS) is
+ begin -- process SouthNFCStatexP
+ -- Default values
+ SouthNFCStatexDN <= SouthNFCStatexDP;
+ SouthNFCDataxDN <= SouthNFCDataxDP;
+ SouthNFCValidxSN <= SouthNFCValidxSP;
+
+ case SouthNFCStatexDP is
+ when C_NFC_IDLE =>
+ SouthNFCStatexDN <= C_NFC_IS_XON;
+ when C_NFC_IS_XON =>
+ if SouthSendXOFFxSP = '0' and SouthSendXOFFxSN = '1' then
+ SouthNFCDataxDN <= C_NFC_XOFF;
+ SouthNFCValidxSN <= '1';
+ SouthNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if SouthSendXOFFxSP = '1' and SouthSendXOFFxSN = '0' then
+ SouthNFCDataxDN <= C_NFC_XON;
+ SouthNFCValidxSN <= '1';
+ SouthNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if SouthTXUFCS2MxD.ReadyxS = '1' then
+ SouthNFCValidxSN <= '0';
+ SouthNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if SouthTXUFCS2MxD.ReadyxS = '1' then
+ SouthNFCValidxSN <= '0';
+ SouthNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process SouthNFCStatexP;
+
+ WestNFCStatexP : process (WestNFCDataxDP, WestNFCStatexDP,
+ WestNFCValidxSP, WestSendXOFFxSN,
+ WestSendXOFFxSP,
+ WestTXUFCS2MxD.ReadyxS) is
+ begin -- process WestNFCStatexP
+ -- Default values
+ WestNFCStatexDN <= WestNFCStatexDP;
+ WestNFCDataxDN <= WestNFCDataxDP;
+ WestNFCValidxSN <= WestNFCValidxSP;
+
+ case WestNFCStatexDP is
+ when C_NFC_IDLE =>
+ WestNFCStatexDN <= C_NFC_IS_XON;
+ when C_NFC_IS_XON =>
+ if WestSendXOFFxSP = '0' and WestSendXOFFxSN = '1' then
+ WestNFCDataxDN <= C_NFC_XOFF;
+ WestNFCValidxSN <= '1';
+ WestNFCStatexDN <= C_NFC_SEND_XOFF;
+ end if;
+
+ when C_NFC_IS_XOFF =>
+ if WestSendXOFFxSP = '1' and WestSendXOFFxSN = '0' then
+ WestNFCDataxDN <= C_NFC_XON;
+ WestNFCValidxSN <= '1';
+ WestNFCStatexDN <= C_NFC_SEND_XON;
+ end if;
+
+ when C_NFC_SEND_XON =>
+ if WestTXUFCS2MxD.ReadyxS = '1' then
+ WestNFCValidxSN <= '0';
+ WestNFCStatexDN <= C_NFC_IS_XON;
+ end if;
+
+ when C_NFC_SEND_XOFF =>
+ if WestTXUFCS2MxD.ReadyxS = '1' then
+ WestNFCValidxSN <= '0';
+ WestNFCStatexDN <= C_NFC_IS_XOFF;
+ end if;
+
+ when others => null;
+ end case;
+
+ end process WestNFCStatexP;
+
+ end block BackPressurexB;
+
end block GTPhyxB;
DebugxB : block is
@@ -646,20 +1037,20 @@ begin
port map (
clk => AuroraClkMasterxC.UserClkxC,
-- North
- probe_in0 => NorthRXM2SxD.DataxD, -- 32 bits
- probe_in1(0) => NorthRXM2SxD.ValidxS,
+ probe_in0 => NorthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ probe_in1(0) => NorthRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in2(0) => NorthTXS2MxD.ReadyxS,
-- East
- probe_in3 => EastRXM2SxD.DataxD, -- 32 bits
- probe_in4(0) => EastRXM2SxD.ValidxS,
+ probe_in3 => EastRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ probe_in4(0) => EastRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in5(0) => EastTXS2MxD.ReadyxS,
-- South
- probe_in6 => SouthRXM2SxD.DataxD, -- 32 bits
- probe_in7(0) => SouthRXM2SxD.ValidxS,
+ probe_in6 => SouthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ probe_in7(0) => SouthRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in8(0) => SouthTXS2MxD.ReadyxS,
-- West
- probe_in9 => WestRXM2SxD.DataxD, -- 32 bits
- probe_in10(0) => WestRXM2SxD.ValidxS,
+ probe_in9 => WestRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ probe_in10(0) => WestRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in11(0) => WestTXS2MxD.ReadyxS,
probe_out0(0) => CntRstxR);
diff --git a/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
index 4ea6692de409321a3372c3ac4f257a163ddb7da9..47f1aa0e7ea7841a73e7249594d8876f055bc2b5 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: Testbench for scalp_firmware
--
--- Last update: 2020-10-13 13:10:02
+-- Last update: 2020-11-07 09:14:14
--
---------------------------------------------------------------------------------