From c519317a1d0cc4cbafb2ee1bc57cbb3c61e7aa87 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Wed, 16 Dec 2020 08:55:05 +0100
Subject: [PATCH] Modification of the file create_project.tcl with the
 description of the Scalp board.

---
 .../2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl         | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
index faef009..9e98aaa 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
 
 # Create the project
 create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part "hepia-cores.ch:scalp_node:part0:0.1" [current_project]
 set_property target_language VHDL [current_project]
 print_status "Create project" "OK"
 
-- 
GitLab