diff --git a/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd b/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
index 3fd74db2d6f90792a6f25a0e92c4060c76e8d38a..7793741e21b156819644aa6e0e2486105e3a139b 100644
--- a/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
+++ b/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: DRP interface control signals for the Aurora phy.
--
--- Last update: 2020-09-03
+-- Last update: 2020-10-12
--
---------------------------------------------------------------------------------
@@ -25,7 +25,7 @@ use ieee.numeric_std.all;
package aurora_drp_pkg is
- constant C_DRP_ADDR_SIZE : integer := 11;
+ constant C_DRP_ADDR_SIZE : integer := 9;
constant C_DRP_DATA_SIZE : integer := 16;
constant C_DRP_SEL_SIZE : integer := 2;
constant C_DRP_SEL_NORTH : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "00";
@@ -36,26 +36,28 @@ package aurora_drp_pkg is
-- DRP Ports
-- Master To Slave
type t_drpm2s is record
- DrpClkxC : std_logic;
DrpAddrxD : std_ulogic_vector((C_DRP_ADDR_SIZE - 1) downto 0);
DrpDIxD : std_ulogic_vector((C_DRP_DATA_SIZE - 1) downto 0);
DrpEnxS : std_ulogic;
DrpWExS : std_ulogic;
end record t_drpm2s;
+ type t_drpm2s_vector is array (natural range <>) of t_drpm2s;
+
-- Slave To Master
type t_drps2m is record
DrpDOxD : std_ulogic_vector((C_DRP_DATA_SIZE - 1) downto 0);
DrpRdyxS : std_ulogic;
end record t_drps2m;
+ type t_drps2m_vector is array (natural range <>) of t_drps2m;
+
type t_drp is record
M2S : t_drpm2s;
S2M : t_drps2m;
end record t_drp;
- constant C_NO_DRP_M2S : t_drpm2s := (DrpClkxC => '0',
- DrpAddrxD => (others => '0'),
+ constant C_NO_DRP_M2S : t_drpm2s := (DrpAddrxD => (others => '0'),
DrpDIxD => (others => '0'),
DrpEnxS => '0',
DrpWExS => '0');
diff --git a/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
index 479d5a295206ce552acfc3683401f5e0f297ceeb..52f9349ed0544c0280ef4bc3b061b7d380ce45a2 100644
--- a/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
+++ b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: Control and status signals for the Aurora phy.
--
--- Last update: 2020-09-03
+-- Last update: 2020-10-06
--
---------------------------------------------------------------------------------
@@ -51,10 +51,10 @@ package aurora_status_pkg is
end record t_aurora_gtp_diff_io_tx;
constant C_AURORA_NO_GTP_DIFF_IO_RX : t_aurora_gtp_diff_io_rx := (RXPxD => (others => '0'),
- RXNxD => (others => '0'));
+ RXNxD => (others => '0'));
constant C_AURORA_NO_GTP_DIFF_IO_TX : t_aurora_gtp_diff_io_tx := (TXPxD => (others => '0'),
- TXNxD => (others => '0'));
+ TXNxD => (others => '0'));
type t_gtp_diff_ref_clk is record
ClkPxC : std_ulogic;
@@ -62,7 +62,7 @@ package aurora_status_pkg is
end record t_gtp_diff_ref_clk;
constant C_NO_GTP_DIFF_REF_CLK : t_gtp_diff_ref_clk := (ClkPxC => '0',
- ClkNxC => '0');
+ ClkNxC => '0');
type t_aurora_control is record
LoopbackxD : std_ulogic_vector((C_LOOPBACK_SIZE - 1) downto 0);
@@ -75,9 +75,9 @@ package aurora_status_pkg is
constant C_MGTREFCLK1_SRC : std_ulogic := '1';
constant C_AURORA_NO_CONTROL : t_aurora_control := (LoopbackxD => (others => '0'),
- PowerDownxS => '1',
- GTPRefClkSrcxS => C_MGTREFCLK0_SRC,
- InitClkLockedxS => '0');
+ PowerDownxS => '1',
+ GTPRefClkSrcxS => C_MGTREFCLK0_SRC,
+ InitClkLockedxS => '0');
type t_laneup_vector is array (0 to (C_NB_GTP_CORE - 1)) of std_ulogic_vector((C_LANEUP_SIZE - 1) downto 0);
@@ -94,24 +94,24 @@ package aurora_status_pkg is
end record t_aurora_status;
constant C_AURORA_NO_STATUS : t_aurora_status := (HardErrxD => (others => '0'),
- SoftErrxD => (others => '0'),
- FrameErrxD => (others => '0'),
- LaneUpxD => (others => (others => '0')),
- ChannelUpxD => (others => '0'),
- RXResetDoneOutxD => (others => '0'),
- TXResetDoneOutxD => (others => '0'),
- TXLockxD => (others => '0'),
- PllNotLockedxS => '1');
+ SoftErrxD => (others => '0'),
+ FrameErrxD => (others => '0'),
+ LaneUpxD => (others => (others => '0')),
+ ChannelUpxD => (others => '0'),
+ RXResetDoneOutxD => (others => '0'),
+ TXResetDoneOutxD => (others => '0'),
+ TXLockxD => (others => '0'),
+ PllNotLockedxS => '1');
constant C_AURORA_STATUS_OK : t_aurora_status := (HardErrxD => (others => '0'),
- SoftErrxD => (others => '0'),
- FrameErrxD => (others => '0'),
- LaneUpxD => (others => (others => '1')),
- ChannelUpxD => (others => '1'),
- RXResetDoneOutxD => (others => '1'),
- TXResetDoneOutxD => (others => '1'),
- TXLockxD => (others => '1'),
- PllNotLockedxS => '1');
+ SoftErrxD => (others => '0'),
+ FrameErrxD => (others => '0'),
+ LaneUpxD => (others => (others => '1')),
+ ChannelUpxD => (others => '1'),
+ RXResetDoneOutxD => (others => '1'),
+ TXResetDoneOutxD => (others => '1'),
+ TXLockxD => (others => '1'),
+ PllNotLockedxS => '1');
type t_aurora_crc is record
CRCPassFailxSN : std_ulogic;
@@ -119,37 +119,95 @@ package aurora_status_pkg is
end record t_aurora_crc;
constant C_AURORA_NO_CRC : t_aurora_crc := (CRCPassFailxSN => '0',
- CRCValidxS => '0');
+ CRCValidxS => '0');
constant C_AURORA_CRC_OK : t_aurora_crc := (CRCPassFailxSN => '1',
- CRCValidxS => '1');
+ CRCValidxS => '1');
constant C_AURORA_CRC_NO_OK : t_aurora_crc := (CRCPassFailxSN => '0',
- CRCValidxS => '1');
+ CRCValidxS => '1');
+
+ type t_gt_ref_slave_clk is record
+ GTRefClkxC : std_ulogic;
+ end record t_gt_ref_slave_clk;
+
+ constant C_GT_REF_NO_SLAVE_CLK : t_gt_ref_slave_clk := (GTRefClkxC => '0');
+
+ type t_gt_common_slave_clk is record
+ GTRefClkxC : std_ulogic;
+ GTPLL0LockDetClkxC : std_ulogic;
+ CommonResetxR : std_ulogic;
+ end record t_gt_common_slave_clk;
+
+ constant C_GT_COMMON_NO_SLAVE_CLK : t_gt_common_slave_clk := (GTRefClkxC => '0',
+ GTPLL0LockDetClkxC => '0',
+ CommonResetxR => '0');
+
+ type t_gt_common_master_clk is record
+ GTPLL0ClkxCO : std_ulogic;
+ GTPLL1ClkxCO : std_ulogic;
+ GTPLL0RefClkxC : std_ulogic;
+ GTPLL1RefClkxC : std_ulogic;
+ GTPLL0LockxS : std_ulogic;
+ GTPLL1LockxS : std_ulogic;
+ GTPLL0RefClkLostxS : std_ulogic;
+ end record t_gt_common_master_clk;
+
+ constant C_GT_COMMON_NO_MASTER_CLK : t_gt_common_master_clk := (GTPLL0ClkxCO => '0',
+ GTPLL1ClkxCO => '0',
+ GTPLL0RefClkxC => '0',
+ GTPLL1RefClkxC => '0',
+ GTPLL0LockxS => '0',
+ GTPLL1LockxS => '0',
+ GTPLL0RefClkLostxS => '0');
type t_aurora_slave_clk is record
InitClkxC : std_ulogic;
DrpClkxC : std_ulogic;
- GTClkxC : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
- GTClkLockedxD : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+ GTClkxC : std_ulogic;
+ GTClkLockedxS : std_ulogic;
end record t_aurora_slave_clk;
constant C_AURORA_NO_SLAVE_CLK : t_aurora_slave_clk := (InitClkxC => '0',
- DrpClkxC => '0',
- GTClkxC => (others => '0'),
- GTClkLockedxD => (others => '0'));
+ DrpClkxC => '0',
+ GTClkxC => '0',
+ GTClkLockedxS => '0');
type t_aurora_master_clk is record
InitClkxC : std_ulogic;
- UserClkxC : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
- SyncClkxC : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
- PllNotLockedxD : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+ UserClkxC : std_ulogic;
+ SyncClkxC : std_ulogic;
+ PllNotLockedxS : std_ulogic;
end record t_aurora_master_clk;
constant C_AURORA_NO_MASTER_CLK : t_aurora_master_clk := (InitClkxC => '0',
- UserClkxC => (others => '0'),
- SyncClkxC => (others => '0'),
- PllNotLockedxD => (others => '0'));
+ UserClkxC => '0',
+ SyncClkxC => '0',
+ PllNotLockedxS => '0');
+
+ type t_aurora_slave_reset is record
+ ResetxR : std_ulogic;
+ GTResetxR : std_ulogic;
+ end record t_aurora_slave_reset;
+
+ constant C_AURORA_NO_SLAVE_RESET : t_aurora_slave_reset := (ResetxR => '0',
+ GTResetxR => '0');
+
+ type t_aurora_master_reset is record
+ SystemResetxR : std_ulogic;
+ GTResetxR : std_ulogic;
+ end record t_aurora_master_reset;
+
+ constant C_AURORA_NO_MASTER_RESET : t_aurora_master_reset := (SystemResetxR => '0',
+ GTResetxR => '0');
+
+ type t_aurora_master_link_reset is record
+ SystemResetxR : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ LinkResetxR : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+ end record t_aurora_master_link_reset;
+
+ constant C_AURORA_NO_MASTER_LINK_RESET : t_aurora_master_link_reset := (SystemResetxR => (others => '0'),
+ LinkResetxR => (others => '0'));
-- Functions
diff --git a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
index c241510cfa03792e570ec44f685feb95d91da7b3..88e0033df01efd4afaebbd2a9823acaaeaa28a9d 100644
--- a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
+++ b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: AXI4 format bus signals.
--
--- Last update: 2020-09-03
+-- Last update: 2020-10-12
--
---------------------------------------------------------------------------------
@@ -25,13 +25,14 @@ use ieee.numeric_std.all;
package axi4_pkg is
- constant C_AXI4_DATA_SIZE : integer range 0 to 32 := 32;
- constant C_AXI4_KEEP_SIZE : integer range 0 to 32 := 4;
- constant C_AXI4_UFC_DATA_SIZE : integer range 0 to 32 := 3;
- constant C_AXI4_NFC_DATA_SIZE : integer range 0 to 32 := 4;
- constant C_AXI4_DEST_SIZE : integer range 0 to 32 := 4;
- constant C_AXI4_STRB_SIZE : integer range 0 to 32 := C_AXI4_KEEP_SIZE; -- Same as Keep
- constant C_AXI4_USER_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_KEEP_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_UFC_RX_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_UFC_TX_DATA_SIZE : integer range 0 to 32 := 3;
+ constant C_AXI4_NFC_DATA_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_DEST_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_STRB_SIZE : integer range 0 to 32 := C_AXI4_KEEP_SIZE; -- Same as Keep
+ constant C_AXI4_USER_SIZE : integer range 0 to 32 := 32;
-- AXI4 Framing
-- Master to Slave
@@ -84,23 +85,34 @@ package axi4_pkg is
type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
-- AXI4 UFC
- -- Master to Slave
- type t_axi4ufcm2s is record
+ -- Master to Slave RX
+ type t_axi4ufcm2s_rx is record
-- Big Endian
- DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_DATA_SIZE - 1));
+ DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_RX_DATA_SIZE - 1));
KeepxD : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+ LastxS : std_ulogic;
ValidxS : std_ulogic;
- end record t_axi4ufcm2s;
+ end record t_axi4ufcm2s_rx;
+
+ -- Master to Slave TX
+ type t_axi4ufcm2s_tx is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_TX_DATA_SIZE - 1));
+ ValidxS : std_ulogic;
+ end record t_axi4ufcm2s_tx;
-- Slave to Master
- type t_axi4ufcs2m is record
+ type t_axi4ufcs2m_tx is record
ReadyxS : std_ulogic;
- end record t_axi4ufcs2m;
-
- constant C_NO_AXI4_UFC_M2S : t_axi4ufcm2s := (DataxD => (others => '0'),
- KeepxD => (others => '0'),
- ValidxS => '0');
- constant C_NO_AXI4_UFC_S2M : t_axi4ufcs2m := (ReadyxS => '0');
+ end record t_axi4ufcs2m_tx;
+
+ constant C_NO_AXI4_UFC_M2S_RX : t_axi4ufcm2s_rx := (DataxD => (others => '0'),
+ KeepxD => (others => '0'),
+ LastxS => '0',
+ ValidxS => '0');
+ constant C_NO_AXI4_UFC_M2S_TX : t_axi4ufcm2s_tx := (DataxD => (others => '0'),
+ ValidxS => '0');
+ constant C_NO_AXI4_UFC_S2M_TX : t_axi4ufcs2m_tx := (ReadyxS => '0');
-- AXI4 NFC
-- Master to Slave