From fdab86816ad90b5f779fbc0374bd7b1c6267f3a6 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Mon, 21 Sep 2020 13:42:06 +0200
Subject: [PATCH] Version of the SCALP project created from the
 vivado_project_creator project manager and integrating the Zynq SoC part.

---
 .../2019.2/lin64/.scripts/.prompt_colors.tcl  |   2 +-
 .../.scripts/clean_prj_scalp_firmware.sh      |   2 +-
 .../.scripts/create_prj_scalp_firmware.sh     |   2 +-
 .../.scripts/create_prj_scalp_firmware.tcl    | 215 ++++++++++++++++++
 .../.scripts/export_hw_scalp_firmware.sh      |   2 +-
 .../.scripts/export_hw_scalp_firmware.tcl     |   2 +-
 .../.scripts/gen_bitstream_scalp_firmware.sh  |   2 +-
 .../.scripts/gen_bitstream_scalp_firmware.tcl |   2 +-
 .../.scripts/gen_sw_apps_scalp_firmware.sh    |   2 +-
 .../.scripts/gen_sw_apps_scalp_firmware.tcl   |   2 +-
 .../.scripts/load_bitstream_scalp_firmware.sh |   2 +-
 .../load_bitstream_scalp_firmware.tcl         |   2 +-
 .../.scripts/load_sw_app_scalp_firmware.sh    |   2 +-
 .../.scripts/load_sw_app_scalp_firmware.tcl   |   2 +-
 .../lin64/.scripts/open_prj_scalp_firmware.sh |   2 +-
 .../2019.2/lin64/.scripts/utils.tcl           |   2 +-
 .../2019.2/lin64/setup.sh                     |   2 +-
 .../2019.2/src/constrs/debug.xdc              |   0
 .../2019.2/src/constrs/ibert_constraints.xdc  |   0
 .../2019.2/src/constrs/scalp_firmware.xdc     |   0
 .../2019.2/src/constrs/timing_constraints.xdc |   0
 .../2019.2/src/hdl/scalp_firmware.vhd         |   0
 .../2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl |   1 +
 .../2019.2/src/sim/tb_scalp_firmware.vhd      |   2 +-
 .../.scripts/create_prj_scalp_firmware.tcl    | 155 -------------
 .../2019.2/src/hdl/scalp_zynqps_wrapper.vhd   |  99 --------
 .../2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl |   7 -
 tools/config/scalp_firmware.json              |   2 +-
 28 files changed, 234 insertions(+), 279 deletions(-)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/.prompt_colors.tcl (96%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh (96%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh (96%)
 create mode 100644 designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh (96%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl (97%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh (96%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl (97%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh (97%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl (98%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh (96%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl (98%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh (96%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl (97%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh (95%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/.scripts/utils.tcl (98%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/lin64/setup.sh (97%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/src/constrs/debug.xdc (100%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/src/constrs/ibert_constraints.xdc (100%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/src/constrs/scalp_firmware.xdc (100%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/src/constrs/timing_constraints.xdc (100%)
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/src/hdl/scalp_firmware.vhd (100%)
 create mode 100644 designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
 rename designs/vivado/{scalp_firmware_old => scalp_firmware}/2019.2/src/sim/tb_scalp_firmware.vhd (96%)
 delete mode 100644 designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
 delete mode 100644 designs/vivado/scalp_firmware_old/2019.2/src/hdl/scalp_zynqps_wrapper.vhd
 delete mode 100644 designs/vivado/scalp_firmware_old/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl

diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
index 16aac84..a3cf9d5 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Console color print utility
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
index fb6f8b8..c84333e 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Cleanup project directory
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
index 7e3d46c..8a727d2 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Create Vivado project
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
new file mode 100644
index 0000000..cc44639
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
@@ -0,0 +1,215 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_firmware
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script for re-creating Vivado project 'scalp_firmware'
+#
+# Last update: 2020-09-21 13:34:23
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_firmware"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "DESIGN_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+#set_property board_part SCALP [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	# add HDL sources
+	set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list    
+	# add the constraints file (XDC)
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
+	add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
+	set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
+
+	#add_files -fileset constrs_1 -norecurse  $src_dir/constrs/${prj_name}.xdc
+	# add IPs source file
+	#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	# components sources are stored in an external directory
+	# add the project component
+	set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list
+	# add IPs source file
+	#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+	# add IP-XACT source file
+	#add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+foreach j $vhdl_src_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
+# Set packages libraries if any
+#set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+foreach j $vhdl_sim_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
+# Add packages sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+}
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
+
+# Add SoC wrapper sources files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
+	add_files -norecurse $vhdl_soc_file_list
+	foreach j $vhdl_soc_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
+	add_files -norecurse $vhdl_soc_file_list
+	foreach j $vhdl_soc_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+}
+print_status "Add SoC wrapper sources" "OK"
+print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
index aa27021..8cad73a 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Export the hardware design to SDK
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
similarity index 97%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
index f2dc144..e5164ce 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Export the hardware design to SDK
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
index 031767a..ea5d957 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Generate bitstream file
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
similarity index 97%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
index 4830b94..bccfb50 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to generate bitstream file
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
similarity index 97%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
index 52a2e56..e01bfd0 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Generate software application
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
similarity index 98%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
index 530e0b5..d733164 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to generate software application
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
index cc3be8e..01cba1a 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Load bitstream file
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
similarity index 98%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
index d67a6d9..d5a42f5 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to load FPGA bitstream
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
index 05f9d3f..1aed91c 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Load software application
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
similarity index 97%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
index f6afbe5..e6717e9 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to load software application
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
similarity index 95%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
index b7219ea..e1ad3a9 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Create Vivado project
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
similarity index 98%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/utils.tcl
rename to designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
index 226b22a..6e207a4 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/utils.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Project management utilities
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/setup.sh b/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
similarity index 97%
rename from designs/vivado/scalp_firmware_old/2019.2/lin64/setup.sh
rename to designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
index f5f1329..a67797b 100755
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/setup.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script creating aliases for Vivado project management scripts
 #
-# Last update: 2020-09-03 11:28:21
+# Last update: 2020-09-21 13:34:23
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/constrs/debug.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
similarity index 100%
rename from designs/vivado/scalp_firmware_old/2019.2/src/constrs/debug.xdc
rename to designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/constrs/ibert_constraints.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/ibert_constraints.xdc
similarity index 100%
rename from designs/vivado/scalp_firmware_old/2019.2/src/constrs/ibert_constraints.xdc
rename to designs/vivado/scalp_firmware/2019.2/src/constrs/ibert_constraints.xdc
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc
similarity index 100%
rename from designs/vivado/scalp_firmware_old/2019.2/src/constrs/scalp_firmware.xdc
rename to designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc
similarity index 100%
rename from designs/vivado/scalp_firmware_old/2019.2/src/constrs/timing_constraints.xdc
rename to designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
similarity index 100%
rename from designs/vivado/scalp_firmware_old/2019.2/src/hdl/scalp_firmware.vhd
rename to designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
diff --git a/designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl b/designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
new file mode 100644
index 0000000..61be405
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
@@ -0,0 +1 @@
+source "../../../../../../soc/vivado/scalp_zynqps/2019.2/src/ipi_tcl/scalp_zynqps_ipi.tcl"
\ No newline at end of file
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/sim/tb_scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
similarity index 96%
rename from designs/vivado/scalp_firmware_old/2019.2/src/sim/tb_scalp_firmware.vhd
rename to designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
index fd05342..b9c126f 100644
--- a/designs/vivado/scalp_firmware_old/2019.2/src/sim/tb_scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.2
 -- Description: Testbench for scalp_firmware
 --
--- Last update: 2020-09-03 11:28:21
+-- Last update: 2020-09-21 13:34:23
 --
 ---------------------------------------------------------------------------------
 
diff --git a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
deleted file mode 100644
index e79ca5e..0000000
--- a/designs/vivado/scalp_firmware_old/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+++ /dev/null
@@ -1,155 +0,0 @@
-##################################################################################
-#                                 _             _
-#                                | |_  ___ _ __(_)__ _
-#                                | ' \/ -_) '_ \ / _` |
-#                                |_||_\___| .__/_\__,_|
-#                                         |_|
-#
-##################################################################################
-#
-# Company: hepia
-# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
-#
-# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
-# Description: TCL script for re-creating Vivado project 'scalp_firmware'
-#
-# Last update: 2020-09-03 11:28:21
-#
-##################################################################################
-
-# Include files
-source utils.tcl
-
-set PRJ_DIR ".."
-set prj_name "scalp_firmware"
-
-# Set project type
-set PRJ_TYPE "DESIGN_PRJ_TYPE"
-
-# Create a variable to store the start time
-set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
-
-# Set the original project directory path for adding/importing sources in the new project
-set src_dir "${PRJ_DIR}/../src"
-set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
-set comp_dir "${ip_dir}/$prj_name"
-set comp_src_dir "${comp_dir}/src"
-# USER DEFINE
-set lib_dir "${PRJ_DIR}/../../../../../lib/${prj_name}_hdl_lib/hw/src"
-#set PRJ_ZYNPS "scalp_zynqps"
-#set zynqps_dir "${PRJ_DIR}/../../../../../soc/hw/${scalp_zynqps}/src"
-##
-
-print_status "Set directory paths" "OK"
-
-# Create the project
-create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
-set_property target_language VHDL [current_project]
-print_status "Create project" "OK"
-
-# Map the IP Repository so that custom IP is included
-set_property ip_repo_paths $ip_dir [current_fileset]
-update_ip_catalog
-
-#----------------------------------------------------------------
-# Add project sources
-#----------------------------------------------------------------
-
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	# add HDL sources
-	set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
-	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
-    #USER DEFINE
-    set vhdl_lib_src_file_list [findFiles $lib_dir/hdl *.vhd]
-    set verilog_lib_src_file_list [findFiles $lib_dir/hdl *.v]
-    ##
-	set vhdl_src_file_list [list {*}$vhdl_src_file_list {*}$vhdl_lib_src_file_list]
-    set verilog_src_file_list [list {*}$verilog_src_file_list {*}$verilog_lib_src_file_list]
-    ##
-    set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]   
-    
-	add_files -norecurse $hdl_src_file_list
-	# add the constraints file (XDC)
-	add_files -fileset constrs_1 -norecurse  $src_dir/constrs/${prj_name}.xdc
-    # USER DEFINE
-    add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
-    add_files -fileset constrs_1 -norecurse  $src_dir/constrs/debug.xdc
-    add_files -fileset constrs_1 -norecurse  $src_dir/constrs/timing_constraints.xdc
-	# add IPs source file
-	#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
-	# components sources are stored in an external directory
-	# add the project component
-	set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
-	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
-    #USER DEFINE
-    set vhdl_lib_src_file_list [findFiles $lib_dir/hdl *.vhd]    
-    set verilog_lib_src_file_list [findFiles $lib_dir/hdl *.v]
-
-    set vhdl_src_file_list [list {*}$vhdl_src_file_list {*}$vhdl_lib_src_file_list]
-    set verilog_src_file_list [list {*}$verilog_src_file_list {*}$verilog_lib_src_file_list]
-    ##
-    set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
-    
-	add_files -norecurse $hdl_src_file_list
-	# add IPs source file
-	#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
-	# add IP-XACT source file
-	#add_files -norecurse $comp_dir/component.xml
-}
-print_status "Add project sources" "OK"
-
-foreach j $vhdl_src_file_list {
-    set_property file_type {VHDL 2008} [get_files  $j]
-    print_status "VHDL 2008 mode configured for the file $j" "OK"
-}
-
-print_status "VHDL 2008 mode configured for project sources" "OK"
-
-# Set packages libraries if any
-#set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
-#update_compile_order -fileset sources_1
-
-# Create the IP Integrator portion of the design
-#create_bd_design "axi_design"
-#update_compile_order -fileset sources_1
-
-# launch the TCL script to generate the IPI design
-source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
-print_status "Add IPI design" "OK"
-
-# Set the top level design
-set_property top $prj_name [current_fileset]
-update_compile_order -fileset sources_1
-
-# Add testbench sources
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
-	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
-	set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
-	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
-}
-set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
-add_files -fileset sim_1 -norecurse $hdl_sim_file_list
-update_compile_order -fileset sim_1
-print_status "Add testbench sources" "OK"
-
-foreach j $vhdl_sim_file_list {
-    set_property file_type {VHDL 2008} [get_files  $j]
-    print_status "VHDL 2008 mode configured for the file $j" "OK"
-}
-
-print_status "VHDL 2008 mode configured for testbench sources" "OK"
-
-# Set the completion time
-set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
-
-# Display the start and end time to the screen
-puts $start_time
-puts $end_time
-
-exit
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/hdl/scalp_zynqps_wrapper.vhd b/designs/vivado/scalp_firmware_old/2019.2/src/hdl/scalp_zynqps_wrapper.vhd
deleted file mode 100644
index 46d154c..0000000
--- a/designs/vivado/scalp_firmware_old/2019.2/src/hdl/scalp_zynqps_wrapper.vhd
+++ /dev/null
@@ -1,99 +0,0 @@
-----------------------------------------------------------------------------------
---                                 _             _
---                                | |_  ___ _ __(_)__ _
---                                | ' \/ -_) '_ \ / _` |
---                                |_||_\___| .__/_\__,_|
---                                         |_|
---
-----------------------------------------------------------------------------------
---
--- Company: hepia
--- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
---
--- Module Name: scalp_zynqps_wrapper - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
--- Description: scalp_zynqps_wrapper
---
--- Last update: 2020-09-07
---
----------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity scalp_zynqps_wrapper is
-
-    port (
-        -- Processor interface
-        FIXED_IO_ps_clk     : inout std_logic;
-        FIXED_IO_ps_porb    : inout std_logic;
-        FIXED_IO_ps_srstb   : inout std_logic;
-        FclkClk0xCO         : out   std_logic;
-        FclkReset0xRO       : out   std_logic;
-        -- DDR interface
-        DDR_addr            : inout std_logic_vector (14 downto 0);
-        DDR_ba              : inout std_logic_vector (2 downto 0);
-        DDR_cas_n           : inout std_logic;
-        DDR_ck_n            : inout std_logic;
-        DDR_ck_p            : inout std_logic;
-        DDR_cke             : inout std_logic;
-        DDR_cs_n            : inout std_logic;
-        DDR_dm              : inout std_logic_vector (3 downto 0);
-        DDR_dq              : inout std_logic_vector (31 downto 0);
-        DDR_dqs_n           : inout std_logic_vector (3 downto 0);
-        DDR_dqs_p           : inout std_logic_vector (3 downto 0);
-        DDR_odt             : inout std_logic;
-        DDR_ras_n           : inout std_logic;
-        DDR_reset_n         : inout std_logic;
-        DDR_we_n            : inout std_logic;
-        FIXED_IO_ddr_vrn    : inout std_logic;
-        FIXED_IO_ddr_vrp    : inout std_logic;
-        -- USB interface
-        Usb0VBusPwrFaultxSI : in    std_logic;
-        -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
-        -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
-        Spi1MOSIxSO         : out   std_logic;
-        Spi1SSxSO           : out   std_logic;
-        Spi1SclkxCO         : out   std_logic;
-        -- MIO
-        FIXED_IO_mio        : inout std_logic_vector (53 downto 0));
-
-end scalp_zynqps_wrapper;
-
-architecture arch of scalp_zynqps_wrapper is
-
-begin
-
-    ScalpZynqPSxI : entity work.scalp_zynqps
-        port map (
-            DDR_addr            => DDR_addr,
-            DDR_ba              => DDR_ba,
-            DDR_cas_n           => DDR_cas_n,
-            DDR_ck_n            => DDR_ck_n,
-            DDR_ck_p            => DDR_ck_p,
-            DDR_cke             => DDR_cke,
-            DDR_cs_n            => DDR_cs_n,
-            DDR_dm              => DDR_dm,
-            DDR_dq              => DDR_dq,
-            DDR_dqs_n           => DDR_dqs_n,
-            DDR_dqs_p           => DDR_dqs_p,
-            DDR_odt             => DDR_odt,
-            DDR_ras_n           => DDR_ras_n,
-            DDR_reset_n         => DDR_reset_n,
-            DDR_we_n            => DDR_we_n,
-            FIXED_IO_ddr_vrn    => FIXED_IO_ddr_vrn,
-            FIXED_IO_ddr_vrp    => FIXED_IO_ddr_vrp,
-            FIXED_IO_mio        => FIXED_IO_mio,
-            FIXED_IO_ps_clk     => FIXED_IO_ps_clk,
-            FIXED_IO_ps_porb    => FIXED_IO_ps_porb,
-            FIXED_IO_ps_srstb   => FIXED_IO_ps_srstb,
-            FclkClk0xCO         => FclkClk0xCO,
-            FclkReset0xRO(0)    => FclkReset0xRO,
-            Spi1MOSIxSO         => Spi1MOSIxSO,
-            Spi1SSxSO           => Spi1SSxSO,
-            Spi1SclkxCO         => Spi1SclkxCO,
-            Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI);
-
-end arch;
diff --git a/designs/vivado/scalp_firmware_old/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl b/designs/vivado/scalp_firmware_old/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
deleted file mode 100644
index effef90..0000000
--- a/designs/vivado/scalp_firmware_old/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
+++ /dev/null
@@ -1,7 +0,0 @@
-set PRJ_ZYNQPS "scalp_zynqps"
-set VIVADO_VERSION "2019.2"
-
-set zynqps_dir "../../../../../../soc/vivado/${PRJ_ZYNQPS}/${VIVADO_VERSION}/src/ipi_tcl"
-set zynqps_ipi "${PRJ_ZYNQPS}_ipi.tcl"
-
-source "${zynqps_dir}/${zynqps_ipi}"
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
index 852d07d..1e259d2 100644
--- a/tools/config/scalp_firmware.json
+++ b/tools/config/scalp_firmware.json
@@ -28,7 +28,7 @@
             "axi4_pkg"          : "enable"
         },
         "soc" : {
-            "scalp_zynqps" : "true"
+            "scalp_zynqps" : "enable"
         }
     }
 }
-- 
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