diff --git a/designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc b/designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc
index 82f080b8837b04a049fcd56b02a70fced9c6e296..a070fb74d595fc7e11207ebfdc5226a5e23e1134 100644
--- a/designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc
+++ b/designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc
@@ -152,52 +152,91 @@ set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
#set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
#set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom7NxSIO]
+##### Fake MIPI pins (Bank 34) #####
+# FAKE LP_CLK_P
+#set_property PACKAGE_PIN M8 [get_ports LVDS2V5Top4PxSIO]
+#set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Top4PxSIO]
+## FAKE LP_CLK_N
+#set_property PACKAGE_PIN M7 [get_ports LVDS2V5Top4NxSIO]
+#set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Top4NxSIO]
+## FAKE LP_LANE1_P
+#set_property PACKAGE_PIN L6 [get_ports LVDS2V5Top3PxSIO]
+#set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Top3PxSIO]
+## FAKE LP_LANE1_N
+#set_property PACKAGE_PIN M6 [get_ports LVDS2V5Top3NxSIO]
+#set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Top3NxSIO]
+## FAKE HS_LANE1_P
+#set_property PACKAGE_PIN J7 [get_ports LVDS2V5Top2PxSIO]
+#set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Top2PxSIO]
+## FAKE HS_LANE1_N
+#set_property PACKAGE_PIN J6 [get_ports LVDS2V5Top2NxSIO]
+#set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Top2NxSIO]
+## FAKE LP_LANE0_P
+#set_property PACKAGE_PIN J5 [get_ports LVDS2V5Top1PxSIO]
+#set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Top1PxSIO]
+## FAKE LP_LANE0_N
+#set_property PACKAGE_PIN K5 [get_ports LVDS2V5Top1NxSIO]
+#set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Top1NxSIO]
+## FAKE HS_LANE0_P
+#set_property PACKAGE_PIN J2 [get_ports LVDS2V5Top0PxSIO]
+#set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Top0PxSIO]
+## FAKE HS_LANE0_N
+#set_property PACKAGE_PIN J1 [get_ports LVDS2V5Top0NxSIO]
+#set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Top0NxSIO]
+## FAKE HS_CLK_P
+#set_property PACKAGE_PIN K4 [get_ports Clk2V5TopPxCI]
+#set_property IOSTANDARD LVDS_25 [get_ports Clk2V5TopPxCI]
+## FAKE HS_CLK_N
+#set_property PACKAGE_PIN K3 [get_ports Clk2V5TopNxCI]
+#set_property IOSTANDARD LVDS_25 [get_ports Clk2V5TopNxCI]
+
+
##### Camera MIPI connector (Bank 34) #####
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
-# Camera GPIO_BTA
-set_property PACKAGE_PIN P6 [get_ports LVDS2V5Bottom6PxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom6PxSIO]
-# Camera PWUP
-set_property PACKAGE_PIN P5 [get_ports LVDS2V5Bottom6NxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom6NxSIO]
-# Camera SDA
-set_property PACKAGE_PIN R5 [get_ports LVDS2V5Bottom5PxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom5PxSIO]
-set_property PULLTYPE PULLUP [get_ports LVDS2V5Bottom5PxSIO]
-# Camera SCL
-set_property PACKAGE_PIN R4 [get_ports LVDS2V5Bottom5NxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom5NxSIO]
-set_property PULLTYPE PULLUP [get_ports LVDS2V5Bottom5NxSIO]
-# Camera LP_CLK_P
-set_property PACKAGE_PIN R3 [get_ports LVDS2V5Bottom4PxSIO]
-set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom4PxSIO]
-# Camera LP_CLK_N
-set_property PACKAGE_PIN R2 [get_ports LVDS2V5Bottom4NxSIO]
-set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom4NxSIO]
-# Camera LP_LANE1_P
-set_property PACKAGE_PIN P3 [get_ports LVDS2V5Bottom3PxSIO]
-set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom3PxSIO]
-# Camera LP_LANE1_N
-set_property PACKAGE_PIN P2 [get_ports LVDS2V5Bottom3NxSIO]
-set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom3NxSIO]
-# Camera HS_LANE1_P
-set_property PACKAGE_PIN N1 [get_ports LVDS2V5Bottom2PxSIO]
-set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom2PxSIO]
-# Camera HS_LANE1_N
-set_property PACKAGE_PIN P1 [get_ports LVDS2V5Bottom2NxSIO]
-set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom2NxSIO]
-# Camera LP_LANE0_P
-set_property PACKAGE_PIN N4 [get_ports LVDS2V5Bottom1PxSIO]
-set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom1PxSIO]
-# Camera LP_LANE0_N
-set_property PACKAGE_PIN N3 [get_ports LVDS2V5Bottom1NxSIO]
-set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom1NxSIO]
-# Camera HS_LANE0_P
-set_property PACKAGE_PIN M2 [get_ports LVDS2V5Bottom0PxSIO]
-set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom0PxSIO]
-# Camera HS_LANE0_N
-set_property PACKAGE_PIN M1 [get_ports LVDS2V5Bottom0NxSIO]
-set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom0NxSIO]
+# Camera GPIO_BTA -> LVDS2V5Bottom6PxSIO
+set_property PACKAGE_PIN P6 [get_ports CamGpioBta]
+set_property IOSTANDARD LVCMOS25 [get_ports CamGpioBta]
+# Camera PWUP -> LVDS2V5Bottom6NxSIO
+set_property PACKAGE_PIN P5 [get_ports CamPwup]
+set_property IOSTANDARD LVCMOS25 [get_ports CamPwup]
+# Camera SDA -> LVDS2V5Bottom5PxSIO
+set_property PACKAGE_PIN R5 [get_ports CamI2cSda]
+set_property IOSTANDARD LVCMOS25 [get_ports CamI2cSda]
+set_property PULLTYPE PULLUP [get_ports CamI2cSda]
+# Camera SCL -> LVDS2V5Bottom5NxSIO
+set_property PACKAGE_PIN R4 [get_ports CamI2cScl]
+set_property IOSTANDARD LVCMOS25 [get_ports CamI2cScl]
+set_property PULLTYPE PULLUP [get_ports CamI2cScl]
+# Camera LP_CLK_P -> LVDS2V5Bottom4PxSIO
+set_property PACKAGE_PIN R3 [get_ports CamLpClkP]
+set_property IOSTANDARD HSUL_12 [get_ports CamLpClkP]
+# Camera LP_CLK_N -> LVDS2V5Bottom4NxSIO
+set_property PACKAGE_PIN R2 [get_ports CamLpClkN]
+set_property IOSTANDARD HSUL_12 [get_ports CamLpClkN]
+# Camera LP_LANE1_P -> LVDS2V5Bottom3PxSIO
+set_property PACKAGE_PIN P3 [get_ports {CamLpDataP[1]}]
+set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataP[1]}]
+# Camera LP_LANE1_N -> LVDS2V5Bottom3NxSIO
+set_property PACKAGE_PIN P2 [get_ports {CamLpDataN[1]}]
+set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataN[1]}]
+# Camera HS_LANE1_P -> LVDS2V5Bottom2PxSIO
+set_property PACKAGE_PIN N1 [get_ports {CamHsDataP[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataP[1]}]
+# Camera HS_LANE1_N -> LVDS2V5Bottom2NxSIO
+set_property PACKAGE_PIN P1 [get_ports {CamHsDataN[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataN[1]}]
+# Camera LP_LANE0_P -> LVDS2V5Bottom1PxSIO
+set_property PACKAGE_PIN N4 [get_ports {CamLpDataP[0]}]
+set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataP[0]}]
+# Camera LP_LANE0_N -> LVDS2V5Bottom1NxSIO
+set_property PACKAGE_PIN N3 [get_ports {CamLpDataN[0]}]
+set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataN[0]}]
+# Camera HS_LANE0_P -> LVDS2V5Bottom0PxSIO
+set_property PACKAGE_PIN M2 [get_ports {CamHsDataP[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataP[0]}]
+# Camera HS_LANE0_N -> LVDS2V5Bottom0NxSIO
+set_property PACKAGE_PIN M1 [get_ports {CamHsDataN[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataN[0]}]
##### RGB LEDs (banks 34 and 13) #####
# LED1_2V5_R_o (bank 34)
@@ -249,12 +288,12 @@ set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
#set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
##### Camera MIPI connector (Bank 34) #####
-# Camera HS_CLK_P
-set_property PACKAGE_PIN U2 [get_ports Clk2V5BottomPxCI]
-set_property IOSTANDARD LVDS_25 [get_ports Clk2V5BottomPxCI]
-# Camera HS_CLK_N
-set_property PACKAGE_PIN U1 [get_ports Clk2V5BottomNxCI]
-set_property IOSTANDARD LVDS_25 [get_ports Clk2V5BottomNxCI]
+# Camera HS_CLK_P -> Clk2V5BottomPxCI
+set_property PACKAGE_PIN U2 [get_ports CamHsClkP]
+set_property IOSTANDARD LVDS_25 [get_ports CamHsClkP]
+# Camera HS_CLK_N -> Clk2V5BottomNxCI
+set_property PACKAGE_PIN U1 [get_ports CamHsClkN]
+set_property IOSTANDARD LVDS_25 [get_ports CamHsClkN]
# Bank 13
#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
diff --git a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
index 8fc403b192c0dd1aefae80f0ad8226103df27c44..e4c2fb5e853dcb4e02bcb0d88b20f13ea0d0b8b3 100644
--- a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
+++ b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
@@ -173,16 +173,16 @@ entity scalp_mipi is
-- LVDS2V5West7NxSIO : inout std_logic;
-- LVDS links towards top-bottom connectors
-- Top
- -- LVDS2V5Top0PxSIO : inout std_logic;
- -- LVDS2V5Top0NxSIO : inout std_logic;
- -- LVDS2V5Top1PxSIO : inout std_logic;
- -- LVDS2V5Top1NxSIO : inout std_logic;
- -- LVDS2V5Top2PxSIO : inout std_logic;
- -- LVDS2V5Top2NxSIO : inout std_logic;
- -- LVDS2V5Top3PxSIO : inout std_logic;
- -- LVDS2V5Top3NxSIO : inout std_logic;
- -- LVDS2V5Top4PxSIO : inout std_logic;
- -- LVDS2V5Top4NxSIO : inout std_logic;
+-- LVDS2V5Top0PxSIO : in std_logic;
+-- LVDS2V5Top0NxSIO : in std_logic;
+-- LVDS2V5Top1PxSIO : in std_logic;
+-- LVDS2V5Top1NxSIO : in std_logic;
+-- LVDS2V5Top2PxSIO : in std_logic;
+-- LVDS2V5Top2NxSIO : in std_logic;
+-- LVDS2V5Top3PxSIO : in std_logic;
+-- LVDS2V5Top3NxSIO : in std_logic;
+-- LVDS2V5Top4PxSIO : in std_logic;
+-- LVDS2V5Top4NxSIO : in std_logic;
-- LVDS2V5Top5PxSIO : inout std_logic;
-- LVDS2V5Top5NxSIO : inout std_logic;
-- LVDS2V5Top6PxSIO : inout std_logic;
@@ -190,22 +190,21 @@ entity scalp_mipi is
-- LVDS2V5Top7PxSIO : inout std_logic;
-- LVDS2V5Top7NxSIO : inout std_logic;
-- Bottom
- LVDS2V5Bottom0PxSIO : in std_logic; -- Camera HS_LANE0_P
- LVDS2V5Bottom0NxSIO : in std_logic; -- Camera HS_LANE0_N
- LVDS2V5Bottom1PxSIO : in std_logic; -- Camera LP_LANE0_P
- LVDS2V5Bottom1NxSIO : in std_logic; -- Camera LP_LANE0_N
- LVDS2V5Bottom2PxSIO : in std_logic; -- Camera HS_LANE1_P
- LVDS2V5Bottom2NxSIO : in std_logic; -- Camera HS_LANE1_N
- LVDS2V5Bottom3PxSIO : in std_logic; -- Camera LP_LANE1_P
- LVDS2V5Bottom3NxSIO : in std_logic; -- Camera LP_LANE1_N
- LVDS2V5Bottom4PxSIO : in std_logic; -- Camera LP_CLK_P
- LVDS2V5Bottom4NxSIO : in std_logic; -- Camera LP_CLK_N
- LVDS2V5Bottom5PxSIO : inout std_logic; -- Camera I2C SDA
- LVDS2V5Bottom5NxSIO : inout std_logic; -- Camera I2C SCL
- LVDS2V5Bottom6PxSIO : inout std_logic; -- Camera GPIO_BTA
- LVDS2V5Bottom6NxSIO : inout std_logic; -- Camera PWUP
-- LVDS2V5Bottom7PxSIO : inout std_logic;
-- LVDS2V5Bottom7NxSIO : inout std_logic;
+ -- Camera signals
+ CamHsDataP : in std_logic_vector(1 downto 0); -- Camera HS DATA P
+ CamHsDataN : in std_logic_vector(1 downto 0); -- Camera HS DATA N
+ CamLpDataP : in std_logic_vector(1 downto 0); -- Camera LP DATA P
+ CamLpDataN : in std_logic_vector(1 downto 0); -- Camera LP DATA N
+ CamLpClkP : in std_logic; -- Camera LP CLK P
+ CamLpClkN : in std_logic; -- Camera LP CLK N
+ CamHsClkP : in std_logic; -- Camera HS CLK P
+ CamHsClkN : in std_logic; -- Camera HS CLK N
+ CamI2cSda : inout std_logic; -- Camera I2C SDA
+ CamI2cScl : inout std_logic; -- Camera I2C SCL
+ CamGpioBta : out std_logic; -- Camera GPIO_BTA
+ CamPwup : out std_logic; -- Camera PWUP
-- RGB LEDs
Led12V5RxSO : out std_logic;
Led12V5GxSO : out std_logic;
@@ -214,7 +213,7 @@ entity scalp_mipi is
Led22V5GxSO : out std_logic;
Led22V5BxSO : out std_logic;
-- Self reset (connected to PS_SRSTB)
- SelfRstxRNO : out std_logic;
+ SelfRstxRNO : out std_logic
-- Clocks from PLLs (connected to MRCC pins)
-- Local
-- PLLClk2V5LocalPxCI : in std_logic;
@@ -251,13 +250,11 @@ entity scalp_mipi is
-- Clk2V5WestPxCO : out std_logic;
-- Clk2V5WestNxCO : out std_logic;
-- -- Top
- -- Clk2V5TopPxCI : in std_logic;
- -- Clk2V5TopNxCI : in std_logic;
+-- Clk2V5TopPxCI : in std_logic;
+-- Clk2V5TopNxCI : in std_logic;
-- Clk2V5TopPxCO : out std_logic;
-- Clk2V5TopNxCO : out std_logic;
-- -- Bottom
- Clk2V5BottomPxCI : in std_logic; -- Camera HS_CLK_P
- Clk2V5BottomNxCI : in std_logic -- Camera HS_CLK_N
-- Clk2V5BottomPxCO : out std_logic;
-- Clk2V5BottomNxCO : out std_logic;
-- -- Recovery
@@ -293,6 +290,9 @@ architecture arch of scalp_mipi is
signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- RGB Leds
signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- Camera GPIO signals
+ signal CamPwupxS : std_logic_vector(0 downto 0) := (others => '0');
+ signal CamGpioxS : std_logic_vector(0 downto 0) := (others => '0');
-- I2C1 signals
signal I2c1SdaIxS : std_logic := '0';
signal I2c1SdaOxS : std_logic := '0';
@@ -300,50 +300,12 @@ architecture arch of scalp_mipi is
signal I2c1SclIxS : std_logic := '0';
signal I2c1SclOxS : std_logic := '0';
signal I2c1SclTxS : std_logic := '0';
- -- GPIO0 signals
- signal GPIO0IxD : std_logic_vector(31 downto 0) := (others => '0');
- signal GPIO0OxD : std_logic_vector(31 downto 0) := (others => '0');
- signal GPIO0TxD : std_logic_vector(31 downto 0) := (others => '0');
- signal Csi2RstnxS : std_logic := '0';
- signal DmaRstnxS : std_logic := '0';
- -- Camera MIPI signals
- signal MipiClockHsNxC : std_logic := '0';
- signal MipiClockHsPxC : std_logic := '0';
- signal MipiClockLpNxC : std_logic := '0';
- signal MipiClockLpPxC : std_logic := '0';
- signal MipiDataHsNxD : std_logic_vector(1 downto 0) := (others => '0');
- signal MipiDataHsPxD : std_logic_vector(1 downto 0) := (others => '0');
- signal MipiDataLpNxD : std_logic_vector(1 downto 0) := (others => '0');
- signal MipiDataLpPxD : std_logic_vector(1 downto 0) := (others => '0');
-
-- Attributes
-- attribute mark_debug : string;
-- attribute keep : string;
-- Clocks
-- attribute keep of PSSysClkxC : signal is "true";
-
- -- GPIO debug probes
- --attribute mark_debug of GPIO0IxD : signal is "true";
- --attribute keep of GPIO0IxD : signal is "true";
- --attribute mark_debug of GPIO0OxD : signal is "true";
--- attribute keep of GPIO0OxD : signal is "true";
--- attribute mark_debug of GPIO0TxD : signal is "true";
--- attribute keep of GPIO0TxD : signal is "true";
-
- -- I2C1 debug probes
--- attribute mark_debug of I2c1SdaIxS : signal is "true";
--- attribute keep of I2c1SdaIxS : signal is "true";
--- attribute mark_debug of I2c1SdaOxS : signal is "true";
--- attribute keep of I2c1SdaOxS : signal is "true";
--- attribute mark_debug of I2c1SdaTxS : signal is "true";
--- attribute keep of I2c1SdaTxS : signal is "true";
--- attribute mark_debug of I2c1SclIxS : signal is "true";
--- attribute keep of I2c1SclIxS : signal is "true";
--- attribute mark_debug of I2c1SclOxS : signal is "true";
--- attribute keep of I2c1SclOxS : signal is "true";
--- attribute mark_debug of I2c1SclTxS : signal is "true";
--- attribute keep of I2c1SclTxS : signal is "true";
begin
@@ -394,28 +356,25 @@ begin
WrDataxDO => WrDataxD,
WrValidxSO => WrValidxS,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD,
- -- Zynq I2C1 interface
+ -- Camera GPIOs
+ CamPwup => CamPwupxS,
+ CamGpio => CamGpioxS,
+ -- Camera I2C interface
I2c1SdaxSI => I2c1SdaIxS,
I2c1SdaxSO => I2c1SdaOxS,
I2c1SdaxST => I2c1SdaTxS,
I2c1SclxSI => I2c1SclIxS,
I2c1SclxSO => I2c1SclOxS,
I2c1SclxST => I2c1SclTxS,
- -- Zynq GPIO0 interface
- GPIO0xDI => GPIO0IxD,
- GPIO0xDO => GPIO0OxD,
- GPIO0xDT => GPIO0TxD,
- -- MIPI interface
- MipiClockHsN => MipiClockHsNxC,
- MipiClockHsP => MipiClockHsPxC,
- MipiClockLpN => MipiClockLpNxC,
- MipiClockLpP => MipiClockLpPxC,
- MipiDataHsN => MipiDataHsNxD,
- MipiDataHsP => MipiDataHsPxD,
- MipiDataLpN => MipiDataLpNxD,
- MipiDataLpP => MipiDataLpPxD,
- Csi2Rstn => Csi2RstnxS,
- DmaRstn => DmaRstnxS
+ -- Camera MIPI interface
+ MipiClockHsN => CamHsClkN,
+ MipiClockHsP => CamHsClkP,
+ MipiClockLpN => CamLpClkN,
+ MipiClockLpP => CamLpClkP,
+ MipiDataHsN => CamHsDataN,
+ MipiDataHsP => CamHsDataP,
+ MipiDataLpN => CamLpDataN,
+ MipiDataLpP => CamLpDataP
);
end block ProcessingSystemxB;
@@ -433,47 +392,16 @@ begin
Led22V5GxAS : Led22V5GxSO <= RgbLedsCtrlPortxD(4);
Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
+ CamPwupxAS : CamPwup <= CamPwupxS(0);
+ CamGpioxAS : CamGpioBta <= CamGpioxS(0);
+
-- Camera I2C SDA tri-state buffer
- LVDS2V5Bottom5PxSIO <= I2c1SdaOxS when I2c1SdaTxS='0' else 'Z';
- I2c1SdaIxS <= LVDS2V5Bottom5PxSIO;
--- LVDS2V5Bottom5PxSIO <= GPIO0OxD(2) when GPIO0TxD(2)='0' else 'Z';
--- GPIO0IxD(2) <= LVDS2V5Bottom5PxSIO;
+ CamI2cSda <= I2c1SdaOxS when I2c1SdaTxS='0' else 'Z';
+ I2c1SdaIxS <= CamI2cSda;
-- Camera I2C SCL tri-state buffer
- LVDS2V5Bottom5NxSIO <= I2c1SclOxS when I2c1SclTxS='0' else 'Z';
- I2c1SclIxS <= LVDS2V5Bottom5NxSIO;
--- LVDS2V5Bottom5NxSIO <= GPIO0OxD(3) when GPIO0TxD(3)='0' else 'Z';
--- GPIO0IxD(3) <= LVDS2V5Bottom5NxSIO;
-
- -- DMA nReset tri-state buffer (GPIO0_0)
- DmaRstnxS <= GPIO0OxD(0) when GPIO0TxD(0)='0' else 'Z';
- GPIO0IxD(0) <= DmaRstnxS;
-
- -- CSI2 nReset tri-state buffer (GPIO0_1)
- Csi2RstnxS <= GPIO0OxD(1) when GPIO0TxD(1)='0' else 'Z';
- GPIO0IxD(1) <= Csi2RstnxS;
-
- -- Camera PWUP tri-state buffer (GPIO0_4)
- LVDS2V5Bottom6NxSIO <= GPIO0OxD(4) when GPIO0TxD(4)='0' else 'Z';
- GPIO0IxD(4) <= LVDS2V5Bottom6NxSIO;
-
- -- Camera GPIO tri-state buffer (GPIO0_5)
- LVDS2V5Bottom6PxSIO <= GPIO0OxD(5) when GPIO0TxD(5)='0' else 'Z';
- GPIO0IxD(5) <= LVDS2V5Bottom6PxSIO;
-
- -- MIPI signal assignement
- MipiPhyClockHsNxAS : MipiClockHsNxC <= Clk2V5BottomNxCI;
- MipiPhyClockHsPxAS : MipiClockHsPxC <= Clk2V5BottomPxCI;
- MipiPhyClockLpNxAS : MipiClockLpNxC <= LVDS2V5Bottom4NxSIO;
- MipiPhyClockLpPxAS : MipiClockLpPxC <= LVDS2V5Bottom4PxSIO;
- MipiPhyDataHsN0xAS : MipiDataHsNxD(0) <= LVDS2V5Bottom0NxSIO;
- MipiPhyDataHsP0xAS : MipiDataHsPxD(0) <= LVDS2V5Bottom0PxSIO;
- MipiPhyDataLpN0xAS : MipiDataLpNxD(0) <= LVDS2V5Bottom1NxSIO;
- MipiPhyDataLpP0xAS : MipiDataLpPxD(0) <= LVDS2V5Bottom1PxSIO;
- MipiPhyDataHsN1xAS : MipiDataHsNxD(1) <= LVDS2V5Bottom2NxSIO;
- MipiPhyDataHsP1xAS : MipiDataHsPxD(1) <= LVDS2V5Bottom2PxSIO;
- MipiPhyDataLpN1xAS : MipiDataLpNxD(1) <= LVDS2V5Bottom3NxSIO;
- MipiPhyDataLpP1xAS : MipiDataLpPxD(1) <= LVDS2V5Bottom3PxSIO;
+ CamI2cScl <= I2c1SclOxS when I2c1SclTxS='0' else 'Z';
+ I2c1SclIxS <= CamI2cScl;
end block EntityIOxB;
diff --git a/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
index aec32d0d3650f606ea1a8b097e8e37193e5a2fbc..558e190fd50e9abefc67a43d691a400e2f220612 100644
--- a/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
@@ -68,7 +68,10 @@ entity scalp_mipi_zynqps_wrapper is
WrDataxDO : out std_logic_vector (31 downto 0);
WrValidxSO : out std_logic;
RgbLedsCtrlPortxDO : out std_logic_vector (31 downto 0);
- -- I2C1 interface
+ -- Camera GPIOs
+ CamPwup : out std_logic_vector (0 downto 0);
+ CamGpio : out std_logic_vector (0 downto 0);
+ -- Camera I2C interface
I2c1SdaxSI : in std_logic;
I2c1SdaxSO : out std_logic;
I2c1SdaxST : out std_logic;
@@ -76,9 +79,9 @@ entity scalp_mipi_zynqps_wrapper is
I2c1SclxSO : out std_logic;
I2c1SclxST : out std_logic;
-- GPIO0 interface
- GPIO0xDI : in std_logic_vector (31 downto 0);
- GPIO0xDO : out std_logic_vector (31 downto 0);
- GPIO0xDT : out std_logic_vector (31 downto 0);
+-- GPIO0xDI : in std_logic_vector (31 downto 0);
+-- GPIO0xDO : out std_logic_vector (31 downto 0);
+-- GPIO0xDT : out std_logic_vector (31 downto 0);
-- MIPI interface
MipiClockHsN : in std_logic;
MipiClockHsP : in std_logic;
@@ -87,9 +90,17 @@ entity scalp_mipi_zynqps_wrapper is
MipiDataHsN : in std_logic_vector (1 downto 0);
MipiDataHsP : in std_logic_vector (1 downto 0);
MipiDataLpN : in std_logic_vector (1 downto 0);
- MipiDataLpP : in std_logic_vector (1 downto 0);
- Csi2Rstn : in std_logic;
- DmaRstn : in std_logic
+ MipiDataLpP : in std_logic_vector (1 downto 0)
+-- FakeMipiClockHsN : in std_logic;
+-- FakeMipiClockHsP : in std_logic;
+-- FakeMipiClockLpN : in std_logic;
+-- FakeMipiClockLpP : in std_logic;
+-- FakeMipiDataHsN : in std_logic_vector (1 downto 0);
+-- FakeMipiDataHsP : in std_logic_vector (1 downto 0);
+-- FakeMipiDataLpN : in std_logic_vector (1 downto 0);
+-- FakeMipiDataLpP : in std_logic_vector (1 downto 0);
+-- Csi2Rstn : in std_logic;
+-- DmaRstn : in std_logic
);
end scalp_mipi_zynqps_wrapper;
@@ -135,15 +146,14 @@ begin
WrDataxDO => WrDataxDO,
WrValidxSO => WrValidxSO,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO,
+ CamPwup => CamPwup,
+ CamGpio => CamGpio,
I2C1_SDA_I => I2c1SdaxSI,
I2C1_SDA_O => I2c1SdaxSO,
I2C1_SDA_T => I2c1SdaxST,
I2C1_SCL_I => I2c1SclxSI,
I2C1_SCL_O => I2c1SclxSO,
I2C1_SCL_T => I2c1SclxST,
- GPIO_0_TRI_I => GPIO0xDI,
- GPIO_0_TRI_O => GPIO0xDO,
- GPIO_0_TRI_T => GPIO0xDT,
MIPI_clk_hs_n => MipiClockHsN,
MIPI_clk_hs_p => MipiClockHsP,
MIPI_clk_lp_n => MipiClockLpN,
@@ -151,9 +161,17 @@ begin
MIPI_data_hs_n => MipiDataHsN,
MIPI_data_hs_p => MipiDataHsP,
MIPI_data_lp_n => MipiDataLpN,
- MIPI_data_lp_p => MipiDataLpP,
- Csi2Rstn => Csi2Rstn,
- DmaRstn => DmaRstn
+ MIPI_data_lp_p => MipiDataLpP
+-- FAKEMIPI_clk_hs_n => FakeMipiClockHsN,
+-- FAKEMIPI_clk_hs_p => FakeMipiClockHsP,
+-- FAKEMIPI_clk_lp_n => FakeMipiClockLpN,
+-- FAKEMIPI_clk_lp_p => FakeMipiClockLpP,
+-- FAKEMIPI_data_hs_n => FakeMipiDataHsN,
+-- FAKEMIPI_data_hs_p => FakeMipiDataHsP,
+-- FAKEMIPI_data_lp_n => FakeMipiDataLpN,
+-- FAKEMIPI_data_lp_p => FakeMipiDataLpP,
+-- Csi2Rstn => Csi2Rstn,
+-- DmaRstn => DmaRstn
);
end arch;
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
index c7be7808183a62b08599ec33c9b6d697b78de3f0..71ae641eb2888e06fae7d19426dc5cefef113a55 100644
--- a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
@@ -59,7 +59,7 @@ set run_remote_bd_flow 1
if { $run_remote_bd_flow == 1 } {
# Set the reference directory for source file relative paths (by default
# the value is script directory path)
- set origin_dir .
+ set origin_dir ./Documents/recherche/scalp/scalp_firmware/designs/vivado/scalp_mipi/2020.2/lin64/.scripts
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
@@ -122,9 +122,9 @@ set bCheckIPsPassed 1
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
-xilinx.com:ip:axi_data_fifo:2.1\
xilinx.com:ip:axis_subset_converter:1.1\
xilinx.com:ip:clk_wiz:6.0\
+xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:mipi_csi2_rx_subsystem:5.1\
@@ -203,16 +203,14 @@ proc create_root_design { parentCell } {
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
- set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ]
-
set I2C1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C1 ]
set MIPI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:mipi_phy_rtl:1.0 MIPI ]
# Create ports
- set Csi2Rstn [ create_bd_port -dir I -type rst Csi2Rstn ]
- set DmaRstn [ create_bd_port -dir I -type rst DmaRstn ]
+ set CamGpio [ create_bd_port -dir O -from 0 -to 0 CamGpio ]
+ set CamPwup [ create_bd_port -dir O -from 0 -to 0 CamPwup ]
set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
@@ -231,14 +229,6 @@ proc create_root_design { parentCell } {
set WrDataxDO [ create_bd_port -dir O -from 31 -to 0 WrDataxDO ]
set WrValidxSO [ create_bd_port -dir O WrValidxSO ]
- # Create instance: axi_data_fifo_0, and set properties
- set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {64} \
- CONFIG.READ_FIFO_DELAY {1} \
- CONFIG.READ_FIFO_DEPTH {512} \
- ] $axi_data_fifo_0
-
# Create instance: axi_mem_intercon, and set properties
set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
set_property -dict [ list \
@@ -252,7 +242,7 @@ proc create_root_design { parentCell } {
CONFIG.M_HAS_TLAST {1} \
CONFIG.M_HAS_TREADY {1} \
CONFIG.M_HAS_TSTRB {1} \
- CONFIG.M_TDATA_NUM_BYTES {3} \
+ CONFIG.M_TDATA_NUM_BYTES {6} \
CONFIG.M_TDEST_WIDTH {1} \
CONFIG.M_TID_WIDTH {1} \
CONFIG.M_TUSER_WIDTH {1} \
@@ -260,38 +250,55 @@ proc create_root_design { parentCell } {
CONFIG.S_TDATA_NUM_BYTES {2} \
CONFIG.S_TDEST_WIDTH {10} \
CONFIG.S_TUSER_WIDTH {1} \
- CONFIG.TDATA_REMAP {8'b00000000,tdata[15:0]} \
+ CONFIG.TDATA_REMAP {32'b00000000000000000000000000000000,tdata[15:0]} \
CONFIG.TDEST_REMAP {tdest[0:0]} \
- CONFIG.TKEEP_REMAP {3'b111} \
+ CONFIG.TKEEP_REMAP {6'b111111} \
CONFIG.TLAST_REMAP {tlast[0]} \
- CONFIG.TSTRB_REMAP {3'b111} \
+ CONFIG.TSTRB_REMAP {6'b111111} \
CONFIG.TUSER_REMAP {tuser[0:0]} \
] $axis_subset_converter_0
# Create instance: clk_wiz_0, and set properties
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
set_property -dict [ list \
- CONFIG.CLKOUT1_DRIVES {BUFG} \
CONFIG.CLKOUT1_JITTER {109.241} \
CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
- CONFIG.CLKOUT2_DRIVES {BUFG} \
- CONFIG.CLKOUT3_DRIVES {BUFG} \
- CONFIG.CLKOUT4_DRIVES {BUFG} \
- CONFIG.CLKOUT5_DRIVES {BUFG} \
- CONFIG.CLKOUT6_DRIVES {BUFG} \
- CONFIG.CLKOUT7_DRIVES {BUFG} \
- CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \
- CONFIG.MMCM_CLKFBOUT_MULT_F {8} \
- CONFIG.MMCM_CLKOUT0_DIVIDE_F {5} \
- CONFIG.MMCM_COMPENSATION {BUF_IN} \
- CONFIG.OVERRIDE_MMCM {true} \
- CONFIG.PRIMITIVE {PLL} \
+ CONFIG.CLKOUT2_JITTER {198.991} \
+ CONFIG.CLKOUT2_PHASE_ERROR {249.865} \
+ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {300} \
+ CONFIG.CLKOUT2_USED {false} \
+ CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
+ CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
+ CONFIG.MMCM_CLKOUT1_DIVIDE {1} \
+ CONFIG.MMCM_COMPENSATION {ZHOLD} \
+ CONFIG.MMCM_DIVCLK_DIVIDE {1} \
+ CONFIG.NUM_OUT_CLKS {1} \
+ CONFIG.OVERRIDE_MMCM {false} \
CONFIG.RESET_PORT {resetn} \
CONFIG.RESET_TYPE {ACTIVE_LOW} \
CONFIG.USE_LOCKED {false} \
] $clk_wiz_0
+ # Create instance: emio_0, and set properties
+ set emio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 emio_0 ]
+
+ # Create instance: emio_4, and set properties
+ set emio_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 emio_4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $emio_4
+
+ # Create instance: emio_5, and set properties
+ set emio_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 emio_5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $emio_5
+
# Create instance: gnd_constant, and set properties
set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
set_property -dict [ list \
@@ -309,9 +316,15 @@ proc create_root_design { parentCell } {
set_property -dict [ list \
CONFIG.CMN_NUM_LANES {2} \
CONFIG.CMN_PXL_FORMAT {YUV422_8bit} \
+ CONFIG.CSI_BUF_DEPTH {4096} \
+ CONFIG.C_CAL_MODE {FIXED} \
CONFIG.C_DPHY_LANES {2} \
- CONFIG.C_EXDES_BOARD {ZCU102} \
- CONFIG.DPY_EN_REG_IF {false} \
+ CONFIG.C_HS_LINE_RATE {336} \
+ CONFIG.C_HS_SETTLE_NS {164} \
+ CONFIG.C_IDLY_TAP {2} \
+ CONFIG.C_SHARE_IDLYCTRL {true} \
+ CONFIG.DPY_EN_REG_IF {true} \
+ CONFIG.DPY_LINE_RATE {336} \
] $mipi_csi2_rx_subsyst_0
# Create instance: processing_system7_0, and set properties
@@ -740,11 +753,19 @@ proc create_root_design { parentCell } {
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {500.000000} \
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
CONFIG.PCW_UIPARAM_DDR_BL {8} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25} \
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
CONFIG.PCW_UIPARAM_DDR_CL {7} \
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
@@ -790,15 +811,11 @@ proc create_root_design { parentCell } {
set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
set_property -dict [ list \
CONFIG.C_MON_TYPE {INTERFACE} \
- CONFIG.C_NUM_MONITOR_SLOTS {3} \
- CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:gpio_rtl:1.0} \
- CONFIG.C_SLOT_0_TYPE {0} \
- CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:iic_rtl:1.0} \
- CONFIG.C_SLOT_1_TYPE {0} \
- CONFIG.C_SLOT_2_APC_EN {0} \
- CONFIG.C_SLOT_2_AXI_DATA_SEL {1} \
- CONFIG.C_SLOT_2_AXI_TRIG_SEL {1} \
- CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_NUM_MONITOR_SLOTS {1} \
+ CONFIG.C_SLOT_0_APC_EN {0} \
+ CONFIG.C_SLOT_0_AXI_DATA_SEL {1} \
+ CONFIG.C_SLOT_0_AXI_TRIG_SEL {1} \
+ CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
] $system_ila_0
# Create instance: util_vector_logic_0, and set properties
@@ -820,18 +837,17 @@ proc create_root_design { parentCell } {
# Create instance: v_frmbuf_wr_0, and set properties
set v_frmbuf_wr_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_frmbuf_wr:2.2 v_frmbuf_wr_0 ]
set_property -dict [ list \
- CONFIG.AXIMM_ADDR_WIDTH {32} \
- CONFIG.AXIMM_DATA_WIDTH {64} \
- CONFIG.C_M_AXI_MM_VIDEO_DATA_WIDTH {64} \
- CONFIG.HAS_BGR8 {1} \
+ CONFIG.AXIMM_DATA_WIDTH {128} \
+ CONFIG.C_M_AXI_MM_VIDEO_DATA_WIDTH {128} \
+ CONFIG.HAS_BGR8 {0} \
CONFIG.HAS_RGB8 {0} \
CONFIG.HAS_UYVY8 {1} \
- CONFIG.HAS_YUYV8 {0} \
- CONFIG.HAS_Y_UV8 {0} \
- CONFIG.MAX_COLS {640} \
- CONFIG.MAX_NR_PLANES {1} \
- CONFIG.MAX_ROWS {480} \
- CONFIG.SAMPLES_PER_CLOCK {1} \
+ CONFIG.HAS_YUYV8 {1} \
+ CONFIG.HAS_Y_UV8 {1} \
+ CONFIG.MAX_COLS {3840} \
+ CONFIG.MAX_NR_PLANES {2} \
+ CONFIG.MAX_ROWS {2160} \
+ CONFIG.SAMPLES_PER_CLOCK {2} \
] $v_frmbuf_wr_0
# Create instance: vio_0, and set properties
@@ -843,30 +859,22 @@ proc create_root_design { parentCell } {
# Create interface connections
connect_bd_intf_net -intf_net MIPI_1 [get_bd_intf_ports MIPI] [get_bd_intf_pins mipi_csi2_rx_subsyst_0/mipi_phy_if]
- connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_mem_intercon/S00_AXI]
connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins axis_subset_converter_0/M_AXIS] [get_bd_intf_pins v_frmbuf_wr_0/s_axis_video]
connect_bd_intf_net -intf_net mipi_csi2_rx_subsyst_0_video_out [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins mipi_csi2_rx_subsyst_0/video_out]
-connect_bd_intf_net -intf_net [get_bd_intf_nets mipi_csi2_rx_subsyst_0_video_out] [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_2_AXIS]
+connect_bd_intf_net -intf_net [get_bd_intf_nets mipi_csi2_rx_subsyst_0_video_out] [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets mipi_csi2_rx_subsyst_0_video_out]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
- connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
-connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_GPIO_0] [get_bd_intf_ports GPIO_0] [get_bd_intf_pins system_ila_0/SLOT_0_GPIO]
- set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets processing_system7_0_GPIO_0]
connect_bd_intf_net -intf_net processing_system7_0_IIC_1 [get_bd_intf_ports I2C1] [get_bd_intf_pins processing_system7_0/IIC_1]
-connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get_bd_intf_ports I2C1] [get_bd_intf_pins system_ila_0/SLOT_1_IIC]
- set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets processing_system7_0_IIC_1]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins mipi_csi2_rx_subsyst_0/csirxss_s_axi] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins v_frmbuf_wr_0/s_axi_CTRL]
- connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_data_fifo_0/S_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
+ connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
# Create port connections
- connect_bd_net -net Csi2Rstn_1 [get_bd_ports Csi2Rstn] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aresetn]
- connect_bd_net -net DmaRstn_1 [get_bd_ports DmaRstn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axis_subset_converter_0/aresetn]
connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
connect_bd_net -net RdDataxDI_0_1 [get_bd_ports RdDataxDI] [get_bd_pins scalp_axi4lite_0/RdDataxDI]
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
@@ -874,12 +882,13 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
connect_bd_net -net mipi_csi2_rx_subsyst_0_csirxss_csi_irq [get_bd_pins irq_xlconcat/In1] [get_bd_pins mipi_csi2_rx_subsyst_0/csirxss_csi_irq]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins vio_0/clk]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
+ connect_bd_net -net processing_system7_0_GPIO_O [get_bd_pins emio_0/Din] [get_bd_pins emio_4/Din] [get_bd_pins emio_5/Din] [get_bd_pins processing_system7_0/GPIO_O]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
- connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn]
connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO]
connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
@@ -891,6 +900,9 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net v_frmbuf_wr_0_interrupt [get_bd_pins irq_xlconcat/In2] [get_bd_pins v_frmbuf_wr_0/interrupt]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
+ connect_bd_net -net xlslice_0_Dout [get_bd_pins axis_subset_converter_0/aresetn] [get_bd_pins emio_0/Dout] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
+ connect_bd_net -net xlslice_1_Dout [get_bd_ports CamPwup] [get_bd_pins emio_4/Dout]
+ connect_bd_net -net xlslice_2_Dout [get_bd_ports CamGpio] [get_bd_pins emio_5/Dout]
# Create address segments
assign_bd_address -offset 0x43C20000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg] -force
@@ -899,11 +911,6 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
assign_bd_address -offset 0x43C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs v_frmbuf_wr_0/s_axi_CTRL/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
- # Exclude Address Segments
- exclude_bd_addr_seg -offset 0x43C20000 -range 0x00001000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg]
- exclude_bd_addr_seg -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr]
- exclude_bd_addr_seg -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr]
-
# Restore current instance
current_bd_instance $oldCurInst