diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/doc/aurora_8b10b_v11_1_changelog.txt b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/doc/aurora_8b10b_v11_1_changelog.txt
deleted file mode 100755
index 7216ee36fdca3a760aa5afc7696e627329ff4e39..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/doc/aurora_8b10b_v11_1_changelog.txt
+++ /dev/null
@@ -1,294 +0,0 @@
-2019.2:
- * Version 11.1 (Rev. 8)
- * Revision change in one or more subcores
-
-2019.1.3:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1.2:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1.1:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1:
- * Version 11.1 (Rev. 7)
- * General: Added support for AKINTEX7 devices
- * Revision change in one or more subcores
-
-2018.3.1:
- * Version 11.1 (Rev. 6)
- * No changes
-
-2018.3:
- * Version 11.1 (Rev. 6)
- * General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
- * General: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
- * Revision change in one or more subcores
-
-2018.2:
- * Version 11.1 (Rev. 5)
- * Bug Fix: Fixed display only issue showing improper clock frequencies for tx_out_clk and sync_clk in IPI flow for GTP devices.
- * Revision change in one or more subcores
-
-2018.1:
- * Version 11.1 (Rev. 4)
- * Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection
- * Bug Fix: Fixed a bug that generated unexpected error messages during re-customization of IP in IP Integrator
- * Other: Added support for Artix-7 XA7A12TCPG238/CSG325 and XA7A25TCPG238/CSG325 devices
- * Revision change in one or more subcores
-
-2017.4:
- * Version 11.1 (Rev. 3)
- * General: Added support for CPG238 packages in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * Revision change in one or more subcores
-
-2017.3:
- * Version 11.1 (Rev. 2)
- * General: GTP attribute update in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * General: Standard CC logic is enabled after lane-up itself instead of waiting till channel-up condition
- * General: Added optional parameter C_DOUBLE_GTRXRESET to assert additional reset for handling errors during lane initialisation in duplex links with very high ppm differences
- * General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides
- * Revision change in one or more subcores
-
-2017.2:
- * Version 11.1 (Rev. 1)
- * Bug Fix: Unused gtrxresetseq drp signals removed from TX-simplex based designs
- * Other: UltraScale GT Wizard version upgrade.
-
-2017.1:
- * Version 11.1
- * New Feature: US GT Wizard Instance can be brought out of Aurora IP for UltraScale devices
- * Other: gt_powergood from US GT Wizard is made an output port on Aurora core when GT is inside Aurora IP
- * Other: gt_powergood from US GT Wizard is brought to gt wrapper in example design when the GT is in example design, outside Aurora IP
- * Revision change in one or more subcores
-
-2016.4:
- * Version 11.0 (Rev. 7)
- * General: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti devices
- * Revision change in one or more subcores
-
-2016.3:
- * Version 11.0 (Rev. 6)
- * Bug Fix: Fixed issue in failure due to floating point precision difference of gt_refclk in validate BD design in IPI
- * Bug Fix: Fixed TXDIFFCTRL and DMONITOROUT port widths for UltraScale devices in IP symbol
- * Feature Enhancement: Added Advanced RX GT Options selection in GUI
- * Other: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * Revision change in one or more subcores
-
-2016.2:
- * Version 11.0 (Rev. 5)
- * Fixed Artix7 periodic channel up toggle issue
- * Revision change in one or more subcores
-
-2016.1:
- * Version 11.0 (Rev. 4)
- * Fixed preserving Equalizer selection issue when additional transceiver ports option is enabled
- * Adjusted line rate and associated frequency limits for -1,-1H,1HV,-1L,-1LV, -2LV speed grade devices to match UltraScale FPGAs Data Sheet
- * Revision change in one or more subcores
-
-2015.4.2:
- * Version 11.0 (Rev. 3)
- * No changes
-
-2015.4.1:
- * Version 11.0 (Rev. 3)
- * No changes
-
-2015.4:
- * Version 11.0 (Rev. 3)
- * Added support for new speedgrades of XQ7K325T and XQ7K410T devices
- * Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices
- * Added support for new speedgrade of XQ7A050T, XQ7A100T and XQ7A200T devices
- * Revision change in one or more subcores
-
-2015.3:
- * Version 11.0 (Rev. 2)
- * Updated RTL to fix CDC warnings
- * Added support for UltraScale+ devices
- * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
-
-2015.2.1:
- * Version 11.0 (Rev. 1)
- * No changes
-
-2015.2:
- * Version 11.0 (Rev. 1)
- * Added support for XQ7VX690T, XQ7Z045 and XQ7Z100 devices
- * BUFG removed on DRP Clock input
- * TXPMARESETDONE used in rxstartupfsm for GTP RX-onlySimplex configuration
- * set_false_path constrain on synchronizers updated
-
-2015.1:
- * Version 11.0
- * Added support for 7 Series devices with FFV and FBV Pb-Free RoHs package
- * Added txinhibit and pcsrsvdin optional transceiver control and status ports
- * Both reset and gt_reset ports made asynchronous to the core
- * Standard CC module made part of IP, do_cc and warn_cc ports removed
- * Flow control ports grouped into AXI4 Stream interfaces
- * Control and status ports are grouped as display interfaces
- * Added support for single ended clocking option to INIT_CLK and GTREFCLK
- * Added support for contiguous lane selection for Ultrascale devices
- * CRC resource utilization optimized
- * GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator
- * Line rate value restricted to 4 decimal digits for Ultrascale devices
- * INIT clock frequency value restricted to 6 decimal digits
-
-2014.4.1:
- * Version 10.3 (Rev. 2)
- * Ultrascale GT Wizard version updated
-
-2014.4:
- * Version 10.3 (Rev. 1)
- * Added support for new XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices
- * Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices
- * Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices
- * BUFG added to DRP Clock input
- * Line rate range for -2L speed grade 1.0V Artix devices updated to 6.25Gbps
- * Location constraint changed for Xilinx Evaluation platform boards
-
-2014.3:
- * Version 10.3
- * Ultrascale GT Wizard version updated
- * Added support for new Ultrascale devices
- * Added support for XQ7A50 devices
- * Added support for XA7Z030 devices
- * Added support for user configurable DRP clock and INIT clock through IP GUI
- * Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup
- * set_max_delay constrain changed to set_false_path constrains to destination flops
- * XDCs compliant with updated timing constraining guidelines
- * Added support for Xilinx Evaluation platform boards
- * User selectable option enabled for GT DRP interface in IPI systems
- * Added support for auto propagate to INIT and DRP clock in IPI systems
- * Fixed gt_dmonitorout_out data width mismatch issue for Zynq devices
- * Differential INIT clock input added to Ultrascale example design
- * Addressed CPLL power down circuit requirement for 7 series Transceivers - refer AR
- * GT startup fsms updated to be complain with 7 Series GT Wizard
- * Addressed update to GTH/GTP Production RX reset sequence implementation- refer AR
- * Parameter declaration issue with IES simulator addressed
-
-2014.2:
- * Version 10.2 (Rev. 1)
- * Ultrascale GT Wizard version change
- * Added support for XQ7Z045 RF900 devices
- * Fixed hold violation timing issues in Ultrascale device based designs
- * Updated channel bonding levels logic for >= 13 lanes in 4 byte mode
- * Fixed gt0_dmonitorout_out port width for GTX devices in transceiver debug ports
- * Free running INIT CLK is connected to VIO core in example design
- * Fixed latch inference issue in crc modules for VHDL designs
- * Updated CLK_COR_MIN_LAT and CLK_COR_MAX_LAT values for 16-GT (GTHE3_CHANNEL) in Ultrascale device
-
-2014.1:
- * Version 10.2
- * Added support for Ultrascale devices
- * Added support for XC7Z015, XC7A50T, XC7A35T devices
- * Added support for automotive aartix XA7A35, XA7A50T, XA7A75T & XA7A100T devices
- * Enhanced support for IP Integrator
- * Added Little endian support for data & flow control interfaces as non-default GUI selectable option
- * Fixed VHDL syntax issue on rxpmaresetdone_t signal for 7-series based designs
- * Updated OOC XDC with all the available clocks for the selected IP configuration
- * Fixed TXCRC and RXCRC modules to operate upon valid data and report correct CRC status
- * Updated core reset logic with tx_lock synchronization
- * Updated the simplex timer values for 7-series production silicon logic updates
- * Updated the hot-plug logic to handle clock domain crossing efficiently
- * Added recovery mechanism for channel bonding failure
-
-2013.4:
- * Version 10.1
- * Increased the number of optional transceiver control and status ports
-
-2013.3:
- * Version 10.0
- * Added support for XC7A75T device
- * Added startup FSM integration for 7-series GT reset sequence
- * Added GUI option to include or exclude Vivado Labtools support for debug
- * Updated line rate for A7 wire bond package devices for speed grade -2 and -3
- * Added GUI option to include or exclude shareable logic resources in the core. For details, refer to Migrating section of Product Guide - pg046-aurora-8b10b.pdf
- * Added optional transceiver control and status ports - Refer to pg046-aurora-8b10b.pdf
- * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
- * Reduced warnings in synthesis and simulation
- * Added support for Cadence IES and Synopsys VCS simulators
- * Added support for IP Integrator level 0
-
-2013.2:
- * Version 9.1
- * Artix-7 GTP and Virtex-7 GTH production attributes updates
- * XDC constraints processing order changed
- * Update for UFC packet drop in back to back data transfer
- * XQ7Z030-RB484 device support
-
-2013.1:
- * Version 9.0
- * Lower case IP level ports
- * Hot-plug timer update
- * CDC fixes
- * New reset sequence for GTRXRESET in Artix-7 GTP Production silicon
- * New reset sequence for GTRXRESET in Virtex-7 GTH Production silicon
- * Out-of-context (OOC) flow support
- * Zynq-7000 family support
-
-2012.4:
- * Version 8.3 (Rev. 1)
- * Artix-7 IES silicon support
- * Autoupgrade feature
-
-2012.3:
- * Version 8.3
- * Artix-7 family support
-
-2012.2:
- * Version 8.2
- * Virtex-7 HT device support
- * CRC feature addition
- * Hot-plug support for 7-series
- * XSIM simulator support
- * Native Vivado release
-
-(c) Copyright 2010 - 2019 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.dcp b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.dcp
deleted file mode 100644
index 20806143be593229b559c33a1cb229f3e4f9b61f..0000000000000000000000000000000000000000
Binary files a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.dcp and /dev/null differ
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.vhd
deleted file mode 100644
index 40588373b6e583619f73a7c4e410b3f48f41ff43..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.vhd
+++ /dev/null
@@ -1,346 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
-------------------------------------------------------------------------------/
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_misc.all;
- use IEEE.numeric_std.all;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
-
-entity east_channel is
- port (
- -- AXI TX Interface
-
- s_axi_tx_tdata : in std_logic_vector(0 to 31);
-
- s_axi_tx_tvalid : in std_logic;
- s_axi_tx_tready : out std_logic;
-
- s_axi_tx_tkeep : in std_logic_vector(0 to 3);
-
- s_axi_tx_tlast : in std_logic;
-
-
- -- AXI RX Interface
-
- m_axi_rx_tdata : out std_logic_vector(0 to 31);
-
- m_axi_rx_tvalid : out std_logic;
-
- m_axi_rx_tkeep : out std_logic_vector(0 to 3);
-
- m_axi_rx_tlast : out std_logic;
-
-
- -- User Flow Control TX Interface
- s_axi_ufc_tx_tvalid : in std_logic;
-
- s_axi_ufc_tx_tdata : in std_logic_vector(0 to 2);
- s_axi_ufc_tx_tready : out std_logic;
-
-
- -- User Flow Control RX Inteface
-
- m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31);
- m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3);
- m_axi_ufc_rx_tvalid : out std_logic;
- m_axi_ufc_rx_tlast : out std_logic;
-
-
-
- -- GT Serial I/O
- rxp : in std_logic_vector(0 downto 0);
- rxn : in std_logic_vector(0 downto 0);
-
- txp : out std_logic_vector(0 downto 0);
- txn : out std_logic_vector(0 downto 0);
-
- -- GT Reference Clock Interface
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
-
- frame_err : out std_logic;
- hard_err : out std_logic;
- soft_err : out std_logic;
- channel_up : out std_logic;
- lane_up : out std_logic_vector(0 downto 0);
-
-
-
-
- -- System Interface
- user_clk : in std_logic;
- sync_clk : in std_logic;
- reset : in std_logic;
-
- power_down : in std_logic;
- loopback : in std_logic_vector(2 downto 0);
- gt_reset : in std_logic;
- tx_lock : out std_logic;
- sys_reset_out : out std_logic;
- init_clk_in : in std_logic;
- tx_resetdone_out : out std_logic;
- rx_resetdone_out : out std_logic;
- link_reset_out : out std_logic;
-
- --DRP Ports
-
- drpclk_in : in std_logic;
- drpaddr_in : in std_logic_vector(8 downto 0);
- drpdi_in : in std_logic_vector(15 downto 0);
- drpdo_out : out std_logic_vector(15 downto 0);
- drpen_in : in std_logic;
- drprdy_out : out std_logic;
- drpwe_in : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- tx_out_clk : out std_logic;
- pll_not_locked : in std_logic
-
- );
-
-end east_channel;
-
-
-architecture STRUCTURE of east_channel is
- attribute core_generation_info : string;
- attribute core_generation_info of STRUCTURE : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- component east_channel_core
- port (
- -- TX Stream Interface
- S_AXI_TX_TDATA : in std_logic_vector(0 to 31);
- S_AXI_TX_TKEEP : in std_logic_vector(0 to 3);
- S_AXI_TX_TVALID : in std_logic;
- S_AXI_TX_TREADY : out std_logic;
- S_AXI_TX_TLAST : in std_logic;
-
- -- RX Stream Interface
- M_AXI_RX_TDATA : out std_logic_vector(0 to 31);
- M_AXI_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_RX_TVALID : out std_logic;
- M_AXI_RX_TLAST : out std_logic;
- -- User Flow Control TX Interface
-
- S_AXI_UFC_TX_REQ : in std_logic;
- S_AXI_UFC_TX_MS : in std_logic_vector(0 to 2);
- S_AXI_UFC_TX_ACK : out std_logic;
-
- -- User Flow Control RX Inteface
-
- M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31);
- M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_UFC_RX_TVALID : out std_logic;
- M_AXI_UFC_RX_TLAST : out std_logic;
-
- -- GTX Serial I/O
- RXP : in std_logic;
- RXN : in std_logic;
- TXP : out std_logic;
- TXN : out std_logic;
-
- -- GT Reference Clock Interface
-
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
- HARD_ERR : out std_logic;
- SOFT_ERR : out std_logic;
-
- -- Status
- CHANNEL_UP : out std_logic;
- LANE_UP : out std_logic;
-
-
- FRAME_ERR : out std_logic;
-
-
-
- -- Clock Compensation Control Interface
-
- -- System Interface
-
- USER_CLK : in std_logic;
- SYNC_CLK : in std_logic;
- GT_RESET : in std_logic;
- RESET : in std_logic;
- sys_reset_out : out std_logic;
- POWER_DOWN : in std_logic;
- LOOPBACK : in std_logic_vector(2 downto 0);
- TX_OUT_CLK : out std_logic;
- INIT_CLK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- TX_RESETDONE_OUT : out std_logic;
- RX_RESETDONE_OUT : out std_logic;
- LINK_RESET_OUT : out std_logic;
-
-
- drpclk_in : in std_logic;
- DRPADDR_IN : in std_logic_vector(8 downto 0);
- DRPDI_IN : in std_logic_vector(15 downto 0);
- DRPDO_OUT : out std_logic_vector(15 downto 0);
- DRPEN_IN : in std_logic;
- DRPRDY_OUT : out std_logic;
- DRPWE_IN : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- TX_LOCK : out std_logic
- );
-
- end component;
-
-begin
-
- --*********************************Main Body of Code**********************************
-
- U0 : east_channel_core
- port map (
- -- AXI TX Interface
- s_axi_tx_tdata => s_axi_tx_tdata,
- s_axi_tx_tkeep => s_axi_tx_tkeep,
- s_axi_tx_tvalid => s_axi_tx_tvalid,
- s_axi_tx_tlast => s_axi_tx_tlast,
- s_axi_tx_tready => s_axi_tx_tready,
-
- -- AXI RX Interface
- m_axi_rx_tdata => m_axi_rx_tdata,
- m_axi_rx_tkeep => m_axi_rx_tkeep,
- m_axi_rx_tvalid => m_axi_rx_tvalid,
- m_axi_rx_tlast => m_axi_rx_tlast,
-
- -- User Flow Control TX Interface
- s_axi_ufc_tx_req => s_axi_ufc_tx_tvalid,
- s_axi_ufc_tx_ms => s_axi_ufc_tx_tdata,
- s_axi_ufc_tx_ack => s_axi_ufc_tx_tready,
-
- -- User Flow Control RX Inteface
- m_axi_ufc_rx_tdata => m_axi_ufc_rx_tdata,
- m_axi_ufc_rx_tkeep => m_axi_ufc_rx_tkeep,
- m_axi_ufc_rx_tvalid => m_axi_ufc_rx_tvalid,
- m_axi_ufc_rx_tlast => m_axi_ufc_rx_tlast,
-
- -- GT Serial I/O
- rxp => rxp(0),
- rxn => rxn(0),
- txp => txp(0),
- txn => txn(0),
-
- -- GT Reference Clock Interface
- gt_refclk1 => gt_refclk1,
- -- Error Detection Interface
- frame_err => frame_err,
-
- -- Error Detection Interface
- hard_err => hard_err,
- soft_err => soft_err,
-
- -- Status
- channel_up => channel_up,
- lane_up => lane_up(0),
-
-
-
-
- -- System Interface
- user_clk => user_clk,
- sync_clk => sync_clk,
- reset => reset,
- sys_reset_out => sys_reset_out,
- power_down => power_down,
- loopback => loopback,
- gt_reset => gt_reset,
- tx_lock => tx_lock,
- init_clk_in => init_clk_in,
- pll_not_locked => pll_not_locked,
- tx_resetdone_out => tx_resetdone_out,
- rx_resetdone_out => rx_resetdone_out,
- link_reset_out => link_reset_out,
- drpclk_in => drpclk_in,
- drpaddr_in => drpaddr_in,
- drpen_in => drpen_in,
- drpdi_in => drpdi_in,
- drprdy_out => drprdy_out,
- drpdo_out => drpdo_out,
- drpwe_in => drpwe_in,
---------------------{
- gt_common_reset_out => gt_common_reset_out,
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in => gt0_pll0refclklost_in,
- quad1_common_lock_in => quad1_common_lock_in,
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
---____________________________COMMON PORTS_______________________________}
---------------------}
- tx_out_clk => tx_out_clk
-
- );
-
- end STRUCTURE;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xdc b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xdc
deleted file mode 100644
index 77e993a4484b11b251448b5bca866f08d32556d8..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xdc
+++ /dev/null
@@ -1,67 +0,0 @@
-
-################################################################################
-##
-## (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-## east_channel.xdc generated for xc7z015-clg485-2 device
-# TXOUTCLK Constraint: Value is selected based on the line rate (5.0 Gbps) and lane width (4-Byte)
-create_clock -period 4.0 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt_wrapper_i*east_channel_multi_gt_i*gt0_east_channel_i*gtpe2_i*}]]
-
-
-#### CDC Path #####
-set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *east_channel_cdc_to*}]]
-
-
-####################### GT reference clock LOC (For use in top level design) #######################
-# set_property LOC V5 [get_ports GTPQ0_N]
-# set_property LOC U5 [get_ports GTPQ0_P]
-
-############################### GT LOC (For use in top level design) ###################################
-# set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells aurora_module_i/east_channel_i/U0/gt_wrapper_i/east_channel_multi_gt_i/gt0_east_channel_i/gtpe2_i]
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xml b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xml
deleted file mode 100644
index abdacee429e59cfdd1179573cd34d552de9643b2..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xml
+++ /dev/null
@@ -1,41348 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
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- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>customized_ip</spirit:library>
- <spirit:name>east_channel</spirit:name>
- <spirit:version>1.0</spirit:version>
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- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.USER_CLK.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.USER_CLK.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
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- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.user_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>sync_clk</spirit:name>
- <spirit:displayName>sync_clk</spirit:displayName>
- <spirit:description>sync_clk frequency depends on line rate and user_clk should be shorted with sync_clk</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>sync_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sync_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>init_clk_out</spirit:name>
- <spirit:displayName>init_clk_out</spirit:displayName>
- <spirit:description>200 MHz independent system clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_BUSIF">gt_reset_out</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.init_clk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>sys_reset_out</spirit:name>
- <spirit:displayName>sys_reset_out</spirit:displayName>
- <spirit:description>system reset available when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>sys_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.SYS_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_reset</spirit:name>
- <spirit:displayName>gt_reset</spirit:displayName>
- <spirit:description>GT reset sampled in INIT_CLK and asserted for 6 clock cycles and after assertion of reset</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_reset_out</spirit:name>
- <spirit:displayName>gt_reset_out</spirit:displayName>
- <spirit:description>GT reset generated when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_reset_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>link_reset_out</spirit:name>
- <spirit:displayName>link_reset_out</spirit:displayName>
- <spirit:description>Link reset is generated when IP is not receiving valid data for longer time</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>link_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.LINK_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.LINK_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.link_reset_out" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))!="TX-only_Simplex"">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>init_clk_in</spirit:name>
- <spirit:displayName>init_clk_in</spirit:displayName>
- <spirit:description>Free running System clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_BUSIF">gt_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.init_clk_in" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true)) or ((spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="kintexu") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="virtexu") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="zynquplus") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="kintexuplus")) or (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=true))">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk1_out</spirit:name>
- <spirit:displayName>gt_refclk1_out</spirit:displayName>
- <spirit:description>GT REFCLK1 when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk1_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk2_out</spirit:name>
- <spirit:displayName>gt_refclk2_out</spirit:displayName>
- <spirit:description>GT REFCLK2 when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk2_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None") and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk1</spirit:name>
- <spirit:displayName>~</spirit:displayName>
- <spirit:description>GT REFCLK1 when shared logic is in example design</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk1" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.c_gtwiz_out'))=false)) or (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=true))">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk2</spirit:name>
- <spirit:displayName>~</spirit:displayName>
- <spirit:description>GT REFCLK2 when shared logic is in example design</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk2" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.c_gtwiz_out'))=false)) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None")) or ((spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None") and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=true)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>GT_DIFF_REFCLK1</spirit:name>
- <spirit:displayName>GT_DIFF_REFCLK1</spirit:displayName>
- <spirit:description>Differential GT REFCLK1 and depends on line rate</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GT_DIFF_REFCLK1" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>GT_DIFF_REFCLK2</spirit:name>
- <spirit:displayName>GT_DIFF_REFCLK2</spirit:displayName>
- <spirit:description>Differential GT REFCLK2 and depends on line rate</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GT_DIFF_REFCLK2" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None")) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>INIT_DIFF_CLK</spirit:name>
- <spirit:displayName>INIT_DIFF_CLK</spirit:displayName>
- <spirit:description>200 MHz independent system clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.ASSOCIATED_RESET">gt_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INIT_DIFF_CLK" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rx_system_reset</spirit:name>
- <spirit:displayName>rx_system_reset</spirit:displayName>
- <spirit:description>Aurora IP reset for Simplex-RX config</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rx_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.RX_SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RX_SYSTEM_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_system_reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))="RX-only_Simplex")">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>tx_system_reset</spirit:name>
- <spirit:displayName>tx_system_reset</spirit:displayName>
- <spirit:description>Aurora IP reset for Simplex-TX config</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>tx_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_system_reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))="TX-only_Simplex")">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_drp_clk_in</spirit:name>
- <spirit:displayName>gt_drp_clk_in</spirit:displayName>
- <spirit:description>DRP clock for 7-series transceiver</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>drpclk_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_BUSIF">GT0_DRP_IF:GT1_DRP_IF:GT2_DRP_IF:GT3_DRP_IF:GT4_DRP_IF:GT5_DRP_IF:GT6_DRP_IF:GT7_DRP_IF:GT8_DRP_IF:GT9_DRP_IF:GT10_DRP_IF:GT11_DRP_IF:GT12_DRP_IF:GT13_DRP_IF:GT14_DRP_IF:GT15_DRP_IF</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
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- <spirit:name>C_REFCLK_LOC_P</spirit:name>
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- <spirit:name>c_column_used</spirit:name>
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- <spirit:name>c_ucolumn_used</spirit:name>
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- <spirit:name>c_xpackage</spirit:name>
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- <spirit:name>c_xspeedgrade</spirit:name>
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- <spirit:name>c_lane_width</spirit:name>
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- <spirit:name>C_active_transceiverquads</spirit:name>
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- <spirit:name>c_stream</spirit:name>
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- <spirit:name>backchannel_mode</spirit:name>
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- <spirit:name>c_line_rate</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_line_rate">50000</spirit:value>
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- <spirit:name>c_refclk_frequency</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_refclk_frequency">125000</spirit:value>
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- <spirit:name>cc_refclk_frequency</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.cc_refclk_frequency">125.000</spirit:value>
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- <spirit:name>c_init_clk</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_init_clk">125.0</spirit:value>
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- <spirit:name>drp_freq</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.drp_freq">125.0</spirit:value>
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- <spirit:name>c_gt_loc_1</spirit:name>
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- <spirit:name>c_gt_loc_2</spirit:name>
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- <spirit:name>c_gt_loc_3</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_3">1</spirit:value>
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- <spirit:name>c_gt_loc_4</spirit:name>
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- <spirit:name>c_gt_loc_6</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_6">X</spirit:value>
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- <spirit:name>c_gt_loc_7</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_7">X</spirit:value>
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- <spirit:name>c_gt_loc_8</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_8">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_9">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_10">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_11">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_20">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_24">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_26">X</spirit:value>
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- <spirit:name>c_gt_loc_27</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_27">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_28">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_29">X</spirit:value>
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- <spirit:name>c_gt_loc_31</spirit:name>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_33">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_35">X</spirit:value>
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- <spirit:name>c_gt_loc_36</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_36">X</spirit:value>
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- <spirit:name>c_gt_loc_37</spirit:name>
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- <spirit:modelParameter spirit:dataType="string">
- <spirit:name>c_gt_clock_1</spirit:name>
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- <spirit:modelParameter spirit:dataType="string">
- <spirit:name>c_gt_clock_2</spirit:name>
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- <spirit:modelParameter spirit:dataType="boolean">
- <spirit:name>c_use_chipscope</spirit:name>
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- <spirit:modelParameter spirit:dataType="boolean">
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- <spirit:modelParameter spirit:dataType="boolean">
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- <spirit:modelParameter spirit:dataType="boolean">
- <spirit:name>c_use_crc</spirit:name>
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- <spirit:modelParameter spirit:dataType="boolean">
- <spirit:name>supportlevel</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.supportlevel">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="boolean">
- <spirit:name>c_use_byteswap</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_use_byteswap">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_cpll_fbdiv">4</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
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- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>c_rxoutdiv</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_rxoutdiv">1</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>c_txoutdiv</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_txoutdiv">1</spirit:value>
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- <spirit:modelParameter spirit:dataType="string">
- <spirit:name>user_interface</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.user_interface">AXI_4_Streaming</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
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- <spirit:modelParameter spirit:dataType="integer">
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gtquadcnt">1</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.port7dmonitorout">14</spirit:value>
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- <spirit:modelParameter spirit:dataType="boolean">
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- <spirit:modelParameter spirit:dataType="boolean">
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- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SINGLEEND_GTREFCLK">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="boolean">
- <spirit:name>C_DOUBLE_GTRXRESET</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUBLE_GTRXRESET">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="boolean">
- <spirit:name>C_DOCCPORT_ENABLE</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOCCPORT_ENABLE">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="string">
- <spirit:name>is_board</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.is_board">None</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>USDRPADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USDRPADDR_WIDTH">8</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TXDIFFCTRL_WIDTH">3</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.rx_termination">PROGRAMMABLE</spirit:value>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:file>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:file>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:file>
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- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_14" spirit:choiceRef="choice_list_9bee990d" spirit:order="25">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_14">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_13</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_13" spirit:choiceRef="choice_list_9bee990d" spirit:order="24">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_13">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_12</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_12" spirit:choiceRef="choice_list_9bee990d" spirit:order="23">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_12">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_11</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_11" spirit:choiceRef="choice_list_9bee990d" spirit:order="22">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_11">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_10</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_10" spirit:choiceRef="choice_list_9bee990d" spirit:order="21">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_10">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_9</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_9" spirit:choiceRef="choice_list_9bee990d" spirit:order="20">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_9">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_8</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_8" spirit:choiceRef="choice_list_9bee990d" spirit:order="19">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_8">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_7</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_7" spirit:choiceRef="choice_list_9bee990d" spirit:order="18">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_7">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_6</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_6" spirit:choiceRef="choice_list_9bee990d" spirit:order="17">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_6">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_5</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_5" spirit:choiceRef="choice_list_9bee990d" spirit:order="16">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_5">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_4</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_4" spirit:choiceRef="choice_list_ddf7a1a5" spirit:order="15">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_4">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_3</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_3" spirit:choiceRef="choice_list_628aac54" spirit:order="14">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_3">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_2</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_2" spirit:choiceRef="choice_list_628aac54" spirit:order="13">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_1</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_1" spirit:choiceRef="choice_list_9bee990d" spirit:order="12">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_1">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_CLOCK_1</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_CLOCK_1" spirit:choiceRef="choice_list_852ec6a0" spirit:order="60">GTPQ0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_CLOCK_1">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_CLOCK_2</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_CLOCK_2" spirit:choiceRef="choice_list_6f5507b7" spirit:order="61">None</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_CLOCK_2">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_CHIPSCOPE</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CHIPSCOPE" spirit:order="62">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_CHIPSCOPE">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_START_QUAD</spirit:name>
- <spirit:displayName>Starting GT Quad</spirit:displayName>
- <spirit:description>Select the quad from which lane assignment begins</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_START_QUAD" spirit:choiceRef="choice_list_949abb3f" spirit:order="63">X0Y0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_START_QUAD">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_START_LANE</spirit:name>
- <spirit:displayName>Starting GT Lane</spirit:displayName>
- <spirit:description>Select the starting lane location.Lane Assignment will begin from this Lane of the Quad selected earlier.</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_START_LANE" spirit:choiceRef="choice_list_949abb3f" spirit:order="64">X0Y0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_START_LANE">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_REFCLK_SOURCE</spirit:name>
- <spirit:displayName>GT Refclk Selection</spirit:displayName>
- <spirit:description>Select a reference clock input</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_REFCLK_SOURCE" spirit:choiceRef="choice_list_4d962a2a" spirit:order="65">none</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_REFCLK_SOURCE">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SINGLEEND_INITCLK</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SINGLEEND_INITCLK" spirit:order="1000">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.SINGLEEND_INITCLK">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SINGLEEND_GTREFCLK</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SINGLEEND_GTREFCLK" spirit:order="1001">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.SINGLEEND_GTREFCLK">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_SCRAMBLER</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_SCRAMBLER" spirit:order="63">true</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_SCRAMBLER">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_CRC</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CRC" spirit:order="64">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_CRC">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SupportLevel</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SupportLevel" spirit:choiceRef="choice_pairs_27553a04" spirit:order="65">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.SupportLevel">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TransceiverControl</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.TransceiverControl" spirit:order="66">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TransceiverControl">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_DOUBLE_GTRXRESET</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DOUBLE_GTRXRESET" spirit:order="167">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DOUBLE_GTRXRESET">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_DOCCPORT_ENABLE</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DOCCPORT_ENABLE" spirit:order="167">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DOCCPORT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_EXAMPLE_SIMULATION</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXAMPLE_SIMULATION" spirit:order="67">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_EXAMPLE_SIMULATION">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_BYTESWAP</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_BYTESWAP" spirit:order="67">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_BYTESWAP">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CHANNEL_ENABLE</spirit:name>
- <spirit:displayName>Enable channel</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CHANNEL_ENABLE" spirit:order="68">X0Y0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CHANNEL_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_DRP_IF</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_DRP_IF" spirit:order="68">true</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DRP_IF">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INS_LOSS_NYQ</spirit:name>
- <spirit:displayName>Insertion loss at Nyquist (dB)</spirit:displayName>
- <spirit:description>Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB</spirit:description>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.INS_LOSS_NYQ" spirit:order="69" spirit:minimum="0" spirit:maximum="4294967295">14</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_EQ_MODE</spirit:name>
- <spirit:displayName>Equalization mode</spirit:displayName>
- <spirit:description>Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes.</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_EQ_MODE" spirit:choiceRef="choice_pairs_aa541099" spirit:order="70">AUTO</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_COUPLING</spirit:name>
- <spirit:displayName>Link coupling</spirit:displayName>
- <spirit:description>Select the link coupling</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COUPLING" spirit:choiceRef="choice_list_24871ac1" spirit:order="71">AC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_TERMINATION</spirit:name>
- <spirit:displayName>Termination</spirit:displayName>
- <spirit:description>Select the receiver termination</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_TERMINATION" spirit:choiceRef="choice_pairs_1040277f" spirit:order="72">PROGRAMMABLE</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_TERMINATION_PROG_VALUE</spirit:name>
- <spirit:displayName>Programmable termination voltage (mV)</spirit:displayName>
- <spirit:description>Select the termination voltage (in mV) when in programmable mode</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_TERMINATION_PROG_VALUE" spirit:choiceRef="choice_list_f490bbca" spirit:order="73">800</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_PPM_OFFSET</spirit:name>
- <spirit:displayName>PPM offset between receiver and transmitter</spirit:displayName>
- <spirit:description>Specify the PPM offset between received data and transmitted data</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PPM_OFFSET" spirit:order="74" spirit:minimum="0" spirit:maximum="1250" spirit:rangeType="long">200</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GTWIZ_OUT</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GTWIZ_OUT" spirit:order="75">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GTWIZ_OUT">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:coreExtensions>
- <xilinx:displayName>Aurora 8B10B</xilinx:displayName>
- <xilinx:coreRevision>8</xilinx:coreRevision>
- <xilinx:configElementInfos>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TKEEP" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TREADY" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TSTRB" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TDEST_WIDTH" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TID_WIDTH" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TUSER_WIDTH" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY" xilinx:valueSource="auto"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
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diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_gt.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_gt.vhd
deleted file mode 100644
index 8334607a8c9834a332f8ebd3e6963b45a441f2e6..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_gt.vhd
+++ /dev/null
@@ -1,960 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
---***************************** Entity Declaration ****************************
-
-entity east_channel_gt is
-generic
-(
- -- Simulation attributes
- GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
- TXSYNC_OVRD_IN : bit := '0';
- TXSYNC_MULTILANE_IN : bit := '0'
-);
-port
-(
- STABLE_CLOCK : IN std_logic; -- System Clock
- RST_IN : in std_logic; -- Connect to System Reset
- DRP_BUSY_OUT : out std_logic; -- Indicates that the DRP bus is not accessible to the User
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- DRPADDR_IN : in std_logic_vector(8 downto 0);
- DRPCLK_IN : in std_logic;
- DRPDI_IN : in std_logic_vector(15 downto 0);
- DRPDO_OUT : out std_logic_vector(15 downto 0);
- DRPEN_IN : in std_logic;
- DRPRDY_OUT : out std_logic;
- DRPWE_IN : in std_logic;
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK_IN : in std_logic;
- PLL0REFCLK_IN : in std_logic;
- PLL1CLK_IN : in std_logic;
- PLL1REFCLK_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK_IN : in std_logic_vector(2 downto 0);
- RXPD_IN : in std_logic_vector(1 downto 0);
- TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- eyescanreset_in : in std_logic;
- RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- rxprbserr_out : out std_logic;
- rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- eyescandataerror_out : out std_logic;
- eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN_IN : in std_logic;
- GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
- rxbyteisaligned_out : out std_logic;
- RXBYTEREALIGN_OUT : out std_logic;
- rxcommadet_out : out std_logic;
- RXMCOMMAALIGNEN_IN : in std_logic;
- RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET_IN : in std_logic;
- rxpcsreset_in : in std_logic;
- rxpmareset_in : in std_logic;
- rxlpmreset_in : in std_logic;
- RXDATA_OUT : out std_logic_vector(31 downto 0);
- RXOUTCLK_OUT : out std_logic;
- RXUSRCLK_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRLOCK_OUT : out std_logic;
- RXLPMHFHOLD_IN : in std_logic;
- RXLPMLFHOLD_IN : in std_logic;
- rxlpmhfovrden_in : in std_logic;
- rxcdrhold_in : in std_logic;
- dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- rxbufreset_in : in std_logic;
- RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRESETDONE_OUT : out std_logic;
- RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- txpostcursor_in : in std_logic_vector(4 downto 0);
- txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- txchardispmode_in : in std_logic_vector(3 downto 0);
- txchardispval_in : in std_logic_vector(3 downto 0);
- TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET_IN : in std_logic;
- TXDATA_IN : in std_logic_vector(31 downto 0);
- TXOUTCLK_OUT : out std_logic;
- TXOUTCLKFABRIC_OUT : out std_logic;
- TXOUTCLKPCS_OUT : out std_logic;
- TXUSRCLK_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN_OUT : out std_logic;
- GTPTXP_OUT : out std_logic;
- txdiffctrl_in : in std_logic_vector(3 downto 0);
- txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- txpcsreset_in : in std_logic;
- txpmareset_in : in std_logic;
- txinhibit_in : in std_logic;
- TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- txpolarity_in : in std_logic
-
-);
-
-
-end east_channel_gt;
-
-architecture MAPPED of east_channel_gt is
-
---*************************** Component Declarations **************************
-component east_channel_gtrxreset_seq
- port (
- RST : IN std_logic;
- GTRXRESET_IN : IN std_logic;
- RXPMARESETDONE: IN std_logic;
- GTRXRESET_OUT : OUT std_logic;
- STABLE_CLOCK : IN std_logic;
-
- DRPCLK : IN std_logic;
- DRPADDR : OUT std_logic_vector(8 downto 0);
- DRPDO : IN std_logic_vector(15 downto 0);
- DRPDI : OUT std_logic_vector(15 downto 0);
- DRPRDY : IN std_logic;
- DRPEN : OUT std_logic;
- DRPWE : OUT std_logic;
- DRP_OP_DONE : OUT std_logic
-);
-end component;
---**************************** Signal Declarations ****************************
-
- -- ground and tied_to_vcc_i signals
- signal tied_to_ground_i : std_logic;
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
- signal tied_to_vcc_i : std_logic;
-
- signal rxpmaresetdone_t : std_logic;
- signal gtrxreset_out : std_logic;
- signal rxpmareset_out : std_logic;
- signal rxrate_out : std_logic_vector(2 downto 0);
- signal drp_op_done : std_logic;
- signal drp_pma_busy : std_logic;
- signal drp_rate_busy : std_logic;
- signal drp_busy_i1 : std_logic:= '0';
- signal drp_busy_i2 : std_logic:= '0';
- signal drpen_rst_t : std_logic;
- signal drpaddr_rst_t : std_logic_vector(8 downto 0);
- signal drpwe_rst_t : std_logic;
- signal drpdo_rst_t : std_logic_vector(15 downto 0);
- signal drpdi_rst_t : std_logic_vector(15 downto 0);
- signal drprdy_rst_t : std_logic;
- signal drpen_pma_t : std_logic;
- signal drpaddr_pma_t : std_logic_vector(8 downto 0);
- signal drpwe_pma_t : std_logic;
- signal drpdo_pma_t : std_logic_vector(15 downto 0);
- signal drpdi_pma_t : std_logic_vector(15 downto 0);
- signal drprdy_pma_t : std_logic;
- signal drpen_rate_t : std_logic;
- signal drpaddr_rate_t : std_logic_vector(8 downto 0);
- signal drpwe_rate_t : std_logic;
- signal drpdo_rate_t : std_logic_vector(15 downto 0);
- signal drpdi_rate_t : std_logic_vector(15 downto 0);
- signal drprdy_rate_t : std_logic;
- signal drpen_i : std_logic;
- signal drpaddr_i : std_logic_vector(8 downto 0);
- signal drpwe_i : std_logic;
- signal drpdo_i : std_logic_vector(15 downto 0);
- signal drpdi_i : std_logic_vector(15 downto 0);
- signal drprdy_i : std_logic;
-
- -- RX Datapath signals
- signal rxdata_i : std_logic_vector(31 downto 0);
-
- -- TX Datapath signals
- signal txdata_i : std_logic_vector(31 downto 0);
- signal rxdatavalid_float_i : std_logic;
-
---******************************** Main Body of Code***************************
-
-begin
-
- --------------------------- Static signal Assignments ---------------------
-
- tied_to_ground_i <= '0';
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');
- tied_to_vcc_i <= '1';
-
- ------------------- GT Datapath byte mapping -----------------
-
- -- The GT provides little endian data (first byte received on RXDATA(7 downto 0))
- RXDATA_OUT <= rxdata_i(31 downto 0);
-
- txdata_i <= (TXDATA_IN);
-
-
-
- ----------------------------- GTPE2 Instance --------------------------
-
- gtpe2_i : GTPE2_CHANNEL
- generic map
- (
-
- --_______________________ Simulation-Only Attributes ___________________
-
- SIM_RECEIVER_DETECT_PASS => ("TRUE"),
- SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
- SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
- SIM_VERSION => ("2.0"),
-
-
- ------------------RX Byte and Word Alignment Attributes---------------
- ALIGN_COMMA_DOUBLE => ("FALSE"),
- ALIGN_COMMA_ENABLE => ("1111111111"),
- ALIGN_COMMA_WORD => (2),
- ALIGN_MCOMMA_DET => ("TRUE"),
- ALIGN_MCOMMA_VALUE => ("1010000011"),
- ALIGN_PCOMMA_DET => ("TRUE"),
- ALIGN_PCOMMA_VALUE => ("0101111100"),
- SHOW_REALIGN_COMMA => ("TRUE"),
- RXSLIDE_AUTO_WAIT => (7),
- RXSLIDE_MODE => ("OFF"),
- RX_SIG_VALID_DLY => (10),
-
- ------------------RX 8B/10B Decoder Attributes---------------
- RX_DISPERR_SEQ_MATCH => ("TRUE"),
- DEC_MCOMMA_DETECT => ("TRUE"),
- DEC_PCOMMA_DETECT => ("TRUE"),
- DEC_VALID_COMMA_ONLY => ("FALSE"),
-
- ------------------------RX Clock Correction Attributes----------------------
- CBCC_DATA_SOURCE_SEL => ("DECODED"),
- CLK_COR_SEQ_2_USE => ("FALSE"),
- CLK_COR_KEEP_IDLE => ("FALSE"),
-CLK_COR_MAX_LAT => (31),
-CLK_COR_MIN_LAT => (24),
- CLK_COR_PRECEDENCE => ("TRUE"),
- CLK_COR_REPEAT_WAIT => (0),
- CLK_COR_SEQ_LEN => (4),
- CLK_COR_SEQ_1_ENABLE => ("1111"),
- CLK_COR_SEQ_1_1 => ("0111110111"),
- CLK_COR_SEQ_1_2 => ("0111110111"),
- CLK_COR_SEQ_1_3 => ("0111110111"),
- CLK_COR_SEQ_1_4 => ("0111110111"),
- CLK_CORRECT_USE => ("TRUE"),
- CLK_COR_SEQ_2_ENABLE => ("1111"),
- CLK_COR_SEQ_2_1 => ("0100000000"),
- CLK_COR_SEQ_2_2 => ("0100000000"),
- CLK_COR_SEQ_2_3 => ("0100000000"),
- CLK_COR_SEQ_2_4 => ("0100000000"),
-
- ------------------------RX Channel Bonding Attributes----------------------
- CHAN_BOND_KEEP_ALIGN => ("FALSE"),
- CHAN_BOND_MAX_SKEW => (7),
- CHAN_BOND_SEQ_LEN => (1),
- CHAN_BOND_SEQ_1_1 => ("0101111100"),
- CHAN_BOND_SEQ_1_2 => ("0000000000"),
- CHAN_BOND_SEQ_1_3 => ("0000000000"),
- CHAN_BOND_SEQ_1_4 => ("0000000000"),
- CHAN_BOND_SEQ_1_ENABLE => ("0001"),
- CHAN_BOND_SEQ_2_1 => ("0000000000"),
- CHAN_BOND_SEQ_2_2 => ("0000000000"),
- CHAN_BOND_SEQ_2_3 => ("0000000000"),
- CHAN_BOND_SEQ_2_4 => ("0000000000"),
- CHAN_BOND_SEQ_2_ENABLE => ("0000"),
- CHAN_BOND_SEQ_2_USE => ("FALSE"),
- FTS_DESKEW_SEQ_ENABLE => ("1111"),
- FTS_LANE_DESKEW_CFG => ("1111"),
- FTS_LANE_DESKEW_EN => ("FALSE"),
-
- ---------------------------RX Margin Analysis Attributes----------------------------
- ES_CONTROL => ("000000"),
- ES_ERRDET_EN => ("FALSE"),
- ES_EYE_SCAN_EN => ("FALSE"),
- ES_HORZ_OFFSET => (x"010"),
- ES_PMA_CFG => ("0000000000"),
- ES_PRESCALE => ("00000"),
- ES_QUALIFIER => (x"00000000000000000000"),
- ES_QUAL_MASK => (x"00000000000000000000"),
- ES_SDATA_MASK => (x"00000000000000000000"),
- ES_VERT_OFFSET => ("000000000"),
-
- -------------------------FPGA RX Interface Attributes-------------------------
- RX_DATA_WIDTH => (40),
-
- ---------------------------PMA Attributes----------------------------
- OUTREFCLK_SEL_INV => ("11"),
- PMA_RSV => (x"00000333"),
- PMA_RSV2 => (x"00002040"),
- PMA_RSV3 => ("00"),
- PMA_RSV4 => ("0000"),
- RX_BIAS_CFG => ("0000111100110011"),
- DMONITOR_CFG => (x"000A00"),
- RX_CM_SEL => ("11"),
- RX_CM_TRIM => ("1010"),
- RX_DEBUG_CFG => ("00000000000000"),
- RX_OS_CFG => ("0000010000000"),
- TERM_RCAL_CFG => ("100001000010000"),
- TERM_RCAL_OVRD => ("000"),
- TST_RSV => (x"00000000"),
-RX_CLK25_DIV => (5),
-TX_CLK25_DIV => (5),
- UCODEER_CLR => ('0'),
-
- ---------------------------PCI Express Attributes----------------------------
- PCS_PCIE_EN => ("FALSE"),
-
- ---------------------------PCS Attributes----------------------------
- PCS_RSVD_ATTR => (x"000000000000"),
-
- -------------RX Buffer Attributes------------
- RXBUF_ADDR_MODE => ("FULL"),
- RXBUF_EIDLE_HI_CNT => ("1000"),
- RXBUF_EIDLE_LO_CNT => ("0000"),
- RXBUF_EN => ("TRUE"),
- RX_BUFFER_CFG => ("000000"),
- RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
- RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
- RXBUF_RESET_ON_EIDLE => ("FALSE"),
- RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
- RXBUFRESET_TIME => ("00001"),
- RXBUF_THRESH_OVFLW => (61),
- RXBUF_THRESH_OVRD => ("FALSE"),
- RXBUF_THRESH_UNDFLW => (4),
- RXDLY_CFG => (x"001F"),
- RXDLY_LCFG => (x"030"),
- RXDLY_TAP_CFG => (x"0000"),
- RXPH_CFG => (x"C00002"),
- RXPHDLY_CFG => (x"084020"),
- RXPH_MONITOR_SEL => ("00000"),
- RX_XCLK_SEL => ("RXREC"),
- RX_DDI_SEL => ("000000"),
- RX_DEFER_RESET_BUF_EN => ("TRUE"),
-
- -----------------------CDR Attributes-------------------------
- RXCDR_CFG => (x"0000107FE406001041010"),
- RXCDR_FR_RESET_ON_EIDLE => ('0'),
- RXCDR_HOLD_DURING_EIDLE => ('0'),
- RXCDR_PH_RESET_ON_EIDLE => ('0'),
- RXCDR_LOCK_CFG => ("001001"),
-
- -------------------RX Initialization and Reset Attributes-------------------
- RXCDRFREQRESET_TIME => ("00001"),
- RXCDRPHRESET_TIME => ("00001"),
- RXISCANRESET_TIME => ("00001"),
- RXPCSRESET_TIME => ("00001"),
- RXPMARESET_TIME => ("00011"),
-
- -------------------RX OOB Signaling Attributes-------------------
- RXOOB_CFG => ("0000110"),
-
- -------------------------RX Gearbox Attributes---------------------------
- RXGEARBOX_EN => ("FALSE"),
- GEARBOX_MODE => ("000"),
-
- -------------------------PRBS Detection Attribute-----------------------
- RXPRBS_ERR_LOOPBACK => ('0'),
-
- -------------Power-Down Attributes----------
- PD_TRANS_TIME_FROM_P2 => (x"03c"),
- PD_TRANS_TIME_NONE_P2 => (x"3c"),
- PD_TRANS_TIME_TO_P2 => (x"64"),
-
- -------------RX OOB Signaling Attributes----------
- SAS_MAX_COM => (64),
- SAS_MIN_COM => (36),
- SATA_BURST_SEQ_LEN => ("0101"),
- SATA_BURST_VAL => ("100"),
- SATA_EIDLE_VAL => ("100"),
- SATA_MAX_BURST => (8),
- SATA_MAX_INIT => (21),
- SATA_MAX_WAKE => (7),
- SATA_MIN_BURST => (4),
- SATA_MIN_INIT => (12),
- SATA_MIN_WAKE => (4),
-
- -------------RX Fabric Clock Output Control Attributes----------
- TRANS_TIME_RATE => (x"0E"),
-
- --------------TX Buffer Attributes----------------
- TXBUF_EN => ("TRUE"),
- TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
- TXDLY_CFG => (x"001F"),
- TXDLY_LCFG => (x"030"),
- TXDLY_TAP_CFG => (x"0000"),
- TXPH_CFG => (x"0780"),
- TXPHDLY_CFG => (x"084020"),
- TXPH_MONITOR_SEL => ("00000"),
- TX_XCLK_SEL => ("TXOUT"),
-
- -------------------------FPGA TX Interface Attributes-------------------------
- TX_DATA_WIDTH => (40),
-
- -------------------------TX Configurable Driver Attributes-------------------------
- TX_DEEMPH0 => ("000000"),
- TX_DEEMPH1 => ("000000"),
- TX_EIDLE_ASSERT_DELAY => ("110"),
- TX_EIDLE_DEASSERT_DELAY => ("100"),
- TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
- TX_MAINCURSOR_SEL => ('0'),
- TX_DRIVE_MODE => ("DIRECT"),
- TX_MARGIN_FULL_0 => ("1001110"),
- TX_MARGIN_FULL_1 => ("1001001"),
- TX_MARGIN_FULL_2 => ("1000101"),
- TX_MARGIN_FULL_3 => ("1000010"),
- TX_MARGIN_FULL_4 => ("1000000"),
- TX_MARGIN_LOW_0 => ("1000110"),
- TX_MARGIN_LOW_1 => ("1000100"),
- TX_MARGIN_LOW_2 => ("1000010"),
- TX_MARGIN_LOW_3 => ("1000000"),
- TX_MARGIN_LOW_4 => ("1000000"),
-
- -------------------------TX Gearbox Attributes--------------------------
- TXGEARBOX_EN => ("FALSE"),
-
- -------------------------TX Initialization and Reset Attributes--------------------------
- TXPCSRESET_TIME => ("00001"),
- TXPMARESET_TIME => ("00001"),
-
- -------------------------TX Receiver Detection Attributes--------------------------
- TX_RXDETECT_CFG => (x"1832"),
- TX_RXDETECT_REF => ("100"),
-
- ------------------ JTAG Attributes ---------------
- ACJTAG_DEBUG_MODE => ('0'),
- ACJTAG_MODE => ('0'),
- ACJTAG_RESET => ('0'),
-
- ------------------ CDR Attributes ---------------
- CFOK_CFG => (x"49000040E80"),
- CFOK_CFG2 => ("0100000"),
- CFOK_CFG3 => ("0100000"),
- CFOK_CFG4 => ('0'),
- CFOK_CFG5 => (x"0"),
- CFOK_CFG6 => ("0000"),
- RXOSCALRESET_TIME => ("00011"),
- RXOSCALRESET_TIMEOUT => ("00000"),
-
- ------------------ PMA Attributes ---------------
- CLK_COMMON_SWING => ('0'),
- RX_CLKMUX_EN => ('1'),
- TX_CLKMUX_EN => ('1'),
- ES_CLK_PHASE_SEL => ('0'),
- USE_PCS_CLK_PHASE_SEL => ('0'),
- PMA_RSV6 => ('0'),
- PMA_RSV7 => ('0'),
-
- ------------------ TX Configuration Driver Attributes ---------------
- TX_PREDRIVER_MODE => ('0'),
- PMA_RSV5 => ('0'),
- SATA_PLL_CFG => ("VCO_3000MHZ"),
-
- ------------------ RX Fabric Clock Output Control Attributes ---------------
- RXOUT_DIV => (1),
-
- ------------------ TX Fabric Clock Output Control Attributes ---------------
- TXOUT_DIV => (1),
-
- ------------------ RX Phase Interpolator Attributes---------------
- RXPI_CFG0 => ("000"),
- RXPI_CFG1 => ('1'),
- RXPI_CFG2 => ('1'),
-
- --------------RX Equalizer Attributes-------------
- ADAPT_CFG0 => (x"00000"),
- RXLPMRESET_TIME => ("0001111"),
-
- RXLPM_BIAS_STARTUP_DISABLE => ('0'),
-
- RXLPM_CFG => ("0110"),
- RXLPM_CFG1 => ('0'),
- RXLPM_CM_CFG => ('0'),
- RXLPM_GC_CFG => ("111100010"),
- RXLPM_GC_CFG2 => ("001"),
- RXLPM_HF_CFG => ("00001111110000"),
- RXLPM_HF_CFG2 => ("01010"),
- RXLPM_HF_CFG3 => ("0000"),
- RXLPM_HOLD_DURING_EIDLE => ('0'),
- RXLPM_INCM_CFG => ('1'),
- RXLPM_IPCM_CFG => ('0'),
- RXLPM_LF_CFG => ("000000001111110000"),
- RXLPM_LF_CFG2 => ("01010"),
- RXLPM_OSINT_CFG => ("100"),
-
- ------------------ TX Phase Interpolator PPM Controller Attributes---------------
- TXPI_CFG0 => ("00"),
- TXPI_CFG1 => ("00"),
- TXPI_CFG2 => ("00"),
- TXPI_CFG3 => ('0'),
- TXPI_CFG4 => ('0'),
- TXPI_CFG5 => ("000"),
- TXPI_GREY_SEL => ('0'),
- TXPI_INVSTROBE_SEL => ('0'),
- TXPI_PPMCLK_SEL => ("TXUSRCLK2"),
- TXPI_PPM_CFG => (x"00"),
- TXPI_SYNFREQ_PPM => ("000"),
-
- ------------------ LOOPBACK Attributes---------------
- LOOPBACK_CFG => ('0'),
- PMA_LOOPBACK_CFG => ('0'),
-
- ------------------RX OOB Signalling Attributes---------------
- RXOOB_CLK_CFG => ("PMA"),
-
- ------------------TX OOB Signalling Attributes---------------
- TXOOB_CFG => ('0'),
-
- ------------------RX Buffer Attributes---------------
- RXSYNC_MULTILANE => ('0'),
- RXSYNC_OVRD => ('0'),
- RXSYNC_SKIP_DA => ('0'),
-
- ------------------TX Buffer Attributes---------------
- TXSYNC_MULTILANE => (TXSYNC_MULTILANE_IN),
- TXSYNC_OVRD => (TXSYNC_OVRD_IN),
- TXSYNC_SKIP_DA => ('0')
-
-
- )
- port map
- (
- ---------------------------------- Channel ---------------------------------
- CFGRESET => tied_to_ground_i,
- GTRESETSEL => tied_to_ground_i,
- GTRSVD => "0000000000000000",
- RESETOVRD => tied_to_ground_i,
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- DRPADDR => drpaddr_i,
- DRPCLK => DRPCLK_IN,
- DRPDI => drpdi_i,
- DRPDO => drpdo_i,
- DRPEN => drpen_i,
- DRPRDY => drprdy_i,
- DRPWE => drpwe_i,
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK => PLL0CLK_IN,
- PLL0REFCLK => PLL0REFCLK_IN,
- PLL1CLK => PLL1CLK_IN,
- PLL1REFCLK => PLL1REFCLK_IN,
- RXSYSCLKSEL => "00",
- TXSYSCLKSEL => "00",
- ------------------------------- Eye Scan Ports -----------------------------
- EYESCANDATAERROR => EYESCANDATAERROR_OUT,
- EYESCANMODE => tied_to_ground_i,
- EYESCANRESET => eyescanreset_in,
- EYESCANTRIGGER => eyescantrigger_in,
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK => LOOPBACK_IN,
- RXPD => RXPD_IN,
- TXPD => TXPD_IN,
- ----------------------------- PCS Reserved Ports ---------------------------
- PCSRSVDIN => "0000000000000000",
- PCSRSVDOUT => open,
- ----------------------------- PMA Reserved Ports ---------------------------
- PMARSVDIN3 => '0',
- PMARSVDIN4 => '0',
- ------------------------------- Receive Ports ------------------------------
- CLKRSVD0 => tied_to_ground_i,
- CLKRSVD1 => tied_to_ground_i,
- DMONFIFORESET => tied_to_ground_i,
- DMONITORCLK => tied_to_ground_i,
- RXPMARESETDONE => rxpmaresetdone_t,
- RXUSERRDY => RXUSERRDY_IN,
- SIGVALIDCLK => tied_to_ground_i,
- -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
- RXDATAVALID => open,
- RXGEARBOXSLIP => tied_to_ground_i,
- RXHEADER => open,
- RXHEADERVALID => open,
- RXSTARTOFSEQ => open,
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RX8B10BEN => tied_to_vcc_i,
- RXCHARISCOMMA => RXCHARISCOMMA_OUT,
- RXCHARISK => RXCHARISK_OUT,
- RXDISPERR => RXDISPERR_OUT,
- RXNOTINTABLE => RXNOTINTABLE_OUT,
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN => GTPRXN_IN,
- GTPRXP => GTPRXP_IN,
- PMARSVDIN2 => '0',
- PMARSVDOUT0 => open,
- PMARSVDOUT1 => open,
- ------------------- Receive Ports - Channel Bonding Ports ------------------
- RXCHANBONDSEQ => open,
- RXCHBONDEN => tied_to_ground_i,
- RXCHBONDI => "0000",
- RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
- RXCHBONDMASTER => tied_to_ground_i,
- RXCHBONDO => open,
- RXCHBONDSLAVE => tied_to_ground_i,
- ------------------- Receive Ports - Channel Bonding Ports -----------------
- RXCHANISALIGNED => open,
- RXCHANREALIGN => open,
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT => RXCLKCORCNT_OUT,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- RXBYTEISALIGNED => rxbyteisaligned_out,
- RXBYTEREALIGN => RXBYTEREALIGN_OUT,
- RXCOMMADET => rxcommadet_out,
- RXCOMMADETEN => tied_to_vcc_i,
- RXMCOMMAALIGNEN => RXMCOMMAALIGNEN_IN,
- RXPCOMMAALIGNEN => RXPCOMMAALIGNEN_IN,
- RXSLIDE => tied_to_ground_i,
- ----------------------- Receive Ports - PRBS Detection ---------------------
- RXPRBSCNTRESET => rxprbscntreset_in,
- RXPRBSERR => rxprbserr_out,
- RXPRBSSEL => rxprbssel_in,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET => gtrxreset_out,
- RXDATA => rxdata_i,
- RXOUTCLK => RXOUTCLK_OUT,
- RXOUTCLKFABRIC => open,
- RXOUTCLKPCS => open,
- RXOUTCLKSEL => "010",
- RXPCSRESET => rxpcsreset_in,
- RXPMARESET => rxpmareset_in,
- RXUSRCLK => RXUSRCLK_IN,
- RXUSRCLK2 => RXUSRCLK2_IN,
- ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
- DMONITOROUT => dmonitorout_out,
- RXADAPTSELTEST => tied_to_ground_vec_i(13 downto 0),
- RXDFEXYDEN => tied_to_ground_i,
- RXOSCALRESET => tied_to_ground_i,
- RXOSHOLD => tied_to_ground_i,
- RXOSINTCFG => "0010",
- RXOSINTDONE => open,
- RXOSINTEN => tied_to_vcc_i,
- RXOSINTHOLD => tied_to_ground_i,
- RXOSINTID0 => tied_to_ground_vec_i(3 downto 0),
- RXOSINTNTRLEN => tied_to_ground_i,
- RXOSINTOVRDEN => tied_to_ground_i,
- RXOSINTPD => tied_to_ground_i,
- RXOSINTSTARTED => open,
- RXOSINTSTROBE => tied_to_ground_i,
- RXOSINTSTROBEDONE => open,
- RXOSINTSTROBESTARTED => open,
- RXOSINTTESTOVRDEN => tied_to_ground_i,
- RXOSOVRDEN => tied_to_ground_i,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRFREQRESET => tied_to_ground_i,
- RXCDRHOLD => rxcdrhold_in,
- RXCDRLOCK => RXCDRLOCK_OUT,
- RXCDROVRDEN => tied_to_ground_i,
- RXCDRRESET => tied_to_ground_i,
- RXCDRRESETRSV => tied_to_ground_i,
- RXELECIDLE => open,
- RXELECIDLEMODE => "11",
- RXLPMHFHOLD => RXLPMHFHOLD_IN,
- RXLPMHFOVRDEN => rxlpmhfovrden_in,
- RXLPMLFHOLD => RXLPMLFHOLD_IN,
- RXLPMLFOVRDEN => tied_to_ground_i,
- RXLPMOSINTNTRLEN => tied_to_ground_i,
- RXLPMRESET => rxlpmreset_in,
- RXOOBRESET => tied_to_ground_i,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- RXBUFRESET => rxbufreset_in,
- RXBUFSTATUS => RXBUFSTATUS_OUT,
- RXDDIEN => tied_to_ground_i,
- RXDLYBYPASS => tied_to_vcc_i,
- RXDLYEN => tied_to_ground_i,
- RXDLYOVRDEN => tied_to_ground_i,
- RXDLYSRESET => tied_to_ground_i,
- RXDLYSRESETDONE => open,
- RXPHALIGN => tied_to_ground_i,
- RXPHALIGNDONE => open,
- RXPHALIGNEN => tied_to_ground_i,
- RXPHDLYPD => tied_to_ground_i,
- RXPHDLYRESET => tied_to_ground_i,
- RXPHMONITOR => open,
- RXPHOVRDEN => tied_to_ground_i,
- RXPHSLIPMONITOR => open,
- RXSTATUS => open,
- RXSYNCALLIN => tied_to_ground_i,
- RXSYNCDONE => open,
- RXSYNCIN => tied_to_ground_i,
- RXSYNCMODE => tied_to_ground_i,
- RXSYNCOUT => open,
- ----------- Receive Ports - RX Fabric Clock Output Control Ports ----------
- RXRATEMODE => '0',
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRATE => tied_to_ground_vec_i(2 downto 0),
- RXRATEDONE => open,
- RXRESETDONE => RXRESETDONE_OUT,
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- PHYSTATUS => open,
- RXVALID => open,
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY => RXPOLARITY_IN,
- --------------------- Receive Ports - RX Ports for SATA --------------------
- RXCOMINITDET => open,
- RXCOMSASDET => open,
- RXCOMWAKEDET => open,
- ------------------------------- Transmit Ports -----------------------------
- SETERRSTATUS => tied_to_ground_i,
- TSTIN => "11111111111111111111",
- TXPHDLYTSTCLK => tied_to_ground_i,
- TXPIPPMEN => tied_to_ground_i,
- TXPIPPMOVRDEN => tied_to_ground_i,
- TXPIPPMPD => tied_to_ground_i,
- TXPIPPMSEL => tied_to_vcc_i,
- TXPIPPMSTEPSIZE => tied_to_ground_vec_i(4 downto 0),
- TXPMARESETDONE => open,
- TXPOSTCURSOR => txpostcursor_in,
- TXPOSTCURSORINV => tied_to_ground_i,
- TXPRECURSOR => txprecursor_in,
- TXPRECURSORINV => tied_to_ground_i,
- TXRATEMODE => tied_to_ground_i,
- TXUSERRDY => TXUSERRDY_IN,
- -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
- TXGEARBOXREADY => open,
- TXHEADER => tied_to_ground_vec_i(2 downto 0),
- TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
- TXSTARTSEQ => tied_to_ground_i,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- TX8B10BBYPASS => tied_to_ground_vec_i(3 downto 0),
- TX8B10BEN => tied_to_vcc_i,
- TXCHARDISPMODE => txchardispmode_in,
- TXCHARDISPVAL => txchardispval_in,
- TXCHARISK => TXCHARISK_IN,
- ----------------- Transmit Ports - Configurable Driver Ports ---------------
- PMARSVDIN0 => '0',
- PMARSVDIN1 => '0',
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS => TXBUFSTATUS_OUT,
- TXDLYBYPASS => tied_to_vcc_i,
- TXDLYEN => tied_to_ground_i,
- TXDLYHOLD => tied_to_ground_i,
- TXDLYOVRDEN => tied_to_ground_i,
- TXDLYSRESET => tied_to_ground_i,
- TXDLYSRESETDONE => open,
- TXDLYUPDOWN => tied_to_ground_i,
- TXPHALIGN => tied_to_ground_i,
- TXPHALIGNDONE => open,
- TXPHALIGNEN => tied_to_ground_i,
- TXPHDLYPD => tied_to_ground_i,
- TXPHDLYRESET => tied_to_ground_i,
- TXPHINIT => tied_to_ground_i,
- TXPHINITDONE => open,
- TXPHOVRDEN => tied_to_ground_i,
- TXSYNCALLIN => tied_to_ground_i,
- TXSYNCDONE => open,
- TXSYNCIN => tied_to_ground_i,
- TXSYNCMODE => tied_to_ground_i,
- TXSYNCOUT => open,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET => GTTXRESET_IN,
- TXDATA => txdata_i,
- TXOUTCLK => TXOUTCLK_OUT,
- TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT,
- TXOUTCLKPCS => TXOUTCLKPCS_OUT,
- TXOUTCLKSEL => "010",
- TXPCSRESET => txpcsreset_in,
- TXPMARESET => txpmareset_in,
- TXUSRCLK => TXUSRCLK_IN,
- TXUSRCLK2 => TXUSRCLK2_IN,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN => GTPTXN_OUT,
- GTPTXP => GTPTXP_OUT,
- TXBUFDIFFCTRL => "100",
- TXDIFFCTRL => txdiffctrl_in,
- TXDIFFPD => tied_to_ground_i,
- TXINHIBIT => txinhibit_in,
- TXMAINCURSOR => txmaincursor_in,
- TXPDELECIDLEMODE => tied_to_ground_i,
- TXPISOPD => tied_to_ground_i,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- TXRATE => tied_to_ground_vec_i(2 downto 0),
- TXRATEDONE => open,
- TXRESETDONE => TXRESETDONE_OUT,
- --------------------- Transmit Ports - TX PRBS Generator -------------------
- TXPRBSFORCEERR => txprbsforceerr_in,
- TXPRBSSEL => txprbssel_in,
- -------------------- Transmit Ports - TX Polarity Control ------------------
- TXPOLARITY => txpolarity_in,
- ----------------- Transmit Ports - TX Ports for PCI Express ----------------
- TXDEEMPH => tied_to_ground_i,
- TXDETECTRX => tied_to_ground_i,
- TXELECIDLE => txelecidle_in,
- TXMARGIN => tied_to_ground_vec_i(2 downto 0),
- TXSWING => tied_to_ground_i,
- --------------------- Transmit Ports - TX Ports for SATA -------------------
- TXCOMFINISH => open,
- TXCOMINIT => tied_to_ground_i,
- TXCOMSAS => tied_to_ground_i,
- TXCOMWAKE => tied_to_ground_i
-
- );
-
- RXPMARESETDONE_OUT <= rxpmaresetdone_t;
-
- ------------------------- Soft Fix for Production Silicon----------------------
- gtrxreset_seq_i : east_channel_gtrxreset_seq
- port map
- (
- RST => RST_IN,
- STABLE_CLOCK => STABLE_CLOCK,
- GTRXRESET_IN => GTRXRESET_IN,
- RXPMARESETDONE => rxpmaresetdone_t,
- GTRXRESET_OUT => gtrxreset_out,
- DRP_OP_DONE => drp_op_done,
- DRPCLK => DRPCLK_IN,
- DRPEN => drpen_rst_t,
- DRPADDR => drpaddr_rst_t,
- DRPWE => drpwe_rst_t,
- DRPDO => drpdo_rst_t,
- DRPDI => drpdi_rst_t,
- DRPRDY => drprdy_rst_t
-
- );
-
- drpen_pma_t <= '0';
- drpaddr_pma_t <= "000000000";
- drpwe_pma_t <= '0';
- drpdi_pma_t <= x"0000";
- drpen_rate_t <= '0';
- drpaddr_rate_t <= "000000000";
- drpwe_rate_t <= '0';
- drpdi_rate_t <= x"0000";
- drpen_i <= drpen_rst_t when drp_op_done ='0' else
- drpen_pma_t when drp_pma_busy = '1' else
- drpen_rate_t when drp_rate_busy ='1' else DRPEN_IN;
-
-
- drpaddr_i <= drpaddr_rst_t when drp_op_done ='0' else
- drpaddr_pma_t when drp_pma_busy = '1' else
- drpaddr_rate_t when drp_rate_busy ='1' else DRPADDR_IN;
-
-
- drpwe_i <= drpwe_rst_t when drp_op_done ='0' else
- drpwe_pma_t when drp_pma_busy = '1' else
- drpwe_rate_t when drp_rate_busy ='1' else DRPWE_IN;
-
-
-
- DRPDO_OUT <= drpdo_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else x"0000";
-
- drpdo_rst_t <= drpdo_i;
-
- drpdo_pma_t <= drpdo_i;
-
- drpdo_rate_t <= drpdo_i;
-
-
- drpdi_i <= drpdi_rst_t when drp_op_done ='0' else
- drpdi_pma_t when drp_pma_busy = '1' else
- drpdi_rate_t when drp_rate_busy ='1' else DRPDI_IN;
-
-
- DRPRDY_OUT <= drprdy_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else '0';
-
- drprdy_rst_t <= drprdy_i;
-
- drprdy_pma_t <= drprdy_i;
-
- drprdy_rate_t <= drprdy_i;
-
-
- drp_pma_busy <= '0';
- drp_rate_busy <= '0';
-
- process (DRPCLK_IN)
- begin
- if(rising_edge(DRPCLK_IN)) then
- if(drp_op_done = '0' or drp_rate_busy='1') then
- drp_busy_i1 <= '1';
- else
- drp_busy_i1 <= '0';
- end if;
- end if;
- end process;
-
- process (DRPCLK_IN)
- begin
- if(rising_edge(DRPCLK_IN)) then
- if(drp_op_done = '0' or drp_pma_busy='1') then
- drp_busy_i2 <= '1';
- else
- drp_busy_i2 <= '0';
- end if;
- end if;
- end process;
-
- DRP_BUSY_OUT <= drp_busy_i1 or drp_busy_i2;
-
-
- end MAPPED;
-
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_gtrxreset_seq.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_gtrxreset_seq.vhd
deleted file mode 100644
index df87e4ca9852fe9eb16b49382739426946bb200f..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_gtrxreset_seq.vhd
+++ /dev/null
@@ -1,416 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-ENTITY east_channel_gtrxreset_seq IS
- port (
- RST : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
- GTRXRESET_IN : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
- RXPMARESETDONE: IN std_logic;
- GTRXRESET_OUT : OUT std_logic;
-
- STABLE_CLOCK : IN std_logic;
- DRPCLK : IN std_logic;
- DRPADDR : OUT std_logic_vector(8 downto 0);
- DRPDO : IN std_logic_vector(15 downto 0);
- DRPDI : OUT std_logic_vector(15 downto 0);
- DRPRDY : IN std_logic;
- DRPEN : OUT std_logic;
- DRPWE : OUT std_logic;
- DRP_OP_DONE : OUT std_logic
-);
-END east_channel_gtrxreset_seq;
-
-ARCHITECTURE Behavioral of east_channel_gtrxreset_seq is
-
- component east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
- constant DLY : time := 1 ns;
- type state_type is (idle,
- drp_rd,
- wait_rd_data,
- wr_16,
- wait_wr_done1,
- wait_pmareset,
- wr_20,
- wait_wr_done2);
-
- signal state : state_type := idle;
- signal next_state : state_type := idle;
- signal gtrxreset_f : std_logic;
- signal gtrxreset_s : std_logic;
- signal gtrxreset_ss : std_logic;
- signal rst_ss : std_logic;
- signal rxpmaresetdone_ss : std_logic;
- signal rxpmaresetdone_sss : std_logic;
- signal rd_data : std_logic_vector(15 downto 0);
- signal next_rd_data : std_logic_vector(15 downto 0);
- signal pmarstdone_fall_edge: std_logic;
- signal gtrxreset_i : std_logic;
- signal gtrxreset_o : std_logic;
- signal drpen_o : std_logic;
- signal drpwe_o : std_logic;
- signal drpaddr_o : std_logic_vector(8 downto 0);
- signal drpdi_o : std_logic_vector(15 downto 0);
- signal drp_op_done_o : std_logic;
- signal flag : std_logic :='0';
- signal original_rd_data : std_logic_vector(15 downto 0);
-
-BEGIN
-
-flag_gen : PROCESS(DRPCLK)
-BEGIN
- IF (DRPCLK = '1' and DRPCLK'event) THEN
- IF (state = wr_16 or state = wait_pmareset or state = wr_20 or state = wait_wr_done1) THEN
- flag <= '1';
- ELSIF(state = wait_wr_done2) THEN
- flag <= '0';
- END IF;
- END IF;
-END PROCESS flag_gen;
-
-org_data_gen : PROCESS(DRPCLK)
-BEGIN
- IF (DRPCLK = '1' and DRPCLK'event) THEN
- IF ( state = wait_rd_data and DRPRDY = '1' and flag = '0') THEN
- original_rd_data <= DRPDO;
- END IF;
- END IF;
-END PROCESS org_data_gen;
-
-
- rxpmaresetdone_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => RXPMARESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => DRPCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxpmaresetdone_ss ,
- scndry_vect_out => open
- );
-
- rst_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => RST ,
- prmry_vect_in => "00" ,
- scndry_aclk => DRPCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rst_ss ,
- scndry_vect_out => open
- );
-
- gtrxreset_in_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => GTRXRESET_IN ,
- prmry_vect_in => "00" ,
- scndry_aclk => DRPCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gtrxreset_f ,
- scndry_vect_out => open
- );
-
-
---output assignment
- GTRXRESET_OUT <= gtrxreset_o;
- DRPEN <= drpen_o;
- DRPWE <= drpwe_o;
- DRPADDR <= drpaddr_o;
- DRPDI <= drpdi_o;
- DRP_OP_DONE <= drp_op_done_o;
-
- PROCESS (DRPCLK, rst_ss)
- BEGIN
- IF (rst_ss = '1') THEN
- state <= idle after DLY;
- gtrxreset_s <= '0' after DLY;
- gtrxreset_ss <= '0' after DLY;
- rxpmaresetdone_sss <= '0' after DLY;
- rd_data <= x"0000" after DLY;
- gtrxreset_o <= '0' after DLY;
- ELSIF (DRPCLK'event and DRPCLK='1') THEN
- state <= next_state after DLY;
- gtrxreset_s <= gtrxreset_f after DLY;
- gtrxreset_ss <= gtrxreset_s after DLY;
- rxpmaresetdone_sss <= rxpmaresetdone_ss after DLY;
- rd_data <= next_rd_data after DLY;
- gtrxreset_o <= gtrxreset_i after DLY;
- END IF;
- END PROCESS;
-
- PROCESS (DRPCLK, gtrxreset_f)
- BEGIN
- IF (gtrxreset_f = '1') THEN
- drp_op_done_o <= '0' after DLY;
-
- ELSIF (DRPCLK'event and DRPCLK='1') THEN
- IF (state = wait_wr_done2 and DRPRDY = '1') THEN
- drp_op_done_o <= '1' after DLY;
- ELSE
- drp_op_done_o <= drp_op_done_o after DLY;
- END IF;
- END IF;
- END PROCESS;
-
- pmarstdone_fall_edge <= (not rxpmaresetdone_ss) and (rxpmaresetdone_sss);
-
- PROCESS (gtrxreset_ss,DRPRDY,state,pmarstdone_fall_edge)
- BEGIN
- CASE state IS
-
- WHEN idle =>
- IF (gtrxreset_ss='1') THEN
- next_state <= drp_rd;
- ELSE
- next_state <= idle;
- END IF;
-
- WHEN drp_rd =>
- next_state<= wait_rd_data;
-
- WHEN wait_rd_data =>
- IF (DRPRDY='1')THEN
- next_state <= wr_16;
- ELSE
- next_state <= wait_rd_data;
- END IF;
-
- WHEN wr_16 =>
- next_state <= wait_wr_done1;
-
- WHEN wait_wr_done1 =>
- IF (DRPRDY='1') THEN
- next_state <= wait_pmareset;
- ELSE
- next_state <= wait_wr_done1;
- END IF;
-
- WHEN wait_pmareset =>
- IF (pmarstdone_fall_edge='1') THEN
- next_state <= wr_20;
- ELSE
- next_state <= wait_pmareset;
- END IF;
-
- WHEN wr_20 =>
- next_state <= wait_wr_done2;
-
- WHEN wait_wr_done2 =>
- IF (DRPRDY='1') THEN
- next_state <= idle;
- ELSE
- next_state <= wait_wr_done2;
- END IF;
-
- WHEN others=>
- next_state <= idle;
-
- END CASE;
- END PROCESS;
-
--- drives DRP interface and GTRXRESET_OUT
- PROCESS(DRPRDY,state,rd_data,DRPDO,gtrxreset_ss,flag,original_rd_data)
- BEGIN
--- assert gtrxreset_out until wr to 16-bit is complete
--- RX_DATA_WIDTH is located at addr x"0011", [13 downto 11]
--- encoding is this : /16 = x "2", /20 = x"3", /32 = x"4", /40 = x"5"
- gtrxreset_i <= '0';
- drpaddr_o <= '0'& x"11"; -- 000010001
- drpen_o <= '0';
- drpwe_o <= '0';
- drpdi_o <= x"0000";
- next_rd_data <= rd_data;
-
- CASE state IS
-
- --do nothing to DRP or reset
- WHEN idle => null;
-
- --assert reset and issue rd
- WHEN drp_rd =>
- gtrxreset_i <= '1';
- drpen_o <= '1';
- drpwe_o <= '0';
-
- --assert reset and wait to load rd data
- WHEN wait_rd_data =>
- gtrxreset_i <= '1';
-
- IF (DRPRDY = '1' and flag = '0') THEN
- next_rd_data <= DRPDO;
- ELSIF (DRPRDY = '1' and flag = '1') THEN
- next_rd_data <= original_rd_data;
- ELSE
- next_rd_data <= rd_data;
- END IF;
-
- --assert reset and write to 16-bit mode
- WHEN wr_16=>
- gtrxreset_i<= '1';
- drpen_o <= '1';
- drpwe_o <= '1';
- -- Addr "00001001" [11] = '0' puts width mode in /16 or /32
- drpdi_o <= rd_data(15 downto 12) & '0' & rd_data(10 downto 0);
-
- --keep asserting reset until write to 16-bit mode is complete
- WHEN wait_wr_done1=>
- gtrxreset_i <= '1';
-
- --deassert reset and no DRP access until 2nd pmareset
- WHEN wait_pmareset => null;
- IF (gtrxreset_ss='1') THEN
- gtrxreset_i <= '1';
- ELSE
- gtrxreset_i <= '0';
- END IF;
-
- --write to 20-bit mode
- WHEN wr_20 =>
- drpen_o <='1';
- drpwe_o <= '1';
- drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read
-
- --wait to complete write to 20-bit mode
- WHEN wait_wr_done2 => null;
-
- WHEN others => null;
-
- END CASE;
- END PROCESS;
-
-END Behavioral;
-
-
-
-
-
-
-
-
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_multi_gt.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_multi_gt.vhd
deleted file mode 100644
index 7845f44e7c990b21878590550e4c327e74e72fea..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_multi_gt.vhd
+++ /dev/null
@@ -1,479 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
--- Module east_channel_GT_WRAPPER
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
---***************************** Entity Declaration ****************************
-
-entity east_channel_multi_gt is
-generic
-(
- -- Simulation attributes
- WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
-);
-port
-(
- STABLE_CLOCK : in std_logic; -- System Clock
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- --____________________________CHANNEL PORTS________________________________
- GT0_DRP_BUSY_OUT : out std_logic;
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
- GT0_DRPCLK_IN : in std_logic;
- GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
- GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
- GT0_DRPEN_IN : in std_logic;
- GT0_DRPRDY_OUT : out std_logic;
- GT0_DRPWE_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
- GT0_RXPD_IN : in std_logic_vector(1 downto 0);
- GT0_TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- GT0_eyescanreset_in : in std_logic;
- GT0_RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- GT0_rxprbserr_out : out std_logic;
- GT0_rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- GT0_rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- GT0_eyescandataerror_out : out std_logic;
- GT0_eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GT0_GTPRXN_IN : in std_logic;
- GT0_GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GT0_rxbyteisaligned_out : out std_logic;
- GT0_RXBYTEREALIGN_OUT : out std_logic;
- GT0_rxcommadet_out : out std_logic;
- GT0_RXMCOMMAALIGNEN_IN : in std_logic;
- GT0_RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GT0_GTRXRESET_IN : in std_logic;
- GT0_rxpcsreset_in : in std_logic;
- GT0_rxpmareset_in : in std_logic;
- GT0_rxlpmreset_in : in std_logic;
- GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
- GT0_RXOUTCLK_OUT : out std_logic;
- GT0_RXUSRCLK_IN : in std_logic;
- GT0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GT0_RXCDRLOCK_OUT : out std_logic;
- GT0_RXLPMHFHOLD_IN : in std_logic;
- GT0_RXLPMLFHOLD_IN : in std_logic;
- GT0_rxlpmhfovrden_in : in std_logic;
- GT0_rxcdrhold_in : in std_logic;
- GT0_dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GT0_rxbufreset_in : in std_logic;
- GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GT0_RXRESETDONE_OUT : out std_logic;
- GT0_RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- GT0_txpostcursor_in : in std_logic_vector(4 downto 0);
- GT0_txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- GT0_RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- GT0_TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GT0_txchardispmode_in : in std_logic_vector(3 downto 0);
- GT0_txchardispval_in : in std_logic_vector(3 downto 0);
- GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- GT0_TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GT0_GTTXRESET_IN : in std_logic;
- GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
- GT0_TXOUTCLK_OUT : out std_logic;
- GT0_TXOUTCLKFABRIC_OUT : out std_logic;
- GT0_TXOUTCLKPCS_OUT : out std_logic;
- GT0_TXUSRCLK_IN : in std_logic;
- GT0_TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- GT0_txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- GT0_txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GT0_GTPTXN_OUT : out std_logic;
- GT0_GTPTXP_OUT : out std_logic;
- GT0_txdiffctrl_in : in std_logic_vector(3 downto 0);
- GT0_txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GT0_txpcsreset_in : in std_logic;
- GT0_txinhibit_in : in std_logic;
- GT0_txpmareset_in : in std_logic;
- GT0_TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- GT0_txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- GT0_txpolarity_in : in std_logic;
-
-
-
- --____________________________COMMON PORTS________________________________
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
- GT0_PLL0RESET_IN : in std_logic
-
-
-);
-
-
-end east_channel_multi_gt;
-
-architecture MAPPED of east_channel_multi_gt is
- attribute core_generation_info : string;
-attribute core_generation_info of MAPPED : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
---***********************************Parameter Declarations********************
-
- constant DLY : time := 1 ns;
-
---***************************** Signal Declarations *****************************
-
- -- ground and tied_to_vcc_i signals
- signal tied_to_ground_i : std_logic;
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
- signal tied_to_vcc_i : std_logic;
-
- signal gt0_pll0clk_i : std_logic;
- signal gt0_pll0refclk_i : std_logic;
- signal gt0_pll1clk_i : std_logic;
- signal gt0_pll1refclk_i : std_logic;
- signal gt0_rst_i : std_logic;
-
---*************************** Component Declarations **************************
-component east_channel_gt
-generic
-(
- -- Simulation attributes
- GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
- TXSYNC_OVRD_IN : bit := '0';
- TXSYNC_MULTILANE_IN : bit := '0'
-);
-port
-(
- STABLE_CLOCK : in std_logic; -- System Clock
- RST_IN : in std_logic; -- Connect to System Reset
- DRP_BUSY_OUT : out std_logic; -- Indicates that the DRP bus is not accessible to the User
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- DRPADDR_IN : in std_logic_vector(8 downto 0);
- DRPCLK_IN : in std_logic;
- DRPDI_IN : in std_logic_vector(15 downto 0);
- DRPDO_OUT : out std_logic_vector(15 downto 0);
- DRPEN_IN : in std_logic;
- DRPRDY_OUT : out std_logic;
- DRPWE_IN : in std_logic;
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK_IN : in std_logic;
- PLL0REFCLK_IN : in std_logic;
- PLL1CLK_IN : in std_logic;
- PLL1REFCLK_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK_IN : in std_logic_vector(2 downto 0);
- RXPD_IN : in std_logic_vector(1 downto 0);
- TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- eyescanreset_in : in std_logic;
- RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- rxprbserr_out : out std_logic;
- rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- eyescandataerror_out : out std_logic;
- eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN_IN : in std_logic;
- GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
- rxbyteisaligned_out : out std_logic;
- RXBYTEREALIGN_OUT : out std_logic;
- rxcommadet_out : out std_logic;
- RXMCOMMAALIGNEN_IN : in std_logic;
- RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET_IN : in std_logic;
- rxpcsreset_in : in std_logic;
- rxpmareset_in : in std_logic;
- rxlpmreset_in : in std_logic;
- RXDATA_OUT : out std_logic_vector(31 downto 0);
- RXOUTCLK_OUT : out std_logic;
- RXUSRCLK_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRLOCK_OUT : out std_logic;
- RXLPMHFHOLD_IN : in std_logic;
- RXLPMLFHOLD_IN : in std_logic;
- rxlpmhfovrden_in : in std_logic;
- rxcdrhold_in : in std_logic;
- dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- rxbufreset_in : in std_logic;
- RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRESETDONE_OUT : out std_logic;
- RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- txpostcursor_in : in std_logic_vector(4 downto 0);
- txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- txchardispmode_in : in std_logic_vector(3 downto 0);
- txchardispval_in : in std_logic_vector(3 downto 0);
- TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET_IN : in std_logic;
- TXDATA_IN : in std_logic_vector(31 downto 0);
- TXOUTCLK_OUT : out std_logic;
- TXOUTCLKFABRIC_OUT : out std_logic;
- TXOUTCLKPCS_OUT : out std_logic;
- TXUSRCLK_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN_OUT : out std_logic;
- GTPTXP_OUT : out std_logic;
- txdiffctrl_in : in std_logic_vector(3 downto 0);
- txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- txpcsreset_in : in std_logic;
- txinhibit_in : in std_logic;
- txpmareset_in : in std_logic;
- TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- txpolarity_in : in std_logic
-
-);
-end component;
-
---********************************* Main Body of Code**************************
-
-begin
-
- tied_to_ground_i <= '0';
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');
- tied_to_vcc_i <= '1';
-
- gt0_pll0clk_i <= GT0_PLL0OUTCLK_IN;
- gt0_pll0refclk_i <= GT0_PLL0OUTREFCLK_IN;
- gt0_pll1clk_i <= GT0_PLL1OUTCLK_IN;
- gt0_pll1refclk_i <= GT0_PLL1OUTREFCLK_IN;
- gt0_rst_i <= GT0_PLL0RESET_IN;
-
- --------------------------- GT Instances -------------------------------
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- gt0_east_channel_i : east_channel_gt
- generic map
- (
- -- Simulation attributes
- GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
- TXSYNC_OVRD_IN => ('0'),
- TXSYNC_MULTILANE_IN => ('0')
- )
- port map
- (
-
- STABLE_CLOCK => STABLE_CLOCK,
- RST_IN => gt0_rst_i,
- DRP_BUSY_OUT => GT0_DRP_BUSY_OUT,
-
- ---------------------------- Channel - DRP Ports --------------------------
- DRPADDR_IN => GT0_DRPADDR_IN,
- DRPCLK_IN => GT0_DRPCLK_IN,
- DRPDI_IN => GT0_DRPDI_IN,
- DRPDO_OUT => GT0_DRPDO_OUT,
- DRPEN_IN => GT0_DRPEN_IN,
- DRPRDY_OUT => GT0_DRPRDY_OUT,
- DRPWE_IN => GT0_DRPWE_IN,
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK_IN => gt0_pll0clk_i,
- PLL0REFCLK_IN => gt0_pll0refclk_i,
- PLL1CLK_IN => gt0_pll1clk_i,
- PLL1REFCLK_IN => gt0_pll1refclk_i,
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK_IN => GT0_LOOPBACK_IN,
- RXPD_IN => GT0_RXPD_IN,
- TXPD_IN => GT0_TXPD_IN,
- ------------------------------- Receive Ports ------------------------------
- eyescanreset_in => gt0_eyescanreset_in,
- RXUSERRDY_IN => GT0_RXUSERRDY_IN,
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- rxprbserr_out => gt0_rxprbserr_out,
- rxprbssel_in => gt0_rxprbssel_in,
- ------------------- Receive Ports - Pattern Checker ports ------------------
- rxprbscntreset_in => gt0_rxprbscntreset_in,
- -------------------------- RX Margin Analysis Ports ------------------------
- eyescandataerror_out => gt0_eyescandataerror_out,
- eyescantrigger_in => gt0_eyescantrigger_in,
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT,
- RXCHARISK_OUT => GT0_RXCHARISK_OUT,
- RXDISPERR_OUT => GT0_RXDISPERR_OUT,
- RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT,
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN_IN => GT0_GTPRXN_IN,
- GTPRXP_IN => GT0_GTPRXP_IN,
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- rxbyteisaligned_out => gt0_rxbyteisaligned_out,
- RXBYTEREALIGN_OUT => GT0_RXBYTEREALIGN_OUT,
- rxcommadet_out => gt0_rxcommadet_out,
- RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN,
- RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET_IN => GT0_GTRXRESET_IN,
- rxpcsreset_in => gt0_rxpcsreset_in,
- rxpmareset_in => gt0_rxpmareset_in,
- rxlpmreset_in => gt0_rxlpmreset_in,
- RXDATA_OUT => GT0_RXDATA_OUT,
- RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
- RXUSRCLK_IN => GT0_RXUSRCLK_IN,
- RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
- RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN,
- RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN,
- rxlpmhfovrden_in => gt0_rxlpmhfovrden_in,
- rxcdrhold_in => gt0_rxcdrhold_in,
- dmonitorout_out => gt0_dmonitorout_out,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- rxbufreset_in => gt0_rxbufreset_in,
- RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRESETDONE_OUT => GT0_RXRESETDONE_OUT,
- RXPMARESETDONE_OUT => GT0_RXPMARESETDONE_OUT,
- ------------------------ TX Configurable Driver Ports ----------------------
- txpostcursor_in => gt0_txpostcursor_in,
- txprecursor_in => gt0_txprecursor_in,
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY_IN => GT0_RXPOLARITY_IN,
- ------------------------------- Transmit Ports -----------------------------
- TXUSERRDY_IN => GT0_TXUSERRDY_IN,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- txchardispmode_in => gt0_txchardispmode_in,
- txchardispval_in => gt0_txchardispval_in,
- TXCHARISK_IN => GT0_TXCHARISK_IN,
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS_OUT => GT0_TXBUFSTATUS_OUT,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET_IN => GT0_GTTXRESET_IN,
- TXDATA_IN => GT0_TXDATA_IN,
- TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
- TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT,
- TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT,
- TXUSRCLK_IN => GT0_TXUSRCLK_IN,
- TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
- --------------------- Transmit Ports - PCI Express Ports -------------------
- txelecidle_in => gt0_txelecidle_in,
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- txprbsforceerr_in => gt0_txprbsforceerr_in,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN_OUT => GT0_GTPTXN_OUT,
- GTPTXP_OUT => GT0_GTPTXP_OUT,
- txdiffctrl_in => gt0_txdiffctrl_in,
- txmaincursor_in => gt0_txmaincursor_in,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- txpcsreset_in => gt0_txpcsreset_in,
- txinhibit_in => GT0_txinhibit_in,
- txpmareset_in => gt0_txpmareset_in,
- TXRESETDONE_OUT => GT0_TXRESETDONE_OUT,
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- txprbssel_in => gt0_txprbssel_in,
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- txpolarity_in => gt0_txpolarity_in
-
-
- );
-
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_rx_startup_fsm.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_rx_startup_fsm.vhd
deleted file mode 100644
index d4a3740d5621cc400e7bbe6ecc084ef172d1c3c8..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_rx_startup_fsm.vhd
+++ /dev/null
@@ -1,978 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity east_channel_rx_startup_fsm is
- Generic(
- EXAMPLE_SIMULATION : integer := 0;
- GT_TYPE : string := "GTP";
- STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- RXPMARESETDONE : in STD_LOGIC;
- RXOUTCLK : in STD_LOGIC;
- TXPMARESETDONE : in STD_LOGIC;
- TXOUTCLK : in STD_LOGIC;
-
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- RXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- RECCLK_STABLE : in STD_LOGIC;
- RECCLK_MONITOR_RESTART : in STD_LOGIC:='0';
- DATA_VALID : in STD_LOGIC;
- TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
- DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected
- GTRXRESET : out STD_LOGIC;
- MMCM_RESET : out STD_LOGIC;
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0 (only if RX uses PLL0)
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1 (only if RX uses PLL1)
- RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
- RXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC;
- PHALIGNMENT_DONE : in STD_LOGIC;
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end east_channel_RX_STARTUP_FSM;
-
---Interdependencies:
--- * Timing depends on the frequency of the stable clock. Hence counters-sizes
--- are calculated at design-time based on the Generics
---
--- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
--- => signal which PLL has been reset
--- *
-
-
-
-architecture RTL of east_channel_RX_STARTUP_FSM is
-
- component east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
- type rx_rst_fsm_type is(
- INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
- RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
- MONITOR_DATA_VALID, FSM_DONE);
-
- signal rx_state : rx_rst_fsm_type := INIT;
-
- constant MMCM_LOCK_CNT_MAX : integer := 1024;
- constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
- constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
- constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
- constant WAIT_TIMEOUT_2ms : integer := 5000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
- constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
- constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out
- constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out
- constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
- constant WAIT_TIME_ADAPT : integer := (37000000 /integer(5.0))/STABLE_CLOCK_PERIOD;
- constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
-
- signal init_wait_count : integer range 0 to WAIT_MAX:=0;
- signal init_wait_done : std_logic := '0';
- signal pll_reset_asserted : std_logic := '0';
- signal rx_fsm_reset_done_int : std_logic := '0';
- signal rx_fsm_reset_done_int_s2 : std_logic := '0';
- signal rx_fsm_reset_done_int_s3 : std_logic := '0';
-
- signal rxresetdone_s2 : std_logic := '0';
- signal rxresetdone_s3 : std_logic := '0';
-
- constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
- signal retry_counter_int : integer range 0 to MAX_RETRIES := 0;
- signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
- signal recclk_mon_restart_count : integer range 0 to 3:= 0;
- signal recclk_mon_count_reset : std_logic := '0';
-
- signal reset_time_out : std_logic := '0';
- signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
- signal time_tlock_max : std_logic := '0';--|have been reached.
- signal time_out_500us : std_logic := '0';--|
- signal time_out_1us : std_logic := '0';--/
- signal time_out_100us : std_logic := '0';--/
- signal check_tlock_max : std_logic := '0';
-
- signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
- signal mmcm_lock_int : std_logic := '0';
- signal mmcm_lock_i : std_logic := '0';
- signal mmcm_lock_reclocked : std_logic := '0';
- signal gtrxreset_i : std_logic := '0';
- signal gtrxreset_s : std_logic := '0';
- signal mmcm_reset_i : std_logic := '1';
- signal rxpmaresetdone_i : std_logic := '0';
- signal txpmaresetdone_i : std_logic := '0';
- signal rxpmaresetdone_ss : std_logic := '0';
- signal rxpmaresetdone_sync : std_logic ;
- signal txpmaresetdone_sync : std_logic ;
- signal rxpmaresetdone_s : std_logic ;
- signal rxpmaresetdone_rx_s : std_logic ;
- signal pmaresetdone_fallingedge_detect : std_logic ;
- signal pmaresetdone_fallingedge_detect_s : std_logic ;
-
- signal run_phase_alignment_int: std_logic := '0';
- signal run_phase_alignment_int_s2 : std_logic := '0';
- signal run_phase_alignment_int_s3 : std_logic := '0';
-
- constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
- signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
- signal time_out_wait_bypass : std_logic := '0';
- signal time_out_wait_bypass_s2 : std_logic := '0';
- signal time_out_wait_bypass_s3 : std_logic := '0';
-
- signal refclk_lost : std_logic;
-
- signal data_valid_sync: std_logic := '0';
- signal pll0lock_sync: std_logic := '0';
- signal pll1lock_sync: std_logic := '0';
- signal pll0lock_prev: std_logic := '0';
- signal pll1lock_prev: std_logic := '0';
- signal pll0lock_ris_edge: std_logic := '0';
- signal pll1lock_ris_edge: std_logic := '0';
- signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
- signal wait_time_done : std_logic;
-begin
- --Alias section, signals used within this module mapped to output ports:
- RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
- RUN_PHALIGNMENT <= run_phase_alignment_int;
- RX_FSM_RESET_DONE <= rx_fsm_reset_done_int_s2;
- GTRXRESET <= gtrxreset_i;
- MMCM_RESET <= mmcm_reset_i;
- process(STABLE_CLOCK,SOFT_RESET)
- begin
- if (SOFT_RESET = '1') then
- init_wait_done <= '0';
- init_wait_count <= 0 ;
- elsif rising_edge(STABLE_CLOCK) then
- -- The counter starts running when configuration has finished and
- -- the clock is stable. When its maximum count-value has been reached,
- -- the 500 ns from Answer Record 43482 have been passed.
- if init_wait_count = WAIT_MAX then
- init_wait_done <= '1';
- else
- init_wait_count <= init_wait_count + 1;
- end if;
- end if;
- end process;
-
-
-
-
- process(RXOUTCLK,gtrxreset_s)
- begin
- if (gtrxreset_s = '1') then
- rxpmaresetdone_i <= '0';
- elsif rising_edge(RXOUTCLK) then
- rxpmaresetdone_i <= rxpmaresetdone_rx_s;
- end if;
- end process;
-
-gtrxreset_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => gtrxreset_i ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXOUTCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gtrxreset_s ,
- scndry_vect_out => open
- );
-
-sync_pmaresetdone_fallingedge_detect_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => pmaresetdone_fallingedge_detect ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXOUTCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pmaresetdone_fallingedge_detect_s ,
- scndry_vect_out => open
- );
-
-sync_rxpmaresetdone_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => RXOUTCLK ,
- prmry_resetn => '1' ,
- prmry_in => rxpmaresetdone_i ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxpmaresetdone_sync ,
- scndry_vect_out => open
- );
-
-sync_rxpmaresetdone_rx_s_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => RXPMARESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXOUTCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxpmaresetdone_rx_s ,
- scndry_vect_out => open
- );
-
-
-
- process(TXOUTCLK,gtrxreset_s)
- begin
- if (gtrxreset_s = '1') then
- txpmaresetdone_i <= '0';
- elsif rising_edge(TXOUTCLK) then
- txpmaresetdone_i <= TXPMARESETDONE;
- end if;
- end process;
-
-sync_txpmaresetdone_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => TXOUTCLK ,
- prmry_resetn => '1' ,
- prmry_in => txpmaresetdone_i ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => txpmaresetdone_sync ,
- scndry_vect_out => open
- );
-
- pmaresetdone_fallingedge_detect <= '0';
- retries_recclk_monitor:process(STABLE_CLOCK)
- begin
- --This counter monitors, how many retries the RECCLK monitor
- --runs. If during startup too many retries are necessary, the whole
- --initialisation-process of the transceivers gets restarted.
- if rising_edge(STABLE_CLOCK) then
- if recclk_mon_count_reset = '1' then
- recclk_mon_restart_count <= 0;
- elsif RECCLK_MONITOR_RESTART = '1' then
- if recclk_mon_restart_count = 3 then
- recclk_mon_restart_count <= 0;
- else
- recclk_mon_restart_count <= recclk_mon_restart_count + 1;
- end if;
- end if;
- end if;
- end process;
-
- timeouts:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- -- One common large counter for generating three time-out signals.
- -- Intermediate time-outs are derived from calculated values, based
- -- on the period of the provided clock.
- if reset_time_out = '1' then
- time_out_counter <= 0;
- time_out_2ms <= '0';
- time_tlock_max <= '0';
- time_out_500us <= '0';
- time_out_1us <= '0';
- time_out_100us <= '0';
- else
- if time_out_counter = WAIT_TIMEOUT_2ms then
- time_out_2ms <= '1';
- else
- time_out_counter <= time_out_counter + 1;
- end if;
-
- if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
- time_tlock_max <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_500us then
- time_out_500us <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_1us then
- time_out_1us <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_100us then
- time_out_100us <= '1';
- end if;
-
- end if;
- end if;
- end process;
-
-
-
- mmcm_lock_wait:process(STABLE_CLOCK)
- begin
- --The lock-signal from the MMCM is not immediately used but
- --enabling a counter. Only when the counter hits its maximum,
- --the MMCM is considered as "really" locked.
- --The counter avoids that the FSM already starts on only a
- --coarse lock of the MMCM (=toggling of the LOCK-signal).
- if rising_edge(STABLE_CLOCK) then
- if mmcm_lock_i = '0' then
- mmcm_lock_count <= 0;
- mmcm_lock_reclocked <= '0';
- else
- if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
- mmcm_lock_count <= mmcm_lock_count + 1;
- else
- mmcm_lock_reclocked <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
- -- Clock Domain Crossing
-
-sync_run_phase_alignment_int_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => run_phase_alignment_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => run_phase_alignment_int_s2 ,
- scndry_vect_out => open
- );
-
-sync_rx_fsm_reset_done_int_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => rx_fsm_reset_done_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rx_fsm_reset_done_int_s2 ,
- scndry_vect_out => open
- );
-
- process(RXUSERCLK)
- begin
- if rising_edge(RXUSERCLK) then
- run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
-
- rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
- end if;
- end process;
-
-sync_RXRESETDONE_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => RXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => RXRESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxresetdone_s2 ,
- scndry_vect_out => open
- );
-
-sync_time_out_wait_bypass_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => RXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => time_out_wait_bypass ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => time_out_wait_bypass_s2 ,
- scndry_vect_out => open
- );
-
-sync_mmcm_lock_reclocked_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => MMCM_LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => mmcm_lock_i ,
- scndry_vect_out => open
- );
-
- data_valid_sync <= DATA_VALID;
-
- process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- rxresetdone_s3 <= rxresetdone_s2;
-
- time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
- pll0lock_prev <= pll0lock_sync;
- pll1lock_prev <= pll1lock_sync;
- end if;
- end process;
-
-
-
-sync_PLL0LOCK_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL0LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll0lock_sync ,
- scndry_vect_out => open
- );
-
-sync_PLL1LOCK_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL1LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll1lock_sync ,
- scndry_vect_out => open
- );
-
-
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll0lock_ris_edge <= '0';
- elsif((pll0lock_prev = '0') and (pll0lock_sync = '1')) then
- pll0lock_ris_edge <= '1';
- elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
- pll0lock_ris_edge <= pll0lock_ris_edge;
- else
- pll0lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll1lock_ris_edge <= '0';
- elsif((pll1lock_prev = '0') and (pll1lock_sync = '1')) then
- pll1lock_ris_edge <= '1';
- elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
- pll1lock_ris_edge <= pll1lock_ris_edge;
- else
- pll1lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
- timeout_buffer_bypass:process(RXUSERCLK)
- begin
- if rising_edge(RXUSERCLK) then
- if run_phase_alignment_int_s3 = '0' then
- wait_bypass_count <= 0;
- time_out_wait_bypass <= '0';
- elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
- if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
- time_out_wait_bypass <= '1';
- else
- wait_bypass_count <= wait_bypass_count + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- refclk_lost <= '1' when ((RX_PLL0_USED and PLL0REFCLKLOST = '1') or (not RX_PLL0_USED and PLL1REFCLKLOST = '1')) else '0';
-
-
- timeout_max:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if((rx_state = ASSERT_ALL_RESETS) or
- (rx_state = RELEASE_MMCM_RESET)) then
- wait_time_cnt <= WAIT_TIME_MAX;
- elsif (wait_time_cnt > 0 ) then
- wait_time_cnt <= wait_time_cnt - 1;
- end if;
- end if;
- end process;
-
- wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
-
- --FSM for resetting the GTX/GTH/GTP in the 7-series.
- --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- --
- -- Following steps are performed:
- -- 1) After configuration wait for approximately 500 ns as specified in
- -- answer-record 43482
- -- 2) Assert all resets on the GT and on an MMCM potentially connected.
- -- After that wait until a reference-clock has been detected.
- -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
- -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
- -- Also get info from the TX-side which PLL has been reset.
- -- 5) Wait for the RESET_DONE-signal from the GT.
- -- 6) Signal to start the phase-alignment procedure and wait for it to
- -- finish.
- -- 7) Reset-sequence has successfully run through. Signal this to the
- -- rest of the design by asserting RX_FSM_RESET_DONE.
-
- reset_fsm:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if (SOFT_RESET = '1' ) then
- --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
- rx_state <= INIT;
- RXUSERRDY <= '0';
- gtrxreset_i <= '0';
- mmcm_reset_i <= '1';
- rx_fsm_reset_done_int <= '0';
- PLL0_RESET <= '0';
- PLL1_RESET <= '0';
- pll_reset_asserted <= '0';
- reset_time_out <= '1';
- retry_counter_int <= 0;
- run_phase_alignment_int <= '0';
- check_tlock_max <= '0';
- RESET_PHALIGNMENT <= '1';
- recclk_mon_count_reset <= '1';
-
- else
-
- case rx_state is
- when INIT =>
- --Initial state after configuration. This state will be left after
- --approx. 500 ns and not be re-entered.
- if init_wait_done = '1' then
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when ASSERT_ALL_RESETS =>
- --This is the state into which the FSM will always jump back if any
- --time-outs will occur.
- --The number of retries is reported on the output RETRY_COUNTER. In
- --case the transceiver never comes up for some reason, this machine
- --will still continue its best and rerun until the FPGA is turned off
- --or the transceivers come up correctly.
- if RX_PLL0_USED and not TX_PLL0_USED then
- if pll_reset_asserted = '0' then
- PLL0_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL0_RESET <= '0';
- end if;
- elsif not RX_PLL0_USED and TX_PLL0_USED then
- if pll_reset_asserted = '0' then
- PLL1_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL1_RESET <= '0';
- end if;
- end if;
-
- RXUSERRDY <= '0';
- gtrxreset_i <= '1';
- mmcm_reset_i <= '1';
- run_phase_alignment_int <= '0';
- RESET_PHALIGNMENT <= '1';
- check_tlock_max <= '0';
- recclk_mon_count_reset <= '1';
- if (RX_PLL0_USED and not TX_PLL0_USED and (pll0lock_sync = '0') and pll_reset_asserted = '1') or
- (not RX_PLL0_USED and TX_PLL0_USED and (pll1lock_sync = '0') and pll_reset_asserted = '1') or
- (RX_PLL0_USED and TX_PLL0_USED ) or
- (not RX_PLL0_USED and not TX_PLL0_USED ) then
- rx_state <= WAIT_FOR_PLL_LOCK;
- reset_time_out <= '1';
- end if;
-
- when WAIT_FOR_PLL_LOCK =>
- if(wait_time_done = '1') then
- rx_state <= RELEASE_PLL_RESET;
- end if;
-
- when RELEASE_PLL_RESET =>
- --PLL-Reset of the GTX gets released and the time-out counter
- --starts running.
- pll_reset_asserted <= '0';
- reset_time_out <= '0';
-
- if (RX_PLL0_USED and not TX_PLL0_USED and (pll0lock_sync = '1')) or
- (not RX_PLL0_USED and TX_PLL0_USED and (pll1lock_sync = '1')) then
- rx_state <= VERIFY_RECCLK_STABLE;
- reset_time_out <= '1';
- recclk_mon_count_reset <= '0';
- elsif (RX_PLL0_USED and (pll0lock_sync = '1')) or
- (not RX_PLL0_USED and (pll1lock_sync = '1')) then
- rx_state <= VERIFY_RECCLK_STABLE;
- reset_time_out <= '1';
- recclk_mon_count_reset <= '0';
- end if;
-
- if time_out_2ms = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when VERIFY_RECCLK_STABLE =>
- --reset_time_out <= '0';
- --Time-out counter is not released in this state as here the FSM
- --does not wait for a certain period of time but checks on the number
- --of retries in the RECCLK monitor
- gtrxreset_i <= '0';
- if RECCLK_STABLE = '1' then
- rx_state <= RELEASE_MMCM_RESET;
- reset_time_out <= '1';
-
- end if;
-
- if recclk_mon_restart_count = 2 then
- --If two retries are performed in the RECCLK monitor
- --the whole initialisation-sequence gets restarted.
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when RELEASE_MMCM_RESET =>
- --Release of the MMCM-reset. Waiting for the MMCM to lock.
- check_tlock_max <= '1';
-
- mmcm_reset_i <= '0';
- reset_time_out <= '0';
-
- if mmcm_lock_reclocked = '1' then
- rx_state <= WAIT_FOR_RXUSRCLK;
- reset_time_out <= '1';
- end if;
-
- if (time_tlock_max = '1' and reset_time_out = '0' )then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when WAIT_FOR_RXUSRCLK =>
- if wait_time_done = '1' then
- rx_state <= WAIT_RESET_DONE;
- end if;
-
- when WAIT_RESET_DONE =>
- --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
- --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
- if TXUSERRDY = '1' then
- RXUSERRDY <= '1';
- end if;
- reset_time_out <= '0';
- if rxresetdone_s3 = '1' then
- rx_state <= DO_PHASE_ALIGNMENT;
- reset_time_out <= '1';
- end if;
-
- if time_out_2ms = '1' and reset_time_out = '0' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when DO_PHASE_ALIGNMENT =>
- --The direct handling of the signals for the Phase Alignment is done outside
- --this state-machine.
- RESET_PHALIGNMENT <= '0';
- run_phase_alignment_int <= '1';
- reset_time_out <= '0';
-
- if PHALIGNMENT_DONE = '1' then
- rx_state <= MONITOR_DATA_VALID;
- reset_time_out <= '1';
- end if;
-
- if time_out_wait_bypass_s3 = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when MONITOR_DATA_VALID =>
- reset_time_out <= '0';
-
- if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then
- rx_state <= ASSERT_ALL_RESETS;
- rx_fsm_reset_done_int <= '0';
- elsif (data_valid_sync = '1') then
- rx_state <= FSM_DONE;
- rx_fsm_reset_done_int <= '0';
- reset_time_out <= '1';
- end if;
-
- when FSM_DONE =>
- reset_time_out <= '0';
- if data_valid_sync = '0' then
- rx_fsm_reset_done_int <= '0';
- reset_time_out <= '1';
- rx_state <= MONITOR_DATA_VALID;
- elsif(time_out_1us = '1' and reset_time_out = '0') then
- rx_fsm_reset_done_int <= '1';
- end if;
-
- when OTHERS =>
- rx_state <= INIT;
- end case;
- end if;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_transceiver_wrapper.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_transceiver_wrapper.vhd
deleted file mode 100644
index de2ca965e299241bd2fdfea5ab29570c43f4a351..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_transceiver_wrapper.vhd
+++ /dev/null
@@ -1,849 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
--- Module east_channel_GT_WRAPPER
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
-entity east_channel_GT_WRAPPER is
-generic
-(
- QPLL_FBDIV_TOP : integer := 40;
- -- Simulation attribute
- EXAMPLE_SIMULATION : integer := 0;
- SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
-);
-
-port
-(
-
----------------------- Loopback and Powerdown Ports ----------------------
-LOOPBACK_IN : in std_logic_vector (2 downto 0);
---------------------- Receive Ports - 8b10b Decoder ----------------------
-RXCHARISCOMMA_OUT : out std_logic_vector (3 downto 0);
-RXCHARISK_OUT : out std_logic_vector (3 downto 0);
-RXDISPERR_OUT : out std_logic_vector (3 downto 0);
-RXNOTINTABLE_OUT : out std_logic_vector (3 downto 0);
------------------ Receive Ports - Channel Bonding Ports -----------------
-ENCHANSYNC_IN : in std_logic;
-CHBONDDONE_OUT : out std_logic;
------------------ Receive Ports - Clock Correction Ports -----------------
-RXBUFERR_OUT : out std_logic;
-------------- Receive Ports - Comma Detection and Alignment --------------
-RXREALIGN_OUT : out std_logic;
-ENMCOMMAALIGN_IN : in std_logic;
-ENPCOMMAALIGN_IN : in std_logic;
------------------ Receive Ports - RX Data Path interface -----------------
-RXDATA_OUT : out std_logic_vector (31 downto 0);
-RXRESET_IN : in std_logic;
-RXUSRCLK_IN : in std_logic;
-RXUSRCLK2_IN : in std_logic;
------ Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-RX1N_IN : in std_logic;
-RX1P_IN : in std_logic;
---------------- Receive Ports - RX Polarity Control Ports ----------------
-RXPOLARITY_IN : in std_logic;
-------------------- Shared Ports - Tile and PLL Ports --------------------
-REFCLK : in std_logic;
-INIT_CLK_IN : in std_logic;
-PLL_NOT_LOCKED : in std_logic;
-GTRESET_IN : in std_logic;
-PLLLKDET_OUT : out std_logic;
- gt0_txresetdone_out : out std_logic;
- gt0_rxresetdone_out : out std_logic;
- gt0_rxpmaresetdone_out : out std_logic;
- gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
- gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
-TX_RESETDONE_OUT : out std_logic;
-RX_RESETDONE_OUT : out std_logic;
--------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-TXCHARISK_IN : in std_logic_vector (3 downto 0);
----------------- Transmit Ports - TX Data Path interface -----------------
-TXDATA_IN : in std_logic_vector (31 downto 0);
-TXOUTCLK1_OUT : out std_logic;
-TXRESET_IN : in std_logic;
-TXUSRCLK_IN : in std_logic;
-TXUSRCLK2_IN : in std_logic;
-TXBUFERR_OUT : out std_logic;
-------------- Transmit Ports - TX Driver and OOB signalling --------------
-TX1N_OUT : out std_logic;
-TX1P_OUT : out std_logic;
----------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
-DRPADDR_IN : in std_logic_vector(8 downto 0);
-DRPCLK_IN : in std_logic;
-DRPDI_IN : in std_logic_vector(15 downto 0);
-DRPDO_OUT : out std_logic_vector(15 downto 0);
-DRPEN_IN : in std_logic;
-DRPRDY_OUT : out std_logic;
-DRPWE_IN : in std_logic;
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
-
-GTRXRESET_IN : in std_logic;
-LINK_RESET_IN : in std_logic;
-RXFSM_DATA_VALID : in std_logic;
-POWERDOWN_IN : in std_logic
-);
-
-end east_channel_GT_WRAPPER;
-
-
-architecture MAPPED of east_channel_GT_WRAPPER is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
- attribute core_generation_info : string;
-attribute core_generation_info of MAPPED : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- -- Parameter Declarations --
- constant DLY : time := 1 ns;
-
- component east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
-
---***************************** Compopnent Declaration ****************************
-
-component east_channel_tx_startup_fsm
- Generic(
- GT_TYPE : string := "GTP";
- STABLE_CLOCK_PERIOD : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- TXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- GTTXRESET : out STD_LOGIC:='0';
- MMCM_RESET : out STD_LOGIC:='0';
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1
- TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
- TXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC:='0';
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- PHALIGNMENT_DONE : in STD_LOGIC;
-
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end component;
-
-component east_channel_rx_startup_fsm
- Generic(
- EXAMPLE_SIMULATION : integer := 0;
- GT_TYPE : string := "GTP";
- STABLE_CLOCK_PERIOD : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- RXPMARESETDONE : in STD_LOGIC;
- RXOUTCLK : in STD_LOGIC;
- TXPMARESETDONE : in STD_LOGIC;
- TXOUTCLK : in STD_LOGIC;
-
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- RXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- RECCLK_STABLE : in STD_LOGIC;
- RECCLK_MONITOR_RESTART : in STD_LOGIC;
- DATA_VALID : in STD_LOGIC;
- TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
- DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
- GTRXRESET : out STD_LOGIC:='0';
- MMCM_RESET : out STD_LOGIC:='0';
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0 (only if RX uses PLL0)
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1 (only if RX uses PLL1)
- RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
- RXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC;
- PHALIGNMENT_DONE : in STD_LOGIC;
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end component;
-
-component east_channel_multi_gt is
-generic
-(
- -- Simulation attributes
- WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
-);
-port
-(
- STABLE_CLOCK : in std_logic; -- System Clock
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- --____________________________CHANNEL PORTS________________________________
- GT0_DRP_BUSY_OUT : out std_logic;
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
- GT0_DRPCLK_IN : in std_logic;
- GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
- GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
- GT0_DRPEN_IN : in std_logic;
- GT0_DRPRDY_OUT : out std_logic;
- GT0_DRPWE_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
- GT0_RXPD_IN : in std_logic_vector(1 downto 0);
- GT0_TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- GT0_eyescanreset_in : in std_logic;
- GT0_RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- GT0_rxprbserr_out : out std_logic;
- GT0_rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- GT0_rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- GT0_eyescandataerror_out : out std_logic;
- GT0_eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GT0_GTPRXN_IN : in std_logic;
- GT0_GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GT0_rxbyteisaligned_out : out std_logic;
- GT0_RXBYTEREALIGN_OUT : out std_logic;
- GT0_rxcommadet_out : out std_logic;
- GT0_RXMCOMMAALIGNEN_IN : in std_logic;
- GT0_RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GT0_GTRXRESET_IN : in std_logic;
- GT0_rxpcsreset_in : in std_logic;
- GT0_rxpmareset_in : in std_logic;
- GT0_rxlpmreset_in : in std_logic;
- GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
- GT0_RXOUTCLK_OUT : out std_logic;
- GT0_RXUSRCLK_IN : in std_logic;
- GT0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GT0_RXCDRLOCK_OUT : out std_logic;
- GT0_RXLPMHFHOLD_IN : in std_logic;
- GT0_RXLPMLFHOLD_IN : in std_logic;
- GT0_rxlpmhfovrden_in : in std_logic;
- GT0_rxcdrhold_in : in std_logic;
- GT0_dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GT0_rxbufreset_in : in std_logic;
- GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GT0_RXRESETDONE_OUT : out std_logic;
- GT0_RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- GT0_txpostcursor_in : in std_logic_vector(4 downto 0);
- GT0_txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- GT0_RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- GT0_TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GT0_txchardispmode_in : in std_logic_vector(3 downto 0);
- GT0_txchardispval_in : in std_logic_vector(3 downto 0);
- GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- GT0_TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GT0_GTTXRESET_IN : in std_logic;
- GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
- GT0_TXOUTCLK_OUT : out std_logic;
- GT0_TXOUTCLKFABRIC_OUT : out std_logic;
- GT0_TXOUTCLKPCS_OUT : out std_logic;
- GT0_TXUSRCLK_IN : in std_logic;
- GT0_TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- GT0_txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- GT0_txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GT0_GTPTXN_OUT : out std_logic;
- GT0_GTPTXP_OUT : out std_logic;
- GT0_txdiffctrl_in : in std_logic_vector(3 downto 0);
- GT0_txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GT0_txpcsreset_in : in std_logic;
- GT0_txinhibit_in : in std_logic;
- GT0_txpmareset_in : in std_logic;
- GT0_TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- GT0_txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- GT0_txpolarity_in : in std_logic;
-
-
- --____________________________COMMON PORTS________________________________
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
- GT0_PLL0RESET_IN : in std_logic
-
-);
-end component;
-
-
- function get_cdrlock_time(is_sim : in integer) return integer is
- variable lock_time: integer;
- begin
- if (is_sim = 1) then
- lock_time := 1000;
- else
- lock_time := 50000 / integer(5.0); --Typical CDR lock time is 50,000UI as per DS181
- end if;
- return lock_time;
- end function;
-
---***********************************Parameter Declarations********************
-
- constant STABLE_CLOCK_PERIOD : integer := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
- constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
-
- signal tied_to_ground_i : std_logic;
- signal tied_to_ground_vec_i : std_logic_vector (63 downto 0);
- signal tied_to_vcc_i : std_logic;
-signal chbondi : std_logic_vector (3 downto 0);
-signal chbondo : std_logic_vector (3 downto 0);
- signal chbondi_unused_i : std_logic_vector (3 downto 0);
-
- signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
- signal rx_cdrlocked : std_logic;
- signal gt_recclk_stable_i : std_logic;
- signal gt_pll0refclklost_i : std_logic;
- signal gt_pll_lock_i : std_logic;
- signal gt0_txresetdone_i : std_logic;
- signal gt0_rxresetdone_i : std_logic;
- signal txfsm_txresetdone_i : std_logic;
- signal rxfsm_rxresetdone_i : std_logic;
- signal txfsm_txresetdone_r : std_logic;
- signal rxfsm_rxresetdone_r : std_logic;
- signal rxfsm_rxresetdone_r1 : std_logic;
- signal rxfsm_rxresetdone_r2 : std_logic;
- signal rxfsm_rxresetdone_r3 : std_logic;
- signal gt_tx_reset_i : std_logic;
- signal gt_rx_reset_i : std_logic;
- signal fsm_gt_rx_reset_t : std_logic;
- signal rxfsm_soft_reset_r : std_logic;
- signal gt_txuserrdy_i : std_logic;
- signal gt_rxuserrdy_i : std_logic;
- signal mmcm_lock_i : std_logic;
- signal mmcm_reset_i : std_logic;
-
- signal gtrxreset_sync : std_logic;
- signal gtrxreset_r1 : std_logic;
- signal gtrxreset_r2 : std_logic;
- signal gtrxreset_r3 : std_logic;
- signal gtrxreset_pulse : std_logic;
-
-
---Timing closure flipflops
- signal gt0_txresetdone_r : std_logic;
- signal gt0_txresetdone_r2 : std_logic;
- signal gt0_txresetdone_r3 : std_logic;
- signal gt0_rxresetdone_r : std_logic;
- signal gt0_rxresetdone_r2 : std_logic;
- signal gt0_rxresetdone_r3 : std_logic;
-
- signal link_reset_r : std_logic;
- signal link_reset_r2 : std_logic;
-
- signal common_reset_i : std_logic;
-
- --concatenation or temp signals
- signal powerdown_i : std_logic_vector(1 downto 0);
-signal rx_buf_status_i : std_logic_vector(2 downto 0);
-signal tx_buf_status_i : std_logic_vector(1 downto 0);
-
- signal gt0_txpmaresetdone_o : std_logic;
- signal TXOUTCLK_OUT : std_logic;
- signal gt_txpmaresetdone_i : std_logic;
- signal gt_txoutclk_out : std_logic;
-
-begin
-
- tied_to_ground_i <= '0';
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');
- tied_to_vcc_i <= '1';
-
-
- powerdown_i <= POWERDOWN_IN & POWERDOWN_IN;
- RXBUFERR_OUT <= rx_buf_status_i(2);
- TXBUFERR_OUT <= tx_buf_status_i(1);
- TXOUTCLK1_OUT <= TXOUTCLK_OUT;
-
-
- chbondi_unused_i <= "0000";
-
-
- --Connect channel bonding bus
-
- chbondi <= chbondi_unused_i;
- CHBONDDONE_OUT <= '1';
-
- gtrxreset_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => RXUSRCLK2_IN ,
- prmry_resetn => '1' ,
- prmry_in => GTRXRESET_IN ,
- prmry_vect_in => "00" ,
- scndry_aclk => INIT_CLK_IN ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gtrxreset_sync ,
- scndry_vect_out => open
- );
-
- process(INIT_CLK_IN)
- begin
- if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
- gtrxreset_r1 <= gtrxreset_sync after DLY;
- gtrxreset_r2 <= gtrxreset_r1 after DLY;
- gtrxreset_r3 <= gtrxreset_r2 after DLY;
- gtrxreset_pulse <= gtrxreset_r2 AND (NOT gtrxreset_r3) after DLY;
- end if;
- end process;
-
- process(INIT_CLK_IN)
- begin
- if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
- link_reset_r <= LINK_RESET_IN after DLY;
- link_reset_r2 <= link_reset_r after DLY;
- gt_rx_reset_i <= fsm_gt_rx_reset_t after DLY;
- rxfsm_soft_reset_r <= link_reset_r2 or GTRESET_IN or gtrxreset_pulse after DLY;
- end if;
- end process;
-
- mmcm_lock_i <= (not PLL_NOT_LOCKED);
-
- gt_common_reset_out <= common_reset_i;
-
- gt_pll0refclklost_i <= gt0_pll0refclklost_in;
-
- PLLLKDET_OUT <= quad1_common_lock_in and (not mmcm_reset_i);
-
- gt_pll_lock_i <= quad1_common_lock_in;
-
- gt0_txresetdone_out <= gt0_txresetdone_i;
- gt0_rxresetdone_out <= gt0_rxresetdone_i;
- gt0_txbufstatus_out <= tx_buf_status_i;
- gt0_rxbufstatus_out <= rx_buf_status_i;
-
- --TXRESETDONE for lane0
- process(TXUSRCLK2_IN)
- begin
- if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
- gt0_txresetdone_r <= gt0_txresetdone_i after DLY;
- gt0_txresetdone_r2 <= gt0_txresetdone_r after DLY;
- gt0_txresetdone_r3 <= gt0_txresetdone_r2 after DLY;
- end if;
- end process;
-
- --RXRESETDONE for lane0
- process(RXUSRCLK2_IN)
- begin
- if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
- gt0_rxresetdone_r <= gt0_rxresetdone_i after DLY;
- gt0_rxresetdone_r2 <= gt0_rxresetdone_r after DLY;
- gt0_rxresetdone_r3 <= gt0_rxresetdone_r2 after DLY;
- end if;
- end process;
-
-
- txfsm_txresetdone_i <= gt0_txresetdone_r3 ;
- rxfsm_rxresetdone_i <= gt0_rxresetdone_r3 ;
-
- process(TXUSRCLK2_IN)
- begin
- if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
- txfsm_txresetdone_r <= txfsm_txresetdone_i after DLY;
- end if;
- end process;
-
- process(RXUSRCLK2_IN)
- begin
- if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
- rxfsm_rxresetdone_r <= rxfsm_rxresetdone_i after DLY;
- rxfsm_rxresetdone_r2 <= rxfsm_rxresetdone_r after DLY;
- rxfsm_rxresetdone_r3 <= rxfsm_rxresetdone_r2 after DLY;
- end if;
- end process;
-
-
- process(RXUSRCLK2_IN)
- begin
- if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
- rxfsm_rxresetdone_r1 <= rxfsm_rxresetdone_i after DLY;
- end if;
- end process;
-
- RX_RESETDONE_OUT <= rxfsm_rxresetdone_r3;
-
- gt_txpmaresetdone_i <= '0';
-
-
-gt_txresetfsm_i: east_channel_tx_startup_fsm
-
- generic map(
- GT_TYPE => "GTP", --GTX or GTH or GTP
- STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH => 8,
- TX_PLL0_USED => TRUE , -- the TX and RX Reset FSMs must
- RX_PLL0_USED => TRUE, -- share these two generic values
- PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- )
- port map (
-
- STABLE_CLOCK => INIT_CLK_IN,
- TXUSERCLK => TXUSRCLK2_IN,
- SOFT_RESET => GTRESET_IN,
- PLL0REFCLKLOST => gt_pll0refclklost_i,
- PLL0LOCK => gt_pll_lock_i,
- PLL1REFCLKLOST => tied_to_ground_i,
- PLL1LOCK => tied_to_vcc_i,
- TXRESETDONE => txfsm_txresetdone_r,
- MMCM_LOCK => mmcm_lock_i,
- GTTXRESET => gt_tx_reset_i,
- MMCM_RESET => mmcm_reset_i,
- PLL0_RESET => common_reset_i,
- PLL1_RESET => open,
- TX_FSM_RESET_DONE => TX_RESETDONE_OUT,
- TXUSERRDY => gt_txuserrdy_i,
- RUN_PHALIGNMENT => open,
- RESET_PHALIGNMENT => open ,
- PHALIGNMENT_DONE => tied_to_vcc_i,
- RETRY_COUNTER => open
- );
-
-
-
-gt_rxresetfsm_i: east_channel_rx_startup_fsm
-
- generic map(
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
- GT_TYPE => "GTP", --GTX or GTH or GTP
- STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH => 8,
- TX_PLL0_USED => TRUE , -- the TX and RX Reset FSMs must
- RX_PLL0_USED => TRUE, -- share these two generic values
- PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- )
- port map (
- STABLE_CLOCK => INIT_CLK_IN,
- RXUSERCLK => RXUSRCLK2_IN,
- SOFT_RESET => rxfsm_soft_reset_r,
- RXPMARESETDONE => gt_txpmaresetdone_i,
- RXOUTCLK => RXUSRCLK2_IN,
- TXPMARESETDONE => tied_to_vcc_i,
- TXOUTCLK => TXUSRCLK2_IN,
-
- DONT_RESET_ON_DATA_ERROR => '0',
- PLL0REFCLKLOST => gt_pll0refclklost_i,
- PLL0LOCK => gt_pll_lock_i,
- PLL1REFCLKLOST => tied_to_ground_i,
- PLL1LOCK => tied_to_vcc_i,
- RXRESETDONE => rxfsm_rxresetdone_r1,
- MMCM_LOCK => tied_to_vcc_i,
- RECCLK_STABLE => gt_recclk_stable_i,
- RECCLK_MONITOR_RESTART => tied_to_ground_i,
- DATA_VALID => gt_rxuserrdy_i,
- TXUSERRDY => gt_txuserrdy_i,
- GTRXRESET => fsm_gt_rx_reset_t,
- MMCM_RESET => open,
- PLL0_RESET => open,
- PLL1_RESET => open,
- RX_FSM_RESET_DONE => open,
- RXUSERRDY => gt_rxuserrdy_i,
- RUN_PHALIGNMENT => open,
- RESET_PHALIGNMENT => open,
- PHALIGNMENT_DONE => tied_to_vcc_i,
- RETRY_COUNTER => open
- );
-
- cdrlock_timeout:process(INIT_CLK_IN)
- begin
- if rising_edge(INIT_CLK_IN) then
- if(gt_rx_reset_i = '1') then
- rx_cdrlocked <= '0';
- rx_cdrlock_counter <= 0 after DLY;
- elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
- rx_cdrlocked <= '1';
- rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
- else
- rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
- end if;
- end if;
- end process;
-
-gt_recclk_stable_i <= rx_cdrlocked;
-
-
- east_channel_multi_gt_i : east_channel_multi_gt
- generic map
- (
- -- Simulation attributes
- WRAPPER_SIM_GTRESET_SPEEDUP => SIM_GTRESET_SPEEDUP
-
- )
- port map
- (
- STABLE_CLOCK => INIT_CLK_IN,
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- --____________________________CHANNEL PORTS________________________________
- GT0_DRP_BUSY_OUT => open,
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
-GT0_DRPADDR_IN => DRPADDR_IN,
-GT0_DRPCLK_IN => DRPCLK_IN,
-GT0_DRPDI_IN => DRPDI_IN,
-GT0_DRPDO_OUT => DRPDO_OUT,
-GT0_DRPEN_IN => DRPEN_IN,
-GT0_DRPRDY_OUT => DRPRDY_OUT,
-GT0_DRPWE_IN => DRPWE_IN,
- ------------------------ Loopback and Powerdown Ports ----------------------
- GT0_LOOPBACK_IN => LOOPBACK_IN,
- GT0_RXPD_IN => powerdown_i,
- GT0_TXPD_IN => powerdown_i,
- ------------------------------- Receive Ports ------------------------------
- GT0_RXUSERRDY_IN => gt_rxuserrdy_i,
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
-GT0_RXCHARISCOMMA_OUT => RXCHARISCOMMA_OUT,
-GT0_RXCHARISK_OUT => RXCHARISK_OUT,
-GT0_RXDISPERR_OUT => RXDISPERR_OUT,
-GT0_RXNOTINTABLE_OUT => RXNOTINTABLE_OUT,
- ------------------------- Receive Ports - AFE Ports ------------------------
-GT0_GTPRXN_IN => RX1N_IN,
-GT0_GTPRXP_IN => RX1P_IN,
- ------------------- Receive Ports - Clock Correction Ports -----------------
- GT0_RXCLKCORCNT_OUT => open,
- --------------- Receive Ports - Comma Detection and Alignment --------------
-GT0_RXBYTEREALIGN_OUT => RXREALIGN_OUT,
-GT0_RXMCOMMAALIGNEN_IN => ENMCOMMAALIGN_IN,
-GT0_RXPCOMMAALIGNEN_IN => ENPCOMMAALIGN_IN,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GT0_GTRXRESET_IN => gt_rx_reset_i,
-GT0_RXDATA_OUT => RXDATA_OUT,
- GT0_RXOUTCLK_OUT => open,
- GT0_RXUSRCLK_IN => RXUSRCLK_IN,
- GT0_RXUSRCLK2_IN => RXUSRCLK2_IN,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GT0_RXCDRLOCK_OUT => open,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-GT0_RXBUFSTATUS_OUT => rx_buf_status_i,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
- GT0_RXPMARESETDONE_OUT => gt0_rxpmaresetdone_out,
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
-GT0_RXPOLARITY_IN => RXPOLARITY_IN,
- ------------------------------- Transmit Ports -----------------------------
- GT0_TXUSERRDY_IN => gt_txuserrdy_i,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-GT0_TXCHARISK_IN => TXCHARISK_IN,
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
-GT0_TXBUFSTATUS_OUT => tx_buf_status_i,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GT0_GTTXRESET_IN => gt_tx_reset_i,
-GT0_TXDATA_IN => TXDATA_IN,
-GT0_TXOUTCLK_OUT => TXOUTCLK_OUT,
- GT0_TXOUTCLKFABRIC_OUT => open,
- GT0_TXOUTCLKPCS_OUT => open,
- GT0_TXUSRCLK_IN => TXUSRCLK_IN,
- GT0_TXUSRCLK2_IN => TXUSRCLK2_IN,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-GT0_GTPTXN_OUT => TX1N_OUT,
-GT0_GTPTXP_OUT => TX1P_OUT,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
- --------------------- Transmit Ports - PCI Express Ports -------------------
- gt0_txelecidle_in => POWERDOWN_IN,
-
- gt0_rxlpmhfhold_in => tied_to_ground_i,
- gt0_rxlpmlfhold_in => tied_to_ground_i,
- gt0_eyescanreset_in => tied_to_ground_i,
- -------------------------- RX Margin Analysis Ports ------------------------
- gt0_eyescandataerror_out => open,
- gt0_eyescantrigger_in => tied_to_ground_i,
- gt0_rxbyteisaligned_out => open,
- gt0_rxcommadet_out => open,
- ------------------------ TX Configurable Driver Ports ----------------------
- gt0_txpostcursor_in => "00000",
- gt0_txprecursor_in => "00000",
- ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
- gt0_txchardispmode_in => "0000",
- gt0_txchardispval_in => "0000",
- gt0_txdiffctrl_in => "1000",
- gt0_txmaincursor_in => "0000000",
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- gt0_txpolarity_in => tied_to_ground_i,
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- gt0_rxprbserr_out => open,
- gt0_rxprbssel_in => "000",
- ------------------- Receive Ports - Pattern Checker ports ------------------
- gt0_rxprbscntreset_in => tied_to_ground_i,
- ------------------- Receive Ports - RX Data Path interface -----------------
- gt0_rxpcsreset_in => tied_to_ground_i,
- gt0_rxpmareset_in => tied_to_ground_i,
- gt0_rxlpmreset_in => tied_to_ground_i,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- gt0_rxlpmhfovrden_in => tied_to_ground_i,
- gt0_rxcdrhold_in => tied_to_ground_i,
- gt0_dmonitorout_out => open,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- gt0_rxbufreset_in => tied_to_ground_i,
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- gt0_txprbsforceerr_in => tied_to_ground_i,
- gt0_txprbssel_in => "000",
- ------------------- Transmit Ports - TX Data Path interface -----------------
- gt0_txpcsreset_in => tied_to_ground_i,
- gt0_txinhibit_in => tied_to_ground_i,
- gt0_txpmareset_in => tied_to_ground_i,
- --____________________________COMMON PORTS________________________________
- GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
- GT0_PLL0RESET_IN => common_reset_i
- );
-
-end MAPPED;
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_tx_startup_fsm.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_tx_startup_fsm.vhd
deleted file mode 100644
index 9c1bd3239818aa137a7df0ce080296da7483e10a..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_tx_startup_fsm.vhd
+++ /dev/null
@@ -1,724 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity east_channel_tx_startup_fsm is
- Generic(
- GT_TYPE : string := "GTP";
- EXAMPLE_SIMULATION : integer := 0;
-
- STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- TXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- GTTXRESET : out STD_LOGIC;
- MMCM_RESET : out STD_LOGIC:='1';
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1
- TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
- TXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC:='0';
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- PHALIGNMENT_DONE : in STD_LOGIC;
-
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end east_channel_TX_STARTUP_FSM;
-
---Interdependencies:
--- * Timing depends on the frequency of the stable clock. Hence counters-sizes
--- are calculated at design-time based on the Generics
---
--- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
--- => signal which PLL has been reset
--- *
-
-
-
-architecture RTL of east_channel_TX_STARTUP_FSM is
-
- component east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
- type tx_rst_fsm_type is(
- INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
- WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
- RESET_FSM_DONE);
-
- signal tx_state : tx_rst_fsm_type := INIT;
-
- constant MMCM_LOCK_CNT_MAX : integer := 1024;
- constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
- constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
- constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
-
- constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
- constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
- constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out
- constant WAIT_1us_cycles : integer := 1000 / STABLE_CLOCK_PERIOD;--1 us time-out
- constant WAIT_1us : integer := WAIT_1us_cycles+ 10; -- 1us plus some additional margin
-
- signal init_wait_count : integer range 0 to WAIT_MAX:=0;
- signal init_wait_done : std_logic := '0';
- signal pll_reset_asserted : std_logic := '0';
-
- signal tx_fsm_reset_done_int : std_logic := '0';
- signal tx_fsm_reset_done_int_s2 : std_logic := '0';
- signal tx_fsm_reset_done_int_s3 : std_logic := '0';
-
- signal txresetdone_s2 : std_logic := '0';
- signal txresetdone_s3 : std_logic := '0';
-
- constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
- signal retry_counter_int : integer range 0 to MAX_RETRIES;
- signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
-
- signal reset_time_out : std_logic := '0';
- signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
- signal time_tlock_max : std_logic := '0';--|have been reached.
- signal time_out_500us : std_logic := '0';--/
-
- signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
- signal mmcm_lock_int : std_logic := '0';
- signal mmcm_lock_i : std_logic := '0';
- signal mmcm_lock_reclocked : std_logic := '0';
-
- signal run_phase_alignment_int : std_logic := '0';
- signal run_phase_alignment_int_s2 : std_logic := '0';
- signal run_phase_alignment_int_s3 : std_logic := '0';
- constant MAX_WAIT_BYPASS : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
-
- constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
-
- signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
- signal time_out_wait_bypass : std_logic := '0';
- signal time_out_wait_bypass_s2 : std_logic := '0';
- signal time_out_wait_bypass_s3 : std_logic := '0';
- signal txuserrdy_i : std_logic := '0';
- signal refclk_lost : std_logic;
- signal gttxreset_i : std_logic := '0';
- signal txpmaresetdone_i : std_logic := '0';
- signal txpmaresetdone_sync : std_logic ;
-
- signal pll0lock_sync: std_logic := '0';
- signal pll1lock_sync: std_logic := '0';
- signal pll0lock_prev: std_logic := '0';
- signal pll1lock_prev: std_logic := '0';
- signal pll0lock_ris_edge: std_logic := '0';
- signal pll1lock_ris_edge: std_logic := '0';
- signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
- signal wait_time_done :std_logic;
-
-begin
- --Alias section, signals used within this module mapped to output ports:
- RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
- RUN_PHALIGNMENT <= run_phase_alignment_int;
- TX_FSM_RESET_DONE <= tx_fsm_reset_done_int_s2;
- GTTXRESET <= gttxreset_i;
-
- process(STABLE_CLOCK,SOFT_RESET)
- begin
- if (SOFT_RESET = '1') then
- init_wait_done <= '0';
- init_wait_count <= 0 ;
- elsif rising_edge(STABLE_CLOCK) then
- -- The counter starts running when configuration has finished and
- -- the clock is stable. When its maximum count-value has been reached,
- -- the 500 ns from Answer Record 43482 have been passed.
- if init_wait_count = WAIT_MAX then
- init_wait_done <= '1';
- else
- init_wait_count <= init_wait_count + 1;
- end if;
- end if;
- end process;
-
- timeouts:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- -- One common large counter for generating three time-out signals.
- -- Intermediate time-outs are derived from calculated values, based
- -- on the period of the provided clock.
- if reset_time_out = '1' then
- time_out_counter <= 0;
- time_out_2ms <= '0';
- time_tlock_max <= '0';
- time_out_500us <= '0';
- else
- if time_out_counter = WAIT_TIMEOUT_2ms then
- time_out_2ms <= '1';
- else
- time_out_counter <= time_out_counter + 1;
- end if;
-
- if time_out_counter = WAIT_TLOCK_MAX then
- time_tlock_max <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_500us then
- time_out_500us <= '1';
- end if;
- end if;
- end if;
- end process;
-
- mmcm_lock_wait:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if mmcm_lock_i = '0' then
- mmcm_lock_count <= 0;
- mmcm_lock_reclocked <= '0';
- else
- if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
- mmcm_lock_count <= mmcm_lock_count + 1;
- else
- mmcm_lock_reclocked <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
-
- -- Clock Domain Crossing
-
-sync_run_phase_alignment_int_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => run_phase_alignment_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => TXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => run_phase_alignment_int_s2 ,
- scndry_vect_out => open
- );
-
-sync_tx_fsm_reset_done_int_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => tx_fsm_reset_done_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => TXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => tx_fsm_reset_done_int_s2 ,
- scndry_vect_out => open
- );
-
- process(TXUSERCLK)
- begin
- if rising_edge(TXUSERCLK) then
- run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
-
- tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2;
- end if;
- end process;
-
-sync_TXRESETDONE_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => TXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => TXRESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => txresetdone_s2 ,
- scndry_vect_out => open
- );
-
-sync_time_out_wait_bypass_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => TXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => time_out_wait_bypass ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => time_out_wait_bypass_s2 ,
- scndry_vect_out => open
- );
-
-sync_mmcm_lock_reclocked_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => MMCM_LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => mmcm_lock_i ,
- scndry_vect_out => open
- );
-
- process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- txresetdone_s3 <= txresetdone_s2;
-
- time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
- pll0lock_prev <= pll0lock_sync;
- pll1lock_prev <= pll1lock_sync;
- end if;
- end process;
-
-
-
-sync_PLL0LOCK_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL0LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll0lock_sync ,
- scndry_vect_out => open
- );
-
-sync_PLL1LOCK_cdc_sync : east_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL1LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll1lock_sync ,
- scndry_vect_out => open
- );
-
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll0lock_ris_edge <= '0';
- elsif((pll0lock_prev = '0') and (pll0lock_sync = '1')) then
- pll0lock_ris_edge <= '1';
- elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
- pll0lock_ris_edge <= pll0lock_ris_edge;
- else
- pll0lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll1lock_ris_edge <= '0';
- elsif((pll1lock_prev = '0') and (pll1lock_sync = '1')) then
- pll1lock_ris_edge <= '1';
- elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
- pll1lock_ris_edge <= pll1lock_ris_edge;
- else
- pll1lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
-
- timeout_buffer_bypass:process(TXUSERCLK)
- begin
- if rising_edge(TXUSERCLK) then
- if run_phase_alignment_int_s3 = '0' then
- wait_bypass_count <= 0;
- time_out_wait_bypass <= '0';
- elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then
- if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
- time_out_wait_bypass <= '1';
- else
- wait_bypass_count <= wait_bypass_count + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- refclk_lost <= '1' when ((TX_PLL0_USED and PLL0REFCLKLOST = '1') or (not TX_PLL0_USED and PLL1REFCLKLOST = '1')) else '0';
-
- timeout_max:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if((tx_state = ASSERT_ALL_RESETS) or
- (tx_state = RELEASE_PLL_RESET) or
- (tx_state = RELEASE_MMCM_RESET)) then
- wait_time_cnt <= WAIT_TIME_MAX;
- elsif (wait_time_cnt > 0 ) then
- wait_time_cnt <= wait_time_cnt - 1;
- end if;
- end if;
- end process;
-
- wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
-
- --FSM for resetting the GTX/GTH/GTP in the 7-series.
- --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- --
- -- Following steps are performed:
- -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
- -- answer-record 43482
- -- 2) Assert all resets on the GT and on an MMCM potentially connected.
- -- After that wait until a reference-clock has been detected.
- -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
- -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
- -- Also signal to the RX-side which PLL has been reset.
- -- 5) Wait for the RESET_DONE-signal from the GT.
- -- 6) Signal to start the phase-alignment procedure and wait for it to
- -- finish.
- -- 7) Reset-sequence has successfully run through. Signal this to the
- -- rest of the design by asserting TX_FSM_RESET_DONE.
-
- reset_fsm:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1') then
- --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
- tx_state <= INIT;
- TXUSERRDY <= '0';
- gttxreset_i <= '0';
- MMCM_RESET <= '0';
- tx_fsm_reset_done_int <= '0';
- PLL0_RESET <= '0';
- PLL1_RESET <= '0';
- pll_reset_asserted <= '0';
- reset_time_out <= '0';
- retry_counter_int <= 0;
- run_phase_alignment_int <= '0';
- RESET_PHALIGNMENT <= '1';
- else
-
- case tx_state is
- when INIT =>
- --Initial state after configuration. This state will be left after
- --approx. 500 ns and not be re-entered.
- if init_wait_done = '1' then
- tx_state <= ASSERT_ALL_RESETS;
- reset_time_out <= '1';
- end if;
-
- when ASSERT_ALL_RESETS =>
- --This is the state into which the FSM will always jump back if any
- --time-outs will occur.
- --The number of retries is reported on the output RETRY_COUNTER. In
- --case the transceiver never comes up for some reason, this machine
- --will still continue its best and rerun until the FPGA is turned off
- --or the transceivers come up correctly.
- if TX_PLL0_USED then
- if pll_reset_asserted = '0' then
- PLL0_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL0_RESET <= '0';
- end if;
- else
- if pll_reset_asserted = '0' then
- PLL1_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL1_RESET <= '0';
- end if;
- end if;
- TXUSERRDY <= '0';
- gttxreset_i <= '1';
- MMCM_RESET <= '1';
- reset_time_out <= '0';
- run_phase_alignment_int <= '0';
- RESET_PHALIGNMENT <= '1';
-
- if (TX_PLL0_USED and (pll0lock_sync = '0') and pll_reset_asserted = '1') or
- (not TX_PLL0_USED and (pll1lock_sync = '0') and pll_reset_asserted = '1') then
- tx_state <= WAIT_FOR_PLL_LOCK;
- end if;
-
- when WAIT_FOR_PLL_LOCK =>
- if(wait_time_done = '1') then
- tx_state <= RELEASE_PLL_RESET;
- end if;
-
- when RELEASE_PLL_RESET =>
- --PLL-Reset of the GTX gets released and the time-out counter
- --starts running.
- pll_reset_asserted <= '0';
-
- if (TX_PLL0_USED and (pll0lock_sync = '1')) or
- (not TX_PLL0_USED and (pll1lock_sync = '1')) then
- tx_state <= WAIT_FOR_TXOUTCLK;
- reset_time_out <= '1';
- end if;
-
- if time_out_2ms = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when WAIT_FOR_TXOUTCLK =>
- gttxreset_i <= '0';
- if(wait_time_done = '1') then
- tx_state <= RELEASE_MMCM_RESET;
- end if;
-
- when RELEASE_MMCM_RESET =>
- --Release of the MMCM-reset. Waiting for the MMCM to lock.
- MMCM_RESET <= '0';
- reset_time_out <= '0';
- if mmcm_lock_reclocked = '1' then
- tx_state <= WAIT_FOR_TXUSRCLK;
- reset_time_out <= '1';
- end if;
-
- if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when WAIT_FOR_TXUSRCLK =>
- if(wait_time_done = '1') then
- tx_state <= WAIT_RESET_DONE;
- end if;
-
- when WAIT_RESET_DONE =>
- TXUSERRDY <= '1';
- reset_time_out <= '0';
- if txresetdone_s3 = '1' then
- tx_state <= DO_PHASE_ALIGNMENT;
- reset_time_out <= '1';
- end if;
-
- if (time_out_500us = '1' and reset_time_out = '0') then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when DO_PHASE_ALIGNMENT =>
- --The direct handling of the signals for the Phase Alignment is done outside
- --this state-machine.
- RESET_PHALIGNMENT <= '0';
- run_phase_alignment_int <= '1';
- reset_time_out <= '0';
-
- if PHALIGNMENT_DONE = '1' then
- tx_state <= RESET_FSM_DONE;
- end if;
-
- if time_out_wait_bypass_s3 = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when RESET_FSM_DONE =>
- reset_time_out <= '1';
- tx_fsm_reset_done_int <= '1';
-
- when OTHERS =>
- tx_state <= INIT;
-
- end case;
- end if;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_aurora_lane_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_aurora_lane_4byte.vhd
deleted file mode 100644
index 32cbcc2e92347ccb2782aca9168daa54e66c1d73..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_aurora_lane_4byte.vhd
+++ /dev/null
@@ -1,786 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------/
---
--- AURORA_LANE_4BYTE
---
---
--- Description: the AURORA_LANE_4BYTE module provides a full duplex 4-byte
--- aurora lane connection using a single GTX. The module handles
--- lane initialization, symbol generation and decoding and error
--- detection. It also decodes some of the channel bonding
--- indicator signals needed by the Global logic.
---
--- * Supports Virtex-5
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_AURORA_LANE_4BYTE is
- generic (
- EXAMPLE_SIMULATION : integer := 0
- );
- port (
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- 4-byte data bus from the GTX.
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- Invalid 10-bit code was recieved.
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- Disparity error detected on RX interface.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Indicates which bytes of RX_DATA are control.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Comma received on given byte.
- RX_STATUS : in std_logic_vector(5 downto 0); -- Part of GT_11 status and error bus
- RX_BUF_ERR : in std_logic; -- Overflow/Underflow of RX buffer detected.
- TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
- RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
- RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
- RX_RESET : out std_logic; -- Reset RX side of GTX logic.
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- TX_DATA byte is a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- 4-byte data bus to the GTX.
- TX_RESET : out std_logic; -- Reset TX side of GTX logic.
- LINK_RESET_OUT : out std_logic; -- Link reset for hotplug scenerio.
- HPCNT_RESET : in std_logic; -- Hotplug count reset input.
- INIT_CLK : in std_logic;
-
- -- Comma Detect Phase Align Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
-
- -- TX_LL Interface
-
- GEN_SCP : in std_logic_vector(0 to 1); -- SCP generation request from TX_LL.
- GEN_ECP : in std_logic_vector(0 to 1); -- ECP generation request from TX_LL.
- GEN_SUF : in std_logic_vector(0 to 1); -- SUF generation request from TX_LL
- GEN_PAD : in std_logic_vector(0 to 1); -- PAD generation request from TX_LL
- FC_NB : in std_logic_vector(0 to 7); -- Size code for SUF and SNF messages
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data from TX_LL to send over lane.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Indicates TX_PE_DATA is Valid.
- GEN_CC : in std_logic; -- CC generation request from TX_LL.
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- Indicates lane received PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- RX data from lane to RX_LL.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- RX_PE_DATA is data, not control symbol.
- RX_SCP : out std_logic_vector(0 to 1); -- Indicates lane received SCP.
- RX_ECP : out std_logic_vector(0 to 1); -- Indicates lane received ECP
- RX_SUF : out std_logic_vector(0 to 1); -- Indicates lane received SUF
- RX_FC_NB : out std_logic_vector(0 to 7); -- Size code for SNF or SUF
-
- -- Global Logic Interface
-
- GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
- GEN_K : in std_logic_vector(0 to 3); -- 'K character' generation request from Global Logic.
- GEN_R : in std_logic_vector(0 to 3); -- 'R character' generation request from Global Logic.
- GEN_V : in std_logic_vector(0 to 3); -- Verification data generation request.
- LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
- SOFT_ERR : out std_logic_vector(0 to 1); -- Soft error detected.
- HARD_ERR : out std_logic; -- Hard error detected.
- CHANNEL_BOND_LOAD : out std_logic; -- Channel Bongding done code recieved.
- GOT_A : out std_logic_vector(0 to 3); -- Indicates lane recieved 'A character' bytes.
- GOT_V : out std_logic; -- Verification symbols received.
- CHANNEL_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET_SYMGEN : in std_logic; -- Reset the SYM_GEN module.
- RESET : in std_logic -- Reset the lane.
-
- );
-
-end east_channel_AURORA_LANE_4BYTE;
-
-architecture RTL of east_channel_AURORA_LANE_4BYTE is
-
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- Wire Declarations --
-
- signal rx_cc_i : std_logic;
- signal ena_comma_align_i : std_logic;
- signal gen_sp_i : std_logic;
- signal gen_spa_i : std_logic;
- signal rx_sp_i : std_logic;
- signal rx_spa_i : std_logic;
- signal rx_neg_i : std_logic;
- signal enable_err_detect_i : std_logic;
- signal do_word_align_i : std_logic;
- signal hard_err_reset_i : std_logic;
-
- signal tx_char_is_k_i : std_logic_vector(3 downto 0);
- signal tx_data_i : std_logic_vector(31 downto 0);
- signal rx_data_i : std_logic_vector(31 downto 0);
- signal rx_char_is_k_i : std_logic_vector(3 downto 0);
- signal rx_char_is_comma_i : std_logic_vector(3 downto 0);
- signal rx_disp_err_i : std_logic_vector(3 downto 0);
- signal rx_not_in_table_i : std_logic_vector(3 downto 0);
- signal LANE_UP_Buffer : std_logic;
-
- -- Scrambler signals
- signal gen_v_r : std_logic;
- signal gen_v_r2 : std_logic;
- signal scrambler_reset_i : std_logic;
- signal TX_DATA_Buffer : std_logic_vector(31 downto 0);
- signal TX_CHAR_IS_K_Buffer : std_logic_vector(3 downto 0);
-
- -- Descrambler signals
- signal descrambler_reset_i : std_logic;
- signal rx_pad_descram_in : std_logic_vector(0 to 1);
- signal rx_pe_data_descram_in : std_logic_vector(0 to 31);
- signal rx_pe_data_v_descram_in : std_logic_vector(0 to 1);
- signal rx_scp_descram_in : std_logic_vector(0 to 1);
- signal rx_ecp_descram_in : std_logic_vector(0 to 1);
- signal rx_suf_descram_in : std_logic_vector(0 to 1);
- signal rx_fc_nb_descram_in : std_logic_vector(0 to 7);
- signal rx_sp_descram_in : std_logic;
- signal rx_spa_descram_in : std_logic;
- signal rx_neg_descram_in : std_logic;
- signal got_a_descram_in : std_logic_vector(0 to 3);
- signal got_v_descram_in : std_logic;
-
-
--- Component Declarations --
-
- component east_channel_LANE_INIT_SM_4BYTE
-
- port (
-
- -- GTX Interface
-
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- GTX received invalid 10b code
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- GTX received 10b code w/ wrong disparity
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- GTX received a Comma
- RX_REALIGN : in std_logic; -- GTX had to change alignment due to new comma
- RX_RESET : out std_logic; -- Reset the RX side of the GTX
- TX_RESET : out std_logic; -- Reset the TX side of the GTX
- RX_POLARITY : out std_logic; -- Sets polarity used to interpet rx'ed symbols
-
- -- Comma Detect Phase Alignment Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Turn on SERDES Alignment in GTX
-
- -- Symbol Generator Interface
-
- GEN_SP : out std_logic; -- Generate SP symbol
- GEN_SPA : out std_logic; -- Generate SPA symbol
-
- -- Symbol Decoder Interface
-
- RX_SP : in std_logic; -- Lane rx'ed SP sequence w/ + or - data
- RX_SPA : in std_logic; -- Lane rx'ed SPA sequence
- RX_NEG : in std_logic; -- Lane rx'ed inverted SP or SPA data
- DO_WORD_ALIGN : out std_logic; -- Enable word alignment
-
- -- Error Detection Logic Interface
-
- ENABLE_ERR_DETECT : out std_logic; -- Turn on Soft Error detection
- HARD_ERR_RESET : in std_logic; -- Reset lane due to hard error
-
- -- Global Logic Interface
-
- LANE_UP : out std_logic; -- Lane is initialized
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora logic
- RESET : in std_logic -- Reset Aurora Lane
-
- );
-
- end component;
-
-
- component east_channel_CHBOND_COUNT_DEC_4BYTE
-
- port (
-
- RX_STATUS : in std_logic_vector(5 downto 0);
- CHANNEL_BOND_LOAD : out std_logic;
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_SYM_GEN_4BYTE
-
- port (
-
- -- TX_LL Interface -- See description for info about GEN_PAD and TX_PE_DATA_V.
-
- GEN_SCP : in std_logic_vector(0 to 1); -- Generate SCP.
- GEN_ECP : in std_logic_vector(0 to 1); -- Generate ECP.
- GEN_SUF : in std_logic_vector(0 to 1); -- Generate SUF using code given by FC_NB.
- GEN_PAD : in std_logic_vector(0 to 1); -- Replace LSB with Pad character.
- FC_NB : in std_logic_vector(0 to 7); -- Size code for Flow Control messages.
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data. Transmitted when TX_PE_DATA_V is asserted.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Transmit data.
- GEN_CC : in std_logic; -- Generate Clock Correction symbols.
-
- -- Global Logic Interface -- See description for info about GEN_K,GEN_R and GEN_A.
-
- GEN_A : in std_logic; -- Generate A character for MSBYTE
- GEN_K : in std_logic_vector(0 to 3); -- Generate K character for selected bytes.
- GEN_R : in std_logic_vector(0 to 3); -- Generate R character for selected bytes.
- GEN_V : in std_logic_vector(0 to 3); -- Generate Ver data character on selected bytes.
-
- -- Lane Init SM Interface
-
- GEN_SP : in std_logic; -- Generate SP pattern.
- GEN_SPA : in std_logic; -- Generate SPA pattern.
-
- -- GTX Interface
-
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- Transmit TX_DATA as a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- Data to GTX for transmission to channel partner.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora Logic.
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_SYM_DEC_4BYTE
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed.
- LANE_UP : in std_logic; -- Lane is up
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- Raw RX data from GTX.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Bits indicating which bytes are control characters.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Rx'ed a comma.
- RX_CC : out std_logic; -- CC pattern.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_ERR_DETECT_4BYTE is
-
- port (
-
- -- Lane Init SM Interface
-
- ENABLE_ERR_DETECT : in std_logic;
- HARD_ERR_RESET : out std_logic;
-
- -- Global Logic Interface
-
- SOFT_ERR : out std_logic_vector(0 to 1);
- HARD_ERR : out std_logic;
-
- -- GTX Interface
-
- RX_DISP_ERR : in std_logic_vector(3 downto 0);
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0);
- RX_BUF_ERR : in std_logic;
- TX_BUF_ERR : in std_logic;
- RX_REALIGN : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-component east_channel_HOTPLUG
-generic
-(
- ENABLE_HOTPLUG : integer := 1;
- EXAMPLE_SIMULATION : integer := 0
-);
-port
-(
-
- ---------------------- Sym Dec Interface -------------------------------
- RX_CC : in std_logic;
- RX_SP : in std_logic;
- RX_SPA : in std_logic;
-
- ---------------------- GT Wrapper Interface ----------------------------
- LINK_RESET_OUT : out std_logic;
- HPCNT_RESET : in std_logic;
-
- ---------------------- System Interface ----------------------------
- INIT_CLK : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
-
-);
-end component;
-
-
- component east_channel_SCRAMBLER_TOP
-
- port (
-
- DATA_OUT : OUT std_logic_vector(31 downto 0);
- CHAR_IS_K_OUT : OUT std_logic_vector(3 downto 0);
-
- DATA : IN std_logic_vector(31 downto 0);
- CHAR_IS_K : IN std_logic_vector(3 downto 0);
- CLEAR : IN std_logic;
- RESET : IN std_logic;
- USER_CLK : IN std_logic
-
- );
-
- end component;
-
- component east_channel_DESCRAMBLER_TOP
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- RX_PAD_IN : in std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA_IN : in std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V_IN : in std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP_IN : in std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP_IN : in std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF_IN : in std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB_IN : in std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- RX_SP_IN : in std_logic; -- SP sequence received with positive or negative data.
- RX_SPA_IN : in std_logic; -- SPA sequence received.
- RX_NEG_IN : in std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- RX_CC : out std_logic; -- CC sequence received.
-
- GOT_A_IN : in std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V_IN : in std_logic; -- V sequence received.
-
- RX_CC_IN : in std_logic; -- CC sequence received.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- CLEAR : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
-begin
-
-
- -- Buffers for twisting data from GTX --
- -- To reuse the Pro Aurora logic, we twist the data to make it compatible.
- TX_CHAR_IS_K <= TX_CHAR_IS_K_Buffer(0) & TX_CHAR_IS_K_Buffer(1) & TX_CHAR_IS_K_Buffer(2) & TX_CHAR_IS_K_Buffer(3);
- TX_DATA <= TX_DATA_Buffer(7 downto 0) & TX_DATA_Buffer(15 downto 8) & TX_DATA_Buffer(23 downto 16) & TX_DATA_Buffer(31 downto 24);
- rx_data_i <= RX_DATA(7 downto 0) & RX_DATA(15 downto 8) & RX_DATA(23 downto 16) & RX_DATA(31 downto 24);
- rx_char_is_k_i <= RX_CHAR_IS_K(0) & RX_CHAR_IS_K(1) & RX_CHAR_IS_K(2) & RX_CHAR_IS_K(3);
- rx_char_is_comma_i <= RX_CHAR_IS_COMMA(0) & RX_CHAR_IS_COMMA(1) & RX_CHAR_IS_COMMA(2) & RX_CHAR_IS_COMMA(3);
- rx_disp_err_i <= RX_DISP_ERR(0) & RX_DISP_ERR(1) & RX_DISP_ERR(2) & RX_DISP_ERR(3);
- rx_not_in_table_i <= RX_NOT_IN_TABLE(0) & RX_NOT_IN_TABLE(1) & RX_NOT_IN_TABLE(2) & RX_NOT_IN_TABLE(3);
-
- LANE_UP <= LANE_UP_Buffer;
-
--- Main Body of Code --
-
- -- Lane Initialization state machine
-
- east_channel_lane_init_sm_4byte_i : east_channel_LANE_INIT_SM_4BYTE
-
- port map (
-
- -- GTX Interface
-
- RX_NOT_IN_TABLE => RX_NOT_IN_TABLE,
- RX_DISP_ERR => RX_DISP_ERR,
- RX_CHAR_IS_COMMA => RX_CHAR_IS_COMMA,
- RX_REALIGN => RX_REALIGN,
- RX_RESET => RX_RESET,
- TX_RESET => TX_RESET,
- RX_POLARITY => RX_POLARITY,
-
- -- Comma Detect Phase Alignment Interface
-
- ENA_COMMA_ALIGN => ENA_COMMA_ALIGN,
-
- -- Symbol Generator Interface
-
- GEN_SP => gen_sp_i,
- GEN_SPA => gen_spa_i,
-
- -- Symbol Decoder Interface
-
- RX_SP => rx_sp_i,
- RX_SPA => rx_spa_i,
- RX_NEG => rx_neg_i,
- DO_WORD_ALIGN => do_word_align_i,
-
- -- Error Detection Logic Interface
-
- HARD_ERR_RESET => hard_err_reset_i,
- ENABLE_ERR_DETECT => enable_err_detect_i,
-
- -- Global Logic Interface
-
- LANE_UP => LANE_UP_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
- -- Channel Bonding Count Decode module
-
- east_channel_chbond_count_dec_4byte_i : east_channel_CHBOND_COUNT_DEC_4BYTE
-
- port map (
-
- RX_STATUS => RX_STATUS,
- CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
- USER_CLK => USER_CLK
-
- );
-
-
- -- Symbol Generation module
-
- east_channel_sym_gen_4byte_i : east_channel_SYM_GEN_4BYTE
-
- port map (
-
- -- TX_LL Interface
-
- GEN_SCP => GEN_SCP,
- GEN_ECP => GEN_ECP,
- GEN_SUF => GEN_SUF,
- GEN_PAD => GEN_PAD,
- FC_NB => FC_NB,
- TX_PE_DATA => TX_PE_DATA,
- TX_PE_DATA_V => TX_PE_DATA_V,
- GEN_CC => GEN_CC,
-
- -- Global Logic Interface
-
- GEN_A => GEN_A,
- GEN_K => GEN_K,
- GEN_R => GEN_R,
- GEN_V => GEN_V,
-
- -- Lane Init SM Interface
-
- GEN_SP => gen_sp_i,
- GEN_SPA => gen_spa_i,
-
- -- GT Interface
-
- TX_CHAR_IS_K => tx_char_is_k_i,
- TX_DATA => tx_data_i,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET_SYMGEN
-
- );
-
-
- -- Symbol Decode module
-
- east_channel_sym_dec_4byte_i : east_channel_SYM_DEC_4BYTE
-
- port map (
-
- -- RX_LL Interface
-
- RX_PAD => rx_pad_descram_in,
- RX_PE_DATA => rx_pe_data_descram_in,
- RX_PE_DATA_V => rx_pe_data_v_descram_in,
- RX_SCP => rx_scp_descram_in,
- RX_ECP => rx_ecp_descram_in,
- RX_SUF => rx_suf_descram_in,
- RX_FC_NB => rx_fc_nb_descram_in,
-
- -- Lane Init SM Interface
-
- DO_WORD_ALIGN => do_word_align_i,
- LANE_UP => LANE_UP_Buffer,
- RX_SP => rx_sp_descram_in,
- RX_SPA => rx_spa_descram_in,
- RX_NEG => rx_neg_descram_in,
-
- -- Global Logic Interface
-
- GOT_A => got_a_descram_in,
- GOT_V => got_v_descram_in,
-
- -- GT Interface
-
- RX_DATA => rx_data_i,
- RX_CHAR_IS_K => rx_char_is_k_i,
- RX_CHAR_IS_COMMA => rx_char_is_comma_i,
- RX_CC => rx_cc_i,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
- -- Error Detection module
-
- east_channel_err_detect_4byte_i : east_channel_ERR_DETECT_4BYTE
-
- port map (
-
- -- Lane Init SM Interface
-
- ENABLE_ERR_DETECT => enable_err_detect_i,
- HARD_ERR_RESET => hard_err_reset_i,
-
- -- Global Logic Interface
-
- SOFT_ERR => SOFT_ERR,
- HARD_ERR => HARD_ERR,
-
- -- GTX Interface
-
- RX_DISP_ERR => rx_disp_err_i,
- RX_NOT_IN_TABLE => rx_not_in_table_i,
- RX_BUF_ERR => RX_BUF_ERR,
- TX_BUF_ERR => TX_BUF_ERR,
- RX_REALIGN => RX_REALIGN,
-
- -- System Interface
-
- USER_CLK => USER_CLK
-
- );
-
- -- Hot Plug module
- east_channel_hotplug_i : east_channel_HOTPLUG
- generic map
- (
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION
- )
- port map
- (
- -- Sym Dec Interface
- RX_CC => rx_cc_i,
- RX_SP => rx_sp_i,
- RX_SPA => rx_spa_i,
-
- -- GT Wrapper Interface
- LINK_RESET_OUT => LINK_RESET_OUT,
- HPCNT_RESET => HPCNT_RESET,
-
- -- System Interface
- INIT_CLK => INIT_CLK,
- USER_CLK => USER_CLK,
- RESET => RESET
- );
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- gen_v_r <= OR_REDUCE(GEN_V) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- gen_v_r2 <= gen_v_r after DLY;
-
- end if;
-
- end process;
-
- scrambler_reset_i <= gen_v_r2 or (not CHANNEL_UP) or RESET;
-
- -- Scrambler
- east_channel_scrambler_top_i : east_channel_SCRAMBLER_TOP
-
- port map
- (
- DATA_OUT => TX_DATA_Buffer,
- CHAR_IS_K_OUT => TX_CHAR_IS_K_Buffer,
-
- DATA => tx_data_i,
- CHAR_IS_K => tx_char_is_k_i,
- CLEAR => GEN_CC,
- RESET => scrambler_reset_i, -- Applied during initialization; not expected after scrambler started operation
- USER_CLK => USER_CLK
- );
-
- descrambler_reset_i <= (not CHANNEL_UP) or RESET;
-
- -- Descrambler
- east_channel_descrambler_top_i : east_channel_DESCRAMBLER_TOP
-
- port map
- (
- -- RX_LL Interface
-
-
- RX_PAD => RX_PAD,
- RX_PE_DATA => RX_PE_DATA,
- RX_PE_DATA_V => RX_PE_DATA_V,
- RX_SCP => RX_SCP,
- RX_ECP => RX_ECP,
- RX_SUF => RX_SUF,
- RX_FC_NB => RX_FC_NB,
-
- RX_PAD_IN => rx_pad_descram_in,
- RX_PE_DATA_IN => rx_pe_data_descram_in,
- RX_PE_DATA_V_IN => rx_pe_data_v_descram_in,
- RX_SCP_IN => rx_scp_descram_in,
- RX_ECP_IN => rx_ecp_descram_in,
- RX_SUF_IN => rx_suf_descram_in,
- RX_FC_NB_IN => rx_fc_nb_descram_in,
-
- -- Lane Init SM Interface
-
- RX_SP => rx_sp_i,
- RX_SPA => rx_spa_i,
- RX_NEG => rx_neg_i,
-
- RX_SP_IN => rx_sp_descram_in,
- RX_SPA_IN => rx_spa_descram_in,
- RX_NEG_IN => rx_neg_descram_in,
-
- -- Global Logic Interface
-
- GOT_A_IN => got_a_descram_in,
- GOT_V_IN => got_v_descram_in,
-
- RX_CC_IN => rx_cc_i,
-
- GOT_A => GOT_A,
- GOT_V => GOT_V,
-
- RX_CC => OPEN,
- CLEAR => '0',
- RESET => descrambler_reset_i, -- Applied during initialization; not expected after descrambler started operation
- USER_CLK => USER_CLK
- );
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_aurora_pkg.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_aurora_pkg.vhd
deleted file mode 100644
index 3ceea680decbfd6f230abcc76b7e3d705970f0fb..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_aurora_pkg.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- AURORA
---
---
--- Description: Aurora Package Definition
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use STD.TEXTIO.all;
-
-package AURORA_PKG is
-
- function std_bool (EXP_IN : in boolean) return std_logic;
-
-end;
-
-package body AURORA_PKG is
-
- function std_bool (EXP_IN : in boolean) return std_logic is
-
- begin
-
- if (EXP_IN) then
-
- return('1');
-
- else
-
- return('0');
-
- end if;
-
- end std_bool;
-
-end;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_axi_to_ll.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_axi_to_ll.vhd
deleted file mode 100644
index 132ceeaa3a465466c047897bba1a0ad58313f29c..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_axi_to_ll.vhd
+++ /dev/null
@@ -1,165 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
---
--- AXI_TO_LL
---
---
--- Description: This light wrapper/shim convertes Legacy LocalLink interface
--- signals from AXI-4 Stream protocol signals
---
---
-------------------------------------------------------------------------------/
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_AXI_TO_LL is
-generic
-(
- DATA_WIDTH : integer := 16; -- DATA bus width
- STRB_WIDTH : integer := 2; -- STROBE bus width
- REM_WIDTH : integer := 1; -- REM bus width
- USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC
- USE_UFC_REM : integer := 0 -- UFC REM bus width identifier
-);
-
-port
-(
-
- ---------------------- AXI4-S Interface -------------------------------
-
- AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_IP_TX_TVALID : in std_logic;
- AXI4_S_IP_TX_TLAST : in std_logic;
- AXI4_S_OP_TX_TREADY : out std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1);
- LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1);
- LL_OP_SRC_RDY_N : out std_logic;
- LL_OP_SOF_N : out std_logic;
- LL_OP_EOF_N : out std_logic;
- LL_IP_DST_RDY_N : in std_logic;
-
- ---------------------- System Interface ----------------------------
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : in std_logic
-
-);
-
-end east_channel_AXI_TO_LL;
-
-architecture BEHAVIORAL of east_channel_AXI_TO_LL is
- attribute core_generation_info : string;
-attribute core_generation_info of BEHAVIORAL : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
- signal new_pkt_r : std_logic;
- signal new_pkt : std_logic;
- signal temp_cond : std_logic;
- signal ll_op_sof : std_logic;
- signal ll_ip_dst_rdy : std_logic;
- signal AXI4_S_IP_TX_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1);
-
-begin
-
---*********************************Main Body of Code**********************************
-
-
-
- ll_ip_dst_rdy <= not LL_IP_DST_RDY_N;
-
- LL_OP_DATA <= AXI4_S_IP_TX_TDATA;
-
-
- AXI4_S_IP_TX_TKEEP_i <= AXI4_S_IP_TX_TKEEP;
-
-
-
-
- LL_OP_SRC_RDY_N <= not AXI4_S_IP_TX_TVALID;
- LL_OP_EOF_N <= not AXI4_S_IP_TX_TLAST;
-
-LL_OP_REM <= ("0" & AXI4_S_IP_TX_TKEEP_i(0)) + ("0" & AXI4_S_IP_TX_TKEEP_i(1)) + ("0" & AXI4_S_IP_TX_TKEEP_i(2)) + ("0" & AXI4_S_IP_TX_TKEEP_i(3)) - '1';
-
- new_pkt <= '0' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
- '1' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND not AXI4_S_IP_TX_TLAST) = '1') else
- new_pkt_r;
-
- temp_cond <= '0' when (new_pkt_r = '1') else
- '1';
- ll_op_sof <= temp_cond when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
- (new_pkt and (not new_pkt_r));
-
- LL_OP_SOF_N <= not ll_op_sof;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- if(RESET = '1') then
- new_pkt_r <= '0' after DLY;
- elsif(CHANNEL_UP = '1') then
- new_pkt_r <= new_pkt after DLY;
- else
- new_pkt_r <= '0' after DLY;
- end if;
- end if;
- end process;
-
- -- Assign output from temp signal
- AXI4_S_OP_TX_TREADY <= ll_ip_dst_rdy;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_cdc_sync.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_cdc_sync.vhd
deleted file mode 100644
index 223b65146f2b6cc8b61c83060269933a75d14785..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_cdc_sync.vhd
+++ /dev/null
@@ -1,741 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-
---Generic Help
---C_CDC_TYPE : Defines the type of CDC needed
--- 0 means pulse synchronizer. Used to transfer one clock pulse
--- from prmry domain to scndry domain.
--- 1 means level synchronizer. Used to transfer level signal.
--- 2 means level synchronizer with ack. Used to transfer level
--- signal. Input signal should change only when prmry_ack is detected
---
---C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
--- Set to 0 when incoming signal is purely floped signal.
---
---C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
--- it might be needed.
--- 0 means reset not needed for sync flops
--- 1 means reset needed for sync flops. i
--- In this case prmry_resetn should be in prmry clock,
--- while scndry_reset should be in scndry clock.
---
---C_SINGLE_BIT : CDC should normally be done for single bit signals only.
--- However, based on design buses can also be CDC'ed.
--- 0 means it is a bus. In this case input be connected to prmry_vect_in.
--- Output is on scndry_vect_out.
--- 1 means it is a single bit. In this case input be connected to prmry_in.
--- Output is on scndry_out.
---
---C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
---
---C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
--- Value of 0, 1 is allowed only for level CDC.
--- Min value for Pulse CDC is 2
---
---Whenever this file is used following XDC constraint has to be added
-
--- set_false_path -to [get_pins -hier *east_channel_cdc_to*/D]
-
-
---IO Ports
---
--- prmry_aclk : clock of originating domain (source domain)
--- prmry_resetn : sync reset of originating clock domain (source domain)
--- prmry_in : input signal bit. This should be a pure flop output without
--- any combi logic. This is source.
--- prmry_vect_in : bus signal. From Source domain.
--- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
--- Used only when C_CDC_TYPE = 2
--- scndry_aclk : destination clock.
--- scndry_resetn : sync reset of destination domain
--- scndry_out : sync'ed output in destination domain. Single bit.
--- scndry_vect_out : sync'ed output in destination domain. bus.
-
-
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_misc.all;
-
-
-
-entity east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
-end east_channel_cdc_sync;
-
--------------------------------------------------------------------------------
--- Architecture
--------------------------------------------------------------------------------
-architecture implementation of east_channel_cdc_sync is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-
--------------------------------------------------------------------------------
--- Functions
--------------------------------------------------------------------------------
-
--- No Functions Declared
-
--------------------------------------------------------------------------------
--- Constants Declarations
--------------------------------------------------------------------------------
-
--- No Constants Declared
-
--------------------------------------------------------------------------------
--- Begin architecture logic
--------------------------------------------------------------------------------
-begin
--- Generate PULSE clock domain crossing
-GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-
--- Primary to Secondary
-signal s_out_d1_east_channel_cdc_to : std_logic := '0';
-signal s_out_d2 : std_logic := '0';
-signal s_out_d3 : std_logic := '0';
-signal s_out_d4 : std_logic := '0';
-signal s_out_d5 : std_logic := '0';
-signal s_out_d6 : std_logic := '0';
-signal s_out_d7 : std_logic := '0';
-signal s_out_re : std_logic := '0';
-signal prmry_in_xored : std_logic := '0';
-signal p_in_d1_cdc_from : std_logic := '0';
-
-
-
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_out_d1_east_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d6 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d7 : SIGNAL IS "true";
-
- ATTRIBUTE shift_extract : STRING;
- ATTRIBUTE shift_extract OF s_out_d1_east_channel_cdc_to : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d2 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d3 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d4 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d5 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d6 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d7 : SIGNAL IS "no";
-
-begin
-
- --*****************************************************************************
- --** Asynchronous Pulse Clock Crossing **
- --** PRIMARY TO SECONDARY OPEN-ENDED **
- --*****************************************************************************
-
-prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
-
- REG_P_IN : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_in_d1_cdc_from <= '0';
- else
- p_in_d1_cdc_from <= prmry_in_xored;
- end if;
- end if;
- end process REG_P_IN;
-
-
- P_IN_CROSS2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_out_d1_east_channel_cdc_to <= '0';
- s_out_d2 <= '0';
- s_out_d3 <= '0';
- s_out_d4 <= '0';
- s_out_d5 <= '0';
- s_out_d6 <= '0';
- s_out_d7 <= '0';
- scndry_out <= '0';
- else
- s_out_d1_east_channel_cdc_to <= p_in_d1_cdc_from;
- s_out_d2 <= s_out_d1_east_channel_cdc_to;
- s_out_d3 <= s_out_d2;
- s_out_d4 <= s_out_d3;
- s_out_d5 <= s_out_d4;
- s_out_d6 <= s_out_d5;
- s_out_d7 <= s_out_d6;
- scndry_out <= s_out_re;
- end if;
- end if;
- end process P_IN_CROSS2SCNDRY;
-
-MTBF_2 : if C_MTBF_STAGES = 2 generate
-begin
- s_out_re <= s_out_d2 xor s_out_d3;
-
-end generate MTBF_2;
-
-MTBF_3 : if C_MTBF_STAGES = 3 generate
-begin
- s_out_re <= s_out_d3 xor s_out_d4;
-
-end generate MTBF_3;
-
-MTBF_4 : if C_MTBF_STAGES = 4 generate
-begin
- s_out_re <= s_out_d4 xor s_out_d5;
-
-end generate MTBF_4;
-
-MTBF_5 : if C_MTBF_STAGES = 5 generate
-begin
- s_out_re <= s_out_d5 xor s_out_d6;
-
-end generate MTBF_5;
-
-MTBF_6 : if C_MTBF_STAGES = 6 generate
-begin
- s_out_re <= s_out_d6 xor s_out_d7;
-
-end generate MTBF_6;
-
- -- Feed secondary pulse out
-
-end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-
-
--- Generate LEVEL clock domain crossing with reset state = 0
-GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
-begin
--- Primary to Secondary
-
-SINGLE_BIT : if C_SINGLE_BIT = 1 generate
-
-signal p_level_in_d1_cdc_from : std_logic := '0';
-signal p_level_in_int : std_logic := '0';
-signal s_level_out_d1_east_channel_cdc_to : std_logic := '0';
-signal s_level_out_d2 : std_logic := '0';
-signal s_level_out_d3 : std_logic := '0';
-signal s_level_out_d4 : std_logic := '0';
-signal s_level_out_d5 : std_logic := '0';
-signal s_level_out_d6 : std_logic := '0';
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_level_out_d1_east_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
-
- ATTRIBUTE shift_extract : STRING;
- ATTRIBUTE shift_extract OF s_level_out_d1_east_channel_cdc_to : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d2 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d3 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d4 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d5 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d6 : SIGNAL IS "no";
-
- ATTRIBUTE keep : STRING;
- ATTRIBUTE keep OF p_level_in_d1_cdc_from : SIGNAL IS "true";
-begin
-
- --*****************************************************************************
- --** Asynchronous Level Clock Crossing **
- --** PRIMARY TO SECONDARY **
- --*****************************************************************************
- -- register is scndry to provide clean ff output to clock crossing logic
-
-INPUT_FLOP : if C_FLOP_INPUT = 1 generate
-begin
-
- REG_PLEVEL_IN : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_level_in_d1_cdc_from <= '0';
- else
- p_level_in_d1_cdc_from <= prmry_in;
- end if;
- end if;
- end process REG_PLEVEL_IN;
-
- p_level_in_int <= p_level_in_d1_cdc_from;
-
-end generate INPUT_FLOP;
-
-
-NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
-begin
-
- p_level_in_int <= prmry_in;
-
-end generate NO_INPUT_FLOP;
-
- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_level_out_d1_east_channel_cdc_to <= '0';
- s_level_out_d2 <= '0';
- s_level_out_d3 <= '0';
- s_level_out_d4 <= '0';
- s_level_out_d5 <= '0';
- s_level_out_d6 <= '0';
- else
- s_level_out_d1_east_channel_cdc_to <= p_level_in_int;
- s_level_out_d2 <= s_level_out_d1_east_channel_cdc_to;
- s_level_out_d3 <= s_level_out_d2;
- s_level_out_d4 <= s_level_out_d3;
- s_level_out_d5 <= s_level_out_d4;
- s_level_out_d6 <= s_level_out_d5;
- end if;
- end if;
- end process CROSS_PLEVEL_IN2SCNDRY;
-
-
-
-
-MTBF_L1 : if C_MTBF_STAGES = 1 generate
-begin
- scndry_out <= s_level_out_d1_east_channel_cdc_to;
-
-
-end generate MTBF_L1;
-
-MTBF_L2 : if C_MTBF_STAGES = 2 generate
-begin
-
- scndry_out <= s_level_out_d2;
-
-
-end generate MTBF_L2;
-
-MTBF_L3 : if C_MTBF_STAGES = 3 generate
-begin
-
- scndry_out <= s_level_out_d3;
-
-
-
-end generate MTBF_L3;
-
-MTBF_L4 : if C_MTBF_STAGES = 4 generate
-begin
- scndry_out <= s_level_out_d4;
-
-
-
-end generate MTBF_L4;
-
-MTBF_L5 : if C_MTBF_STAGES = 5 generate
-begin
-
- scndry_out <= s_level_out_d5;
-
-
-end generate MTBF_L5;
-
-MTBF_L6 : if C_MTBF_STAGES = 6 generate
-begin
-
- scndry_out <= s_level_out_d6;
-
-
-end generate MTBF_L6;
-
-end generate SINGLE_BIT;
-
-
-
-MULTI_BIT : if C_SINGLE_BIT = 0 generate
-
-signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d1_east_channel_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_level_out_bus_d1_east_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
-
- ATTRIBUTE shift_extract : STRING;
- ATTRIBUTE shift_extract OF s_level_out_bus_d1_east_channel_cdc_to : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d2 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d3 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d4 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d5 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d6 : SIGNAL IS "no";
-
-begin
-
- --*****************************************************************************
- --** Asynchronous Level Clock Crossing **
- --** PRIMARY TO SECONDARY **
- --*****************************************************************************
- -- register is scndry to provide clean ff output to clock crossing logic
--- REG_PLEVEL_IN : process(prmry_aclk)
--- begin
--- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
--- p_level_in_bus_d1_cdc_from <= (others => '0');
--- else
--- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
--- end if;
--- end if;
--- end process REG_PLEVEL_IN;
-
- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_level_out_bus_d1_east_channel_cdc_to <= (others => '0');
- s_level_out_bus_d2 <= (others => '0');
- s_level_out_bus_d3 <= (others => '0');
- s_level_out_bus_d4 <= (others => '0');
- s_level_out_bus_d5 <= (others => '0');
- s_level_out_bus_d6 <= (others => '0');
- else
- s_level_out_bus_d1_east_channel_cdc_to <= prmry_vect_in;
- s_level_out_bus_d2 <= s_level_out_bus_d1_east_channel_cdc_to;
- s_level_out_bus_d3 <= s_level_out_bus_d2;
- s_level_out_bus_d4 <= s_level_out_bus_d3;
- s_level_out_bus_d5 <= s_level_out_bus_d4;
- s_level_out_bus_d6 <= s_level_out_bus_d5;
- end if;
- end if;
- end process CROSS_PLEVEL_IN2SCNDRY;
-
-
-
-MTBF_L1 : if C_MTBF_STAGES = 1 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d1_east_channel_cdc_to;
-
-
-end generate MTBF_L1;
-
-MTBF_L2 : if C_MTBF_STAGES = 2 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d2;
-
-
-end generate MTBF_L2;
-
-MTBF_L3 : if C_MTBF_STAGES = 3 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d3;
-
-
-
-end generate MTBF_L3;
-
-MTBF_L4 : if C_MTBF_STAGES = 4 generate
-begin
- scndry_vect_out <= s_level_out_bus_d4;
-
-
-
-end generate MTBF_L4;
-
-MTBF_L5 : if C_MTBF_STAGES = 5 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d5;
-
-
-end generate MTBF_L5;
-
-MTBF_L6 : if C_MTBF_STAGES = 6 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d6;
-
-
-end generate MTBF_L6;
-
-end generate MULTI_BIT;
-
-
-end generate GENERATE_LEVEL_P_S_CDC;
-
-
-GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
--- Primary to Secondary
-
-
-signal p_level_in_d1_cdc_from : std_logic := '0';
-signal p_level_in_int : std_logic := '0';
-signal s_level_out_d1_east_channel_cdc_to : std_logic := '0';
-signal s_level_out_d2 : std_logic := '0';
-signal s_level_out_d3 : std_logic := '0';
-signal s_level_out_d4 : std_logic := '0';
-signal s_level_out_d5 : std_logic := '0';
-signal s_level_out_d6 : std_logic := '0';
-signal p_level_out_d1_east_channel_cdc_to : std_logic := '0';
-signal p_level_out_d2 : std_logic := '0';
-signal p_level_out_d3 : std_logic := '0';
-signal p_level_out_d4 : std_logic := '0';
-signal p_level_out_d5 : std_logic := '0';
-signal p_level_out_d6 : std_logic := '0';
-signal p_level_out_d7 : std_logic := '0';
-signal scndry_out_int : std_logic := '0';
-signal prmry_pulse_ack : std_logic := '0';
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_level_out_d1_east_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
-
- ATTRIBUTE async_reg OF p_level_out_d1_east_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d6 : SIGNAL IS "true";
-
-begin
-
- --*****************************************************************************
- --** Asynchronous Level Clock Crossing **
- --** PRIMARY TO SECONDARY **
- --*****************************************************************************
- -- register is scndry to provide clean ff output to clock crossing logic
-INPUT_FLOP : if C_FLOP_INPUT = 1 generate
-begin
-
- REG_PLEVEL_IN : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_level_in_d1_cdc_from <= '0';
- else
- p_level_in_d1_cdc_from <= prmry_in;
- end if;
- end if;
- end process REG_PLEVEL_IN;
-
- p_level_in_int <= p_level_in_d1_cdc_from;
-
-end generate INPUT_FLOP;
-
-
-NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
-begin
-
- p_level_in_int <= prmry_in;
-
-end generate NO_INPUT_FLOP;
-
- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_level_out_d1_east_channel_cdc_to <= '0';
- s_level_out_d2 <= '0';
- s_level_out_d3 <= '0';
- s_level_out_d4 <= '0';
- s_level_out_d5 <= '0';
- s_level_out_d6 <= '0';
- else
- s_level_out_d1_east_channel_cdc_to <= p_level_in_int;
- s_level_out_d2 <= s_level_out_d1_east_channel_cdc_to;
- s_level_out_d3 <= s_level_out_d2;
- s_level_out_d4 <= s_level_out_d3;
- s_level_out_d5 <= s_level_out_d4;
- s_level_out_d6 <= s_level_out_d5;
- end if;
- end if;
- end process CROSS_PLEVEL_IN2SCNDRY;
-
-
- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_level_out_d1_east_channel_cdc_to <= '0';
- p_level_out_d2 <= '0';
- p_level_out_d3 <= '0';
- p_level_out_d4 <= '0';
- p_level_out_d5 <= '0';
- p_level_out_d6 <= '0';
- p_level_out_d7 <= '0';
- prmry_ack <= '0';
- else
- p_level_out_d1_east_channel_cdc_to <= scndry_out_int;
- p_level_out_d2 <= p_level_out_d1_east_channel_cdc_to;
- p_level_out_d3 <= p_level_out_d2;
- p_level_out_d4 <= p_level_out_d3;
- p_level_out_d5 <= p_level_out_d4;
- p_level_out_d6 <= p_level_out_d5;
- p_level_out_d7 <= p_level_out_d6;
- prmry_ack <= prmry_pulse_ack;
- end if;
- end if;
- end process CROSS_PLEVEL_SCNDRY2PRMRY;
-
-
-
-
-MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
-begin
-
- scndry_out_int <= s_level_out_d2;
- prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
-
-
-end generate MTBF_L2;
-
-MTBF_L3 : if C_MTBF_STAGES = 3 generate
-begin
-
- scndry_out_int <= s_level_out_d3;
- prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
-
-
-
-end generate MTBF_L3;
-
-MTBF_L4 : if C_MTBF_STAGES = 4 generate
-begin
- scndry_out_int <= s_level_out_d4;
- prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
-
-
-
-end generate MTBF_L4;
-
-MTBF_L5 : if C_MTBF_STAGES = 5 generate
-begin
-
- scndry_out_int <= s_level_out_d5;
- prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
-
-
-end generate MTBF_L5;
-
-MTBF_L6 : if C_MTBF_STAGES = 6 generate
-begin
-
- scndry_out_int <= s_level_out_d6;
- prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
-
-
-end generate MTBF_L6;
-
- scndry_out <= scndry_out_int;
-
-
-end generate GENERATE_LEVEL_ACK_P_S_CDC;
-
-
-end implementation;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_channel_err_detect.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_channel_err_detect.vhd
deleted file mode 100644
index a7072f1f7bdbba57aca2e168141ced6bb0dec586..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_channel_err_detect.vhd
+++ /dev/null
@@ -1,202 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- CHANNEL_ERR_DETECT
---
---
--- Description: the CHANNEL_ERR_DETECT module monitors the error signals
--- from the Aurora Lanes in the channel. If one or more errors
--- are detected, the error is reported as a channel error. If
--- a hard error is detected, it sends a message to the channel
--- initialization state machine to reset the channel.
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity east_channel_CHANNEL_ERR_DETECT is
-
- port (
-
- -- Aurora Lane Interface
-
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-LANE_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- POWER_DOWN : in std_logic;
-
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic;
-
- -- Channel Init SM Interface
-
- RESET_CHANNEL : out std_logic
-
- );
-
-end east_channel_CHANNEL_ERR_DETECT;
-
-architecture RTL of east_channel_CHANNEL_ERR_DETECT is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal CHANNEL_SOFT_ERR_Buffer : std_logic := '1';
- signal CHANNEL_HARD_ERR_Buffer : std_logic := '1';
- signal RESET_CHANNEL_Buffer : std_logic := '1';
-
--- Internal Register Declarations --
-
-signal soft_err_r : std_logic_vector(0 to 1);
-signal hard_err_r : std_logic;
-signal lane_up_r : std_logic;
-
--- Wire Declarations --
-
- signal channel_soft_err_c : std_logic;
- signal channel_hard_err_c : std_logic;
- signal reset_channel_c : std_logic;
-
-begin
-
- CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer;
- CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;
- RESET_CHANNEL <= RESET_CHANNEL_Buffer;
-
--- Main Body of Code --
-
- -- Register all of the incoming error signals. This is neccessary for timing.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- soft_err_r <= SOFT_ERR after DLY;
- hard_err_r <= HARD_ERR after DLY;
-
- end if;
-
- end process;
-
-
- -- Assert Channel soft error if any of the soft error signals are asserted.
-
- channel_soft_err_c <= soft_err_r(0) or
- soft_err_r(1);
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- CHANNEL_SOFT_ERR_Buffer <= channel_soft_err_c after DLY;
-
- end if;
-
- end process;
-
-
- -- Assert Channel hard error if any of the hard error signals are asserted.
-
- channel_hard_err_c <= hard_err_r;
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- CHANNEL_HARD_ERR_Buffer <= channel_hard_err_c after DLY;
-
- end if;
-
- end process;
-
- -- FF stage added for timing closure
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- lane_up_r <= LANE_UP after DLY;
-
- end if;
-
- end process;
-
- -- "reset_channel_c" is asserted when any of the LANE_UP signals are low.
-
- reset_channel_c <= not lane_up_r;
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RESET_CHANNEL_Buffer <= reset_channel_c or POWER_DOWN after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_channel_init_sm.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_channel_init_sm.vhd
deleted file mode 100644
index 372f2a460078bc87680b1a2501f410abf37490c2..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_channel_init_sm.vhd
+++ /dev/null
@@ -1,557 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- CHANNEL_INIT_SM
---
---
---
--- Description: the CHANNEL_INIT_SM module is a state machine for managing channel
--- bonding and verification.
---
--- The channel init state machine is reset until the lane up signals
--- of all the lanes that constitute the channel are asserted. It then
--- requests channel bonding until the lanes have been bonded and
--- checks to make sure the bonding was successful. Channel bonding is
--- skipped if there is only one lane in the channel. If bonding is
--- unsuccessful, the lanes are reset.
---
--- After the bonding phase is complete, the state machine sends
--- verification sequences through the channel until it is clear that
--- the channel is ready to be used. If verification is successful,
--- the CHANNEL_UP signal is asserted. If it is unsuccessful, the
--- lanes are reset.
---
--- After CHANNEL_UP goes high, the state machine is quiescent, and will
--- reset only if one of the lanes goes down, a hard error is detected, or
--- a general reset is requested.
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.NUMERIC_STD.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-
-library UNISIM;
-use UNISIM.all;
-
--- synthesis translate_on
-
-entity east_channel_CHANNEL_INIT_SM is
-
- generic (
- WATCHDOG_TIMEOUT : integer := 14
- );
- port (
-
- -- GTP Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-RESET_LANES : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
-
- -- Idle and Verification Sequence Generator Interface
-
- DID_VER : in std_logic;
- GEN_VER : out std_logic;
-
- -- Channel Init State Machine Interface
-
- GTRXRESET_OUT : out std_logic;
- RESET_CHANNEL : in std_logic
-
- );
-
-end east_channel_CHANNEL_INIT_SM;
-
-architecture RTL of east_channel_CHANNEL_INIT_SM is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal EN_CHAN_SYNC_Buffer : std_logic;
-signal RESET_LANES_Buffer : std_logic;
- signal CHANNEL_UP_Buffer : std_logic;
- signal START_RX_Buffer : std_logic;
- signal GEN_VER_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal free_count_done_w : std_logic;
- signal verify_watchdog_r : std_logic_vector(0 to 15);
- signal all_lanes_v_r : std_logic;
- signal got_first_v_r : std_logic;
- signal v_count_r : std_logic_vector(0 to 15);
- signal bad_v_r : std_logic;
- signal rxver_count_r : std_logic_vector(0 to 2);
- signal txver_count_r : std_logic_vector(0 to 7);
- signal free_count_r : std_logic_vector(0 to WATCHDOG_TIMEOUT-1);
-
- -- State registers
-
- signal wait_for_lane_up_r : std_logic;
- signal verify_r : std_logic;
- signal ready_r : std_logic;
-
- -- FF for timing closure
- signal ready_r2 : std_logic;
-
-
- signal gtreset_c : std_logic;
- signal gtrxreset_nxt : std_logic;
- signal gtrxreset_extend_r : std_logic_vector(7 downto 0) := "00000000";
-
-
--- Wire Declarations --
-
- signal insert_ver_c : std_logic;
- signal verify_watchdog_done_r : std_logic;
- signal rxver_3d_done_r : std_logic;
- signal txver_8d_done_r : std_logic;
- signal reset_lanes_c : std_logic;
-
- -- Next state signals
-
- signal next_verify_c : std_logic;
- signal next_ready_c : std_logic;
-
- -- VHDL utility signals
-
- signal tied_to_vcc : std_logic;
- signal tied_to_gnd : std_logic;
-
--- Component Declarations
-
- component FD
-
- -- synthesis translate_off
-
- generic (INIT : bit := '0');
-
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic
-
- );
-
- end component;
-
-begin
-
- EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
- RESET_LANES <= RESET_LANES_Buffer;
- CHANNEL_UP <= CHANNEL_UP_Buffer;
- START_RX <= START_RX_Buffer;
- GEN_VER <= GEN_VER_Buffer;
-
- tied_to_vcc <= '1';
- tied_to_gnd <= '0';
-
--- Main Body of Code --
-
- -- Main state machine for bonding and verification --
-
- -- State registers
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or RESET_CHANNEL) = '1') then
-
- wait_for_lane_up_r <= '1' after DLY;
- verify_r <= '0' after DLY;
- ready_r <= '0' after DLY;
-
- else
-
- wait_for_lane_up_r <= '0' after DLY;
- verify_r <= next_verify_c after DLY;
- ready_r <= next_ready_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Next state logic
-
- next_verify_c <= wait_for_lane_up_r or
- (verify_r and (not rxver_3d_done_r or not txver_8d_done_r));
-
- next_ready_c <= ((verify_r and txver_8d_done_r) and rxver_3d_done_r) or
- ready_r;
-
-
- -- Output Logic
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- ready_r2 <= ready_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Channel up is high as long as the Global Logic is in the ready state.
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- CHANNEL_UP_Buffer <= ready_r2 after DLY;
-
- end if;
-
- end process;
-
-
- -- Turn the receive engine on as soon as all the lanes are up.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- START_RX_Buffer <= '0' after DLY;
-
- else
-
- START_RX_Buffer <= not wait_for_lane_up_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate the Verification sequence when in the verify state.
-
- GEN_VER_Buffer <= verify_r;
-
-
- -- Channel Reset --
-
- -- Some problems during channel bonding and verification require the lanes to
- -- be reset. When this happens, we assert the Reset Lanes signal, which gets
- -- sent to all Aurora Lanes. When the Aurora Lanes reset, their LANE_UP signals
- -- go down. This causes the Channel Error Detector to assert the Reset Channel
- -- signal.
-
- reset_lanes_c <= (verify_r and verify_watchdog_done_r) or
- (verify_r and bad_v_r and not rxver_3d_done_r) or
- (RESET_CHANNEL and not wait_for_lane_up_r) or
- RESET;
-
- reset_lanes_flop_i : FD
-
- -- synthesis translate_off
-
- generic map (INIT => '1')
-
- -- synthesis translate_on
-
- port map (
-
- D => reset_lanes_c,
- C => USER_CLK,
- Q => RESET_LANES_Buffer
-
- );
-
-
-
- gtreset_c <= (verify_r and verify_watchdog_done_r) or
- ((verify_r and bad_v_r) and not rxver_3d_done_r);
-
-
- gtreset_flop_0_i : FD
-
- -- synthesis translate_off
-
- generic map (INIT => '1')
-
- -- synthesis translate_on
-
- port map (
-
- D => gtreset_c,
- C => USER_CLK,
- Q => gtrxreset_nxt
-
- );
-
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- if (RESET = '1') then
- gtrxreset_extend_r <= (others => '0') after DLY;
- else
- gtrxreset_extend_r <= (gtrxreset_nxt & gtrxreset_extend_r(7 downto 1)) after DLY;
- end if;
- end if;
- end process;
-
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- GTRXRESET_OUT <= OR_REDUCE(gtrxreset_extend_r) after DLY;
- end if;
- end process;
-
-
- -- Watchdog timers --
-
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- if ((RESET or RESET_CHANNEL) = '1') then
- free_count_r <= (others => '1') after DLY;
- else
- free_count_r <= free_count_r - '1' after DLY;
- end if;
- end if;
- end process;
-
-
- free_count_done_w <= (std_bool(free_count_r = 0));
-
- -- We use the free running count as a CE for the verify watchdog. The
- -- count runs continuously so the watchdog will vary between a count of 4096
- -- and 3840 cycles - acceptable for this application.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((free_count_done_w or not verify_r) = '1') then
-
- verify_watchdog_r <= verify_r & verify_watchdog_r(0 to 14) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- verify_watchdog_done_r <= verify_watchdog_r(15);
-
-
- -- Channel Bonding --
-
- -- We don't use channel bonding for the single lane case, so we tie the
- -- EN_CHAN_SYNC signal low.
-
- EN_CHAN_SYNC_Buffer <= '0';
-
-
- -- Verification --
-
- -- Vs need to appear on all lanes simultaneously.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- all_lanes_v_r <= GOT_V after DLY;
-
- end if;
-
- end process;
-
-
- -- Vs need to be decoded by the aurora lane and then checked by the
- -- Global logic. They must appear periodically.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (verify_r = '0') then
-
- got_first_v_r <= '0' after DLY;
-
- else
-
- if (all_lanes_v_r = '1') then
-
- got_first_v_r <= '1' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- insert_ver_c <= (all_lanes_v_r and not got_first_v_r) or (v_count_r(15) and verify_r);
-
-
- -- Shift register for measuring the time between V counts.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- v_count_r <= insert_ver_c & v_count_r(0 to 14) after DLY;
-
- end if;
-
- end process;
-
-
- -- Assert bad_v_r if a V does not arrive when expected.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- bad_v_r <= (v_count_r(15) xor all_lanes_v_r) and got_first_v_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Count the number of Ver sequences received. You're done after you receive four.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (((v_count_r(15) and all_lanes_v_r) or not verify_r) = '1') then
-
- rxver_count_r <= verify_r & rxver_count_r(0 to 1) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- rxver_3d_done_r <= rxver_count_r(2);
-
-
- -- Count the number of Ver sequences transmitted. You're done after you send eight.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((DID_VER or not verify_r) = '1') then
-
- txver_count_r <= verify_r & txver_count_r(0 to 6) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- txver_8d_done_r <= txver_count_r(7);
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_chbond_count_dec_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_chbond_count_dec_4byte.vhd
deleted file mode 100644
index 385d8ddcaf5fc5dafcbb3e0839d3a549763c0fa7..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_chbond_count_dec_4byte.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- CHBOND_COUNT_DEC_4BYTE
---
---
---
--- Description: This module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
--- that Channel Bonding is complete
---
--- * Supports Virtex-5
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_CHBOND_COUNT_DEC_4BYTE is
-
- port (
-
- RX_STATUS : in std_logic_vector(5 downto 0);
- CHANNEL_BOND_LOAD : out std_logic;
- USER_CLK : in std_logic
-
- );
-
-end east_channel_CHBOND_COUNT_DEC_4BYTE;
-
-architecture RTL of east_channel_CHBOND_COUNT_DEC_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
- constant CHANNEL_BOND_LOAD_CODE : std_logic_vector(5 downto 0) := "100111"; -- Status bus code: Channel Bond load complete
-
--- External Register Declarations
-
- signal CHANNEL_BOND_LOAD_Buffer : std_logic;
-
-begin
-
- CHANNEL_BOND_LOAD <= CHANNEL_BOND_LOAD_Buffer;
-
--- Main Body of Code --
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK'event and USER_CLK = '1') then
-
- CHANNEL_BOND_LOAD_Buffer <= std_bool(RX_STATUS = CHANNEL_BOND_LOAD_CODE) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_descrambler_top.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_descrambler_top.vhd
deleted file mode 100644
index 02a9fbeee071b2780835c4f85f8eee1564ab08fb..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_descrambler_top.vhd
+++ /dev/null
@@ -1,246 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
-
---***************************** Module Declaration ****************************
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_DESCRAMBLER_TOP is
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- RX_PAD_IN : in std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA_IN : in std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V_IN : in std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP_IN : in std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP_IN : in std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF_IN : in std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB_IN : in std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- RX_SP_IN : in std_logic; -- SP sequence received with positive or negative data.
- RX_SPA_IN : in std_logic; -- SPA sequence received.
- RX_NEG_IN : in std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- RX_CC : out std_logic; -- CC sequence received.
-
- GOT_A_IN : in std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V_IN : in std_logic; -- V sequence received.
-
- RX_CC_IN : in std_logic; -- CC sequence received.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- CLEAR : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_DESCRAMBLER_TOP;
-
-architecture BEHAVIORAL of east_channel_DESCRAMBLER_TOP is
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
---**************************************Signal Declarations***************************
-
- signal en_scrambler : std_logic_vector(1 downto 0);
- signal bypass_w : std_logic_vector(1 downto 0);
- signal bypass_r : std_logic_vector(1 downto 0);
- signal user_data : std_logic_vector(31 downto 0);
- signal scrambled_data : std_logic_vector(31 downto 0);
- signal data_nxt2 : std_logic_vector(0 to 31);
- signal RX_PE_DATA_Buffer : std_logic_vector(0 to 31);
- signal RX_SUF_Buffer : std_logic_vector(0 to 1);
-
- component east_channel_SCRAMBLER is
-
- generic
- (
- C_SEED : std_logic_vector := X"FFFF"
- );
-
- port
- (
- DOUT : out std_logic_vector(15 downto 0);
-
- DIN : in std_logic_vector(15 downto 0);
- BYPASS : in std_logic;
- EN : in std_logic;
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- CLK : in std_logic
- );
-
- end component;
-
-
-begin
-
---*********************************Main Body of Code**********************************
-
- -- pipeline all SYM DEC inputs
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- RX_PAD <= RX_PAD_IN after DLY;
- data_nxt2 <= RX_PE_DATA_IN after DLY;
- RX_PE_DATA_V <= RX_PE_DATA_V_IN after DLY;
- RX_SCP <= RX_SCP_IN after DLY;
- RX_ECP <= RX_ECP_IN after DLY;
- RX_SUF_Buffer <= RX_SUF_IN after DLY;
- RX_FC_NB <= RX_FC_NB_IN after DLY;
- RX_SP <= RX_SP_IN after DLY;
- RX_SPA <= RX_SPA_IN after DLY;
- RX_NEG <= RX_NEG_IN after DLY;
- GOT_A <= GOT_A_IN after DLY;
- GOT_V <= GOT_V_IN after DLY;
- RX_CC <= RX_CC_IN after DLY;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- bypass_r <= bypass_w;
- end if;
- end process;
-
- bypass_w(0) <= '1' when ((NOT RX_PE_DATA_V_IN(0) or RX_PAD_IN(0) or GOT_V_IN or RESET) = '1') else
- '0';
-
- bypass_w(1) <= '1' when ((NOT RX_PE_DATA_V_IN(1) or RX_PAD_IN(1) or GOT_V_IN or RESET) = '1') else
- '0';
-
- user_data(15 downto 0) <= X"0000" when (bypass_w(0) = '1') else
- RX_PE_DATA_IN(0 to 15);
-
- user_data(31 downto 16) <= X"0000" when (bypass_w(1) = '1') else
- RX_PE_DATA_IN(16 to 31);
-
- en_scrambler(0) <= NOT bypass_w(0);
-
- en_scrambler(1) <= NOT bypass_w(1);
-
- east_channel_descrambler0_i : east_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(15 downto 0),
- DIN => user_data(15 downto 0),
- EN => en_scrambler(0),
- BYPASS => bypass_w(0),
- CLEAR => RX_CC_IN,
- RESET => RESET,
- CLK => USER_CLK
- );
-
- east_channel_descrambler1_i : east_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(31 downto 16),
- DIN => user_data(31 downto 16),
- EN => en_scrambler(1),
- BYPASS => bypass_w(1),
- CLEAR => RX_CC_IN,
- RESET => RESET,
- CLK => USER_CLK
- );
-
-
- -- Outputs
-
- RX_PE_DATA_Buffer(0 to 15) <= data_nxt2(0 to 15) when (bypass_r(0) = '1') else
- scrambled_data(15 downto 0);
-
- RX_PE_DATA_buffer(16 to 31) <= data_nxt2(16 to 31) when (bypass_r(1) = '1') else
- scrambled_data(31 downto 16);
-
- RX_PE_DATA(0 to 15) <= RX_PE_DATA_Buffer(0 to 15);
-
- RX_PE_DATA(16 to 31) <= RX_PE_DATA_Buffer(16 to 31);
-
- RX_SUF <= RX_SUF_Buffer;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_err_detect_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_err_detect_4byte.vhd
deleted file mode 100644
index c21e938c8662fc14181d4a14159174d4bd95d4fb..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_err_detect_4byte.vhd
+++ /dev/null
@@ -1,295 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
---
--- ERR_DETECT_4BYTE
---
---
--- Description : The ERR_DETECT module monitors the GTX to detect hard errors.
--- It accumulates the Soft errors according to the leaky bucket
--- algorithm described in the Aurora Specification to detect Hard
--- errors. All errors are reported to the Global Logic Interface.
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use IEEE.STD_LOGIC_MISC.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_ERR_DETECT_4BYTE is
-generic
-(
- ENABLE_SOFT_ERR_MONITOR : integer := 1
-);
-port (
- -- Lane Init SM Interface
-
- ENABLE_ERR_DETECT : in std_logic;
- HARD_ERR_RESET : out std_logic;
-
- -- Global Logic Interface
-
- SOFT_ERR : out std_logic_vector(0 to 1);
- HARD_ERR : out std_logic;
-
- -- GTX Interface
-
- RX_BUF_ERR : in std_logic;
- RX_DISP_ERR : in std_logic_vector(3 downto 0);
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0);
- TX_BUF_ERR : in std_logic;
- RX_REALIGN : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
- );
-
-end east_channel_ERR_DETECT_4BYTE;
-
-architecture RTL of east_channel_ERR_DETECT_4BYTE is
-
---Constant Declarations --
-
- constant DLY : time := 1 ns;
-
--- VHDL out buffer logic --
-
- signal SOFT_ERR_Buffer : std_logic_vector(0 to 1);
- signal HARD_ERR_Buffer : std_logic;
-
-
--- Internal Register Declarations --
-
- signal hard_err_gt : std_logic;
- signal hard_err_frm_soft_err : std_logic;
- signal err_cnt_r : std_logic_vector(2 downto 0);
- signal good_cnt_r : std_logic_vector(3 downto 0);
- signal soft_err_r : std_logic_vector(0 to 3);
-
- -- FSM registers
- signal start_r : std_logic;
- signal cnt_soft_err_r : std_logic;
- signal cnt_good_code_r : std_logic;
-
- signal next_start_c : std_logic;
- signal next_soft_err_c : std_logic;
- signal next_good_code_c : std_logic;
-
-begin
-
- -- VHDL Output Buffers --
-
- SOFT_ERR <= SOFT_ERR_Buffer;
- HARD_ERR <= HARD_ERR_Buffer;
-
--- Main Body of Code --
-
- -- Error Processing --
-
- -- Detect Soft Errors. The lane is divided into 2 2-byte sublanes for this purpose.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- -- Sublane 0
- soft_err_r(0) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(3) or RX_NOT_IN_TABLE(3)) after DLY;
- soft_err_r(1) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(2) or RX_NOT_IN_TABLE(2)) after DLY;
-
- -- Sublane 1
- soft_err_r(2) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(1) or RX_NOT_IN_TABLE(1)) after DLY;
- soft_err_r(3) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(0) or RX_NOT_IN_TABLE(0)) after DLY;
-
- end if;
-
- end process;
-
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- -- Sublane 0
- SOFT_ERR_Buffer(0) <= soft_err_r(0) or soft_err_r(1) after DLY;
-
- -- Sublane 1
- SOFT_ERR_Buffer(1) <= soft_err_r(2) or soft_err_r(3) after DLY;
-
- end if;
-
- end process;
-
-
- -- Detect Hard Errors
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(ENABLE_ERR_DETECT = '1') then
-
- hard_err_gt <= (RX_BUF_ERR or TX_BUF_ERR or RX_REALIGN) after DLY;
-
- else
-
- hard_err_gt <= '0' after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(ENABLE_ERR_DETECT = '0') then
-
- hard_err_frm_soft_err <= '0' after DLY;
-
- else
-
- hard_err_frm_soft_err <= err_cnt_r(2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-soft_err_mon_enable : if ENABLE_SOFT_ERR_MONITOR = 1 generate
-
- HARD_ERR_Buffer <= hard_err_gt or (err_cnt_r(2) AND (NOT hard_err_frm_soft_err));
-
-end generate soft_err_mon_enable;
-
-
-soft_err_mon_disable : if ENABLE_SOFT_ERR_MONITOR = 0 generate
-
- HARD_ERR_Buffer <= hard_err_gt;
-
-end generate soft_err_mon_disable;
-
-
- -- Assert hard error reset when there is a hard error. This assignment
- -- just renames the two fanout branches of the hard error signal.
-
- HARD_ERR_RESET <= HARD_ERR_Buffer;
-
- --State registers for 1-hot state machine
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(ENABLE_ERR_DETECT = '0') then
- start_r <= '1' after DLY;
- cnt_soft_err_r <= '0' after DLY;
- cnt_good_code_r <= '0' after DLY;
- else
- start_r <= next_start_c after DLY;
- cnt_soft_err_r <= next_soft_err_c after DLY;
- cnt_good_code_r <= next_good_code_c after DLY;
- end if;
- end if;
- end process;
-
-
- next_start_c <= (start_r AND not(OR_REDUCE(soft_err_r))) OR
- (cnt_good_code_r AND not(OR_REDUCE(soft_err_r)) AND (AND_REDUCE(good_cnt_r)));
-
- next_soft_err_c <= (start_r AND (OR_REDUCE(soft_err_r))) OR
- (cnt_soft_err_r AND (OR_REDUCE(soft_err_r))) OR
- (cnt_good_code_r AND (OR_REDUCE(soft_err_r)));
-
- next_good_code_c <= (cnt_good_code_r AND NOT(OR_REDUCE(soft_err_r)) AND (NOT(AND_REDUCE(good_cnt_r)))) OR
- (cnt_soft_err_r AND NOT(OR_REDUCE(soft_err_r)));
-
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(ENABLE_ERR_DETECT = '0') then
- err_cnt_r <= (others => '0') after DLY;
- elsif((err_cnt_r(2) OR ((std_bool(good_cnt_r=X"4") OR std_bool(good_cnt_r=X"8") OR std_bool(good_cnt_r=X"C")) AND std_bool(cnt_soft_err_r='1'))) = '1') then
- err_cnt_r <= err_cnt_r after DLY;
- elsif(((OR_REDUCE(err_cnt_r)) AND (std_bool(good_cnt_r=X"4") OR std_bool(good_cnt_r=X"8") OR std_bool(good_cnt_r=X"C"))) = '1') then
- err_cnt_r <= err_cnt_r - 1 after DLY;
- elsif(cnt_soft_err_r = '1') then
- err_cnt_r <= err_cnt_r + 1 after DLY;
- end if;
- end if;
- end process;
-
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(((NOT ENABLE_ERR_DETECT) OR cnt_soft_err_r OR start_r) = '1') then
- good_cnt_r <= (others => '0') after DLY;
- elsif(cnt_good_code_r = '1') then
- good_cnt_r <= good_cnt_r + 1 after DLY;
- else
- good_cnt_r <= (others => '0') after DLY;
- end if;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_global_logic.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_global_logic.vhd
deleted file mode 100644
index 44bc138f0f22967b12c5d089c0272d578fe470fd..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_global_logic.vhd
+++ /dev/null
@@ -1,318 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- GLOBAL_LOGIC
---
---
---
--- Description: The GLOBAL_LOGIC module handles channel bonding, channel
--- verification, channel error manangement and idle generation.
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity east_channel_GLOBAL_LOGIC is
-
- port (
-
- -- GTP Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-LANE_UP : in std_logic;
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-RESET_LANES : out std_logic;
-
- GTRXRESET_OUT : out std_logic;
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- POWER_DOWN : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic
-
- );
-
-end east_channel_GLOBAL_LOGIC;
-
-architecture MAPPED of east_channel_GLOBAL_LOGIC is
-
--- External Register Declarations --
-
- signal EN_CHAN_SYNC_Buffer : std_logic;
-signal GEN_A_Buffer : std_logic;
-signal GEN_K_Buffer : std_logic_vector(0 to 3);
-signal GEN_R_Buffer : std_logic_vector(0 to 3);
-signal GEN_V_Buffer : std_logic_vector(0 to 3);
-signal RESET_LANES_Buffer : std_logic;
- signal CHANNEL_UP_Buffer : std_logic;
- signal START_RX_Buffer : std_logic;
- signal CHANNEL_SOFT_ERR_Buffer : std_logic;
- signal CHANNEL_HARD_ERR_Buffer : std_logic;
-
--- Wire Declarations --
-
- signal gen_ver_i : std_logic;
- signal reset_channel_i : std_logic;
- signal did_ver_i : std_logic;
-
--- Component Declarations --
-
- component east_channel_CHANNEL_INIT_SM
-
- port (
-
- -- GTP Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-RESET_LANES : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
-
- -- Idle and Verification Sequence Generator Interface
-
- DID_VER : in std_logic;
- GEN_VER : out std_logic;
-
- -- Channel Init State Machine Interface
-
- GTRXRESET_OUT : out std_logic;
- RESET_CHANNEL : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_IDLE_AND_VER_GEN
-
- port (
-
- -- Channel Init SM Interface
-
- GEN_VER : in std_logic;
- DID_VER : out std_logic;
-
- -- Aurora Lane Interface
-
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-
- -- System Interface
-
- RESET : in std_logic;
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_CHANNEL_ERR_DETECT
-
- port (
-
- -- Aurora Lane Interface
-
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-LANE_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- POWER_DOWN : in std_logic;
-
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic;
-
- -- Channel Init SM Interface
-
- RESET_CHANNEL : out std_logic
-
- );
-
- end component;
-
-begin
-
- EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
- GEN_A <= GEN_A_Buffer;
- GEN_K <= GEN_K_Buffer;
- GEN_R <= GEN_R_Buffer;
- GEN_V <= GEN_V_Buffer;
- RESET_LANES <= RESET_LANES_Buffer;
- CHANNEL_UP <= CHANNEL_UP_Buffer;
- START_RX <= START_RX_Buffer;
- CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer;
- CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;
-
--- Main Body of Code --
-
- -- State Machine for channel bonding and verification.
-
- channel_init_sm_i : east_channel_CHANNEL_INIT_SM
-
- port map (
-
- -- GTP Interface
-
- CH_BOND_DONE => CH_BOND_DONE,
- EN_CHAN_SYNC => EN_CHAN_SYNC_Buffer,
-
- -- Aurora Lane Interface
-
- CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
- GOT_A => GOT_A,
- GOT_V => GOT_V,
- RESET_LANES => RESET_LANES_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET,
- START_RX => START_RX_Buffer,
- CHANNEL_UP => CHANNEL_UP_Buffer,
-
- -- Idle and Verification Sequence Generator Interface
-
- DID_VER => did_ver_i,
- GEN_VER => gen_ver_i,
-
- -- Channel Error Management Module Interface
- GTRXRESET_OUT => GTRXRESET_OUT,
- RESET_CHANNEL => reset_channel_i
-
- );
-
-
- -- Idle and verification sequence generator module.
-
- idle_and_ver_gen_i : east_channel_IDLE_AND_VER_GEN
-
- port map (
-
- -- Channel Init SM Interface
-
- GEN_VER => gen_ver_i,
- DID_VER => did_ver_i,
-
- -- Aurora Lane Interface
-
- GEN_A => GEN_A_Buffer,
- GEN_K => GEN_K_Buffer,
- GEN_R => GEN_R_Buffer,
- GEN_V => GEN_V_Buffer,
-
- -- System Interface
-
- RESET => RESET,
- USER_CLK => USER_CLK
-
- );
-
-
-
- -- Channel Error Management module.
-
- channel_err_detect_i : east_channel_CHANNEL_ERR_DETECT
-
- port map (
-
- -- Aurora Lane Interface
-
- SOFT_ERR => SOFT_ERR,
- HARD_ERR => HARD_ERR,
- LANE_UP => LANE_UP,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- POWER_DOWN => POWER_DOWN,
- CHANNEL_SOFT_ERR => CHANNEL_SOFT_ERR_Buffer,
- CHANNEL_HARD_ERR => CHANNEL_HARD_ERR_Buffer,
-
- -- Channel Init State Machine Interface
-
- RESET_CHANNEL => reset_channel_i
-
- );
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_hotplug.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_hotplug.vhd
deleted file mode 100644
index c1551d29b3c4c2892898397ea989a565d32f7db9..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_hotplug.vhd
+++ /dev/null
@@ -1,264 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
--- Hot-plug logic
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_HOTPLUG is
-generic
-(
- ENABLE_HOTPLUG : integer := 1;
- EXAMPLE_SIMULATION : integer := 0
-);
-port
-(
-
- ---------------------- Sym Dec Interface -------------------------------
- RX_CC : in std_logic;
- RX_SP : in std_logic;
- RX_SPA : in std_logic;
-
- ---------------------- GT Wrapper Interface ----------------------------
- LINK_RESET_OUT : out std_logic := '0';
- HPCNT_RESET : in std_logic;
-
- ---------------------- System Interface ----------------------------
- INIT_CLK : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
-
-);
-
-end east_channel_HOTPLUG;
-
-architecture BEHAVIORAL of east_channel_HOTPLUG is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of BEHAVIORAL : architecture is "yes";
- attribute core_generation_info : string;
-attribute core_generation_info of BEHAVIORAL : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- component east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
- signal link_reset_0 : std_logic;
- signal link_reset_r : std_logic;
- signal count_for_reset_r : std_logic_vector(21 downto 0) := "0000000000000000000000";
- signal rx_cc_extend_r : std_logic_vector(7 downto 0) := "00000000";
- signal rx_cc_extend_r2 : std_logic;
- signal cc_sync : std_logic;
-
-begin
-
---*********************************Main Body of Code**********************************
-
---Extend the RX_CC pulse for 8 clock cycles
---This RX_CC extension is required when INIT_CLK is slower than USER_CLK
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- rx_cc_extend_r <= (others => '0') after DLY;
- else
- rx_cc_extend_r <= RX_CC & rx_cc_extend_r(7 downto 1) after DLY;
- end if;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- rx_cc_extend_r2 <= OR_REDUCE(rx_cc_extend_r) after DLY;
- end if;
- end process;
-
- -- Clock domain crossing from USER_CLK to INIT_CLK
- rx_cc_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => USER_CLK ,
- prmry_resetn => '1' ,
- prmry_in => rx_cc_extend_r2 ,
- prmry_vect_in => "00" ,
- scndry_aclk => INIT_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => cc_sync ,
- scndry_vect_out => open
- );
-
- -- Incoming control characters are decoded to detmine CC reception
- -- Reset the link if CC is not detected for longer time
- -- Wait for sufficient time to allow the link recovery and CC consumption
- -- link_reset_0 is used to reset the GT & Aurora core
-
- -- RX_CC is used as the reset for the count_for_reset_r
-hotplug_count_synth : if EXAMPLE_SIMULATION = 0 generate
- process(INIT_CLK,HPCNT_RESET)
- begin
- if(HPCNT_RESET = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- elsif(INIT_CLK'event and INIT_CLK = '1') then
- if(cc_sync = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- else
- count_for_reset_r <= count_for_reset_r + 1 after DLY;
- end if;
- end if;
- end process;
-end generate hotplug_count_synth;
-
-hotplug_count_sim : if EXAMPLE_SIMULATION = 1 generate
-process(INIT_CLK,HPCNT_RESET)
-begin
- if(HPCNT_RESET = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- elsif(INIT_CLK'event and INIT_CLK = '1') then
- if(cc_sync = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- else
- if (count_for_reset_r = X"FFFFF") then
- count_for_reset_r <= (others => '0') after DLY;
- else
- count_for_reset_r <= count_for_reset_r + 1 after DLY;
- end if;
- end if;
- end if;
-end process;
-end generate hotplug_count_sim;
-
-link_reset_synth : if EXAMPLE_SIMULATION = 0 generate
- link_reset_0 <= '1' when ((count_for_reset_r > X"3FFFEB") AND (count_for_reset_r < X"3FFFFF")) else
- '0'; -- 4194283 to 4194303
-end generate link_reset_synth;
-
-link_reset_sim : if EXAMPLE_SIMULATION = 1 generate
- -- Wait for sufficient time : 2^20 = 1048576 for simulation
- link_reset_0 <= '1' when ((count_for_reset_r > X"FF447") AND (count_for_reset_r < X"FFFFA")) else
- '0'; -- 1045575 to 1048570
-end generate link_reset_sim;
-
- process(INIT_CLK)
- begin
- if(INIT_CLK'event and INIT_CLK = '1') then
- link_reset_r <= link_reset_0 after DLY;
- end if;
- end process;
-
-hotplug_enable : if ENABLE_HOTPLUG = 1 generate
-
- process(INIT_CLK)
- begin
- if(INIT_CLK'event and INIT_CLK = '1') then
- LINK_RESET_OUT <= link_reset_r after DLY;
- end if;
- end process;
-
-end generate hotplug_enable;
-
-
-hotplug_disable : if ENABLE_HOTPLUG = 0 generate
-
- LINK_RESET_OUT <= '0';
-
-end generate hotplug_disable;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_idle_and_ver_gen.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_idle_and_ver_gen.vhd
deleted file mode 100644
index 4b23df2cb3070aa36907b1e74c3e4f5c47de9c39..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_idle_and_ver_gen.vhd
+++ /dev/null
@@ -1,599 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- IDLE_AND_VER_GEN
---
---
--- Description: the IDLE_AND_VER_GEN module generates idle sequences and
--- verification sequences for the Aurora channel. The idle sequences
--- are constantly generated by a pseudorandom generator and a counter
--- to make the sequence Aurora compliant. If the gen_ver signal is high,
--- verification symbols are added to the mix at appropriate intervals
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-
-entity east_channel_IDLE_AND_VER_GEN is
-
- port (
-
- -- Channel Init SM Interface
-
- GEN_VER : in std_logic;
- DID_VER : out std_logic;
-
- -- Aurora Lane Interface
-
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-
- -- System Interface
-
- RESET : in std_logic;
- USER_CLK : in std_logic
-
- );
-
-end east_channel_IDLE_AND_VER_GEN;
-
-architecture RTL of east_channel_IDLE_AND_VER_GEN is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal DID_VER_Buffer : std_logic;
-signal GEN_A_Buffer : std_logic;
-signal GEN_K_Buffer : std_logic_vector(0 to 3);
-signal GEN_R_Buffer : std_logic_vector(0 to 3);
-signal GEN_V_Buffer : std_logic_vector(0 to 3);
-
--- Internal Register Declarations --
-
- signal lfsr_reg : std_logic_vector(0 to 3) := "0000";
- signal down_count_r : std_logic_vector(0 to 2) := "000";
- signal downcounter_r : std_logic_vector(0 to 2) := "000";
- signal prev_cycle_gen_ver_r : std_logic;
-
--- Wire Declarations --
-
- signal gen_k_c : std_logic_vector(0 to 3);
- signal gen_r_c : std_logic_vector(0 to 3);
- signal ver_counter_c : std_logic;
- signal gen_k_flop_c : std_logic_vector(0 to 3);
- signal gen_r_flop_c : std_logic_vector(0 to 3);
- signal gen_a_flop_c : std_logic;
- signal downcounter_done_c : std_logic;
- signal gen_ver_edge_c : std_logic;
- signal recycle_gen_ver_c : std_logic;
- signal insert_ver_c : std_logic;
-
- signal tied_to_gnd : std_logic;
- signal tied_to_vcc : std_logic;
-
--- Component Declaration --
-
- component FD
-
- -- synthesis translate_off
- generic (INIT : bit := '0');
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic
-
- );
-
- end component;
-
- component FDR
-
- -- synthesis translate_off
- generic (INIT : bit := '0');
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic;
- R : in std_ulogic
-
- );
-
- end component;
-
- component SRL16
-
- -- synthesis translate_off
- generic (INIT : bit_vector := X"0000");
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- A0 : in std_ulogic;
- A1 : in std_ulogic;
- A2 : in std_ulogic;
- A3 : in std_ulogic;
- CLK : in std_ulogic;
- D : in std_ulogic
-
- );
-
- end component;
-
-begin
-
- DID_VER <= DID_VER_Buffer;
- GEN_A <= GEN_A_Buffer;
- GEN_K <= GEN_K_Buffer;
- GEN_R <= GEN_R_Buffer;
- GEN_V <= GEN_V_Buffer;
-
- tied_to_gnd <= '0';
- tied_to_vcc <= '1';
-
--- Main Body of Code --
-
- -- Use an LFSR to create pseudorandom patterns. This is a 4-bit LFSR from
- -- the Aurora 401. Taps on bits 0 and 3 are XORed with the OR of bits 1:3
- -- to make the input to the register.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- lfsr_reg(0) <= lfsr_reg(1);
- lfsr_reg(1) <= lfsr_reg(2);
- lfsr_reg(2) <= lfsr_reg(3);
- lfsr_reg(3) <= (lfsr_reg(0) xor lfsr_reg(3) xor
- (not (lfsr_reg(1) or lfsr_reg(2) or lfsr_reg(3))));
-
- end if;
-
- end process;
-
-
- -- A constants generator is used to limit the downcount range to values
- -- between 3 and 6 (4 to 7 clocks, 16 to 28 bytes).
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case lfsr_reg(1 to 3) is
-
- when "000" => down_count_r <= "011";
- when "001" => down_count_r <= "100";
- when "010" => down_count_r <= "101";
- when "011" => down_count_r <= "110";
- when "100" => down_count_r <= "011";
- when "101" => down_count_r <= "100";
- when "110" => down_count_r <= "101";
- when "111" => down_count_r <= "110";
- when others => down_count_r <= "XXX";
-
- end case;
-
- end if;
-
- end process;
-
- -- Use a downcounter to determine when A's should be added to the idle pattern.
- -- Load the counter with the 3 least significant bits of the lfsr whenever the
- -- counter reaches 0.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- downcounter_r <= "000" after DLY;
-
- else
-
- if (downcounter_done_c = '1') then
-
- downcounter_r <= down_count_r after DLY;
-
- else
-
- downcounter_r <= downcounter_r - "001" after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- downcounter_done_c <= std_bool(downcounter_r = "000");
-
-
- -- The LFSR's pseudo random patterns are also used to generate the sequence of
- -- K and R characters that make up the rest of the idle sequence. Note that
- -- R characters are used whenever K characters are not.
-
- gen_r_c <= lfsr_reg;
- gen_k_c <= not lfsr_reg;
-
- -- Verification Sequence Generation --
-
- -- Use a counter to generate the verification sequence every 64 bytes
- -- (16 clocks), starting from when verification is enabled.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- prev_cycle_gen_ver_r <= GEN_VER after DLY;
-
- end if;
-
- end process;
-
-
- -- Detect the positive edge of the GEN_VER signal.
-
- gen_ver_edge_c <= GEN_VER and not prev_cycle_gen_ver_r;
-
-
- -- If GEN_VER is still high after generating a verification sequence,
- -- indicate that the gen_ver signal can be generated again.
-
- recycle_gen_ver_c <= DID_VER_Buffer and GEN_VER;
-
-
- -- Prime the verification counter SRL16 with a 1. When this 1 reaches the end
- -- of the register, it will become the gen_ver_word signal. Prime the counter
- -- only if there was a positive edge on GEN_VER to start the sequence, or if
- -- the sequence has just ended and another must be generated.
-
- insert_ver_c <= gen_ver_edge_c or recycle_gen_ver_c;
-
-
- -- Main Body of the verification counter. It is implemented as a shift register
- -- made from an SRL16. The register is 15 cycles long, and operates by
- -- taking the 1 from the insert_ver_c signal and passing it though its stages.
-
- ver_counter_i : SRL16
-
-
- -- synthesis translate_off
- generic map (INIT => X"0000")
- -- synthesis translate_on
- port map (
-
- Q => ver_counter_c,
- A0 => tied_to_gnd,
- A1 => tied_to_vcc,
- A2 => tied_to_vcc,
- A3 => tied_to_vcc,
- CLK => USER_CLK,
- D => insert_ver_c
-
- );
-
-
- -- Generate the 4 bytes of the verification sequence on the cycle after
- -- the verification counter reaches '15'. Also signals that the verification
- -- sequence has been generated.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- DID_VER_Buffer <= ver_counter_c after DLY;
-
- end if;
-
- end process;
-
- -- Output Signals --
-
- -- Assert GEN_V in the LSBytes of each lane when DID_VER is asserted. We use
- -- a seperate register for each output to provide enough slack to allow the
- -- Global logic to communicate with all lanes without causing timing problems.
-
- GEN_V_Buffer(0) <= '0';
-
-
- gen_v_flop_1_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
- port map (
-
- D => recycle_gen_ver_c,
- C => USER_CLK,
- Q => GEN_V_Buffer(1)
-
- );
-
-
- gen_v_flop_2_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
- D => recycle_gen_ver_c,
- C => USER_CLK,
- Q => GEN_V_Buffer(2)
- );
-
-
- gen_v_flop_3_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
- D => recycle_gen_ver_c,
- C => USER_CLK,
- Q => GEN_V_Buffer(3)
- );
-
-
- -- Assert GEN_A in the MSByte of each lane when the GEN_A downcounter reaches 0.
- -- Note that the signal has a register for each output for the same reason as the
- -- GEN_V signal. GEN_A is ignored when it collides with other non-idle
- -- generation requests at the Aurora Lane, but we qualify the signal with
- -- the gen_ver_word_1_r signal so it does not overwrite the K used in the
- -- MSByte of the first word of the Verification sequence.
-
- gen_a_flop_c <= downcounter_done_c and not recycle_gen_ver_c;
-
-
- gen_a_flop_0_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_a_flop_c,
- C => USER_CLK,
- Q => GEN_A_Buffer
-
- );
-
-
- -- Assert GEN_K in the MSByte when the lfsr dictates. Turn off the assertion if an
- -- /A/ symbol is being generated on the byte. Assert the signal without qualifications
- -- if GEN_V is asserted. Assert GEN_K in the LSBytes when the lfsr dictates.
- -- There are no qualifications because only the GEN_R signal can collide with it, and
- -- this is prevented by the way the gen_k_c signal is generated. All other GEN signals
- -- will override this signal at the AURORA_LANE.
-
- gen_k_flop_c(0) <= (gen_k_c(0) and not downcounter_done_c) or recycle_gen_ver_c;
-
-
- gen_k_flop_0_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(0),
- C => USER_CLK,
- Q => GEN_K_Buffer(0)
-
- );
-
-
-
- gen_k_flop_c(1) <= gen_k_c(1);
-
-
- gen_k_flop_1_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(1),
- C => USER_CLK,
- Q => GEN_K_Buffer(1)
-
- );
-
-
- gen_k_flop_c(2) <= gen_k_c(2);
-
-
- gen_k_flop_2_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(2),
- C => USER_CLK,
- Q => GEN_K_Buffer(2)
-
- );
-
-
- gen_k_flop_c(3) <= gen_k_c(3);
-
-
- gen_k_flop_3_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(3),
- C => USER_CLK,
- Q => GEN_K_Buffer(3)
-
- );
-
-
- -- Assert GEN_R in the MSByte when the lfsr dictates. Turn off the assertion if an
- -- /A/ symbol, or the first verification word is being generated. Assert GEN_R in the
- -- LSByte when the lfsr dictates, with no qualifications (same reason as the GEN_K LSByte).
-
- gen_r_flop_c(0) <= gen_r_c(0) and not downcounter_done_c and not recycle_gen_ver_c;
-
-
- gen_r_flop_0_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_r_flop_c(0),
- C => USER_CLK,
- Q => GEN_R_Buffer(0)
-
- );
-
-
- gen_r_flop_c(1) <= gen_r_c(1);
-
-
- gen_r_flop_1_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_r_flop_c(1),
- C => USER_CLK,
- Q => GEN_R_Buffer(1)
-
- );
-
-
- gen_r_flop_c(2) <= gen_r_c(2);
-
-
- gen_r_flop_2_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_r_flop_c(2),
- C => USER_CLK,
- Q => GEN_R_Buffer(2)
-
- );
-
-
- gen_r_flop_c(3) <= gen_r_c(3);
-
-
- gen_r_flop_3_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
- D => gen_r_flop_c(3),
- C => USER_CLK,
- Q => GEN_R_Buffer(3)
- );
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_lane_init_sm_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_lane_init_sm_4byte.vhd
deleted file mode 100644
index 29e891a6326f0ea59f7fdb84856b18f987c268a2..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_lane_init_sm_4byte.vhd
+++ /dev/null
@@ -1,667 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- LANE_INIT_SM_4BYTE
---
---
---
--- Description: This logic manages the initialization of the GTX in 2-byte mode.
--- It consists of a small state machine, a set of counters for
--- tracking the progress of initializtion and detecting problems,
--- and some additional support logic.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
---synthesis translate_on
-
-entity east_channel_LANE_INIT_SM_4BYTE is
- port (
-
- -- GTX Interface
-
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- GTX received invalid 10b code
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- GTX received 10b code w/ wrong disparity
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- GTX received a Comma
- RX_REALIGN : in std_logic; -- GTX had to change alignment due to new comma
- RX_RESET : out std_logic; -- Reset the RX side of the GTX
- TX_RESET : out std_logic; -- Reset the TX side of the GTX
- RX_POLARITY : out std_logic; -- Sets polarity used to interpet rx'ed symbols
-
- -- Comma Detect Phase Alignment Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Turn on SERDES Alignment in GTX
-
- -- Symbol Generator Interface
-
- GEN_SP : out std_logic; -- Generate SP symbol
- GEN_SPA : out std_logic; -- Generate SPA symbol
-
- -- Symbol Decoder Interface
-
- RX_SP : in std_logic; -- Lane rx'ed SP sequence w/ + or - data
- RX_SPA : in std_logic; -- Lane rx'ed SPA sequence
- RX_NEG : in std_logic; -- Lane rx'ed inverted SP or SPA data
- DO_WORD_ALIGN : out std_logic; -- Enable word alignment
-
- -- Error Detection Logic Interface
-
- ENABLE_ERR_DETECT : out std_logic; -- Turn on Soft Error detection
- HARD_ERR_RESET : in std_logic; -- Reset lane due to hard error
-
- -- Global Logic Interface
-
- LANE_UP : out std_logic; -- Lane is initialized
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora logic
- RESET : in std_logic -- Reset Aurora Lane
-
- );
-
-end east_channel_LANE_INIT_SM_4BYTE;
-
-architecture RTL of east_channel_LANE_INIT_SM_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal RX_RESET_Buffer : std_logic;
- signal TX_RESET_Buffer : std_logic;
- signal RX_POLARITY_Buffer : std_logic;
- signal ENA_COMMA_ALIGN_Buffer : std_logic;
- signal GEN_SP_Buffer : std_logic;
- signal GEN_SPA_Buffer : std_logic;
- signal DO_WORD_ALIGN_Buffer : std_logic;
- signal ENABLE_ERR_DETECT_Buffer : std_logic;
- signal LANE_UP_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- -- counter1 is intitialized to ensure that the counter comes up at some value other than X.
- -- We have tried different initial values and it does not matter what the value is, as long
- -- as it is not X since X breaks the state machine
- signal counter1_r : unsigned(0 to 7) := "00000001";
- signal counter2_r : std_logic_vector(0 to 15);
- signal counter3_r : std_logic_vector(0 to 3);
- signal counter4_r : std_logic_vector(0 to 15);
- signal counter5_r : std_logic_vector(0 to 15);
- signal rx_polarity_r : std_logic := '0';
- signal RX_CHAR_IS_COMMA_R : std_logic_vector(3 downto 0);
- signal prev_char_was_comma_r : std_logic;
- signal consecutive_commas_r : std_logic;
- signal prev_count_128d_done_r : std_logic;
- signal do_watchdog_count_r : std_logic;
-
- -- FSM states, encoded for one-hot implementation.
-
- signal begin_r : std_logic;
- signal rst_r : std_logic; -- Reset GTXs
- signal align_r : std_logic; -- Align SERDES
- signal realign_r : std_logic; -- Verify no spurious realignment
- signal polarity_r : std_logic; -- Verify polarity of rx'ed symbols
- signal ack_r : std_logic; -- Ack initialization with partner
- signal ready_r : std_logic; -- Lane ready for Bonding/Verification
-
--- Wire Declarations --
-
- signal count_8d_done_r : std_logic;
- signal count_32d_done_r : std_logic;
- signal count_128d_done_r : std_logic;
- signal reset_count_r : std_logic;
- signal symbol_err_c : std_logic;
- signal txack_16d_done_r : std_logic;
- signal rxack_4d_done_r : std_logic;
- signal sp_polarity_c : std_logic;
- signal inc_count_c : std_logic;
- signal change_in_state_c : std_logic;
- signal watchdog_done_r : std_logic;
- signal remote_reset_watchdog_done_r : std_logic;
-
- signal next_begin_c : std_logic;
- signal next_rst_c : std_logic;
- signal next_align_c : std_logic;
- signal next_realign_c : std_logic;
- signal next_polarity_c : std_logic;
- signal next_ack_c : std_logic;
- signal next_ready_c : std_logic;
-
- component FDR
-
- port (
- D : in std_logic;
- C : in std_logic;
- R : in std_logic;
- Q : out std_logic
- );
-
- end component;
-
-begin
-
- RX_RESET <= RX_RESET_Buffer;
- TX_RESET <= TX_RESET_Buffer;
- RX_POLARITY <= RX_POLARITY_Buffer;
- ENA_COMMA_ALIGN <= ENA_COMMA_ALIGN_Buffer;
- GEN_SP <= GEN_SP_Buffer;
- GEN_SPA <= GEN_SPA_Buffer;
- DO_WORD_ALIGN <= DO_WORD_ALIGN_Buffer;
- ENABLE_ERR_DETECT <= ENABLE_ERR_DETECT_Buffer;
- LANE_UP <= LANE_UP_Buffer;
-
--- Main Body of Code --
-
- -- Main state machine for managing initialization --
-
- -- State registers
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or HARD_ERR_RESET ) = '1') then
-
- begin_r <= '1' after DLY;
- rst_r <= '0' after DLY;
- align_r <= '0' after DLY;
- realign_r <= '0' after DLY;
- polarity_r <= '0' after DLY;
- ack_r <= '0' after DLY;
- ready_r <= '0' after DLY;
-
- else
-
- begin_r <= next_begin_c after DLY;
- rst_r <= next_rst_c after DLY;
- align_r <= next_align_c after DLY;
- realign_r <= next_realign_c after DLY;
- polarity_r <= next_polarity_c after DLY;
- ack_r <= next_ack_c after DLY;
- ready_r <= next_ready_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
- -- Next state logic
-
- next_begin_c <= (realign_r and RX_REALIGN) or
- (polarity_r and not sp_polarity_c) or
- (ack_r and watchdog_done_r) or
- (ready_r and remote_reset_watchdog_done_r);
-
- next_rst_c <= (rst_r and not count_8d_done_r) or begin_r;
-
-
- next_align_c <= (rst_r and count_8d_done_r) or
- (align_r and not count_128d_done_r);
-
-
- next_realign_c <= (align_r and count_128d_done_r) or
- ((realign_r and not count_32d_done_r) and not RX_REALIGN);
-
-
- next_polarity_c <= ((realign_r and count_32d_done_r) and not RX_REALIGN);
-
-
- next_ack_c <= (polarity_r and sp_polarity_c) or
- ((ack_r and (not txack_16d_done_r or not rxack_4d_done_r)) and not watchdog_done_r);
-
-
- next_ready_c <= (ack_r and txack_16d_done_r and rxack_4d_done_r and not watchdog_done_r) or
- (ready_r and not remote_reset_watchdog_done_r);
-
-
- -- Output Logic
-
- -- Enable comma align when in the ALIGN state.
-
- ENA_COMMA_ALIGN_Buffer <= align_r;
-
-
- -- Hold RX_RESET when in the RST state.
-
- RX_RESET_Buffer <= rst_r;
-
-
- -- Hold TX_RESET when in the RST state.
-
- TX_RESET_Buffer <= rst_r;
-
-
- -- LANE_UP is asserted when in the READY state. The FDR flop is
- -- instantiated to ensure that the LANE_UP signal is initialised
- -- to '0' at start-up.
-
- lane_up_flop_i : FDR
-
- port map (
- D => ready_r,
- C => USER_CLK,
- R => RESET,
- Q => LANE_UP_Buffer
- );
-
-
- -- ENABLE_ERR_DETECT is asserted when in the ACK or READY states. Asserting
- -- it earlier will result in too many false errors. After it is asserted,
- -- higher level modules can respond to Hard Errors by resetting the Aurora Lane.
- -- We register the signal before it leaves the lane_init_sm submodule.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- ENABLE_ERR_DETECT_Buffer <= ack_r or ready_r after DLY;
-
- end if;
-
- end process;
-
-
- -- The Aurora Lane should transmit SP sequences when not ACKing or Ready.
-
- GEN_SP_Buffer <= not (ack_r or ready_r);
-
-
- -- The Aurora Lane transmits SPA sequences while in the ACK state.
-
- GEN_SPA_Buffer <= ack_r;
-
-
- -- Do word alignment in the ALIGN state and then again in the ready state. Align
- -- state word alignment makes SP and SPA decodes less expensive. Ready state word
- -- alignment is needed to correct any shifts due to channel bonding : it runs
- -- until it is shut off by arrival of the first /V/ sequence in the sym_dec module.
-
- DO_WORD_ALIGN_Buffer <= align_r or ready_r;
-
-
- -- Counter 1, for reset cycles, align cycles and realign cycles --
-
- -- Core of the counter.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((reset_count_r or ready_r) = '1') then
-
- counter1_r <= "00000001" after DLY;
-
- else
-
- if (inc_count_c = '1') then
-
- counter1_r <= counter1_r + "00000001" after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Assert count_8d_done_r when the 2^4 flop in the register first goes high.
-
- count_8d_done_r <= counter1_r(4);
-
-
- -- Assert count_32d_done_r when the 2^6 flop in the register first goes high.
-
- count_32d_done_r <= counter1_r(2);
-
-
- -- Assert count_128d_done_r when the 2^8 flop in the register first goes high.
-
- count_128d_done_r <= counter1_r(0);
-
-
- -- The counter resets any time the RESET signal is asserted, there is a change in
- -- state, there is a symbol error, or commas are not consecutive in the align state.
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- reset_count_r <= RESET or change_in_state_c or ( not rst_r and (symbol_err_c or not consecutive_commas_r));
-
- end if;
-
- end process;
-
-
- -- The counter should be reset when entering and leaving the reset state.
-
- change_in_state_c <= std_bool(rst_r /= next_rst_c);
-
-
- -- Symbol error is asserted whenever there is a disparity error or an invalid
- -- 10b code.
-
- symbol_err_c <= std_bool((RX_DISP_ERR /= "0000") or (RX_NOT_IN_TABLE /= "0000"));
-
- -- Pipeline stage to meet timing
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_CHAR_IS_COMMA_R <= RX_CHAR_IS_COMMA after DLY;
-
- end if;
-
- end process;
-
- -- Previous cycle comma is used to check for consecutive commas.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- prev_char_was_comma_r <= (RX_CHAR_IS_COMMA_R(3) or RX_CHAR_IS_COMMA_R(2) or
- RX_CHAR_IS_COMMA_R(1) or RX_CHAR_IS_COMMA_R(0)) after DLY;
-
- end if;
-
- end process;
-
-
- -- Check to see that commas are consecutive in the align state.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- consecutive_commas_r <= (RX_CHAR_IS_COMMA_R(3) or RX_CHAR_IS_COMMA_R(2) or
- RX_CHAR_IS_COMMA_R(1) or RX_CHAR_IS_COMMA_R(0)) or not align_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Increment count is always asserted, except in the ALIGN state when it is asserted
- -- only upon the arrival of a comma character.
-
- inc_count_c <= not align_r or (align_r and (RX_CHAR_IS_COMMA_R(3) or RX_CHAR_IS_COMMA_R(2) or
- RX_CHAR_IS_COMMA_R(1) or RX_CHAR_IS_COMMA_R(0)));
-
-
- -- Counter 2, for counting tx_acks --
-
- -- This counter is implemented as a shift register. It is constantly shifting. As a
- -- result, when the state machine is not in the ack state, the register clears out.
- -- When the state machine goes into the ack state, the count is incremented every
- -- cycle. The txack_16d_done signal goes high and stays high after 16 cycles in the
- -- ack state. The signal deasserts only after its had enough time for all the ones
- -- to clear out after the machine leaves the ack state, but this is tolerable because
- -- the machine will spend at least 8 cycles in reset, 256 in ALIGN and 32 in REALIGN.
-
- -- The counter is implemented seperately from the main counter because it is required
- -- to stop counting when it reaches the end of its count. Adding this functionality
- -- to the main counter is more expensive and more complex than implementing it seperately.
-
- -- Counter Logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- counter2_r <= ack_r & counter2_r(0 to 14) after DLY;
-
- end if;
-
- end process;
-
-
- -- The counter is done when a 1 reaches the end of the shift register.
-
- txack_16d_done_r <= counter2_r(15);
-
-
- -- Counter 3, for counting rx_acks --
-
- -- This counter is also implemented as a shift register. It is always shifting when
- -- the state machine is not in the ack state to clear it out. When the state machine
- -- goes into the ack state, the register shifts only when a SPA is received. When
- -- 4 SPAs have been received in the ACK state, the rxack_4d_done_r signal is triggered.
-
- -- This counter is implemented seperately from the main counter because it is required
- -- to increment only when ACKs are received, and then hold its count. Adding this
- -- functionality to the main counter is more expensive than creating a second counter,
- -- and more complex.
-
- -- Counter Logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RX_SPA or not ack_r) = '1') then
-
- counter3_r <= ack_r & counter3_r(0 to 2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The counter is done when a 1 reaches the end of the shift register.
-
- rxack_4d_done_r <= counter3_r(3);
-
-
- -- Counter 4, remote reset watchdog timer --
-
- -- Another counter implemented as a shift register. This counter puts an upper
- -- limit on the number of SPs that can be recieved in the Ready state. If the
- -- number of SPs exceeds the limit, the Aurora Lane resets itself. The Global
- -- logic module will reset all the lanes if this occurs while they are all in
- -- the lane ready state (ie lane_up is asserted for all).
-
- -- Counter logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RX_SP or not ready_r) = '1') then
-
- counter4_r <= ready_r & counter4_r(0 to 14) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The counter is done when a 1 reaches the end of the shift register.
-
- remote_reset_watchdog_done_r <= counter4_r(15);
-
-
- -- Counter 5, internal watchdog timer --
-
- -- This counter puts an upper limit on the number of cycles the state machine can
- -- spend in the ack state before it gives up and resets.
-
- -- The counter is implemented as a shift register extending counter 1. The counter
- -- clears out in all non-ack cycles by keeping CE asserted. When it gets into the
- -- ack state, CE is asserted only when there is a transition on the most
- -- significant bit of counter 1. This happens every 128 cycles. We count out 32 of
- -- these transitions to get a count of approximately 4096 cycles. The actual
- -- number of cycles is less than this because we don't reset counter1, so it
- -- starts off about 34 cycles into its count.
-
- -- Counter logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((do_watchdog_count_r or not ack_r) = '1') then
-
- counter5_r <= ack_r & counter5_r(0 to 14) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Store the count_128d_done_r result from the previous cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- prev_count_128d_done_r <= count_128d_done_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Trigger CE only when the previous 128d_done is not the same as the
- -- current one, and the current value is high.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- do_watchdog_count_r <= count_128d_done_r and not prev_count_128d_done_r after DLY;
-
- end if;
-
- end process;
-
-
- -- The counter is done when bit 15 is high.
-
- watchdog_done_r <= counter5_r(15);
-
-
- -- Polarity Control --
-
- -- sp_polarity_c, is low if neg symbols received, otherwise high.
-
- sp_polarity_c <= not RX_NEG;
-
-
- -- The Polarity flop drives the polarity setting of the GTX. We initialize it for the
- -- sake of simulation. We Initialize it after configuration for the hardware version.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((polarity_r and not sp_polarity_c) = '1') then
-
- rx_polarity_r <= not rx_polarity_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Drive the rx_polarity register value on the interface.
-
- RX_POLARITY_Buffer <= rx_polarity_r;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_left_align_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_left_align_control.vhd
deleted file mode 100644
index d87bc5f1326d313553a7cda0a37547b3320603a6..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_left_align_control.vhd
+++ /dev/null
@@ -1,243 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- LEFT_ALIGN_CONTROL
---
---
---
--- Description: The LEFT_ALIGN_CONTROL is used to control the Left Align Muxes in
--- the RX_LL module. Each module supports up to 8 lanes. Modules can
--- be combined in stages to support channels with more than 8 lanes.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_LEFT_ALIGN_CONTROL is
-
- port (
-
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
- MUX_SELECT : out std_logic_vector(0 to 5);
- VALID : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_LEFT_ALIGN_CONTROL;
-
-architecture RTL of east_channel_LEFT_ALIGN_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal MUX_SELECT_Buffer : std_logic_vector(0 to 5);
- signal VALID_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal mux_select_c : std_logic_vector(0 to 5);
- signal valid_c : std_logic_vector(0 to 1);
-
-begin
-
- MUX_SELECT <= MUX_SELECT_Buffer;
- VALID <= VALID_Buffer;
-
--- Main Body of Code --
-
- -- SELECT --
-
- -- Lane 0
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "01" =>
-
-mux_select_c(0 to 2) <= conv_std_logic_vector(1,3);
-
-when "10" =>
-
-mux_select_c(0 to 2) <= conv_std_logic_vector(0,3);
-
-when "11" =>
-
-mux_select_c(0 to 2) <= conv_std_logic_vector(0,3);
-
- when others =>
-
- mux_select_c(0 to 2) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Lane 1
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "11" =>
-
-mux_select_c(3 to 5) <= conv_std_logic_vector(0,3);
-
- when others =>
-
- mux_select_c(3 to 5) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the select signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- MUX_SELECT_Buffer <= mux_select_c after DLY;
-
- end if;
-
- end process;
-
-
- -- VALID --
-
- -- Lane 0
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "01" =>
-
- valid_c(0) <= '1';
-
-when "10" =>
-
- valid_c(0) <= '1';
-
-when "11" =>
-
- valid_c(0) <= '1';
-
- when others =>
-
- valid_c(0) <= '0';
-
- end case;
-
- end process;
-
-
- -- Lane 1
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "11" =>
-
- valid_c(1) <= '1';
-
- when others =>
-
- valid_c(1) <= '0';
-
- end case;
-
- end process;
-
-
- -- Register the valid signals for the next stage.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- VALID_Buffer <= (others => '0') after DLY;
-
- else
-
- VALID_Buffer <= valid_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_left_align_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_left_align_mux.vhd
deleted file mode 100644
index 5553be71fa3d155a6c6ab0b8f4dbb8541f95e04e..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_left_align_mux.vhd
+++ /dev/null
@@ -1,163 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- LEFT_ALIGN_MUX
---
---
---
--- Description: The left align mux is used to shift incoming data symbols
--- leftwards in the channel during the RX_LL left align step.
--- It consists of a set of muxes, one for each position in the
--- channel. The number of inputs for each mux decrements as the
--- position gets further from the left: the muxes for the leftmost
--- position are N:1. The 'muxes' for the rightmost position are 1:1
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_LEFT_ALIGN_MUX is
-
- port (
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end east_channel_LEFT_ALIGN_MUX;
-
-architecture RTL of east_channel_LEFT_ALIGN_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal MUXED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal muxed_data_c : std_logic_vector(0 to 31);
-
-begin
-
- MUXED_DATA <= MUXED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create muxes for each of the lanes.
-
- -- Mux for lane 0
-
- process (MUX_SELECT(0 to 2), RAW_DATA)
-
- begin
-
- case MUX_SELECT(0 to 2) is
-
-when "000" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "001" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (MUX_SELECT(3 to 5), RAW_DATA)
-
- begin
-
- case MUX_SELECT(3 to 5) is
-
-when "000" =>
-
- muxed_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the muxed data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- MUXED_DATA_Buffer <= muxed_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ll_to_axi.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ll_to_axi.vhd
deleted file mode 100644
index 2c3017126ec8463776caffbd5efd5a1d100aa697..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ll_to_axi.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
---
--- AXI_TO_LL
---
---
--- Description: This light wrapper/shim convertes Legacy LocalLink interface
--- signals from AXI-4 Stream protocol signals
---
---
-------------------------------------------------------------------------------/
-library IEEE;
-use IEEE.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-
-entity east_channel_LL_TO_AXI is
-generic
-(
- DATA_WIDTH : integer := 16; -- DATA bus width
- STRB_WIDTH : integer := 2; -- STROBE bus width
- USE_UFC_REM : integer := 0; -- UFC REM bus width identifier
- REM_WIDTH : integer := 1 -- REM bus width
-);
-
-port
-(
-
- ---------------------- AXI4-S Interface -------------------------------
- AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_OP_TVALID : out std_logic;
- AXI4_S_OP_TLAST : out std_logic;
- AXI4_S_IP_TREADY : in std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1);
- LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1);
- LL_IP_SRC_RDY_N : in std_logic;
- LL_IP_SOF_N : in std_logic;
- LL_IP_EOF_N : in std_logic;
- LL_OP_DST_RDY_N : out std_logic
-
-);
-
-end east_channel_LL_TO_AXI;
-
-architecture BEHAVIORAL of east_channel_LL_TO_AXI is
- attribute core_generation_info : string;
-attribute core_generation_info of BEHAVIORAL : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
- signal ll_ip_rem_inc_shift : std_logic_vector(0 to STRB_WIDTH-1);
- signal rem_int : integer range 0 to 4;
- signal ufc_rem_int : integer range 0 to 16;
- signal AXI4_S_OP_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1);
-
-begin
-
---*********************************Main Body of Code**********************************
-
- AXI4_S_OP_TDATA <= LL_IP_DATA;
-
-
- AXI4_S_OP_TKEEP <= AXI4_S_OP_TKEEP_i when (LL_IP_EOF_N = '0') else
- (others => '1');
-
-
-
-pdu_rem : if USE_UFC_REM = 0 generate
- rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
-ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl rem_int);
-AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else
- (not ll_ip_rem_inc_shift);
-end generate pdu_rem;
-
-ufc_rem : if USE_UFC_REM = 1 generate
- ufc_rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
-ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl ufc_rem_int);
-AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else
- (not ll_ip_rem_inc_shift);
-end generate ufc_rem;
-
- AXI4_S_OP_TVALID <= not LL_IP_SRC_RDY_N;
- AXI4_S_OP_TLAST <= not LL_IP_EOF_N;
- LL_OP_DST_RDY_N <= not AXI4_S_IP_TREADY;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_output_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_output_mux.vhd
deleted file mode 100644
index b3d8fab87919071beb2ac604369d572aa0397403..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_output_mux.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- OUTPUT_MUX
---
---
---
--- Description: The OUTPUT_MUX controls the flow of data to the LocalLink output
--- for user PDUs.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_OUTPUT_MUX is
-
- port (
-
- STORAGE_DATA : in std_logic_vector(0 to 31);
- LEFT_ALIGNED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- USER_CLK : in std_logic;
- OUTPUT_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end east_channel_OUTPUT_MUX;
-
-architecture RTL of east_channel_OUTPUT_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal OUTPUT_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal output_data_c : std_logic_vector(0 to 31);
-
-begin
-
- OUTPUT_DATA <= OUTPUT_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create a set of muxes for each lane. The number of inputs for each set of
- -- muxes increases as the lane index increases: lane 0 has one input only, the
- -- rightmost lane has 2 inputs. Note that the 0th input connection
- -- is always to the storage lane with the same index as the output lane: the
- -- remaining inputs connect to the left_aligned data register, starting at index 0.
-
- -- Mux for lane 0
-
- process (MUX_SELECT(0 to 4), STORAGE_DATA)
-
- begin
-
- case MUX_SELECT(0 to 4) is
-
-when "00000" =>
-
- output_data_c(0 to 15) <= STORAGE_DATA(0 to 15);
-
- when others =>
-
- output_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (MUX_SELECT(5 to 9), STORAGE_DATA, LEFT_ALIGNED_DATA)
-
- begin
-
- case MUX_SELECT(5 to 9) is
-
-when "00000" =>
-
- output_data_c(16 to 31) <= STORAGE_DATA(16 to 31);
-
-when "00001" =>
-
- output_data_c(16 to 31) <= LEFT_ALIGNED_DATA(0 to 15);
-
- when others =>
-
- output_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the output data
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- OUTPUT_DATA_Buffer <= output_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_output_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_output_switch_control.vhd
deleted file mode 100644
index f25885c90d90b556df37191e7d643692d9de41e0..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_output_switch_control.vhd
+++ /dev/null
@@ -1,150 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--------------------------------------------------------------------------------
---
--- OUTPUT_SWITCH_CONTROL
---
--------------------------------------------------------------------------------
---
---
--- Description: OUTPUT_SWITCH_CONTROL selects the input chunk for each muxed output chunk.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_OUTPUT_SWITCH_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- OUTPUT_SELECT : out std_logic_vector(0 to 9);
- USER_CLK : in std_logic
-
- );
-
-end east_channel_OUTPUT_SWITCH_CONTROL;
-
-architecture RTL of east_channel_OUTPUT_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal OUTPUT_SELECT_Buffer : std_logic_vector(0 to 9);
-
--- Internal Register Declarations --
-
- signal output_select_c : std_logic_vector(0 to 9);
-
--- Wire Declarations --
-
- signal take_storage_c : std_logic;
-
-begin
-
- OUTPUT_SELECT <= OUTPUT_SELECT_Buffer;
-
-
--- *************************** Main Body of Code ****************************
-
- -- Combine the End signals --
-
- take_storage_c <= END_STORAGE or START_WITH_DATA;
-
-
- -- Generate switch signals --
-
- -- Lane 0 is always connected to storage lane 0.
-
- -- Calculate switch setting for lane 1.
- process (take_storage_c, LEFT_ALIGNED_COUNT, STORAGE_COUNT)
- variable vec : std_logic_vector(0 to 3);
- begin
- if (take_storage_c = '1') then
- output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
- else
- vec := LEFT_ALIGNED_COUNT & STORAGE_COUNT;
- case vec is
-when "0001" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-when "0010" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
-when "0101" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-when "0110" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
-when "1001" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-when "1010" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
- when others =>
- output_select_c(5 to 9) <= (others => 'X');
- end case;
- end if;
- end process;
-
-
- -- Register the output select values.
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- OUTPUT_SELECT_Buffer <= "00000" & output_select_c(5 to 9) after DLY;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_reset_logic.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_reset_logic.vhd
deleted file mode 100644
index 088b971fc57e99e5a70b20278038682417dd1cc0..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_reset_logic.vhd
+++ /dev/null
@@ -1,301 +0,0 @@
-
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
----------------------------------------------------------------------------------------------
--- AURORA RESET LOGIC
---
---
--- Description: RESET logic using Debouncer
---
---
-
-library IEEE;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
--- synthesis translate_on
-
-entity east_channel_RESET_LOGIC is
- port (
- RESET : in std_logic;
- USER_CLK : in std_logic;
- INIT_CLK_IN : in std_logic;
- TX_LOCK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- LINK_RESET_IN : in std_logic;
- TX_RESETDONE_IN : in std_logic;
- RX_RESETDONE_IN : in std_logic;
- SYSTEM_RESET : out std_logic
- );
-
-end east_channel_RESET_LOGIC;
-
-architecture MAPPED of east_channel_RESET_LOGIC is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
- attribute core_generation_info : string;
- attribute core_generation_info of MAPPED : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- Internal Register Declarations --
-
- signal link_reset_sync : std_logic;
- signal link_reset_comb_r : std_logic;
- signal pll_not_locked_sync: std_logic;
- signal tx_lock_sync : std_logic;
- signal tx_lock_comb_r : std_logic;
- signal gt_rxresetdone_r : std_logic;
- signal gt_rxresetdone_r2 : std_logic;
- signal gt_rxresetdone_r3 : std_logic;
- signal gt_txresetdone_r : std_logic;
- signal gt_txresetdone_r2 : std_logic;
- signal gt_txresetdone_r3 : std_logic;
- signal tx_resetdone_sync : std_logic;
- signal tied_to_ground_i : std_logic;
-
--- Component Declarations --
-
- component east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
-
- component IBUFDS
- port (
-
- O : out std_ulogic;
- I : in std_ulogic;
- IB : in std_ulogic);
-
- end component;
-
-begin
-
- -- Tie off top level constants.
- tied_to_ground_i <= '0';
-
- -- ___________________________Debouncing circuit for GT_RESET_IN________________________
-
- process (USER_CLK, RX_RESETDONE_IN)
- begin
- if (RX_RESETDONE_IN = '0') then
- gt_rxresetdone_r <= '0' after DLY;
- gt_rxresetdone_r2 <= '0' after DLY;
- elsif (USER_CLK 'event and USER_CLK = '1') then
- gt_rxresetdone_r <= RX_RESETDONE_IN after DLY;
- gt_rxresetdone_r2 <= gt_rxresetdone_r after DLY;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- gt_rxresetdone_r3 <= gt_rxresetdone_r2 after DLY;
- end if;
- end process;
-
-
- tx_resetdone_sync <= TX_RESETDONE_IN;
-
- process (USER_CLK, tx_resetdone_sync)
- begin
- if (tx_resetdone_sync = '0') then
- gt_txresetdone_r <= '0' after DLY;
- gt_txresetdone_r2 <= '0' after DLY;
- elsif (USER_CLK 'event and USER_CLK = '1') then
- gt_txresetdone_r <= tx_resetdone_sync after DLY;
- gt_txresetdone_r2 <= gt_txresetdone_r after DLY;
- end if;
- end process;
-
- --FF for slack violations fix
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- gt_txresetdone_r3 <= gt_txresetdone_r2 after DLY;
- end if;
- end process;
-
-
- --This flop will pipeline wide-OR in case of multi-lane
- process(INIT_CLK_IN)
- begin
- if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
- link_reset_comb_r <= LINK_RESET_IN after DLY;
- end if;
- end process;
-
- link_reset_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => INIT_CLK_IN ,
- prmry_resetn => '1' ,
- prmry_in => link_reset_comb_r ,
- prmry_vect_in => "00" ,
- scndry_aclk => USER_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => link_reset_sync ,
- scndry_vect_out => open
- );
-
- pll_not_locked_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => INIT_CLK_IN ,
- prmry_resetn => '1' ,
- prmry_in => PLL_NOT_LOCKED ,
- prmry_vect_in => "00" ,
- scndry_aclk => USER_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll_not_locked_sync ,
- scndry_vect_out => open
- );
-
- --This flop will pipeline wide-OR in case of multi-lane
- process (INIT_CLK_IN)
- begin
- if (INIT_CLK_IN = '1' and INIT_CLK_IN'event) then
- tx_lock_comb_r <= TX_LOCK_IN after DLY;
- end if;
- end process;
-
-
- tx_lock_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => INIT_CLK_IN ,
- prmry_resetn => '1' ,
- prmry_in => tx_lock_comb_r ,
- prmry_vect_in => "00" ,
- scndry_aclk => USER_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => tx_lock_sync ,
- scndry_vect_out => open
- );
-
-process (USER_CLK)
-begin
- if (USER_CLK = '1' and USER_CLK'event) then
- SYSTEM_RESET <= (RESET or (not gt_rxresetdone_r3) or (not gt_txresetdone_r3)) or link_reset_sync or (not tx_lock_sync) or pll_not_locked_sync;
- end if;
-end process;
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll.vhd
deleted file mode 100644
index e1f2c03a7669121928e3893c766bfa347bbb98f7..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll.vhd
+++ /dev/null
@@ -1,366 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- RX_LL
---
---
---
--- Description: The RX_LL module receives data from the Aurora Channel,
--- converts it to LocalLink and sends it to the user interface.
--- It also handles NFC and UFC messages.
---
--- This module supports 2 4-byte lane designs.
---
--- This module supports User Flow Control.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity east_channel_RX_LL is
-
- port (
-
- -- LocalLink PDU Interface
-
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- -- Global Logic Interface
-
- START_RX : in std_logic;
-
- -- Aurora Lane Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
-end east_channel_RX_LL;
-
-architecture MAPPED of east_channel_RX_LL is
-
--- External Register Declarations --
-
-signal RX_D_Buffer : std_logic_vector(0 to 31);
-signal RX_REM_Buffer : std_logic_vector(0 to 1);
- signal RX_SRC_RDY_N_Buffer : std_logic;
- signal RX_SOF_N_Buffer : std_logic;
- signal RX_EOF_N_Buffer : std_logic;
-signal UFC_RX_DATA_Buffer : std_logic_vector(0 to 31);
-signal UFC_RX_REM_Buffer : std_logic_vector(0 to 1);
- signal UFC_RX_SRC_RDY_N_Buffer : std_logic;
- signal UFC_RX_SOF_N_Buffer : std_logic;
- signal UFC_RX_EOF_N_Buffer : std_logic;
- signal FRAME_ERR_Buffer : std_logic;
-
--- Wire Declarations --
-
-signal pdu_pad_i : std_logic_vector(0 to 1);
-signal pdu_data_i : std_logic_vector(0 to 31);
-signal pdu_data_v_i : std_logic_vector(0 to 1);
-signal pdu_scp_i : std_logic_vector(0 to 1);
-signal pdu_ecp_i : std_logic_vector(0 to 1);
-signal ufc_message_start_i : std_logic_vector(0 to 1);
-signal ufc_data_i : std_logic_vector(0 to 31);
-signal ufc_data_v_i : std_logic_vector(0 to 1);
- signal ufc_start_i : std_logic;
-
- signal start_rx_i : std_logic;
-
--- Component Declarations --
-
- component east_channel_UFC_FILTER
-
- port (
-
- -- Aurora Channel Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- PDU Datapath Interface
-
-PDU_DATA : out std_logic_vector(0 to 31);
-PDU_DATA_V : out std_logic_vector(0 to 1);
-PDU_PAD : out std_logic_vector(0 to 1);
-PDU_SCP : out std_logic_vector(0 to 1);
-PDU_ECP : out std_logic_vector(0 to 1);
-
- -- UFC Datapath Interface
-
-UFC_DATA : out std_logic_vector(0 to 31);
-UFC_DATA_V : out std_logic_vector(0 to 1);
-UFC_MESSAGE_START : out std_logic_vector(0 to 1);
- UFC_START : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_RX_LL_PDU_DATAPATH
-
- port (
-
- -- Traffic Separator Interface
-
-PDU_DATA : in std_logic_vector(0 to 31);
-PDU_DATA_V : in std_logic_vector(0 to 1);
-PDU_PAD : in std_logic_vector(0 to 1);
-PDU_SCP : in std_logic_vector(0 to 1);
-PDU_ECP : in std_logic_vector(0 to 1);
-
- -- LocalLink PDU Interface
-
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_RX_LL_UFC_DATAPATH
-
- port (
-
- --Traffic Separator Interface
-
-UFC_DATA : in std_logic_vector(0 to 31);
-UFC_DATA_V : in std_logic_vector(0 to 1);
-UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
-
- --LocalLink UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- --System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
-begin
-
- RX_D <= RX_D_Buffer;
- RX_REM <= RX_REM_Buffer;
- RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
- RX_SOF_N <= RX_SOF_N_Buffer;
- RX_EOF_N <= RX_EOF_N_Buffer;
- UFC_RX_DATA <= UFC_RX_DATA_Buffer;
- UFC_RX_REM <= UFC_RX_REM_Buffer;
- UFC_RX_SRC_RDY_N <= UFC_RX_SRC_RDY_N_Buffer;
- UFC_RX_SOF_N <= UFC_RX_SOF_N_Buffer;
- UFC_RX_EOF_N <= UFC_RX_EOF_N_Buffer;
- FRAME_ERR <= FRAME_ERR_Buffer;
-
- start_rx_i <= not START_RX;
-
--- Main Body of Code --
-
- -- Separate UFC traffic from regular data --
-
- ufc_filter_i : east_channel_UFC_FILTER
-
- port map (
-
- -- Aurora Channel Interface
-
- RX_PAD => RX_PAD,
- RX_PE_DATA => RX_PE_DATA,
- RX_PE_DATA_V => RX_PE_DATA_V,
- RX_SCP => RX_SCP,
- RX_ECP => RX_ECP,
- RX_SUF => RX_SUF,
- RX_FC_NB => RX_FC_NB,
-
- -- PDU Datapath Interface
-
- PDU_DATA => pdu_data_i,
- PDU_DATA_V => pdu_data_v_i,
- PDU_PAD => pdu_pad_i,
- PDU_SCP => pdu_scp_i,
- PDU_ECP => pdu_ecp_i,
-
- -- UFC Datapath Interface
-
- UFC_DATA => ufc_data_i,
- UFC_DATA_V => ufc_data_v_i,
- UFC_MESSAGE_START => ufc_message_start_i,
- UFC_START => ufc_start_i,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => start_rx_i
-
- );
-
-
- -- Datapath for user PDUs --
-
- rx_ll_pdu_datapath_i : east_channel_RX_LL_PDU_DATAPATH
-
- port map (
-
- -- Traffic Separator Interface
-
- PDU_DATA => pdu_data_i,
- PDU_DATA_V => pdu_data_v_i,
- PDU_PAD => pdu_pad_i,
- PDU_SCP => pdu_scp_i,
- PDU_ECP => pdu_ecp_i,
-
- -- LocalLink PDU Interface
-
- RX_D => RX_D_Buffer,
- RX_REM => RX_REM_Buffer,
- RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer,
- RX_SOF_N => RX_SOF_N_Buffer,
- RX_EOF_N => RX_EOF_N_Buffer,
-
- -- Error Interface
-
- FRAME_ERR => FRAME_ERR_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => start_rx_i
-
- );
-
-
- -- Datapath for UFC PDUs --
-
- rx_ll_ufc_datapath_i : east_channel_RX_LL_UFC_DATAPATH
-
- port map (
-
- -- Traffic Separator Interface
-
- UFC_DATA => ufc_data_i,
- UFC_DATA_V => ufc_data_v_i,
- UFC_MESSAGE_START => ufc_message_start_i,
- UFC_START => ufc_start_i,
-
- -- LocalLink PDU Interface
-
- UFC_RX_DATA => UFC_RX_DATA_Buffer,
- UFC_RX_REM => UFC_RX_REM_Buffer,
- UFC_RX_SRC_RDY_N => UFC_RX_SRC_RDY_N_Buffer,
- UFC_RX_SOF_N => UFC_RX_SOF_N_Buffer,
- UFC_RX_EOF_N => UFC_RX_EOF_N_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => start_rx_i
-
- );
-
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_deframer.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_deframer.vhd
deleted file mode 100644
index f179305739b4763baf17b9a13517b1aea52eb8c9..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_deframer.vhd
+++ /dev/null
@@ -1,297 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- RX_LL_DEFRAMER
---
---
---
--- Description: The RX_LL_DEFRAMER extracts framing information from incoming channel
--- data beats. It detects the start and end of frames, invalidates data
--- that is outside of a frame, and generates signals that go to the Output
--- and Storage blocks to indicate when the end of a frame has been detected.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-
-entity east_channel_RX_LL_DEFRAMER is
-
- port (
-
- PDU_DATA_V : in std_logic_vector(0 to 1);
- PDU_SCP : in std_logic_vector(0 to 1);
- PDU_ECP : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
- DEFRAMED_DATA_V : out std_logic_vector(0 to 1);
- IN_FRAME : out std_logic_vector(0 to 1);
- AFTER_SCP : out std_logic_vector(0 to 1)
-
- );
-
-end east_channel_RX_LL_DEFRAMER;
-
-architecture RTL of east_channel_RX_LL_DEFRAMER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal DEFRAMED_DATA_V_Buffer : std_logic_vector(0 to 1);
- signal IN_FRAME_Buffer : std_logic_vector(0 to 1);
- signal AFTER_SCP_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal in_frame_r : std_logic;
- signal tied_gnd : std_logic;
- signal tied_vcc : std_logic;
-
--- Wire Declarations --
-
- signal carry_select_c : std_logic_vector(0 to 1);
- signal after_scp_select_c : std_logic_vector(0 to 1);
- signal in_frame_c : std_logic_vector(0 to 1);
- signal after_scp_c : std_logic_vector(0 to 1);
-
- component MUXCY
-
- port (
-
- O : out std_logic;
- CI : in std_logic;
- DI : in std_logic;
- S : in std_logic
-
- );
-
- end component;
-
-begin
-
- DEFRAMED_DATA_V <= DEFRAMED_DATA_V_Buffer;
- IN_FRAME <= IN_FRAME_Buffer;
- AFTER_SCP <= AFTER_SCP_Buffer;
-
- tied_gnd <= '0';
- tied_vcc <= '1';
-
--- Main Body of Code --
-
- -- Mask Invalid data --
-
- -- Keep track of inframe status between clock cycles.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(RESET = '1') then
-
- in_frame_r <= '0' after DLY;
-
- else
-
- in_frame_r <= in_frame_c(1) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Combinatorial inframe detect for lane 0.
-
- carry_select_c(0) <= not PDU_ECP(0) and not PDU_SCP(0);
-
- in_frame_muxcy_0 : MUXCY
-
- port map (
-
- O => in_frame_c(0),
- CI => in_frame_r,
- DI => PDU_SCP(0),
- S => carry_select_c(0)
-
- );
-
-
- -- Combinatorial inframe detect for 2-byte chunk 1.
-
- carry_select_c(1) <= not PDU_ECP(1) and not PDU_SCP(1);
-
- in_frame_muxcy_1 : MUXCY
-
- port map (
-
- O => in_frame_c(1),
- CI => in_frame_c(0),
- DI => PDU_SCP(1),
- S => carry_select_c(1)
-
- );
-
-
- -- The data from a lane is valid if its valid signal is asserted and it is
- -- inside a frame. Note the use of Bitwise AND.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- DEFRAMED_DATA_V_Buffer <= (others => '0') after DLY;
-
- else
-
- DEFRAMED_DATA_V_Buffer <= (in_frame_c and PDU_DATA_V) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Register the inframe status.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- IN_FRAME_Buffer <= conv_std_logic_vector(0,2) after DLY;
-
- else
-
- IN_FRAME_Buffer <= in_frame_r & in_frame_c(0 to 0) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Mark lanes that could contain data that occurs after an SCP. --
-
- -- Combinatorial data after start detect for lane 0.
-
- after_scp_select_c(0) <= not PDU_SCP(0);
-
- data_after_start_muxcy_0:MUXCY
-
- port map (
-
- O => after_scp_c(0),
- CI => tied_gnd,
- DI => tied_vcc,
- S => after_scp_select_c(0)
-
- );
-
-
- -- Combinatorial data after start detect for lane1.
-
- after_scp_select_c(1) <= not PDU_SCP(1);
-
- data_after_start_muxcy_1:MUXCY
-
- port map (
-
- O => after_scp_c(1),
- CI => after_scp_c(0),
- DI => tied_vcc,
- S => after_scp_select_c(1)
- );
-
-
- -- Register the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- AFTER_SCP_Buffer <= (others => '0');
-
- else
-
- AFTER_SCP_Buffer <= after_scp_c;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_pdu_datapath.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_pdu_datapath.vhd
deleted file mode 100644
index 09666693ab85e5773a469fcb9c8dc3c7bdfcb717..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_pdu_datapath.vhd
+++ /dev/null
@@ -1,712 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
---
--- RX_LL_PDU_DATAPATH
---
---
--- Description: the RX_LL_PDU_DATAPATH module takes regular PDU data in Aurora format
--- and transforms it to LocalLink formatted data
---
--- This module supports 2 4-byte lane designs
---
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_RX_LL_PDU_DATAPATH is
-
- port (
-
- -- Traffic Separator Interface
-
-PDU_DATA : in std_logic_vector(0 to 31);
-PDU_DATA_V : in std_logic_vector(0 to 1);
-PDU_PAD : in std_logic_vector(0 to 1);
-PDU_SCP : in std_logic_vector(0 to 1);
-PDU_ECP : in std_logic_vector(0 to 1);
-
- -- LocalLink PDU Interface
-
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_RX_LL_PDU_DATAPATH;
-
-
-architecture RTL of east_channel_RX_LL_PDU_DATAPATH is
-
---****************************Parameter Declarations**************************
-
- constant DLY : time := 1 ns;
-
-
---****************************External Register Declarations**************************
-
-signal RX_D_Buffer : std_logic_vector(0 to 31);
-signal RX_REM_Buffer : std_logic_vector(0 to 1);
- signal RX_SRC_RDY_N_Buffer : std_logic;
- signal RX_SOF_N_Buffer : std_logic;
- signal RX_EOF_N_Buffer : std_logic;
- signal FRAME_ERR_Buffer : std_logic;
-
-
---****************************Internal Register Declarations**************************
- --Stage 1
- signal stage_1_data_r : std_logic_vector(0 to 31);
- signal stage_1_pad_r : std_logic;
- signal stage_1_ecp_r : std_logic_vector(0 to 1);
- signal stage_1_scp_r : std_logic_vector(0 to 1);
- signal stage_1_start_detected_r : std_logic;
-
-
- --Stage 2
- signal stage_2_data_r : std_logic_vector(0 to 31);
- signal stage_2_pad_r : std_logic;
- signal stage_2_start_with_data_r : std_logic;
- signal stage_2_end_before_start_r : std_logic;
- signal stage_2_end_after_start_r : std_logic;
- signal stage_2_start_detected_r : std_logic;
- signal stage_2_frame_err_r : std_logic;
-
-
-
-
-
-
-
---*********************************Wire Declarations**********************************
- --Stage 1
- signal stage_1_data_v_r : std_logic_vector(0 to 1);
- signal stage_1_after_scp_r : std_logic_vector(0 to 1);
- signal stage_1_in_frame_r : std_logic_vector(0 to 1);
-
- --Stage 2
- signal stage_2_left_align_select_r : std_logic_vector(0 to 5);
- signal stage_2_data_v_r : std_logic_vector(0 to 1);
-
- signal stage_2_data_v_count_r : std_logic_vector(0 to 1);
- signal stage_2_frame_err_c : std_logic;
-
- --Stage 3
- signal stage_3_data_r : std_logic_vector(0 to 31);
-
-
-
- signal stage_3_storage_count_r : std_logic_vector(0 to 1);
- signal stage_3_storage_ce_r : std_logic_vector(0 to 1);
- signal stage_3_end_storage_r : std_logic;
- signal stage_3_storage_select_r : std_logic_vector(0 to 9);
- signal stage_3_output_select_r : std_logic_vector(0 to 9);
- signal stage_3_src_rdy_n_r : std_logic;
- signal stage_3_sof_n_r : std_logic;
- signal stage_3_eof_n_r : std_logic;
- signal stage_3_rem_r : std_logic_vector(0 to 1);
- signal stage_3_frame_err_r : std_logic;
-
-
-
- --Stage 4
- signal storage_data_r : std_logic_vector(0 to 31);
-
-
-
--- ********************************** Component Declarations ************************************--
-
- component east_channel_RX_LL_DEFRAMER
- port (
- PDU_DATA_V : in std_logic_vector(0 to 1);
- PDU_SCP : in std_logic_vector(0 to 1);
- PDU_ECP : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- DEFRAMED_DATA_V : out std_logic_vector(0 to 1);
- IN_FRAME : out std_logic_vector(0 to 1);
- AFTER_SCP : out std_logic_vector(0 to 1)
- );
- end component;
-
-
- component east_channel_LEFT_ALIGN_CONTROL
- port (
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
-
- MUX_SELECT : out std_logic_vector(0 to 5);
- VALID : out std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
- end component;
-
-
- component east_channel_VALID_DATA_COUNTER
- port (
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- COUNT : out std_logic_vector(0 to 1)
- );
- end component;
-
-
- component east_channel_LEFT_ALIGN_MUX
- port (
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
-
- USER_CLK : in std_logic;
-
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
- end component;
-
-
- component east_channel_STORAGE_COUNT_CONTROL
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- FRAME_ERR : in std_logic;
-
- STORAGE_COUNT : out std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic
- );
- end component;
-
-
- component east_channel_STORAGE_CE_CONTROL
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
-
- STORAGE_CE : out std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic
- );
- end component;
-
-
- component east_channel_STORAGE_SWITCH_CONTROL
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
-
- STORAGE_SELECT : out std_logic_vector(0 to 9);
-
- USER_CLK : in std_logic
- );
- end component;
-
-
- component east_channel_OUTPUT_SWITCH_CONTROL
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
-
- OUTPUT_SELECT : out std_logic_vector(0 to 9);
-
- USER_CLK : in std_logic
- );
- end component;
-
-
- component east_channel_SIDEBAND_OUTPUT
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_BEFORE_START : in std_logic;
- END_AFTER_START : in std_logic;
- START_DETECTED : in std_logic;
- START_WITH_DATA : in std_logic;
- PAD : in std_logic;
- FRAME_ERR : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- END_STORAGE : out std_logic;
- SRC_RDY_N : out std_logic;
- SOF_N : out std_logic;
- EOF_N : out std_logic;
- RX_REM : out std_logic_vector(0 to 1);
- FRAME_ERR_RESULT : out std_logic
- );
- end component;
-
-
- component east_channel_STORAGE_MUX
- port (
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- STORAGE_CE : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
-
- STORAGE_DATA : out std_logic_vector(0 to 31)
- );
- end component;
-
-
- component east_channel_OUTPUT_MUX
- port (
- STORAGE_DATA : in std_logic_vector(0 to 31);
- LEFT_ALIGNED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- USER_CLK : in std_logic;
-
- OUTPUT_DATA : out std_logic_vector(0 to 31)
- );
- end component;
-
-
-begin
-
---*********************************Main Body of Code**********************************
-
- -- VHDL Helper Logic
- RX_D <= RX_D_Buffer;
- RX_REM <= RX_REM_Buffer;
- RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
- RX_SOF_N <= RX_SOF_N_Buffer;
- RX_EOF_N <= RX_EOF_N_Buffer;
- FRAME_ERR <= FRAME_ERR_Buffer;
-
-
-
-
- --_____Stage 1: Decode Frame Encapsulation and remove unframed data ________
-
-
- stage_1_rx_ll_deframer_i : east_channel_RX_LL_DEFRAMER
- port map
- (
- PDU_DATA_V => PDU_DATA_V,
- PDU_SCP => PDU_SCP,
- PDU_ECP => PDU_ECP,
- USER_CLK => USER_CLK,
- RESET => RESET,
-
- DEFRAMED_DATA_V => stage_1_data_v_r,
- IN_FRAME => stage_1_in_frame_r,
- AFTER_SCP => stage_1_after_scp_r
-
- );
-
-
- --Determine whether there were any SCPs detected, regardless of data
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_1_start_detected_r <= '0' after DLY;
- else
-stage_1_start_detected_r <= std_bool(PDU_SCP /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
- --Pipeline the data signal, and register a signal to indicate whether the data in
- -- the current cycle contained a Pad character.
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- stage_1_data_r <= PDU_DATA after DLY;
-stage_1_pad_r <= std_bool(PDU_PAD /= "00") after DLY;
- stage_1_ecp_r <= PDU_ECP after DLY;
- stage_1_scp_r <= PDU_SCP after DLY;
- end if;
- end process;
-
-
-
- --_______________________Stage 2: First Control Stage ___________________________
-
-
- --We instantiate a LEFT_ALIGN_CONTROL module to drive the select signals for the
- --left align mux in the next stage, and to compute the next stage valid signals
-
- stage_2_left_align_control_i : east_channel_LEFT_ALIGN_CONTROL
- port map(
- PREVIOUS_STAGE_VALID => stage_1_data_v_r,
-
- MUX_SELECT => stage_2_left_align_select_r,
- VALID => stage_2_data_v_r,
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
-
- --Count the number of valid data lanes: this count is used to select which data
- -- is stored and which data is sent to output in later stages
- stage_2_valid_data_counter_i : east_channel_VALID_DATA_COUNTER
- port map(
- PREVIOUS_STAGE_VALID => stage_1_data_v_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
-
- COUNT => stage_2_data_v_count_r
- );
-
-
-
- --Pipeline the data and pad bits
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- stage_2_data_r <= stage_1_data_r after DLY;
- stage_2_pad_r <= stage_1_pad_r after DLY;
- end if;
- end process;
-
-
-
-
- --Determine whether there was any valid data after any SCP characters
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_start_with_data_r <= '0' after DLY;
- else
-stage_2_start_with_data_r <= std_bool((stage_1_data_v_r and stage_1_after_scp_r) /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
-
- --Determine whether there were any ECPs detected before any SPC characters
- -- arrived
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_end_before_start_r <= '0' after DLY;
- else
-stage_2_end_before_start_r <= std_bool((stage_1_ecp_r and not stage_1_after_scp_r) /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
- --Determine whether there were any ECPs detected at all
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_end_after_start_r <= '0' after DLY;
- else
-stage_2_end_after_start_r <= std_bool((stage_1_ecp_r and stage_1_after_scp_r) /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
- --Pipeline the SCP detected signal
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_start_detected_r <= '0' after DLY;
- else
- stage_2_start_detected_r <= stage_1_start_detected_r after DLY;
- end if;
- end if;
- end process;
-
-
-
- --Detect frame errors. Note that the frame error signal is held until the start of
- -- a frame following the data beat that caused the frame error
-stage_2_frame_err_c <= std_bool( (stage_1_ecp_r and not stage_1_in_frame_r) /= "00" ) or
-std_bool( (stage_1_scp_r and stage_1_in_frame_r) /= "00" );
-
-
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_frame_err_r <= '0' after DLY;
- elsif(stage_2_frame_err_c = '1') then
- stage_2_frame_err_r <= '1' after DLY;
- elsif((stage_1_start_detected_r or stage_2_frame_err_r) = '1') then
- stage_2_frame_err_r <= '0' after DLY;
- end if;
- end if;
- end process;
-
-
-
-
-
-
-
- --_______________________________ Stage 3 Left Alignment _________________________
-
-
- --We instantiate a left align mux to shift all lanes with valid data in the channel leftward
- --The data is seperated into groups of 8 lanes, and all valid data within each group is left
- --aligned.
- stage_3_left_align_datapath_mux_i : east_channel_LEFT_ALIGN_MUX
- port map(
- RAW_DATA => stage_2_data_r,
- MUX_SELECT => stage_2_left_align_select_r,
- USER_CLK => USER_CLK,
-
- MUXED_DATA => stage_3_data_r
- );
-
-
-
-
-
-
-
- --Determine the number of valid data lanes that will be in storage on the next cycle
- stage_3_storage_count_control_i : east_channel_STORAGE_COUNT_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
- FRAME_ERR => stage_2_frame_err_r,
-
- STORAGE_COUNT => stage_3_storage_count_r,
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
-
- --Determine the CE settings for the storage module for the next cycle
- stage_3_storage_ce_control_i : east_channel_STORAGE_CE_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
-
- STORAGE_CE => stage_3_storage_ce_r,
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
-
- --Determine the appropriate switch settings for the storage module for the next cycle
- stage_3_storage_switch_control_i : east_channel_STORAGE_SWITCH_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
-
- STORAGE_SELECT => stage_3_storage_select_r,
-
- USER_CLK => USER_CLK
-
- );
-
-
-
- --Determine the appropriate switch settings for the output module for the next cycle
- stage_3_output_switch_control_i : east_channel_OUTPUT_SWITCH_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
-
- OUTPUT_SELECT => stage_3_output_select_r,
-
- USER_CLK => USER_CLK
-
- );
-
-
- --Instantiate a sideband output controller
- sideband_output_i : east_channel_SIDEBAND_OUTPUT
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_BEFORE_START => stage_2_end_before_start_r,
- END_AFTER_START => stage_2_end_after_start_r,
- START_DETECTED => stage_2_start_detected_r,
- START_WITH_DATA => stage_2_start_with_data_r,
- PAD => stage_2_pad_r,
- FRAME_ERR => stage_2_frame_err_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
-
- END_STORAGE => stage_3_end_storage_r,
- SRC_RDY_N => stage_3_src_rdy_n_r,
- SOF_N => stage_3_sof_n_r,
- EOF_N => stage_3_eof_n_r,
- RX_REM => stage_3_rem_r,
- FRAME_ERR_RESULT => stage_3_frame_err_r
- );
-
-
-
-
-
- --________________________________ Stage 4: Storage and Output_______________________
-
-
- --Storage: Data is moved to storage when it cannot be sent directly to the output.
-
- stage_4_storage_mux_i : east_channel_STORAGE_MUX
- port map(
- RAW_DATA => stage_3_data_r,
- MUX_SELECT => stage_3_storage_select_r,
- STORAGE_CE => stage_3_storage_ce_r,
- USER_CLK => USER_CLK,
-
- STORAGE_DATA => storage_data_r
-
- );
-
-
-
- --Output: Data is moved to the locallink output when a full word of valid data is ready,
- -- or the end of a frame is reached
-
- output_mux_i : east_channel_OUTPUT_MUX
- port map(
- STORAGE_DATA => storage_data_r,
- LEFT_ALIGNED_DATA => stage_3_data_r,
- MUX_SELECT => stage_3_output_select_r,
- USER_CLK => USER_CLK,
-
- OUTPUT_DATA => RX_D_Buffer
-
- );
-
-
- --Pipeline LocalLink sideband signals
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- RX_SOF_N_Buffer <= stage_3_sof_n_r after DLY;
- RX_EOF_N_Buffer <= stage_3_eof_n_r after DLY;
- RX_REM_Buffer <= stage_3_rem_r after DLY;
- end if;
- end process;
-
-
- --Pipeline the LocalLink source Ready signal
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- RX_SRC_RDY_N_Buffer <= '1' after DLY;
- else
- RX_SRC_RDY_N_Buffer <= stage_3_src_rdy_n_r after DLY;
- end if;
- end if;
- end process;
-
-
-
- --Pipeline the Frame error signal
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- FRAME_ERR_Buffer <= '0' after DLY;
- else
- FRAME_ERR_Buffer <= stage_3_frame_err_r after DLY;
- end if;
- end if;
- end process;
-
-
-
-end RTL;
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_ufc_datapath.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_ufc_datapath.vhd
deleted file mode 100644
index 9aba7ea2a1d9b699cf2e665473e1b1e06cd92fe6..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_rx_ll_ufc_datapath.vhd
+++ /dev/null
@@ -1,507 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- RX_LL_UFC_DATAPATH
---
---
---
--- Description: the RX_LL_UFC_DATAPATH module takes UFC data in Aurora format
--- and transforms it to LocalLink formatted data
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_RX_LL_UFC_DATAPATH is
-
- port (
-
- --Traffic Separator Interface
-
-UFC_DATA : in std_logic_vector(0 to 31);
-UFC_DATA_V : in std_logic_vector(0 to 1);
-UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
-
- --LocalLink UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- --System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_RX_LL_UFC_DATAPATH;
-
-architecture RTL of east_channel_RX_LL_UFC_DATAPATH is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
-signal UFC_RX_DATA_Buffer : std_logic_vector(0 to 31);
-signal UFC_RX_REM_Buffer : std_logic_vector(0 to 1);
- signal UFC_RX_SRC_RDY_N_Buffer : std_logic;
- signal UFC_RX_SOF_N_Buffer : std_logic;
- signal UFC_RX_EOF_N_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- -- Stage 1
-
- signal stage_1_data_r : std_logic_vector(0 to 31);
- signal stage_1_ufc_start_r : std_logic;
-
- -- Stage 1
-
- signal barrel_shifter_control_r : std_logic_vector(0 to 1);
- signal barrel_shifted_count_r : std_logic_vector(0 to 1);
-
- -- Stage 2
-
- signal barrel_shifted_data_r : std_logic_vector(0 to 31);
- signal ufc_storage_count_r : std_logic_vector(0 to 1);
- signal ufc_storage_select_r : std_logic_vector(0 to 5);
- signal ufc_output_select_r : std_logic_vector(0 to 5);
- signal stage_2_ufc_src_rdy_n_r : std_logic;
- signal stage_2_ufc_sof_n_r : std_logic;
- signal stage_2_ufc_eof_n_r : std_logic;
- signal stage_2_ufc_rem_r : std_logic_vector(0 to 1);
-
- -- Stage 3
-
- signal ufc_storage_data_r : std_logic_vector(0 to 31);
-
-
--- Component Declarations
-
- component east_channel_UFC_BARREL_SHIFTER_CONTROL
-
- port (
-
- UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- BARREL_SHIFTER_CONTROL : out std_logic_vector(0 to 1)
-
- );
-
- end component;
-
-
- component east_channel_VALID_DATA_COUNTER
-
- port (
-
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
- COUNT : out std_logic_vector(0 to 1)
- );
-
- end component;
-
-
- component east_channel_UFC_BARREL_SHIFTER
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTER_CONTROL : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- -- Mux output
-
- SHIFTED_DATA : out std_logic_vector(0 to 31)
-
- );
-
- end component;
-
-
- component east_channel_UFC_STORAGE_COUNT_CONTROL
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- UFC_STORAGE_COUNT : out std_logic_vector(0 to 1)
-
- );
-
- end component;
-
-
- component east_channel_UFC_STORAGE_SWITCH_CONTROL
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- UFC_STORAGE_SELECT : out std_logic_vector(0 to 5)
-
- );
-
- end component;
-
-
- component east_channel_UFC_OUTPUT_SWITCH_CONTROL
-
- port (
-
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- UFC_OUTPUT_SELECT : out std_logic_vector(0 to 5)
-
- );
-
- end component;
-
-
- component east_channel_UFC_SIDEBAND_OUTPUT
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- UFC_SRC_RDY_N : out std_logic;
- UFC_SOF_N : out std_logic;
- UFC_EOF_N : out std_logic;
- UFC_REM : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_UFC_STORAGE_MUX
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
-
- -- Mux output
-
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
- end component;
-
-
- component east_channel_UFC_OUTPUT_MUX
-
- port (
-
- -- Input interface to the muxes
-
- UFC_STORAGE_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
- end component;
-
-begin
-
- UFC_RX_DATA <= UFC_RX_DATA_Buffer;
- UFC_RX_REM <= UFC_RX_REM_Buffer;
- UFC_RX_SRC_RDY_N <= UFC_RX_SRC_RDY_N_Buffer;
- UFC_RX_SOF_N <= UFC_RX_SOF_N_Buffer;
- UFC_RX_EOF_N <= UFC_RX_EOF_N_Buffer;
-
--- Main Body of Code --
-
- -- Stage 1: Shifter Control and Count --
-
- -- Instantiate a barrel shifter control module.
-
- ufc_barrel_shifter_control_i : east_channel_UFC_BARREL_SHIFTER_CONTROL
-
- port map (
-
- UFC_MESSAGE_START => UFC_MESSAGE_START,
- USER_CLK => USER_CLK,
- BARREL_SHIFTER_CONTROL => barrel_shifter_control_r
-
- );
-
-
- -- Instantiate a Valid Data counter to count the number of valid UFC data lanes
- -- that will be barrel-shifted in the cycle.
-
- ufc_valid_data_counter : east_channel_VALID_DATA_COUNTER
-
- port map (
-
- PREVIOUS_STAGE_VALID => UFC_DATA_V,
- USER_CLK => USER_CLK,
- RESET => RESET,
- COUNT => barrel_shifted_count_r
-
- );
-
-
- -- Pipeline the data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- stage_1_data_r <= UFC_DATA after DLY;
-
- end if;
-
- end process;
-
-
- -- Pipeline the UFC_START signal.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_1_ufc_start_r <= '0' after DLY;
-
- else
-
- stage_1_ufc_start_r <= UFC_START after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Stage 2: Barrel Shifter, control for storage and output --
-
- -- Instantiate a barrel shifter for the UFC data.
-
- ufc_barrel_shifter_i : east_channel_UFC_BARREL_SHIFTER
-
- port map (
-
- RAW_DATA => stage_1_data_r,
- BARREL_SHIFTER_CONTROL => barrel_shifter_control_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
- SHIFTED_DATA => barrel_shifted_data_r
-
- );
-
-
- -- Instantiate a ufc_storage_count controller.
-
- ufc_storage_count_control_i : east_channel_UFC_STORAGE_COUNT_CONTROL
-
- port map (
-
- BARREL_SHIFTED_COUNT => barrel_shifted_count_r,
- UFC_START => stage_1_ufc_start_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
- UFC_STORAGE_COUNT => ufc_storage_count_r
-
- );
-
-
- -- Instantiate a control module for the storage switch.
-
- ufc_storage_switch_control_i : east_channel_UFC_STORAGE_SWITCH_CONTROL
-
- port map (
-
- BARREL_SHIFTED_COUNT => barrel_shifted_count_r,
- UFC_STORAGE_COUNT => ufc_storage_count_r,
- UFC_START => stage_1_ufc_start_r,
- USER_CLK => USER_CLK,
- UFC_STORAGE_SELECT => ufc_storage_select_r
-
- );
-
-
- -- Instantiate a control module for the output switch.
-
- ufc_output_switch_control_i:east_channel_UFC_OUTPUT_SWITCH_CONTROL
-
- port map (
-
- UFC_STORAGE_COUNT => ufc_storage_count_r,
- USER_CLK => USER_CLK,
- UFC_OUTPUT_SELECT => ufc_output_select_r
-
- );
-
-
- -- Instantiate a control module for the sideband signals.
-
- ufc_sideband_output_i : east_channel_UFC_SIDEBAND_OUTPUT
-
- port map (
-
- BARREL_SHIFTED_COUNT => barrel_shifted_count_r,
- UFC_STORAGE_COUNT => ufc_storage_count_r,
- UFC_START => stage_1_ufc_start_r,
- UFC_SRC_RDY_N => stage_2_ufc_src_rdy_n_r,
- UFC_SOF_N => stage_2_ufc_sof_n_r,
- UFC_EOF_N => stage_2_ufc_eof_n_r,
- UFC_REM => stage_2_ufc_rem_r,
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
- -- Stage 3:Storage and Output --
-
- -- Instantiate the storage mux.
-
- ufc_storage_mux_i : east_channel_UFC_STORAGE_MUX
-
- port map (
-
- RAW_DATA => barrel_shifted_data_r,
- MUX_SELECT => ufc_storage_select_r,
- USER_CLK => USER_CLK,
- MUXED_DATA => ufc_storage_data_r
-
- );
-
-
- -- Instantiate the output mux.
-
- ufc_output_mux_i : east_channel_UFC_OUTPUT_MUX
-
- port map (
-
- UFC_STORAGE_DATA => ufc_storage_data_r,
- BARREL_SHIFTED_DATA => barrel_shifted_data_r,
- MUX_SELECT => ufc_output_select_r,
- USER_CLK => USER_CLK,
- MUXED_DATA => UFC_RX_DATA_Buffer
-
- );
-
-
- -- Pipeline the LocalLink SRC_RDY_N output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_RX_SRC_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- UFC_RX_SRC_RDY_N_Buffer <= stage_2_ufc_src_rdy_n_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the remaining LocalLink signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_RX_SOF_N_Buffer <= stage_2_ufc_sof_n_r after DLY;
- UFC_RX_EOF_N_Buffer <= stage_2_ufc_eof_n_r after DLY;
- UFC_RX_REM_Buffer <= stage_2_ufc_rem_r after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_scrambler.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_scrambler.vhd
deleted file mode 100644
index b2e8fa39bc54b06f17e5cd13fcb17fa0467b99b1..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_scrambler.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
-
---***************************** Module Declaration ****************************
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity east_channel_SCRAMBLER is
-
-generic
-(
- C_SEED : std_logic_vector := X"FFFF"
-);
-port
-(
- DOUT : out std_logic_vector(15 downto 0) := X"0000";
-
- DIN : in std_logic_vector(15 downto 0);
- BYPASS : in std_logic;
- EN : in std_logic;
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- CLK : in std_logic
-);
-
-end east_channel_SCRAMBLER;
-
-architecture BEHAVIORAL of east_channel_SCRAMBLER is
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
---**************************************Signal Declarations***************************
-
- signal dataNext : std_logic_vector(15 downto 0);
- signal lfsrNext : std_logic_vector(15 downto 0);
- signal lfsr : std_logic_vector(15 downto 0) :=X"0000";
- signal dout_temp : std_logic_vector(15 downto 0);
-
-begin
-
---*********************************Main Body of Code**********************************
-
- dout_temp <= DIN when (BYPASS = '1') else
- dataNext;
-
- -----------------------------------------------------------------------------
- -- Scrambler / De-Scrambler Register
- -----------------------------------------------------------------------------
- process(CLK)
- begin
- if(CLK'event and CLK='1') then
- if(EN = '1') then
- DOUT <= dout_temp after DLY;
- end if;
- end if;
- end process;
-
- -----------------------------------------------------------------------------
- -- 16-bit LFSR
- -----------------------------------------------------------------------------
- process(CLK)
- begin
- if(CLK'event and CLK='1') then
- if((RESET OR CLEAR)= '1') then
- lfsr <= C_SEED;
- elsif(EN = '1') then
- lfsr <= lfsrNext;
- end if;
- end if;
- end process;
-
- -----------------------------------------------------------------------------
- -- LFSR XORs
- -----------------------------------------------------------------------------
- lfsrNext(0) <= lfsr(8) ;
- lfsrNext(1) <= lfsr(9) ;
- lfsrNext(2) <= lfsr(10) ;
- lfsrNext(3) <= lfsr(8) XOR lfsr(11) ;
- lfsrNext(4) <= lfsr(8) XOR lfsr(9) XOR lfsr(12) ;
- lfsrNext(5) <= lfsr(8) XOR lfsr(9) XOR lfsr(10) XOR lfsr(13) ;
- lfsrNext(6) <= lfsr(9) XOR lfsr(10) XOR lfsr(11) XOR lfsr(14) ;
- lfsrNext(7) <= lfsr(10) XOR lfsr(11) XOR lfsr(12) XOR lfsr(15) ;
- lfsrNext(8) <= lfsr(0) XOR lfsr(11) XOR lfsr(12) XOR lfsr(13) ;
- lfsrNext(9) <= lfsr(1) XOR lfsr(12) XOR lfsr(13) XOR lfsr(14) ;
- lfsrNext(10) <= lfsr(2) XOR lfsr(13) XOR lfsr(14) XOR lfsr(15) ;
- lfsrNext(11) <= lfsr(3) XOR lfsr(14) XOR lfsr(15) ;
- lfsrNext(12) <= lfsr(4) XOR lfsr(15) ;
- lfsrNext(13) <= lfsr(5) ;
- lfsrNext(14) <= lfsr(6) ;
- lfsrNext(15) <= lfsr(7) ;
-
- -----------------------------------------------------------------------------
- -- Additive Scrambler / De-Scrambler XORs
- -----------------------------------------------------------------------------
- dataNext(0) <= EN AND (DIN(0) XOR lfsr(15)) ;
- dataNext(1) <= EN AND (DIN(1) XOR lfsr(14)) ;
- dataNext(2) <= EN AND (DIN(2) XOR lfsr(13)) ;
- dataNext(3) <= EN AND (DIN(3) XOR lfsr(12)) ;
- dataNext(4) <= EN AND (DIN(4) XOR lfsr(11)) ;
- dataNext(5) <= EN AND (DIN(5) XOR lfsr(10)) ;
- dataNext(6) <= EN AND (DIN(6) XOR lfsr(9)) ;
- dataNext(7) <= EN AND (DIN(7) XOR lfsr(8)) ;
- dataNext(8) <= EN AND (DIN(8) XOR lfsr(7)) ;
- dataNext(9) <= EN AND (DIN(9) XOR lfsr(6)) ;
- dataNext(10) <= EN AND (DIN(10) XOR lfsr(5)) ;
- dataNext(11) <= EN AND (DIN(11) XOR lfsr(4)) ;
- dataNext(12) <= EN AND (DIN(12) XOR lfsr(3)) ;
- dataNext(13) <= EN AND (DIN(13) XOR lfsr(2)) ;
- dataNext(14) <= EN AND (DIN(14) XOR lfsr(1)) ;
- dataNext(15) <= EN AND (DIN(15) XOR lfsr(0)) ;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_scrambler_top.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_scrambler_top.vhd
deleted file mode 100644
index f8d492dd37be7982ae2c2a1abf59c9c4a56dd8a2..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_scrambler_top.vhd
+++ /dev/null
@@ -1,213 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
-
---***************************** Module Declaration ****************************
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-
-entity east_channel_SCRAMBLER_TOP is
-
-port
-(
- DATA_OUT : out std_logic_vector(31 downto 0);
- CHAR_IS_K_OUT : out std_logic_vector(3 downto 0);
-
- DATA : in std_logic_vector(31 downto 0);
- CHAR_IS_K : in std_logic_vector(3 downto 0);
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- USER_CLK : in std_logic
-);
-
-end east_channel_SCRAMBLER_TOP;
-
-architecture BEHAVIORAL of east_channel_SCRAMBLER_TOP is
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
---**************************************Signal Declarations***************************
-
- signal en_scrambler : std_logic_vector(1 downto 0);
- signal bypass_w : std_logic_vector(1 downto 0);
- signal bypass_r : std_logic_vector(1 downto 0);
- signal seed_lfsr : std_logic;
- signal user_data : std_logic_vector(31 downto 0);
- signal scrambled_data : std_logic_vector(31 downto 0);
- signal clear_nxt : std_logic;
- signal clear_nxt2 : std_logic;
- signal data_nxt : std_logic_vector(31 downto 0);
-
- component east_channel_SCRAMBLER is
-
- generic
- (
- C_SEED : std_logic_vector := X"FFFF"
- );
-
- port
- (
- DOUT : out std_logic_vector(15 downto 0);
-
- DIN : in std_logic_vector(15 downto 0);
- BYPASS : in std_logic;
- EN : in std_logic;
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- CLK : in std_logic
- );
-
- end component;
-
-
-begin
-
---*********************************Main Body of Code**********************************
-
- -- data pipeline
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- data_nxt <= DATA after DLY;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- bypass_r <= bypass_w after DLY;
- end if;
- end process;
-
- -- register clear to reset scrambler when CC is being sent from SYM_GEN
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- clear_nxt <= CLEAR after DLY;
- clear_nxt2 <= clear_nxt after DLY;
- end if;
- end process;
-
- seed_lfsr <= clear_nxt2;
-
- bypass_w(0) <= '1' when (RESET = '1') else
- '1' when ((OR_REDUCE(CHAR_IS_K(1 downto 0))) = '1') else
- '0';
-
- bypass_w(1) <= '1' when (RESET = '1') else
- '1' when ((OR_REDUCE(CHAR_IS_K(3 downto 2))) = '1') else
- '0';
-
- user_data(15 downto 0) <= X"0000" when (bypass_w(0) = '1') else
- DATA(15 downto 0);
-
- user_data(31 downto 16) <= X"0000" when (bypass_w(1) = '1') else
- DATA(31 downto 16);
-
- en_scrambler(0) <= NOT bypass_w(0);
-
- en_scrambler(1) <= NOT bypass_w(1);
-
- east_channel_scrambler0_i : east_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(15 downto 0),
- DIN => user_data(15 downto 0),
- EN => en_scrambler(0),
- BYPASS => bypass_w(0),
- CLEAR => seed_lfsr,
- RESET => RESET,
- CLK => USER_CLK
- );
-
- east_channel_scrambler1_i : east_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(31 downto 16),
- DIN => user_data(31 downto 16),
- EN => en_scrambler(1),
- BYPASS => bypass_w(1),
- CLEAR => seed_lfsr,
- RESET => RESET,
- CLK => USER_CLK
- );
-
- -- Outputs
-
- DATA_OUT(15 downto 0) <= data_nxt(15 downto 0) when (bypass_r(0) = '1') else
- scrambled_data(15 downto 0);
-
- DATA_OUT(31 downto 16) <= data_nxt(31 downto 16) when (bypass_r(1) = '1') else
- scrambled_data(31 downto 16);
-
- -- CHAR_IS_K pipeline
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- CHAR_IS_K_OUT <= CHAR_IS_K after DLY;
- end if;
- end process;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sideband_output.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sideband_output.vhd
deleted file mode 100644
index cd3e83f7a576926700de2cb7ddbd89e40c33d78d..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sideband_output.vhd
+++ /dev/null
@@ -1,439 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- SIDEBAND_OUTPUT
---
---
--- Description: SIDEBAND_OUTPUT generates the SRC_RDY_N, EOF_N, SOF_N and
--- RX_REM signals for the RX localLink interface.
---
--- This module supports 2 4-byte lane designs.
---
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_SIDEBAND_OUTPUT is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_BEFORE_START : in std_logic;
- END_AFTER_START : in std_logic;
- START_DETECTED : in std_logic;
- START_WITH_DATA : in std_logic;
- PAD : in std_logic;
- FRAME_ERR : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- END_STORAGE : out std_logic;
- SRC_RDY_N : out std_logic;
- SOF_N : out std_logic;
- EOF_N : out std_logic;
- RX_REM : out std_logic_vector(0 to 1);
- FRAME_ERR_RESULT : out std_logic
-
- );
-
-end east_channel_SIDEBAND_OUTPUT;
-
-architecture RTL of east_channel_SIDEBAND_OUTPUT is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal END_STORAGE_Buffer : std_logic;
- signal SRC_RDY_N_Buffer : std_logic;
- signal SOF_N_Buffer : std_logic;
- signal EOF_N_Buffer : std_logic;
- signal RX_REM_Buffer : std_logic_vector(0 to 1);
- signal FRAME_ERR_RESULT_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal start_next_r : std_logic;
- signal start_storage_r : std_logic;
- signal end_storage_r : std_logic;
- signal pad_storage_r : std_logic;
- signal rx_rem_c : std_logic_vector(0 to 2);
-
--- Wire Declarations --
-
- signal word_valid_c : std_logic;
- signal total_lanes_c : std_logic_vector(0 to 2);
- signal excess_c : std_logic;
- signal storage_not_empty_c : std_logic;
-
-begin
-
- END_STORAGE <= END_STORAGE_Buffer;
- SRC_RDY_N <= SRC_RDY_N_Buffer;
- SOF_N <= SOF_N_Buffer;
- EOF_N <= EOF_N_Buffer;
- RX_REM <= RX_REM_Buffer;
- FRAME_ERR_RESULT <= FRAME_ERR_RESULT_Buffer;
-
--- Main Body of Code --
-
- -- Storage not Empty --
-
- -- Determine whether there is any data in storage.
-
- storage_not_empty_c <= std_bool(STORAGE_COUNT /= conv_std_logic_vector(0,2));
-
-
- -- Start Next Register --
-
- -- start_next_r indicates that the Start Storage Register should be set on the next
- -- cycle. This condition occurs when an old frame ends, filling storage with ending
- -- data, and the SCP for the next cycle arrives on the same cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- start_next_r <= '0' after DLY;
-
- else
-
- start_next_r <= (START_DETECTED and
- not START_WITH_DATA) and
- not END_AFTER_START after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Start Storage Register --
-
- -- Setting the start storage register indicates the data in storage is from
- -- the start of a frame. The register is cleared when the data in storage is sent
- -- to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- start_storage_r <= '0' after DLY;
-
- else
-
- if ((start_next_r or START_WITH_DATA) = '1') then
-
- start_storage_r <= '1' after DLY;
-
- else
-
- if (word_valid_c = '1') then
-
- start_storage_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- End Storage Register --
-
- -- Setting the end storage register indicates the data in storage is from the end
- -- of a frame. The register is cleared when the data in storage is sent to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- end_storage_r <= '0' after DLY;
-
- else
-
-if ((((END_BEFORE_START and not START_WITH_DATA) and std_bool(total_lanes_c /= "000")) or
- (END_AFTER_START and START_WITH_DATA)) = '1') then
-
- end_storage_r <= '1' after DLY;
-
- else
-
- end_storage_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- END_STORAGE_Buffer <= end_storage_r;
-
-
- -- Pad Storage Register --
-
- -- Setting the pad storage register indicates that the data in storage had a pad
- -- character associated with it. The register is cleared when the data in storage
- -- is sent to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- pad_storage_r <= '0' after DLY;
-
- else
-
- if (PAD = '1') then
-
- pad_storage_r <= '1' after DLY;
-
- else
-
- if (word_valid_c = '1') then
-
- pad_storage_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Word Valid signal and SRC_RDY register --
-
- -- The word valid signal indicates that the output word has valid data. This can
- -- only occur when data is removed from storage. Furthermore, the data must be
- -- marked as valid so that the user knows to read the data as it appears on the
- -- LocalLink interface.
-
- word_valid_c <= (END_BEFORE_START and START_WITH_DATA) or
- (excess_c and not START_WITH_DATA) or
- (end_storage_r);
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- SRC_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- SRC_RDY_N_Buffer <= not word_valid_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Frame error result signal --
- -- Indicate a frame error whenever the deframer detects a frame error, or whenever
- -- a frame without data is detected.
- -- Empty frames are detected by looking for frames that end while the storage
- -- register is empty. We must be careful not to confuse the data from seperate
- -- frames.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- FRAME_ERR_RESULT_Buffer <= FRAME_ERR or (END_AFTER_START and not START_WITH_DATA) or
-(END_BEFORE_START and std_bool(total_lanes_c = "000") and not START_WITH_DATA) or
- (END_BEFORE_START and START_WITH_DATA and not storage_not_empty_c) after DLY;
-
- end if;
-
- end process;
-
-
-
-
- -- The total_lanes and excess signals --
-
- -- When there is too much data to put into storage, the excess signal is asserted.
-
- total_lanes_c <= conv_std_logic_vector(0,3) + LEFT_ALIGNED_COUNT + STORAGE_COUNT;
-
- excess_c <= std_bool(total_lanes_c > conv_std_logic_vector(2,3));
-
-
- -- The Start of Frame signal --
-
- -- To save logic, start of frame is asserted from the time the start of a frame
- -- is placed in storage to the time it is placed on the locallink output register.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- SOF_N_Buffer <= not start_storage_r after DLY;
-
- end if;
-
- end process;
-
-
- -- The end of frame signal --
-
- -- End of frame is asserted when storage contains ended data, or when an ECP arrives
- -- at the same time as new data that must replace old data in storage.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- EOF_N_Buffer <= not (end_storage_r or ((END_BEFORE_START and
- START_WITH_DATA) and storage_not_empty_c)) after DLY;
-
- end if;
-
- end process;
-
-
- -- The RX_REM signal --
-
- -- RX_REM is equal to the number of bytes written to the output, minus 1 if there is
- -- a pad.
-
- process (PAD, pad_storage_r, START_WITH_DATA, end_storage_r, STORAGE_COUNT, total_lanes_c)
-
- begin
-
- if ((end_storage_r or START_WITH_DATA) = '1') then
-
- if (pad_storage_r = '1') then
-
- rx_rem_c <= conv_std_logic_vector(0,3) + ((STORAGE_COUNT & '0') - conv_std_logic_vector(2,3));
-
- else
-
- rx_rem_c <= conv_std_logic_vector(0,3) + ((STORAGE_COUNT & '0') - conv_std_logic_vector(1,3));
-
- end if;
-
-
- else
-
- if ((PAD or pad_storage_r) = '1') then
-
- rx_rem_c <= (total_lanes_c(1 to 2) & '0') - conv_std_logic_vector(2,3);
-
- else
-
- rx_rem_c <= (total_lanes_c(1 to 2) & '0') - conv_std_logic_vector(1,3);
-
- end if;
-
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_REM_Buffer <= rx_rem_c(1 to 2) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_standard_cc_module.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_standard_cc_module.vhd
deleted file mode 100644
index aeaf2e398f545cb61f784fd715fda1d8030345fe..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_standard_cc_module.vhd
+++ /dev/null
@@ -1,314 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STANDARD_CC_MODULE
---
---
--- Description: This module drives the Aurora module's Clock Compensation
--- interface. Clock Compensation sequences are generated according
--- to the requirements in the Aurora Protocol specification.
---
--- This module supports modules with User Flow Control and
--- 1 4-byte lanes.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-entity east_channel_STANDARD_CC_MODULE is
-generic
-(
- CC_FREQ_FACTOR : integer := 12
-);
-port
-(
- -- Clock Compensation Control Interface
- WARN_CC : out std_logic;
- DO_CC : out std_logic;
-
- -- System Interface
- PLL_NOT_LOCKED : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
-
-);
-end east_channel_STANDARD_CC_MODULE;
-
-architecture RTL of east_channel_STANDARD_CC_MODULE is
- attribute core_generation_info : string;
-attribute core_generation_info of RTL : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
---******************************Parameter Declarations*******************************
-
- constant DLY : time := 1 ns;
-
---************************** Internal Register Declarations **************************
-
- signal prepare_count_r : std_logic_vector(0 to 9) := "0000000000";
- signal cc_count_r : std_logic_vector(0 to 5) := "000000";
- signal reset_r : std_logic;
-
- signal count_13d_srl_r : std_logic_vector(0 to 11);
- signal count_13d_flop_r : std_logic;
- signal count_16d_srl_r : std_logic_vector(0 to 14);
- signal count_16d_flop_r : std_logic;
- signal count_24d_srl_r : std_logic_vector(0 to CC_FREQ_FACTOR-2);
- signal count_24d_flop_r : std_logic;
-
---*********************************Wire Declarations**********************************
- signal enable_cc_c : std_logic;
-
- signal start_cc_c : std_logic;
- signal inner_count_done_r : std_logic;
- signal middle_count_done_c : std_logic;
- signal cc_idle_count_done_c : std_logic;
-
---*********************************Main Body of Code**********************************
-begin
-
- --________________________Clock Correction State Machine__________________________
- enable_cc_c <= not RESET;
-
- -- The clock correction state machine is a counter with three sections. The first
- -- section counts out the idle period before a clock correction occurs. The second
- -- section counts out a period when NFC and UFC operations should not be attempted
- -- because they will not be completed. The last section counts out the cycles of
- -- the clock correction sequence.
-
- -- The inner count for the CC counter counts to 13. It is implemented using
- -- an SRL16 and a flop
-
- -- The SRL counts 12 bits of the count
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_13d_srl_r <= "000000000000" after DLY;
- else
- count_13d_srl_r <= (count_13d_flop_r & count_13d_srl_r(0 to 10)) after DLY;
- end if;
- end if;
- end process;
-
- -- The inner count is done when a 1 reaches the end of the SRL
- inner_count_done_r <= count_13d_srl_r(11);
-
- -- The flop extends the shift register to 13 bits for counting. It is held at
- -- zero while channel up is low to clear the register, and is seeded with a
- -- single 1 when channel up transitions from 0 to 1
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_13d_flop_r <= '0' after DLY;
- elsif( (enable_cc_c and reset_r)= '1') then
- count_13d_flop_r <= '1' after DLY;
- else
- count_13d_flop_r <= inner_count_done_r after DLY;
- end if;
- end if;
- end process;
-
- -- The middle count for the CC counter counts to 16. Its count increments only
- -- when the inner count is done. It is implemented using an SRL16 and a flop
-
- -- The SRL counts 15 bits of the count. It is enabled only when the inner count
- -- is done
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if (RESET = '1') then
- count_16d_srl_r <= "000000000000000" after DLY;
- elsif((inner_count_done_r or not enable_cc_c ) = '1') then
- count_16d_srl_r <= ( count_16d_flop_r & count_16d_srl_r(0 to 13) ) after DLY;
- end if;
- end if;
- end process;
-
- -- The middle count is done when a 1 reaches the end of the SRL and the inner
- -- count finishes
- middle_count_done_c <= inner_count_done_r and count_16d_srl_r(14);
-
- -- The flop extends the shift register to 16 bits for counting. It is held at
- -- zero while channel up is low to clear the register, and is seeded with a
- -- single 1 when channel up transitions from 0 to 1
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_16d_flop_r <= '0' after DLY;
- elsif((enable_cc_c and reset_r)='1') then
- count_16d_flop_r <= '1' after DLY;
- elsif(inner_count_done_r = '1') then
- count_16d_flop_r <= middle_count_done_c after DLY;
- end if;
- end if;
- end process;
-
-
- -- The outer count (aka the cc idle count) is done when it reaches 12. Its count
- -- increments only when the middle count is done. It is implemented with an
- -- SRL16 and a flop
-
- -- The SRL counts 23 bits of the count. It is enabled only when the middle count is
- -- done
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_24d_srl_r <= (others => '0') after DLY;
- elsif((middle_count_done_c or not enable_cc_c ) = '1') then
- count_24d_srl_r <= (count_24d_flop_r & count_24d_srl_r(0 to CC_FREQ_FACTOR - 3)) after DLY;
- end if;
- end if;
- end process;
-
- -- The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
- cc_idle_count_done_c <= middle_count_done_c and count_24d_srl_r(CC_FREQ_FACTOR - 2);
-
- -- The flop extends the shift register to 12 bits for counting. It is held at
- -- zero while channel up is low to clear the register, and is seeded with a single
- -- 1 when channel up transitions from 0 to 1
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_24d_flop_r <= '0' after DLY;
- elsif( (enable_cc_c and reset_r) = '1') then
- count_24d_flop_r <= '1' after DLY;
- elsif( middle_count_done_c = '1') then
- count_24d_flop_r <= cc_idle_count_done_c after DLY;
- end if;
- end if;
- end process;
-
-
- -- Because UFC and CC sequences are not allowed to preempt one another, there
- -- there is a warning signal to indicate an impending CC sequence. This signal
- -- is used to prevent UFC messages from starting.
-
- -- For 1 lane, we use a 6-cycle count.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- prepare_count_r <= "0000000000" after DLY;
- else
- prepare_count_r <= ("0000" & cc_idle_count_done_c & prepare_count_r(4 to 8)) after DLY;
- end if;
- end if;
- end process;
-
-
- -- The state machine stays in the prepare_cc state from when the cc idle
- -- count finishes, to when the prepare count has finished. While in this
- -- state, UFC operations cannot start, which prevents them from having to
- -- be pre-empted by CC sequences.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- WARN_CC <= '0' after DLY;
- elsif(cc_idle_count_done_c = '1') then
- WARN_CC <= '1' after DLY;
- elsif(prepare_count_r(9) = '1') then
- WARN_CC <= '0' after DLY;
- end if;
- end if;
- end process;
-
- -- Track the state of channel up on the previous cycle. We use this signal to determine
- -- when to seed the shift register counters with ones
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- reset_r <= RESET after DLY;
- end if;
- end process;
-
- --Do a CC after enable_cc_c is asserted or CC_warning is complete.
- start_cc_c <= prepare_count_r(9) or (enable_cc_c and reset_r);
-
- -- This SRL counter keeps track of the number of cycles spent in the CC
- -- sequence. It starts counting when the prepare_cc state ends, and
- -- finishes counting after 3 cycles have passed.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- cc_count_r <= "000000" after DLY;
- else
- cc_count_r <= ( "000" & (not enable_cc_c or prepare_count_r(9)) & cc_count_r(3 to 4) ) after DLY;
- end if;
- end if;
- end process;
-
- -- The TX_LL module stays in the do_cc state for 3 cycles. It starts
- -- when the prepare_cc state ends.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- DO_CC <= '0' after DLY;
- elsif(start_cc_c = '1') then
- DO_CC <= '1' after DLY;
- elsif(cc_count_r /= "000000" ) then
- DO_CC <= '1' after DLY;
- elsif(cc_count_r = "000000") then
- DO_CC <= '0' after DLY;
- end if;
- end if;
- end process;
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_ce_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_ce_control.vhd
deleted file mode 100644
index d3bd2bbad65c8a7efdccfb2d7f8242369802160c..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_ce_control.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STORAGE_CE_CONTROL
---
---
---
--- Description: the STORAGE_CE controls the enable signals of the the Storage register
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_STORAGE_CE_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- STORAGE_CE : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_STORAGE_CE_CONTROL;
-
-architecture RTL of east_channel_STORAGE_CE_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_CE_Buffer : std_logic_vector(0 to 1);
-
--- Wire Declarations --
-
- signal overwrite_c : std_logic;
- signal excess_c : std_logic;
- signal ce_command_c : std_logic_vector(0 to 1);
-
-begin
-
- STORAGE_CE <= STORAGE_CE_Buffer;
-
--- Main Body of Code --
-
- -- Combine the end signals.
-
- overwrite_c <= END_STORAGE or START_WITH_DATA;
-
-
- -- For each lane, determine the appropriate CE value.
-
- excess_c <= std_bool(( ("1" & LEFT_ALIGNED_COUNT) + ("1" & STORAGE_COUNT) ) > conv_std_logic_vector(2,3));
-
- ce_command_c(0) <= excess_c or std_bool(STORAGE_COUNT < conv_std_logic_vector(1,2)) or overwrite_c;
- ce_command_c(1) <= excess_c or std_bool(STORAGE_COUNT < conv_std_logic_vector(2,2)) or overwrite_c;
-
-
- -- Register the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- STORAGE_CE_Buffer <= (others => '0') after DLY;
-
- else
-
- STORAGE_CE_Buffer <= ce_command_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_count_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_count_control.vhd
deleted file mode 100644
index 005cf0354bfaf3f07e7bf91c195c9115b102fcb6..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_count_control.vhd
+++ /dev/null
@@ -1,181 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STORAGE_COUNT_CONTROL
---
---
---
--- Description: STORAGE_COUNT_CONTROL sets the storage count value for the next clock
--- cycle
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_STORAGE_COUNT_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- FRAME_ERR : in std_logic;
- STORAGE_COUNT : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_STORAGE_COUNT_CONTROL;
-
-architecture RTL of east_channel_STORAGE_COUNT_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_COUNT_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal storage_count_c : std_logic_vector(0 to 1);
- signal storage_count_r : std_logic_vector(0 to 1);
-
--- Wire Declarations --
-
- signal overwrite_c : std_logic;
- signal sum_c : std_logic_vector(0 to 2);
- signal remainder_c : std_logic_vector(0 to 2);
- signal overflow_c : std_logic;
-
-begin
-
- STORAGE_COUNT <= STORAGE_COUNT_Buffer;
-
--- Main Body of Code --
-
- -- Calculate the value that will be used for the switch.
-
- sum_c <= conv_std_logic_vector(0,3) + LEFT_ALIGNED_COUNT + storage_count_r;
- remainder_c <= sum_c - conv_std_logic_vector(2,3);
-
- overwrite_c <= END_STORAGE or START_WITH_DATA;
- overflow_c <= std_bool(sum_c > conv_std_logic_vector(2,3));
-
-
- process (overwrite_c, overflow_c, sum_c, remainder_c, LEFT_ALIGNED_COUNT)
-
- variable vec : std_logic_vector(0 to 1);
-
- begin
-
- vec := overwrite_c & overflow_c;
-
- case vec is
-
- when "00" =>
-
- storage_count_c <= sum_c(1 to 2);
-
- when "01" =>
-
- storage_count_c <= remainder_c(1 to 2);
-
- when "10" =>
-
- storage_count_c <= LEFT_ALIGNED_COUNT;
-
- when "11" =>
-
- storage_count_c <= LEFT_ALIGNED_COUNT;
-
- when others =>
-
- storage_count_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the Storage Count for the next cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- storage_count_r <= (others => '0') after DLY;
-
- else
-
- storage_count_r <= storage_count_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Make the output of the storage count register available to other modules.
-
- STORAGE_COUNT_Buffer <= storage_count_r;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_mux.vhd
deleted file mode 100644
index d7381ca3fc149a6891e375e97ebb87d1520dcdc3..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_mux.vhd
+++ /dev/null
@@ -1,174 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STORAGE_MUX
---
---
---
--- Description: The STORAGE_MUX has a set of 16 bit muxes to control the
--- flow of data. Every output position has its own N:1 mux.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_STORAGE_MUX is
-
- port (
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- STORAGE_CE : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- STORAGE_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end east_channel_STORAGE_MUX;
-
-architecture RTL of east_channel_STORAGE_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal storage_data_c : std_logic_vector(0 to 31);
-
-begin
-
- STORAGE_DATA <= STORAGE_DATA_Buffer;
-
--- Main Body of Code --
-
- -- Each lane has a set of 16 N:1 muxes connected to all the raw data lanes.
-
- -- Muxes for Lane 0
-
- process (MUX_SELECT(0 to 4), RAW_DATA)
-
- begin
-
- case MUX_SELECT(0 to 4) is
-
-when "00000" =>
-
- storage_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "00001" =>
-
- storage_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- storage_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Muxes for Lane 1
-
- process (MUX_SELECT(5 to 9), RAW_DATA)
-
- begin
-
- case MUX_SELECT(5 to 9) is
-
-when "00000" =>
-
- storage_data_c(16 to 31) <= RAW_DATA(0 to 15);
-
-when "00001" =>
-
- storage_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- storage_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the stored data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (STORAGE_CE(0) = '1') then
-
- STORAGE_DATA_Buffer(0 to 15) <= storage_data_c(0 to 15) after DLY;
-
- end if;
-
- if (STORAGE_CE(1) = '1') then
-
- STORAGE_DATA_Buffer(16 to 31) <= storage_data_c(16 to 31) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_switch_control.vhd
deleted file mode 100644
index 4fc71f0f6e9e39e26a84a636e0fff03a6d36d671..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_storage_switch_control.vhd
+++ /dev/null
@@ -1,223 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--------------------------------------------------------------------------------
---
--- STORAGE_SWITCH_CONTROL
---
---
---
--- Description: STORAGE_SWITCH_CONTROL selects the input chunk for each storage chunk mux
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_STORAGE_SWITCH_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- STORAGE_SELECT : out std_logic_vector(0 to 9);
- USER_CLK : in std_logic
-
- );
-
-end east_channel_STORAGE_SWITCH_CONTROL;
-
-architecture RTL of east_channel_STORAGE_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_SELECT_Buffer : std_logic_vector(0 to 9);
-
--- Internal Register Declarations --
-
- signal end_r : std_logic;
- signal lac_r : std_logic_vector(0 to 1);
- signal stc_r : std_logic_vector(0 to 1);
- signal storage_select_c : std_logic_vector(0 to 9);
-
--- Wire Declarations --
-
- signal overwrite_c : std_logic;
-
-
-
-begin
-
- STORAGE_SELECT <= STORAGE_SELECT_Buffer;
-
--- Main Body of Code --
-
- -- Combine the end signals.
-
- overwrite_c <= END_STORAGE or START_WITH_DATA;
-
-
- -- Generate switch signals --
-
- process (overwrite_c, LEFT_ALIGNED_COUNT, STORAGE_COUNT)
-
- variable vec : std_logic_vector(0 to 3);
-
- begin
-
- if (overwrite_c = '1') then
-
- storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
- else
-
- vec := LEFT_ALIGNED_COUNT & STORAGE_COUNT;
-
- case vec is
-
-when "0100" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
-when "0110" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
-when "1000" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
-when "1001" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(1,5);
-
-when "1010" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
- when others =>
-
- storage_select_c(0 to 4) <= (others => 'X');
-
- end case;
-
- end if;
-
- end process;
-
-
- process (overwrite_c, LEFT_ALIGNED_COUNT, STORAGE_COUNT)
-
- variable vec : std_logic_vector(0 to 3);
-
- begin
-
- if (overwrite_c = '1') then
-
- storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
- else
-
- vec := LEFT_ALIGNED_COUNT & STORAGE_COUNT;
-
- case vec is
-
-when "0100" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
-when "0101" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(0,5);
-
-when "0110" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
-when "1000" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
-when "1010" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
- when others =>
-
- storage_select_c(5 to 9) <= (others => 'X');
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Register the storage select signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- STORAGE_SELECT_Buffer <= storage_select_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sym_dec_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sym_dec_4byte.vhd
deleted file mode 100644
index 1a7f6ecbe4d73a03539fa72d023f2b3a8165d88b..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sym_dec_4byte.vhd
+++ /dev/null
@@ -1,958 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- SYM_DEC_4BYTE
---
---
--- Description: The SYM_DEC_4BYTE module is a symbol decoder for the
--- 4-byte Aurora Lane. Its inputs are the raw data from
--- the GTX. It word-aligns the regular data and decodes
--- all of the Aurora control symbols. Its outputs are the
--- word-aligned data and signals indicating the arrival of
--- specific control characters.
---
--- This module supports User Flow Control
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_SYM_DEC_4BYTE is
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed.
- LANE_UP : in std_logic;
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- RX_CC : out std_logic; -- CC sequence received.
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- Raw RX data from GTX.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Bits indicating which bytes are control characters.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Rx'ed a comma.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET : in std_logic
-
- );
-
-end east_channel_SYM_DEC_4BYTE;
-
-architecture RTL of east_channel_SYM_DEC_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
- constant K_CHAR_0 : std_logic_vector(0 to 3) := X"B";
- constant K_CHAR_1 : std_logic_vector(0 to 3) := X"C";
- constant SP_DATA_0 : std_logic_vector(0 to 3) := X"4";
- constant SP_DATA_1 : std_logic_vector(0 to 3) := X"A";
- constant SPA_DATA_0 : std_logic_vector(0 to 3) := X"2";
- constant SPA_DATA_1 : std_logic_vector(0 to 3) := X"C";
- constant SP_NEG_DATA_0 : std_logic_vector(0 to 3) := X"B";
- constant SP_NEG_DATA_1 : std_logic_vector(0 to 3) := X"5";
- constant SPA_NEG_DATA_0 : std_logic_vector(0 to 3) := X"D";
- constant SPA_NEG_DATA_1 : std_logic_vector(0 to 3) := X"3";
- constant PAD_0 : std_logic_vector(0 to 3) := X"9";
- constant PAD_1 : std_logic_vector(0 to 3) := X"C";
- constant SCP_0 : std_logic_vector(0 to 3) := X"5";
- constant SCP_1 : std_logic_vector(0 to 3) := X"C";
- constant SCP_2 : std_logic_vector(0 to 3) := X"F";
- constant SCP_3 : std_logic_vector(0 to 3) := X"B";
- constant ECP_0 : std_logic_vector(0 to 3) := X"F";
- constant ECP_1 : std_logic_vector(0 to 3) := X"D";
- constant ECP_2 : std_logic_vector(0 to 3) := X"F";
- constant ECP_3 : std_logic_vector(0 to 3) := X"E";
- constant SUF_0 : std_logic_vector(0 to 3) := X"9";
- constant SUF_1 : std_logic_vector(0 to 3) := X"C";
- constant A_CHAR_0 : std_logic_vector(0 to 3) := X"7";
- constant A_CHAR_1 : std_logic_vector(0 to 3) := X"C";
- constant VER_DATA_0 : std_logic_vector(0 to 3) := X"E";
- constant VER_DATA_1 : std_logic_vector(0 to 3) := X"8";
- constant CC_CHAR_0 : std_logic_vector(0 to 3) := X"F";
- constant CC_CHAR_1 : std_logic_vector(0 to 3) := X"7";
-
--- External Register Declarations --
-
- signal RX_PAD_Buffer : std_logic_vector(0 to 1);
- signal RX_PE_DATA_Buffer : std_logic_vector(0 to 31);
- signal RX_PE_DATA_V_Buffer : std_logic_vector(0 to 1);
- signal RX_SCP_Buffer : std_logic_vector(0 to 1);
- signal RX_ECP_Buffer : std_logic_vector(0 to 1);
- signal RX_SUF_Buffer : std_logic_vector(0 to 1);
- signal RX_FC_NB_Buffer : std_logic_vector(0 to 7);
- signal RX_SP_Buffer : std_logic;
- signal RX_SPA_Buffer : std_logic;
- signal RX_NEG_Buffer : std_logic;
- signal GOT_A_Buffer : std_logic_vector(0 to 3);
- signal GOT_V_Buffer : std_logic;
- signal RX_CC_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal left_align_select_r : std_logic_vector(0 to 1);
- signal previous_cycle_data_r : std_logic_vector(23 downto 0);
- signal previous_cycle_control_r : std_logic_vector(2 downto 0);
- signal word_aligned_data_r : std_logic_vector(0 to 31);
- signal word_aligned_control_bits_r : std_logic_vector(0 to 3);
- signal rx_pe_data_r : std_logic_vector(0 to 31);
- signal rx_pe_control_r : std_logic_vector(0 to 3);
- signal rx_pad_d_r : std_logic_vector(0 to 3);
- signal rx_scp_d_r : std_logic_vector(0 to 7);
- signal rx_ecp_d_r : std_logic_vector(0 to 7);
- signal rx_suf_d_r : std_logic_vector(0 to 3);
- signal rx_sp_r : std_logic_vector(0 to 7);
- signal rx_spa_r : std_logic_vector(0 to 7);
- signal rx_sp_neg_d_r : std_logic_vector(0 to 1);
- signal rx_spa_neg_d_r : std_logic_vector(0 to 1);
- signal rx_v_d_r : std_logic_vector(0 to 7);
- signal got_a_d_r : std_logic_vector(0 to 7);
- signal first_v_received_r : std_logic := '0';
- signal rx_cc_r : std_logic_vector(0 to 7);
-
--- Wire Declarations --
-
- signal got_v_c : std_logic;
-
-begin
-
- RX_PAD <= RX_PAD_Buffer;
- RX_PE_DATA <= RX_PE_DATA_Buffer;
- RX_PE_DATA_V <= RX_PE_DATA_V_Buffer;
- RX_SCP <= RX_SCP_Buffer;
- RX_ECP <= RX_ECP_Buffer;
- RX_SUF <= RX_SUF_Buffer;
- RX_FC_NB <= RX_FC_NB_Buffer;
- RX_SP <= RX_SP_Buffer;
- RX_SPA <= RX_SPA_Buffer;
- RX_NEG <= RX_NEG_Buffer;
- GOT_A <= GOT_A_Buffer;
- GOT_V <= GOT_V_Buffer;
- RX_CC <= RX_CC_Buffer;
-
--- Main Body of Code --
-
- -- Word Alignment --
-
- -- Determine whether the lane is aligned to the left byte (MSByte) or the
- -- right byte (LSByte). This information is used for word alignment. To
- -- prevent the word align from changing during normal operation, we do word
- -- alignment only when it is allowed by the lane_init_sm.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((DO_WORD_ALIGN and not first_v_received_r) = '1') then
-
- case RX_CHAR_IS_K is
-
- when "1000" => left_align_select_r <= "00" after DLY;
- when "0100" => left_align_select_r <= "01" after DLY;
- when "0010" => left_align_select_r <= "10" after DLY;
- when "1100" => left_align_select_r <= "01" after DLY;
- when "1110" => left_align_select_r <= "10" after DLY;
- when "0001" => left_align_select_r <= "11" after DLY;
- when others => left_align_select_r <= left_align_select_r after DLY;
-
- end case;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Store bytes 1, 2 and 3 from the previous cycle. If the lane is aligned
- -- on one of those bytes, we use the data in the current cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- previous_cycle_data_r <= RX_DATA(23 downto 0) after DLY;
-
- end if;
-
- end process;
-
-
- -- Store the control bits from bytes 1, 2 and 3 from the previous cycle. If
- -- we align on one of those bytes, we will also need to use their previous
- -- value control bits.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- previous_cycle_control_r <= RX_CHAR_IS_K(2 downto 0) after DLY;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 0.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(0 to 7) <= RX_DATA(31 downto 24) after DLY;
- when "01" => word_aligned_data_r(0 to 7) <= previous_cycle_data_r(23 downto 16) after DLY;
- when "10" => word_aligned_data_r(0 to 7) <= previous_cycle_data_r(15 downto 8) after DLY;
- when "11" => word_aligned_data_r(0 to 7) <= previous_cycle_data_r(7 downto 0) after DLY;
- when others => word_aligned_data_r(0 to 7) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 1.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(8 to 15) <= RX_DATA(23 downto 16) after DLY;
- when "01" => word_aligned_data_r(8 to 15) <= previous_cycle_data_r(15 downto 8) after DLY;
- when "10" => word_aligned_data_r(8 to 15) <= previous_cycle_data_r(7 downto 0) after DLY;
- when "11" => word_aligned_data_r(8 to 15) <= RX_DATA(31 downto 24) after DLY;
- when others => word_aligned_data_r(8 to 15) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 2.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(16 to 23) <= RX_DATA(15 downto 8) after DLY;
- when "01" => word_aligned_data_r(16 to 23) <= previous_cycle_data_r(7 downto 0) after DLY;
- when "10" => word_aligned_data_r(16 to 23) <= RX_DATA(31 downto 24) after DLY;
- when "11" => word_aligned_data_r(16 to 23) <= RX_DATA(23 downto 16) after DLY;
- when others => word_aligned_data_r(16 to 23) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 3.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(24 to 31) <= RX_DATA(7 downto 0) after DLY;
- when "01" => word_aligned_data_r(24 to 31) <= RX_DATA(31 downto 24) after DLY;
- when "10" => word_aligned_data_r(24 to 31) <= RX_DATA(23 downto 16) after DLY;
- when "11" => word_aligned_data_r(24 to 31) <= RX_DATA(15 downto 8) after DLY;
- when others => word_aligned_data_r(24 to 31) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 0.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(0) <= RX_CHAR_IS_K(3) after DLY;
- when "01" => word_aligned_control_bits_r(0) <= previous_cycle_control_r(2) after DLY;
- when "10" => word_aligned_control_bits_r(0) <= previous_cycle_control_r(1) after DLY;
- when "11" => word_aligned_control_bits_r(0) <= previous_cycle_control_r(0) after DLY;
- when others => word_aligned_control_bits_r(0) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 1.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(2) after DLY;
- when "01" => word_aligned_control_bits_r(1) <= previous_cycle_control_r(1) after DLY;
- when "10" => word_aligned_control_bits_r(1) <= previous_cycle_control_r(0) after DLY;
- when "11" => word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(3) after DLY;
- when others => word_aligned_control_bits_r(1) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 2.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(2) <= RX_CHAR_IS_K(1) after DLY;
- when "01" => word_aligned_control_bits_r(2) <= previous_cycle_control_r(0) after DLY;
- when "10" => word_aligned_control_bits_r(2) <= RX_CHAR_IS_K(3) after DLY;
- when "11" => word_aligned_control_bits_r(2) <= RX_CHAR_IS_K(2) after DLY;
- when others => word_aligned_control_bits_r(2) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 3.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(0) after DLY;
- when "01" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(3) after DLY;
- when "10" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(2) after DLY;
- when "11" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(1) after DLY;
- when others => word_aligned_control_bits_r(3) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Pipeline the word-aligned data for 1 cycle to match the Decodes.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pe_data_r <= word_aligned_data_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Register the pipelined word-aligned data for the RX_LL interface.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_PE_DATA_Buffer <= rx_pe_data_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode Control Symbols --
-
- -- All decodes are pipelined to keep the number of logic levels to a minimum.
-
- -- Delay the control bits: they are most often used in the second stage of the
- -- decoding process.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pe_control_r <= word_aligned_control_bits_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode PAD.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pad_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = PAD_0) after DLY;
- rx_pad_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = PAD_1) after DLY;
- rx_pad_d_r(2) <= std_bool(word_aligned_data_r(24 to 27) = PAD_0) after DLY;
- rx_pad_d_r(3) <= std_bool(word_aligned_data_r(28 to 31) = PAD_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_PAD_Buffer(0) <= std_bool((rx_pad_d_r(0 to 1) = "11") and (rx_pe_control_r(0 to 1)) = "01") after DLY;
- RX_PAD_Buffer(1) <= std_bool((rx_pad_d_r(2 to 3) = "11") and (rx_pe_control_r(2 to 3)) = "01") after DLY;
-
- end if;
-
- end process;
-
-
-
- -- Decode RX_PE_DATA_V.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_PE_DATA_V_Buffer(0) <= not rx_pe_control_r(0) after DLY;
- RX_PE_DATA_V_Buffer(1) <= not rx_pe_control_r(2) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode RX_SCP.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_scp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SCP_0) after DLY;
- rx_scp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SCP_1) after DLY;
- rx_scp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SCP_2) after DLY;
- rx_scp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SCP_3) after DLY;
- rx_scp_d_r(4) <= std_bool(word_aligned_data_r(16 to 19) = SCP_0) after DLY;
- rx_scp_d_r(5) <= std_bool(word_aligned_data_r(20 to 23) = SCP_1) after DLY;
- rx_scp_d_r(6) <= std_bool(word_aligned_data_r(24 to 27) = SCP_2) after DLY;
- rx_scp_d_r(7) <= std_bool(word_aligned_data_r(28 to 31) = SCP_3) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SCP_Buffer(0) <= rx_pe_control_r(0) and
- rx_pe_control_r(1) and
- rx_scp_d_r(0) and
- rx_scp_d_r(1) and
- rx_scp_d_r(2) and
- rx_scp_d_r(3) after DLY;
-
- RX_SCP_Buffer(1) <= rx_pe_control_r(2) and
- rx_pe_control_r(3) and
- rx_scp_d_r(4) and
- rx_scp_d_r(5) and
- rx_scp_d_r(6) and
- rx_scp_d_r(7) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode RX_ECP.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_ecp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = ECP_0) after DLY;
- rx_ecp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = ECP_1) after DLY;
- rx_ecp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = ECP_2) after DLY;
- rx_ecp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = ECP_3) after DLY;
- rx_ecp_d_r(4) <= std_bool(word_aligned_data_r(16 to 19) = ECP_0) after DLY;
- rx_ecp_d_r(5) <= std_bool(word_aligned_data_r(20 to 23) = ECP_1) after DLY;
- rx_ecp_d_r(6) <= std_bool(word_aligned_data_r(24 to 27) = ECP_2) after DLY;
- rx_ecp_d_r(7) <= std_bool(word_aligned_data_r(28 to 31) = ECP_3) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_ECP_Buffer(0) <= rx_pe_control_r(0) and
- rx_pe_control_r(1) and
- rx_ecp_d_r(0) and
- rx_ecp_d_r(1) and
- rx_ecp_d_r(2) and
- rx_ecp_d_r(3) after DLY;
-
- RX_ECP_Buffer(1) <= rx_pe_control_r(2) and
- rx_pe_control_r(3) and
- rx_ecp_d_r(4) and
- rx_ecp_d_r(5) and
- rx_ecp_d_r(6) and
- rx_ecp_d_r(7) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode RX_SUF.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_suf_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SUF_0) after DLY;
- rx_suf_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SUF_1) after DLY;
- rx_suf_d_r(2) <= std_bool(word_aligned_data_r(16 to 19) = SUF_0) after DLY;
- rx_suf_d_r(3) <= std_bool(word_aligned_data_r(20 to 23) = SUF_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SUF_Buffer(0) <= rx_pe_control_r(0) and
- rx_suf_d_r(0) and
- rx_suf_d_r(1) after DLY;
-
- RX_SUF_Buffer(1) <= rx_pe_control_r(2) and
- rx_suf_d_r(2) and
- rx_suf_d_r(3) after DLY;
-
- end if;
-
- end process;
-
-
- -- Extract the Flow Control Size code and register it for the RX_LL interface.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_FC_NB_Buffer(0 to 3) <= rx_pe_data_r(8 to 11) after DLY;
- RX_FC_NB_Buffer(4 to 7) <= rx_pe_data_r(24 to 27) after DLY;
-
- end if;
-
- end process;
-
-
- -- Indicate the SP sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_sp_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
- rx_sp_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
-
- rx_sp_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
- (word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
-
- rx_sp_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
- (word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
-
- rx_sp_r(4) <= std_bool((word_aligned_data_r(16 to 19) = SP_DATA_0) or
- (word_aligned_data_r(16 to 19) = SP_NEG_DATA_0)) after DLY;
-
- rx_sp_r(5) <= std_bool((word_aligned_data_r(20 to 23) = SP_DATA_1) or
- (word_aligned_data_r(20 to 23) = SP_NEG_DATA_1)) after DLY;
-
- rx_sp_r(6) <= std_bool((word_aligned_data_r(24 to 27) = SP_DATA_0) or
- (word_aligned_data_r(24 to 27) = SP_NEG_DATA_0)) after DLY;
-
- rx_sp_r(7) <= std_bool((word_aligned_data_r(28 to 31) = SP_DATA_1) or
- (word_aligned_data_r(28 to 31) = SP_NEG_DATA_1)) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SP_Buffer <= std_bool((rx_pe_control_r = "1000") and (rx_sp_r = X"FF")) after DLY;
-
- end if;
-
- end process;
-
-
- -- Indicate the SPA sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_spa_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
- rx_spa_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
- rx_spa_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
- rx_spa_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
- rx_spa_r(4) <= std_bool(word_aligned_data_r(16 to 19) = SPA_DATA_0) after DLY;
- rx_spa_r(5) <= std_bool(word_aligned_data_r(20 to 23) = SPA_DATA_1) after DLY;
- rx_spa_r(6) <= std_bool(word_aligned_data_r(24 to 27) = SPA_DATA_0) after DLY;
- rx_spa_r(7) <= std_bool(word_aligned_data_r(28 to 31) = SPA_DATA_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SPA_Buffer <= std_bool((rx_pe_control_r = "1000") and (rx_spa_r = X"FF")) after DLY;
-
- end if;
-
- end process;
-
-
- -- Indicate reversed data received. We look only at the word aligned LSByte
- -- which, during an SP or SPA sequence, will always contain a data byte.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_sp_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0) after DLY;
- rx_sp_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1) after DLY;
-
- rx_spa_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SPA_NEG_DATA_0) after DLY;
- rx_spa_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SPA_NEG_DATA_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_NEG_Buffer <= not rx_pe_control_r(1) and
- std_bool((rx_sp_neg_d_r = "11") or
- (rx_spa_neg_d_r = "11")) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode GOT_A.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- got_a_d_r(0) <= std_bool(RX_DATA(31 downto 28) = A_CHAR_0) after DLY;
- got_a_d_r(1) <= std_bool(RX_DATA(27 downto 24) = A_CHAR_1) after DLY;
- got_a_d_r(2) <= std_bool(RX_DATA(23 downto 20) = A_CHAR_0) after DLY;
- got_a_d_r(3) <= std_bool(RX_DATA(19 downto 16) = A_CHAR_1) after DLY;
- got_a_d_r(4) <= std_bool(RX_DATA(15 downto 12) = A_CHAR_0) after DLY;
- got_a_d_r(5) <= std_bool(RX_DATA(11 downto 8) = A_CHAR_1) after DLY;
- got_a_d_r(6) <= std_bool(RX_DATA(7 downto 4) = A_CHAR_0) after DLY;
- got_a_d_r(7) <= std_bool(RX_DATA(3 downto 0) = A_CHAR_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- GOT_A_Buffer(0) <= RX_CHAR_IS_K(3) and std_bool(got_a_d_r(0 to 1) = "11") after DLY;
- GOT_A_Buffer(1) <= RX_CHAR_IS_K(2) and std_bool(got_a_d_r(2 to 3) = "11") after DLY;
- GOT_A_Buffer(2) <= RX_CHAR_IS_K(1) and std_bool(got_a_d_r(4 to 5) = "11") after DLY;
- GOT_A_Buffer(3) <= RX_CHAR_IS_K(0) and std_bool(got_a_d_r(6 to 7) = "11") after DLY;
-
- end if;
-
- end process;
-
-
- -- Verification symbol decode --
-
- -- Indicate the SP sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
- rx_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
- rx_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
- rx_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
- rx_v_d_r(4) <= std_bool(word_aligned_data_r(16 to 19) = VER_DATA_0) after DLY;
- rx_v_d_r(5) <= std_bool(word_aligned_data_r(20 to 23) = VER_DATA_1) after DLY;
- rx_v_d_r(6) <= std_bool(word_aligned_data_r(24 to 27) = VER_DATA_0) after DLY;
- rx_v_d_r(7) <= std_bool(word_aligned_data_r(28 to 31) = VER_DATA_1) after DLY;
-
- end if;
-
- end process;
-
-
- got_v_c <= std_bool((rx_pe_control_r = "1000") and (rx_v_d_r = X"FF"));
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- GOT_V_Buffer <= got_v_c after DLY;
-
- end if;
-
- end process;
-
-
- -- Remember that the first V sequence has been detected.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (LANE_UP = '0') then
-
- first_v_received_r <= '0' after DLY;
-
- else
-
- if (got_v_c = '1') then
-
- first_v_received_r <= '1' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
- -- Indicate the CC sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_cc_r(0) <= std_bool(word_aligned_data_r(0 to 3) = CC_CHAR_0) after DLY;
- rx_cc_r(1) <= std_bool(word_aligned_data_r(4 to 7) = CC_CHAR_1) after DLY;
- rx_cc_r(2) <= std_bool(word_aligned_data_r(8 to 11) = CC_CHAR_0) after DLY;
- rx_cc_r(3) <= std_bool(word_aligned_data_r(12 to 15) = CC_CHAR_1) after DLY;
- rx_cc_r(4) <= std_bool(word_aligned_data_r(16 to 19) = CC_CHAR_0) after DLY;
- rx_cc_r(5) <= std_bool(word_aligned_data_r(20 to 23) = CC_CHAR_1) after DLY;
- rx_cc_r(6) <= std_bool(word_aligned_data_r(24 to 27) = CC_CHAR_0) after DLY;
- rx_cc_r(7) <= std_bool(word_aligned_data_r(28 to 31) = CC_CHAR_1) after DLY;
-
- end if;
-
- end process;
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_CC_Buffer <= std_bool((rx_pe_control_r = "1111") and
- (rx_cc_r = X"FF")) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sym_gen_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sym_gen_4byte.vhd
deleted file mode 100644
index 821434ba1f5c92788ac6c218b6d2214bc32b6730..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_sym_gen_4byte.vhd
+++ /dev/null
@@ -1,562 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- SYM_GEN_4BYTE
---
---
---
--- Description: The SYM_GEN module is a symbol generator for 4-byte Aurora Lanes.
--- Its inputs request the transmission of specific symbols, and its
--- outputs drive the GTX interface to fulfill those requests.
---
--- All generation request inputs must be asserted exclusively
--- except for the GEN_K, GEN_R and GEN_A signals from the Global
--- Logic, and the GEN_PAD and TX_PE_DATA_V signals from TX_LL.
---
--- GEN_K, GEN_R and GEN_A can be asserted anytime, but they are
--- ignored when other signals are being asserted. This allows the
--- idle generator in the Global Logic to run continuously without
--- feedback, but requires the TX_LL and Lane Init SM modules to
--- be quiescent during Channel Bonding and Verification.
---
--- The GEN_PAD signal is only valid while the TX_PE_DATA_V signal
--- is asserted. This allows padding to be specified for the LSB
--- of the data transmission. GEN_PAD must not be asserted when
--- TX_PE_DATA_V is not asserted - this will generate errors.
---
--- This module supports User Flow Control.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity east_channel_SYM_GEN_4BYTE is
-
- port (
-
- -- TX_LL Interface -- See description for info about GEN_PAD and TX_PE_DATA_V.
-
- GEN_SCP : in std_logic_vector(0 to 1); -- Generate SCP.
- GEN_ECP : in std_logic_vector(0 to 1); -- Generate ECP.
- GEN_SUF : in std_logic_vector(0 to 1); -- Generate SUF using code given by FC_NB.
- GEN_PAD : in std_logic_vector(0 to 1); -- Replace LSB with Pad character.
- FC_NB : in std_logic_vector(0 to 7); -- Size code for Flow Control messages.
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data. Transmitted when TX_PE_DATA_V is asserted.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Transmit data.
- GEN_CC : in std_logic; -- Generate Clock Correction symbols.
-
- -- Global Logic Interface -- See description for info about GEN_K,GEN_R and GEN_A.
-
- GEN_A : in std_logic; -- Generate A character for MSBYTE
- GEN_K : in std_logic_vector(0 to 3); -- Generate K character for selected bytes.
- GEN_R : in std_logic_vector(0 to 3); -- Generate R character for selected bytes.
- GEN_V : in std_logic_vector(0 to 3); -- Generate Ver data character on selected bytes.
-
- -- Lane Init SM Interface
-
- GEN_SP : in std_logic; -- Generate SP pattern.
- GEN_SPA : in std_logic; -- Generate SPA pattern.
-
- -- GTX Interface
-
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- Transmit TX_DATA as a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- Data to GTX for transmission to channel partner.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora Logic.
- RESET : in std_logic -- RESET signal to drive TX_CHAR_IS_K to known value
- );
-
-end east_channel_SYM_GEN_4BYTE;
-
-architecture RTL of east_channel_SYM_GEN_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal TX_CHAR_IS_K_Buffer : std_logic_vector(3 downto 0) := "0000";
- signal TX_DATA_Buffer : std_logic_vector(31 downto 0);
-
--- Internal Register Declarations --
-
- -- Slack registers. These registers allow slack for routing delay and automatic retiming.
-
- signal gen_scp_r : std_logic_vector(0 to 1);
- signal gen_ecp_r : std_logic_vector(0 to 1);
- signal gen_suf_r : std_logic_vector(0 to 1);
- signal gen_pad_r : std_logic_vector(0 to 1);
- signal fc_nb_r : std_logic_vector(0 to 7);
- signal tx_pe_data_r : std_logic_vector(0 to 31);
- signal tx_pe_data_v_r : std_logic_vector(0 to 1);
- signal gen_cc_r : std_logic;
- signal gen_a_r : std_logic;
- signal gen_k_r : std_logic_vector(0 to 3);
- signal gen_r_r : std_logic_vector(0 to 3);
- signal gen_v_r : std_logic_vector(0 to 3);
- signal gen_sp_r : std_logic;
- signal gen_spa_r : std_logic;
-
--- Wire Declarations --
-
- signal idle_c : std_logic_vector(0 to 3);
-
-begin
-
- TX_CHAR_IS_K <= TX_CHAR_IS_K_Buffer;
- TX_DATA <= TX_DATA_Buffer;
-
--- Main Body of Code --
-
- -- Register all inputs with the slack registers.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- gen_scp_r <= GEN_SCP after DLY;
- gen_ecp_r <= GEN_ECP after DLY;
- gen_suf_r <= GEN_SUF after DLY;
- gen_pad_r <= GEN_PAD after DLY;
- fc_nb_r <= FC_NB after DLY;
- tx_pe_data_r <= TX_PE_DATA after DLY;
- tx_pe_data_v_r <= TX_PE_DATA_V after DLY;
- gen_cc_r <= GEN_CC after DLY;
- gen_a_r <= GEN_A after DLY;
- gen_k_r <= GEN_K after DLY;
- gen_r_r <= GEN_R after DLY;
- gen_v_r <= GEN_V after DLY;
- gen_sp_r <= GEN_SP after DLY;
- gen_spa_r <= GEN_SPA after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 0 --
-
- -- When none of the byte0 non_idle inputs are asserted, allow idle characters.
-
- idle_c(0) <= not (gen_scp_r(0) or
- gen_ecp_r(0) or
- gen_suf_r(0) or
- tx_pe_data_v_r(0) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(0));
-
-
-
- -- Generate data for byte0. Note that all inputs must be asserted exclusively, except
- -- for the GEN_A, GEN_K and GEN_R inputs which are ignored when other characters
- -- are asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"5C" after DLY; -- K28.2(SCP)
-
- elsif (gen_ecp_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"FD" after DLY; -- K29.7(ECP)
-
- elsif (gen_suf_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"9C" after DLY; -- K28.4(SUF)
-
- elsif (tx_pe_data_v_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= tx_pe_data_r(0 to 7) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(0) and gen_a_r) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"7C" after DLY; -- K28.3(A)
-
- elsif ((idle_c(0) and gen_k_r(0)) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(0) and gen_r_r(0)) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"BC" after DLY; -- K28.5(K)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"BC" after DLY; -- K28.5(K)
-
- elsif (gen_v_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for MSB.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(3) <= not (tx_pe_data_v_r(0) or
- gen_v_r(0)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 1 --
-
- -- When none of the byte1 non_idle inputs are asserted, allow idle characters. Note
- -- that because gen_pad is only valid with the data valid signal, we only look at
- -- the data valid signal.
-
- idle_c(1) <= not (gen_scp_r(0) or
- gen_ecp_r(0) or
- gen_suf_r(0) or
- tx_pe_data_v_r(0) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(1));
-
-
- -- Generate data for byte1. Note that all inputs must be asserted exclusively except
- -- for the GEN_PAD signal and the GEN_K and GEN_R set. GEN_PAD can be asserted
- -- at the same time as TX_DATA_VALID. This will override TX_DATA valid and replace
- -- the lsb user data with a PAD character. The GEN_K and GEN_R inputs are
- -- ignored if any other input is asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(0) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"FB" after DLY; -- K27.7(SCP)
-
- elsif (gen_ecp_r(0) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"FE" after DLY; -- K30.7(ECP)
-
- elsif (gen_suf_r(0) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= fc_nb_r(0 to 3) & "0000" after DLY; -- SUF Data
-
- elsif ((tx_pe_data_v_r(0) and gen_pad_r(0)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"9C" after DLY; -- K28.4(PAD)
-
- elsif ((tx_pe_data_v_r(0) and not gen_pad_r(0)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= tx_pe_data_r(8 to 15) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(1) and gen_k_r(1)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(1) and gen_r_r(1)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"4A" after DLY; -- D10.2(SP data)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"2C" after DLY; -- D12.1(SPA data)
-
- elsif (gen_v_r(1) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for byte1.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(2) <= not ((tx_pe_data_v_r(0) and not gen_pad_r(0)) or
- gen_suf_r(0) or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(1)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 2 --
-
- -- When none of the byte2 non_idle inputs are asserted, allow idle characters.
-
- idle_c(2) <= not (gen_scp_r(1) or
- gen_ecp_r(1) or
- gen_suf_r(1) or
- tx_pe_data_v_r(1) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(2));
-
-
-
- -- Generate data for byte2. Note that all inputs must be asserted exclusively,
- -- except for the GEN_K and GEN_R inputs which are ignored when other
- -- characters are asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"5C" after DLY; -- K28.2(SCP)
-
- elsif (gen_ecp_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"FD" after DLY; -- K29.7(ECP)
-
- elsif (gen_suf_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"9C" after DLY; -- K28.4(SUF)
-
- elsif (tx_pe_data_v_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= tx_pe_data_r(16 to 23) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(2) and gen_k_r(2)) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(2) and gen_r_r(2)) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"4A" after DLY; -- D10.2(SP data)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"2C" after DLY; -- D12.1(SPA data)
-
- elsif (gen_v_r(2) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for MSB.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(1) <= not (tx_pe_data_v_r(1) or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(2)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 3 --
-
- -- When none of the byte3 non_idle inputs are asserted, allow idle characters.
- -- Note that because gen_pad is only valid with the data valid signal, we only
- -- look at the data valid signal.
-
- idle_c(3) <= not (gen_scp_r(1) or
- gen_ecp_r(1) or
- gen_suf_r(1) or
- tx_pe_data_v_r(1) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(3));
-
-
-
- -- Generate data for byte3. Note that all inputs must be asserted exclusively
- -- except for the GEN_PAD signal and the GEN_K and GEN_R set. GEN_PAD
- -- can be asserted at the same time as TX_DATA_VALID. This will override
- -- TX_DATA valid and replace the lsb user data with a PAD character. The GEN_K
- -- and GEN_R inputs are ignored if any other input is asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(1) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"FB" after DLY; -- K27.7(SCP)
-
- elsif (gen_ecp_r(1) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"FE" after DLY; -- K30.7(ECP)
-
- elsif (gen_suf_r(1) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= fc_nb_r(4 to 7) & "0000" after DLY; -- SUF Data
-
- elsif ((tx_pe_data_v_r(1) and gen_pad_r(1)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"9C" after DLY; -- K28.4(PAD)
-
- elsif ((tx_pe_data_v_r(1) and not gen_pad_r(1)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= tx_pe_data_r(24 to 31) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(3) and gen_k_r(3)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(3) and gen_r_r(3)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"4A" after DLY; -- D10.2(SP data)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"2C" after DLY; -- D12.1(SPA data)
-
- elsif (gen_v_r(3) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for byte3.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(0) <= not ((tx_pe_data_v_r(1) and not gen_pad_r(1)) or
- gen_suf_r(1) or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(3)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll.vhd
deleted file mode 100644
index 67392192316ac6c12d50990d01c71c700d3b920f..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll.vhd
+++ /dev/null
@@ -1,320 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- TX_LL
---
---
--- Description: The TX_LL module converts user data from the LocalLink interface
--- to Aurora Data, then sends it to the Aurora Channel for transmission.
--- It also handles NFC and UFC messages.
---
--- This module supports 2 4-byte lane designs
---
--- This module supports User Flow Control
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity east_channel_TX_LL is
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
-
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
-
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
-end east_channel_TX_LL;
-
-architecture MAPPED of east_channel_TX_LL is
-
--- External Register Declarations --
-
- signal TX_DST_RDY_N_Buffer : std_logic;
- signal UFC_TX_ACK_N_Buffer : std_logic;
- signal GEN_SCP_Buffer : std_logic;
- signal GEN_ECP_Buffer : std_logic;
- signal GEN_SUF_Buffer : std_logic;
- signal FC_NB_Buffer : std_logic_vector(0 to 3);
-signal TX_PE_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal GEN_PAD_Buffer : std_logic_vector(0 to 1);
-signal TX_PE_DATA_Buffer : std_logic_vector(0 to 31);
-signal GEN_CC_Buffer : std_logic;
-
--- Wire Declarations --
-
- signal halt_c_i : std_logic;
- signal tx_dst_rdy_n_i : std_logic;
-signal ufc_message_i : std_logic_vector(0 to 1);
-
--- Component Declarations --
-
- component east_channel_TX_LL_DATAPATH
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-
- -- Aurora Lane Interface
-
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-
- -- TX_LL Control Module Interface
-
- HALT_C : in std_logic;
- TX_DST_RDY_N : in std_logic;
-UFC_MESSAGE : in std_logic_vector(0 to 1);
-
- -- System Interface
-
- CHANNEL_UP : in std_logic;
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-
- component east_channel_TX_LL_CONTROL
-
- port (
-
- -- LocalLink PDU Interface
-
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-TX_REM : in std_logic_vector(0 to 1);
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
-
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
-
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- TX_LL Control Module Interface
-
- HALT_C : out std_logic;
-UFC_MESSAGE : out std_logic_vector(0 to 1);
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-begin
-
- TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
- UFC_TX_ACK_N <= UFC_TX_ACK_N_Buffer;
- GEN_SCP <= GEN_SCP_Buffer;
- GEN_ECP <= GEN_ECP_Buffer;
- GEN_SUF <= GEN_SUF_Buffer;
- FC_NB <= FC_NB_Buffer;
- TX_PE_DATA_V <= TX_PE_DATA_V_Buffer;
- GEN_PAD <= GEN_PAD_Buffer;
- TX_PE_DATA <= TX_PE_DATA_Buffer;
- GEN_CC <= GEN_CC_Buffer;
-
--- Main Body of Code --
-
- -- TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
- -- external modules to regulate incoming pdu data signals.
-
- TX_DST_RDY_N_Buffer <= tx_dst_rdy_n_i;
-
-
- -- TX_LL_Datapath module
-
- tx_ll_datapath_i : east_channel_TX_LL_DATAPATH
-
- port map (
-
- -- LocalLink PDU Interface
-
- TX_D => TX_D,
- TX_REM => TX_REM,
- TX_SRC_RDY_N => TX_SRC_RDY_N,
- TX_SOF_N => TX_SOF_N,
- TX_EOF_N => TX_EOF_N,
-
- -- Aurora Lane Interface
-
- TX_PE_DATA_V => TX_PE_DATA_V_Buffer,
- GEN_PAD => GEN_PAD_Buffer,
- TX_PE_DATA => TX_PE_DATA_Buffer,
-
- -- TX_LL Control Module Interface
-
- HALT_C => halt_c_i,
- TX_DST_RDY_N => tx_dst_rdy_n_i,
- UFC_MESSAGE => ufc_message_i,
-
- -- System Interface
-
- CHANNEL_UP => CHANNEL_UP,
- USER_CLK => USER_CLK
-
- );
-
-
- -- TX_LL_Control module
-
- tx_ll_control_i : east_channel_TX_LL_CONTROL
-
- port map (
-
- -- LocalLink PDU Interface
-
- TX_SRC_RDY_N => TX_SRC_RDY_N,
- TX_SOF_N => TX_SOF_N,
- TX_EOF_N => TX_EOF_N,
- TX_REM => TX_REM,
- TX_DST_RDY_N => tx_dst_rdy_n_i,
-
- -- UFC Interface
-
- UFC_TX_REQ_N => UFC_TX_REQ_N,
- UFC_TX_MS => UFC_TX_MS,
- UFC_TX_ACK_N => UFC_TX_ACK_N_Buffer,
-
- -- Clock Compensation Interface
-
- WARN_CC => WARN_CC,
- DO_CC => DO_CC,
-
- -- Global Logic Interface
-
- CHANNEL_UP => CHANNEL_UP,
-
- -- TX_LL Control Module Interface
-
- HALT_C => halt_c_i,
- UFC_MESSAGE => ufc_message_i,
-
- -- Aurora Lane Interface
-
- GEN_SCP => GEN_SCP_Buffer,
- GEN_ECP => GEN_ECP_Buffer,
- GEN_SUF => GEN_SUF_Buffer,
- FC_NB => FC_NB_Buffer,
- GEN_CC => GEN_CC_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK
-
- );
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll_control.vhd
deleted file mode 100644
index 45757c9a6517555ee39370968f271a4d1dd51df5..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll_control.vhd
+++ /dev/null
@@ -1,761 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- TX_LL_CONTROL
---
---
---
--- Description: This module provides the transmitter state machine
--- control logic to connect the LocalLink interface to
--- the Aurora Channel.
---
--- This module supports 2 4-byte lane designs
---
--- This module supports User Flow Control.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-entity east_channel_TX_LL_CONTROL is
-
- port (
-
- -- LocalLink PDU Interface
-
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-TX_REM : in std_logic_vector(0 to 1);
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
-
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
-
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- TX_LL Control Module Interface
-
- HALT_C : out std_logic;
-UFC_MESSAGE : out std_logic_vector(0 to 1);
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
-end east_channel_TX_LL_CONTROL;
-
-architecture RTL of east_channel_TX_LL_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal TX_DST_RDY_N_Buffer : std_logic;
- signal UFC_TX_ACK_N_Buffer : std_logic;
- signal HALT_C_Buffer : std_logic;
-signal UFC_MESSAGE_Buffer : std_logic_vector(0 to 1);
- signal GEN_SCP_Buffer : std_logic;
- signal GEN_ECP_Buffer : std_logic;
- signal GEN_SUF_Buffer : std_logic;
- signal FC_NB_Buffer : std_logic_vector(0 to 3);
-signal GEN_CC_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal do_cc_r : std_logic;
- signal ufc_idle_r : std_logic;
- signal ufc_header_r : std_logic;
- signal ufc_message1_r : std_logic;
- signal ufc_message2_r : std_logic;
- signal ufc_message3_r : std_logic;
- signal ufc_message4_r : std_logic;
- signal ufc_message5_r : std_logic;
- signal ufc_message6_r : std_logic;
- signal ufc_message7_r : std_logic;
- signal ufc_message8_r : std_logic;
-
- signal ufc_message_count_r : std_logic_vector(0 to 2);
-
- signal suf_delay_1_r : std_logic;
- signal suf_delay_2_r : std_logic;
-
- signal delay_ms_1_r : std_logic_vector(0 to 3);
- signal delay_ms_2_r : std_logic_vector(0 to 3);
-
- signal previous_cycle_ufc_message_r : std_logic;
- signal create_gap_for_scp_r : std_logic;
-
- signal idle_r : std_logic;
- signal sof_to_data_r : std_logic;
- signal data_r : std_logic;
- signal data_to_eof_1_r : std_logic;
- signal data_to_eof_2_r : std_logic;
- signal eof_r : std_logic;
- signal sof_to_eof_1_r : std_logic;
- signal sof_to_eof_2_r : std_logic;
- signal sof_and_eof_r : std_logic;
-
--- Wire Declarations --
-
- signal next_ufc_idle_c : std_logic;
- signal next_ufc_header_c : std_logic;
- signal next_ufc_message1_c : std_logic;
- signal next_ufc_message2_c : std_logic;
- signal next_ufc_message3_c : std_logic;
- signal next_ufc_message4_c : std_logic;
- signal next_ufc_message5_c : std_logic;
- signal next_ufc_message6_c : std_logic;
- signal next_ufc_message7_c : std_logic;
- signal next_ufc_message8_c : std_logic;
- signal ufc_ok_c : std_logic;
- signal create_gap_for_scp_c : std_logic;
-
- signal next_idle_c : std_logic;
- signal next_sof_to_data_c : std_logic;
- signal next_data_c : std_logic;
- signal next_data_to_eof_1_c : std_logic;
- signal next_data_to_eof_2_c : std_logic;
- signal next_eof_c : std_logic;
- signal next_sof_to_eof_1_c : std_logic;
- signal next_sof_to_eof_2_c : std_logic;
- signal next_sof_and_eof_c : std_logic;
-
- signal fc_nb_c : std_logic_vector(0 to 3);
- signal tx_dst_rdy_n_c : std_logic;
- signal do_sof_c : std_logic;
- signal do_eof_c : std_logic;
- signal channel_full_c : std_logic;
- signal pdu_ok_c : std_logic;
-
--- Declarations to handle VHDL limitations
- signal reset_i : std_logic;
-
--- Component Declarations --
-
- component FDR
-
- generic (INIT : bit := '0');
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic;
- R : in std_ulogic
-
- );
-
- end component;
-
-begin
-
- TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
- UFC_TX_ACK_N <= UFC_TX_ACK_N_Buffer;
- HALT_C <= HALT_C_Buffer;
- UFC_MESSAGE <= UFC_MESSAGE_Buffer;
- GEN_SCP <= GEN_SCP_Buffer;
- GEN_ECP <= GEN_ECP_Buffer;
- GEN_SUF <= GEN_SUF_Buffer;
- FC_NB <= FC_NB_Buffer;
- GEN_CC <= GEN_CC_Buffer;
-
--- Main Body of Code --
-
-
-
- reset_i <= not CHANNEL_UP;
-
-
- -- Clock Compensation --
-
- -- Register the DO_CC and WARN_CC signals for internal use. Note that the raw DO_CC
- -- signal is used for some logic so the DO_CC signal should be driven directly
- -- from a register whenever possible.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- do_cc_r <= DO_CC after DLY;
- end if;
-
- end process;
-
-
-
- -- UFC State Machine --
-
- -- The UFC state machine has 10 states: waiting for a UFC request, sending
- -- a UFC header, and 8 states for sending up to 8 words of a UFC message.
- -- It can take over the channel at any time except when there is an NFC
- -- message or a CC sequence being sent.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- ufc_idle_r <= '1' after DLY;
- ufc_header_r <= '0' after DLY;
- ufc_message1_r <= '0' after DLY;
- ufc_message2_r <= '0' after DLY;
- ufc_message3_r <= '0' after DLY;
- ufc_message4_r <= '0' after DLY;
- ufc_message5_r <= '0' after DLY;
- ufc_message6_r <= '0' after DLY;
- ufc_message7_r <= '0' after DLY;
- ufc_message8_r <= '0' after DLY;
-
- else
-
- ufc_idle_r <= next_ufc_idle_c after DLY;
- ufc_header_r <= next_ufc_header_c after DLY;
- ufc_message1_r <= next_ufc_message1_c after DLY;
- ufc_message2_r <= next_ufc_message2_c after DLY;
- ufc_message3_r <= next_ufc_message3_c after DLY;
- ufc_message4_r <= next_ufc_message4_c after DLY;
- ufc_message5_r <= next_ufc_message5_c after DLY;
- ufc_message6_r <= next_ufc_message6_c after DLY;
- ufc_message7_r <= next_ufc_message7_c after DLY;
- ufc_message8_r <= next_ufc_message8_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Capture the message count so it can be used to determine the appropriate
- -- next state.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (next_ufc_header_c = '1') then
-
- ufc_message_count_r <= UFC_TX_MS(0 to 2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
-
- next_ufc_idle_c <= ((UFC_TX_REQ_N or not ufc_ok_c) and
- ((ufc_idle_r) or
- (ufc_message1_r) or
- (ufc_message2_r and std_bool(ufc_message_count_r = "001")) or
- (ufc_message3_r) or
- (ufc_message4_r and std_bool(ufc_message_count_r = "011")) or
- (ufc_message5_r) or
- (ufc_message6_r and std_bool(ufc_message_count_r = "101")) or
- (ufc_message7_r) or
- (ufc_message8_r and std_bool(ufc_message_count_r = "111"))));
-
-
- next_ufc_header_c <= ((not UFC_TX_REQ_N and ufc_ok_c) and
- ((ufc_idle_r) or
- (ufc_message1_r) or
- (ufc_message2_r and std_bool(ufc_message_count_r = "001")) or
- (ufc_message3_r) or
- (ufc_message4_r and std_bool(ufc_message_count_r = "011")) or
- (ufc_message5_r) or
- (ufc_message6_r and std_bool(ufc_message_count_r = "101")) or
- (ufc_message7_r) or
- (ufc_message8_r and std_bool(ufc_message_count_r = "111"))));
-
-
- next_ufc_message1_c <= ufc_header_r and std_bool(ufc_message_count_r = "000");
-
- next_ufc_message2_c <= ufc_header_r and std_bool(ufc_message_count_r > "000");
-
- next_ufc_message3_c <= ufc_message2_r and std_bool(ufc_message_count_r = "010");
-
- next_ufc_message4_c <= ufc_message2_r and std_bool(ufc_message_count_r > "010");
-
- next_ufc_message5_c <= ufc_message4_r and std_bool(ufc_message_count_r = "100");
-
- next_ufc_message6_c <= ufc_message4_r and std_bool(ufc_message_count_r > "100");
-
- next_ufc_message7_c <= ufc_message6_r and std_bool(ufc_message_count_r = "110");
-
- next_ufc_message8_c <= ufc_message6_r and std_bool(ufc_message_count_r = "111");
-
- UFC_MESSAGE_Buffer(0) <= not ufc_idle_r and not ufc_header_r;
-
- UFC_MESSAGE_Buffer(1) <= ufc_message2_r or
- ufc_message4_r or
- ufc_message6_r or
- ufc_message8_r;
-
-
- ufc_ok_c <= not DO_CC and not WARN_CC;
-
-
- UFC_TX_ACK_N_Buffer <= not ufc_header_r;
-
-
- -- Delay UFC_TX_MS so it arrives at the lanes at the same time as the
- -- UFC header.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- delay_ms_1_r <= UFC_TX_MS after DLY;
- delay_ms_2_r <= delay_ms_1_r after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- previous_cycle_ufc_message_r <= not ufc_idle_r and not ufc_header_r after DLY;
-
- end if;
-
- end process;
-
-
- -- PDU State Machine --
-
- -- The PDU state machine handles the encapsulation and transmission of user
- -- PDUs. It can use the channel when there is no CC, NFC message, UFC header,
- -- UFC message or remote NFC request.
-
- -- State Registers
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- idle_r <= '1' after DLY;
- sof_to_data_r <= '0' after DLY;
- data_r <= '0' after DLY;
- data_to_eof_1_r <= '0' after DLY;
- data_to_eof_2_r <= '0' after DLY;
- eof_r <= '0' after DLY;
- sof_to_eof_1_r <= '0' after DLY;
- sof_to_eof_2_r <= '0' after DLY;
- sof_and_eof_r <= '0' after DLY;
-
- else
-
- if (pdu_ok_c = '1') then
-
- idle_r <= next_idle_c after DLY;
- sof_to_data_r <= next_sof_to_data_c after DLY;
- data_r <= next_data_c after DLY;
- data_to_eof_1_r <= next_data_to_eof_1_c after DLY;
- data_to_eof_2_r <= next_data_to_eof_2_c after DLY;
- eof_r <= next_eof_c after DLY;
- sof_to_eof_1_r <= next_sof_to_eof_1_c after DLY;
- sof_to_eof_2_r <= next_sof_to_eof_2_c after DLY;
- sof_and_eof_r <= next_sof_and_eof_c after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Next State Logic
-
- next_idle_c <= (idle_r and not do_sof_c) or
- (data_to_eof_2_r and not do_sof_c) or
- (eof_r and not do_sof_c ) or
- (sof_to_eof_2_r and not do_sof_c) or
- (sof_and_eof_r and not do_sof_c);
-
-
- next_sof_to_data_c <= ((idle_r and do_sof_c) and not do_eof_c) or
- ((data_to_eof_2_r and do_sof_c) and not do_eof_c) or
- ((eof_r and do_sof_c) and not do_eof_c) or
- ((sof_to_eof_2_r and do_sof_c) and not do_eof_c) or
- ((sof_and_eof_r and do_sof_c) and not do_eof_c);
-
-
- next_data_c <= (sof_to_data_r and not do_eof_c) or
- (data_r and not do_eof_c);
-
-
- next_data_to_eof_1_c <= (sof_to_data_r and do_eof_c and channel_full_c) or
- (data_r and do_eof_c and channel_full_c);
-
-
- next_data_to_eof_2_c <= data_to_eof_1_r;
-
-
- next_eof_c <= (sof_to_data_r and do_eof_c and not channel_full_c) or
- (data_r and do_eof_c and not channel_full_c);
-
-
- next_sof_to_eof_1_c <= (idle_r and do_sof_c and do_eof_c and channel_full_c) or
- (data_to_eof_2_r and do_sof_c and do_eof_c and channel_full_c) or
- (eof_r and do_sof_c and do_eof_c and channel_full_c) or
- (sof_to_eof_2_r and do_sof_c and do_eof_c and channel_full_c) or
- (sof_and_eof_r and do_sof_c and do_eof_c and channel_full_c);
-
-
- next_sof_to_eof_2_c <= sof_to_eof_1_r;
-
-
- next_sof_and_eof_c <= (idle_r and do_sof_c and do_eof_c and not channel_full_c) or
- (data_to_eof_2_r and do_sof_c and do_eof_c and not channel_full_c) or
- (eof_r and do_sof_c and do_eof_c and not channel_full_c) or
- (sof_to_eof_2_r and do_sof_c and do_eof_c and not channel_full_c) or
- (sof_and_eof_r and do_sof_c and do_eof_c and not channel_full_c);
-
-
- -- Drive the GEN_SCP signal when in an SOF state with the PDU state machine active.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- GEN_SCP_Buffer <= '0' after DLY;
-
- else
-
- GEN_SCP_Buffer <= (sof_to_data_r or
- sof_to_eof_1_r or
- sof_and_eof_r) and
- pdu_ok_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Drive the GEN_ECP signal when in an EOF state with the PDU state machine active.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- GEN_ECP_Buffer <= '0' after DLY;
-
- else
-
- GEN_ECP_Buffer <= (data_to_eof_2_r or
- eof_r or
- sof_to_eof_2_r or
- sof_and_eof_r) and
- pdu_ok_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- TX_DST_RDY is the critical path in this module. It must be deasserted (high)
- -- whenever an event occurs that prevents the pdu state machine from using the
- -- Aurora channel to transmit PDUs.
-
- tx_dst_rdy_n_c <= (next_data_to_eof_1_c and pdu_ok_c) or
- not next_ufc_idle_c or
- DO_CC or
- create_gap_for_scp_c or
- (next_sof_to_eof_1_c and pdu_ok_c) or
- (sof_to_eof_1_r and not pdu_ok_c) or
- (data_to_eof_1_r and not pdu_ok_c);
-
-
- -- SCP characters can only be added when the first lane position is open. After UFC messages,
- -- data gets deliberately held off for one cycle to create this gap. No gap is added if no
- -- SCP character is needed.
-
- create_gap_for_scp_c <= (not ufc_idle_r and not ufc_header_r) and
- not (data_r or
- sof_to_data_r or
- data_to_eof_1_r or
- sof_to_eof_1_r);
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- create_gap_for_scp_r <= create_gap_for_scp_c after DLY;
-
- end if;
-
- end process;
-
-
- -- The flops for the GEN_CC signal are replicated for timing and instantiated to allow us
- -- to set their value reliably on powerup.
-
- gen_cc_flop_0_i : FDR
-
- port map (
-
- D => do_cc_r,
- C => USER_CLK,
- R => '0',
- -- R => reset_i,
- Q => GEN_CC_Buffer
-
- );
-
-
- -- The UFC header state triggers the generation of SUF characters in the lane. The signal is
- -- delayed to match up with the datapath delay so that SUF always appears on the cycle
- -- before the first data byte.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- suf_delay_1_r <= '0' after DLY;
-
- else
-
- suf_delay_1_r <= ufc_header_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(CHANNEL_UP = '0') then
-
- suf_delay_2_r <= '0' after DLY;
-
- else
-
- suf_delay_2_r <= suf_delay_1_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- GEN_SUF_Buffer <= '0' after DLY;
-
- else
-
- GEN_SUF_Buffer <= suf_delay_2_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- FC_NB carries flow control codes to the Lane Logic.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- FC_NB_Buffer <= fc_nb_c after DLY;
-
- end if;
-
- end process;
-
-
- -- Flow control codes come from the UFC_TX_MS input delayed to match the UFC data delay.
-
- fc_nb_c <= delay_ms_2_r;
-
-
- -- The TX_DST_RDY_N signal is registered.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- TX_DST_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- TX_DST_RDY_N_Buffer <= tx_dst_rdy_n_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Helper Logic
-
- -- SOF requests are valid when TX_SRC_RDY_N. TX_DST_RDY_N and TX_SOF_N are asserted
-
- do_sof_c <= not TX_SRC_RDY_N and
- not TX_DST_RDY_N_Buffer and
- not TX_SOF_N;
-
-
- -- EOF requests are valid when TX_SRC_RDY_N, TX_DST_RDY_N and TX_EOF_N are asserted
-
- do_eof_c <= not TX_SRC_RDY_N and
- not TX_DST_RDY_N_Buffer and
- not TX_EOF_N;
-
-
-
- -- Freeze the PDU state machine when CCs must be handled. Note that the PDU state machine
- -- does not freeze for UFCs - instead, logic is provided to allow the two datastreams
- -- to cooperate.
-
- pdu_ok_c <= not do_cc_r;
-
-
- -- Halt the flow of data through the datastream when the PDU state machine is frozen or
- -- when an SCP character has been delayed due to UFC collision.
-
- HALT_C_Buffer <= not pdu_ok_c;
-
-
- -- The aurora channel is 'full' if there is more than enough data to fit into
- -- a channel that is already carrying an SCP and an ECP character.
-
- channel_full_c <= '1';
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll_datapath.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll_datapath.vhd
deleted file mode 100644
index 04e175bff35c6e0043e3203cb8b9d053265779aa..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_tx_ll_datapath.vhd
+++ /dev/null
@@ -1,399 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- TX_LL_DATAPATH
---
---
--- Description: This module pipelines the data path while handling the PAD
--- character placement and valid data flags.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity east_channel_TX_LL_DATAPATH is
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-
- -- Aurora Lane Interface
-
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-
- -- TX_LL Control Module Interface
-
- HALT_C : in std_logic;
- TX_DST_RDY_N : in std_logic;
-UFC_MESSAGE : in std_logic_vector(0 to 1);
-
- -- System Interface
-
- CHANNEL_UP : in std_logic;
- USER_CLK : in std_logic
-
- );
-
-end east_channel_TX_LL_DATAPATH;
-
-architecture RTL of east_channel_TX_LL_DATAPATH is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
-signal TX_PE_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal GEN_PAD_Buffer : std_logic_vector(0 to 1);
-signal TX_PE_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
-signal in_frame_r : std_logic;
-signal storage_r : std_logic_vector(0 to 15);
-signal storage_v_r : std_logic;
-signal storage_ufc_v_r : std_logic;
-signal storage_pad_r : std_logic;
-signal tx_pe_data_r : std_logic_vector(0 to 31);
-signal valid_c : std_logic_vector(0 to 1);
-signal tx_pe_data_v_r : std_logic_vector(0 to 1);
-signal tx_pe_ufc_v_r : std_logic_vector(0 to 1);
-signal gen_pad_c : std_logic_vector(0 to 1);
-signal gen_pad_r : std_logic_vector(0 to 1);
-
--- Internal Wire Declarations --
-
-signal ll_valid_c : std_logic;
-signal in_frame_c : std_logic;
-
-begin
-
- TX_PE_DATA_V <= TX_PE_DATA_V_Buffer;
- GEN_PAD <= GEN_PAD_Buffer;
- TX_PE_DATA <= TX_PE_DATA_Buffer;
-
--- Main Body of Code --
-
-
-
- -- LocalLink input is only valid when TX_SRC_RDY_N and TX_DST_RDY_N are both asserted
- ll_valid_c <= not TX_SRC_RDY_N and not TX_DST_RDY_N;
-
-
- -- Data must only be read if it is within a frame. If a frame will last multiple cycles
- -- we assert in_frame_r as long as the frame is open.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(CHANNEL_UP = '0') then
- in_frame_r <= '0' after DLY;
- elsif(ll_valid_c = '1') then
- if( (TX_SOF_N = '0') and (TX_EOF_N = '1') ) then
- in_frame_r <= '1' after DLY;
- elsif( TX_EOF_N = '0') then
- in_frame_r <= '0' after DLY;
- end if;
- end if;
- end if;
- end process;
-
-
- in_frame_c <= ll_valid_c and (in_frame_r or not TX_SOF_N);
-
-
-
-
- -- The last 2 bytes of data from the LocalLink interface must be stored
- -- for the next cycle to make room for the SCP character that must be
- -- placed at the beginning of the lane.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- storage_r <= TX_D(16 to 31) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
-
- -- All of the remaining bytes (except the last two) must be shifted
- -- and registered to be sent to the Channel. The stored bytes go
- -- into the first position.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- tx_pe_data_r <= storage_r & TX_D(0 to 15) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- We generate the valid_c signal based on the REM signal and the EOF signal.
-
- process (TX_EOF_N, TX_REM)
-
- begin
-
- if (TX_EOF_N = '1') then
-
-valid_c <= "11";
-
- else
-
- case TX_REM(0 to 1) is
-
-when "00" => valid_c <= "10";
-when "01" => valid_c <= "10";
-when "10" => valid_c <= "11";
-when "11" => valid_c <= "11";
-when others => valid_c <= "11";
-
- end case;
-
- end if;
-
- end process;
-
-
- -- If the last 2 bytes in the word are valid, they are placed in the storage register and
- -- storage_v_r is asserted to indicate the data is valid. Note that data is only moved to
- -- storage if the PDU datapath is not halted, the data is valid and both TX_SRC_RDY_N
- -- and TX_DST_RDY_N are asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C ='0') then
-
- storage_v_r <= valid_c(1) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The storage_ufc_v_r register is asserted when valid UFC data is placed in the storage register.
- -- Note that UFC data cannot be halted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- storage_ufc_v_r <= UFC_MESSAGE(1) after DLY;
-
- end if;
-
- end process;
-
-
- -- The tx_pe_data_v_r registers track valid data in the TX_PE_DATA register. The data is valid
- -- if it was valid in the previous stage. Since the first 2 bytes come from storage, validity is
- -- determined from the storage_v_r signal. The remaining bytes are valid if their valid signal
- -- is asserted, and both TX_SRC_RDY_N and TX_DST_RDY_N are asserted.
- -- Note that pdu data movement can be frozen by the halt signal.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- tx_pe_data_v_r(0) <= storage_v_r after DLY;
- tx_pe_data_v_r(1) <= valid_c(0) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The tx_pe_ufc_v_r register tracks valid ufc data in the tx_pe_data_register. The first 2 bytes
- -- come from storage: they are valid if storage_ufc_v_r was asserted. The remaining bytes come from
- -- the TX_D input. They are valid if UFC_MESSAGE was high when they were exampled. Note that UFC data
- -- cannot be halted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- tx_pe_ufc_v_r(0) <= storage_ufc_v_r after DLY;
- tx_pe_ufc_v_r(1) <= UFC_MESSAGE(0) after DLY;
-
- end if;
-
- end process;
-
-
- -- We generate the gen_pad_c signal based on the REM signal and the EOF signal.
-
- process (TX_EOF_N, TX_REM)
-
- begin
-
- if (TX_EOF_N = '1') then
-
-gen_pad_c <= "00";
-
- else
-
- case TX_REM(0 to 1) is
-
-when "00" => gen_pad_c <= "10";
-when "01" => gen_pad_c <= "00";
-when "10" => gen_pad_c <= "01";
-when "11" => gen_pad_c <= "00";
-when others => gen_pad_c <= "00";
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Store a byte with a pad if TX_DST_RDY_N and TX_SRC_RDY_N is asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- storage_pad_r <= gen_pad_c(1) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Register the gen_pad_r signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- gen_pad_r(0) <= storage_pad_r after DLY;
- gen_pad_r(1) <= gen_pad_c(0) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Implement the data out register.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- TX_PE_DATA_Buffer <= tx_pe_data_r after DLY;
- TX_PE_DATA_V_Buffer(0) <= (tx_pe_data_v_r(0) and not HALT_C) or tx_pe_ufc_v_r(0) after DLY;
- TX_PE_DATA_V_Buffer(1) <= (tx_pe_data_v_r(1) and not HALT_C) or tx_pe_ufc_v_r(1) after DLY;
- GEN_PAD_Buffer(0) <= (gen_pad_r(0) and not HALT_C) and not tx_pe_ufc_v_r(0) after DLY;
- GEN_PAD_Buffer(1) <= (gen_pad_r(1) and not HALT_C) and not tx_pe_ufc_v_r(1) after DLY;
-
- end if;
-
- end process;
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_barrel_shifter.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_barrel_shifter.vhd
deleted file mode 100644
index bc09d784fcff91e49cd2d23f7a17c502495cb403..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_barrel_shifter.vhd
+++ /dev/null
@@ -1,166 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_BARREL_SHIFTER
---
---
---
--- Description: the UFC_BARREL shifter is a barrel shifter that takes UFC
--- message data from the Aurora channel and left aligns it.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_UFC_BARREL_SHIFTER is
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTER_CONTROL : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- -- Mux output
-
- SHIFTED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end east_channel_UFC_BARREL_SHIFTER;
-
-architecture RTL of east_channel_UFC_BARREL_SHIFTER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal SHIFTED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal ufc_select_c : std_logic_vector(0 to 1);
- signal shifted_data_c : std_logic_vector(0 to 31);
-
-begin
-
- SHIFTED_DATA <= SHIFTED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- Muxes for barrel shifting --
-
- -- Mux for lane 0
-
- process (BARREL_SHIFTER_CONTROL, RAW_DATA)
-
- begin
-
- case BARREL_SHIFTER_CONTROL is
-
-when "00" =>
-
- shifted_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "01" =>
-
- shifted_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- shifted_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (BARREL_SHIFTER_CONTROL, RAW_DATA)
-
- begin
-
- case BARREL_SHIFTER_CONTROL is
-
-when "00" =>
-
- shifted_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- shifted_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the output.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- SHIFTED_DATA_Buffer <= shifted_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_barrel_shifter_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_barrel_shifter_control.vhd
deleted file mode 100644
index 0701700fa58e37aedbaeff16c2aa0b77b6fb3a4d..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_barrel_shifter_control.vhd
+++ /dev/null
@@ -1,131 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_BARREL_SHIFTER_CONTROL
---
---
---
--- Description: this module controls the UFC barrel shifter
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_UFC_BARREL_SHIFTER_CONTROL is
-
- port (
-
- UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- BARREL_SHIFTER_CONTROL : out std_logic_vector(0 to 1)
-
- );
-
-end east_channel_UFC_BARREL_SHIFTER_CONTROL;
-
-architecture RTL of east_channel_UFC_BARREL_SHIFTER_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal BARREL_SHIFTER_CONTROL_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal barrel_shifter_control_i : std_logic_vector(0 to 1);
-
-begin
-
- BARREL_SHIFTER_CONTROL <= BARREL_SHIFTER_CONTROL_Buffer;
-
--- Main Body of Code --
-
- -- Control for barrel shifting --
-
- -- Generate a barrel shift control number, which indicates how far to the left all the
- -- lane data should be shifted.
-
- process (UFC_MESSAGE_START)
-
- begin
-
- if (UFC_MESSAGE_START(0) = '1') then
-
- barrel_shifter_control_i <= conv_std_logic_vector(1,2);
-
- else
-
- barrel_shifter_control_i <= (others => '0');
-
- end if;
-
- end process;
-
-
- -- Register the barrel shifter control number
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- BARREL_SHIFTER_CONTROL_Buffer <= barrel_shifter_control_i after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_filter.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_filter.vhd
deleted file mode 100644
index 98f6b61313689c8a1ee0910b936ee17f7d3a5644..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_filter.vhd
+++ /dev/null
@@ -1,757 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--------------------------------------------------------------------------------
---
--- UFC_FILTER
---
---
---
--- Description: The UFC module separates data into UFC data and regular data.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_UFC_FILTER is
-
- port (
-
- -- Aurora Channel Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- PDU Datapath Interface
-
-PDU_DATA : out std_logic_vector(0 to 31);
-PDU_DATA_V : out std_logic_vector(0 to 1);
-PDU_PAD : out std_logic_vector(0 to 1);
-PDU_SCP : out std_logic_vector(0 to 1);
-PDU_ECP : out std_logic_vector(0 to 1);
-
- -- UFC Datapath Interface
-
-UFC_DATA : out std_logic_vector(0 to 31);
-UFC_DATA_V : out std_logic_vector(0 to 1);
-UFC_MESSAGE_START : out std_logic_vector(0 to 1);
- UFC_START : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_UFC_FILTER;
-
-architecture RTL of east_channel_UFC_FILTER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
-signal PDU_DATA_Buffer : std_logic_vector(0 to 31);
-signal PDU_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal PDU_PAD_Buffer : std_logic_vector(0 to 1);
-signal PDU_SCP_Buffer : std_logic_vector(0 to 1);
-signal PDU_ECP_Buffer : std_logic_vector(0 to 1);
-signal UFC_DATA_Buffer : std_logic_vector(0 to 31);
-signal UFC_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal UFC_MESSAGE_START_Buffer : std_logic_vector(0 to 1);
- signal UFC_START_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal stage_1_lane_mask_0_c : std_logic_vector(0 to 1);
- signal stage_1_count_value_0_c : std_logic_vector(0 to 3);
- signal stage_1_lane_mask_1_c : std_logic_vector(0 to 1);
- signal stage_1_count_value_1_c : std_logic_vector(0 to 3);
-signal stage_1_lane_mask_r : std_logic_vector(0 to 1);
- signal stage_1_count_value_r : std_logic_vector(0 to 3);
- signal load_ufc_control_code_r : std_logic;
-signal rx_data_v_r : std_logic_vector(0 to 1);
-signal rx_suf_r : std_logic_vector(0 to 1);
-signal rx_pad_r : std_logic_vector(0 to 1);
-signal rx_pe_data_r : std_logic_vector(0 to 31);
-signal rx_scp_r : std_logic_vector(0 to 1);
-signal rx_ecp_r : std_logic_vector(0 to 1);
- signal stage_2_count_value_r : std_logic_vector(0 to 3);
-signal stage_2_lane_mask_c : std_logic_vector(0 to 1);
- signal stage_2_count_value_c : std_logic_vector(0 to 3);
- signal save_start_r : std_logic;
-
-begin
-
- PDU_DATA <= PDU_DATA_Buffer;
- PDU_DATA_V <= PDU_DATA_V_Buffer;
- PDU_PAD <= PDU_PAD_Buffer;
- PDU_SCP <= PDU_SCP_Buffer;
- PDU_ECP <= PDU_ECP_Buffer;
- UFC_DATA <= UFC_DATA_Buffer;
- UFC_DATA_V <= UFC_DATA_V_Buffer;
- UFC_MESSAGE_START <= UFC_MESSAGE_START_Buffer;
- UFC_START <= UFC_START_Buffer;
-
--- Main Body of Code --
-
- -- Stage 1 --
-
- -- Decode a lane mask value for each lane. The lane mask indicates which lanes in the
- -- current cycle contain UFC data.
-
- -- Lane mask for lane 0.
-
- process (RX_FC_NB(0 to 2))
-
- begin
-
- case RX_FC_NB(0 to 2) is
-
- when "000" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "001" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "010" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "011" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "100" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "101" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "110" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "111" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when others =>
-
- stage_1_lane_mask_0_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Lane mask for lane 1.
-
- process (RX_FC_NB(4 to 6))
-
- begin
-
- case RX_FC_NB(4 to 6) is
-
- when "000" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "001" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "010" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "011" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "100" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "101" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "110" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "111" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when others =>
-
- stage_1_lane_mask_1_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Decode a count value for each lane. The count value indicates the number of lanes in
- -- the cycles that will follow will contain UFC data, based on the current FC_NB value
- -- and its lane position.
-
- -- Count value for lane 0.
-
- process (RX_FC_NB(0 to 2))
-
- begin
-
- case RX_FC_NB(0 to 2) is
-
- when "000" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(0,4);
-
- when "001" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(1,4);
-
- when "010" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(2,4);
-
- when "011" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(3,4);
-
- when "100" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(4,4);
-
- when "101" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(5,4);
-
- when "110" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(6,4);
-
- when "111" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(7,4);
-
- when others =>
-
- stage_1_count_value_0_c <= "0000";
-
- end case;
-
- end process;
-
-
- -- Count value for lane 1.
-
- process (RX_FC_NB(4 to 6))
-
- begin
-
- case RX_FC_NB(4 to 6) is
-
- when "000" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(1,4);
-
- when "001" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(2,4);
-
- when "010" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(3,4);
-
- when "011" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(4,4);
-
- when "100" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(5,4);
-
- when "101" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(6,4);
-
- when "110" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(7,4);
-
- when "111" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(8,4);
-
- when others =>
-
- stage_1_count_value_1_c <= "0000";
-
- end case;
-
- end process;
-
-
- -- Select and store the lane mask from the lane that contained the UFC message header.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_1_lane_mask_r <= (others => '0') after DLY;
-
- else
-
- if (RX_SUF(0) = '1') then
-
- stage_1_lane_mask_r <= stage_1_lane_mask_0_c after DLY;
-
- elsif (RX_SUF(1) = '1') then
-
- stage_1_lane_mask_r <= stage_1_lane_mask_1_c after DLY;
-
- else
-
- stage_1_lane_mask_r <= (others => '0') after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Select and store the count value from the lane that contained the UFC message header.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_1_count_value_r <= "0000" after DLY;
-
- else
-
- if (RX_SUF(1) = '1') then
-
- stage_1_count_value_r <= stage_1_count_value_1_c after DLY;
-
- elsif (RX_SUF(0) = '1') then
-
- stage_1_count_value_r <= stage_1_count_value_0_c after DLY;
-
- else
-
- stage_1_count_value_r <= "0000" after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Register a load flag if any of the SUF flags are high.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- load_ufc_control_code_r <= '0' after DLY;
-
- else
-
-if (RX_SUF /= "00") then
-
- load_ufc_control_code_r <= '1' after DLY;
-
- else
-
- load_ufc_control_code_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the data valid signal and the RX_SUF signal: they need reset.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- rx_data_v_r <= (others => '0') after DLY;
- rx_suf_r <= (others => '0') after DLY;
-
- else
-
- rx_data_v_r <= RX_PE_DATA_V after DLY;
- rx_suf_r <= RX_SUF after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the remaining signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pad_r <= RX_PAD after DLY;
- rx_pe_data_r <= RX_PE_DATA after DLY;
- rx_scp_r <= RX_SCP after DLY;
- rx_ecp_r <= RX_ECP after DLY;
-
- end if;
-
- end process;
-
-
- -- Stage 2 --
-
- -- If a new message was started in the previous cycle, load the new message size value into a
- -- counter. Otherwise, continue to process the previous count.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_2_count_value_r <= "0000" after DLY;
-
- else
-
- if (load_ufc_control_code_r = '1') then
-
- stage_2_count_value_r <= stage_1_count_value_r after DLY;
-
- else
-
- stage_2_count_value_r <= stage_2_count_value_c after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate a lane mask based on previous count.
-
- process (stage_2_count_value_r)
-
- begin
-
- case stage_2_count_value_r is
-
- when "0001" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(2,2);
-
- when "0010" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0011" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0100" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0101" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0110" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0111" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "1000" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when others =>
-
- stage_2_lane_mask_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Generate a new lane count based on previous count.
-
- process (stage_2_count_value_r)
-
- begin
-
- case stage_2_count_value_r is
-
- when "0001" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(0,4);
-
- when "0010" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(0,4);
-
- when "0011" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(1,4);
-
- when "0100" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(2,4);
-
- when "0101" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(3,4);
-
- when "0110" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(4,4);
-
- when "0111" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(5,4);
-
- when "1000" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(6,4);
-
- when others =>
-
- stage_2_count_value_c <= "0000";
-
- end case;
-
- end process;
-
-
- -- For each lane, mask the valid bit based on the incoming valid signal and the stage 1 and stage 2 lane masks.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- PDU_DATA_V_Buffer <= (others => '0') after DLY;
-
- else
-
- PDU_DATA_V_Buffer <= rx_data_v_r and (not stage_1_lane_mask_r and not stage_2_lane_mask_c) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- For each lane, the lane mask serves as a data valid signal for the UFC data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_DATA_V_Buffer <= (others => '0') after DLY;
-
- else
-
- UFC_DATA_V_Buffer <= stage_1_lane_mask_r or stage_2_lane_mask_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Save start signals from ufc headers that appeared at the end of previous cycles.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- save_start_r <= '0' after DLY;
-
- else
-
- save_start_r <= rx_suf_r(1) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate the UFC_MESSAGE_START and the UFC_START signals
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_MESSAGE_START_Buffer <= (others => '0') after DLY;
- UFC_START_Buffer <= '0' after DLY;
-
- else
-
- UFC_MESSAGE_START_Buffer <= rx_suf_r after DLY;
-
-if (rx_suf_r(0 to 0) & save_start_r /= "00") then
-
- UFC_START_Buffer <= '1' after DLY;
-
- else
-
- UFC_START_Buffer <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the remaining signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- PDU_PAD_Buffer <= rx_pad_r after DLY;
- PDU_DATA_Buffer <= rx_pe_data_r after DLY;
- UFC_DATA_Buffer <= rx_pe_data_r after DLY;
- PDU_SCP_Buffer <= rx_scp_r after DLY;
- PDU_ECP_Buffer <= rx_ecp_r after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_output_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_output_mux.vhd
deleted file mode 100644
index a678121384dafbaa6288e7106e07a94544874404..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_output_mux.vhd
+++ /dev/null
@@ -1,150 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_OUTPUT_MUX
---
---
---
--- Description: the UFC_OUTPUT mux moves selected data from ufc storage and the
--- ufc barrel shifter to the ufc LocalLink output register. It
--- is made up of a series of muxes, one set for each lane. The
--- number of selections available for each mux increments with
--- lane position. The first lane has only one possible input, the
--- nth lane has N inputs.
--- Note that the 0th selection for each mux is connected to the
--- UFC storage input, and the remaining selections are connected
--- to the barrel-shifted input lanes in incrementing order.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_UFC_OUTPUT_MUX is
-
- port (
-
- -- Input interface to the muxes
-
- UFC_STORAGE_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end east_channel_UFC_OUTPUT_MUX;
-
-architecture RTL of east_channel_UFC_OUTPUT_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal MUXED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal muxed_data_c : std_logic_vector(0 to 31);
-
-begin
-
- MUXED_DATA <= MUXED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create a set of muxes for each lane.
-
- -- Lane 0 needs no mux, it is always connected to the storage lane.
-
- -- Mux for lane 1
-
- process (MUX_SELECT(3 to 5), UFC_STORAGE_DATA, BARREL_SHIFTED_DATA)
-
- begin
-
- case MUX_SELECT(3 to 5) is
-
-when "000" =>
-
- muxed_data_c(16 to 31) <= UFC_STORAGE_DATA(16 to 31);
-
-when "001" =>
-
- muxed_data_c(16 to 31) <= BARREL_SHIFTED_DATA(0 to 15);
-
- when others =>
-
- muxed_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- MUXED_DATA_Buffer <= UFC_STORAGE_DATA(0 to 15) & muxed_data_c(16 to 31) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_output_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_output_switch_control.vhd
deleted file mode 100644
index 3c9eabf17512cdd2f7d8ad38962f6c83897f462b..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_output_switch_control.vhd
+++ /dev/null
@@ -1,159 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_OUTPUT_SWITCH_CONTROL
---
---
---
--- Description: UFC_OUTPUT_SWITCH_CONTROL selects the input chunk for each ufc output mux
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_UFC_OUTPUT_SWITCH_CONTROL is
-
- port (
-
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- UFC_OUTPUT_SELECT : out std_logic_vector(0 to 5)
-
- );
-
-end east_channel_UFC_OUTPUT_SWITCH_CONTROL;
-
-architecture RTL of east_channel_UFC_OUTPUT_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal UFC_OUTPUT_SELECT_Buffer : std_logic_vector(0 to 5);
-
--- Internal Register Declarations --
-
- signal ufc_output_select_c : std_logic_vector(0 to 5);
-
--- Wire Declarations --
-
- signal overflow_c : std_logic;
- signal sum_c : std_logic_vector(0 to 7);
-
-begin
-
- UFC_OUTPUT_SELECT <= UFC_OUTPUT_SELECT_Buffer;
-
--- Main Body of Code --
-
- -- Generate switch signals --
-
- -- Select for Lane 0
-
- sum_c(0 to 3) <= conv_std_logic_vector(1,4) - UFC_STORAGE_COUNT;
-
- process (sum_c)
-
- begin
-
- if (sum_c(0) = '1') then
-
- ufc_output_select_c(0 to 2) <= (others => '0');
-
- else
-
- ufc_output_select_c(0 to 2) <= sum_c(1 to 3);
-
- end if;
-
- end process;
-
-
- -- Select for Lane 1
-
- sum_c(4 to 7) <= conv_std_logic_vector(2,4) - UFC_STORAGE_COUNT;
-
- process (sum_c)
-
- begin
-
- if (sum_c(4) = '1') then
-
- ufc_output_select_c(3 to 5) <= (others => '0');
-
- else
-
- ufc_output_select_c(3 to 5) <= sum_c(5 to 7);
-
- end if;
-
- end process;
-
-
- -- Register the output
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_OUTPUT_SELECT_Buffer <= ufc_output_select_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_sideband_output.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_sideband_output.vhd
deleted file mode 100644
index 8eaf34fef12d8fea0afbd0aebcae6487bc676465..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_sideband_output.vhd
+++ /dev/null
@@ -1,230 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_SIDEBAND_OUTPUT
---
---
---
--- Description: UFC_SIDEBAND_OUTPUT generates the UFC_SRC_RDY_N, UFC_EOF_N,
--- UFC_SOF_N and UFC_REM signals for the RX localLink interface.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_UFC_SIDEBAND_OUTPUT is
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- UFC_SRC_RDY_N : out std_logic;
- UFC_SOF_N : out std_logic;
- UFC_EOF_N : out std_logic;
- UFC_REM : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end east_channel_UFC_SIDEBAND_OUTPUT;
-
-architecture RTL of east_channel_UFC_SIDEBAND_OUTPUT is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal UFC_SRC_RDY_N_Buffer : std_logic;
- signal UFC_SOF_N_Buffer : std_logic;
- signal UFC_EOF_N_Buffer : std_logic;
- signal UFC_REM_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal ufc_sof_early_r : std_logic;
-
--- Wire Declarations --
-
- signal sum_c : std_logic_vector(0 to 2);
- signal storage_count_2x_c : std_logic_vector(0 to 2);
- signal sum_2x_c : std_logic_vector(0 to 2);
- signal back_to_back_rem_c : std_logic_vector(0 to 2);
- signal non_back_to_back_rem_c : std_logic_vector(0 to 2);
- signal storage_empty_c : std_logic;
- signal message_finished_c : std_logic;
- signal back_to_back_ufc_c : std_logic;
-
-begin
-
- UFC_SRC_RDY_N <= UFC_SRC_RDY_N_Buffer;
- UFC_SOF_N <= UFC_SOF_N_Buffer;
- UFC_EOF_N <= UFC_EOF_N_Buffer;
- UFC_REM <= UFC_REM_Buffer;
-
--- Main Body of Code --
-
- -- Calculate the output --
-
- -- Assert ufc_src_rdy_n whenever data is moved to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_SRC_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- UFC_SRC_RDY_N_Buffer <= not std_bool(UFC_STORAGE_COUNT > conv_std_logic_vector(0,2)) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Assert ufc_sof one cycle after a new frame is delivered to storage.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- ufc_sof_early_r <= UFC_START after DLY;
-
- UFC_SOF_N_Buffer <= not ufc_sof_early_r after DLY;
-
- end if;
-
- end process;
-
-
- sum_c <= conv_std_logic_vector(0,3) + UFC_STORAGE_COUNT + BARREL_SHIFTED_COUNT;
-
-
- -- Detect empty storage.
-
- storage_empty_c <= std_bool(not (UFC_STORAGE_COUNT > conv_std_logic_vector(0,2)));
-
-
- -- Detect back to back ufc messages.
-
- back_to_back_ufc_c <= not storage_empty_c and UFC_START;
-
-
- -- Detect messages that are finishing.
-
- message_finished_c <= not storage_empty_c and (std_bool(sum_c <= conv_std_logic_vector(2,3)) or UFC_START);
-
-
- -- Assert eof_n when the storage will empty or a new frame arrives.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_EOF_N_Buffer <= not message_finished_c after DLY;
-
- end if;
-
- end process;
-
-
- -- REM calculations
-
- storage_count_2x_c <= UFC_STORAGE_COUNT & '0';
-
- sum_2x_c <= sum_c(1 to 2) & '0';
-
- back_to_back_rem_c <= storage_count_2x_c - conv_std_logic_vector(1,3);
-
- non_back_to_back_rem_c <= sum_2x_c - conv_std_logic_vector(1,3);
-
-
- -- Rem depends on the number of valid bytes being transferred to output
- -- on the eof cycle.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (back_to_back_ufc_c = '1') then
-
- UFC_REM_Buffer <= back_to_back_rem_c(1 to 2) after DLY;
-
- else
-
- UFC_REM_Buffer <= non_back_to_back_rem_c(1 to 2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_count_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_count_control.vhd
deleted file mode 100644
index f3cfbffc9aaa63f8104ea31314faa36f373416fb..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_count_control.vhd
+++ /dev/null
@@ -1,156 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_STORAGE_COUNT_CONTROL
---
---
---
--- Description: UFC_STORAGE_COUNT_CONTROL sets the ufc storage count value for the next clock
--- cycle
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_UFC_STORAGE_COUNT_CONTROL is
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- UFC_STORAGE_COUNT : out std_logic_vector(0 to 1)
-
- );
-
-end east_channel_UFC_STORAGE_COUNT_CONTROL;
-
-architecture RTL of east_channel_UFC_STORAGE_COUNT_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal UFC_STORAGE_COUNT_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal storage_count_c : std_logic_vector(0 to 1);
- signal storage_count_r : std_logic_vector(0 to 1);
-
--- Wire Declarations --
-
- signal sum_c : std_logic_vector(0 to 2);
- signal reduced_sum_c : std_logic_vector(0 to 2);
- signal next_storage_count_c : std_logic_vector(0 to 1);
-
-begin
-
- UFC_STORAGE_COUNT <= UFC_STORAGE_COUNT_Buffer;
-
--- Main Body of Code --
-
- -- Calculate the value that will be used for the switch.
-
- sum_c <= conv_std_logic_vector(0,3) + BARREL_SHIFTED_COUNT + storage_count_r;
- reduced_sum_c <= sum_c - conv_std_logic_vector(2,3);
-
- next_storage_count_c <= reduced_sum_c(1 to 2) when (sum_c > conv_std_logic_vector(2,3)) else (others =>'0');
-
-
- process (UFC_START, next_storage_count_c, BARREL_SHIFTED_COUNT)
-
- begin
-
- if (UFC_START = '1') then
-
- storage_count_c <= BARREL_SHIFTED_COUNT;
-
- else
-
- storage_count_c <= next_storage_count_c;
-
- end if;
-
- end process;
-
-
- -- Register the storage count and make it available to the outside world.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(RESET = '1') then
-
- storage_count_r <= (others => '0') after DLY;
-
- else
-
- storage_count_r <= storage_count_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- UFC_STORAGE_COUNT_Buffer <= storage_count_r;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_mux.vhd
deleted file mode 100644
index 461b8369a8b1b0b484b0d0582f1a1e22b983f9d1..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_mux.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_STORAGE_MUX
---
---
---
--- Description: the UFC_STORAGE_MUX is a series of N:1 muxes used to determine
--- which input lanes feed which storage register.
---
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity east_channel_UFC_STORAGE_MUX is
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
-
- -- Mux output
-
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end east_channel_UFC_STORAGE_MUX;
-
-architecture RTL of east_channel_UFC_STORAGE_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal MUXED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal muxed_data_c : std_logic_vector(0 to 31);
-
-begin
-
- MUXED_DATA <= MUXED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create muxes for each lane
-
- -- Mux for lane 0
-
- process (MUX_SELECT(0 to 2), RAW_DATA)
-
- begin
-
- case MUX_SELECT(0 to 2) is
-
-when "000" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "001" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (MUX_SELECT(3 to 5), RAW_DATA)
-
- begin
-
- case MUX_SELECT(3 to 5) is
-
-when "000" =>
-
- muxed_data_c(16 to 31) <= RAW_DATA(0 to 15);
-
-when "001" =>
-
- muxed_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the data
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK'event and USER_CLK = '1') then
-
- MUXED_DATA_Buffer <= muxed_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_switch_control.vhd
deleted file mode 100644
index 4da026870972115a85c15100530d0b499e986412..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_ufc_storage_switch_control.vhd
+++ /dev/null
@@ -1,167 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_STORAGE_SWITCH_CONTROL
---
---
---
--- Description: UFC_STORAGE_SWITCH_CONTROL selects the input chunk for each ufc storage chunk mux
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity east_channel_UFC_STORAGE_SWITCH_CONTROL is
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- UFC_STORAGE_SELECT : out std_logic_vector(0 to 5)
-
- );
-
-end east_channel_UFC_STORAGE_SWITCH_CONTROL;
-
-architecture RTL of east_channel_UFC_STORAGE_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal UFC_STORAGE_SELECT_Buffer : std_logic_vector(0 to 5);
-
--- Internal Register Declarations --
-
- signal ufc_storage_select_c : std_logic_vector(0 to 5);
-
--- Wire Declarations --
-
- signal sum_c : std_logic_vector(0 to 3);
- signal overflow_c : std_logic;
- signal overflow_value_c : std_logic_vector(0 to 7);
-
-begin
-
- UFC_STORAGE_SELECT <= UFC_STORAGE_SELECT_Buffer;
-
--- Main Body of Code --
-
- sum_c <= "0000" + BARREL_SHIFTED_COUNT + UFC_STORAGE_COUNT;
- overflow_c <= std_bool(sum_c > conv_std_logic_vector(2,3)) and not UFC_START;
-
-
- -- Generate switch signals --
-
- -- Select for Lane 0
-
- overflow_value_c(0 to 3) <= conv_std_logic_vector(2,4) - UFC_STORAGE_COUNT;
-
- process (overflow_c, overflow_value_c)
-
- begin
-
- if (overflow_c = '1') then
-
- ufc_storage_select_c(0 to 2) <= overflow_value_c(1 to 3);
-
- else
-
- ufc_storage_select_c(0 to 2) <= conv_std_logic_vector(0,3);
-
- end if;
-
- end process;
-
-
- -- Select for Lane 1
-
- overflow_value_c(4 to 7) <= conv_std_logic_vector(3,4) - UFC_STORAGE_COUNT;
-
- process (overflow_c, overflow_value_c)
-
- begin
-
- if (overflow_c = '1') then
-
- ufc_storage_select_c(3 to 5) <= overflow_value_c(5 to 7);
-
- else
-
- ufc_storage_select_c(3 to 5) <= conv_std_logic_vector(1,3);
-
- end if;
-
- end process;
-
-
- -- Register the storage selection.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_STORAGE_SELECT_Buffer <= ufc_storage_select_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_valid_data_counter.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_valid_data_counter.vhd
deleted file mode 100644
index 406b5122316bd43973ae26e85d188f0957555264..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_valid_data_counter.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- VALID_DATA_COUNTER
---
---
---
--- Description: The VALID_DATA_COUNTER module counts the number of ones in a register filled
--- with ones and zeros.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity east_channel_VALID_DATA_COUNTER is
-
- port (
-
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
- COUNT : out std_logic_vector(0 to 1)
-
- );
-
-end east_channel_VALID_DATA_COUNTER;
-
-architecture RTL of east_channel_VALID_DATA_COUNTER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal COUNT_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal count_c : std_logic_vector(0 to 1);
-
-begin
-
- COUNT <= COUNT_Buffer;
-
--- Main Body of Code --
-
- -- Return the number of 1's in the binary representation of the input value.
-
- process (PREVIOUS_STAGE_VALID)
-
- begin
-
- count_c <= (
-
- conv_std_logic_vector(0,2)
- + PREVIOUS_STAGE_VALID(0)
- + PREVIOUS_STAGE_VALID(1)
-
- );
-
- end process;
-
-
- --Register the count
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- COUNT_Buffer <= (others => '0') after DLY;
-
- else
-
- COUNT_Buffer <= count_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_clocks.xdc b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_clocks.xdc
deleted file mode 100644
index c8d240341b87f7517460512497d56f6fc9f6d383..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_clocks.xdc
+++ /dev/null
@@ -1,76 +0,0 @@
-
-################################################################################
-##
-## (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-## east_channel.xdc generated for xc7z015-clg485-2 device
-#
-#
-#
-## TXOUTCLK Constraint: Value is selected based on the line rate (5.0 Gbps) and lane width (4-Byte)
-#
-#create_clock -period 4.0 [get_pins -hier -filter {name=~*gt_wrapper_i*east_channel_multi_gt_i*gt0_east_channel_i*gtpe2_i*TXOUTCLK}]
-#
-#
-#
-#
-#
-
-##### CDC Path #####
-#set_false_path -to [get_pins -hier *east_channel_cdc_to*/D]
-#
-#
-#
-####################### GT reference clock LOC (For use in top level design) #######################
-# set_property LOC V5 [get_ports GTPQ0_N]
-# set_property LOC U5 [get_ports GTPQ0_P]
-
-############################### GT LOC (For use in top level design) ###################################
-# set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells aurora_module_i/east_channel_i/U0/gt_wrapper_i/east_channel_multi_gt_i/gt0_east_channel_i/gtpe2_i]
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_core.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_core.vhd
deleted file mode 100644
index 1f8c6043a6d73b117e0d147465bb147fde7dd960..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_core.vhd
+++ /dev/null
@@ -1,1368 +0,0 @@
----------------------------------------------------------------------------------------------
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------------------
---
--- east_channel
---
---
--- Description: This is the top level module for a 1 4-byte lane Aurora
--- reference design module. This module supports the following features:
---
--- * User Flow Control
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
---synthesis translate_on
-
-entity east_channel_core is
- generic (
-
- SIM_GTRESET_SPEEDUP : string := "FALSE";
- CC_FREQ_FACTOR : integer := 12;
- EXAMPLE_SIMULATION : integer := 0
- );
- port (
-
- -- TX Stream Interface
-
-S_AXI_TX_TDATA : in std_logic_vector(0 to 31);
-S_AXI_TX_TKEEP : in std_logic_vector(0 to 3);
-
- S_AXI_TX_TVALID : in std_logic;
- S_AXI_TX_TREADY : out std_logic;
- S_AXI_TX_TLAST : in std_logic;
-
- -- RX Stream Interface
-
-M_AXI_RX_TDATA : out std_logic_vector(0 to 31);
-M_AXI_RX_TKEEP : out std_logic_vector(0 to 3);
-
- M_AXI_RX_TVALID : out std_logic;
- M_AXI_RX_TLAST : out std_logic;
-
- -- User Flow Control TX Interface
-
- S_AXI_UFC_TX_REQ : in std_logic;
- S_AXI_UFC_TX_MS : in std_logic_vector(0 to 2);
- S_AXI_UFC_TX_ACK : out std_logic;
-
- -- User Flow Control RX Inteface
-
-M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31);
-M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_UFC_RX_TVALID : out std_logic;
- M_AXI_UFC_RX_TLAST : out std_logic;
- -- GTX Serial I/O
-
-RXP : in std_logic;
-RXN : in std_logic;
-TXP : out std_logic;
-TXN : out std_logic;
-
- --GTX Reference Clock Interface
-
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
-
- HARD_ERR : out std_logic;
- SOFT_ERR : out std_logic;
- FRAME_ERR : out std_logic;
-
-
- -- Status
-
- CHANNEL_UP : out std_logic;
-LANE_UP : out std_logic;
-
- -- System Interface
-
- user_clk : in std_logic;
- sync_clk : in std_logic;
- RESET : in std_logic;
- POWER_DOWN : in std_logic;
- LOOPBACK : in std_logic_vector(2 downto 0);
- GT_RESET : in std_logic;
- init_clk_in : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- TX_RESETDONE_OUT : out std_logic;
- RX_RESETDONE_OUT : out std_logic;
- LINK_RESET_OUT : out std_logic;
-drpclk_in : in std_logic;
-DRPADDR_IN : in std_logic_vector(8 downto 0);
-DRPDI_IN : in std_logic_vector(15 downto 0);
-DRPDO_OUT : out std_logic_vector(15 downto 0);
-DRPEN_IN : in std_logic;
-DRPRDY_OUT : out std_logic;
-DRPWE_IN : in std_logic;
-
- TX_OUT_CLK : out std_logic;
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
-
- sys_reset_out : out std_logic;
- tx_lock : out std_logic
-
- );
-
-end east_channel_core;
-
-
-architecture MAPPED of east_channel_core is
- attribute core_generation_info : string;
-attribute core_generation_info of MAPPED : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- -- Parameter Declarations --
- constant DLY : time := 1 ns;
-
--- Component Declarations --
- component east_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
- end component;
-
- component east_channel_RESET_LOGIC
- port (
- RESET : in std_logic;
- USER_CLK : in std_logic;
- INIT_CLK_IN : in std_logic;
- TX_LOCK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- LINK_RESET_IN : in std_logic;
- TX_RESETDONE_IN : in std_logic;
- RX_RESETDONE_IN : in std_logic;
- SYSTEM_RESET : out std_logic
- );
- end component;
-
-
- -- AXI Shim modules
- component east_channel_LL_TO_AXI is
- generic
- (
- DATA_WIDTH : integer := 16; -- DATA bus width
- USE_UFC_REM : integer := 0; -- UFC REM bus width identifier
- STRB_WIDTH : integer := 2; -- STROBE bus width
- REM_WIDTH : integer := 1 -- REM bus width
- );
-
- port
- (
-
- ---------------------- AXI4-S Interface -------------------------------
- AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_OP_TVALID : out std_logic;
- AXI4_S_OP_TLAST : out std_logic;
- AXI4_S_IP_TREADY : in std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1);
- LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1);
- LL_IP_SRC_RDY_N : in std_logic;
- LL_IP_SOF_N : in std_logic;
- LL_IP_EOF_N : in std_logic;
- LL_OP_DST_RDY_N : out std_logic
-
- );
- end component;
-
- component east_channel_AXI_TO_LL is
- generic
- (
- DATA_WIDTH : integer := 16; -- DATA bus width
- STRB_WIDTH : integer := 2; -- STROBE bus width
- REM_WIDTH : integer := 1; -- REM bus width
- USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC
- USE_UFC_REM : integer := 0 -- UFC REM bus width identifier
- );
-
- port
- (
-
- ---------------------- AXI4-S Interface -------------------------------
- AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_IP_TX_TVALID : in std_logic;
- AXI4_S_IP_TX_TLAST : in std_logic;
- AXI4_S_OP_TX_TREADY : out std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1);
- LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1);
- LL_OP_SRC_RDY_N : out std_logic;
- LL_OP_SOF_N : out std_logic;
- LL_OP_EOF_N : out std_logic;
- LL_IP_DST_RDY_N : in std_logic;
-
- ---------------------- System Interface ----------------------------
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : in std_logic
-
- );
- end component;
-
- component FD
-
- generic (
- INIT : bit := '0'
- );
-
- port (
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic
- );
-
- end component;
-
-
- component east_channel_AURORA_LANE_4BYTE
- generic (
- EXAMPLE_SIMULATION : integer := 0
-
- );
- port (
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- 4-byte data bus from the GTX.
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- Invalid 10-bit code was recieved.
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- Disparity error detected on RX interface.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Indicates which bytes of RX_DATA are control.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Comma received on given byte.
- RX_BUF_ERR : in std_logic; -- Overflow/Underflow of RX buffer detected.
- RX_STATUS : in std_logic_vector(5 downto 0); -- Part of GT_11 status and error bus
- TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
- RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
- RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
- RX_RESET : out std_logic; -- Reset RX side of GTX logic.
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- TX_DATA byte is a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- 4-byte data bus to the GTX.
- TX_RESET : out std_logic; -- Reset TX side of GTX logic.
- LINK_RESET_OUT : out std_logic; -- Link reset for hotplug scenerio.
- HPCNT_RESET : in std_logic; -- Hotplug count reset input.
- INIT_CLK : in std_logic;
-
- -- Comma Detect Phase Align Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
-
- -- TX_LL Interface
-
- GEN_SCP : in std_logic_vector(0 to 1); -- SCP generation request from TX_LL.
- GEN_ECP : in std_logic_vector(0 to 1); -- ECP generation request from TX_LL.
- GEN_SUF : in std_logic_vector(0 to 1); -- SUF generation request from TX_LL
- GEN_PAD : in std_logic_vector(0 to 1); -- PAD generation request from TX_LL
- FC_NB : in std_logic_vector(0 to 7); -- Size code for SUF and SNF messages
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data from TX_LL to send over lane.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Indicates TX_PE_DATA is Valid.
- GEN_CC : in std_logic; -- CC generation request from TX_LL.
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- Indicates lane received PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- RX data from lane to RX_LL.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- RX_PE_DATA is data, not control symbol.
- RX_SCP : out std_logic_vector(0 to 1); -- Indicates lane received SCP.
- RX_ECP : out std_logic_vector(0 to 1); -- Indicates lane received ECP
- RX_SUF : out std_logic_vector(0 to 1); -- Indicates lane received SUF
- RX_FC_NB : out std_logic_vector(0 to 7); -- Size code for SNF or SUF
-
- -- Global Logic Interface
-
- GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
- GEN_K : in std_logic_vector(0 to 3); -- 'K character' generation request from Global Logic.
- GEN_R : in std_logic_vector(0 to 3); -- 'R character' generation request from Global Logic.
- GEN_V : in std_logic_vector(0 to 3); -- Verification data generation request.
- LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
- SOFT_ERR : out std_logic_vector(0 to 1); -- Soft error detected.
- HARD_ERR : out std_logic; -- Hard error detected.
- CHANNEL_BOND_LOAD : out std_logic; -- Channel Bongding done code recieved.
- GOT_A : out std_logic_vector(0 to 3); -- Indicates lane recieved 'A character' bytes.
- GOT_V : out std_logic; -- Verification symbols received.
- CHANNEL_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET_SYMGEN : in std_logic; -- Reset the SYM_GEN module.
- RESET : in std_logic -- Reset the lane.
-
- );
-
- end component;
-
-
- component east_channel_GT_WRAPPER
- generic(
- SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
- EXAMPLE_SIMULATION : integer := 0
- );
- port (
-RXFSM_DATA_VALID : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- gt0_txresetdone_out : out std_logic;
- gt0_rxresetdone_out : out std_logic;
- gt0_rxpmaresetdone_out : out std_logic;
- gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
- gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
-
-
- -- DRP I/F
-DRPADDR_IN : in std_logic_vector(8 downto 0);
-DRPCLK_IN : in std_logic;
-DRPDI_IN : in std_logic_vector(15 downto 0);
-DRPDO_OUT : out std_logic_vector(15 downto 0);
-DRPEN_IN : in std_logic;
-DRPRDY_OUT : out std_logic;
-DRPWE_IN : in std_logic;
-
- INIT_CLK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- TX_RESETDONE_OUT : out std_logic;
- RX_RESETDONE_OUT : out std_logic;
-ENCHANSYNC_IN : in std_logic;
-ENMCOMMAALIGN_IN : in std_logic;
-ENPCOMMAALIGN_IN : in std_logic;
- REFCLK : in std_logic;
- LOOPBACK_IN : in std_logic_vector (2 downto 0);
-RXPOLARITY_IN : in std_logic;
-RXRESET_IN : in std_logic;
- RXUSRCLK_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
-RX1N_IN : in std_logic;
-RX1P_IN : in std_logic;
-TXCHARISK_IN : in std_logic_vector (3 downto 0);
-TXDATA_IN : in std_logic_vector (31 downto 0);
- GTRESET_IN : in std_logic;
-TXRESET_IN : in std_logic;
- TXUSRCLK_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
-RXBUFERR_OUT : out std_logic;
-RXCHARISCOMMA_OUT : out std_logic_vector (3 downto 0);
-RXCHARISK_OUT : out std_logic_vector (3 downto 0);
-RXDATA_OUT : out std_logic_vector (31 downto 0);
-RXDISPERR_OUT : out std_logic_vector (3 downto 0);
-RXNOTINTABLE_OUT : out std_logic_vector (3 downto 0);
-RXREALIGN_OUT : out std_logic;
-CHBONDDONE_OUT : out std_logic;
-TXBUFERR_OUT : out std_logic;
-
- GTRXRESET_IN : in std_logic;
-
- LINK_RESET_IN : in std_logic; -- Link reset for hotplug scenerio.
-PLLLKDET_OUT : out std_logic;
-TXOUTCLK1_OUT : out std_logic;
-TX1N_OUT : out std_logic;
-TX1P_OUT : out std_logic;
- POWERDOWN_IN : in std_logic
-
- );
-
- end component;
-
- component BUFG
-
- port (
- O : out STD_ULOGIC;
- I : in STD_ULOGIC
- );
-
- end component;
-
-
- component east_channel_GLOBAL_LOGIC
-
- port (
-
- -- GTX Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-LANE_UP : in std_logic;
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-RESET_LANES : out std_logic;
- GTRXRESET_OUT : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- POWER_DOWN : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic
-
- );
-
- end component;
-
-
- component east_channel_TX_LL
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
- );
-
- end component;
-
-
- component east_channel_RX_LL
-
- port (
-
- -- LocalLink PDU Interface
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- -- Global Logic Interface
-
- START_RX : in std_logic;
-
- -- Aurora Lane Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-component east_channel_STANDARD_CC_MODULE
- generic
- (
- CC_FREQ_FACTOR : integer := 24
- );
- port (
- -- Clock Compensation Control Interface
- WARN_CC : out std_logic;
- DO_CC : out std_logic;
- -- System Interface
- PLL_NOT_LOCKED : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
- );
- end component;
--- Signal Declarations --
-
-signal TX1N_OUT_unused : std_logic;
-signal TX1P_OUT_unused : std_logic;
-signal RX1N_IN_unused : std_logic;
-signal RX1P_IN_unused : std_logic;
-signal rx_char_is_comma_i_unused : std_logic_vector(3 downto 0);
-signal rx_char_is_k_i_unused : std_logic_vector(3 downto 0);
-signal rx_data_i_unused : std_logic_vector(31 downto 0);
-signal rx_disp_err_i_unused : std_logic_vector(3 downto 0);
-signal rx_not_in_table_i_unused : std_logic_vector(3 downto 0);
-signal rx_realign_i_unused : std_logic;
-signal ch_bond_done_i_unused : std_logic;
-
-signal ch_bond_done_i : std_logic;
-signal ch_bond_done_r1 : std_logic;
-signal ch_bond_done_r2 : std_logic;
-signal ch_bond_load_not_used_i : std_logic;
-signal channel_up_i : std_logic;
-signal chbondi_not_used_i : std_logic_vector(4 downto 0);
-signal chbondo_not_used_i : std_logic_vector(4 downto 0);
-signal combus_in_not_used_i : std_logic_vector(15 downto 0);
-signal combusout_out_not_used_i: std_logic_vector(15 downto 0);
-signal en_chan_sync_i : std_logic;
-signal ena_comma_align_i : std_logic;
-signal fc_nb_i : std_logic_vector(0 to 3);
-
-signal fc_nb_striped_i : std_logic_vector(0 to 7);
-signal gen_a_i : std_logic;
-signal gen_cc_i : std_logic;
-signal gen_ecp_i : std_logic;
-signal gen_ecp_striped_i : std_logic_vector(0 to 1);
-signal gen_k_i : std_logic_vector(0 to 3);
-signal gen_pad_i : std_logic_vector(0 to 1);
-signal gen_pad_striped_i : std_logic_vector(0 to 1);
-signal gen_r_i : std_logic_vector(0 to 3);
-signal gen_scp_i : std_logic;
-signal gen_scp_striped_i : std_logic_vector(0 to 1);
-signal gen_suf_i : std_logic;
-signal gen_suf_striped_i : std_logic_vector(0 to 1);
-signal gen_v_i : std_logic_vector(0 to 3);
-signal got_a_i : std_logic_vector(0 to 3);
-signal got_v_i : std_logic;
-signal hard_err_i : std_logic;
-signal lane_up_i : std_logic;
-signal open_rx_char_is_comma_i : std_logic_vector(3 downto 0);
-signal open_rx_char_is_k_i : std_logic_vector(3 downto 0);
-signal open_rx_comma_det_i : std_logic;
-signal open_rx_data_i : std_logic_vector(31 downto 0);
-signal open_rx_disp_err_i : std_logic_vector(3 downto 0);
-signal open_rx_loss_of_sync_i : std_logic_vector(1 downto 0);
-signal open_rx_not_in_table_i : std_logic_vector(3 downto 0);
-signal open_rx_rec1_clk_i : std_logic;
-signal open_rx_rec2_clk_i : std_logic;
-signal open_rx_run_disp_i : std_logic_vector(7 downto 0);
-signal open_tx_k_err_i : std_logic_vector(7 downto 0);
-signal open_tx_run_disp_i : std_logic_vector(7 downto 0);
-signal pma_rx_lock_i : std_logic;
- signal link_reset_lane0_i : std_logic;
-signal link_reset_i : std_logic;
-signal raw_tx_out_clk_i : std_logic;
-signal reset_lanes_i : std_logic;
-signal rx_buf_err_i : std_logic;
-signal rx_char_is_comma_i : std_logic_vector(3 downto 0);
-signal rx_char_is_comma_gtx_i : std_logic_vector(7 downto 0);
-signal rx_char_is_k_i : std_logic_vector(3 downto 0);
-signal rx_char_is_k_gtx_i : std_logic_vector(7 downto 0);
-signal rx_data_i : std_logic_vector(31 downto 0);
-signal rx_data_gtx_i : std_logic_vector(63 downto 0);
-signal rx_disp_err_i : std_logic_vector(3 downto 0);
-signal rx_disp_err_gtx_i : std_logic_vector(7 downto 0);
-signal rx_ecp_i : std_logic_vector(0 to 1);
-signal rx_ecp_striped_i : std_logic_vector(0 to 1);
-signal rx_fc_nb_i : std_logic_vector(0 to 7);
-signal rx_fc_nb_striped_i : std_logic_vector(0 to 7);
-signal rx_not_in_table_i : std_logic_vector(3 downto 0);
-signal rx_not_in_table_gtx_i : std_logic_vector(7 downto 0);
-signal rx_pad_i : std_logic_vector(0 to 1);
-signal rx_pad_striped_i : std_logic_vector(0 to 1);
-signal rx_pe_data_i : std_logic_vector(0 to 31);
-signal rx_pe_data_striped_i : std_logic_vector(0 to 31);
-signal rx_pe_data_v_i : std_logic_vector(0 to 1);
-signal rx_pe_data_v_striped_i : std_logic_vector(0 to 1);
-signal rx_polarity_i : std_logic;
-signal rx_realign_i : std_logic;
-signal rx_reset_i : std_logic;
-signal rx_scp_i : std_logic_vector(0 to 1);
-signal rx_scp_striped_i : std_logic_vector(0 to 1);
-signal rx_status_float_i : std_logic_vector(4 downto 0);
-signal rx_suf_i : std_logic_vector(0 to 1);
-signal rx_suf_striped_i : std_logic_vector(0 to 1);
-signal soft_err_i : std_logic_vector(0 to 1);
-signal all_soft_err_i : std_logic;
-signal start_rx_i : std_logic;
-signal tied_to_ground_i : std_logic;
-signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
-signal tied_to_vcc_i : std_logic;
-signal tx_buf_err_i : std_logic;
-signal tx_char_is_k_i : std_logic_vector(3 downto 0);
-signal tx_data_i : std_logic_vector(31 downto 0);
-signal tx_lock_i : std_logic;
-signal tx_out_clk_i : std_logic;
-signal tx_pe_data_i : std_logic_vector(0 to 31);
-signal tx_pe_data_striped_i : std_logic_vector(0 to 31);
-signal tx_pe_data_v_i : std_logic_vector(0 to 1);
-signal tx_pe_data_v_striped_i : std_logic_vector(0 to 1);
-signal tx_reset_i : std_logic;
-signal ufc_tx_ms_i : std_logic_vector(0 to 3);
-
-signal tied_to_gnd_vec_i : std_logic_vector(0 to 31);
-signal rx_nfc_data : std_logic_vector(0 to 7);
- -- TX AXI PDU I/F signals
-signal tx_data : std_logic_vector(0 to 31);
-signal tx_rem : std_logic_vector(0 to 1);
-signal tx_src_rdy : std_logic;
-signal tx_sof : std_logic;
-signal tx_eof : std_logic;
-signal tx_dst_rdy : std_logic;
-
- -- RX AXI PDU I/F signals
-signal rx_data : std_logic_vector(0 to 31);
-signal rx_rem : std_logic_vector(0 to 1);
-signal rx_src_rdy : std_logic;
-signal rx_sof : std_logic;
-signal rx_eof : std_logic;
-
- -- TX AXI UFC I/F signals
-signal tx_ufc_data : std_logic_vector(0 to 3);
-signal tx_ufc_src_rdy : std_logic;
-signal tx_ufc_dst_rdy : std_logic;
-
- -- RX AXI UFC I/F signals
-signal rx_ufc_data : std_logic_vector(0 to 31);
-signal rx_ufc_rem : std_logic_vector(0 to 1);
-signal rx_ufc_src_rdy : std_logic;
-signal rx_ufc_sof : std_logic;
-signal rx_ufc_eof : std_logic;
-
-signal gtrxreset_i : std_logic;
-signal system_reset_i : std_logic;
-signal tx_lock_comb_i : std_logic;
-signal tx_resetdone_i : std_logic;
-signal rx_resetdone_i : std_logic;
-signal rxfsm_data_valid_r : std_logic;
-signal rst_cc_module_i : std_logic;
-signal hpcnt_reset_i : std_logic;
-signal reset_sync_init_clk : std_logic;
-signal reset_sync_user_clk : std_logic;
-signal gt_reset_sync_init_clk : std_logic;
-signal DO_CC_I : std_logic;
-signal WARN_CC : std_logic;
-begin
--- Main Body of Code --
-
- -- Tie off top level constants.
- tied_to_gnd_vec_i <= (others => '0');
- tied_to_ground_vec_i <= (others => '0');
- tied_to_ground_i <= '0';
- tied_to_vcc_i <= '1';
-
- link_reset_i <= link_reset_lane0_i ;
-
-
- process (user_clk)
- begin
- if(user_clk'event and user_clk='1') then
- rxfsm_data_valid_r <= lane_up_i after DLY;
- end if;
- end process;
-
- LINK_RESET_OUT <= link_reset_i;
-
- all_soft_err_i <= soft_err_i(0) or soft_err_i(1);
- chbondi_not_used_i <= (others => '0');
-
- -- Connect top level logic.
-
- CHANNEL_UP <= channel_up_i;
- tx_lock <= tx_lock_comb_i;
- tx_resetdone_out <= tx_resetdone_i;
- rx_resetdone_out <= rx_resetdone_i;
- sys_reset_out <= system_reset_i;
-
-
-
- --Connect the TXOUTCLK of lane 0 to TX_OUT_CLK
-TX_OUT_CLK <= raw_tx_out_clk_i;
-
- -- Connect tx_lock To tx_lock_i from lane 0
- tx_lock_comb_i <= tx_lock_i;
-
-
- reset_sync_user_clk_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1,
- c_flop_input => 0,
- c_reset_state => 0,
- c_single_bit => 1,
- c_vector_width => 2,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => RESET ,
- prmry_vect_in => "00" ,
- scndry_aclk => user_clk ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => reset_sync_user_clk,
- scndry_vect_out => open
- );
-
- gt_reset_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1,
- c_flop_input => 0,
- c_reset_state => 0,
- c_single_bit => 1,
- c_vector_width => 2,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => GT_RESET ,
- prmry_vect_in => "00" ,
- scndry_aclk => init_clk_in ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gt_reset_sync_init_clk,
- scndry_vect_out => open
- );
-
- -- RESET_LOGIC instance
- core_reset_logic_i : east_channel_RESET_LOGIC
- port map
- (
- RESET => reset_sync_user_clk,
- USER_CLK => user_clk ,
- INIT_CLK_IN => init_clk_in ,
- TX_LOCK_IN => tx_lock_comb_i ,
- PLL_NOT_LOCKED => pll_not_locked ,
- TX_RESETDONE_IN => tx_resetdone_i ,
- RX_RESETDONE_IN => rx_resetdone_i ,
- LINK_RESET_IN => link_reset_i ,
- SYSTEM_RESET => system_reset_i
- );
-
- hpcnt_reset_cdc_sync : east_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1,
- c_flop_input => 0,
- c_reset_state => 0,
- c_single_bit => 1,
- c_vector_width => 2,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => user_clk ,
- prmry_resetn => '1' ,
- prmry_in => RESET ,
- prmry_vect_in => "00" ,
- scndry_aclk => init_clk_in ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => reset_sync_init_clk,
- scndry_vect_out => open
- );
-
-hpcnt_reset_i <= gt_reset_sync_init_clk or reset_sync_init_clk;
-
- -- Instantiate Lane 0 --
-
-LANE_UP <= lane_up_i;
-
- -- Aurora lane striping rules require each 4-byte lane to carry 2 bytes
- -- from the first half of the overall word, and 2 bytes from the second
- -- half. This ensures that the data will be ordered correctly if it is
- -- sent to a 2-byte lane. Here we perform the required concatenation.
-
- gen_scp_striped_i <= gen_scp_i & '0';
- gen_suf_striped_i <= gen_suf_i & '0';
- fc_nb_striped_i <= fc_nb_i & "0000";
- gen_ecp_striped_i <= '0' & gen_ecp_i;
- gen_pad_striped_i(0 to 1) <= gen_pad_i(0) & gen_pad_i(1);
- tx_pe_data_striped_i(0 to 31) <= tx_pe_data_i(0 to 15) & tx_pe_data_i(16 to 31);
- tx_pe_data_v_striped_i(0 to 1) <= tx_pe_data_v_i(0) & tx_pe_data_v_i(1);
- rx_pad_i(0) <= rx_pad_striped_i(0);
- rx_pad_i(1) <= rx_pad_striped_i(1);
- rx_pe_data_i(0 to 15) <= rx_pe_data_striped_i(0 to 15);
- rx_pe_data_i(16 to 31) <= rx_pe_data_striped_i(16 to 31);
- rx_pe_data_v_i(0) <= rx_pe_data_v_striped_i(0);
- rx_pe_data_v_i(1) <= rx_pe_data_v_striped_i(1);
- rx_scp_i(0) <= rx_scp_striped_i(0);
- rx_scp_i(1) <= rx_scp_striped_i(1);
- rx_ecp_i(0) <= rx_ecp_striped_i(0);
- rx_ecp_i(1) <= rx_ecp_striped_i(1);
- rx_suf_i(0) <= rx_suf_striped_i(0);
- rx_suf_i(1) <= rx_suf_striped_i(1);
- rx_fc_nb_i(0 to 3) <= rx_fc_nb_striped_i(0 to 3);
- rx_fc_nb_i(4 to 7) <= rx_fc_nb_striped_i(4 to 7);
-
- east_channel_aurora_lane_4byte_0_i : east_channel_AURORA_LANE_4BYTE
- generic map
- (
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION
- )
- port map (
-
- -- GTX Interface
-
- RX_DATA => rx_data_i(31 downto 0),
- RX_NOT_IN_TABLE => rx_not_in_table_i(3 downto 0),
- RX_DISP_ERR => rx_disp_err_i(3 downto 0),
- RX_CHAR_IS_K => rx_char_is_k_i(3 downto 0),
- RX_CHAR_IS_COMMA => rx_char_is_comma_i(3 downto 0),
- RX_STATUS => tied_to_ground_vec_i(5 downto 0),
- TX_BUF_ERR => tx_buf_err_i,
- RX_BUF_ERR => rx_buf_err_i,
- RX_REALIGN => rx_realign_i,
- RX_POLARITY => rx_polarity_i,
- RX_RESET => rx_reset_i,
- TX_CHAR_IS_K => tx_char_is_k_i(3 downto 0),
- TX_DATA => tx_data_i(31 downto 0),
- TX_RESET => tx_reset_i,
- INIT_CLK => init_clk_in,
- LINK_RESET_OUT => link_reset_lane0_i,
- HPCNT_RESET => hpcnt_reset_i,
-
- -- Comma Detect Phase Align Interface
-
-ENA_COMMA_ALIGN => ena_comma_align_i,
-
- -- TX_LL Interface
- GEN_SCP => gen_scp_striped_i,
- GEN_SUF => gen_suf_striped_i,
- FC_NB => fc_nb_striped_i,
- GEN_ECP => gen_ecp_striped_i,
- GEN_PAD => gen_pad_striped_i(0 to 1),
- TX_PE_DATA => tx_pe_data_striped_i(0 to 31),
- TX_PE_DATA_V => tx_pe_data_v_striped_i(0 to 1),
-GEN_CC => gen_cc_i,
-
- -- RX_LL Interface
-
- RX_PAD => rx_pad_striped_i(0 to 1),
- RX_PE_DATA => rx_pe_data_striped_i(0 to 31),
- RX_PE_DATA_V => rx_pe_data_v_striped_i(0 to 1),
- RX_SCP => rx_scp_striped_i(0 to 1),
- RX_ECP => rx_ecp_striped_i(0 to 1),
- RX_SUF => rx_suf_striped_i(0 to 1),
- RX_FC_NB => rx_fc_nb_striped_i(0 to 7),
-
- -- Global Logic Interface
-
-GEN_A => gen_a_i,
- GEN_K => gen_k_i(0 to 3),
- GEN_R => gen_r_i(0 to 3),
- GEN_V => gen_v_i(0 to 3),
-LANE_UP => lane_up_i,
- SOFT_ERR => soft_err_i(0 to 1),
-HARD_ERR => hard_err_i,
-CHANNEL_BOND_LOAD => ch_bond_load_not_used_i,
- GOT_A => got_a_i(0 to 3),
-GOT_V => got_v_i,
- CHANNEL_UP => channel_up_i,
-
- -- System Interface
-
- USER_CLK => user_clk,
- RESET_SYMGEN => system_reset_i,
-RESET => reset_lanes_i
-
- );
-
-
-
-
- -- Instantiate GT Wrapper --
- gt_wrapper_i : east_channel_GT_WRAPPER
- generic map
- (
- SIM_GTRESET_SPEEDUP => SIM_GTRESET_SPEEDUP,
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION
- )
- port map
- (
-RXFSM_DATA_VALID => rxfsm_data_valid_r,
-
- gt_common_reset_out => gt_common_reset_out,
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in => gt0_pll0refclklost_in,
- quad1_common_lock_in => quad1_common_lock_in,
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
---____________________________COMMON PORTS_______________________________}
-
- gt0_txresetdone_out => open,
- gt0_rxresetdone_out => open,
- gt0_rxpmaresetdone_out => open,
- gt0_txbufstatus_out => open,
- gt0_rxbufstatus_out => open,
-
- -- DRP I/F
-DRPCLK_IN => drpclk_in,
-DRPADDR_IN => DRPADDR_IN,
-DRPDI_IN => DRPDI_IN,
-DRPDO_OUT => DRPDO_OUT,
-DRPEN_IN => DRPEN_IN,
-DRPRDY_OUT => DRPRDY_OUT,
-DRPWE_IN => DRPWE_IN,
-
- INIT_CLK_IN => init_clk_in,
- PLL_NOT_LOCKED => PLL_NOT_LOCKED,
- TX_RESETDONE_OUT => tx_resetdone_i,
- RX_RESETDONE_OUT => rx_resetdone_i,
- -- Aurora Lane Interface
-
-RXPOLARITY_IN => rx_polarity_i,
-RXRESET_IN => rx_reset_i,
-TXCHARISK_IN => tx_char_is_k_i(3 downto 0),
-TXDATA_IN => tx_data_i(31 downto 0),
-TXRESET_IN => tx_reset_i,
-RXDATA_OUT => rx_data_i(31 downto 0),
-RXNOTINTABLE_OUT => rx_not_in_table_i(3 downto 0),
-RXDISPERR_OUT => rx_disp_err_i(3 downto 0),
-RXCHARISK_OUT => rx_char_is_k_i(3 downto 0),
-RXCHARISCOMMA_OUT => rx_char_is_comma_i(3 downto 0),
-TXBUFERR_OUT => tx_buf_err_i,
-RXBUFERR_OUT => rx_buf_err_i,
-RXREALIGN_OUT => rx_realign_i,
- -- Reset due to channel initialization watchdog timer expiry
- GTRXRESET_IN => gtrxreset_i,
-
- -- reset for hot plug
- LINK_RESET_IN => link_reset_i,
-
- -- Phase Align Interface
-
-ENMCOMMAALIGN_IN => ena_comma_align_i,
-ENPCOMMAALIGN_IN => ena_comma_align_i,
- -- Global Logic Interface
-
-ENCHANSYNC_IN => en_chan_sync_i,
-CHBONDDONE_OUT => ch_bond_done_i,
-
- -- Serial IO
-RX1N_IN => RXN,
-RX1P_IN => RXP,
-TX1N_OUT => TXN,
-TX1P_OUT => TXP,
-
-
- -- Reference Clocks and User Clock
-
- RXUSRCLK_IN => sync_clk,
- RXUSRCLK2_IN => user_clk,
- TXUSRCLK_IN => sync_clk,
- TXUSRCLK2_IN => user_clk,
- REFCLK => gt_refclk1,
-
-TXOUTCLK1_OUT => raw_tx_out_clk_i,
-PLLLKDET_OUT => tx_lock_i,
-
- -- System Interface
-
- GTRESET_IN => gt_reset_sync_init_clk,
- LOOPBACK_IN => LOOPBACK,
-
- POWERDOWN_IN => POWER_DOWN
- );
-
- -- Instantiate Global Logic to combine Lanes into a Channel --
-
- east_channel_global_logic_i : east_channel_GLOBAL_LOGIC
- port map (
- -- GTX Interface
-
- CH_BOND_DONE => ch_bond_done_i,
- EN_CHAN_SYNC => en_chan_sync_i,
-
- -- Aurora Lane Interface
-
- LANE_UP => lane_up_i,
- SOFT_ERR => soft_err_i,
- HARD_ERR => hard_err_i,
- CHANNEL_BOND_LOAD => ch_bond_done_i,
- GOT_A => got_a_i,
- GOT_V => got_v_i,
- GEN_A => gen_a_i,
- GEN_K => gen_k_i,
- GEN_R => gen_r_i,
- GEN_V => gen_v_i,
- RESET_LANES => reset_lanes_i,
- GTRXRESET_OUT => gtrxreset_i,
-
-
- -- System Interface
-
- USER_CLK => user_clk,
- RESET => system_reset_i,
- POWER_DOWN => POWER_DOWN,
- CHANNEL_UP => channel_up_i,
- START_RX => start_rx_i,
- CHANNEL_SOFT_ERR => SOFT_ERR,
- CHANNEL_HARD_ERR => HARD_ERR
- );
-
-
- --_____________________________ TX AXI SHIM _______________________________
- axi_to_ll_pdu_i : east_channel_AXI_TO_LL
- generic map
- (
- DATA_WIDTH => 32,
- STRB_WIDTH => 4,
- REM_WIDTH => 2,
- USE_4_NFC => 0,
- USE_UFC_REM => 0
- )
-
- port map
- (
- AXI4_S_IP_TX_TVALID => S_AXI_TX_TVALID,
- AXI4_S_IP_TX_TDATA => S_AXI_TX_TDATA,
- AXI4_S_IP_TX_TKEEP => S_AXI_TX_TKEEP,
- AXI4_S_IP_TX_TLAST => S_AXI_TX_TLAST,
- AXI4_S_OP_TX_TREADY => S_AXI_TX_TREADY,
-
- LL_OP_DATA => tx_data,
- LL_OP_SOF_N => tx_sof,
- LL_OP_EOF_N => tx_eof,
- LL_OP_REM => tx_rem,
- LL_OP_SRC_RDY_N => tx_src_rdy,
- LL_IP_DST_RDY_N => tx_dst_rdy,
-
- -- System Interface
- USER_CLK => user_clk,
- RESET => system_reset_i,
- CHANNEL_UP => channel_up_i
- );
-
-
- axi_to_ll_ufc_i : east_channel_AXI_TO_LL
- generic map
- (
- DATA_WIDTH => 4,
- STRB_WIDTH => 4,
- REM_WIDTH => 2,
- USE_4_NFC => 2,
- USE_UFC_REM => 1
- )
-
- port map
- (
- AXI4_S_IP_TX_TVALID => S_AXI_UFC_TX_REQ,
- AXI4_S_OP_TX_TREADY => S_AXI_UFC_TX_ACK,
- AXI4_S_IP_TX_TDATA => ufc_tx_ms_i,
-AXI4_S_IP_TX_TKEEP => "0000",
- AXI4_S_IP_TX_TLAST => tied_to_ground_i,
-
- LL_OP_DATA => tx_ufc_data,
- LL_OP_SOF_N => OPEN,
- LL_OP_EOF_N => OPEN,
- LL_OP_REM => OPEN,
- LL_OP_SRC_RDY_N => tx_ufc_src_rdy,
- LL_IP_DST_RDY_N => tx_ufc_dst_rdy,
-
- -- System Interface
- USER_CLK => user_clk,
- RESET => system_reset_i,
- CHANNEL_UP => channel_up_i
- );
-
-
- -- Instantiate TX_LL --
-
- -- The TX_LL module takes 4 bits. We append a 1 to the end so all
- -- ufc message sizes are odd. This sizing is a holdover from the
- -- original Aurora protocol.
-
- ufc_tx_ms_i <= S_AXI_UFC_TX_MS & '1';
-
- rst_cc_module_i <= system_reset_i;
- standard_cc_module_i : east_channel_STANDARD_CC_MODULE
- generic map
- (
- CC_FREQ_FACTOR => CC_FREQ_FACTOR
- )
- port map (
- -- Clock Compensation Control Interface
- WARN_CC => WARN_CC,
- DO_CC => DO_CC_I,
- -- System Interface
- PLL_NOT_LOCKED => pll_not_locked,
- USER_CLK => user_clk,
- RESET => rst_cc_module_i
- );
-
- east_channel_tx_ll_i : east_channel_TX_LL
- port map (
- -- AXI PDU Interface
- TX_D => tx_data,
- TX_REM => tx_rem,
- TX_SRC_RDY_N => tx_src_rdy,
- TX_SOF_N => tx_sof,
- TX_EOF_N => tx_eof,
- TX_DST_RDY_N => tx_dst_rdy,
-
-
- -- UFC Interface
- UFC_TX_REQ_N => tx_ufc_src_rdy,
- UFC_TX_MS => tx_ufc_data,
- UFC_TX_ACK_N => tx_ufc_dst_rdy,
-
- -- Clock Compenstaion Interface
- WARN_CC => WARN_CC,
- DO_CC => DO_CC_I,
-
- -- Global Logic Interface
-
- CHANNEL_UP => channel_up_i,
-
- -- Aurora Lane Interface
-
- GEN_SCP => gen_scp_i,
- GEN_ECP => gen_ecp_i,
- GEN_SUF => gen_suf_i,
- FC_NB => fc_nb_i,
- TX_PE_DATA_V => tx_pe_data_v_i,
- GEN_PAD => gen_pad_i,
- TX_PE_DATA => tx_pe_data_i,
- GEN_CC => gen_cc_i,
-
- -- System Interface
-
- USER_CLK => user_clk
- );
-
-
- --_____________________________ RX AXI SHIM _______________________________
- ll_to_axi_pdu_i : east_channel_LL_TO_AXI
- generic map
- (
- DATA_WIDTH => 32,
- STRB_WIDTH => 4,
- REM_WIDTH => 2
- )
-
- port map
- (
- LL_IP_DATA => rx_data,
- LL_IP_SOF_N => rx_sof,
- LL_IP_EOF_N => rx_eof,
- LL_IP_REM => rx_rem,
- LL_IP_SRC_RDY_N => rx_src_rdy,
- LL_OP_DST_RDY_N => OPEN,
-
- AXI4_S_OP_TVALID => M_AXI_RX_TVALID,
- AXI4_S_OP_TDATA => M_AXI_RX_TDATA,
- AXI4_S_OP_TKEEP => M_AXI_RX_TKEEP,
- AXI4_S_OP_TLAST => M_AXI_RX_TLAST,
- AXI4_S_IP_TREADY => tied_to_ground_i
-
- );
-
- ll_to_axi_ufc_i : east_channel_LL_TO_AXI
- generic map
- (
- DATA_WIDTH => 32,
- USE_UFC_REM => 1,
- STRB_WIDTH => 4,
- REM_WIDTH => 2
- )
-
- port map
- (
- LL_IP_DATA => rx_ufc_data,
- LL_IP_SOF_N => rx_ufc_sof,
- LL_IP_EOF_N => rx_ufc_eof,
- LL_IP_REM => rx_ufc_rem,
- LL_IP_SRC_RDY_N => rx_ufc_src_rdy,
- LL_OP_DST_RDY_N => OPEN,
-
- AXI4_S_OP_TVALID => M_AXI_UFC_RX_TVALID,
- AXI4_S_OP_TDATA => M_AXI_UFC_RX_TDATA,
- AXI4_S_OP_TKEEP => M_AXI_UFC_RX_TKEEP,
- AXI4_S_OP_TLAST => M_AXI_UFC_RX_TLAST,
- AXI4_S_IP_TREADY => tied_to_ground_i
-
- );
-
-
- -- Instantiate RX_LL --
-
- east_channel_rx_ll_i : east_channel_RX_LL
- port map (
- -- AXI PDU Interface
- RX_D => rx_data,
- RX_REM => rx_rem,
- RX_SRC_RDY_N => rx_src_rdy,
- RX_SOF_N => rx_sof,
- RX_EOF_N => rx_eof,
-
- -- UFC Interface
-
- UFC_RX_DATA => rx_ufc_data,
- UFC_RX_REM => rx_ufc_rem,
- UFC_RX_SRC_RDY_N => rx_ufc_src_rdy,
- UFC_RX_SOF_N => rx_ufc_sof,
- UFC_RX_EOF_N => rx_ufc_eof,
-
- -- Global Logic Interface
-
- START_RX => start_rx_i,
-
- -- Aurora Lane Interface
-
- RX_PAD => rx_pad_i,
- RX_PE_DATA => rx_pe_data_i,
- RX_PE_DATA_V => rx_pe_data_v_i,
- RX_SCP => rx_scp_i,
- RX_ECP => rx_ecp_i,
- RX_SUF => rx_suf_i,
- RX_FC_NB => rx_fc_nb_i,
-
- -- Error Interface
-
- FRAME_ERR => FRAME_ERR,
-
- -- System Interface
-
- USER_CLK => user_clk
- );
-end MAPPED;
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_ooc.xdc b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_ooc.xdc
deleted file mode 100644
index 4d98db81e71a118f3dca1ed8cf7ed6eaa35310ea..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_ooc.xdc
+++ /dev/null
@@ -1,70 +0,0 @@
-
-################################################################################
-##
-## (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-## east_channel_ooc.xdc generated for xc7z015-clg485-2 device
-################################################################################
-# This constraints file contains default clock frequencies to be used during out-of-context flows such as
-# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
-# to match the target frequencies.
-# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
-################################################################################
-# 125.0MHz GT Reference clock constraint
-create_clock -period 8.0 [get_ports gt_refclk1]
-
-
-## USER_CLOCK & SYNC_CLOCK constraint
-create_clock -period 4.0 [get_ports user_clk]
-create_clock -period 4.0 [get_ports sync_clk]
-
-## 8.0 ns period INIT_CLK constraint
-create_clock -period 8.0 [get_ports init_clk_in]
-# 8.000 ns DRP Clock Constraint
-create_clock -period 8.000 [get_ports drpclk_in]
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_sim_netlist.v b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_sim_netlist.v
deleted file mode 100644
index da51903efc441a1fb42db776de5ec5c14107e6cd..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_sim_netlist.v
+++ /dev/null
@@ -1,28578 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 28 10:23:57 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_sim_netlist.v
-// Design : east_channel
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* NotValidForBitStream *)
-module east_channel
- (s_axi_tx_tdata,
- s_axi_tx_tvalid,
- s_axi_tx_tready,
- s_axi_tx_tkeep,
- s_axi_tx_tlast,
- m_axi_rx_tdata,
- m_axi_rx_tvalid,
- m_axi_rx_tkeep,
- m_axi_rx_tlast,
- s_axi_ufc_tx_tvalid,
- s_axi_ufc_tx_tdata,
- s_axi_ufc_tx_tready,
- m_axi_ufc_rx_tdata,
- m_axi_ufc_rx_tkeep,
- m_axi_ufc_rx_tvalid,
- m_axi_ufc_rx_tlast,
- rxp,
- rxn,
- txp,
- txn,
- gt_refclk1,
- frame_err,
- hard_err,
- soft_err,
- channel_up,
- lane_up,
- user_clk,
- sync_clk,
- reset,
- power_down,
- loopback,
- gt_reset,
- tx_lock,
- sys_reset_out,
- init_clk_in,
- tx_resetdone_out,
- rx_resetdone_out,
- link_reset_out,
- drpclk_in,
- drpaddr_in,
- drpdi_in,
- drpdo_out,
- drpen_in,
- drprdy_out,
- drpwe_in,
- gt_common_reset_out,
- gt0_pll0refclklost_in,
- quad1_common_lock_in,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- tx_out_clk,
- pll_not_locked);
- input [0:31]s_axi_tx_tdata;
- input s_axi_tx_tvalid;
- output s_axi_tx_tready;
- input [0:3]s_axi_tx_tkeep;
- input s_axi_tx_tlast;
- output [0:31]m_axi_rx_tdata;
- output m_axi_rx_tvalid;
- output [0:3]m_axi_rx_tkeep;
- output m_axi_rx_tlast;
- input s_axi_ufc_tx_tvalid;
- input [0:2]s_axi_ufc_tx_tdata;
- output s_axi_ufc_tx_tready;
- output [0:31]m_axi_ufc_rx_tdata;
- output [0:3]m_axi_ufc_rx_tkeep;
- output m_axi_ufc_rx_tvalid;
- output m_axi_ufc_rx_tlast;
- input [0:0]rxp;
- input [0:0]rxn;
- output [0:0]txp;
- output [0:0]txn;
- input gt_refclk1;
- output frame_err;
- output hard_err;
- output soft_err;
- output channel_up;
- output [0:0]lane_up;
- input user_clk;
- input sync_clk;
- input reset;
- input power_down;
- input [2:0]loopback;
- input gt_reset;
- output tx_lock;
- output sys_reset_out;
- input init_clk_in;
- output tx_resetdone_out;
- output rx_resetdone_out;
- output link_reset_out;
- input drpclk_in;
- input [8:0]drpaddr_in;
- input [15:0]drpdi_in;
- output [15:0]drpdo_out;
- input drpen_in;
- output drprdy_out;
- input drpwe_in;
- output gt_common_reset_out;
- input gt0_pll0refclklost_in;
- input quad1_common_lock_in;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- output tx_out_clk;
- input pll_not_locked;
-
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire channel_up;
- wire [8:0]drpaddr_in;
- wire drpclk_in;
- wire [15:0]drpdi_in;
- wire [15:0]drpdo_out;
- wire drpen_in;
- wire drprdy_out;
- wire drpwe_in;
- wire frame_err;
- wire gt0_pll0refclklost_in;
- wire gt_common_reset_out;
- wire gt_refclk1;
- wire gt_reset;
- wire hard_err;
- wire init_clk_in;
- wire [0:0]lane_up;
- wire link_reset_out;
- wire [2:0]loopback;
- wire [0:31]m_axi_rx_tdata;
- wire [0:3]m_axi_rx_tkeep;
- wire m_axi_rx_tlast;
- wire m_axi_rx_tvalid;
- wire [0:31]m_axi_ufc_rx_tdata;
- wire [0:3]m_axi_ufc_rx_tkeep;
- wire m_axi_ufc_rx_tlast;
- wire m_axi_ufc_rx_tvalid;
- wire pll_not_locked;
- wire power_down;
- wire quad1_common_lock_in;
- wire reset;
- wire rx_resetdone_out;
- wire [0:0]rxn;
- wire [0:0]rxp;
- wire [0:31]s_axi_tx_tdata;
- wire [0:3]s_axi_tx_tkeep;
- wire s_axi_tx_tlast;
- wire s_axi_tx_tready;
- wire s_axi_tx_tvalid;
- wire [0:2]s_axi_ufc_tx_tdata;
- wire s_axi_ufc_tx_tready;
- wire s_axi_ufc_tx_tvalid;
- wire soft_err;
- wire sync_clk;
- wire sys_reset_out;
- wire tx_lock;
- wire tx_out_clk;
- wire tx_resetdone_out;
- wire [0:0]txn;
- wire [0:0]txp;
- wire user_clk;
-
- (* CC_FREQ_FACTOR = "12" *)
- (* EXAMPLE_SIMULATION = "0" *)
- (* SIM_GTRESET_SPEEDUP = "FALSE" *)
- east_channel_east_channel_core U0
- (.CHANNEL_UP(channel_up),
- .DRPADDR_IN(drpaddr_in),
- .DRPDI_IN(drpdi_in),
- .DRPDO_OUT(drpdo_out),
- .DRPEN_IN(drpen_in),
- .DRPRDY_OUT(drprdy_out),
- .DRPWE_IN(drpwe_in),
- .FRAME_ERR(frame_err),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .GT_RESET(gt_reset),
- .HARD_ERR(hard_err),
- .LANE_UP(lane_up),
- .LINK_RESET_OUT(link_reset_out),
- .LOOPBACK(loopback),
- .M_AXI_RX_TDATA(m_axi_rx_tdata),
- .M_AXI_RX_TKEEP(m_axi_rx_tkeep),
- .M_AXI_RX_TLAST(m_axi_rx_tlast),
- .M_AXI_RX_TVALID(m_axi_rx_tvalid),
- .M_AXI_UFC_RX_TDATA(m_axi_ufc_rx_tdata),
- .M_AXI_UFC_RX_TKEEP(m_axi_ufc_rx_tkeep),
- .M_AXI_UFC_RX_TLAST(m_axi_ufc_rx_tlast),
- .M_AXI_UFC_RX_TVALID(m_axi_ufc_rx_tvalid),
- .PLL_NOT_LOCKED(pll_not_locked),
- .POWER_DOWN(power_down),
- .RESET(reset),
- .RXN(rxn),
- .RXP(rxp),
- .RX_RESETDONE_OUT(rx_resetdone_out),
- .SOFT_ERR(soft_err),
- .S_AXI_TX_TDATA(s_axi_tx_tdata),
- .S_AXI_TX_TKEEP(s_axi_tx_tkeep),
- .S_AXI_TX_TLAST(s_axi_tx_tlast),
- .S_AXI_TX_TREADY(s_axi_tx_tready),
- .S_AXI_TX_TVALID(s_axi_tx_tvalid),
- .S_AXI_UFC_TX_ACK(s_axi_ufc_tx_tready),
- .S_AXI_UFC_TX_MS(s_axi_ufc_tx_tdata),
- .S_AXI_UFC_TX_REQ(s_axi_ufc_tx_tvalid),
- .TXN(txn),
- .TXP(txp),
- .TX_OUT_CLK(tx_out_clk),
- .TX_RESETDONE_OUT(tx_resetdone_out),
- .drpclk_in(drpclk_in),
- .gt0_pll0refclklost_in(gt0_pll0refclklost_in),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_refclk1(gt_refclk1),
- .init_clk_in(init_clk_in),
- .quad1_common_lock_in(quad1_common_lock_in),
- .sync_clk(sync_clk),
- .sys_reset_out(sys_reset_out),
- .tx_lock(tx_lock),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_AURORA_LANE_4BYTE" *)
-module east_channel_east_channel_AURORA_LANE_4BYTE
- (LANE_UP,
- ena_comma_align_i,
- tx_reset_i,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- D,
- LINK_RESET_OUT,
- got_v_i,
- rx_polarity_i,
- hard_err_i,
- Q,
- ready_r_reg,
- \previous_cycle_data_r_reg[7] ,
- \previous_cycle_control_r_reg[0] ,
- neqOp,
- \RX_SUF_Buffer_reg[0] ,
- rx_pe_data_striped_i,
- \data_nxt2_reg[26] ,
- \data_nxt2_reg[26]_0 ,
- \data_nxt2_reg[25] ,
- \RX_SUF_Buffer_reg[1] ,
- \SOFT_ERR_Buffer_reg[0] ,
- TXDATA,
- \CHAR_IS_K_OUT_reg[3] ,
- \RX_PE_DATA_V_reg[0] ,
- p_9_out,
- p_8_out,
- reset_lanes_i,
- user_clk,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[1]_0 ,
- \word_aligned_control_bits_r_reg[3] ,
- \word_aligned_control_bits_r_reg[2] ,
- hard_err_gt0,
- init_clk_in,
- gen_cc_i,
- HPCNT_RESET,
- \fc_nb_r_reg[0] ,
- \fc_nb_r_reg[1] ,
- \fc_nb_r_reg[2] ,
- rx_realign_i,
- \bypass_r_reg[0] ,
- RXNOTINTABLE,
- RXDISPERR,
- reset_count_r_reg,
- RXDATA,
- RXCHARISK,
- \RX_CHAR_IS_COMMA_R_reg[3] ,
- \word_aligned_data_r_reg[24] ,
- \word_aligned_data_r_reg[16] ,
- \soft_err_r_reg[0] ,
- \soft_err_r_reg[1] ,
- \soft_err_r_reg[2] ,
- \soft_err_r_reg[3] ,
- SS,
- \gen_v_r_reg[1] ,
- \gen_pad_r_reg[0] ,
- \tx_pe_data_v_r_reg[0] ,
- GEN_SUF,
- GEN_ECP,
- GEN_SCP,
- \gen_r_r_reg[0] ,
- \gen_k_r_reg[0] ,
- \tx_pe_data_r_reg[0] ,
- GEN_A);
- output LANE_UP;
- output ena_comma_align_i;
- output tx_reset_i;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output [0:0]D;
- output LINK_RESET_OUT;
- output got_v_i;
- output rx_polarity_i;
- output hard_err_i;
- output [1:0]Q;
- output ready_r_reg;
- output [7:0]\previous_cycle_data_r_reg[7] ;
- output [0:0]\previous_cycle_control_r_reg[0] ;
- output neqOp;
- output [1:0]\RX_SUF_Buffer_reg[0] ;
- output [0:31]rx_pe_data_striped_i;
- output \data_nxt2_reg[26] ;
- output \data_nxt2_reg[26]_0 ;
- output \data_nxt2_reg[25] ;
- output \RX_SUF_Buffer_reg[1] ;
- output [1:0]\SOFT_ERR_Buffer_reg[0] ;
- output [31:0]TXDATA;
- output [3:0]\CHAR_IS_K_OUT_reg[3] ;
- output [1:0]\RX_PE_DATA_V_reg[0] ;
- output [1:0]p_9_out;
- output [1:0]p_8_out;
- input reset_lanes_i;
- input user_clk;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[1]_0 ;
- input \word_aligned_control_bits_r_reg[3] ;
- input \word_aligned_control_bits_r_reg[2] ;
- input hard_err_gt0;
- input init_clk_in;
- input gen_cc_i;
- input HPCNT_RESET;
- input \fc_nb_r_reg[0] ;
- input \fc_nb_r_reg[1] ;
- input \fc_nb_r_reg[2] ;
- input rx_realign_i;
- input \bypass_r_reg[0] ;
- input [1:0]RXNOTINTABLE;
- input [1:0]RXDISPERR;
- input reset_count_r_reg;
- input [31:0]RXDATA;
- input [3:0]RXCHARISK;
- input [3:0]\RX_CHAR_IS_COMMA_R_reg[3] ;
- input [7:0]\word_aligned_data_r_reg[24] ;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input \soft_err_r_reg[0] ;
- input \soft_err_r_reg[1] ;
- input \soft_err_r_reg[2] ;
- input \soft_err_r_reg[3] ;
- input [0:0]SS;
- input [2:0]\gen_v_r_reg[1] ;
- input [1:0]\gen_pad_r_reg[0] ;
- input [1:0]\tx_pe_data_v_r_reg[0] ;
- input [0:0]GEN_SUF;
- input [0:0]GEN_ECP;
- input [0:0]GEN_SCP;
- input [3:0]\gen_r_r_reg[0] ;
- input [3:0]\gen_k_r_reg[0] ;
- input [31:0]\tx_pe_data_r_reg[0] ;
- input GEN_A;
-
- wire BYPASS;
- wire BYPASS_2;
- wire [3:0]\CHAR_IS_K_OUT_reg[3] ;
- wire [0:0]D;
- wire D_0;
- wire EN;
- wire EN_3;
- wire GEN_A;
- wire [0:0]GEN_ECP;
- wire [0:0]GEN_SCP;
- wire [0:0]GEN_SUF;
- wire HPCNT_RESET;
- wire LANE_UP;
- wire LINK_RESET_OUT;
- wire [1:0]Q;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire [1:0]RXNOTINTABLE;
- wire [3:0]\RX_CHAR_IS_COMMA_R_reg[3] ;
- wire [1:0]\RX_PE_DATA_V_reg[0] ;
- wire [1:0]\RX_SUF_Buffer_reg[0] ;
- wire \RX_SUF_Buffer_reg[1] ;
- wire [1:0]\SOFT_ERR_Buffer_reg[0] ;
- wire [0:0]SS;
- wire [31:0]TXDATA;
- wire begin_r0;
- wire \bypass_r_reg[0] ;
- wire bypass_w_reg;
- wire counter4_r0;
- wire \data_nxt2_reg[25] ;
- wire \data_nxt2_reg[26] ;
- wire \data_nxt2_reg[26]_0 ;
- wire [15:0]dout_temp;
- wire [15:0]dout_temp_1;
- wire \east_channel_descrambler0_i/p_0_in ;
- wire \east_channel_descrambler0_i/p_0_in3_in ;
- wire \east_channel_descrambler0_i/p_11_in ;
- wire \east_channel_descrambler0_i/p_12_in ;
- wire \east_channel_descrambler0_i/p_13_in28_in ;
- wire \east_channel_descrambler0_i/p_14_in ;
- wire \east_channel_descrambler0_i/p_15_in25_in ;
- wire \east_channel_descrambler0_i/p_1_in ;
- wire \east_channel_descrambler0_i/p_2_in ;
- wire \east_channel_descrambler0_i/p_3_in ;
- wire \east_channel_descrambler0_i/p_5_in ;
- wire \east_channel_descrambler0_i/p_6_in ;
- wire \east_channel_descrambler0_i/p_7_in ;
- wire \east_channel_descrambler0_i/p_8_in ;
- wire \east_channel_descrambler0_i/p_9_in ;
- wire \east_channel_descrambler1_i/p_0_in ;
- wire \east_channel_descrambler1_i/p_0_in3_in ;
- wire \east_channel_descrambler1_i/p_11_in ;
- wire \east_channel_descrambler1_i/p_12_in ;
- wire \east_channel_descrambler1_i/p_13_in28_in ;
- wire \east_channel_descrambler1_i/p_14_in ;
- wire \east_channel_descrambler1_i/p_15_in25_in ;
- wire \east_channel_descrambler1_i/p_1_in ;
- wire \east_channel_descrambler1_i/p_2_in ;
- wire \east_channel_descrambler1_i/p_3_in ;
- wire \east_channel_descrambler1_i/p_5_in ;
- wire \east_channel_descrambler1_i/p_6_in ;
- wire \east_channel_descrambler1_i/p_7_in ;
- wire \east_channel_descrambler1_i/p_8_in ;
- wire \east_channel_descrambler1_i/p_9_in ;
- wire east_channel_descrambler_top_i_n_18;
- wire east_channel_descrambler_top_i_n_34;
- wire east_channel_descrambler_top_i_n_74;
- wire \east_channel_scrambler0_i/p_0_in ;
- wire \east_channel_scrambler0_i/p_0_in3_in ;
- wire \east_channel_scrambler0_i/p_11_in ;
- wire \east_channel_scrambler0_i/p_12_in ;
- wire \east_channel_scrambler0_i/p_13_in28_in ;
- wire \east_channel_scrambler0_i/p_14_in ;
- wire \east_channel_scrambler0_i/p_15_in25_in ;
- wire \east_channel_scrambler0_i/p_1_in ;
- wire \east_channel_scrambler0_i/p_2_in ;
- wire \east_channel_scrambler0_i/p_3_in ;
- wire \east_channel_scrambler0_i/p_5_in ;
- wire \east_channel_scrambler0_i/p_6_in ;
- wire \east_channel_scrambler0_i/p_7_in ;
- wire \east_channel_scrambler0_i/p_8_in ;
- wire \east_channel_scrambler0_i/p_9_in ;
- wire \east_channel_scrambler1_i/p_0_in ;
- wire \east_channel_scrambler1_i/p_0_in3_in ;
- wire \east_channel_scrambler1_i/p_11_in ;
- wire \east_channel_scrambler1_i/p_12_in ;
- wire \east_channel_scrambler1_i/p_13_in28_in ;
- wire \east_channel_scrambler1_i/p_14_in ;
- wire \east_channel_scrambler1_i/p_15_in25_in ;
- wire \east_channel_scrambler1_i/p_1_in ;
- wire \east_channel_scrambler1_i/p_2_in ;
- wire \east_channel_scrambler1_i/p_3_in ;
- wire \east_channel_scrambler1_i/p_5_in ;
- wire \east_channel_scrambler1_i/p_6_in ;
- wire \east_channel_scrambler1_i/p_7_in ;
- wire \east_channel_scrambler1_i/p_8_in ;
- wire \east_channel_scrambler1_i/p_9_in ;
- wire east_channel_scrambler_top_i_n_15;
- wire east_channel_scrambler_top_i_n_31;
- wire east_channel_sym_dec_4byte_i_n_40;
- wire east_channel_sym_dec_4byte_i_n_45;
- wire east_channel_sym_dec_4byte_i_n_46;
- wire east_channel_sym_dec_4byte_i_n_47;
- wire east_channel_sym_dec_4byte_i_n_48;
- wire east_channel_sym_dec_4byte_i_n_49;
- wire east_channel_sym_dec_4byte_i_n_50;
- wire east_channel_sym_dec_4byte_i_n_51;
- wire east_channel_sym_dec_4byte_i_n_52;
- wire east_channel_sym_dec_4byte_i_n_53;
- wire east_channel_sym_dec_4byte_i_n_54;
- wire east_channel_sym_dec_4byte_i_n_55;
- wire east_channel_sym_dec_4byte_i_n_56;
- wire east_channel_sym_dec_4byte_i_n_57;
- wire east_channel_sym_dec_4byte_i_n_58;
- wire east_channel_sym_dec_4byte_i_n_59;
- wire east_channel_sym_dec_4byte_i_n_60;
- wire east_channel_sym_gen_4byte_i_n_10;
- wire east_channel_sym_gen_4byte_i_n_11;
- wire east_channel_sym_gen_4byte_i_n_12;
- wire east_channel_sym_gen_4byte_i_n_13;
- wire east_channel_sym_gen_4byte_i_n_14;
- wire east_channel_sym_gen_4byte_i_n_15;
- wire east_channel_sym_gen_4byte_i_n_16;
- wire east_channel_sym_gen_4byte_i_n_17;
- wire east_channel_sym_gen_4byte_i_n_18;
- wire east_channel_sym_gen_4byte_i_n_19;
- wire east_channel_sym_gen_4byte_i_n_20;
- wire east_channel_sym_gen_4byte_i_n_21;
- wire east_channel_sym_gen_4byte_i_n_22;
- wire east_channel_sym_gen_4byte_i_n_56;
- wire east_channel_sym_gen_4byte_i_n_7;
- wire east_channel_sym_gen_4byte_i_n_73;
- wire east_channel_sym_gen_4byte_i_n_8;
- wire east_channel_sym_gen_4byte_i_n_9;
- wire ena_comma_align_i;
- wire enable_err_detect_i;
- wire \fc_nb_r_reg[0] ;
- wire \fc_nb_r_reg[1] ;
- wire \fc_nb_r_reg[2] ;
- wire first_v_received_r;
- wire gen_cc_i;
- wire gen_cc_r;
- wire [3:0]\gen_k_r_reg[0] ;
- wire [1:0]\gen_pad_r_reg[0] ;
- wire [3:0]\gen_r_r_reg[0] ;
- wire gen_sp_i;
- wire gen_spa_i;
- wire gen_spa_r;
- wire gen_v_r;
- wire gen_v_r2;
- wire [2:0]\gen_v_r_reg[1] ;
- wire good_cnt_r3;
- wire got_v_descram_in;
- wire got_v_i;
- wire hard_err_gt0;
- wire hard_err_i;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[1] ;
- wire \left_align_select_r_reg[1]_0 ;
- wire neqOp;
- wire p_0_in_0;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [0:0]\previous_cycle_control_r_reg[0] ;
- wire [7:0]\previous_cycle_data_r_reg[7] ;
- wire ready_r_reg;
- wire reset_count_r_reg;
- wire reset_lanes_i;
- wire rx_neg_descram_in;
- wire rx_neg_i;
- wire [0:31]rx_pe_data_descram_in;
- wire [0:31]rx_pe_data_striped_i;
- wire [0:1]rx_pe_data_v_descram_in;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire rx_sp_descram_in;
- wire rx_spa_descram_in;
- wire [0:1]rx_suf_descram_in;
- wire \soft_err_r_reg[0] ;
- wire \soft_err_r_reg[1] ;
- wire \soft_err_r_reg[2] ;
- wire \soft_err_r_reg[3] ;
- wire [3:0]tx_char_is_k_i;
- wire [31:0]tx_data_i;
- wire [31:0]\tx_pe_data_r_reg[0] ;
- wire [1:0]\tx_pe_data_v_r_reg[0] ;
- wire tx_reset_i;
- wire user_clk;
- wire \word_aligned_control_bits_r_reg[2] ;
- wire \word_aligned_control_bits_r_reg[3] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
- wire [7:0]\word_aligned_data_r_reg[24] ;
-
- east_channel_east_channel_DESCRAMBLER_TOP east_channel_descrambler_top_i
- (.BYPASS(BYPASS),
- .D({east_channel_sym_dec_4byte_i_n_45,east_channel_sym_dec_4byte_i_n_46,east_channel_sym_dec_4byte_i_n_47,east_channel_sym_dec_4byte_i_n_48,east_channel_sym_dec_4byte_i_n_49,east_channel_sym_dec_4byte_i_n_50,east_channel_sym_dec_4byte_i_n_51,east_channel_sym_dec_4byte_i_n_52,east_channel_sym_dec_4byte_i_n_53,east_channel_sym_dec_4byte_i_n_54,east_channel_sym_dec_4byte_i_n_55,east_channel_sym_dec_4byte_i_n_56,east_channel_sym_dec_4byte_i_n_57,east_channel_sym_dec_4byte_i_n_58,east_channel_sym_dec_4byte_i_n_59,east_channel_sym_dec_4byte_i_n_60}),
- .\DOUT_reg[0] (east_channel_sym_dec_4byte_i_n_40),
- .\DOUT_reg[15] (dout_temp),
- .D_0(D_0),
- .E(EN),
- .Q({\east_channel_descrambler0_i/p_11_in ,\east_channel_descrambler0_i/p_8_in ,\east_channel_descrambler0_i/p_6_in ,\east_channel_descrambler0_i/p_3_in ,\east_channel_descrambler0_i/p_2_in ,\east_channel_descrambler0_i/p_0_in3_in ,\east_channel_descrambler0_i/p_0_in ,\east_channel_descrambler0_i/p_1_in ,\east_channel_descrambler0_i/p_15_in25_in ,\east_channel_descrambler0_i/p_14_in ,\east_channel_descrambler0_i/p_13_in28_in ,\east_channel_descrambler0_i/p_12_in ,\east_channel_descrambler0_i/p_9_in ,\east_channel_descrambler0_i/p_7_in ,\east_channel_descrambler0_i/p_5_in ,east_channel_descrambler_top_i_n_18}),
- .\RX_PE_DATA_V_reg[0]_0 (\RX_PE_DATA_V_reg[0] ),
- .\RX_PE_DATA_V_reg[0]_1 ({rx_pe_data_v_descram_in[0],rx_pe_data_v_descram_in[1]}),
- .RX_SPA_reg_0(east_channel_descrambler_top_i_n_74),
- .\RX_SUF_Buffer_reg[0]_0 (\RX_SUF_Buffer_reg[0] ),
- .\RX_SUF_Buffer_reg[0]_1 ({rx_suf_descram_in[0],rx_suf_descram_in[1]}),
- .\RX_SUF_Buffer_reg[1]_0 (\RX_SUF_Buffer_reg[1] ),
- .SS(SS),
- .bypass_w_reg(bypass_w_reg),
- .counter4_r0(counter4_r0),
- .\data_nxt2_reg[25]_0 (\data_nxt2_reg[25] ),
- .\data_nxt2_reg[26]_0 (\data_nxt2_reg[26] ),
- .\data_nxt2_reg[26]_1 (\data_nxt2_reg[26]_0 ),
- .gen_spa_i(gen_spa_i),
- .got_v_descram_in(got_v_descram_in),
- .got_v_i(got_v_i),
- .\lfsr_reg[15] ({\east_channel_descrambler1_i/p_11_in ,\east_channel_descrambler1_i/p_8_in ,\east_channel_descrambler1_i/p_6_in ,\east_channel_descrambler1_i/p_3_in ,\east_channel_descrambler1_i/p_2_in ,\east_channel_descrambler1_i/p_0_in3_in ,\east_channel_descrambler1_i/p_0_in ,\east_channel_descrambler1_i/p_1_in ,\east_channel_descrambler1_i/p_15_in25_in ,\east_channel_descrambler1_i/p_14_in ,\east_channel_descrambler1_i/p_13_in28_in ,\east_channel_descrambler1_i/p_12_in ,\east_channel_descrambler1_i/p_9_in ,\east_channel_descrambler1_i/p_7_in ,\east_channel_descrambler1_i/p_5_in ,east_channel_descrambler_top_i_n_34}),
- .neqOp(neqOp),
- .rx_neg_descram_in(rx_neg_descram_in),
- .rx_neg_i(rx_neg_i),
- .rx_pe_data_descram_in(rx_pe_data_descram_in),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .rx_sp_descram_in(rx_sp_descram_in),
- .rx_spa_descram_in(rx_spa_descram_in),
- .user_clk(user_clk));
- east_channel_east_channel_ERR_DETECT_4BYTE east_channel_err_detect_4byte_i
- (.\SOFT_ERR_Buffer_reg[0]_0 (\SOFT_ERR_Buffer_reg[0] ),
- .begin_r0(begin_r0),
- .enable_err_detect_i(enable_err_detect_i),
- .good_cnt_r3(good_cnt_r3),
- .hard_err_gt0(hard_err_gt0),
- .hard_err_i(hard_err_i),
- .reset_lanes_i(reset_lanes_i),
- .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
- .\soft_err_r_reg[1]_0 (\soft_err_r_reg[1] ),
- .\soft_err_r_reg[2]_0 (\soft_err_r_reg[2] ),
- .\soft_err_r_reg[3]_0 (\soft_err_r_reg[3] ),
- .user_clk(user_clk));
- east_channel_east_channel_HOTPLUG east_channel_hotplug_i
- (.D(D),
- .HPCNT_RESET(HPCNT_RESET),
- .LINK_RESET_OUT(LINK_RESET_OUT),
- .init_clk_in(init_clk_in),
- .reset_lanes_i(reset_lanes_i),
- .user_clk(user_clk));
- east_channel_east_channel_LANE_INIT_SM_4BYTE east_channel_lane_init_sm_4byte_i
- (.D(D_0),
- .GEN_SP(gen_sp_i),
- .LANE_UP(LANE_UP),
- .RXDISPERR(RXDISPERR),
- .RXNOTINTABLE(RXNOTINTABLE),
- .\RX_CHAR_IS_COMMA_R_reg[3]_0 (\RX_CHAR_IS_COMMA_R_reg[3] ),
- .align_r_reg_0(ena_comma_align_i),
- .begin_r0(begin_r0),
- .\counter3_r_reg[3]_0 (east_channel_descrambler_top_i_n_74),
- .counter4_r0(counter4_r0),
- .enable_err_detect_i(enable_err_detect_i),
- .first_v_received_r(first_v_received_r),
- .gen_spa_i(gen_spa_i),
- .gen_spa_r(gen_spa_r),
- .good_cnt_r3(good_cnt_r3),
- .ready_r_reg_0(ready_r_reg),
- .reset_count_r_reg_0(reset_count_r_reg),
- .reset_lanes_i(reset_lanes_i),
- .rst_r_reg_0(tx_reset_i),
- .rx_neg_i(rx_neg_i),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .user_clk(user_clk));
- east_channel_east_channel_SCRAMBLER_TOP east_channel_scrambler_top_i
- (.BYPASS(BYPASS_2),
- .\CHAR_IS_K_OUT_reg[3]_0 (\CHAR_IS_K_OUT_reg[3] ),
- .\CHAR_IS_K_OUT_reg[3]_1 (tx_char_is_k_i),
- .D(dout_temp_1),
- .\DOUT_reg[0] (EN_3),
- .\DOUT_reg[15] ({east_channel_sym_gen_4byte_i_n_7,east_channel_sym_gen_4byte_i_n_8,east_channel_sym_gen_4byte_i_n_9,east_channel_sym_gen_4byte_i_n_10,east_channel_sym_gen_4byte_i_n_11,east_channel_sym_gen_4byte_i_n_12,east_channel_sym_gen_4byte_i_n_13,east_channel_sym_gen_4byte_i_n_14,east_channel_sym_gen_4byte_i_n_15,east_channel_sym_gen_4byte_i_n_16,east_channel_sym_gen_4byte_i_n_17,east_channel_sym_gen_4byte_i_n_18,east_channel_sym_gen_4byte_i_n_19,east_channel_sym_gen_4byte_i_n_20,east_channel_sym_gen_4byte_i_n_21,east_channel_sym_gen_4byte_i_n_22}),
- .E(east_channel_sym_gen_4byte_i_n_56),
- .Q({\east_channel_scrambler0_i/p_11_in ,\east_channel_scrambler0_i/p_8_in ,\east_channel_scrambler0_i/p_6_in ,\east_channel_scrambler0_i/p_3_in ,\east_channel_scrambler0_i/p_2_in ,\east_channel_scrambler0_i/p_0_in3_in ,\east_channel_scrambler0_i/p_0_in ,\east_channel_scrambler0_i/p_1_in ,\east_channel_scrambler0_i/p_15_in25_in ,\east_channel_scrambler0_i/p_14_in ,\east_channel_scrambler0_i/p_13_in28_in ,\east_channel_scrambler0_i/p_12_in ,\east_channel_scrambler0_i/p_9_in ,\east_channel_scrambler0_i/p_7_in ,\east_channel_scrambler0_i/p_5_in ,east_channel_scrambler_top_i_n_15}),
- .TXDATA(TXDATA),
- .\bypass_r_reg[0]_0 (east_channel_sym_gen_4byte_i_n_73),
- .\data_nxt_reg[31]_0 (tx_data_i),
- .gen_cc_r(gen_cc_r),
- .gen_v_r2(gen_v_r2),
- .\lfsr_reg[15] ({\east_channel_scrambler1_i/p_11_in ,\east_channel_scrambler1_i/p_8_in ,\east_channel_scrambler1_i/p_6_in ,\east_channel_scrambler1_i/p_3_in ,\east_channel_scrambler1_i/p_2_in ,\east_channel_scrambler1_i/p_0_in3_in ,\east_channel_scrambler1_i/p_0_in ,\east_channel_scrambler1_i/p_1_in ,\east_channel_scrambler1_i/p_15_in25_in ,\east_channel_scrambler1_i/p_14_in ,\east_channel_scrambler1_i/p_13_in28_in ,\east_channel_scrambler1_i/p_12_in ,\east_channel_scrambler1_i/p_9_in ,\east_channel_scrambler1_i/p_7_in ,\east_channel_scrambler1_i/p_5_in ,east_channel_scrambler_top_i_n_31}),
- .\lfsr_reg[15]_0 (\bypass_r_reg[0] ),
- .reset_lanes_i(reset_lanes_i),
- .user_clk(user_clk));
- east_channel_east_channel_SYM_DEC_4BYTE east_channel_sym_dec_4byte_i
- (.BYPASS(BYPASS),
- .CHANNEL_UP_Buffer_reg(east_channel_sym_dec_4byte_i_n_40),
- .D(D),
- .\DOUT_reg[0] ({\east_channel_descrambler1_i/p_11_in ,\east_channel_descrambler1_i/p_8_in ,\east_channel_descrambler1_i/p_6_in ,\east_channel_descrambler1_i/p_3_in ,\east_channel_descrambler1_i/p_2_in ,\east_channel_descrambler1_i/p_0_in3_in ,\east_channel_descrambler1_i/p_0_in ,\east_channel_descrambler1_i/p_1_in ,\east_channel_descrambler1_i/p_15_in25_in ,\east_channel_descrambler1_i/p_14_in ,\east_channel_descrambler1_i/p_13_in28_in ,\east_channel_descrambler1_i/p_12_in ,\east_channel_descrambler1_i/p_9_in ,\east_channel_descrambler1_i/p_7_in ,\east_channel_descrambler1_i/p_5_in ,east_channel_descrambler_top_i_n_34}),
- .\DOUT_reg[0]_0 ({\east_channel_descrambler0_i/p_11_in ,\east_channel_descrambler0_i/p_8_in ,\east_channel_descrambler0_i/p_6_in ,\east_channel_descrambler0_i/p_3_in ,\east_channel_descrambler0_i/p_2_in ,\east_channel_descrambler0_i/p_0_in3_in ,\east_channel_descrambler0_i/p_0_in ,\east_channel_descrambler0_i/p_1_in ,\east_channel_descrambler0_i/p_15_in25_in ,\east_channel_descrambler0_i/p_14_in ,\east_channel_descrambler0_i/p_13_in28_in ,\east_channel_descrambler0_i/p_12_in ,\east_channel_descrambler0_i/p_9_in ,\east_channel_descrambler0_i/p_7_in ,\east_channel_descrambler0_i/p_5_in ,east_channel_descrambler_top_i_n_18}),
- .E(EN),
- .LANE_UP(LANE_UP),
- .Q(Q),
- .RXCHARISK(RXCHARISK),
- .RXDATA(RXDATA),
- .\RX_PE_DATA_Buffer_reg[0]_0 (dout_temp),
- .\RX_PE_DATA_Buffer_reg[16]_0 ({east_channel_sym_dec_4byte_i_n_45,east_channel_sym_dec_4byte_i_n_46,east_channel_sym_dec_4byte_i_n_47,east_channel_sym_dec_4byte_i_n_48,east_channel_sym_dec_4byte_i_n_49,east_channel_sym_dec_4byte_i_n_50,east_channel_sym_dec_4byte_i_n_51,east_channel_sym_dec_4byte_i_n_52,east_channel_sym_dec_4byte_i_n_53,east_channel_sym_dec_4byte_i_n_54,east_channel_sym_dec_4byte_i_n_55,east_channel_sym_dec_4byte_i_n_56,east_channel_sym_dec_4byte_i_n_57,east_channel_sym_dec_4byte_i_n_58,east_channel_sym_dec_4byte_i_n_59,east_channel_sym_dec_4byte_i_n_60}),
- .\RX_PE_DATA_V_Buffer_reg[0]_0 ({rx_pe_data_v_descram_in[0],rx_pe_data_v_descram_in[1]}),
- .\RX_SUF_Buffer_reg[0]_0 ({rx_suf_descram_in[0],rx_suf_descram_in[1]}),
- .\bypass_r_reg[0] (\bypass_r_reg[0] ),
- .bypass_w_reg(bypass_w_reg),
- .first_v_received_r(first_v_received_r),
- .got_v_descram_in(got_v_descram_in),
- .\left_align_select_r_reg[0]_0 (\left_align_select_r_reg[0] ),
- .\left_align_select_r_reg[0]_1 (\left_align_select_r_reg[0]_0 ),
- .\left_align_select_r_reg[1]_0 (\left_align_select_r_reg[1] ),
- .\left_align_select_r_reg[1]_1 (\left_align_select_r_reg[1]_0 ),
- .p_8_out(p_8_out),
- .p_9_out(p_9_out),
- .\previous_cycle_control_r_reg[0]_0 (\previous_cycle_control_r_reg[0] ),
- .\previous_cycle_data_r_reg[7]_0 (\previous_cycle_data_r_reg[7] ),
- .reset_lanes_i(reset_lanes_i),
- .rx_neg_descram_in(rx_neg_descram_in),
- .rx_pe_data_descram_in(rx_pe_data_descram_in),
- .rx_sp_descram_in(rx_sp_descram_in),
- .rx_spa_descram_in(rx_spa_descram_in),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2]_0 (\word_aligned_control_bits_r_reg[2] ),
- .\word_aligned_control_bits_r_reg[3]_0 (\word_aligned_control_bits_r_reg[3] ),
- .\word_aligned_data_r_reg[16]_0 (\word_aligned_data_r_reg[16] ),
- .\word_aligned_data_r_reg[24]_0 (\word_aligned_data_r_reg[24] ));
- east_channel_east_channel_SYM_GEN_4BYTE east_channel_sym_gen_4byte_i
- (.BYPASS(BYPASS_2),
- .CHANNEL_UP_Buffer_reg(EN_3),
- .D(dout_temp_1),
- .\DOUT_reg[0] ({\east_channel_scrambler1_i/p_11_in ,\east_channel_scrambler1_i/p_8_in ,\east_channel_scrambler1_i/p_6_in ,\east_channel_scrambler1_i/p_3_in ,\east_channel_scrambler1_i/p_2_in ,\east_channel_scrambler1_i/p_0_in3_in ,\east_channel_scrambler1_i/p_0_in ,\east_channel_scrambler1_i/p_1_in ,\east_channel_scrambler1_i/p_15_in25_in ,\east_channel_scrambler1_i/p_14_in ,\east_channel_scrambler1_i/p_13_in28_in ,\east_channel_scrambler1_i/p_12_in ,\east_channel_scrambler1_i/p_9_in ,\east_channel_scrambler1_i/p_7_in ,\east_channel_scrambler1_i/p_5_in ,east_channel_scrambler_top_i_n_31}),
- .E(east_channel_sym_gen_4byte_i_n_56),
- .GEN_A(GEN_A),
- .GEN_ECP(GEN_ECP),
- .GEN_SCP(GEN_SCP),
- .GEN_SP(gen_sp_i),
- .GEN_SUF(GEN_SUF),
- .Q({\east_channel_scrambler0_i/p_11_in ,\east_channel_scrambler0_i/p_8_in ,\east_channel_scrambler0_i/p_6_in ,\east_channel_scrambler0_i/p_3_in ,\east_channel_scrambler0_i/p_2_in ,\east_channel_scrambler0_i/p_0_in3_in ,\east_channel_scrambler0_i/p_0_in ,\east_channel_scrambler0_i/p_1_in ,\east_channel_scrambler0_i/p_15_in25_in ,\east_channel_scrambler0_i/p_14_in ,\east_channel_scrambler0_i/p_13_in28_in ,\east_channel_scrambler0_i/p_12_in ,\east_channel_scrambler0_i/p_9_in ,\east_channel_scrambler0_i/p_7_in ,\east_channel_scrambler0_i/p_5_in ,east_channel_scrambler_top_i_n_15}),
- .\TX_CHAR_IS_K_Buffer_reg[1]_0 (east_channel_sym_gen_4byte_i_n_73),
- .\TX_CHAR_IS_K_Buffer_reg[3]_0 (tx_char_is_k_i),
- .\TX_DATA_Buffer_reg[31]_0 ({east_channel_sym_gen_4byte_i_n_7,east_channel_sym_gen_4byte_i_n_8,east_channel_sym_gen_4byte_i_n_9,east_channel_sym_gen_4byte_i_n_10,east_channel_sym_gen_4byte_i_n_11,east_channel_sym_gen_4byte_i_n_12,east_channel_sym_gen_4byte_i_n_13,east_channel_sym_gen_4byte_i_n_14,east_channel_sym_gen_4byte_i_n_15,east_channel_sym_gen_4byte_i_n_16,east_channel_sym_gen_4byte_i_n_17,east_channel_sym_gen_4byte_i_n_18,east_channel_sym_gen_4byte_i_n_19,east_channel_sym_gen_4byte_i_n_20,east_channel_sym_gen_4byte_i_n_21,east_channel_sym_gen_4byte_i_n_22}),
- .\TX_DATA_Buffer_reg[31]_1 (tx_data_i),
- .\bypass_r_reg[0] (\bypass_r_reg[0] ),
- .\fc_nb_r_reg[0]_0 (\fc_nb_r_reg[0] ),
- .\fc_nb_r_reg[1]_0 (\fc_nb_r_reg[1] ),
- .\fc_nb_r_reg[2]_0 (\fc_nb_r_reg[2] ),
- .gen_cc_i(gen_cc_i),
- .gen_cc_r(gen_cc_r),
- .\gen_k_r_reg[0]_0 (\gen_k_r_reg[0] ),
- .\gen_pad_r_reg[0]_0 (\gen_pad_r_reg[0] ),
- .\gen_r_r_reg[0]_0 (\gen_r_r_reg[0] ),
- .gen_spa_i(gen_spa_i),
- .gen_spa_r(gen_spa_r),
- .gen_v_r2(gen_v_r2),
- .\gen_v_r_reg[1]_0 (\gen_v_r_reg[1] ),
- .reset_lanes_i(reset_lanes_i),
- .\tx_pe_data_r_reg[0]_0 (\tx_pe_data_r_reg[0] ),
- .\tx_pe_data_v_r_reg[0]_0 (\tx_pe_data_v_r_reg[0] ),
- .user_clk(user_clk));
- LUT3 #(
- .INIT(8'hFE))
- gen_v_r0
- (.I0(\gen_v_r_reg[1] [1]),
- .I1(\gen_v_r_reg[1] [0]),
- .I2(\gen_v_r_reg[1] [2]),
- .O(p_0_in_0));
- FDRE gen_v_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_v_r),
- .Q(gen_v_r2),
- .R(1'b0));
- FDRE gen_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in_0),
- .Q(gen_v_r),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_AXI_TO_LL" *)
-module east_channel_east_channel_AXI_TO_LL
- (new_pkt_r_reg_0,
- new_pkt_r,
- user_clk);
- output new_pkt_r_reg_0;
- input new_pkt_r;
- input user_clk;
-
- wire new_pkt_r;
- wire new_pkt_r_reg_0;
- wire user_clk;
-
- FDRE new_pkt_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(new_pkt_r),
- .Q(new_pkt_r_reg_0),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_CHANNEL_ERR_DETECT" *)
-module east_channel_east_channel_CHANNEL_ERR_DETECT
- (SOFT_ERR,
- HARD_ERR,
- reset_channel_i,
- user_clk,
- hard_err_i,
- LANE_UP,
- POWER_DOWN,
- \soft_err_r_reg[0]_0 );
- output SOFT_ERR;
- output HARD_ERR;
- output reset_channel_i;
- input user_clk;
- input hard_err_i;
- input LANE_UP;
- input POWER_DOWN;
- input [1:0]\soft_err_r_reg[0]_0 ;
-
- wire HARD_ERR;
- wire LANE_UP;
- wire POWER_DOWN;
- wire RESET_CHANNEL_Buffer0;
- wire SOFT_ERR;
- wire channel_soft_err_c;
- wire hard_err_i;
- wire hard_err_r;
- wire lane_up_r;
- wire reset_channel_i;
- wire [1:0]soft_err_r;
- wire [1:0]\soft_err_r_reg[0]_0 ;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b1))
- CHANNEL_HARD_ERR_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(hard_err_r),
- .Q(HARD_ERR),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- CHANNEL_SOFT_ERR_Buffer_i_1
- (.I0(soft_err_r[1]),
- .I1(soft_err_r[0]),
- .O(channel_soft_err_c));
- FDRE #(
- .INIT(1'b1))
- CHANNEL_SOFT_ERR_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(channel_soft_err_c),
- .Q(SOFT_ERR),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- RESET_CHANNEL_Buffer_i_1
- (.I0(POWER_DOWN),
- .I1(lane_up_r),
- .O(RESET_CHANNEL_Buffer0));
- FDRE #(
- .INIT(1'b1))
- RESET_CHANNEL_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(RESET_CHANNEL_Buffer0),
- .Q(reset_channel_i),
- .R(1'b0));
- FDRE hard_err_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(hard_err_i),
- .Q(hard_err_r),
- .R(1'b0));
- FDRE lane_up_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(LANE_UP),
- .Q(lane_up_r),
- .R(1'b0));
- FDRE \soft_err_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[0]_0 [1]),
- .Q(soft_err_r[1]),
- .R(1'b0));
- FDRE \soft_err_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[0]_0 [0]),
- .Q(soft_err_r[0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_CHANNEL_INIT_SM" *)
-module east_channel_east_channel_CHANNEL_INIT_SM
- (reset_lanes_i,
- GTRXRESET_OUT,
- gen_ver_i,
- CHANNEL_UP_Buffer_reg_0,
- START_RX,
- SS,
- CHANNEL_UP_Buffer_reg_1,
- RESET,
- user_clk,
- got_v_i,
- wait_for_lane_up_r0,
- START_RX_Buffer_reg_0,
- \txver_count_r_reg[7]_0 ,
- D,
- reset_channel_i);
- output reset_lanes_i;
- output GTRXRESET_OUT;
- output gen_ver_i;
- output CHANNEL_UP_Buffer_reg_0;
- output START_RX;
- output [0:0]SS;
- output CHANNEL_UP_Buffer_reg_1;
- output RESET;
- input user_clk;
- input got_v_i;
- input wait_for_lane_up_r0;
- input START_RX_Buffer_reg_0;
- input \txver_count_r_reg[7]_0 ;
- input [0:0]D;
- input reset_channel_i;
-
- wire CHANNEL_UP_Buffer_reg_0;
- wire CHANNEL_UP_Buffer_reg_1;
- wire [0:0]D;
- wire D_0;
- wire GTRXRESET_OUT;
- wire GTRXRESET_OUT_i_1_n_0;
- wire GTRXRESET_OUT_i_2_n_0;
- wire Q;
- wire RESET;
- wire [0:0]SS;
- wire START_RX;
- wire START_RX_Buffer0;
- wire START_RX_Buffer_reg_0;
- wire all_lanes_v_r;
- wire bad_v_r;
- wire bad_v_r0;
- wire \free_count_r[13]_i_2_n_0 ;
- wire \free_count_r[13]_i_3_n_0 ;
- wire \free_count_r[13]_i_4_n_0 ;
- wire \free_count_r[13]_i_5_n_0 ;
- wire \free_count_r[1]_i_2_n_0 ;
- wire \free_count_r[1]_i_3_n_0 ;
- wire \free_count_r[5]_i_2_n_0 ;
- wire \free_count_r[5]_i_3_n_0 ;
- wire \free_count_r[5]_i_4_n_0 ;
- wire \free_count_r[5]_i_5_n_0 ;
- wire \free_count_r[9]_i_2_n_0 ;
- wire \free_count_r[9]_i_3_n_0 ;
- wire \free_count_r[9]_i_4_n_0 ;
- wire \free_count_r[9]_i_5_n_0 ;
- wire [0:13]free_count_r_reg;
- wire \free_count_r_reg[13]_i_1_n_0 ;
- wire \free_count_r_reg[13]_i_1_n_1 ;
- wire \free_count_r_reg[13]_i_1_n_2 ;
- wire \free_count_r_reg[13]_i_1_n_3 ;
- wire \free_count_r_reg[13]_i_1_n_4 ;
- wire \free_count_r_reg[13]_i_1_n_5 ;
- wire \free_count_r_reg[13]_i_1_n_6 ;
- wire \free_count_r_reg[13]_i_1_n_7 ;
- wire \free_count_r_reg[1]_i_1_n_3 ;
- wire \free_count_r_reg[1]_i_1_n_6 ;
- wire \free_count_r_reg[1]_i_1_n_7 ;
- wire \free_count_r_reg[5]_i_1_n_0 ;
- wire \free_count_r_reg[5]_i_1_n_1 ;
- wire \free_count_r_reg[5]_i_1_n_2 ;
- wire \free_count_r_reg[5]_i_1_n_3 ;
- wire \free_count_r_reg[5]_i_1_n_4 ;
- wire \free_count_r_reg[5]_i_1_n_5 ;
- wire \free_count_r_reg[5]_i_1_n_6 ;
- wire \free_count_r_reg[5]_i_1_n_7 ;
- wire \free_count_r_reg[9]_i_1_n_0 ;
- wire \free_count_r_reg[9]_i_1_n_1 ;
- wire \free_count_r_reg[9]_i_1_n_2 ;
- wire \free_count_r_reg[9]_i_1_n_3 ;
- wire \free_count_r_reg[9]_i_1_n_4 ;
- wire \free_count_r_reg[9]_i_1_n_5 ;
- wire \free_count_r_reg[9]_i_1_n_6 ;
- wire \free_count_r_reg[9]_i_1_n_7 ;
- wire gen_ver_i;
- wire got_first_v_r;
- wire got_first_v_r_i_1_n_0;
- wire got_v_i;
- wire [7:0]gtrxreset_extend_r;
- wire next_ready_c;
- wire next_verify_c;
- wire [15:15]p_2_out;
- wire p_3_in;
- wire ready_r;
- wire ready_r2;
- wire reset_channel_i;
- wire reset_lanes_i;
- wire rxver_count_r0;
- wire \rxver_count_r_reg[1]_srl2_n_0 ;
- wire \rxver_count_r_reg_n_0_[2] ;
- wire \txver_count_r_reg[6]_srl7_n_0 ;
- wire \txver_count_r_reg[7]_0 ;
- wire \txver_count_r_reg_n_0_[7] ;
- wire user_clk;
- wire \v_count_r_reg[14]_srl15_n_0 ;
- wire \v_count_r_reg_n_0_[15] ;
- wire verify_watchdog_r0;
- wire \verify_watchdog_r_reg[14]_srl15_i_2_n_0 ;
- wire \verify_watchdog_r_reg[14]_srl15_i_3_n_0 ;
- wire \verify_watchdog_r_reg[14]_srl15_n_0 ;
- wire \verify_watchdog_r_reg_n_0_[15] ;
- wire wait_for_lane_up_r;
- wire wait_for_lane_up_r0;
- wire [3:1]\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED ;
- wire [3:2]\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED ;
-
- FDRE CHANNEL_UP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ready_r2),
- .Q(CHANNEL_UP_Buffer_reg_0),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- FRAME_ERR_Buffer_i_1
- (.I0(START_RX),
- .O(RESET));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- GTRXRESET_OUT_i_1
- (.I0(gtrxreset_extend_r[2]),
- .I1(gtrxreset_extend_r[3]),
- .I2(gtrxreset_extend_r[0]),
- .I3(gtrxreset_extend_r[1]),
- .I4(GTRXRESET_OUT_i_2_n_0),
- .O(GTRXRESET_OUT_i_1_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- GTRXRESET_OUT_i_2
- (.I0(gtrxreset_extend_r[5]),
- .I1(gtrxreset_extend_r[4]),
- .I2(gtrxreset_extend_r[7]),
- .I3(gtrxreset_extend_r[6]),
- .O(GTRXRESET_OUT_i_2_n_0));
- FDRE GTRXRESET_OUT_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GTRXRESET_OUT_i_1_n_0),
- .Q(GTRXRESET_OUT),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- START_RX_Buffer_i_1
- (.I0(wait_for_lane_up_r),
- .O(START_RX_Buffer0));
- FDRE START_RX_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(START_RX_Buffer0),
- .Q(START_RX),
- .R(START_RX_Buffer_reg_0));
- FDRE all_lanes_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(got_v_i),
- .Q(all_lanes_v_r),
- .R(1'b0));
- LUT3 #(
- .INIT(8'h48))
- bad_v_r_i_1
- (.I0(all_lanes_v_r),
- .I1(got_first_v_r),
- .I2(\v_count_r_reg_n_0_[15] ),
- .O(bad_v_r0));
- FDRE bad_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(bad_v_r0),
- .Q(bad_v_r),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_2
- (.I0(free_count_r_reg[10]),
- .O(\free_count_r[13]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_3
- (.I0(free_count_r_reg[11]),
- .O(\free_count_r[13]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_4
- (.I0(free_count_r_reg[12]),
- .O(\free_count_r[13]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_5
- (.I0(free_count_r_reg[13]),
- .O(\free_count_r[13]_i_5_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[1]_i_2
- (.I0(free_count_r_reg[0]),
- .O(\free_count_r[1]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[1]_i_3
- (.I0(free_count_r_reg[1]),
- .O(\free_count_r[1]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_2
- (.I0(free_count_r_reg[2]),
- .O(\free_count_r[5]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_3
- (.I0(free_count_r_reg[3]),
- .O(\free_count_r[5]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_4
- (.I0(free_count_r_reg[4]),
- .O(\free_count_r[5]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_5
- (.I0(free_count_r_reg[5]),
- .O(\free_count_r[5]_i_5_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_2
- (.I0(free_count_r_reg[6]),
- .O(\free_count_r[9]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_3
- (.I0(free_count_r_reg[7]),
- .O(\free_count_r[9]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_4
- (.I0(free_count_r_reg[8]),
- .O(\free_count_r[9]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_5
- (.I0(free_count_r_reg[9]),
- .O(\free_count_r[9]_i_5_n_0 ));
- FDSE \free_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[1]_i_1_n_6 ),
- .Q(free_count_r_reg[0]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_4 ),
- .Q(free_count_r_reg[10]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_5 ),
- .Q(free_count_r_reg[11]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_6 ),
- .Q(free_count_r_reg[12]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_7 ),
- .Q(free_count_r_reg[13]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[13]_i_1
- (.CI(1'b0),
- .CO({\free_count_r_reg[13]_i_1_n_0 ,\free_count_r_reg[13]_i_1_n_1 ,\free_count_r_reg[13]_i_1_n_2 ,\free_count_r_reg[13]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O({\free_count_r_reg[13]_i_1_n_4 ,\free_count_r_reg[13]_i_1_n_5 ,\free_count_r_reg[13]_i_1_n_6 ,\free_count_r_reg[13]_i_1_n_7 }),
- .S({\free_count_r[13]_i_2_n_0 ,\free_count_r[13]_i_3_n_0 ,\free_count_r[13]_i_4_n_0 ,\free_count_r[13]_i_5_n_0 }));
- FDSE \free_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[1]_i_1_n_7 ),
- .Q(free_count_r_reg[1]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[1]_i_1
- (.CI(\free_count_r_reg[5]_i_1_n_0 ),
- .CO({\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED [3:1],\free_count_r_reg[1]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED [3:2],\free_count_r_reg[1]_i_1_n_6 ,\free_count_r_reg[1]_i_1_n_7 }),
- .S({1'b0,1'b0,\free_count_r[1]_i_2_n_0 ,\free_count_r[1]_i_3_n_0 }));
- FDSE \free_count_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_4 ),
- .Q(free_count_r_reg[2]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_5 ),
- .Q(free_count_r_reg[3]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_6 ),
- .Q(free_count_r_reg[4]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_7 ),
- .Q(free_count_r_reg[5]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[5]_i_1
- (.CI(\free_count_r_reg[9]_i_1_n_0 ),
- .CO({\free_count_r_reg[5]_i_1_n_0 ,\free_count_r_reg[5]_i_1_n_1 ,\free_count_r_reg[5]_i_1_n_2 ,\free_count_r_reg[5]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O({\free_count_r_reg[5]_i_1_n_4 ,\free_count_r_reg[5]_i_1_n_5 ,\free_count_r_reg[5]_i_1_n_6 ,\free_count_r_reg[5]_i_1_n_7 }),
- .S({\free_count_r[5]_i_2_n_0 ,\free_count_r[5]_i_3_n_0 ,\free_count_r[5]_i_4_n_0 ,\free_count_r[5]_i_5_n_0 }));
- FDSE \free_count_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_4 ),
- .Q(free_count_r_reg[6]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_5 ),
- .Q(free_count_r_reg[7]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_6 ),
- .Q(free_count_r_reg[8]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_7 ),
- .Q(free_count_r_reg[9]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[9]_i_1
- (.CI(\free_count_r_reg[13]_i_1_n_0 ),
- .CO({\free_count_r_reg[9]_i_1_n_0 ,\free_count_r_reg[9]_i_1_n_1 ,\free_count_r_reg[9]_i_1_n_2 ,\free_count_r_reg[9]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O({\free_count_r_reg[9]_i_1_n_4 ,\free_count_r_reg[9]_i_1_n_5 ,\free_count_r_reg[9]_i_1_n_6 ,\free_count_r_reg[9]_i_1_n_7 }),
- .S({\free_count_r[9]_i_2_n_0 ,\free_count_r[9]_i_3_n_0 ,\free_count_r[9]_i_4_n_0 ,\free_count_r[9]_i_5_n_0 }));
- (* SOFT_HLUTNM = "soft_lutpair129" *)
- LUT3 #(
- .INIT(8'hA8))
- got_first_v_r_i_1
- (.I0(gen_ver_i),
- .I1(got_first_v_r),
- .I2(all_lanes_v_r),
- .O(got_first_v_r_i_1_n_0));
- FDRE got_first_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(got_first_v_r_i_1_n_0),
- .Q(got_first_v_r),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gtreset_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_in),
- .Q(Q),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hAE00))
- gtreset_flop_0_i_i_1
- (.I0(\verify_watchdog_r_reg_n_0_[15] ),
- .I1(bad_v_r),
- .I2(\rxver_count_r_reg_n_0_[2] ),
- .I3(gen_ver_i),
- .O(p_3_in));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[1]),
- .Q(gtrxreset_extend_r[0]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[2]),
- .Q(gtrxreset_extend_r[1]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[3]),
- .Q(gtrxreset_extend_r[2]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[4]),
- .Q(gtrxreset_extend_r[3]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[5]),
- .Q(gtrxreset_extend_r[4]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[6]),
- .Q(gtrxreset_extend_r[5]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[7]),
- .Q(gtrxreset_extend_r[6]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q),
- .Q(gtrxreset_extend_r[7]),
- .R(START_RX_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair131" *)
- LUT3 #(
- .INIT(8'hFD))
- \lfsr[15]_i_1__0
- (.I0(CHANNEL_UP_Buffer_reg_0),
- .I1(reset_lanes_i),
- .I2(D),
- .O(SS));
- FDRE ready_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ready_r),
- .Q(ready_r2),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair130" *)
- LUT4 #(
- .INIT(16'hFF80))
- ready_r_i_1__0
- (.I0(\txver_count_r_reg_n_0_[7] ),
- .I1(\rxver_count_r_reg_n_0_[2] ),
- .I2(gen_ver_i),
- .I3(ready_r),
- .O(next_ready_c));
- FDRE ready_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ready_c),
- .Q(ready_r),
- .R(wait_for_lane_up_r0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- reset_lanes_flop_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D_0),
- .Q(reset_lanes_i),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hFFAE))
- reset_lanes_flop_i_i_1
- (.I0(START_RX_Buffer_reg_0),
- .I1(reset_channel_i),
- .I2(wait_for_lane_up_r),
- .I3(p_3_in),
- .O(D_0));
- (* srl_bus_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/rxver_count_r_reg " *)
- (* srl_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/rxver_count_r_reg[1]_srl2 " *)
- SRL16E \rxver_count_r_reg[1]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(rxver_count_r0),
- .CLK(user_clk),
- .D(gen_ver_i),
- .Q(\rxver_count_r_reg[1]_srl2_n_0 ));
- LUT3 #(
- .INIT(8'h8F))
- \rxver_count_r_reg[1]_srl2_i_1
- (.I0(\v_count_r_reg_n_0_[15] ),
- .I1(all_lanes_v_r),
- .I2(gen_ver_i),
- .O(rxver_count_r0));
- FDRE \rxver_count_r_reg[2]
- (.C(user_clk),
- .CE(rxver_count_r0),
- .D(\rxver_count_r_reg[1]_srl2_n_0 ),
- .Q(\rxver_count_r_reg_n_0_[2] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/txver_count_r_reg " *)
- (* srl_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/txver_count_r_reg[6]_srl7 " *)
- SRL16E \txver_count_r_reg[6]_srl7
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b0),
- .CE(\txver_count_r_reg[7]_0 ),
- .CLK(user_clk),
- .D(gen_ver_i),
- .Q(\txver_count_r_reg[6]_srl7_n_0 ));
- FDRE \txver_count_r_reg[7]
- (.C(user_clk),
- .CE(\txver_count_r_reg[7]_0 ),
- .D(\txver_count_r_reg[6]_srl7_n_0 ),
- .Q(\txver_count_r_reg_n_0_[7] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair131" *)
- LUT1 #(
- .INIT(2'h1))
- ufc_header_r_i_1
- (.I0(CHANNEL_UP_Buffer_reg_0),
- .O(CHANNEL_UP_Buffer_reg_1));
- (* srl_bus_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/v_count_r_reg " *)
- (* srl_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/v_count_r_reg[14]_srl15 " *)
- SRL16E \v_count_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_2_out),
- .Q(\v_count_r_reg[14]_srl15_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair129" *)
- LUT4 #(
- .INIT(16'hF444))
- \v_count_r_reg[14]_srl15_i_1
- (.I0(got_first_v_r),
- .I1(all_lanes_v_r),
- .I2(gen_ver_i),
- .I3(\v_count_r_reg_n_0_[15] ),
- .O(p_2_out));
- FDRE \v_count_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\v_count_r_reg[14]_srl15_n_0 ),
- .Q(\v_count_r_reg_n_0_[15] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair130" *)
- LUT4 #(
- .INIT(16'hFF2A))
- verify_r_i_2
- (.I0(gen_ver_i),
- .I1(\txver_count_r_reg_n_0_[7] ),
- .I2(\rxver_count_r_reg_n_0_[2] ),
- .I3(wait_for_lane_up_r),
- .O(next_verify_c));
- FDRE verify_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_verify_c),
- .Q(gen_ver_i),
- .R(wait_for_lane_up_r0));
- (* srl_bus_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/verify_watchdog_r_reg " *)
- (* srl_name = "U0/\east_channel_global_logic_i/channel_init_sm_i/verify_watchdog_r_reg[14]_srl15 " *)
- SRL16E \verify_watchdog_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(verify_watchdog_r0),
- .CLK(user_clk),
- .D(gen_ver_i),
- .Q(\verify_watchdog_r_reg[14]_srl15_n_0 ));
- LUT5 #(
- .INIT(32'h0200FFFF))
- \verify_watchdog_r_reg[14]_srl15_i_1
- (.I0(\verify_watchdog_r_reg[14]_srl15_i_2_n_0 ),
- .I1(free_count_r_reg[12]),
- .I2(free_count_r_reg[13]),
- .I3(\verify_watchdog_r_reg[14]_srl15_i_3_n_0 ),
- .I4(gen_ver_i),
- .O(verify_watchdog_r0));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \verify_watchdog_r_reg[14]_srl15_i_2
- (.I0(free_count_r_reg[9]),
- .I1(free_count_r_reg[8]),
- .I2(free_count_r_reg[11]),
- .I3(free_count_r_reg[10]),
- .I4(free_count_r_reg[6]),
- .I5(free_count_r_reg[7]),
- .O(\verify_watchdog_r_reg[14]_srl15_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \verify_watchdog_r_reg[14]_srl15_i_3
- (.I0(free_count_r_reg[3]),
- .I1(free_count_r_reg[2]),
- .I2(free_count_r_reg[5]),
- .I3(free_count_r_reg[4]),
- .I4(free_count_r_reg[0]),
- .I5(free_count_r_reg[1]),
- .O(\verify_watchdog_r_reg[14]_srl15_i_3_n_0 ));
- FDRE \verify_watchdog_r_reg[15]
- (.C(user_clk),
- .CE(verify_watchdog_r0),
- .D(\verify_watchdog_r_reg[14]_srl15_n_0 ),
- .Q(\verify_watchdog_r_reg_n_0_[15] ),
- .R(1'b0));
- FDRE wait_for_lane_up_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(wait_for_lane_up_r0),
- .Q(wait_for_lane_up_r),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_DESCRAMBLER_TOP" *)
-module east_channel_east_channel_DESCRAMBLER_TOP
- (rx_neg_i,
- got_v_i,
- counter4_r0,
- Q,
- \lfsr_reg[15] ,
- neqOp,
- \RX_SUF_Buffer_reg[0]_0 ,
- rx_pe_data_striped_i,
- \data_nxt2_reg[26]_0 ,
- \data_nxt2_reg[26]_1 ,
- \data_nxt2_reg[25]_0 ,
- \RX_SUF_Buffer_reg[1]_0 ,
- RX_SPA_reg_0,
- \RX_PE_DATA_V_reg[0]_0 ,
- rx_sp_descram_in,
- user_clk,
- rx_spa_descram_in,
- rx_neg_descram_in,
- got_v_descram_in,
- rx_pe_data_descram_in,
- D_0,
- gen_spa_i,
- SS,
- E,
- \DOUT_reg[0] ,
- BYPASS,
- bypass_w_reg,
- D,
- \DOUT_reg[15] ,
- \RX_PE_DATA_V_reg[0]_1 ,
- \RX_SUF_Buffer_reg[0]_1 );
- output rx_neg_i;
- output got_v_i;
- output counter4_r0;
- output [15:0]Q;
- output [15:0]\lfsr_reg[15] ;
- output neqOp;
- output [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- output [0:31]rx_pe_data_striped_i;
- output \data_nxt2_reg[26]_0 ;
- output \data_nxt2_reg[26]_1 ;
- output \data_nxt2_reg[25]_0 ;
- output \RX_SUF_Buffer_reg[1]_0 ;
- output RX_SPA_reg_0;
- output [1:0]\RX_PE_DATA_V_reg[0]_0 ;
- input rx_sp_descram_in;
- input user_clk;
- input rx_spa_descram_in;
- input rx_neg_descram_in;
- input got_v_descram_in;
- input [0:31]rx_pe_data_descram_in;
- input D_0;
- input gen_spa_i;
- input [0:0]SS;
- input [0:0]E;
- input [0:0]\DOUT_reg[0] ;
- input BYPASS;
- input bypass_w_reg;
- input [15:0]D;
- input [15:0]\DOUT_reg[15] ;
- input [1:0]\RX_PE_DATA_V_reg[0]_1 ;
- input [1:0]\RX_SUF_Buffer_reg[0]_1 ;
-
- wire BYPASS;
- wire [15:0]D;
- wire [0:0]\DOUT_reg[0] ;
- wire [15:0]\DOUT_reg[15] ;
- wire D_0;
- wire [0:0]E;
- wire [15:0]Q;
- wire [1:0]\RX_PE_DATA_V_reg[0]_0 ;
- wire [1:0]\RX_PE_DATA_V_reg[0]_1 ;
- wire RX_SPA_reg_0;
- wire [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- wire [1:0]\RX_SUF_Buffer_reg[0]_1 ;
- wire \RX_SUF_Buffer_reg[1]_0 ;
- wire [0:0]SS;
- wire \bypass_r_reg_n_0_[0] ;
- wire \bypass_r_reg_n_0_[1] ;
- wire bypass_w_reg;
- wire counter4_r0;
- wire \data_nxt2_reg[25]_0 ;
- wire \data_nxt2_reg[26]_0 ;
- wire \data_nxt2_reg[26]_1 ;
- wire \data_nxt2_reg_n_0_[0] ;
- wire \data_nxt2_reg_n_0_[10] ;
- wire \data_nxt2_reg_n_0_[11] ;
- wire \data_nxt2_reg_n_0_[12] ;
- wire \data_nxt2_reg_n_0_[13] ;
- wire \data_nxt2_reg_n_0_[14] ;
- wire \data_nxt2_reg_n_0_[15] ;
- wire \data_nxt2_reg_n_0_[16] ;
- wire \data_nxt2_reg_n_0_[17] ;
- wire \data_nxt2_reg_n_0_[18] ;
- wire \data_nxt2_reg_n_0_[19] ;
- wire \data_nxt2_reg_n_0_[1] ;
- wire \data_nxt2_reg_n_0_[20] ;
- wire \data_nxt2_reg_n_0_[21] ;
- wire \data_nxt2_reg_n_0_[22] ;
- wire \data_nxt2_reg_n_0_[23] ;
- wire \data_nxt2_reg_n_0_[24] ;
- wire \data_nxt2_reg_n_0_[25] ;
- wire \data_nxt2_reg_n_0_[26] ;
- wire \data_nxt2_reg_n_0_[27] ;
- wire \data_nxt2_reg_n_0_[28] ;
- wire \data_nxt2_reg_n_0_[29] ;
- wire \data_nxt2_reg_n_0_[2] ;
- wire \data_nxt2_reg_n_0_[30] ;
- wire \data_nxt2_reg_n_0_[31] ;
- wire \data_nxt2_reg_n_0_[3] ;
- wire \data_nxt2_reg_n_0_[4] ;
- wire \data_nxt2_reg_n_0_[5] ;
- wire \data_nxt2_reg_n_0_[6] ;
- wire \data_nxt2_reg_n_0_[7] ;
- wire \data_nxt2_reg_n_0_[8] ;
- wire \data_nxt2_reg_n_0_[9] ;
- wire gen_spa_i;
- wire got_v_descram_in;
- wire got_v_i;
- wire [15:0]\lfsr_reg[15] ;
- wire neqOp;
- wire rx_neg_descram_in;
- wire rx_neg_i;
- wire [0:31]rx_pe_data_descram_in;
- wire [0:31]rx_pe_data_striped_i;
- wire rx_sp_descram_in;
- wire rx_sp_i;
- wire rx_spa_descram_in;
- wire rx_spa_i;
- wire user_clk;
-
- FDRE GOT_V_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(got_v_descram_in),
- .Q(got_v_i),
- .R(1'b0));
- FDRE RX_NEG_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_neg_descram_in),
- .Q(rx_neg_i),
- .R(1'b0));
- FDRE \RX_PE_DATA_V_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_reg[0]_1 [1]),
- .Q(\RX_PE_DATA_V_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_PE_DATA_V_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_reg[0]_1 [0]),
- .Q(\RX_PE_DATA_V_reg[0]_0 [0]),
- .R(1'b0));
- FDRE RX_SPA_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_spa_descram_in),
- .Q(rx_spa_i),
- .R(1'b0));
- FDRE RX_SP_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_sp_descram_in),
- .Q(rx_sp_i),
- .R(1'b0));
- FDRE \RX_SUF_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_SUF_Buffer_reg[0]_1 [1]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_SUF_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_SUF_Buffer_reg[0]_1 [0]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \bypass_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(bypass_w_reg),
- .Q(\bypass_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \bypass_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(BYPASS),
- .Q(\bypass_r_reg_n_0_[1] ),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- \counter3_r_reg[2]_srl3_i_1
- (.I0(rx_spa_i),
- .I1(gen_spa_i),
- .O(RX_SPA_reg_0));
- LUT2 #(
- .INIT(4'hB))
- \counter4_r_reg[14]_srl15_i_1
- (.I0(rx_sp_i),
- .I1(D_0),
- .O(counter4_r0));
- FDRE \data_nxt2_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[0]),
- .Q(\data_nxt2_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[10]),
- .Q(\data_nxt2_reg_n_0_[10] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[11]),
- .Q(\data_nxt2_reg_n_0_[11] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[12]),
- .Q(\data_nxt2_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[13]),
- .Q(\data_nxt2_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[14]),
- .Q(\data_nxt2_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[15]),
- .Q(\data_nxt2_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[16]),
- .Q(\data_nxt2_reg_n_0_[16] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[17]),
- .Q(\data_nxt2_reg_n_0_[17] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[18]),
- .Q(\data_nxt2_reg_n_0_[18] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[19]),
- .Q(\data_nxt2_reg_n_0_[19] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[1]),
- .Q(\data_nxt2_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[20]),
- .Q(\data_nxt2_reg_n_0_[20] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[21]),
- .Q(\data_nxt2_reg_n_0_[21] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[22]),
- .Q(\data_nxt2_reg_n_0_[22] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[23]),
- .Q(\data_nxt2_reg_n_0_[23] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[24]),
- .Q(\data_nxt2_reg_n_0_[24] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[25]),
- .Q(\data_nxt2_reg_n_0_[25] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[26]),
- .Q(\data_nxt2_reg_n_0_[26] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[27]),
- .Q(\data_nxt2_reg_n_0_[27] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[28]),
- .Q(\data_nxt2_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[29]),
- .Q(\data_nxt2_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[2]),
- .Q(\data_nxt2_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[30]),
- .Q(\data_nxt2_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[31]),
- .Q(\data_nxt2_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[3]),
- .Q(\data_nxt2_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[4]),
- .Q(\data_nxt2_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[5]),
- .Q(\data_nxt2_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[6]),
- .Q(\data_nxt2_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[7]),
- .Q(\data_nxt2_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[8]),
- .Q(\data_nxt2_reg_n_0_[8] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[9]),
- .Q(\data_nxt2_reg_n_0_[9] ),
- .R(1'b0));
- east_channel_east_channel_SCRAMBLER_25 east_channel_descrambler0_i
- (.\DOUT_reg[15]_0 (\DOUT_reg[15] ),
- .E(E),
- .Q(Q),
- .SS(SS),
- .rx_pe_data_striped_i({rx_pe_data_striped_i[0],rx_pe_data_striped_i[1],rx_pe_data_striped_i[2],rx_pe_data_striped_i[3],rx_pe_data_striped_i[4],rx_pe_data_striped_i[5],rx_pe_data_striped_i[6],rx_pe_data_striped_i[7],rx_pe_data_striped_i[8],rx_pe_data_striped_i[9],rx_pe_data_striped_i[10],rx_pe_data_striped_i[11],rx_pe_data_striped_i[12],rx_pe_data_striped_i[13],rx_pe_data_striped_i[14],rx_pe_data_striped_i[15]}),
- .\stage_1_data_r_reg[0] ({\data_nxt2_reg_n_0_[0] ,\data_nxt2_reg_n_0_[1] ,\data_nxt2_reg_n_0_[2] ,\data_nxt2_reg_n_0_[3] ,\data_nxt2_reg_n_0_[4] ,\data_nxt2_reg_n_0_[5] ,\data_nxt2_reg_n_0_[6] ,\data_nxt2_reg_n_0_[7] ,\data_nxt2_reg_n_0_[12] ,\data_nxt2_reg_n_0_[13] ,\data_nxt2_reg_n_0_[14] ,\data_nxt2_reg_n_0_[15] }),
- .\stage_1_data_r_reg[10] (\data_nxt2_reg_n_0_[10] ),
- .\stage_1_data_r_reg[11] (\data_nxt2_reg_n_0_[11] ),
- .\stage_1_data_r_reg[15] (\bypass_r_reg_n_0_[0] ),
- .\stage_1_data_r_reg[8] (\data_nxt2_reg_n_0_[8] ),
- .\stage_1_data_r_reg[9] (\data_nxt2_reg_n_0_[9] ),
- .user_clk(user_clk));
- east_channel_east_channel_SCRAMBLER_26 east_channel_descrambler1_i
- (.D(D),
- .\DOUT_reg[0]_0 (\DOUT_reg[0] ),
- .Q(\lfsr_reg[15] ),
- .SS(SS),
- .rx_pe_data_striped_i({rx_pe_data_striped_i[16],rx_pe_data_striped_i[17],rx_pe_data_striped_i[18],rx_pe_data_striped_i[19],rx_pe_data_striped_i[20],rx_pe_data_striped_i[21],rx_pe_data_striped_i[22],rx_pe_data_striped_i[23],rx_pe_data_striped_i[24],rx_pe_data_striped_i[25],rx_pe_data_striped_i[26],rx_pe_data_striped_i[27],rx_pe_data_striped_i[28],rx_pe_data_striped_i[29],rx_pe_data_striped_i[30],rx_pe_data_striped_i[31]}),
- .\stage_1_data_r_reg[16] ({\data_nxt2_reg_n_0_[16] ,\data_nxt2_reg_n_0_[17] ,\data_nxt2_reg_n_0_[18] ,\data_nxt2_reg_n_0_[19] ,\data_nxt2_reg_n_0_[20] ,\data_nxt2_reg_n_0_[21] ,\data_nxt2_reg_n_0_[22] ,\data_nxt2_reg_n_0_[23] ,\data_nxt2_reg_n_0_[28] ,\data_nxt2_reg_n_0_[29] ,\data_nxt2_reg_n_0_[30] ,\data_nxt2_reg_n_0_[31] }),
- .\stage_1_data_r_reg[24] (\data_nxt2_reg_n_0_[24] ),
- .\stage_1_data_r_reg[25] (\data_nxt2_reg_n_0_[25] ),
- .\stage_1_data_r_reg[26] (\data_nxt2_reg_n_0_[26] ),
- .\stage_1_data_r_reg[27] (\data_nxt2_reg_n_0_[27] ),
- .\stage_1_data_r_reg[31] (\bypass_r_reg_n_0_[1] ),
- .user_clk(user_clk));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT2 #(
- .INIT(4'hE))
- load_ufc_control_code_r_i_1
- (.I0(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I1(\RX_SUF_Buffer_reg[0]_0 [0]),
- .O(neqOp));
- LUT4 #(
- .INIT(16'h8000))
- \stage_1_count_value_r[0]_i_1
- (.I0(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I1(\data_nxt2_reg_n_0_[24] ),
- .I2(\data_nxt2_reg_n_0_[26] ),
- .I3(\data_nxt2_reg_n_0_[25] ),
- .O(\RX_SUF_Buffer_reg[1]_0 ));
- LUT6 #(
- .INIT(64'h78FF780078007800))
- \stage_1_count_value_r[1]_i_1
- (.I0(\data_nxt2_reg_n_0_[25] ),
- .I1(\data_nxt2_reg_n_0_[26] ),
- .I2(\data_nxt2_reg_n_0_[24] ),
- .I3(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I4(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I5(\data_nxt2_reg_n_0_[8] ),
- .O(\data_nxt2_reg[25]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT5 #(
- .INIT(32'h6F606060))
- \stage_1_count_value_r[2]_i_1
- (.I0(\data_nxt2_reg_n_0_[26] ),
- .I1(\data_nxt2_reg_n_0_[25] ),
- .I2(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I3(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I4(\data_nxt2_reg_n_0_[9] ),
- .O(\data_nxt2_reg[26]_1 ));
- LUT4 #(
- .INIT(16'h7444))
- \stage_1_count_value_r[3]_i_1
- (.I0(\data_nxt2_reg_n_0_[26] ),
- .I1(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I2(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I3(\data_nxt2_reg_n_0_[10] ),
- .O(\data_nxt2_reg[26]_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_ERR_DETECT_4BYTE" *)
-module east_channel_east_channel_ERR_DETECT_4BYTE
- (begin_r0,
- hard_err_i,
- \SOFT_ERR_Buffer_reg[0]_0 ,
- good_cnt_r3,
- user_clk,
- hard_err_gt0,
- reset_lanes_i,
- enable_err_detect_i,
- \soft_err_r_reg[0]_0 ,
- \soft_err_r_reg[1]_0 ,
- \soft_err_r_reg[2]_0 ,
- \soft_err_r_reg[3]_0 );
- output begin_r0;
- output hard_err_i;
- output [1:0]\SOFT_ERR_Buffer_reg[0]_0 ;
- input good_cnt_r3;
- input user_clk;
- input hard_err_gt0;
- input reset_lanes_i;
- input enable_err_detect_i;
- input \soft_err_r_reg[0]_0 ;
- input \soft_err_r_reg[1]_0 ;
- input \soft_err_r_reg[2]_0 ;
- input \soft_err_r_reg[3]_0 ;
-
- wire [1:0]\SOFT_ERR_Buffer_reg[0]_0 ;
- wire begin_r0;
- wire cnt_good_code_r;
- wire cnt_good_code_r_i_2_n_0;
- wire cnt_good_code_r_i_3_n_0;
- wire cnt_soft_err_r;
- wire enable_err_detect_i;
- wire \err_cnt_r[0]_i_1_n_0 ;
- wire \err_cnt_r[1]_i_1_n_0 ;
- wire \err_cnt_r[2]_i_1_n_0 ;
- wire \err_cnt_r[2]_i_2_n_0 ;
- wire \err_cnt_r_reg_n_0_[0] ;
- wire \err_cnt_r_reg_n_0_[1] ;
- wire good_cnt_r3;
- wire \good_cnt_r[3]_i_1_n_0 ;
- wire [3:0]good_cnt_r_reg;
- wire hard_err_frm_soft_err;
- wire hard_err_gt;
- wire hard_err_gt0;
- wire hard_err_i;
- wire next_good_code_c;
- wire next_soft_err_c;
- wire next_start_c;
- wire p_0_in;
- wire p_1_in;
- wire p_2_in;
- wire [1:0]p_3_out;
- wire [3:0]plusOp;
- wire reset_lanes_i;
- wire \soft_err_r_reg[0]_0 ;
- wire \soft_err_r_reg[1]_0 ;
- wire \soft_err_r_reg[2]_0 ;
- wire \soft_err_r_reg[3]_0 ;
- wire \soft_err_r_reg_n_0_[0] ;
- wire \soft_err_r_reg_n_0_[3] ;
- wire start_r;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'hE))
- \SOFT_ERR_Buffer[0]_i_1
- (.I0(p_2_in),
- .I1(\soft_err_r_reg_n_0_[0] ),
- .O(p_3_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'hE))
- \SOFT_ERR_Buffer[1]_i_1
- (.I0(\soft_err_r_reg_n_0_[3] ),
- .I1(p_1_in),
- .O(p_3_out[0]));
- FDRE \SOFT_ERR_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[1]),
- .Q(\SOFT_ERR_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \SOFT_ERR_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[0]),
- .Q(\SOFT_ERR_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT4 #(
- .INIT(16'hFFAE))
- align_r_i_1
- (.I0(hard_err_gt),
- .I1(p_0_in),
- .I2(hard_err_frm_soft_err),
- .I3(reset_lanes_i),
- .O(begin_r0));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT4 #(
- .INIT(16'h00EA))
- cnt_good_code_r_i_1
- (.I0(cnt_soft_err_r),
- .I1(cnt_good_code_r_i_2_n_0),
- .I2(cnt_good_code_r),
- .I3(cnt_good_code_r_i_3_n_0),
- .O(next_good_code_c));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT4 #(
- .INIT(16'h7FFF))
- cnt_good_code_r_i_2
- (.I0(good_cnt_r_reg[2]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[1]),
- .I3(good_cnt_r_reg[3]),
- .O(cnt_good_code_r_i_2_n_0));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT4 #(
- .INIT(16'hFFFE))
- cnt_good_code_r_i_3
- (.I0(p_1_in),
- .I1(\soft_err_r_reg_n_0_[3] ),
- .I2(\soft_err_r_reg_n_0_[0] ),
- .I3(p_2_in),
- .O(cnt_good_code_r_i_3_n_0));
- FDRE cnt_good_code_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_good_code_c),
- .Q(cnt_good_code_r),
- .R(good_cnt_r3));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT4 #(
- .INIT(16'hFE00))
- cnt_soft_err_r_i_1
- (.I0(start_r),
- .I1(cnt_soft_err_r),
- .I2(cnt_good_code_r),
- .I3(cnt_good_code_r_i_3_n_0),
- .O(next_soft_err_c));
- FDRE cnt_soft_err_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_soft_err_c),
- .Q(cnt_soft_err_r),
- .R(good_cnt_r3));
- LUT5 #(
- .INIT(32'hBEBE4140))
- \err_cnt_r[0]_i_1
- (.I0(p_0_in),
- .I1(cnt_soft_err_r),
- .I2(\err_cnt_r[2]_i_2_n_0 ),
- .I3(\err_cnt_r_reg_n_0_[1] ),
- .I4(\err_cnt_r_reg_n_0_[0] ),
- .O(\err_cnt_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT5 #(
- .INIT(32'hAAAA6AA8))
- \err_cnt_r[1]_i_1
- (.I0(\err_cnt_r_reg_n_0_[1] ),
- .I1(\err_cnt_r_reg_n_0_[0] ),
- .I2(\err_cnt_r[2]_i_2_n_0 ),
- .I3(cnt_soft_err_r),
- .I4(p_0_in),
- .O(\err_cnt_r[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT5 #(
- .INIT(32'hFFFF8000))
- \err_cnt_r[2]_i_1
- (.I0(\err_cnt_r_reg_n_0_[1] ),
- .I1(\err_cnt_r_reg_n_0_[0] ),
- .I2(\err_cnt_r[2]_i_2_n_0 ),
- .I3(cnt_soft_err_r),
- .I4(p_0_in),
- .O(\err_cnt_r[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT4 #(
- .INIT(16'hEEEF))
- \err_cnt_r[2]_i_2
- (.I0(good_cnt_r_reg[1]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[3]),
- .I3(good_cnt_r_reg[2]),
- .O(\err_cnt_r[2]_i_2_n_0 ));
- FDRE \err_cnt_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\err_cnt_r[0]_i_1_n_0 ),
- .Q(\err_cnt_r_reg_n_0_[0] ),
- .R(good_cnt_r3));
- FDRE \err_cnt_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\err_cnt_r[1]_i_1_n_0 ),
- .Q(\err_cnt_r_reg_n_0_[1] ),
- .R(good_cnt_r3));
- FDRE \err_cnt_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\err_cnt_r[2]_i_1_n_0 ),
- .Q(p_0_in),
- .R(good_cnt_r3));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT1 #(
- .INIT(2'h1))
- \good_cnt_r[0]_i_1
- (.I0(good_cnt_r_reg[0]),
- .O(plusOp[0]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT2 #(
- .INIT(4'h6))
- \good_cnt_r[1]_i_1
- (.I0(good_cnt_r_reg[0]),
- .I1(good_cnt_r_reg[1]),
- .O(plusOp[1]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT3 #(
- .INIT(8'h78))
- \good_cnt_r[2]_i_1
- (.I0(good_cnt_r_reg[1]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[2]),
- .O(plusOp[2]));
- LUT4 #(
- .INIT(16'hFFF7))
- \good_cnt_r[3]_i_1
- (.I0(cnt_good_code_r),
- .I1(enable_err_detect_i),
- .I2(cnt_soft_err_r),
- .I3(start_r),
- .O(\good_cnt_r[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT4 #(
- .INIT(16'h7F80))
- \good_cnt_r[3]_i_2
- (.I0(good_cnt_r_reg[2]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[1]),
- .I3(good_cnt_r_reg[3]),
- .O(plusOp[3]));
- FDRE \good_cnt_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[0]),
- .Q(good_cnt_r_reg[0]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE \good_cnt_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[1]),
- .Q(good_cnt_r_reg[1]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE \good_cnt_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[2]),
- .Q(good_cnt_r_reg[2]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE \good_cnt_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[3]),
- .Q(good_cnt_r_reg[3]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE hard_err_frm_soft_err_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in),
- .Q(hard_err_frm_soft_err),
- .R(good_cnt_r3));
- FDRE hard_err_gt_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(hard_err_gt0),
- .Q(hard_err_gt),
- .R(good_cnt_r3));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT3 #(
- .INIT(8'hF4))
- hard_err_r_i_1
- (.I0(hard_err_frm_soft_err),
- .I1(p_0_in),
- .I2(hard_err_gt),
- .O(hard_err_i));
- FDRE \soft_err_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[0]_0 ),
- .Q(\soft_err_r_reg_n_0_[0] ),
- .R(good_cnt_r3));
- FDRE \soft_err_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[1]_0 ),
- .Q(p_2_in),
- .R(good_cnt_r3));
- FDRE \soft_err_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[2]_0 ),
- .Q(p_1_in),
- .R(good_cnt_r3));
- FDRE \soft_err_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[3]_0 ),
- .Q(\soft_err_r_reg_n_0_[3] ),
- .R(good_cnt_r3));
- LUT4 #(
- .INIT(16'h00BA))
- start_r_i_1
- (.I0(start_r),
- .I1(cnt_good_code_r_i_2_n_0),
- .I2(cnt_good_code_r),
- .I3(cnt_good_code_r_i_3_n_0),
- .O(next_start_c));
- FDSE start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_start_c),
- .Q(start_r),
- .S(good_cnt_r3));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_GLOBAL_LOGIC" *)
-module east_channel_east_channel_GLOBAL_LOGIC
- (reset_lanes_i,
- gen_v_flop_1_i,
- GEN_A,
- gen_k_flop_0_i,
- gen_r_flop_0_i,
- GTRXRESET_OUT,
- CHANNEL_UP_Buffer_reg,
- SOFT_ERR,
- HARD_ERR,
- reset_channel_i,
- START_RX,
- SS,
- CHANNEL_UP_Buffer_reg_0,
- RESET,
- user_clk,
- got_v_i,
- wait_for_lane_up_r0,
- hard_err_i,
- LANE_UP,
- \downcounter_r_reg[2] ,
- D,
- POWER_DOWN,
- \soft_err_r_reg[0] );
- output reset_lanes_i;
- output [2:0]gen_v_flop_1_i;
- output GEN_A;
- output [3:0]gen_k_flop_0_i;
- output [3:0]gen_r_flop_0_i;
- output GTRXRESET_OUT;
- output CHANNEL_UP_Buffer_reg;
- output SOFT_ERR;
- output HARD_ERR;
- output reset_channel_i;
- output START_RX;
- output [0:0]SS;
- output CHANNEL_UP_Buffer_reg_0;
- output RESET;
- input user_clk;
- input got_v_i;
- input wait_for_lane_up_r0;
- input hard_err_i;
- input LANE_UP;
- input \downcounter_r_reg[2] ;
- input [0:0]D;
- input POWER_DOWN;
- input [1:0]\soft_err_r_reg[0] ;
-
- wire CHANNEL_UP_Buffer_reg;
- wire CHANNEL_UP_Buffer_reg_0;
- wire [0:0]D;
- wire GEN_A;
- wire GTRXRESET_OUT;
- wire HARD_ERR;
- wire LANE_UP;
- wire POWER_DOWN;
- wire RESET;
- wire SOFT_ERR;
- wire [0:0]SS;
- wire START_RX;
- wire \downcounter_r_reg[2] ;
- wire [3:0]gen_k_flop_0_i;
- wire [3:0]gen_r_flop_0_i;
- wire [2:0]gen_v_flop_1_i;
- wire gen_ver_i;
- wire got_v_i;
- wire hard_err_i;
- wire idle_and_ver_gen_i_n_12;
- wire reset_channel_i;
- wire reset_lanes_i;
- wire [1:0]\soft_err_r_reg[0] ;
- wire user_clk;
- wire wait_for_lane_up_r0;
-
- east_channel_east_channel_CHANNEL_ERR_DETECT channel_err_detect_i
- (.HARD_ERR(HARD_ERR),
- .LANE_UP(LANE_UP),
- .POWER_DOWN(POWER_DOWN),
- .SOFT_ERR(SOFT_ERR),
- .hard_err_i(hard_err_i),
- .reset_channel_i(reset_channel_i),
- .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
- .user_clk(user_clk));
- east_channel_east_channel_CHANNEL_INIT_SM channel_init_sm_i
- (.CHANNEL_UP_Buffer_reg_0(CHANNEL_UP_Buffer_reg),
- .CHANNEL_UP_Buffer_reg_1(CHANNEL_UP_Buffer_reg_0),
- .D(D),
- .GTRXRESET_OUT(GTRXRESET_OUT),
- .RESET(RESET),
- .SS(SS),
- .START_RX(START_RX),
- .START_RX_Buffer_reg_0(\downcounter_r_reg[2] ),
- .gen_ver_i(gen_ver_i),
- .got_v_i(got_v_i),
- .reset_channel_i(reset_channel_i),
- .reset_lanes_i(reset_lanes_i),
- .\txver_count_r_reg[7]_0 (idle_and_ver_gen_i_n_12),
- .user_clk(user_clk),
- .wait_for_lane_up_r0(wait_for_lane_up_r0));
- east_channel_east_channel_IDLE_AND_VER_GEN idle_and_ver_gen_i
- (.DID_VER_Buffer_reg_0(idle_and_ver_gen_i_n_12),
- .GEN_A(GEN_A),
- .\downcounter_r_reg[2]_0 (\downcounter_r_reg[2] ),
- .gen_k_flop_0_i_0(gen_k_flop_0_i),
- .gen_r_flop_0_i_0(gen_r_flop_0_i),
- .gen_v_flop_1_i_0(gen_v_flop_1_i),
- .gen_ver_i(gen_ver_i),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_GT_WRAPPER" *)
-module east_channel_east_channel_GT_WRAPPER
- (TX_RESETDONE_OUT,
- drpclk_in_0,
- TXN,
- TXP,
- rx_realign_i,
- TX_OUT_CLK,
- DRPDO_OUT,
- RXDATA,
- drpclk_in_1,
- RXCHARISK,
- RXDISPERR,
- RXNOTINTABLE,
- RX_RESETDONE_OUT,
- gt_common_reset_out,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- rst_r_reg,
- drpclk_in_2,
- drpclk_in_3,
- drpclk_in_4,
- drpclk_in_5,
- \left_align_select_r_reg[1]_0 ,
- \left_align_select_r_reg[1]_1 ,
- \left_align_select_r_reg[1]_2 ,
- \left_align_select_r_reg[1]_3 ,
- hard_err_gt0,
- tx_lock,
- rxfsm_rxresetdone_r3_reg_0,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ,
- quad1_common_lock_in,
- drpclk_in,
- RXN,
- RXP,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- ena_comma_align_i,
- rx_polarity_i,
- sync_clk,
- user_clk,
- POWER_DOWN,
- LOOPBACK,
- TXDATA,
- drprdy_out,
- GTRXRESET_OUT,
- init_clk_in,
- link_reset_r,
- AR,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[0]_1 ,
- \left_align_select_r_reg[1]_4 ,
- tx_reset_i,
- \word_aligned_data_r_reg[16] ,
- \word_aligned_control_bits_r_reg[2] ,
- PLL_NOT_LOCKED,
- DRPADDR_IN,
- DRPDI_IN,
- DRPWE_IN,
- DRPEN_IN);
- output TX_RESETDONE_OUT;
- output drpclk_in_0;
- output TXN;
- output TXP;
- output rx_realign_i;
- output TX_OUT_CLK;
- output [15:0]DRPDO_OUT;
- output [31:0]RXDATA;
- output [3:0]drpclk_in_1;
- output [3:0]RXCHARISK;
- output [1:0]RXDISPERR;
- output [1:0]RXNOTINTABLE;
- output RX_RESETDONE_OUT;
- output gt_common_reset_out;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output rst_r_reg;
- output drpclk_in_2;
- output drpclk_in_3;
- output drpclk_in_4;
- output drpclk_in_5;
- output [7:0]\left_align_select_r_reg[1]_0 ;
- output [7:0]\left_align_select_r_reg[1]_1 ;
- output \left_align_select_r_reg[1]_2 ;
- output \left_align_select_r_reg[1]_3 ;
- output hard_err_gt0;
- output tx_lock;
- output rxfsm_rxresetdone_r3_reg_0;
- output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- input quad1_common_lock_in;
- input drpclk_in;
- input RXN;
- input RXP;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- input ena_comma_align_i;
- input rx_polarity_i;
- input sync_clk;
- input user_clk;
- input POWER_DOWN;
- input [2:0]LOOPBACK;
- input [31:0]TXDATA;
- input [3:0]drprdy_out;
- input GTRXRESET_OUT;
- input init_clk_in;
- input link_reset_r;
- input [0:0]AR;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[0]_1 ;
- input \left_align_select_r_reg[1]_4 ;
- input tx_reset_i;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input [0:0]\word_aligned_control_bits_r_reg[2] ;
- input PLL_NOT_LOCKED;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- input DRPWE_IN;
- input DRPEN_IN;
-
- wire [0:0]AR;
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN_IN;
- wire DRPWE_IN;
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire GTRXRESET_OUT;
- wire [2:0]LOOPBACK;
- wire PLL_NOT_LOCKED;
- wire POWER_DOWN;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire RXN;
- wire [1:0]RXNOTINTABLE;
- wire RXP;
- wire RX_RESETDONE_OUT;
- wire [31:0]TXDATA;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire TX_RESETDONE_OUT;
- wire drpclk_in;
- wire drpclk_in_0;
- wire [3:0]drpclk_in_1;
- wire drpclk_in_2;
- wire drpclk_in_3;
- wire drpclk_in_4;
- wire drpclk_in_5;
- wire [3:0]drprdy_out;
- wire east_channel_multi_gt_i_n_4;
- wire east_channel_multi_gt_i_n_6;
- wire ena_comma_align_i;
- wire gt0_rxresetdone_r3_reg_srl3_n_0;
- wire gt0_txresetdone_r3_reg_srl3_n_0;
- wire gt_common_reset_out;
- wire gt_rx_reset_i;
- wire gt_rxuserrdy_i;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire gtrxreset_i;
- wire gtrxreset_pulse;
- wire gtrxreset_pulse0;
- wire gtrxreset_r1;
- wire gtrxreset_r2;
- wire gtrxreset_r3;
- wire gtrxreset_sync;
- wire hard_err_gt0;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1] ;
- wire [7:0]\left_align_select_r_reg[1]_0 ;
- wire [7:0]\left_align_select_r_reg[1]_1 ;
- wire \left_align_select_r_reg[1]_2 ;
- wire \left_align_select_r_reg[1]_3 ;
- wire \left_align_select_r_reg[1]_4 ;
- wire link_reset_r;
- wire link_reset_r2;
- wire [10:0]p_0_in__2;
- wire quad1_common_lock_in;
- wire rst_r_reg;
- wire rx_cdrlock_counter;
- wire \rx_cdrlock_counter[10]_i_4_n_0 ;
- wire \rx_cdrlock_counter[10]_i_5_n_0 ;
- wire \rx_cdrlock_counter[10]_i_6_n_0 ;
- wire [10:0]rx_cdrlock_counter_reg;
- wire rx_cdrlocked;
- wire rx_cdrlocked_i_1_n_0;
- wire rx_cdrlocked_reg_n_0;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire rxfsm_rxresetdone_r;
- wire rxfsm_rxresetdone_r2;
- wire rxfsm_rxresetdone_r3_reg_0;
- wire rxfsm_soft_reset_r;
- wire rxfsm_soft_reset_r_i_1_n_0;
- wire sync_clk;
- wire tx_lock;
- wire tx_reset_i;
- wire txfsm_txresetdone_r;
- wire user_clk;
- wire [0:0]\word_aligned_control_bits_r_reg[2] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
-
- east_channel_east_channel_multi_gt east_channel_multi_gt_i
- (.DRPADDR_IN(DRPADDR_IN),
- .DRPDI_IN(DRPDI_IN),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE_IN(DRPWE_IN),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .LOOPBACK(LOOPBACK),
- .POWER_DOWN(POWER_DOWN),
- .RXCHARISK(RXCHARISK),
- .RXDATA(RXDATA),
- .RXDISPERR(RXDISPERR),
- .RXN(RXN),
- .RXNOTINTABLE(RXNOTINTABLE),
- .RXP(RXP),
- .SR(gt_rx_reset_i),
- .TXDATA(TXDATA),
- .TXN(TXN),
- .TXP(TXP),
- .TX_OUT_CLK(TX_OUT_CLK),
- .drpclk_in(drpclk_in),
- .drpclk_in_0(drpclk_in_0),
- .drpclk_in_1(east_channel_multi_gt_i_n_4),
- .drpclk_in_2(east_channel_multi_gt_i_n_6),
- .drpclk_in_3(drpclk_in_1),
- .drpclk_in_4(drpclk_in_2),
- .drpclk_in_5(drpclk_in_3),
- .drpclk_in_6(drpclk_in_4),
- .drpclk_in_7(drpclk_in_5),
- .drprdy_out(drprdy_out),
- .ena_comma_align_i(ena_comma_align_i),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_rxuserrdy_i(gt_rxuserrdy_i),
- .gt_tx_reset_i(gt_tx_reset_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .hard_err_gt0(hard_err_gt0),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (\left_align_select_r_reg[0] ),
- .\left_align_select_r_reg[0]_0 (\left_align_select_r_reg[0]_0 ),
- .\left_align_select_r_reg[0]_1 (\left_align_select_r_reg[0]_1 ),
- .\left_align_select_r_reg[1] (\left_align_select_r_reg[1] ),
- .\left_align_select_r_reg[1]_0 (\left_align_select_r_reg[1]_0 ),
- .\left_align_select_r_reg[1]_1 (\left_align_select_r_reg[1]_1 ),
- .\left_align_select_r_reg[1]_2 (\left_align_select_r_reg[1]_2 ),
- .\left_align_select_r_reg[1]_3 (\left_align_select_r_reg[1]_3 ),
- .\left_align_select_r_reg[1]_4 (\left_align_select_r_reg[1]_4 ),
- .rst_r_reg(rst_r_reg),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .sync_clk(sync_clk),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (\word_aligned_control_bits_r_reg[2] ),
- .\word_aligned_data_r_reg[16] (\word_aligned_data_r_reg[16] ));
- (* srl_name = "U0/\gt_wrapper_i/gt0_rxresetdone_r3_reg_srl3 " *)
- SRL16E gt0_rxresetdone_r3_reg_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(east_channel_multi_gt_i_n_4),
- .Q(gt0_rxresetdone_r3_reg_srl3_n_0));
- (* srl_name = "U0/\gt_wrapper_i/gt0_txresetdone_r3_reg_srl3 " *)
- SRL16E gt0_txresetdone_r3_reg_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(east_channel_multi_gt_i_n_6),
- .Q(gt0_txresetdone_r3_reg_srl3_n_0));
- (* equivalent_register_removal = "no" *)
- FDRE gt_rx_reset_i_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_i),
- .Q(gt_rx_reset_i),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gt_rxresetdone_r_i_1
- (.I0(RX_RESETDONE_OUT),
- .O(rxfsm_rxresetdone_r3_reg_0));
- east_channel_east_channel_rx_startup_fsm gt_rxresetfsm_i
- (.AR(rxfsm_soft_reset_r),
- .\FSM_sequential_rx_state_reg[0]_0 (rx_cdrlocked_reg_n_0),
- .gt_rxuserrdy_i(gt_rxuserrdy_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .gtrxreset_i(gtrxreset_i),
- .init_clk_in(init_clk_in),
- .quad1_common_lock_in(quad1_common_lock_in),
- .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
- .user_clk(user_clk));
- east_channel_east_channel_tx_startup_fsm gt_txresetfsm_i
- (.AR(AR),
- .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ),
- .PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_tx_reset_i(gt_tx_reset_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .init_clk_in(init_clk_in),
- .out(TX_RESETDONE_OUT),
- .quad1_common_lock_in(quad1_common_lock_in),
- .tx_lock(tx_lock),
- .txfsm_txresetdone_r(txfsm_txresetdone_r),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized6 gtrxreset_cdc_sync
- (.GTRXRESET_OUT(GTRXRESET_OUT),
- .init_clk_in(init_clk_in),
- .out(gtrxreset_sync),
- .user_clk(user_clk));
- LUT2 #(
- .INIT(4'h2))
- gtrxreset_pulse_i_1
- (.I0(gtrxreset_r2),
- .I1(gtrxreset_r3),
- .O(gtrxreset_pulse0));
- FDRE gtrxreset_pulse_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_pulse0),
- .Q(gtrxreset_pulse),
- .R(1'b0));
- FDRE gtrxreset_r1_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_sync),
- .Q(gtrxreset_r1),
- .R(1'b0));
- FDRE gtrxreset_r2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_r1),
- .Q(gtrxreset_r2),
- .R(1'b0));
- FDRE gtrxreset_r3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_r2),
- .Q(gtrxreset_r3),
- .R(1'b0));
- (* equivalent_register_removal = "no" *)
- FDRE link_reset_r2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_r),
- .Q(link_reset_r2),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- \rx_cdrlock_counter[0]_i_1
- (.I0(rx_cdrlock_counter_reg[0]),
- .O(p_0_in__2[0]));
- LUT1 #(
- .INIT(2'h1))
- \rx_cdrlock_counter[10]_i_1
- (.I0(rx_cdrlocked),
- .O(rx_cdrlock_counter));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \rx_cdrlock_counter[10]_i_2
- (.I0(rx_cdrlock_counter_reg[10]),
- .I1(rx_cdrlock_counter_reg[6]),
- .I2(rx_cdrlock_counter_reg[7]),
- .I3(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .I4(rx_cdrlock_counter_reg[8]),
- .I5(rx_cdrlock_counter_reg[9]),
- .O(p_0_in__2[10]));
- LUT5 #(
- .INIT(32'h00000004))
- \rx_cdrlock_counter[10]_i_3
- (.I0(rx_cdrlock_counter_reg[2]),
- .I1(rx_cdrlock_counter_reg[10]),
- .I2(rx_cdrlock_counter_reg[8]),
- .I3(\rx_cdrlock_counter[10]_i_5_n_0 ),
- .I4(\rx_cdrlock_counter[10]_i_6_n_0 ),
- .O(rx_cdrlocked));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_cdrlock_counter[10]_i_4
- (.I0(rx_cdrlock_counter_reg[5]),
- .I1(rx_cdrlock_counter_reg[2]),
- .I2(rx_cdrlock_counter_reg[0]),
- .I3(rx_cdrlock_counter_reg[1]),
- .I4(rx_cdrlock_counter_reg[3]),
- .I5(rx_cdrlock_counter_reg[4]),
- .O(\rx_cdrlock_counter[10]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair277" *)
- LUT4 #(
- .INIT(16'hFF7F))
- \rx_cdrlock_counter[10]_i_5
- (.I0(rx_cdrlock_counter_reg[7]),
- .I1(rx_cdrlock_counter_reg[6]),
- .I2(rx_cdrlock_counter_reg[1]),
- .I3(rx_cdrlock_counter_reg[0]),
- .O(\rx_cdrlock_counter[10]_i_5_n_0 ));
- LUT4 #(
- .INIT(16'hFFFD))
- \rx_cdrlock_counter[10]_i_6
- (.I0(rx_cdrlock_counter_reg[5]),
- .I1(rx_cdrlock_counter_reg[4]),
- .I2(rx_cdrlock_counter_reg[9]),
- .I3(rx_cdrlock_counter_reg[3]),
- .O(\rx_cdrlock_counter[10]_i_6_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair278" *)
- LUT2 #(
- .INIT(4'h6))
- \rx_cdrlock_counter[1]_i_1
- (.I0(rx_cdrlock_counter_reg[0]),
- .I1(rx_cdrlock_counter_reg[1]),
- .O(p_0_in__2[1]));
- (* SOFT_HLUTNM = "soft_lutpair278" *)
- LUT3 #(
- .INIT(8'h6A))
- \rx_cdrlock_counter[2]_i_1
- (.I0(rx_cdrlock_counter_reg[2]),
- .I1(rx_cdrlock_counter_reg[0]),
- .I2(rx_cdrlock_counter_reg[1]),
- .O(p_0_in__2[2]));
- (* SOFT_HLUTNM = "soft_lutpair275" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \rx_cdrlock_counter[3]_i_1
- (.I0(rx_cdrlock_counter_reg[3]),
- .I1(rx_cdrlock_counter_reg[1]),
- .I2(rx_cdrlock_counter_reg[0]),
- .I3(rx_cdrlock_counter_reg[2]),
- .O(p_0_in__2[3]));
- (* SOFT_HLUTNM = "soft_lutpair275" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \rx_cdrlock_counter[4]_i_1
- (.I0(rx_cdrlock_counter_reg[2]),
- .I1(rx_cdrlock_counter_reg[0]),
- .I2(rx_cdrlock_counter_reg[1]),
- .I3(rx_cdrlock_counter_reg[3]),
- .I4(rx_cdrlock_counter_reg[4]),
- .O(p_0_in__2[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \rx_cdrlock_counter[5]_i_1
- (.I0(rx_cdrlock_counter_reg[5]),
- .I1(rx_cdrlock_counter_reg[2]),
- .I2(rx_cdrlock_counter_reg[0]),
- .I3(rx_cdrlock_counter_reg[1]),
- .I4(rx_cdrlock_counter_reg[3]),
- .I5(rx_cdrlock_counter_reg[4]),
- .O(p_0_in__2[5]));
- LUT2 #(
- .INIT(4'h6))
- \rx_cdrlock_counter[6]_i_1
- (.I0(rx_cdrlock_counter_reg[6]),
- .I1(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .O(p_0_in__2[6]));
- (* SOFT_HLUTNM = "soft_lutpair277" *)
- LUT3 #(
- .INIT(8'h6A))
- \rx_cdrlock_counter[7]_i_1
- (.I0(rx_cdrlock_counter_reg[7]),
- .I1(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .I2(rx_cdrlock_counter_reg[6]),
- .O(p_0_in__2[7]));
- (* SOFT_HLUTNM = "soft_lutpair276" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \rx_cdrlock_counter[8]_i_1
- (.I0(rx_cdrlock_counter_reg[8]),
- .I1(rx_cdrlock_counter_reg[6]),
- .I2(rx_cdrlock_counter_reg[7]),
- .I3(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .O(p_0_in__2[8]));
- (* SOFT_HLUTNM = "soft_lutpair276" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \rx_cdrlock_counter[9]_i_1
- (.I0(rx_cdrlock_counter_reg[9]),
- .I1(rx_cdrlock_counter_reg[8]),
- .I2(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .I3(rx_cdrlock_counter_reg[7]),
- .I4(rx_cdrlock_counter_reg[6]),
- .O(p_0_in__2[9]));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[0]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[0]),
- .Q(rx_cdrlock_counter_reg[0]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[10]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[10]),
- .Q(rx_cdrlock_counter_reg[10]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[1]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[1]),
- .Q(rx_cdrlock_counter_reg[1]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[2]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[2]),
- .Q(rx_cdrlock_counter_reg[2]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[3]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[3]),
- .Q(rx_cdrlock_counter_reg[3]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[4]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[4]),
- .Q(rx_cdrlock_counter_reg[4]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[5]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[5]),
- .Q(rx_cdrlock_counter_reg[5]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[6]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[6]),
- .Q(rx_cdrlock_counter_reg[6]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[7]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[7]),
- .Q(rx_cdrlock_counter_reg[7]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[8]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[8]),
- .Q(rx_cdrlock_counter_reg[8]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[9]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[9]),
- .Q(rx_cdrlock_counter_reg[9]),
- .R(gt_rx_reset_i));
- LUT3 #(
- .INIT(8'h0E))
- rx_cdrlocked_i_1
- (.I0(rx_cdrlocked_reg_n_0),
- .I1(rx_cdrlocked),
- .I2(gt_rx_reset_i),
- .O(rx_cdrlocked_i_1_n_0));
- FDRE rx_cdrlocked_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rx_cdrlocked_i_1_n_0),
- .Q(rx_cdrlocked_reg_n_0),
- .R(1'b0));
- (* equivalent_register_removal = "no" *)
- FDRE rxfsm_rxresetdone_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxfsm_rxresetdone_r),
- .Q(rxfsm_rxresetdone_r2),
- .R(1'b0));
- FDRE rxfsm_rxresetdone_r3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxfsm_rxresetdone_r2),
- .Q(RX_RESETDONE_OUT),
- .R(1'b0));
- FDRE rxfsm_rxresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt0_rxresetdone_r3_reg_srl3_n_0),
- .Q(rxfsm_rxresetdone_r),
- .R(1'b0));
- LUT3 #(
- .INIT(8'hFE))
- rxfsm_soft_reset_r_i_1
- (.I0(link_reset_r2),
- .I1(gtrxreset_pulse),
- .I2(AR),
- .O(rxfsm_soft_reset_r_i_1_n_0));
- FDRE rxfsm_soft_reset_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rxfsm_soft_reset_r_i_1_n_0),
- .Q(rxfsm_soft_reset_r),
- .R(1'b0));
- FDRE txfsm_txresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt0_txresetdone_r3_reg_srl3_n_0),
- .Q(txfsm_txresetdone_r),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_HOTPLUG" *)
-module east_channel_east_channel_HOTPLUG
- (LINK_RESET_OUT,
- user_clk,
- init_clk_in,
- HPCNT_RESET,
- reset_lanes_i,
- D);
- output LINK_RESET_OUT;
- input user_clk;
- input init_clk_in;
- input HPCNT_RESET;
- input reset_lanes_i;
- input [0:0]D;
-
- wire [0:0]D;
- wire HPCNT_RESET;
- wire LINK_RESET_OUT;
- wire [21:0]\hotplug_count_synth.count_for_reset_r_reg ;
- wire init_clk_in;
- wire link_reset_0;
- wire link_reset_r;
- wire link_reset_r_i_2_n_0;
- wire link_reset_r_i_3_n_0;
- wire link_reset_r_i_4_n_0;
- wire link_reset_r_i_5_n_0;
- wire link_reset_r_i_6_n_0;
- wire p_0_in;
- wire reset_lanes_i;
- wire rx_cc_cdc_sync_n_0;
- wire rx_cc_cdc_sync_n_1;
- wire rx_cc_cdc_sync_n_10;
- wire rx_cc_cdc_sync_n_11;
- wire rx_cc_cdc_sync_n_12;
- wire rx_cc_cdc_sync_n_13;
- wire rx_cc_cdc_sync_n_14;
- wire rx_cc_cdc_sync_n_15;
- wire rx_cc_cdc_sync_n_16;
- wire rx_cc_cdc_sync_n_17;
- wire rx_cc_cdc_sync_n_18;
- wire rx_cc_cdc_sync_n_19;
- wire rx_cc_cdc_sync_n_2;
- wire rx_cc_cdc_sync_n_20;
- wire rx_cc_cdc_sync_n_21;
- wire rx_cc_cdc_sync_n_3;
- wire rx_cc_cdc_sync_n_4;
- wire rx_cc_cdc_sync_n_5;
- wire rx_cc_cdc_sync_n_6;
- wire rx_cc_cdc_sync_n_7;
- wire rx_cc_cdc_sync_n_8;
- wire rx_cc_cdc_sync_n_9;
- wire [7:0]rx_cc_extend_r;
- wire rx_cc_extend_r2;
- wire rx_cc_extend_r2_i_2_n_0;
- wire user_clk;
-
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[0]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_3),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [0]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[10]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_9),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [10]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[11]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_8),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [11]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[12]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_15),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [12]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[13]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_14),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [13]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[14]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_13),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [14]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[15]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_12),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [15]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[16]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_19),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [16]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[17]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_18),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [17]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[18]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_17),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [18]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[19]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_16),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [19]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[1]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_2),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [1]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[20]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_21),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [20]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[21]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_20),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [21]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[2]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_1),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [2]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[3]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_0),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [3]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[4]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_7),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [4]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[5]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_6),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [5]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[6]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_5),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [6]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[7]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_4),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [7]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[8]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_11),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [8]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[9]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_10),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [9]));
- FDRE #(
- .INIT(1'b0))
- \hotplug_enable.LINK_RESET_OUT_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_r),
- .Q(LINK_RESET_OUT),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0222222222222222))
- link_reset_r_i_1
- (.I0(link_reset_r_i_2_n_0),
- .I1(link_reset_r_i_3_n_0),
- .I2(link_reset_r_i_4_n_0),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [4]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [1]),
- .I5(\hotplug_count_synth.count_for_reset_r_reg [0]),
- .O(link_reset_0));
- LUT6 #(
- .INIT(64'h0000000040000000))
- link_reset_r_i_2
- (.I0(link_reset_r_i_5_n_0),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [12]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [19]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [9]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [16]),
- .I5(link_reset_r_i_6_n_0),
- .O(link_reset_r_i_2_n_0));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- link_reset_r_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [15]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [13]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [10]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [11]),
- .I5(\hotplug_count_synth.count_for_reset_r_reg [7]),
- .O(link_reset_r_i_3_n_0));
- LUT2 #(
- .INIT(4'h8))
- link_reset_r_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [2]),
- .O(link_reset_r_i_4_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- link_reset_r_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [14]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [18]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [21]),
- .O(link_reset_r_i_5_n_0));
- LUT6 #(
- .INIT(64'h07FFFFFFFFFFFFFF))
- link_reset_r_i_6
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [2]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [4]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [20]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [5]),
- .I5(\hotplug_count_synth.count_for_reset_r_reg [17]),
- .O(link_reset_r_i_6_n_0));
- FDRE link_reset_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_0),
- .Q(link_reset_r),
- .R(1'b0));
- east_channel_east_channel_cdc_sync__parameterized6_24 rx_cc_cdc_sync
- (.O({rx_cc_cdc_sync_n_0,rx_cc_cdc_sync_n_1,rx_cc_cdc_sync_n_2,rx_cc_cdc_sync_n_3}),
- .\hotplug_count_synth.count_for_reset_r_reg (\hotplug_count_synth.count_for_reset_r_reg ),
- .\hotplug_count_synth.count_for_reset_r_reg[11] ({rx_cc_cdc_sync_n_8,rx_cc_cdc_sync_n_9,rx_cc_cdc_sync_n_10,rx_cc_cdc_sync_n_11}),
- .\hotplug_count_synth.count_for_reset_r_reg[15] ({rx_cc_cdc_sync_n_12,rx_cc_cdc_sync_n_13,rx_cc_cdc_sync_n_14,rx_cc_cdc_sync_n_15}),
- .\hotplug_count_synth.count_for_reset_r_reg[19] ({rx_cc_cdc_sync_n_16,rx_cc_cdc_sync_n_17,rx_cc_cdc_sync_n_18,rx_cc_cdc_sync_n_19}),
- .\hotplug_count_synth.count_for_reset_r_reg[21] ({rx_cc_cdc_sync_n_20,rx_cc_cdc_sync_n_21}),
- .\hotplug_count_synth.count_for_reset_r_reg[7] ({rx_cc_cdc_sync_n_4,rx_cc_cdc_sync_n_5,rx_cc_cdc_sync_n_6,rx_cc_cdc_sync_n_7}),
- .init_clk_in(init_clk_in),
- .rx_cc_extend_r2(rx_cc_extend_r2),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- rx_cc_extend_r2_i_1
- (.I0(rx_cc_extend_r[2]),
- .I1(rx_cc_extend_r[3]),
- .I2(rx_cc_extend_r[0]),
- .I3(rx_cc_extend_r[1]),
- .I4(rx_cc_extend_r2_i_2_n_0),
- .O(p_0_in));
- LUT4 #(
- .INIT(16'hFFFE))
- rx_cc_extend_r2_i_2
- (.I0(rx_cc_extend_r[5]),
- .I1(rx_cc_extend_r[4]),
- .I2(rx_cc_extend_r[7]),
- .I3(rx_cc_extend_r[6]),
- .O(rx_cc_extend_r2_i_2_n_0));
- FDRE rx_cc_extend_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in),
- .Q(rx_cc_extend_r2),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[1]),
- .Q(rx_cc_extend_r[0]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[2]),
- .Q(rx_cc_extend_r[1]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[3]),
- .Q(rx_cc_extend_r[2]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[4]),
- .Q(rx_cc_extend_r[3]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[5]),
- .Q(rx_cc_extend_r[4]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[6]),
- .Q(rx_cc_extend_r[5]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[7]),
- .Q(rx_cc_extend_r[6]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(rx_cc_extend_r[7]),
- .R(reset_lanes_i));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_IDLE_AND_VER_GEN" *)
-module east_channel_east_channel_IDLE_AND_VER_GEN
- (gen_v_flop_1_i_0,
- GEN_A,
- gen_k_flop_0_i_0,
- gen_r_flop_0_i_0,
- DID_VER_Buffer_reg_0,
- user_clk,
- gen_ver_i,
- \downcounter_r_reg[2]_0 );
- output [2:0]gen_v_flop_1_i_0;
- output GEN_A;
- output [3:0]gen_k_flop_0_i_0;
- output [3:0]gen_r_flop_0_i_0;
- output DID_VER_Buffer_reg_0;
- input user_clk;
- input gen_ver_i;
- input \downcounter_r_reg[2]_0 ;
-
- wire D;
- wire D0_in;
- wire D0_out;
- wire D1_in;
- wire D1_out;
- wire D2_out;
- wire DID_VER_Buffer_reg_0;
- wire GEN_A;
- wire did_ver_i;
- wire [0:2]down_count_r;
- wire \down_count_r[0]_i_1_n_0 ;
- wire \down_count_r[1]_i_1_n_0 ;
- wire \downcounter_r[0]_i_1_n_0 ;
- wire \downcounter_r[1]_i_1_n_0 ;
- wire \downcounter_r[2]_i_1_n_0 ;
- wire \downcounter_r_reg[2]_0 ;
- wire \downcounter_r_reg_n_0_[0] ;
- wire \downcounter_r_reg_n_0_[1] ;
- wire \downcounter_r_reg_n_0_[2] ;
- wire [3:0]gen_k_flop_0_i_0;
- wire gen_k_flop_1_i_i_1_n_0;
- wire gen_k_flop_2_i_i_1_n_0;
- wire gen_k_flop_3_i_i_1_n_0;
- wire [3:0]gen_r_flop_0_i_0;
- wire gen_r_flop_0_i_i_1_n_0;
- wire [2:0]gen_v_flop_1_i_0;
- wire gen_ver_i;
- wire \lfsr_reg_reg_n_0_[3] ;
- wire p_1_in;
- wire [0:0]p_4_out;
- wire prev_cycle_gen_ver_r;
- wire user_clk;
- wire ver_counter_c;
-
- FDRE DID_VER_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ver_counter_c),
- .Q(did_ver_i),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair134" *)
- LUT2 #(
- .INIT(4'hE))
- \down_count_r[0]_i_1
- (.I0(\lfsr_reg_reg_n_0_[3] ),
- .I1(D0_in),
- .O(\down_count_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair136" *)
- LUT2 #(
- .INIT(4'h9))
- \down_count_r[1]_i_1
- (.I0(\lfsr_reg_reg_n_0_[3] ),
- .I1(D0_in),
- .O(\down_count_r[1]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \down_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\down_count_r[0]_i_1_n_0 ),
- .Q(down_count_r[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \down_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\down_count_r[1]_i_1_n_0 ),
- .Q(down_count_r[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \down_count_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_3_i_i_1_n_0),
- .Q(down_count_r[2]),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hE1E0))
- \downcounter_r[0]_i_1
- (.I0(\downcounter_r_reg_n_0_[1] ),
- .I1(\downcounter_r_reg_n_0_[2] ),
- .I2(\downcounter_r_reg_n_0_[0] ),
- .I3(down_count_r[0]),
- .O(\downcounter_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair133" *)
- LUT4 #(
- .INIT(16'hF00E))
- \downcounter_r[1]_i_1
- (.I0(down_count_r[1]),
- .I1(\downcounter_r_reg_n_0_[0] ),
- .I2(\downcounter_r_reg_n_0_[1] ),
- .I3(\downcounter_r_reg_n_0_[2] ),
- .O(\downcounter_r[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair133" *)
- LUT4 #(
- .INIT(16'h0F0E))
- \downcounter_r[2]_i_1
- (.I0(down_count_r[2]),
- .I1(\downcounter_r_reg_n_0_[0] ),
- .I2(\downcounter_r_reg_n_0_[2] ),
- .I3(\downcounter_r_reg_n_0_[1] ),
- .O(\downcounter_r[2]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \downcounter_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\downcounter_r[0]_i_1_n_0 ),
- .Q(\downcounter_r_reg_n_0_[0] ),
- .R(\downcounter_r_reg[2]_0 ));
- FDRE #(
- .INIT(1'b0))
- \downcounter_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\downcounter_r[1]_i_1_n_0 ),
- .Q(\downcounter_r_reg_n_0_[1] ),
- .R(\downcounter_r_reg[2]_0 ));
- FDRE #(
- .INIT(1'b0))
- \downcounter_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\downcounter_r[2]_i_1_n_0 ),
- .Q(\downcounter_r_reg_n_0_[2] ),
- .R(\downcounter_r_reg[2]_0 ));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_a_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D1_out),
- .Q(GEN_A),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair132" *)
- LUT5 #(
- .INIT(32'h00000007))
- gen_a_flop_0_i_i_1
- (.I0(did_ver_i),
- .I1(gen_ver_i),
- .I2(\downcounter_r_reg_n_0_[0] ),
- .I3(\downcounter_r_reg_n_0_[2] ),
- .I4(\downcounter_r_reg_n_0_[1] ),
- .O(D1_out));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D2_out),
- .Q(gen_k_flop_0_i_0[3]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hFFFF555455545554))
- gen_k_flop_0_i_i_1
- (.I0(p_1_in),
- .I1(\downcounter_r_reg_n_0_[1] ),
- .I2(\downcounter_r_reg_n_0_[2] ),
- .I3(\downcounter_r_reg_n_0_[0] ),
- .I4(did_ver_i),
- .I5(gen_ver_i),
- .O(D2_out));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_1_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_1_i_i_1_n_0),
- .Q(gen_k_flop_0_i_0[2]),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gen_k_flop_1_i_i_1
- (.I0(D1_in),
- .O(gen_k_flop_1_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_2_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_2_i_i_1_n_0),
- .Q(gen_k_flop_0_i_0[1]),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gen_k_flop_2_i_i_1
- (.I0(D0_in),
- .O(gen_k_flop_2_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_3_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_3_i_i_1_n_0),
- .Q(gen_k_flop_0_i_0[0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair136" *)
- LUT1 #(
- .INIT(2'h1))
- gen_k_flop_3_i_i_1
- (.I0(\lfsr_reg_reg_n_0_[3] ),
- .O(gen_k_flop_3_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_r_flop_0_i_i_1_n_0),
- .Q(gen_r_flop_0_i_0[3]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h2A2A2A2A2A2A2A00))
- gen_r_flop_0_i_i_1
- (.I0(p_1_in),
- .I1(gen_ver_i),
- .I2(did_ver_i),
- .I3(\downcounter_r_reg_n_0_[0] ),
- .I4(\downcounter_r_reg_n_0_[2] ),
- .I5(\downcounter_r_reg_n_0_[1] ),
- .O(gen_r_flop_0_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_1_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D1_in),
- .Q(gen_r_flop_0_i_0[2]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_2_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_in),
- .Q(gen_r_flop_0_i_0[1]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_3_i
- (.C(user_clk),
- .CE(1'b1),
- .D(\lfsr_reg_reg_n_0_[3] ),
- .Q(gen_r_flop_0_i_0[0]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_v_flop_1_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_out),
- .Q(gen_v_flop_1_i_0[2]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair135" *)
- LUT2 #(
- .INIT(4'h8))
- gen_v_flop_1_i_i_1
- (.I0(did_ver_i),
- .I1(gen_ver_i),
- .O(D0_out));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_v_flop_2_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_out),
- .Q(gen_v_flop_1_i_0[1]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_v_flop_3_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_out),
- .Q(gen_v_flop_1_i_0[0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair134" *)
- LUT4 #(
- .INIT(16'h0EF1))
- \lfsr_reg[3]_i_1
- (.I0(D0_in),
- .I1(D1_in),
- .I2(\lfsr_reg_reg_n_0_[3] ),
- .I3(p_1_in),
- .O(p_4_out));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D1_in),
- .Q(p_1_in),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_in),
- .Q(D1_in),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\lfsr_reg_reg_n_0_[3] ),
- .Q(D0_in),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_4_out),
- .Q(\lfsr_reg_reg_n_0_[3] ),
- .R(1'b0));
- FDRE prev_cycle_gen_ver_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_ver_i),
- .Q(prev_cycle_gen_ver_r),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair132" *)
- LUT2 #(
- .INIT(4'hB))
- \txver_count_r_reg[6]_srl7_i_1
- (.I0(did_ver_i),
- .I1(gen_ver_i),
- .O(DID_VER_Buffer_reg_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "SRL16" *)
- (* srl_name = "U0/\east_channel_global_logic_i/idle_and_ver_gen_i/ver_counter_i " *)
- SRL16E #(
- .INIT(16'h0000))
- ver_counter_i
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(D),
- .Q(ver_counter_c));
- (* SOFT_HLUTNM = "soft_lutpair135" *)
- LUT3 #(
- .INIT(8'hD0))
- ver_counter_i_i_1
- (.I0(prev_cycle_gen_ver_r),
- .I1(did_ver_i),
- .I2(gen_ver_i),
- .O(D));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_LANE_INIT_SM_4BYTE" *)
-module east_channel_east_channel_LANE_INIT_SM_4BYTE
- (LANE_UP,
- D,
- align_r_reg_0,
- gen_spa_i,
- rst_r_reg_0,
- enable_err_detect_i,
- rx_polarity_i,
- GEN_SP,
- good_cnt_r3,
- ready_r_reg_0,
- reset_lanes_i,
- user_clk,
- begin_r0,
- counter4_r0,
- gen_spa_r,
- \counter3_r_reg[3]_0 ,
- rx_realign_i,
- rx_neg_i,
- RXNOTINTABLE,
- RXDISPERR,
- reset_count_r_reg_0,
- first_v_received_r,
- \RX_CHAR_IS_COMMA_R_reg[3]_0 );
- output LANE_UP;
- output D;
- output align_r_reg_0;
- output gen_spa_i;
- output rst_r_reg_0;
- output enable_err_detect_i;
- output rx_polarity_i;
- output GEN_SP;
- output good_cnt_r3;
- output ready_r_reg_0;
- input reset_lanes_i;
- input user_clk;
- input begin_r0;
- input counter4_r0;
- input gen_spa_r;
- input \counter3_r_reg[3]_0 ;
- input rx_realign_i;
- input rx_neg_i;
- input [1:0]RXNOTINTABLE;
- input [1:0]RXDISPERR;
- input reset_count_r_reg_0;
- input first_v_received_r;
- input [3:0]\RX_CHAR_IS_COMMA_R_reg[3]_0 ;
-
- wire D;
- wire ENABLE_ERR_DETECT_Buffer0;
- wire GEN_SP;
- wire LANE_UP;
- wire [1:0]RXDISPERR;
- wire [1:0]RXNOTINTABLE;
- wire [3:0]\RX_CHAR_IS_COMMA_R_reg[3]_0 ;
- wire \RX_CHAR_IS_COMMA_R_reg_n_0_[0] ;
- wire \RX_CHAR_IS_COMMA_R_reg_n_0_[3] ;
- wire align_r_reg_0;
- wire begin_r;
- wire begin_r0;
- wire begin_r_i_2_n_0;
- wire consecutive_commas_r;
- wire consecutive_commas_r0;
- wire count_128d_done_r;
- wire count_32d_done_r;
- wire count_8d_done_r;
- wire counter1_r0;
- wire \counter1_r[0]_i_3_n_0 ;
- wire \counter1_r_reg_n_0_[1] ;
- wire \counter1_r_reg_n_0_[3] ;
- wire \counter1_r_reg_n_0_[5] ;
- wire \counter1_r_reg_n_0_[6] ;
- wire \counter1_r_reg_n_0_[7] ;
- wire \counter2_r_reg[14]_srl14_n_0 ;
- wire \counter2_r_reg_n_0_[15] ;
- wire \counter3_r_reg[2]_srl3_n_0 ;
- wire \counter3_r_reg[3]_0 ;
- wire \counter3_r_reg_n_0_[3] ;
- wire counter4_r0;
- wire \counter4_r_reg[14]_srl15_n_0 ;
- wire \counter4_r_reg_n_0_[15] ;
- wire \counter5_r_reg[14]_srl15_i_1_n_0 ;
- wire \counter5_r_reg[14]_srl15_n_0 ;
- wire \counter5_r_reg_n_0_[15] ;
- wire do_watchdog_count_r;
- wire do_watchdog_count_r0;
- wire enable_err_detect_i;
- wire first_v_received_r;
- wire gen_spa_i;
- wire gen_spa_r;
- wire good_cnt_r3;
- wire next_ack_c;
- wire next_align_c;
- wire next_begin_c;
- wire next_polarity_c;
- wire next_ready_c;
- wire next_realign_c;
- wire next_rst_c;
- wire [7:0]p_0_in;
- wire p_0_in2_in;
- wire p_1_in;
- wire polarity_r;
- wire prev_count_128d_done_r;
- wire ready_r_reg_0;
- wire realign_r;
- wire reset_count_r;
- wire reset_count_r0;
- wire reset_count_r_i_2_n_0;
- wire reset_count_r_reg_0;
- wire reset_lanes_i;
- wire rst_r_reg_0;
- wire rx_neg_i;
- wire rx_polarity_i;
- wire rx_polarity_r_i_1_n_0;
- wire rx_realign_i;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'hE))
- ENABLE_ERR_DETECT_Buffer_i_1
- (.I0(gen_spa_i),
- .I1(D),
- .O(ENABLE_ERR_DETECT_Buffer0));
- FDRE ENABLE_ERR_DETECT_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ENABLE_ERR_DETECT_Buffer0),
- .Q(enable_err_detect_i),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [0]),
- .Q(\RX_CHAR_IS_COMMA_R_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [1]),
- .Q(p_1_in),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [2]),
- .Q(p_0_in2_in),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [3]),
- .Q(\RX_CHAR_IS_COMMA_R_reg_n_0_[3] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h444444444FFF4444))
- ack_r_i_1
- (.I0(rx_neg_i),
- .I1(polarity_r),
- .I2(\counter2_r_reg_n_0_[15] ),
- .I3(\counter3_r_reg_n_0_[3] ),
- .I4(gen_spa_i),
- .I5(\counter5_r_reg_n_0_[15] ),
- .O(next_ack_c));
- FDRE ack_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ack_c),
- .Q(gen_spa_i),
- .R(begin_r0));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT4 #(
- .INIT(16'h8F88))
- align_r_i_2
- (.I0(count_8d_done_r),
- .I1(rst_r_reg_0),
- .I2(count_128d_done_r),
- .I3(align_r_reg_0),
- .O(next_align_c));
- FDRE align_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_align_c),
- .Q(align_r_reg_0),
- .R(begin_r0));
- LUT3 #(
- .INIT(8'hF8))
- begin_r_i_1
- (.I0(polarity_r),
- .I1(rx_neg_i),
- .I2(begin_r_i_2_n_0),
- .O(next_begin_c));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- begin_r_i_2
- (.I0(\counter4_r_reg_n_0_[15] ),
- .I1(D),
- .I2(gen_spa_i),
- .I3(\counter5_r_reg_n_0_[15] ),
- .I4(rx_realign_i),
- .I5(realign_r),
- .O(begin_r_i_2_n_0));
- FDSE begin_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_begin_c),
- .Q(begin_r),
- .S(begin_r0));
- LUT5 #(
- .INIT(32'hFFFFFFEF))
- consecutive_commas_r_i_1
- (.I0(\RX_CHAR_IS_COMMA_R_reg_n_0_[0] ),
- .I1(\RX_CHAR_IS_COMMA_R_reg_n_0_[3] ),
- .I2(align_r_reg_0),
- .I3(p_0_in2_in),
- .I4(p_1_in),
- .O(consecutive_commas_r0));
- FDRE consecutive_commas_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(consecutive_commas_r0),
- .Q(consecutive_commas_r),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- \counter1_r[0]_i_1
- (.I0(reset_count_r),
- .I1(D),
- .O(counter1_r0));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT3 #(
- .INIT(8'hD2))
- \counter1_r[0]_i_2
- (.I0(\counter1_r_reg_n_0_[1] ),
- .I1(\counter1_r[0]_i_3_n_0 ),
- .I2(count_128d_done_r),
- .O(p_0_in[7]));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- \counter1_r[0]_i_3
- (.I0(\counter1_r_reg_n_0_[3] ),
- .I1(\counter1_r_reg_n_0_[5] ),
- .I2(\counter1_r_reg_n_0_[7] ),
- .I3(\counter1_r_reg_n_0_[6] ),
- .I4(count_8d_done_r),
- .I5(count_32d_done_r),
- .O(\counter1_r[0]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT2 #(
- .INIT(4'h9))
- \counter1_r[1]_i_1
- (.I0(\counter1_r[0]_i_3_n_0 ),
- .I1(\counter1_r_reg_n_0_[1] ),
- .O(p_0_in[6]));
- LUT6 #(
- .INIT(64'h7FFFFFFF80000000))
- \counter1_r[2]_i_1
- (.I0(\counter1_r_reg_n_0_[3] ),
- .I1(\counter1_r_reg_n_0_[5] ),
- .I2(\counter1_r_reg_n_0_[7] ),
- .I3(\counter1_r_reg_n_0_[6] ),
- .I4(count_8d_done_r),
- .I5(count_32d_done_r),
- .O(p_0_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \counter1_r[3]_i_1
- (.I0(count_8d_done_r),
- .I1(\counter1_r_reg_n_0_[6] ),
- .I2(\counter1_r_reg_n_0_[7] ),
- .I3(\counter1_r_reg_n_0_[5] ),
- .I4(\counter1_r_reg_n_0_[3] ),
- .O(p_0_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT4 #(
- .INIT(16'h7F80))
- \counter1_r[4]_i_1
- (.I0(\counter1_r_reg_n_0_[5] ),
- .I1(\counter1_r_reg_n_0_[7] ),
- .I2(\counter1_r_reg_n_0_[6] ),
- .I3(count_8d_done_r),
- .O(p_0_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT3 #(
- .INIT(8'h78))
- \counter1_r[5]_i_1
- (.I0(\counter1_r_reg_n_0_[6] ),
- .I1(\counter1_r_reg_n_0_[7] ),
- .I2(\counter1_r_reg_n_0_[5] ),
- .O(p_0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT2 #(
- .INIT(4'h6))
- \counter1_r[6]_i_1
- (.I0(\counter1_r_reg_n_0_[7] ),
- .I1(\counter1_r_reg_n_0_[6] ),
- .O(p_0_in[1]));
- LUT1 #(
- .INIT(2'h1))
- \counter1_r[7]_i_1
- (.I0(\counter1_r_reg_n_0_[7] ),
- .O(p_0_in[0]));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[0]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[7]),
- .Q(count_128d_done_r),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[1]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[6]),
- .Q(\counter1_r_reg_n_0_[1] ),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[2]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[5]),
- .Q(count_32d_done_r),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[3]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[4]),
- .Q(\counter1_r_reg_n_0_[3] ),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[4]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[3]),
- .Q(count_8d_done_r),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[5]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[2]),
- .Q(\counter1_r_reg_n_0_[5] ),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[6]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[1]),
- .Q(\counter1_r_reg_n_0_[6] ),
- .R(counter1_r0));
- FDSE #(
- .INIT(1'b1))
- \counter1_r_reg[7]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[0]),
- .Q(\counter1_r_reg_n_0_[7] ),
- .S(counter1_r0));
- (* srl_bus_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter2_r_reg " *)
- (* srl_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter2_r_reg[14]_srl14 " *)
- SRL16E \counter2_r_reg[14]_srl14
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b1),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(gen_spa_r),
- .Q(\counter2_r_reg[14]_srl14_n_0 ));
- FDRE \counter2_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\counter2_r_reg[14]_srl14_n_0 ),
- .Q(\counter2_r_reg_n_0_[15] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter3_r_reg " *)
- (* srl_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter3_r_reg[2]_srl3 " *)
- SRL16E \counter3_r_reg[2]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(\counter3_r_reg[3]_0 ),
- .CLK(user_clk),
- .D(gen_spa_i),
- .Q(\counter3_r_reg[2]_srl3_n_0 ));
- FDRE \counter3_r_reg[3]
- (.C(user_clk),
- .CE(\counter3_r_reg[3]_0 ),
- .D(\counter3_r_reg[2]_srl3_n_0 ),
- .Q(\counter3_r_reg_n_0_[3] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter4_r_reg " *)
- (* srl_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter4_r_reg[14]_srl15 " *)
- SRL16E \counter4_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(counter4_r0),
- .CLK(user_clk),
- .D(D),
- .Q(\counter4_r_reg[14]_srl15_n_0 ));
- FDRE \counter4_r_reg[15]
- (.C(user_clk),
- .CE(counter4_r0),
- .D(\counter4_r_reg[14]_srl15_n_0 ),
- .Q(\counter4_r_reg_n_0_[15] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter5_r_reg " *)
- (* srl_name = "U0/\east_channel_aurora_lane_4byte_0_i/east_channel_lane_init_sm_4byte_i/counter5_r_reg[14]_srl15 " *)
- SRL16E \counter5_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(\counter5_r_reg[14]_srl15_i_1_n_0 ),
- .CLK(user_clk),
- .D(gen_spa_i),
- .Q(\counter5_r_reg[14]_srl15_n_0 ));
- LUT2 #(
- .INIT(4'hB))
- \counter5_r_reg[14]_srl15_i_1
- (.I0(do_watchdog_count_r),
- .I1(gen_spa_i),
- .O(\counter5_r_reg[14]_srl15_i_1_n_0 ));
- FDRE \counter5_r_reg[15]
- (.C(user_clk),
- .CE(\counter5_r_reg[14]_srl15_i_1_n_0 ),
- .D(\counter5_r_reg[14]_srl15_n_0 ),
- .Q(\counter5_r_reg_n_0_[15] ),
- .R(1'b0));
- LUT2 #(
- .INIT(4'h2))
- do_watchdog_count_r_i_1
- (.I0(count_128d_done_r),
- .I1(prev_count_128d_done_r),
- .O(do_watchdog_count_r0));
- FDRE do_watchdog_count_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(do_watchdog_count_r0),
- .Q(do_watchdog_count_r),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT2 #(
- .INIT(4'h1))
- gen_sp_r_i_1
- (.I0(D),
- .I1(gen_spa_i),
- .O(GEN_SP));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FDR" *)
- FDRE #(
- .INIT(1'b0))
- lane_up_flop_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(LANE_UP),
- .R(reset_lanes_i));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT3 #(
- .INIT(8'h0E))
- \left_align_select_r[0]_i_2
- (.I0(D),
- .I1(align_r_reg_0),
- .I2(first_v_received_r),
- .O(ready_r_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT3 #(
- .INIT(8'h40))
- polarity_r_i_1
- (.I0(rx_realign_i),
- .I1(count_32d_done_r),
- .I2(realign_r),
- .O(next_polarity_c));
- FDRE polarity_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_polarity_c),
- .Q(polarity_r),
- .R(begin_r0));
- FDRE prev_count_128d_done_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(count_128d_done_r),
- .Q(prev_count_128d_done_r),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0080FFFF00800080))
- ready_r_i_1
- (.I0(\counter2_r_reg_n_0_[15] ),
- .I1(\counter3_r_reg_n_0_[3] ),
- .I2(gen_spa_i),
- .I3(\counter5_r_reg_n_0_[15] ),
- .I4(\counter4_r_reg_n_0_[15] ),
- .I5(D),
- .O(next_ready_c));
- FDRE ready_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ready_c),
- .Q(D),
- .R(begin_r0));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT5 #(
- .INIT(32'hFF020202))
- realign_r_i_1
- (.I0(realign_r),
- .I1(rx_realign_i),
- .I2(count_32d_done_r),
- .I3(count_128d_done_r),
- .I4(align_r_reg_0),
- .O(next_realign_c));
- FDRE realign_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_realign_c),
- .Q(realign_r),
- .R(begin_r0));
- LUT6 #(
- .INIT(64'hFFAAFFAAFFFEFFFF))
- reset_count_r_i_1
- (.I0(reset_count_r_i_2_n_0),
- .I1(RXNOTINTABLE[1]),
- .I2(RXDISPERR[1]),
- .I3(reset_lanes_i),
- .I4(consecutive_commas_r),
- .I5(rst_r_reg_0),
- .O(reset_count_r0));
- LUT6 #(
- .INIT(64'hFFFFFFFF77763332))
- reset_count_r_i_2
- (.I0(begin_r),
- .I1(rst_r_reg_0),
- .I2(RXDISPERR[0]),
- .I3(RXNOTINTABLE[0]),
- .I4(count_8d_done_r),
- .I5(reset_count_r_reg_0),
- .O(reset_count_r_i_2_n_0));
- FDRE reset_count_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(reset_count_r0),
- .Q(reset_count_r),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT3 #(
- .INIT(8'hF4))
- rst_r_i_1
- (.I0(count_8d_done_r),
- .I1(rst_r_reg_0),
- .I2(begin_r),
- .O(next_rst_c));
- FDRE rst_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_rst_c),
- .Q(rst_r_reg_0),
- .R(begin_r0));
- LUT3 #(
- .INIT(8'h78))
- rx_polarity_r_i_1
- (.I0(polarity_r),
- .I1(rx_neg_i),
- .I2(rx_polarity_i),
- .O(rx_polarity_r_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- rx_polarity_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_polarity_r_i_1_n_0),
- .Q(rx_polarity_i),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- \soft_err_r[0]_i_1
- (.I0(enable_err_detect_i),
- .O(good_cnt_r3));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_LEFT_ALIGN_CONTROL" *)
-module east_channel_east_channel_LEFT_ALIGN_CONTROL
- (MUX_SELECT,
- mux_select_c,
- user_clk);
- output [0:0]MUX_SELECT;
- input [0:0]mux_select_c;
- input user_clk;
-
- wire [0:0]MUX_SELECT;
- wire [0:0]mux_select_c;
- wire user_clk;
-
- FDRE \MUX_SELECT_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(mux_select_c),
- .Q(MUX_SELECT),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_LEFT_ALIGN_MUX" *)
-module east_channel_east_channel_LEFT_ALIGN_MUX
- (\MUXED_DATA_Buffer_reg[0]_0 ,
- D,
- Q,
- MUX_SELECT,
- user_clk,
- STORAGE_SELECT_Buffer);
- output [15:0]\MUXED_DATA_Buffer_reg[0]_0 ;
- output [31:0]D;
- input [31:0]Q;
- input [0:0]MUX_SELECT;
- input user_clk;
- input [1:0]STORAGE_SELECT_Buffer;
-
- wire [31:0]D;
- wire [16:31]MUXED_DATA_Buffer;
- wire [15:0]\MUXED_DATA_Buffer_reg[0]_0 ;
- wire [0:0]MUX_SELECT;
- wire [31:0]Q;
- wire [1:0]STORAGE_SELECT_Buffer;
- wire [0:15]muxed_data_c;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair157" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[0]_i_1
- (.I0(Q[15]),
- .I1(MUX_SELECT),
- .I2(Q[31]),
- .O(muxed_data_c[0]));
- (* SOFT_HLUTNM = "soft_lutpair152" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[10]_i_1
- (.I0(Q[5]),
- .I1(MUX_SELECT),
- .I2(Q[21]),
- .O(muxed_data_c[10]));
- (* SOFT_HLUTNM = "soft_lutpair152" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[11]_i_1
- (.I0(Q[4]),
- .I1(MUX_SELECT),
- .I2(Q[20]),
- .O(muxed_data_c[11]));
- (* SOFT_HLUTNM = "soft_lutpair151" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[12]_i_1
- (.I0(Q[3]),
- .I1(MUX_SELECT),
- .I2(Q[19]),
- .O(muxed_data_c[12]));
- (* SOFT_HLUTNM = "soft_lutpair151" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[13]_i_1
- (.I0(Q[2]),
- .I1(MUX_SELECT),
- .I2(Q[18]),
- .O(muxed_data_c[13]));
- (* SOFT_HLUTNM = "soft_lutpair150" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[14]_i_1
- (.I0(Q[1]),
- .I1(MUX_SELECT),
- .I2(Q[17]),
- .O(muxed_data_c[14]));
- (* SOFT_HLUTNM = "soft_lutpair150" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[15]_i_1
- (.I0(Q[0]),
- .I1(MUX_SELECT),
- .I2(Q[16]),
- .O(muxed_data_c[15]));
- (* SOFT_HLUTNM = "soft_lutpair157" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[1]_i_1
- (.I0(Q[14]),
- .I1(MUX_SELECT),
- .I2(Q[30]),
- .O(muxed_data_c[1]));
- (* SOFT_HLUTNM = "soft_lutpair156" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[2]_i_1
- (.I0(Q[13]),
- .I1(MUX_SELECT),
- .I2(Q[29]),
- .O(muxed_data_c[2]));
- (* SOFT_HLUTNM = "soft_lutpair156" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[3]_i_1
- (.I0(Q[12]),
- .I1(MUX_SELECT),
- .I2(Q[28]),
- .O(muxed_data_c[3]));
- (* SOFT_HLUTNM = "soft_lutpair155" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[4]_i_1
- (.I0(Q[11]),
- .I1(MUX_SELECT),
- .I2(Q[27]),
- .O(muxed_data_c[4]));
- (* SOFT_HLUTNM = "soft_lutpair155" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[5]_i_1
- (.I0(Q[10]),
- .I1(MUX_SELECT),
- .I2(Q[26]),
- .O(muxed_data_c[5]));
- (* SOFT_HLUTNM = "soft_lutpair154" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[6]_i_1
- (.I0(Q[9]),
- .I1(MUX_SELECT),
- .I2(Q[25]),
- .O(muxed_data_c[6]));
- (* SOFT_HLUTNM = "soft_lutpair154" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[7]_i_1
- (.I0(Q[8]),
- .I1(MUX_SELECT),
- .I2(Q[24]),
- .O(muxed_data_c[7]));
- (* SOFT_HLUTNM = "soft_lutpair153" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[8]_i_1
- (.I0(Q[7]),
- .I1(MUX_SELECT),
- .I2(Q[23]),
- .O(muxed_data_c[8]));
- (* SOFT_HLUTNM = "soft_lutpair153" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[9]_i_1
- (.I0(Q[6]),
- .I1(MUX_SELECT),
- .I2(Q[22]),
- .O(muxed_data_c[9]));
- FDRE \MUXED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[0]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [15]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[10]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [5]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[11]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [4]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[12]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [3]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[13]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [2]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[14]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[15]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[15]),
- .Q(MUXED_DATA_Buffer[16]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[14]),
- .Q(MUXED_DATA_Buffer[17]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[13]),
- .Q(MUXED_DATA_Buffer[18]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[12]),
- .Q(MUXED_DATA_Buffer[19]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[1]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [14]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[11]),
- .Q(MUXED_DATA_Buffer[20]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[10]),
- .Q(MUXED_DATA_Buffer[21]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[9]),
- .Q(MUXED_DATA_Buffer[22]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[8]),
- .Q(MUXED_DATA_Buffer[23]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[7]),
- .Q(MUXED_DATA_Buffer[24]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[6]),
- .Q(MUXED_DATA_Buffer[25]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[5]),
- .Q(MUXED_DATA_Buffer[26]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[4]),
- .Q(MUXED_DATA_Buffer[27]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[3]),
- .Q(MUXED_DATA_Buffer[28]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[2]),
- .Q(MUXED_DATA_Buffer[29]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[2]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [13]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[1]),
- .Q(MUXED_DATA_Buffer[30]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[0]),
- .Q(MUXED_DATA_Buffer[31]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[3]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [12]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[4]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [11]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[5]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [10]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[6]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [9]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[7]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [8]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[8]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [7]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[9]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [6]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair173" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[0]_i_1
- (.I0(MUXED_DATA_Buffer[16]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [15]),
- .O(D[31]));
- (* SOFT_HLUTNM = "soft_lutpair163" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[10]_i_1
- (.I0(MUXED_DATA_Buffer[26]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [5]),
- .O(D[21]));
- (* SOFT_HLUTNM = "soft_lutpair162" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[11]_i_1
- (.I0(MUXED_DATA_Buffer[27]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [4]),
- .O(D[20]));
- (* SOFT_HLUTNM = "soft_lutpair161" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[12]_i_1
- (.I0(MUXED_DATA_Buffer[28]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [3]),
- .O(D[19]));
- (* SOFT_HLUTNM = "soft_lutpair160" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[13]_i_1
- (.I0(MUXED_DATA_Buffer[29]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [2]),
- .O(D[18]));
- (* SOFT_HLUTNM = "soft_lutpair159" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[14]_i_1
- (.I0(MUXED_DATA_Buffer[30]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [1]),
- .O(D[17]));
- (* SOFT_HLUTNM = "soft_lutpair158" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[15]_i_1
- (.I0(MUXED_DATA_Buffer[31]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [0]),
- .O(D[16]));
- (* SOFT_HLUTNM = "soft_lutpair173" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[16]_i_1
- (.I0(MUXED_DATA_Buffer[16]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [15]),
- .O(D[15]));
- (* SOFT_HLUTNM = "soft_lutpair172" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[17]_i_1
- (.I0(MUXED_DATA_Buffer[17]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [14]),
- .O(D[14]));
- (* SOFT_HLUTNM = "soft_lutpair171" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[18]_i_1
- (.I0(MUXED_DATA_Buffer[18]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [13]),
- .O(D[13]));
- (* SOFT_HLUTNM = "soft_lutpair170" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[19]_i_1
- (.I0(MUXED_DATA_Buffer[19]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [12]),
- .O(D[12]));
- (* SOFT_HLUTNM = "soft_lutpair172" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[1]_i_1
- (.I0(MUXED_DATA_Buffer[17]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [14]),
- .O(D[30]));
- (* SOFT_HLUTNM = "soft_lutpair169" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[20]_i_1
- (.I0(MUXED_DATA_Buffer[20]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [11]),
- .O(D[11]));
- (* SOFT_HLUTNM = "soft_lutpair168" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[21]_i_1
- (.I0(MUXED_DATA_Buffer[21]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [10]),
- .O(D[10]));
- (* SOFT_HLUTNM = "soft_lutpair167" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[22]_i_1
- (.I0(MUXED_DATA_Buffer[22]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [9]),
- .O(D[9]));
- (* SOFT_HLUTNM = "soft_lutpair166" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[23]_i_1
- (.I0(MUXED_DATA_Buffer[23]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [8]),
- .O(D[8]));
- (* SOFT_HLUTNM = "soft_lutpair165" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[24]_i_1
- (.I0(MUXED_DATA_Buffer[24]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [7]),
- .O(D[7]));
- (* SOFT_HLUTNM = "soft_lutpair164" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[25]_i_1
- (.I0(MUXED_DATA_Buffer[25]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [6]),
- .O(D[6]));
- (* SOFT_HLUTNM = "soft_lutpair163" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[26]_i_1
- (.I0(MUXED_DATA_Buffer[26]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [5]),
- .O(D[5]));
- (* SOFT_HLUTNM = "soft_lutpair162" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[27]_i_1
- (.I0(MUXED_DATA_Buffer[27]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [4]),
- .O(D[4]));
- (* SOFT_HLUTNM = "soft_lutpair161" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[28]_i_1
- (.I0(MUXED_DATA_Buffer[28]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [3]),
- .O(D[3]));
- (* SOFT_HLUTNM = "soft_lutpair160" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[29]_i_1
- (.I0(MUXED_DATA_Buffer[29]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [2]),
- .O(D[2]));
- (* SOFT_HLUTNM = "soft_lutpair171" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[2]_i_1
- (.I0(MUXED_DATA_Buffer[18]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [13]),
- .O(D[29]));
- (* SOFT_HLUTNM = "soft_lutpair159" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[30]_i_1
- (.I0(MUXED_DATA_Buffer[30]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [1]),
- .O(D[1]));
- (* SOFT_HLUTNM = "soft_lutpair158" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[31]_i_1
- (.I0(MUXED_DATA_Buffer[31]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [0]),
- .O(D[0]));
- (* SOFT_HLUTNM = "soft_lutpair170" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[3]_i_1
- (.I0(MUXED_DATA_Buffer[19]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [12]),
- .O(D[28]));
- (* SOFT_HLUTNM = "soft_lutpair169" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[4]_i_1
- (.I0(MUXED_DATA_Buffer[20]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [11]),
- .O(D[27]));
- (* SOFT_HLUTNM = "soft_lutpair168" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[5]_i_1
- (.I0(MUXED_DATA_Buffer[21]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [10]),
- .O(D[26]));
- (* SOFT_HLUTNM = "soft_lutpair167" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[6]_i_1
- (.I0(MUXED_DATA_Buffer[22]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [9]),
- .O(D[25]));
- (* SOFT_HLUTNM = "soft_lutpair166" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[7]_i_1
- (.I0(MUXED_DATA_Buffer[23]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [8]),
- .O(D[24]));
- (* SOFT_HLUTNM = "soft_lutpair165" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[8]_i_1
- (.I0(MUXED_DATA_Buffer[24]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [7]),
- .O(D[23]));
- (* SOFT_HLUTNM = "soft_lutpair164" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[9]_i_1
- (.I0(MUXED_DATA_Buffer[25]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [6]),
- .O(D[22]));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_LL_TO_AXI" *)
-module east_channel_east_channel_LL_TO_AXI
- (M_AXI_RX_TKEEP,
- rx_eof,
- \m_axi_rx_tkeep[1] );
- output [2:0]M_AXI_RX_TKEEP;
- input rx_eof;
- input [1:0]\m_axi_rx_tkeep[1] ;
-
- wire [2:0]M_AXI_RX_TKEEP;
- wire [1:0]\m_axi_rx_tkeep[1] ;
- wire rx_eof;
-
- (* SOFT_HLUTNM = "soft_lutpair279" *)
- LUT3 #(
- .INIT(8'hFE))
- \M_AXI_RX_TKEEP[1]_INST_0
- (.I0(rx_eof),
- .I1(\m_axi_rx_tkeep[1] [0]),
- .I2(\m_axi_rx_tkeep[1] [1]),
- .O(M_AXI_RX_TKEEP[2]));
- LUT2 #(
- .INIT(4'hE))
- \M_AXI_RX_TKEEP[2]_INST_0
- (.I0(rx_eof),
- .I1(\m_axi_rx_tkeep[1] [1]),
- .O(M_AXI_RX_TKEEP[1]));
- (* SOFT_HLUTNM = "soft_lutpair279" *)
- LUT3 #(
- .INIT(8'hEA))
- \M_AXI_RX_TKEEP[3]_INST_0
- (.I0(rx_eof),
- .I1(\m_axi_rx_tkeep[1] [1]),
- .I2(\m_axi_rx_tkeep[1] [0]),
- .O(M_AXI_RX_TKEEP[0]));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_OUTPUT_MUX" *)
-module east_channel_east_channel_OUTPUT_MUX
- (M_AXI_RX_TDATA,
- Q,
- user_clk,
- \OUTPUT_DATA_Buffer_reg[16]_0 ,
- OUTPUT_SELECT_Buffer);
- output [0:31]M_AXI_RX_TDATA;
- input [31:0]Q;
- input user_clk;
- input [15:0]\OUTPUT_DATA_Buffer_reg[16]_0 ;
- input OUTPUT_SELECT_Buffer;
-
- wire [0:31]M_AXI_RX_TDATA;
- wire [15:0]\OUTPUT_DATA_Buffer_reg[16]_0 ;
- wire OUTPUT_SELECT_Buffer;
- wire [31:0]Q;
- wire [16:31]output_data_c;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair144" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[16]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [15]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[15]),
- .O(output_data_c[16]));
- (* SOFT_HLUTNM = "soft_lutpair144" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[17]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [14]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[14]),
- .O(output_data_c[17]));
- (* SOFT_HLUTNM = "soft_lutpair143" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[18]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [13]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[13]),
- .O(output_data_c[18]));
- (* SOFT_HLUTNM = "soft_lutpair143" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[19]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [12]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[12]),
- .O(output_data_c[19]));
- (* SOFT_HLUTNM = "soft_lutpair142" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[20]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [11]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[11]),
- .O(output_data_c[20]));
- (* SOFT_HLUTNM = "soft_lutpair142" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[21]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [10]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[10]),
- .O(output_data_c[21]));
- (* SOFT_HLUTNM = "soft_lutpair141" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[22]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [9]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[9]),
- .O(output_data_c[22]));
- (* SOFT_HLUTNM = "soft_lutpair141" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[23]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [8]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[8]),
- .O(output_data_c[23]));
- (* SOFT_HLUTNM = "soft_lutpair140" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[24]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [7]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[7]),
- .O(output_data_c[24]));
- (* SOFT_HLUTNM = "soft_lutpair140" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[25]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [6]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[6]),
- .O(output_data_c[25]));
- (* SOFT_HLUTNM = "soft_lutpair139" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[26]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [5]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[5]),
- .O(output_data_c[26]));
- (* SOFT_HLUTNM = "soft_lutpair139" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[27]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [4]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[4]),
- .O(output_data_c[27]));
- (* SOFT_HLUTNM = "soft_lutpair138" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[28]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [3]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[3]),
- .O(output_data_c[28]));
- (* SOFT_HLUTNM = "soft_lutpair138" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[29]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [2]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[2]),
- .O(output_data_c[29]));
- (* SOFT_HLUTNM = "soft_lutpair137" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[30]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [1]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[1]),
- .O(output_data_c[30]));
- (* SOFT_HLUTNM = "soft_lutpair137" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[31]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [0]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[0]),
- .O(output_data_c[31]));
- FDRE \OUTPUT_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[31]),
- .Q(M_AXI_RX_TDATA[0]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[21]),
- .Q(M_AXI_RX_TDATA[10]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[20]),
- .Q(M_AXI_RX_TDATA[11]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[19]),
- .Q(M_AXI_RX_TDATA[12]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[18]),
- .Q(M_AXI_RX_TDATA[13]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[17]),
- .Q(M_AXI_RX_TDATA[14]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[16]),
- .Q(M_AXI_RX_TDATA[15]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[16]),
- .Q(M_AXI_RX_TDATA[16]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[17]),
- .Q(M_AXI_RX_TDATA[17]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[18]),
- .Q(M_AXI_RX_TDATA[18]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[19]),
- .Q(M_AXI_RX_TDATA[19]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[30]),
- .Q(M_AXI_RX_TDATA[1]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[20]),
- .Q(M_AXI_RX_TDATA[20]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[21]),
- .Q(M_AXI_RX_TDATA[21]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[22]),
- .Q(M_AXI_RX_TDATA[22]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[23]),
- .Q(M_AXI_RX_TDATA[23]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[24]),
- .Q(M_AXI_RX_TDATA[24]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[25]),
- .Q(M_AXI_RX_TDATA[25]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[26]),
- .Q(M_AXI_RX_TDATA[26]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[27]),
- .Q(M_AXI_RX_TDATA[27]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[28]),
- .Q(M_AXI_RX_TDATA[28]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[29]),
- .Q(M_AXI_RX_TDATA[29]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[29]),
- .Q(M_AXI_RX_TDATA[2]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[30]),
- .Q(M_AXI_RX_TDATA[30]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[31]),
- .Q(M_AXI_RX_TDATA[31]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[28]),
- .Q(M_AXI_RX_TDATA[3]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[27]),
- .Q(M_AXI_RX_TDATA[4]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[26]),
- .Q(M_AXI_RX_TDATA[5]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[25]),
- .Q(M_AXI_RX_TDATA[6]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[24]),
- .Q(M_AXI_RX_TDATA[7]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[23]),
- .Q(M_AXI_RX_TDATA[8]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[22]),
- .Q(M_AXI_RX_TDATA[9]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_OUTPUT_SWITCH_CONTROL" *)
-module east_channel_east_channel_OUTPUT_SWITCH_CONTROL
- (OUTPUT_SELECT_Buffer,
- output_select_c,
- user_clk);
- output OUTPUT_SELECT_Buffer;
- input [0:0]output_select_c;
- input user_clk;
-
- wire OUTPUT_SELECT_Buffer;
- wire [0:0]output_select_c;
- wire user_clk;
-
- FDRE \OUTPUT_SELECT_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_select_c),
- .Q(OUTPUT_SELECT_Buffer),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_RESET_LOGIC" *)
-module east_channel_east_channel_RESET_LOGIC
- (link_reset_r,
- SYSTEM_RESET_reg_0,
- wait_for_lane_up_r0,
- new_pkt_r,
- PLL_NOT_LOCKED,
- out,
- LINK_RESET_OUT,
- init_clk_in,
- user_clk,
- tx_lock,
- gt_rxresetdone_r2_reg_0,
- gt_txresetdone_r2_reg_0,
- reset_channel_i,
- new_pkt_r_reg,
- S_AXI_TX_TLAST,
- S_AXI_TX_TVALID,
- tx_dst_rdy,
- new_pkt_r_reg_0);
- output link_reset_r;
- output SYSTEM_RESET_reg_0;
- output wait_for_lane_up_r0;
- output new_pkt_r;
- input PLL_NOT_LOCKED;
- input out;
- input LINK_RESET_OUT;
- input init_clk_in;
- input user_clk;
- input tx_lock;
- input gt_rxresetdone_r2_reg_0;
- input gt_txresetdone_r2_reg_0;
- input reset_channel_i;
- input new_pkt_r_reg;
- input S_AXI_TX_TLAST;
- input S_AXI_TX_TVALID;
- input tx_dst_rdy;
- input new_pkt_r_reg_0;
-
- wire LINK_RESET_OUT;
- wire PLL_NOT_LOCKED;
- wire SYSTEM_RESET0_n_0;
- wire SYSTEM_RESET_reg_0;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TVALID;
- wire gt_rxresetdone_r;
- wire gt_rxresetdone_r2;
- wire gt_rxresetdone_r2_reg_0;
- wire gt_rxresetdone_r3;
- wire gt_txresetdone_r;
- wire gt_txresetdone_r2;
- wire gt_txresetdone_r2_reg_0;
- wire gt_txresetdone_r3;
- wire init_clk_in;
- wire link_reset_r;
- wire new_pkt_r;
- wire new_pkt_r_reg;
- wire new_pkt_r_reg_0;
- wire out;
- wire pll_not_locked_sync;
- wire reset_channel_i;
- wire scndry_out;
- wire tx_dst_rdy;
- wire tx_lock;
- wire tx_lock_comb_r;
- wire tx_lock_sync;
- wire user_clk;
- wire wait_for_lane_up_r0;
-
- LUT6 #(
- .INIT(64'hFFFFEFFFFFFFFFFF))
- SYSTEM_RESET0
- (.I0(pll_not_locked_sync),
- .I1(out),
- .I2(gt_txresetdone_r3),
- .I3(gt_rxresetdone_r3),
- .I4(scndry_out),
- .I5(tx_lock_sync),
- .O(SYSTEM_RESET0_n_0));
- FDRE SYSTEM_RESET_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(SYSTEM_RESET0_n_0),
- .Q(SYSTEM_RESET_reg_0),
- .R(1'b0));
- FDCE gt_rxresetdone_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_rxresetdone_r2_reg_0),
- .D(gt_rxresetdone_r),
- .Q(gt_rxresetdone_r2));
- FDRE gt_rxresetdone_r3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt_rxresetdone_r2),
- .Q(gt_rxresetdone_r3),
- .R(1'b0));
- FDCE gt_rxresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_rxresetdone_r2_reg_0),
- .D(1'b1),
- .Q(gt_rxresetdone_r));
- FDCE gt_txresetdone_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_txresetdone_r2_reg_0),
- .D(gt_txresetdone_r),
- .Q(gt_txresetdone_r2));
- FDRE gt_txresetdone_r3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt_txresetdone_r2),
- .Q(gt_txresetdone_r3),
- .R(1'b0));
- FDCE gt_txresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_txresetdone_r2_reg_0),
- .D(1'b1),
- .Q(gt_txresetdone_r));
- east_channel_east_channel_cdc_sync__parameterized3_27 link_reset_cdc_sync
- (.init_clk_in(init_clk_in),
- .link_reset_r(link_reset_r),
- .out(scndry_out),
- .user_clk(user_clk));
- FDRE link_reset_comb_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(LINK_RESET_OUT),
- .Q(link_reset_r),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h4444044400000400))
- new_pkt_r_i_1
- (.I0(SYSTEM_RESET_reg_0),
- .I1(new_pkt_r_reg),
- .I2(S_AXI_TX_TLAST),
- .I3(S_AXI_TX_TVALID),
- .I4(tx_dst_rdy),
- .I5(new_pkt_r_reg_0),
- .O(new_pkt_r));
- east_channel_east_channel_cdc_sync_28 pll_not_locked_cdc_sync
- (.PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .out(pll_not_locked_sync),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized3_29 tx_lock_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(tx_lock_sync),
- .tx_lock_comb_r(tx_lock_comb_r),
- .user_clk(user_clk));
- FDRE tx_lock_comb_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_lock),
- .Q(tx_lock_comb_r),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- verify_r_i_1
- (.I0(SYSTEM_RESET_reg_0),
- .I1(reset_channel_i),
- .O(wait_for_lane_up_r0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_RX_LL" *)
-module east_channel_east_channel_RX_LL
- (rx_eof,
- FRAME_ERR,
- M_AXI_RX_TLAST,
- M_AXI_RX_TVALID,
- M_AXI_UFC_RX_TVALID,
- \RX_REM_Buffer_reg[0] ,
- M_AXI_RX_TDATA,
- M_AXI_UFC_RX_TDATA,
- M_AXI_UFC_RX_TKEEP,
- M_AXI_UFC_RX_TLAST,
- user_clk,
- RESET,
- neqOp,
- \rx_suf_r_reg[0] ,
- p_8_out,
- p_9_out,
- Q,
- rx_pe_data_striped_i,
- START_RX,
- \stage_1_count_value_r_reg[0] ,
- \stage_1_count_value_r_reg[1] ,
- \stage_1_count_value_r_reg[2] ,
- \stage_1_count_value_r_reg[3] ,
- D);
- output rx_eof;
- output FRAME_ERR;
- output M_AXI_RX_TLAST;
- output M_AXI_RX_TVALID;
- output M_AXI_UFC_RX_TVALID;
- output [1:0]\RX_REM_Buffer_reg[0] ;
- output [0:31]M_AXI_RX_TDATA;
- output [0:31]M_AXI_UFC_RX_TDATA;
- output [0:0]M_AXI_UFC_RX_TKEEP;
- output M_AXI_UFC_RX_TLAST;
- input user_clk;
- input RESET;
- input neqOp;
- input [1:0]\rx_suf_r_reg[0] ;
- input [1:0]p_8_out;
- input [1:0]p_9_out;
- input [1:0]Q;
- input [0:31]rx_pe_data_striped_i;
- input START_RX;
- input \stage_1_count_value_r_reg[0] ;
- input \stage_1_count_value_r_reg[1] ;
- input \stage_1_count_value_r_reg[2] ;
- input \stage_1_count_value_r_reg[3] ;
- input [1:0]D;
-
- wire [1:0]D;
- wire FRAME_ERR;
- wire [0:31]M_AXI_RX_TDATA;
- wire M_AXI_RX_TLAST;
- wire M_AXI_RX_TVALID;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [0:0]M_AXI_UFC_RX_TKEEP;
- wire M_AXI_UFC_RX_TLAST;
- wire M_AXI_UFC_RX_TVALID;
- wire [1:0]Q;
- wire RESET;
- wire [1:0]\RX_REM_Buffer_reg[0] ;
- wire START_RX;
- wire UFC_START;
- wire barrel_shifter_control_i;
- wire neqOp;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [0:1]pdu_data_v_i;
- wire [0:1]pdu_ecp_i;
- wire [0:1]pdu_scp_i;
- wire plusOp;
- wire rx_eof;
- wire [0:31]rx_pe_data_striped_i;
- wire [1:0]\rx_suf_r_reg[0] ;
- wire \stage_1_count_value_r_reg[0] ;
- wire \stage_1_count_value_r_reg[1] ;
- wire \stage_1_count_value_r_reg[2] ;
- wire \stage_1_count_value_r_reg[3] ;
- wire [0:31]stage_1_data_r;
- wire \stage_1_rx_ll_deframer_i/S1_in ;
- wire ufc_filter_i_n_10;
- wire ufc_filter_i_n_11;
- wire ufc_filter_i_n_12;
- wire ufc_filter_i_n_13;
- wire ufc_filter_i_n_14;
- wire ufc_filter_i_n_15;
- wire ufc_filter_i_n_16;
- wire ufc_filter_i_n_17;
- wire ufc_filter_i_n_18;
- wire ufc_filter_i_n_19;
- wire ufc_filter_i_n_20;
- wire ufc_filter_i_n_21;
- wire ufc_filter_i_n_22;
- wire ufc_filter_i_n_23;
- wire ufc_filter_i_n_24;
- wire ufc_filter_i_n_25;
- wire ufc_filter_i_n_26;
- wire ufc_filter_i_n_27;
- wire ufc_filter_i_n_28;
- wire ufc_filter_i_n_29;
- wire ufc_filter_i_n_30;
- wire ufc_filter_i_n_31;
- wire ufc_filter_i_n_32;
- wire ufc_filter_i_n_33;
- wire ufc_filter_i_n_34;
- wire ufc_filter_i_n_35;
- wire ufc_filter_i_n_36;
- wire ufc_filter_i_n_37;
- wire ufc_filter_i_n_38;
- wire ufc_filter_i_n_39;
- wire ufc_filter_i_n_40;
- wire ufc_filter_i_n_44;
- wire ufc_filter_i_n_45;
- wire ufc_filter_i_n_6;
- wire ufc_filter_i_n_7;
- wire ufc_filter_i_n_8;
- wire ufc_filter_i_n_9;
- wire user_clk;
-
- east_channel_east_channel_RX_LL_PDU_DATAPATH rx_ll_pdu_datapath_i
- (.\AFTER_SCP_Buffer_reg[1] (ufc_filter_i_n_45),
- .D({pdu_scp_i[0],pdu_scp_i[1]}),
- .FRAME_ERR(FRAME_ERR),
- .\IN_FRAME_Buffer_reg[1] (ufc_filter_i_n_40),
- .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
- .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
- .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
- .Q({pdu_data_v_i[0],pdu_data_v_i[1]}),
- .RESET(RESET),
- .\RX_REM_Buffer_reg[0]_0 (\RX_REM_Buffer_reg[0] ),
- .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
- .START_RX(START_RX),
- .in_frame_r_reg(ufc_filter_i_n_39),
- .rx_eof(rx_eof),
- .\stage_1_ecp_r_reg[0]_0 ({pdu_ecp_i[0],pdu_ecp_i[1]}),
- .stage_1_pad_r_reg_0(ufc_filter_i_n_38),
- .\stage_2_data_r_reg[0]_0 ({stage_1_data_r[0],stage_1_data_r[1],stage_1_data_r[2],stage_1_data_r[3],stage_1_data_r[4],stage_1_data_r[5],stage_1_data_r[6],stage_1_data_r[7],stage_1_data_r[8],stage_1_data_r[9],stage_1_data_r[10],stage_1_data_r[11],stage_1_data_r[12],stage_1_data_r[13],stage_1_data_r[14],stage_1_data_r[15],stage_1_data_r[16],stage_1_data_r[17],stage_1_data_r[18],stage_1_data_r[19],stage_1_data_r[20],stage_1_data_r[21],stage_1_data_r[22],stage_1_data_r[23],stage_1_data_r[24],stage_1_data_r[25],stage_1_data_r[26],stage_1_data_r[27],stage_1_data_r[28],stage_1_data_r[29],stage_1_data_r[30],stage_1_data_r[31]}),
- .user_clk(user_clk));
- east_channel_east_channel_RX_LL_UFC_DATAPATH rx_ll_ufc_datapath_i
- (.M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
- .M_AXI_UFC_RX_TKEEP(M_AXI_UFC_RX_TKEEP),
- .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
- .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
- .Q({plusOp,ufc_filter_i_n_44}),
- .RESET(RESET),
- .UFC_START(UFC_START),
- .barrel_shifter_control_i(barrel_shifter_control_i),
- .\stage_1_data_r_reg[0]_0 ({stage_1_data_r[0],stage_1_data_r[1],stage_1_data_r[2],stage_1_data_r[3],stage_1_data_r[4],stage_1_data_r[5],stage_1_data_r[6],stage_1_data_r[7],stage_1_data_r[8],stage_1_data_r[9],stage_1_data_r[10],stage_1_data_r[11],stage_1_data_r[12],stage_1_data_r[13],stage_1_data_r[14],stage_1_data_r[15],stage_1_data_r[16],stage_1_data_r[17],stage_1_data_r[18],stage_1_data_r[19],stage_1_data_r[20],stage_1_data_r[21],stage_1_data_r[22],stage_1_data_r[23],stage_1_data_r[24],stage_1_data_r[25],stage_1_data_r[26],stage_1_data_r[27],stage_1_data_r[28],stage_1_data_r[29],stage_1_data_r[30],stage_1_data_r[31]}),
- .\stage_1_data_r_reg[0]_1 (ufc_filter_i_n_6),
- .\stage_1_data_r_reg[10]_0 (ufc_filter_i_n_16),
- .\stage_1_data_r_reg[11]_0 (ufc_filter_i_n_17),
- .\stage_1_data_r_reg[12]_0 (ufc_filter_i_n_18),
- .\stage_1_data_r_reg[13]_0 (ufc_filter_i_n_19),
- .\stage_1_data_r_reg[14]_0 (ufc_filter_i_n_20),
- .\stage_1_data_r_reg[15]_0 (ufc_filter_i_n_21),
- .\stage_1_data_r_reg[16]_0 (ufc_filter_i_n_22),
- .\stage_1_data_r_reg[17]_0 (ufc_filter_i_n_23),
- .\stage_1_data_r_reg[18]_0 (ufc_filter_i_n_24),
- .\stage_1_data_r_reg[19]_0 (ufc_filter_i_n_25),
- .\stage_1_data_r_reg[1]_0 (ufc_filter_i_n_7),
- .\stage_1_data_r_reg[20]_0 (ufc_filter_i_n_26),
- .\stage_1_data_r_reg[21]_0 (ufc_filter_i_n_27),
- .\stage_1_data_r_reg[22]_0 (ufc_filter_i_n_28),
- .\stage_1_data_r_reg[23]_0 (ufc_filter_i_n_29),
- .\stage_1_data_r_reg[24]_0 (ufc_filter_i_n_30),
- .\stage_1_data_r_reg[25]_0 (ufc_filter_i_n_31),
- .\stage_1_data_r_reg[26]_0 (ufc_filter_i_n_32),
- .\stage_1_data_r_reg[27]_0 (ufc_filter_i_n_33),
- .\stage_1_data_r_reg[28]_0 (ufc_filter_i_n_34),
- .\stage_1_data_r_reg[29]_0 (ufc_filter_i_n_35),
- .\stage_1_data_r_reg[2]_0 (ufc_filter_i_n_8),
- .\stage_1_data_r_reg[30]_0 (ufc_filter_i_n_36),
- .\stage_1_data_r_reg[31]_0 (ufc_filter_i_n_37),
- .\stage_1_data_r_reg[3]_0 (ufc_filter_i_n_9),
- .\stage_1_data_r_reg[4]_0 (ufc_filter_i_n_10),
- .\stage_1_data_r_reg[5]_0 (ufc_filter_i_n_11),
- .\stage_1_data_r_reg[6]_0 (ufc_filter_i_n_12),
- .\stage_1_data_r_reg[7]_0 (ufc_filter_i_n_13),
- .\stage_1_data_r_reg[8]_0 (ufc_filter_i_n_14),
- .\stage_1_data_r_reg[9]_0 (ufc_filter_i_n_15),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_FILTER ufc_filter_i
- (.D({pdu_scp_i[0],pdu_scp_i[1]}),
- .\PDU_DATA_V_Buffer_reg[0]_0 ({pdu_data_v_i[0],pdu_data_v_i[1]}),
- .\PDU_ECP_Buffer_reg[0]_0 ({pdu_ecp_i[0],pdu_ecp_i[1]}),
- .\PDU_ECP_Buffer_reg[0]_1 (ufc_filter_i_n_40),
- .\PDU_ECP_Buffer_reg[1]_0 (ufc_filter_i_n_39),
- .\PDU_PAD_Buffer_reg[0]_0 (ufc_filter_i_n_38),
- .\PDU_SCP_Buffer_reg[1]_0 (ufc_filter_i_n_45),
- .Q(Q),
- .RESET(RESET),
- .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
- .\UFC_DATA_V_Buffer_reg[0]_0 ({plusOp,ufc_filter_i_n_44}),
- .UFC_START(UFC_START),
- .barrel_shifter_control_i(barrel_shifter_control_i),
- .neqOp(neqOp),
- .p_8_out(p_8_out),
- .p_9_out(p_9_out),
- .\rx_data_v_r_reg[0]_0 (D),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .\rx_suf_r_reg[0]_0 (\rx_suf_r_reg[0] ),
- .\stage_1_count_value_r_reg[0]_0 (\stage_1_count_value_r_reg[0] ),
- .\stage_1_count_value_r_reg[1]_0 (\stage_1_count_value_r_reg[1] ),
- .\stage_1_count_value_r_reg[2]_0 (\stage_1_count_value_r_reg[2] ),
- .\stage_1_count_value_r_reg[3]_0 (\stage_1_count_value_r_reg[3] ),
- .user_clk(user_clk),
- .user_clk_0(ufc_filter_i_n_6),
- .user_clk_1(ufc_filter_i_n_7),
- .user_clk_10(ufc_filter_i_n_16),
- .user_clk_11(ufc_filter_i_n_17),
- .user_clk_12(ufc_filter_i_n_18),
- .user_clk_13(ufc_filter_i_n_19),
- .user_clk_14(ufc_filter_i_n_20),
- .user_clk_15(ufc_filter_i_n_21),
- .user_clk_16(ufc_filter_i_n_22),
- .user_clk_17(ufc_filter_i_n_23),
- .user_clk_18(ufc_filter_i_n_24),
- .user_clk_19(ufc_filter_i_n_25),
- .user_clk_2(ufc_filter_i_n_8),
- .user_clk_20(ufc_filter_i_n_26),
- .user_clk_21(ufc_filter_i_n_27),
- .user_clk_22(ufc_filter_i_n_28),
- .user_clk_23(ufc_filter_i_n_29),
- .user_clk_24(ufc_filter_i_n_30),
- .user_clk_25(ufc_filter_i_n_31),
- .user_clk_26(ufc_filter_i_n_32),
- .user_clk_27(ufc_filter_i_n_33),
- .user_clk_28(ufc_filter_i_n_34),
- .user_clk_29(ufc_filter_i_n_35),
- .user_clk_3(ufc_filter_i_n_9),
- .user_clk_30(ufc_filter_i_n_36),
- .user_clk_31(ufc_filter_i_n_37),
- .user_clk_4(ufc_filter_i_n_10),
- .user_clk_5(ufc_filter_i_n_11),
- .user_clk_6(ufc_filter_i_n_12),
- .user_clk_7(ufc_filter_i_n_13),
- .user_clk_8(ufc_filter_i_n_14),
- .user_clk_9(ufc_filter_i_n_15));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_RX_LL_DEFRAMER" *)
-module east_channel_east_channel_RX_LL_DEFRAMER
- (mux_select_c,
- \AFTER_SCP_Buffer_reg[0]_0 ,
- \AFTER_SCP_Buffer_reg[0]_1 ,
- \AFTER_SCP_Buffer_reg[0]_2 ,
- \DEFRAMED_DATA_V_Buffer_reg[1]_0 ,
- \stage_1_ecp_r_reg[0] ,
- \IN_FRAME_Buffer_reg[1]_0 ,
- D,
- in_frame_r_reg_0,
- S1_in,
- \AFTER_SCP_Buffer_reg[1]_0 ,
- RESET,
- user_clk,
- Q,
- stage_2_frame_err_r_reg,
- \DEFRAMED_DATA_V_Buffer_reg[0]_0 );
- output [0:0]mux_select_c;
- output \AFTER_SCP_Buffer_reg[0]_0 ;
- output \AFTER_SCP_Buffer_reg[0]_1 ;
- output \AFTER_SCP_Buffer_reg[0]_2 ;
- output [1:0]\DEFRAMED_DATA_V_Buffer_reg[1]_0 ;
- output \stage_1_ecp_r_reg[0] ;
- input \IN_FRAME_Buffer_reg[1]_0 ;
- input [1:0]D;
- input in_frame_r_reg_0;
- input S1_in;
- input \AFTER_SCP_Buffer_reg[1]_0 ;
- input RESET;
- input user_clk;
- input [1:0]Q;
- input [1:0]stage_2_frame_err_r_reg;
- input [1:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;
-
- wire \AFTER_SCP_Buffer_reg[0]_0 ;
- wire \AFTER_SCP_Buffer_reg[0]_1 ;
- wire \AFTER_SCP_Buffer_reg[0]_2 ;
- wire \AFTER_SCP_Buffer_reg[1]_0 ;
- wire CI;
- wire [1:0]D;
- wire \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ;
- wire \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;
- wire [1:0]\DEFRAMED_DATA_V_Buffer_reg[1]_0 ;
- wire \IN_FRAME_Buffer_reg[1]_0 ;
- wire [1:0]Q;
- wire RESET;
- wire S1_in;
- wire after_scp_c_1;
- wire data_after_start_muxcy_1_n_0;
- wire in_frame_c_0;
- wire in_frame_c_1;
- wire in_frame_r_reg_0;
- wire [0:0]mux_select_c;
- wire [0:1]stage_1_after_scp_r;
- wire [0:1]stage_1_data_v_r;
- wire \stage_1_ecp_r_reg[0] ;
- wire [0:1]stage_1_in_frame_r;
- wire [1:0]stage_2_frame_err_r_reg;
- wire user_clk;
- wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED;
- wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED;
- wire [3:0]NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED;
- wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED;
- wire [3:2]NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED;
- wire [3:2]NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED;
- wire [3:0]NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED;
- wire [3:2]NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED;
-
- FDRE \AFTER_SCP_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(after_scp_c_1),
- .Q(stage_1_after_scp_r[0]),
- .R(RESET));
- FDRE \AFTER_SCP_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(data_after_start_muxcy_1_n_0),
- .Q(stage_1_after_scp_r[1]),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair148" *)
- LUT2 #(
- .INIT(4'h8))
- \COUNT_Buffer[0]_i_1
- (.I0(stage_1_data_v_r[1]),
- .I1(stage_1_data_v_r[0]),
- .O(\DEFRAMED_DATA_V_Buffer_reg[1]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair148" *)
- LUT2 #(
- .INIT(4'h6))
- \COUNT_Buffer[1]_i_1
- (.I0(stage_1_data_v_r[0]),
- .I1(stage_1_data_v_r[1]),
- .O(\DEFRAMED_DATA_V_Buffer_reg[1]_0 [0]));
- LUT2 #(
- .INIT(4'h8))
- \DEFRAMED_DATA_V_Buffer[0]_i_1
- (.I0(in_frame_c_1),
- .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [1]),
- .O(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \DEFRAMED_DATA_V_Buffer[1]_i_1
- (.I0(in_frame_c_0),
- .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [0]),
- .O(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \DEFRAMED_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ),
- .Q(stage_1_data_v_r[0]),
- .R(RESET));
- FDRE \DEFRAMED_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(stage_1_data_v_r[1]),
- .R(RESET));
- FDRE \IN_FRAME_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(CI),
- .Q(stage_1_in_frame_r[0]),
- .R(RESET));
- FDRE \IN_FRAME_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(in_frame_c_1),
- .Q(stage_1_in_frame_r[1]),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair147" *)
- LUT2 #(
- .INIT(4'h2))
- \MUX_SELECT_Buffer[2]_i_1
- (.I0(stage_1_data_v_r[1]),
- .I1(stage_1_data_v_r[0]),
- .O(mux_select_c));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* OPT_MODIFIED = "MLO" *)
- (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
- CARRY4 data_after_start_muxcy_0_CARRY4
- (.CI(1'b0),
- .CO({NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED[3:2],data_after_start_muxcy_1_n_0,after_scp_c_1}),
- .CYINIT(1'b0),
- .DI({NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED[3:2],1'b1,1'b1}),
- .O(NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
- .S({NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED[3:2],\AFTER_SCP_Buffer_reg[1]_0 ,S1_in}));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* OPT_MODIFIED = "MLO" *)
- (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
- CARRY4 in_frame_muxcy_0_CARRY4
- (.CI(1'b0),
- .CO({NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED[3:2],in_frame_c_0,in_frame_c_1}),
- .CYINIT(CI),
- .DI({NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED[3:2],D[0],D[1]}),
- .O(NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
- .S({NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED[3:2],in_frame_r_reg_0,\IN_FRAME_Buffer_reg[1]_0 }));
- FDRE in_frame_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(in_frame_c_0),
- .Q(CI),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair146" *)
- LUT4 #(
- .INIT(16'hF888))
- stage_2_end_after_start_r_i_1
- (.I0(stage_1_after_scp_r[0]),
- .I1(Q[1]),
- .I2(stage_1_after_scp_r[1]),
- .I3(Q[0]),
- .O(\AFTER_SCP_Buffer_reg[0]_2 ));
- (* SOFT_HLUTNM = "soft_lutpair146" *)
- LUT4 #(
- .INIT(16'h4F44))
- stage_2_end_before_start_r_i_1
- (.I0(stage_1_after_scp_r[0]),
- .I1(Q[1]),
- .I2(stage_1_after_scp_r[1]),
- .I3(Q[0]),
- .O(\AFTER_SCP_Buffer_reg[0]_1 ));
- LUT6 #(
- .INIT(64'hFFFFF0AAFCEEFCEE))
- stage_2_frame_err_r_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .I2(stage_2_frame_err_r_reg[1]),
- .I3(stage_1_in_frame_r[0]),
- .I4(stage_2_frame_err_r_reg[0]),
- .I5(stage_1_in_frame_r[1]),
- .O(\stage_1_ecp_r_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair147" *)
- LUT4 #(
- .INIT(16'hF888))
- stage_2_start_with_data_r_i_1
- (.I0(stage_1_after_scp_r[0]),
- .I1(stage_1_data_v_r[0]),
- .I2(stage_1_after_scp_r[1]),
- .I3(stage_1_data_v_r[1]),
- .O(\AFTER_SCP_Buffer_reg[0]_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_RX_LL_PDU_DATAPATH" *)
-module east_channel_east_channel_RX_LL_PDU_DATAPATH
- (rx_eof,
- FRAME_ERR,
- M_AXI_RX_TLAST,
- M_AXI_RX_TVALID,
- \RX_REM_Buffer_reg[0]_0 ,
- M_AXI_RX_TDATA,
- \IN_FRAME_Buffer_reg[1] ,
- D,
- in_frame_r_reg,
- S1_in,
- \AFTER_SCP_Buffer_reg[1] ,
- user_clk,
- RESET,
- stage_1_pad_r_reg_0,
- START_RX,
- Q,
- \stage_1_ecp_r_reg[0]_0 ,
- \stage_2_data_r_reg[0]_0 );
- output rx_eof;
- output FRAME_ERR;
- output M_AXI_RX_TLAST;
- output M_AXI_RX_TVALID;
- output [1:0]\RX_REM_Buffer_reg[0]_0 ;
- output [0:31]M_AXI_RX_TDATA;
- input \IN_FRAME_Buffer_reg[1] ;
- input [1:0]D;
- input in_frame_r_reg;
- input S1_in;
- input \AFTER_SCP_Buffer_reg[1] ;
- input user_clk;
- input RESET;
- input stage_1_pad_r_reg_0;
- input START_RX;
- input [1:0]Q;
- input [1:0]\stage_1_ecp_r_reg[0]_0 ;
- input [31:0]\stage_2_data_r_reg[0]_0 ;
-
- wire \AFTER_SCP_Buffer_reg[1] ;
- wire [1:0]D;
- wire EOF_N_Buffer;
- wire FRAME_ERR;
- wire FRAME_ERR_RESULT_Buffer;
- wire FRAME_ERR_RESULT_Buffer0;
- wire \IN_FRAME_Buffer_reg[1] ;
- wire [0:15]MUXED_DATA_Buffer;
- wire [2:2]MUX_SELECT;
- wire [0:31]M_AXI_RX_TDATA;
- wire M_AXI_RX_TLAST;
- wire M_AXI_RX_TVALID;
- wire OUTPUT_SELECT_Buffer;
- wire [1:0]Q;
- wire RESET;
- wire [0:1]RX_REM_Buffer;
- wire [1:0]\RX_REM_Buffer_reg[0]_0 ;
- wire RX_SRC_RDY_N_Buffer;
- wire S1_in;
- wire SRC_RDY_N_Buffer;
- wire START_RX;
- wire [0:31]STORAGE_DATA;
- wire [4:9]STORAGE_SELECT_Buffer;
- wire [0:1]ce_command_c;
- wire end_storage_r0;
- wire in_frame_r_reg;
- wire [2:2]mux_select_c;
- wire [9:9]output_select_c;
- wire p_0_in0;
- wire rx_eof;
- wire sideband_output_i_n_1;
- wire sideband_output_i_n_5;
- wire [0:1]stage_1_ecp_r;
- wire [1:0]\stage_1_ecp_r_reg[0]_0 ;
- wire stage_1_pad_r;
- wire stage_1_pad_r_reg_0;
- wire stage_1_rx_ll_deframer_i_n_1;
- wire stage_1_rx_ll_deframer_i_n_2;
- wire stage_1_rx_ll_deframer_i_n_3;
- wire stage_1_rx_ll_deframer_i_n_4;
- wire stage_1_rx_ll_deframer_i_n_5;
- wire stage_1_rx_ll_deframer_i_n_6;
- wire [0:1]stage_1_scp_r;
- wire [0:31]stage_2_data_r;
- wire [31:0]\stage_2_data_r_reg[0]_0 ;
- wire [1:1]stage_2_data_v_count_r;
- wire stage_2_end_after_start_r;
- wire stage_2_end_before_start_r;
- wire stage_2_frame_err_r;
- wire stage_2_pad_r;
- wire stage_2_start_with_data_r;
- wire stage_2_valid_data_counter_i_n_3;
- wire stage_3_end_storage_r;
- wire stage_3_left_align_datapath_mux_i_n_16;
- wire stage_3_left_align_datapath_mux_i_n_17;
- wire stage_3_left_align_datapath_mux_i_n_18;
- wire stage_3_left_align_datapath_mux_i_n_19;
- wire stage_3_left_align_datapath_mux_i_n_20;
- wire stage_3_left_align_datapath_mux_i_n_21;
- wire stage_3_left_align_datapath_mux_i_n_22;
- wire stage_3_left_align_datapath_mux_i_n_23;
- wire stage_3_left_align_datapath_mux_i_n_24;
- wire stage_3_left_align_datapath_mux_i_n_25;
- wire stage_3_left_align_datapath_mux_i_n_26;
- wire stage_3_left_align_datapath_mux_i_n_27;
- wire stage_3_left_align_datapath_mux_i_n_28;
- wire stage_3_left_align_datapath_mux_i_n_29;
- wire stage_3_left_align_datapath_mux_i_n_30;
- wire stage_3_left_align_datapath_mux_i_n_31;
- wire stage_3_left_align_datapath_mux_i_n_32;
- wire stage_3_left_align_datapath_mux_i_n_33;
- wire stage_3_left_align_datapath_mux_i_n_34;
- wire stage_3_left_align_datapath_mux_i_n_35;
- wire stage_3_left_align_datapath_mux_i_n_36;
- wire stage_3_left_align_datapath_mux_i_n_37;
- wire stage_3_left_align_datapath_mux_i_n_38;
- wire stage_3_left_align_datapath_mux_i_n_39;
- wire stage_3_left_align_datapath_mux_i_n_40;
- wire stage_3_left_align_datapath_mux_i_n_41;
- wire stage_3_left_align_datapath_mux_i_n_42;
- wire stage_3_left_align_datapath_mux_i_n_43;
- wire stage_3_left_align_datapath_mux_i_n_44;
- wire stage_3_left_align_datapath_mux_i_n_45;
- wire stage_3_left_align_datapath_mux_i_n_46;
- wire stage_3_left_align_datapath_mux_i_n_47;
- wire stage_3_storage_ce_control_i_n_1;
- wire stage_3_storage_count_control_i_n_4;
- wire [0:1]stage_3_storage_count_r;
- wire std_bool2_in;
- wire std_bool6_in;
- wire user_clk;
-
- FDRE FRAME_ERR_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(FRAME_ERR_RESULT_Buffer),
- .Q(FRAME_ERR),
- .R(RESET));
- LUT1 #(
- .INIT(2'h1))
- M_AXI_RX_TLAST_INST_0
- (.I0(rx_eof),
- .O(M_AXI_RX_TLAST));
- LUT1 #(
- .INIT(2'h1))
- M_AXI_RX_TVALID_INST_0
- (.I0(RX_SRC_RDY_N_Buffer),
- .O(M_AXI_RX_TVALID));
- FDRE RX_EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(EOF_N_Buffer),
- .Q(rx_eof),
- .R(1'b0));
- FDRE \RX_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_REM_Buffer[0]),
- .Q(\RX_REM_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_REM_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_REM_Buffer[1]),
- .Q(\RX_REM_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDSE RX_SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(SRC_RDY_N_Buffer),
- .Q(RX_SRC_RDY_N_Buffer),
- .S(RESET));
- east_channel_east_channel_OUTPUT_MUX output_mux_i
- (.M_AXI_RX_TDATA(M_AXI_RX_TDATA),
- .\OUTPUT_DATA_Buffer_reg[16]_0 ({MUXED_DATA_Buffer[0],MUXED_DATA_Buffer[1],MUXED_DATA_Buffer[2],MUXED_DATA_Buffer[3],MUXED_DATA_Buffer[4],MUXED_DATA_Buffer[5],MUXED_DATA_Buffer[6],MUXED_DATA_Buffer[7],MUXED_DATA_Buffer[8],MUXED_DATA_Buffer[9],MUXED_DATA_Buffer[10],MUXED_DATA_Buffer[11],MUXED_DATA_Buffer[12],MUXED_DATA_Buffer[13],MUXED_DATA_Buffer[14],MUXED_DATA_Buffer[15]}),
- .OUTPUT_SELECT_Buffer(OUTPUT_SELECT_Buffer),
- .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31]}),
- .user_clk(user_clk));
- east_channel_east_channel_SIDEBAND_OUTPUT sideband_output_i
- (.D(sideband_output_i_n_5),
- .EOF_N_Buffer(EOF_N_Buffer),
- .EOF_N_Buffer_reg_0(stage_3_storage_count_control_i_n_4),
- .FRAME_ERR_RESULT_Buffer(FRAME_ERR_RESULT_Buffer),
- .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
- .Q(stage_3_storage_count_r[1]),
- .\RX_REM_Buffer_reg[0]_0 ({RX_REM_Buffer[0],RX_REM_Buffer[1]}),
- .\RX_REM_Buffer_reg[0]_1 (stage_2_data_v_count_r),
- .SR(sideband_output_i_n_1),
- .SRC_RDY_N_Buffer(SRC_RDY_N_Buffer),
- .START_RX(START_RX),
- .end_storage_r0(end_storage_r0),
- .stage_2_end_before_start_r(stage_2_end_before_start_r),
- .stage_2_frame_err_r(stage_2_frame_err_r),
- .stage_2_pad_r(stage_2_pad_r),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .std_bool6_in(std_bool6_in),
- .user_clk(user_clk));
- FDRE \stage_1_ecp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_ecp_r_reg[0]_0 [1]),
- .Q(stage_1_ecp_r[0]),
- .R(1'b0));
- FDRE \stage_1_ecp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_ecp_r_reg[0]_0 [0]),
- .Q(stage_1_ecp_r[1]),
- .R(1'b0));
- FDRE stage_1_pad_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_pad_r_reg_0),
- .Q(stage_1_pad_r),
- .R(1'b0));
- east_channel_east_channel_RX_LL_DEFRAMER stage_1_rx_ll_deframer_i
- (.\AFTER_SCP_Buffer_reg[0]_0 (stage_1_rx_ll_deframer_i_n_1),
- .\AFTER_SCP_Buffer_reg[0]_1 (stage_1_rx_ll_deframer_i_n_2),
- .\AFTER_SCP_Buffer_reg[0]_2 (stage_1_rx_ll_deframer_i_n_3),
- .\AFTER_SCP_Buffer_reg[1]_0 (\AFTER_SCP_Buffer_reg[1] ),
- .D(D),
- .\DEFRAMED_DATA_V_Buffer_reg[0]_0 (Q),
- .\DEFRAMED_DATA_V_Buffer_reg[1]_0 ({stage_1_rx_ll_deframer_i_n_4,stage_1_rx_ll_deframer_i_n_5}),
- .\IN_FRAME_Buffer_reg[1]_0 (\IN_FRAME_Buffer_reg[1] ),
- .Q({stage_1_ecp_r[0],stage_1_ecp_r[1]}),
- .RESET(RESET),
- .S1_in(S1_in),
- .in_frame_r_reg_0(in_frame_r_reg),
- .mux_select_c(mux_select_c),
- .\stage_1_ecp_r_reg[0] (stage_1_rx_ll_deframer_i_n_6),
- .stage_2_frame_err_r_reg({stage_1_scp_r[0],stage_1_scp_r[1]}),
- .user_clk(user_clk));
- FDRE \stage_1_scp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(stage_1_scp_r[0]),
- .R(1'b0));
- FDRE \stage_1_scp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(stage_1_scp_r[1]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [31]),
- .Q(stage_2_data_r[0]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [21]),
- .Q(stage_2_data_r[10]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [20]),
- .Q(stage_2_data_r[11]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [19]),
- .Q(stage_2_data_r[12]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [18]),
- .Q(stage_2_data_r[13]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [17]),
- .Q(stage_2_data_r[14]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [16]),
- .Q(stage_2_data_r[15]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [15]),
- .Q(stage_2_data_r[16]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [14]),
- .Q(stage_2_data_r[17]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [13]),
- .Q(stage_2_data_r[18]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [12]),
- .Q(stage_2_data_r[19]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [30]),
- .Q(stage_2_data_r[1]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [11]),
- .Q(stage_2_data_r[20]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [10]),
- .Q(stage_2_data_r[21]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [9]),
- .Q(stage_2_data_r[22]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [8]),
- .Q(stage_2_data_r[23]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [7]),
- .Q(stage_2_data_r[24]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [6]),
- .Q(stage_2_data_r[25]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [5]),
- .Q(stage_2_data_r[26]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [4]),
- .Q(stage_2_data_r[27]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [3]),
- .Q(stage_2_data_r[28]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [2]),
- .Q(stage_2_data_r[29]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [29]),
- .Q(stage_2_data_r[2]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [1]),
- .Q(stage_2_data_r[30]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [0]),
- .Q(stage_2_data_r[31]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [28]),
- .Q(stage_2_data_r[3]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [27]),
- .Q(stage_2_data_r[4]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [26]),
- .Q(stage_2_data_r[5]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [25]),
- .Q(stage_2_data_r[6]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [24]),
- .Q(stage_2_data_r[7]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [23]),
- .Q(stage_2_data_r[8]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [22]),
- .Q(stage_2_data_r[9]),
- .R(1'b0));
- FDRE stage_2_end_after_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_3),
- .Q(stage_2_end_after_start_r),
- .R(RESET));
- FDRE stage_2_end_before_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_2),
- .Q(stage_2_end_before_start_r),
- .R(RESET));
- FDRE stage_2_frame_err_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_6),
- .Q(stage_2_frame_err_r),
- .R(RESET));
- east_channel_east_channel_LEFT_ALIGN_CONTROL stage_2_left_align_control_i
- (.MUX_SELECT(MUX_SELECT),
- .mux_select_c(mux_select_c),
- .user_clk(user_clk));
- FDRE stage_2_pad_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_pad_r),
- .Q(stage_2_pad_r),
- .R(1'b0));
- FDRE stage_2_start_with_data_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_1),
- .Q(stage_2_start_with_data_r),
- .R(RESET));
- east_channel_east_channel_VALID_DATA_COUNTER_22 stage_2_valid_data_counter_i
- (.\COUNT_Buffer_reg[0]_0 ({stage_1_rx_ll_deframer_i_n_4,stage_1_rx_ll_deframer_i_n_5}),
- .D({ce_command_c[0],ce_command_c[1]}),
- .Q(stage_2_data_v_count_r),
- .RESET(RESET),
- .\STORAGE_CE_Buffer_reg[0] ({stage_3_storage_count_r[0],stage_3_storage_count_r[1]}),
- .end_storage_r0(end_storage_r0),
- .end_storage_r_reg(stage_2_valid_data_counter_i_n_3),
- .stage_2_end_after_start_r(stage_2_end_after_start_r),
- .stage_2_end_before_start_r(stage_2_end_before_start_r),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .std_bool2_in(std_bool2_in),
- .std_bool6_in(std_bool6_in),
- .user_clk(user_clk));
- east_channel_east_channel_LEFT_ALIGN_MUX stage_3_left_align_datapath_mux_i
- (.D({stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,stage_3_left_align_datapath_mux_i_n_32,stage_3_left_align_datapath_mux_i_n_33,stage_3_left_align_datapath_mux_i_n_34,stage_3_left_align_datapath_mux_i_n_35,stage_3_left_align_datapath_mux_i_n_36,stage_3_left_align_datapath_mux_i_n_37,stage_3_left_align_datapath_mux_i_n_38,stage_3_left_align_datapath_mux_i_n_39,stage_3_left_align_datapath_mux_i_n_40,stage_3_left_align_datapath_mux_i_n_41,stage_3_left_align_datapath_mux_i_n_42,stage_3_left_align_datapath_mux_i_n_43,stage_3_left_align_datapath_mux_i_n_44,stage_3_left_align_datapath_mux_i_n_45,stage_3_left_align_datapath_mux_i_n_46,stage_3_left_align_datapath_mux_i_n_47}),
- .\MUXED_DATA_Buffer_reg[0]_0 ({MUXED_DATA_Buffer[0],MUXED_DATA_Buffer[1],MUXED_DATA_Buffer[2],MUXED_DATA_Buffer[3],MUXED_DATA_Buffer[4],MUXED_DATA_Buffer[5],MUXED_DATA_Buffer[6],MUXED_DATA_Buffer[7],MUXED_DATA_Buffer[8],MUXED_DATA_Buffer[9],MUXED_DATA_Buffer[10],MUXED_DATA_Buffer[11],MUXED_DATA_Buffer[12],MUXED_DATA_Buffer[13],MUXED_DATA_Buffer[14],MUXED_DATA_Buffer[15]}),
- .MUX_SELECT(MUX_SELECT),
- .Q({stage_2_data_r[0],stage_2_data_r[1],stage_2_data_r[2],stage_2_data_r[3],stage_2_data_r[4],stage_2_data_r[5],stage_2_data_r[6],stage_2_data_r[7],stage_2_data_r[8],stage_2_data_r[9],stage_2_data_r[10],stage_2_data_r[11],stage_2_data_r[12],stage_2_data_r[13],stage_2_data_r[14],stage_2_data_r[15],stage_2_data_r[16],stage_2_data_r[17],stage_2_data_r[18],stage_2_data_r[19],stage_2_data_r[20],stage_2_data_r[21],stage_2_data_r[22],stage_2_data_r[23],stage_2_data_r[24],stage_2_data_r[25],stage_2_data_r[26],stage_2_data_r[27],stage_2_data_r[28],stage_2_data_r[29],stage_2_data_r[30],stage_2_data_r[31]}),
- .STORAGE_SELECT_Buffer({STORAGE_SELECT_Buffer[4],STORAGE_SELECT_Buffer[9]}),
- .user_clk(user_clk));
- east_channel_east_channel_OUTPUT_SWITCH_CONTROL stage_3_output_switch_control_i
- (.OUTPUT_SELECT_Buffer(OUTPUT_SELECT_Buffer),
- .output_select_c(output_select_c),
- .user_clk(user_clk));
- east_channel_east_channel_STORAGE_CE_CONTROL stage_3_storage_ce_control_i
- (.D({ce_command_c[0],ce_command_c[1]}),
- .Q({p_0_in0,stage_3_storage_ce_control_i_n_1}),
- .RESET(RESET),
- .user_clk(user_clk));
- east_channel_east_channel_STORAGE_COUNT_CONTROL stage_3_storage_count_control_i
- (.D({stage_2_valid_data_counter_i_n_3,sideband_output_i_n_5}),
- .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
- .Q({stage_3_storage_count_r[0],stage_3_storage_count_r[1]}),
- .SR(sideband_output_i_n_1),
- .end_storage_r_reg(stage_3_storage_count_control_i_n_4),
- .output_select_c(output_select_c),
- .stage_2_end_after_start_r(stage_2_end_after_start_r),
- .stage_2_end_before_start_r(stage_2_end_before_start_r),
- .stage_2_frame_err_r(stage_2_frame_err_r),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .std_bool2_in(std_bool2_in),
- .user_clk(user_clk));
- east_channel_east_channel_STORAGE_SWITCH_CONTROL stage_3_storage_switch_control_i
- (.Q(stage_3_storage_count_r[1]),
- .STORAGE_SELECT_Buffer({STORAGE_SELECT_Buffer[4],STORAGE_SELECT_Buffer[9]}),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .user_clk(user_clk));
- east_channel_east_channel_STORAGE_MUX stage_4_storage_mux_i
- (.D({stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,stage_3_left_align_datapath_mux_i_n_32,stage_3_left_align_datapath_mux_i_n_33,stage_3_left_align_datapath_mux_i_n_34,stage_3_left_align_datapath_mux_i_n_35,stage_3_left_align_datapath_mux_i_n_36,stage_3_left_align_datapath_mux_i_n_37,stage_3_left_align_datapath_mux_i_n_38,stage_3_left_align_datapath_mux_i_n_39,stage_3_left_align_datapath_mux_i_n_40,stage_3_left_align_datapath_mux_i_n_41,stage_3_left_align_datapath_mux_i_n_42,stage_3_left_align_datapath_mux_i_n_43,stage_3_left_align_datapath_mux_i_n_44,stage_3_left_align_datapath_mux_i_n_45,stage_3_left_align_datapath_mux_i_n_46,stage_3_left_align_datapath_mux_i_n_47}),
- .E({p_0_in0,stage_3_storage_ce_control_i_n_1}),
- .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31]}),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_RX_LL_UFC_DATAPATH" *)
-module east_channel_east_channel_RX_LL_UFC_DATAPATH
- (\stage_1_data_r_reg[0]_0 ,
- M_AXI_UFC_RX_TVALID,
- M_AXI_UFC_RX_TDATA,
- M_AXI_UFC_RX_TKEEP,
- M_AXI_UFC_RX_TLAST,
- user_clk,
- RESET,
- UFC_START,
- barrel_shifter_control_i,
- \stage_1_data_r_reg[0]_1 ,
- \stage_1_data_r_reg[1]_0 ,
- \stage_1_data_r_reg[2]_0 ,
- \stage_1_data_r_reg[3]_0 ,
- \stage_1_data_r_reg[4]_0 ,
- \stage_1_data_r_reg[5]_0 ,
- \stage_1_data_r_reg[6]_0 ,
- \stage_1_data_r_reg[7]_0 ,
- \stage_1_data_r_reg[8]_0 ,
- \stage_1_data_r_reg[9]_0 ,
- \stage_1_data_r_reg[10]_0 ,
- \stage_1_data_r_reg[11]_0 ,
- \stage_1_data_r_reg[12]_0 ,
- \stage_1_data_r_reg[13]_0 ,
- \stage_1_data_r_reg[14]_0 ,
- \stage_1_data_r_reg[15]_0 ,
- \stage_1_data_r_reg[16]_0 ,
- \stage_1_data_r_reg[17]_0 ,
- \stage_1_data_r_reg[18]_0 ,
- \stage_1_data_r_reg[19]_0 ,
- \stage_1_data_r_reg[20]_0 ,
- \stage_1_data_r_reg[21]_0 ,
- \stage_1_data_r_reg[22]_0 ,
- \stage_1_data_r_reg[23]_0 ,
- \stage_1_data_r_reg[24]_0 ,
- \stage_1_data_r_reg[25]_0 ,
- \stage_1_data_r_reg[26]_0 ,
- \stage_1_data_r_reg[27]_0 ,
- \stage_1_data_r_reg[28]_0 ,
- \stage_1_data_r_reg[29]_0 ,
- \stage_1_data_r_reg[30]_0 ,
- \stage_1_data_r_reg[31]_0 ,
- Q);
- output [31:0]\stage_1_data_r_reg[0]_0 ;
- output M_AXI_UFC_RX_TVALID;
- output [0:31]M_AXI_UFC_RX_TDATA;
- output [0:0]M_AXI_UFC_RX_TKEEP;
- output M_AXI_UFC_RX_TLAST;
- input user_clk;
- input RESET;
- input UFC_START;
- input barrel_shifter_control_i;
- input \stage_1_data_r_reg[0]_1 ;
- input \stage_1_data_r_reg[1]_0 ;
- input \stage_1_data_r_reg[2]_0 ;
- input \stage_1_data_r_reg[3]_0 ;
- input \stage_1_data_r_reg[4]_0 ;
- input \stage_1_data_r_reg[5]_0 ;
- input \stage_1_data_r_reg[6]_0 ;
- input \stage_1_data_r_reg[7]_0 ;
- input \stage_1_data_r_reg[8]_0 ;
- input \stage_1_data_r_reg[9]_0 ;
- input \stage_1_data_r_reg[10]_0 ;
- input \stage_1_data_r_reg[11]_0 ;
- input \stage_1_data_r_reg[12]_0 ;
- input \stage_1_data_r_reg[13]_0 ;
- input \stage_1_data_r_reg[14]_0 ;
- input \stage_1_data_r_reg[15]_0 ;
- input \stage_1_data_r_reg[16]_0 ;
- input \stage_1_data_r_reg[17]_0 ;
- input \stage_1_data_r_reg[18]_0 ;
- input \stage_1_data_r_reg[19]_0 ;
- input \stage_1_data_r_reg[20]_0 ;
- input \stage_1_data_r_reg[21]_0 ;
- input \stage_1_data_r_reg[22]_0 ;
- input \stage_1_data_r_reg[23]_0 ;
- input \stage_1_data_r_reg[24]_0 ;
- input \stage_1_data_r_reg[25]_0 ;
- input \stage_1_data_r_reg[26]_0 ;
- input \stage_1_data_r_reg[27]_0 ;
- input \stage_1_data_r_reg[28]_0 ;
- input \stage_1_data_r_reg[29]_0 ;
- input \stage_1_data_r_reg[30]_0 ;
- input \stage_1_data_r_reg[31]_0 ;
- input [1:0]Q;
-
- wire BARREL_SHIFTER_CONTROL_Buffer;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [0:0]M_AXI_UFC_RX_TKEEP;
- wire M_AXI_UFC_RX_TLAST;
- wire M_AXI_UFC_RX_TVALID;
- wire [1:0]Q;
- wire RESET;
- wire [0:31]SHIFTED_DATA_Buffer;
- wire UFC_EOF_N_Buffer;
- wire [1:0]UFC_OUTPUT_SELECT_Buffer;
- wire [0:0]UFC_RX_REM_Buffer;
- wire UFC_RX_SRC_RDY_N_Buffer;
- wire UFC_SRC_RDY_N_Buffer;
- wire UFC_START;
- wire [2:5]UFC_STORAGE_SELECT_Buffer;
- wire [0:1]barrel_shifted_count_r;
- wire barrel_shifter_control_i;
- wire rx_ufc_eof;
- wire [31:0]\stage_1_data_r_reg[0]_0 ;
- wire \stage_1_data_r_reg[0]_1 ;
- wire \stage_1_data_r_reg[10]_0 ;
- wire \stage_1_data_r_reg[11]_0 ;
- wire \stage_1_data_r_reg[12]_0 ;
- wire \stage_1_data_r_reg[13]_0 ;
- wire \stage_1_data_r_reg[14]_0 ;
- wire \stage_1_data_r_reg[15]_0 ;
- wire \stage_1_data_r_reg[16]_0 ;
- wire \stage_1_data_r_reg[17]_0 ;
- wire \stage_1_data_r_reg[18]_0 ;
- wire \stage_1_data_r_reg[19]_0 ;
- wire \stage_1_data_r_reg[1]_0 ;
- wire \stage_1_data_r_reg[20]_0 ;
- wire \stage_1_data_r_reg[21]_0 ;
- wire \stage_1_data_r_reg[22]_0 ;
- wire \stage_1_data_r_reg[23]_0 ;
- wire \stage_1_data_r_reg[24]_0 ;
- wire \stage_1_data_r_reg[25]_0 ;
- wire \stage_1_data_r_reg[26]_0 ;
- wire \stage_1_data_r_reg[27]_0 ;
- wire \stage_1_data_r_reg[28]_0 ;
- wire \stage_1_data_r_reg[29]_0 ;
- wire \stage_1_data_r_reg[2]_0 ;
- wire \stage_1_data_r_reg[30]_0 ;
- wire \stage_1_data_r_reg[31]_0 ;
- wire \stage_1_data_r_reg[3]_0 ;
- wire \stage_1_data_r_reg[4]_0 ;
- wire \stage_1_data_r_reg[5]_0 ;
- wire \stage_1_data_r_reg[6]_0 ;
- wire \stage_1_data_r_reg[7]_0 ;
- wire \stage_1_data_r_reg[8]_0 ;
- wire \stage_1_data_r_reg[9]_0 ;
- wire stage_1_ufc_start_r;
- wire [1:1]storage_count_2x_c;
- wire ufc_barrel_shifter_i_n_32;
- wire ufc_barrel_shifter_i_n_33;
- wire ufc_barrel_shifter_i_n_34;
- wire ufc_barrel_shifter_i_n_35;
- wire ufc_barrel_shifter_i_n_36;
- wire ufc_barrel_shifter_i_n_37;
- wire ufc_barrel_shifter_i_n_38;
- wire ufc_barrel_shifter_i_n_39;
- wire ufc_barrel_shifter_i_n_40;
- wire ufc_barrel_shifter_i_n_41;
- wire ufc_barrel_shifter_i_n_42;
- wire ufc_barrel_shifter_i_n_43;
- wire ufc_barrel_shifter_i_n_44;
- wire ufc_barrel_shifter_i_n_45;
- wire ufc_barrel_shifter_i_n_46;
- wire ufc_barrel_shifter_i_n_47;
- wire ufc_sideband_output_i_n_0;
- wire ufc_storage_count_control_i_n_0;
- wire ufc_storage_count_control_i_n_1;
- wire ufc_storage_count_control_i_n_3;
- wire ufc_storage_count_control_i_n_4;
- wire ufc_storage_count_control_i_n_5;
- wire ufc_storage_count_control_i_n_6;
- wire ufc_storage_count_control_i_n_7;
- wire ufc_storage_mux_i_n_0;
- wire ufc_storage_mux_i_n_1;
- wire ufc_storage_mux_i_n_10;
- wire ufc_storage_mux_i_n_11;
- wire ufc_storage_mux_i_n_12;
- wire ufc_storage_mux_i_n_13;
- wire ufc_storage_mux_i_n_14;
- wire ufc_storage_mux_i_n_15;
- wire ufc_storage_mux_i_n_16;
- wire ufc_storage_mux_i_n_17;
- wire ufc_storage_mux_i_n_18;
- wire ufc_storage_mux_i_n_19;
- wire ufc_storage_mux_i_n_2;
- wire ufc_storage_mux_i_n_20;
- wire ufc_storage_mux_i_n_21;
- wire ufc_storage_mux_i_n_22;
- wire ufc_storage_mux_i_n_23;
- wire ufc_storage_mux_i_n_24;
- wire ufc_storage_mux_i_n_25;
- wire ufc_storage_mux_i_n_26;
- wire ufc_storage_mux_i_n_27;
- wire ufc_storage_mux_i_n_28;
- wire ufc_storage_mux_i_n_29;
- wire ufc_storage_mux_i_n_3;
- wire ufc_storage_mux_i_n_30;
- wire ufc_storage_mux_i_n_31;
- wire ufc_storage_mux_i_n_4;
- wire ufc_storage_mux_i_n_5;
- wire ufc_storage_mux_i_n_6;
- wire ufc_storage_mux_i_n_7;
- wire ufc_storage_mux_i_n_8;
- wire ufc_storage_mux_i_n_9;
- wire \ufc_storage_switch_control_i/_n_0 ;
- wire ufc_storage_switch_control_i_n_0;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair213" *)
- LUT2 #(
- .INIT(4'hE))
- \M_AXI_UFC_RX_TKEEP[3]_INST_0
- (.I0(rx_ufc_eof),
- .I1(UFC_RX_REM_Buffer),
- .O(M_AXI_UFC_RX_TKEEP));
- (* SOFT_HLUTNM = "soft_lutpair213" *)
- LUT1 #(
- .INIT(2'h1))
- M_AXI_UFC_RX_TLAST_INST_0
- (.I0(rx_ufc_eof),
- .O(M_AXI_UFC_RX_TLAST));
- LUT1 #(
- .INIT(2'h1))
- M_AXI_UFC_RX_TVALID_INST_0
- (.I0(UFC_RX_SRC_RDY_N_Buffer),
- .O(M_AXI_UFC_RX_TVALID));
- FDRE UFC_RX_EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_EOF_N_Buffer),
- .Q(rx_ufc_eof),
- .R(1'b0));
- FDRE \UFC_RX_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(ufc_sideband_output_i_n_0),
- .Q(UFC_RX_REM_Buffer),
- .R(1'b0));
- FDSE UFC_RX_SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_SRC_RDY_N_Buffer),
- .Q(UFC_RX_SRC_RDY_N_Buffer),
- .S(RESET));
- FDRE \stage_1_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[0]_1 ),
- .Q(\stage_1_data_r_reg[0]_0 [31]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[10]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [21]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[11]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [20]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[12]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [19]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[13]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [18]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[14]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [17]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[15]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [16]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[16]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [15]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[17]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [14]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[18]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [13]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[19]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [12]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[1]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [30]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[20]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [11]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[21]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [10]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[22]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [9]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[23]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [8]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[24]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [7]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[25]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [6]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[26]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [5]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[27]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [4]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[28]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [3]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[29]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [2]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[2]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [29]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[30]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[31]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[3]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [28]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[4]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [27]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[5]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [26]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[6]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [25]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[7]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [24]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[8]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [23]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[9]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [22]),
- .R(1'b0));
- FDRE stage_1_ufc_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_START),
- .Q(stage_1_ufc_start_r),
- .R(RESET));
- east_channel_east_channel_UFC_BARREL_SHIFTER_CONTROL ufc_barrel_shifter_control_i
- (.BARREL_SHIFTER_CONTROL_Buffer(BARREL_SHIFTER_CONTROL_Buffer),
- .barrel_shifter_control_i(barrel_shifter_control_i),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_BARREL_SHIFTER ufc_barrel_shifter_i
- (.BARREL_SHIFTER_CONTROL_Buffer(BARREL_SHIFTER_CONTROL_Buffer),
- .\MUXED_DATA_Buffer_reg[16] (ufc_storage_mux_i_n_16),
- .\MUXED_DATA_Buffer_reg[17] (ufc_storage_mux_i_n_17),
- .\MUXED_DATA_Buffer_reg[18] (ufc_storage_mux_i_n_18),
- .\MUXED_DATA_Buffer_reg[19] (ufc_storage_mux_i_n_19),
- .\MUXED_DATA_Buffer_reg[20] (ufc_storage_mux_i_n_20),
- .\MUXED_DATA_Buffer_reg[21] (ufc_storage_mux_i_n_21),
- .\MUXED_DATA_Buffer_reg[22] (ufc_storage_mux_i_n_22),
- .\MUXED_DATA_Buffer_reg[23] (ufc_storage_mux_i_n_23),
- .\MUXED_DATA_Buffer_reg[24] (ufc_storage_mux_i_n_24),
- .\MUXED_DATA_Buffer_reg[25] (ufc_storage_mux_i_n_25),
- .\MUXED_DATA_Buffer_reg[26] (ufc_storage_mux_i_n_26),
- .\MUXED_DATA_Buffer_reg[27] (ufc_storage_mux_i_n_27),
- .\MUXED_DATA_Buffer_reg[28] (ufc_storage_mux_i_n_28),
- .\MUXED_DATA_Buffer_reg[29] (ufc_storage_mux_i_n_29),
- .\MUXED_DATA_Buffer_reg[30] (ufc_storage_mux_i_n_30),
- .\MUXED_DATA_Buffer_reg[31] (ufc_storage_mux_i_n_31),
- .SHIFTED_DATA_Buffer(SHIFTED_DATA_Buffer),
- .\SHIFTED_DATA_Buffer_reg[0]_0 (ufc_barrel_shifter_i_n_47),
- .\SHIFTED_DATA_Buffer_reg[0]_1 (\stage_1_data_r_reg[0]_0 ),
- .\SHIFTED_DATA_Buffer_reg[10]_0 (ufc_barrel_shifter_i_n_37),
- .\SHIFTED_DATA_Buffer_reg[11]_0 (ufc_barrel_shifter_i_n_36),
- .\SHIFTED_DATA_Buffer_reg[12]_0 (ufc_barrel_shifter_i_n_35),
- .\SHIFTED_DATA_Buffer_reg[13]_0 (ufc_barrel_shifter_i_n_34),
- .\SHIFTED_DATA_Buffer_reg[14]_0 (ufc_barrel_shifter_i_n_33),
- .\SHIFTED_DATA_Buffer_reg[15]_0 (ufc_barrel_shifter_i_n_32),
- .\SHIFTED_DATA_Buffer_reg[1]_0 (ufc_barrel_shifter_i_n_46),
- .\SHIFTED_DATA_Buffer_reg[2]_0 (ufc_barrel_shifter_i_n_45),
- .\SHIFTED_DATA_Buffer_reg[3]_0 (ufc_barrel_shifter_i_n_44),
- .\SHIFTED_DATA_Buffer_reg[4]_0 (ufc_barrel_shifter_i_n_43),
- .\SHIFTED_DATA_Buffer_reg[5]_0 (ufc_barrel_shifter_i_n_42),
- .\SHIFTED_DATA_Buffer_reg[6]_0 (ufc_barrel_shifter_i_n_41),
- .\SHIFTED_DATA_Buffer_reg[7]_0 (ufc_barrel_shifter_i_n_40),
- .\SHIFTED_DATA_Buffer_reg[8]_0 (ufc_barrel_shifter_i_n_39),
- .\SHIFTED_DATA_Buffer_reg[9]_0 (ufc_barrel_shifter_i_n_38),
- .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer[0]),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_OUTPUT_MUX ufc_output_mux_i
- (.D({ufc_storage_mux_i_n_0,ufc_storage_mux_i_n_1,ufc_storage_mux_i_n_2,ufc_storage_mux_i_n_3,ufc_storage_mux_i_n_4,ufc_storage_mux_i_n_5,ufc_storage_mux_i_n_6,ufc_storage_mux_i_n_7,ufc_storage_mux_i_n_8,ufc_storage_mux_i_n_9,ufc_storage_mux_i_n_10,ufc_storage_mux_i_n_11,ufc_storage_mux_i_n_12,ufc_storage_mux_i_n_13,ufc_storage_mux_i_n_14,ufc_storage_mux_i_n_15}),
- .\MUXED_DATA_Buffer_reg[16]_0 (ufc_barrel_shifter_i_n_47),
- .\MUXED_DATA_Buffer_reg[17]_0 (ufc_barrel_shifter_i_n_46),
- .\MUXED_DATA_Buffer_reg[18]_0 (ufc_barrel_shifter_i_n_45),
- .\MUXED_DATA_Buffer_reg[19]_0 (ufc_barrel_shifter_i_n_44),
- .\MUXED_DATA_Buffer_reg[20]_0 (ufc_barrel_shifter_i_n_43),
- .\MUXED_DATA_Buffer_reg[21]_0 (ufc_barrel_shifter_i_n_42),
- .\MUXED_DATA_Buffer_reg[22]_0 (ufc_barrel_shifter_i_n_41),
- .\MUXED_DATA_Buffer_reg[23]_0 (ufc_barrel_shifter_i_n_40),
- .\MUXED_DATA_Buffer_reg[24]_0 (ufc_barrel_shifter_i_n_39),
- .\MUXED_DATA_Buffer_reg[25]_0 (ufc_barrel_shifter_i_n_38),
- .\MUXED_DATA_Buffer_reg[26]_0 (ufc_barrel_shifter_i_n_37),
- .\MUXED_DATA_Buffer_reg[27]_0 (ufc_barrel_shifter_i_n_36),
- .\MUXED_DATA_Buffer_reg[28]_0 (ufc_barrel_shifter_i_n_35),
- .\MUXED_DATA_Buffer_reg[29]_0 (ufc_barrel_shifter_i_n_34),
- .\MUXED_DATA_Buffer_reg[30]_0 (ufc_barrel_shifter_i_n_33),
- .\MUXED_DATA_Buffer_reg[31]_0 (ufc_barrel_shifter_i_n_32),
- .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
- .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer[1]),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_OUTPUT_SWITCH_CONTROL ufc_output_switch_control_i
- (.Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
- .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer),
- .\UFC_OUTPUT_SELECT_Buffer_reg[4]_0 (ufc_storage_count_control_i_n_6),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_SIDEBAND_OUTPUT ufc_sideband_output_i
- (.RESET(RESET),
- .UFC_EOF_N_Buffer(UFC_EOF_N_Buffer),
- .UFC_EOF_N_Buffer_reg_0(ufc_storage_count_control_i_n_0),
- .\UFC_REM_Buffer_reg[0]_0 (ufc_sideband_output_i_n_0),
- .\UFC_REM_Buffer_reg[0]_1 (ufc_storage_count_control_i_n_7),
- .UFC_SRC_RDY_N_Buffer(UFC_SRC_RDY_N_Buffer),
- .UFC_SRC_RDY_N_Buffer_reg_0(ufc_storage_count_control_i_n_6),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_STORAGE_COUNT_CONTROL ufc_storage_count_control_i
- (.D(ufc_storage_count_control_i_n_5),
- .Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
- .RESET(RESET),
- .UFC_EOF_N_Buffer_reg({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
- .stage_1_ufc_start_r(stage_1_ufc_start_r),
- .stage_1_ufc_start_r_reg(ufc_storage_count_control_i_n_0),
- .stage_1_ufc_start_r_reg_0(ufc_storage_count_control_i_n_7),
- .\storage_count_r_reg[0]_0 (ufc_storage_count_control_i_n_6),
- .\storage_count_r_reg[1]_0 (ufc_storage_count_control_i_n_3),
- .\storage_count_r_reg[1]_1 (ufc_storage_count_control_i_n_4),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_STORAGE_MUX ufc_storage_mux_i
- (.D({ufc_storage_mux_i_n_0,ufc_storage_mux_i_n_1,ufc_storage_mux_i_n_2,ufc_storage_mux_i_n_3,ufc_storage_mux_i_n_4,ufc_storage_mux_i_n_5,ufc_storage_mux_i_n_6,ufc_storage_mux_i_n_7,ufc_storage_mux_i_n_8,ufc_storage_mux_i_n_9,ufc_storage_mux_i_n_10,ufc_storage_mux_i_n_11,ufc_storage_mux_i_n_12,ufc_storage_mux_i_n_13,ufc_storage_mux_i_n_14,ufc_storage_mux_i_n_15}),
- .\MUXED_DATA_Buffer_reg[0]_0 (ufc_storage_switch_control_i_n_0),
- .\MUXED_DATA_Buffer_reg[16]_0 (ufc_storage_mux_i_n_16),
- .\MUXED_DATA_Buffer_reg[17]_0 (ufc_storage_mux_i_n_17),
- .\MUXED_DATA_Buffer_reg[18]_0 (ufc_storage_mux_i_n_18),
- .\MUXED_DATA_Buffer_reg[19]_0 (ufc_storage_mux_i_n_19),
- .\MUXED_DATA_Buffer_reg[20]_0 (ufc_storage_mux_i_n_20),
- .\MUXED_DATA_Buffer_reg[21]_0 (ufc_storage_mux_i_n_21),
- .\MUXED_DATA_Buffer_reg[22]_0 (ufc_storage_mux_i_n_22),
- .\MUXED_DATA_Buffer_reg[23]_0 (ufc_storage_mux_i_n_23),
- .\MUXED_DATA_Buffer_reg[24]_0 (ufc_storage_mux_i_n_24),
- .\MUXED_DATA_Buffer_reg[25]_0 (ufc_storage_mux_i_n_25),
- .\MUXED_DATA_Buffer_reg[26]_0 (ufc_storage_mux_i_n_26),
- .\MUXED_DATA_Buffer_reg[27]_0 (ufc_storage_mux_i_n_27),
- .\MUXED_DATA_Buffer_reg[28]_0 (ufc_storage_mux_i_n_28),
- .\MUXED_DATA_Buffer_reg[29]_0 (ufc_storage_mux_i_n_29),
- .\MUXED_DATA_Buffer_reg[30]_0 (ufc_storage_mux_i_n_30),
- .\MUXED_DATA_Buffer_reg[31]_0 (ufc_storage_mux_i_n_31),
- .SHIFTED_DATA_Buffer(SHIFTED_DATA_Buffer),
- .UFC_STORAGE_SELECT_Buffer({UFC_STORAGE_SELECT_Buffer[2],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[5]}),
- .user_clk(user_clk));
- east_channel_east_channel_UFC_STORAGE_SWITCH_CONTROL ufc_storage_switch_control_i
- (.D(ufc_storage_count_control_i_n_5),
- .Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
- .\UFC_STORAGE_SELECT_Buffer_reg[0]_0 (ufc_storage_switch_control_i_n_0),
- .\UFC_STORAGE_SELECT_Buffer_reg[0]_1 (ufc_storage_count_control_i_n_3),
- .\UFC_STORAGE_SELECT_Buffer_reg[1]_0 (ufc_storage_count_control_i_n_4),
- .\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ({UFC_STORAGE_SELECT_Buffer[2],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[5]}),
- .\UFC_STORAGE_SELECT_Buffer_reg[4]_0 (\ufc_storage_switch_control_i/_n_0 ),
- .\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
- .stage_1_ufc_start_r(stage_1_ufc_start_r),
- .user_clk(user_clk));
- LUT1 #(
- .INIT(2'h1))
- \ufc_storage_switch_control_i/
- (.I0(ufc_storage_count_control_i_n_1),
- .O(\ufc_storage_switch_control_i/_n_0 ));
- east_channel_east_channel_VALID_DATA_COUNTER ufc_valid_data_counter
- (.\COUNT_Buffer_reg[0]_0 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
- .Q(Q),
- .RESET(RESET),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SCRAMBLER" *)
-module east_channel_east_channel_SCRAMBLER
- (SS,
- Q,
- \DOUT_reg[15]_0 ,
- gen_v_r2,
- reset_lanes_i,
- \lfsr_reg[15]_0 ,
- clear_nxt2,
- E,
- user_clk,
- D);
- output [0:0]SS;
- output [15:0]Q;
- output [15:0]\DOUT_reg[15]_0 ;
- input gen_v_r2;
- input reset_lanes_i;
- input \lfsr_reg[15]_0 ;
- input clear_nxt2;
- input [0:0]E;
- input user_clk;
- input [15:0]D;
-
- wire [15:0]D;
- wire [15:0]\DOUT_reg[15]_0 ;
- wire [0:0]E;
- wire [15:0]Q;
- wire [0:0]SS;
- wire clear_nxt2;
- wire gen_v_r2;
- wire [12:3]lfsrNext;
- wire \lfsr_reg[15]_0 ;
- wire reset_lanes_i;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(D[0]),
- .Q(\DOUT_reg[15]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(D[10]),
- .Q(\DOUT_reg[15]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(D[11]),
- .Q(\DOUT_reg[15]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(D[12]),
- .Q(\DOUT_reg[15]_0 [12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(D[13]),
- .Q(\DOUT_reg[15]_0 [13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(D[14]),
- .Q(\DOUT_reg[15]_0 [14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(D[15]),
- .Q(\DOUT_reg[15]_0 [15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(D[1]),
- .Q(\DOUT_reg[15]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(D[2]),
- .Q(\DOUT_reg[15]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(D[3]),
- .Q(\DOUT_reg[15]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(D[4]),
- .Q(\DOUT_reg[15]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(D[5]),
- .Q(\DOUT_reg[15]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(D[6]),
- .Q(\DOUT_reg[15]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(D[7]),
- .Q(\DOUT_reg[15]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(D[8]),
- .Q(\DOUT_reg[15]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(D[9]),
- .Q(\DOUT_reg[15]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- LUT4 #(
- .INIT(16'hFFEF))
- \lfsr[15]_i_1__2
- (.I0(gen_v_r2),
- .I1(reset_lanes_i),
- .I2(\lfsr_reg[15]_0 ),
- .I3(clear_nxt2),
- .O(SS));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SCRAMBLER" *)
-module east_channel_east_channel_SCRAMBLER_23
- (Q,
- \DOUT_reg[15]_0 ,
- SS,
- \DOUT_reg[0]_0 ,
- user_clk,
- \DOUT_reg[15]_1 );
- output [15:0]Q;
- output [15:0]\DOUT_reg[15]_0 ;
- input [0:0]SS;
- input [0:0]\DOUT_reg[0]_0 ;
- input user_clk;
- input [15:0]\DOUT_reg[15]_1 ;
-
- wire [0:0]\DOUT_reg[0]_0 ;
- wire [15:0]\DOUT_reg[15]_0 ;
- wire [15:0]\DOUT_reg[15]_1 ;
- wire [15:0]Q;
- wire [0:0]SS;
- wire [12:3]lfsrNext;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [0]),
- .Q(\DOUT_reg[15]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [10]),
- .Q(\DOUT_reg[15]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [11]),
- .Q(\DOUT_reg[15]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [12]),
- .Q(\DOUT_reg[15]_0 [12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [13]),
- .Q(\DOUT_reg[15]_0 [13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [14]),
- .Q(\DOUT_reg[15]_0 [14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [15]),
- .Q(\DOUT_reg[15]_0 [15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [1]),
- .Q(\DOUT_reg[15]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [2]),
- .Q(\DOUT_reg[15]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [3]),
- .Q(\DOUT_reg[15]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [4]),
- .Q(\DOUT_reg[15]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [5]),
- .Q(\DOUT_reg[15]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [6]),
- .Q(\DOUT_reg[15]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [7]),
- .Q(\DOUT_reg[15]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [8]),
- .Q(\DOUT_reg[15]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [9]),
- .Q(\DOUT_reg[15]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1__0
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1__0
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1__0
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1__0
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1__0
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1__0
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1__0
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1__0
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1__0
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1__0
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SCRAMBLER" *)
-module east_channel_east_channel_SCRAMBLER_25
- (Q,
- rx_pe_data_striped_i,
- \stage_1_data_r_reg[0] ,
- \stage_1_data_r_reg[15] ,
- \stage_1_data_r_reg[11] ,
- \stage_1_data_r_reg[10] ,
- \stage_1_data_r_reg[9] ,
- \stage_1_data_r_reg[8] ,
- SS,
- E,
- user_clk,
- \DOUT_reg[15]_0 );
- output [15:0]Q;
- output [15:0]rx_pe_data_striped_i;
- input [11:0]\stage_1_data_r_reg[0] ;
- input [0:0]\stage_1_data_r_reg[15] ;
- input \stage_1_data_r_reg[11] ;
- input \stage_1_data_r_reg[10] ;
- input \stage_1_data_r_reg[9] ;
- input \stage_1_data_r_reg[8] ;
- input [0:0]SS;
- input [0:0]E;
- input user_clk;
- input [15:0]\DOUT_reg[15]_0 ;
-
- wire [15:0]DOUT;
- wire [15:0]\DOUT_reg[15]_0 ;
- wire [0:0]E;
- wire [15:0]Q;
- wire [0:0]SS;
- wire [12:3]lfsrNext;
- wire [15:0]rx_pe_data_striped_i;
- wire [11:0]\stage_1_data_r_reg[0] ;
- wire \stage_1_data_r_reg[10] ;
- wire \stage_1_data_r_reg[11] ;
- wire [0:0]\stage_1_data_r_reg[15] ;
- wire \stage_1_data_r_reg[8] ;
- wire \stage_1_data_r_reg[9] ;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [0]),
- .Q(DOUT[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [10]),
- .Q(DOUT[10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [11]),
- .Q(DOUT[11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [12]),
- .Q(DOUT[12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [13]),
- .Q(DOUT[13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [14]),
- .Q(DOUT[14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [15]),
- .Q(DOUT[15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [1]),
- .Q(DOUT[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [2]),
- .Q(DOUT[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [3]),
- .Q(DOUT[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [4]),
- .Q(DOUT[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [5]),
- .Q(DOUT[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [6]),
- .Q(DOUT[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [7]),
- .Q(DOUT[7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [8]),
- .Q(DOUT[8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [9]),
- .Q(DOUT[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[0]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [11]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[15]),
- .O(rx_pe_data_striped_i[15]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[10]_srl2_i_1
- (.I0(\stage_1_data_r_reg[10] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[5]),
- .O(rx_pe_data_striped_i[5]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[11]_srl2_i_1
- (.I0(\stage_1_data_r_reg[11] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[4]),
- .O(rx_pe_data_striped_i[4]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[12]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [3]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[3]),
- .O(rx_pe_data_striped_i[3]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[13]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [2]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[2]),
- .O(rx_pe_data_striped_i[2]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[14]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [1]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[1]),
- .O(rx_pe_data_striped_i[1]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[15]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [0]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[0]),
- .O(rx_pe_data_striped_i[0]));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[1]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [10]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[14]),
- .O(rx_pe_data_striped_i[14]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[2]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [9]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[13]),
- .O(rx_pe_data_striped_i[13]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[3]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [8]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[12]),
- .O(rx_pe_data_striped_i[12]));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[4]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [7]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[11]),
- .O(rx_pe_data_striped_i[11]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[5]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [6]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[10]),
- .O(rx_pe_data_striped_i[10]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[6]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [5]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[9]),
- .O(rx_pe_data_striped_i[9]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[7]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [4]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[8]),
- .O(rx_pe_data_striped_i[8]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[8]_srl2_i_1
- (.I0(\stage_1_data_r_reg[8] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[7]),
- .O(rx_pe_data_striped_i[7]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[9]_srl2_i_1
- (.I0(\stage_1_data_r_reg[9] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[6]),
- .O(rx_pe_data_striped_i[6]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1__1
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1__1
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1__1
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1__1
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1__1
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1__1
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1__1
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1__1
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1__1
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1__1
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SCRAMBLER" *)
-module east_channel_east_channel_SCRAMBLER_26
- (Q,
- rx_pe_data_striped_i,
- \stage_1_data_r_reg[16] ,
- \stage_1_data_r_reg[31] ,
- \stage_1_data_r_reg[27] ,
- \stage_1_data_r_reg[26] ,
- \stage_1_data_r_reg[25] ,
- \stage_1_data_r_reg[24] ,
- SS,
- \DOUT_reg[0]_0 ,
- user_clk,
- D);
- output [15:0]Q;
- output [15:0]rx_pe_data_striped_i;
- input [11:0]\stage_1_data_r_reg[16] ;
- input [0:0]\stage_1_data_r_reg[31] ;
- input \stage_1_data_r_reg[27] ;
- input \stage_1_data_r_reg[26] ;
- input \stage_1_data_r_reg[25] ;
- input \stage_1_data_r_reg[24] ;
- input [0:0]SS;
- input [0:0]\DOUT_reg[0]_0 ;
- input user_clk;
- input [15:0]D;
-
- wire [15:0]D;
- wire [0:0]\DOUT_reg[0]_0 ;
- wire \DOUT_reg_n_0_[0] ;
- wire \DOUT_reg_n_0_[10] ;
- wire \DOUT_reg_n_0_[11] ;
- wire \DOUT_reg_n_0_[12] ;
- wire \DOUT_reg_n_0_[13] ;
- wire \DOUT_reg_n_0_[14] ;
- wire \DOUT_reg_n_0_[15] ;
- wire \DOUT_reg_n_0_[1] ;
- wire \DOUT_reg_n_0_[2] ;
- wire \DOUT_reg_n_0_[3] ;
- wire \DOUT_reg_n_0_[4] ;
- wire \DOUT_reg_n_0_[5] ;
- wire \DOUT_reg_n_0_[6] ;
- wire \DOUT_reg_n_0_[7] ;
- wire \DOUT_reg_n_0_[8] ;
- wire \DOUT_reg_n_0_[9] ;
- wire [15:0]Q;
- wire [0:0]SS;
- wire [12:3]lfsrNext;
- wire [15:0]rx_pe_data_striped_i;
- wire [11:0]\stage_1_data_r_reg[16] ;
- wire \stage_1_data_r_reg[24] ;
- wire \stage_1_data_r_reg[25] ;
- wire \stage_1_data_r_reg[26] ;
- wire \stage_1_data_r_reg[27] ;
- wire [0:0]\stage_1_data_r_reg[31] ;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[0]),
- .Q(\DOUT_reg_n_0_[0] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[10]),
- .Q(\DOUT_reg_n_0_[10] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[11]),
- .Q(\DOUT_reg_n_0_[11] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[12]),
- .Q(\DOUT_reg_n_0_[12] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[13]),
- .Q(\DOUT_reg_n_0_[13] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[14]),
- .Q(\DOUT_reg_n_0_[14] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[15]),
- .Q(\DOUT_reg_n_0_[15] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[1]),
- .Q(\DOUT_reg_n_0_[1] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[2]),
- .Q(\DOUT_reg_n_0_[2] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[3]),
- .Q(\DOUT_reg_n_0_[3] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[4]),
- .Q(\DOUT_reg_n_0_[4] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[5]),
- .Q(\DOUT_reg_n_0_[5] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[6]),
- .Q(\DOUT_reg_n_0_[6] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[7]),
- .Q(\DOUT_reg_n_0_[7] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[8]),
- .Q(\DOUT_reg_n_0_[8] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[9]),
- .Q(\DOUT_reg_n_0_[9] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[16]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [11]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[15] ),
- .O(rx_pe_data_striped_i[15]));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[17]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [10]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[14] ),
- .O(rx_pe_data_striped_i[14]));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[18]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [9]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[13] ),
- .O(rx_pe_data_striped_i[13]));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[19]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [8]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[12] ),
- .O(rx_pe_data_striped_i[12]));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[20]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [7]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[11] ),
- .O(rx_pe_data_striped_i[11]));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[21]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [6]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[10] ),
- .O(rx_pe_data_striped_i[10]));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[22]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [5]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[9] ),
- .O(rx_pe_data_striped_i[9]));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[23]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [4]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[8] ),
- .O(rx_pe_data_striped_i[8]));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[24]_srl2_i_1
- (.I0(\stage_1_data_r_reg[24] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[7] ),
- .O(rx_pe_data_striped_i[7]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[25]_srl2_i_1
- (.I0(\stage_1_data_r_reg[25] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[6] ),
- .O(rx_pe_data_striped_i[6]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[26]_srl2_i_1
- (.I0(\stage_1_data_r_reg[26] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[5] ),
- .O(rx_pe_data_striped_i[5]));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[27]_srl2_i_1
- (.I0(\stage_1_data_r_reg[27] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[4] ),
- .O(rx_pe_data_striped_i[4]));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[28]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [3]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[3] ),
- .O(rx_pe_data_striped_i[3]));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[29]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [2]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[2] ),
- .O(rx_pe_data_striped_i[2]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[30]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [1]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[1] ),
- .O(rx_pe_data_striped_i[1]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[31]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [0]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[0] ),
- .O(rx_pe_data_striped_i[0]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1__2
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1__2
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1__2
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1__2
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1__2
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1__2
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1__2
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1__2
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1__2
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1__2
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SCRAMBLER_TOP" *)
-module east_channel_east_channel_SCRAMBLER_TOP
- (Q,
- \lfsr_reg[15] ,
- TXDATA,
- \CHAR_IS_K_OUT_reg[3]_0 ,
- gen_cc_r,
- user_clk,
- gen_v_r2,
- reset_lanes_i,
- \lfsr_reg[15]_0 ,
- E,
- \DOUT_reg[0] ,
- BYPASS,
- \bypass_r_reg[0]_0 ,
- D,
- \data_nxt_reg[31]_0 ,
- \DOUT_reg[15] ,
- \CHAR_IS_K_OUT_reg[3]_1 );
- output [15:0]Q;
- output [15:0]\lfsr_reg[15] ;
- output [31:0]TXDATA;
- output [3:0]\CHAR_IS_K_OUT_reg[3]_0 ;
- input gen_cc_r;
- input user_clk;
- input gen_v_r2;
- input reset_lanes_i;
- input \lfsr_reg[15]_0 ;
- input [0:0]E;
- input [0:0]\DOUT_reg[0] ;
- input BYPASS;
- input \bypass_r_reg[0]_0 ;
- input [15:0]D;
- input [31:0]\data_nxt_reg[31]_0 ;
- input [15:0]\DOUT_reg[15] ;
- input [3:0]\CHAR_IS_K_OUT_reg[3]_1 ;
-
- wire BYPASS;
- wire [3:0]\CHAR_IS_K_OUT_reg[3]_0 ;
- wire [3:0]\CHAR_IS_K_OUT_reg[3]_1 ;
- wire [15:0]D;
- wire [15:0]DOUT;
- wire [0:0]\DOUT_reg[0] ;
- wire [15:0]\DOUT_reg[15] ;
- wire [0:0]E;
- wire [15:0]Q;
- wire [31:0]TXDATA;
- wire [1:0]bypass_r;
- wire \bypass_r_reg[0]_0 ;
- wire clear_nxt2;
- wire [31:0]data_nxt;
- wire [31:0]\data_nxt_reg[31]_0 ;
- wire east_channel_scrambler0_i_n_0;
- wire east_channel_scrambler1_i_n_16;
- wire east_channel_scrambler1_i_n_17;
- wire east_channel_scrambler1_i_n_18;
- wire east_channel_scrambler1_i_n_19;
- wire east_channel_scrambler1_i_n_20;
- wire east_channel_scrambler1_i_n_21;
- wire east_channel_scrambler1_i_n_22;
- wire east_channel_scrambler1_i_n_23;
- wire east_channel_scrambler1_i_n_24;
- wire east_channel_scrambler1_i_n_25;
- wire east_channel_scrambler1_i_n_26;
- wire east_channel_scrambler1_i_n_27;
- wire east_channel_scrambler1_i_n_28;
- wire east_channel_scrambler1_i_n_29;
- wire east_channel_scrambler1_i_n_30;
- wire east_channel_scrambler1_i_n_31;
- wire gen_cc_r;
- wire gen_v_r2;
- wire [15:0]\lfsr_reg[15] ;
- wire \lfsr_reg[15]_0 ;
- wire reset_lanes_i;
- wire user_clk;
-
- FDRE \CHAR_IS_K_OUT_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [0]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [0]),
- .R(1'b0));
- FDRE \CHAR_IS_K_OUT_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [1]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [1]),
- .R(1'b0));
- FDRE \CHAR_IS_K_OUT_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [2]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [2]),
- .R(1'b0));
- FDRE \CHAR_IS_K_OUT_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [3]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [3]),
- .R(1'b0));
- FDRE \bypass_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\bypass_r_reg[0]_0 ),
- .Q(bypass_r[0]),
- .R(1'b0));
- FDRE \bypass_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(BYPASS),
- .Q(bypass_r[1]),
- .R(1'b0));
- FDRE clear_nxt2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_cc_r),
- .Q(clear_nxt2),
- .R(1'b0));
- FDRE \data_nxt_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [0]),
- .Q(data_nxt[0]),
- .R(1'b0));
- FDRE \data_nxt_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [10]),
- .Q(data_nxt[10]),
- .R(1'b0));
- FDRE \data_nxt_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [11]),
- .Q(data_nxt[11]),
- .R(1'b0));
- FDRE \data_nxt_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [12]),
- .Q(data_nxt[12]),
- .R(1'b0));
- FDRE \data_nxt_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [13]),
- .Q(data_nxt[13]),
- .R(1'b0));
- FDRE \data_nxt_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [14]),
- .Q(data_nxt[14]),
- .R(1'b0));
- FDRE \data_nxt_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [15]),
- .Q(data_nxt[15]),
- .R(1'b0));
- FDRE \data_nxt_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [16]),
- .Q(data_nxt[16]),
- .R(1'b0));
- FDRE \data_nxt_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [17]),
- .Q(data_nxt[17]),
- .R(1'b0));
- FDRE \data_nxt_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [18]),
- .Q(data_nxt[18]),
- .R(1'b0));
- FDRE \data_nxt_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [19]),
- .Q(data_nxt[19]),
- .R(1'b0));
- FDRE \data_nxt_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [1]),
- .Q(data_nxt[1]),
- .R(1'b0));
- FDRE \data_nxt_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [20]),
- .Q(data_nxt[20]),
- .R(1'b0));
- FDRE \data_nxt_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [21]),
- .Q(data_nxt[21]),
- .R(1'b0));
- FDRE \data_nxt_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [22]),
- .Q(data_nxt[22]),
- .R(1'b0));
- FDRE \data_nxt_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [23]),
- .Q(data_nxt[23]),
- .R(1'b0));
- FDRE \data_nxt_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [24]),
- .Q(data_nxt[24]),
- .R(1'b0));
- FDRE \data_nxt_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [25]),
- .Q(data_nxt[25]),
- .R(1'b0));
- FDRE \data_nxt_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [26]),
- .Q(data_nxt[26]),
- .R(1'b0));
- FDRE \data_nxt_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [27]),
- .Q(data_nxt[27]),
- .R(1'b0));
- FDRE \data_nxt_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [28]),
- .Q(data_nxt[28]),
- .R(1'b0));
- FDRE \data_nxt_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [29]),
- .Q(data_nxt[29]),
- .R(1'b0));
- FDRE \data_nxt_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [2]),
- .Q(data_nxt[2]),
- .R(1'b0));
- FDRE \data_nxt_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [30]),
- .Q(data_nxt[30]),
- .R(1'b0));
- FDRE \data_nxt_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [31]),
- .Q(data_nxt[31]),
- .R(1'b0));
- FDRE \data_nxt_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [3]),
- .Q(data_nxt[3]),
- .R(1'b0));
- FDRE \data_nxt_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [4]),
- .Q(data_nxt[4]),
- .R(1'b0));
- FDRE \data_nxt_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [5]),
- .Q(data_nxt[5]),
- .R(1'b0));
- FDRE \data_nxt_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [6]),
- .Q(data_nxt[6]),
- .R(1'b0));
- FDRE \data_nxt_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [7]),
- .Q(data_nxt[7]),
- .R(1'b0));
- FDRE \data_nxt_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [8]),
- .Q(data_nxt[8]),
- .R(1'b0));
- FDRE \data_nxt_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [9]),
- .Q(data_nxt[9]),
- .R(1'b0));
- east_channel_east_channel_SCRAMBLER east_channel_scrambler0_i
- (.D(D),
- .\DOUT_reg[15]_0 (DOUT),
- .E(E),
- .Q(Q),
- .SS(east_channel_scrambler0_i_n_0),
- .clear_nxt2(clear_nxt2),
- .gen_v_r2(gen_v_r2),
- .\lfsr_reg[15]_0 (\lfsr_reg[15]_0 ),
- .reset_lanes_i(reset_lanes_i),
- .user_clk(user_clk));
- east_channel_east_channel_SCRAMBLER_23 east_channel_scrambler1_i
- (.\DOUT_reg[0]_0 (\DOUT_reg[0] ),
- .\DOUT_reg[15]_0 ({east_channel_scrambler1_i_n_16,east_channel_scrambler1_i_n_17,east_channel_scrambler1_i_n_18,east_channel_scrambler1_i_n_19,east_channel_scrambler1_i_n_20,east_channel_scrambler1_i_n_21,east_channel_scrambler1_i_n_22,east_channel_scrambler1_i_n_23,east_channel_scrambler1_i_n_24,east_channel_scrambler1_i_n_25,east_channel_scrambler1_i_n_26,east_channel_scrambler1_i_n_27,east_channel_scrambler1_i_n_28,east_channel_scrambler1_i_n_29,east_channel_scrambler1_i_n_30,east_channel_scrambler1_i_n_31}),
- .\DOUT_reg[15]_1 (\DOUT_reg[15] ),
- .Q(\lfsr_reg[15] ),
- .SS(east_channel_scrambler0_i_n_0),
- .user_clk(user_clk));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_19
- (.I0(data_nxt[7]),
- .I1(bypass_r[0]),
- .I2(DOUT[7]),
- .O(TXDATA[31]));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_20
- (.I0(data_nxt[6]),
- .I1(bypass_r[0]),
- .I2(DOUT[6]),
- .O(TXDATA[30]));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_21
- (.I0(data_nxt[5]),
- .I1(bypass_r[0]),
- .I2(DOUT[5]),
- .O(TXDATA[29]));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_22
- (.I0(data_nxt[4]),
- .I1(bypass_r[0]),
- .I2(DOUT[4]),
- .O(TXDATA[28]));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_23
- (.I0(data_nxt[3]),
- .I1(bypass_r[0]),
- .I2(DOUT[3]),
- .O(TXDATA[27]));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_24
- (.I0(data_nxt[2]),
- .I1(bypass_r[0]),
- .I2(DOUT[2]),
- .O(TXDATA[26]));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_25
- (.I0(data_nxt[1]),
- .I1(bypass_r[0]),
- .I2(DOUT[1]),
- .O(TXDATA[25]));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_26
- (.I0(data_nxt[0]),
- .I1(bypass_r[0]),
- .I2(DOUT[0]),
- .O(TXDATA[24]));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_27
- (.I0(data_nxt[15]),
- .I1(bypass_r[0]),
- .I2(DOUT[15]),
- .O(TXDATA[23]));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_28
- (.I0(data_nxt[14]),
- .I1(bypass_r[0]),
- .I2(DOUT[14]),
- .O(TXDATA[22]));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_29
- (.I0(data_nxt[13]),
- .I1(bypass_r[0]),
- .I2(DOUT[13]),
- .O(TXDATA[21]));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_30
- (.I0(data_nxt[12]),
- .I1(bypass_r[0]),
- .I2(DOUT[12]),
- .O(TXDATA[20]));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_31
- (.I0(data_nxt[11]),
- .I1(bypass_r[0]),
- .I2(DOUT[11]),
- .O(TXDATA[19]));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_32
- (.I0(data_nxt[10]),
- .I1(bypass_r[0]),
- .I2(DOUT[10]),
- .O(TXDATA[18]));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_33
- (.I0(data_nxt[9]),
- .I1(bypass_r[0]),
- .I2(DOUT[9]),
- .O(TXDATA[17]));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_34
- (.I0(data_nxt[8]),
- .I1(bypass_r[0]),
- .I2(DOUT[8]),
- .O(TXDATA[16]));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_35
- (.I0(data_nxt[23]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_24),
- .O(TXDATA[15]));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_36
- (.I0(data_nxt[22]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_25),
- .O(TXDATA[14]));
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_37
- (.I0(data_nxt[21]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_26),
- .O(TXDATA[13]));
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_38
- (.I0(data_nxt[20]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_27),
- .O(TXDATA[12]));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_39
- (.I0(data_nxt[19]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_28),
- .O(TXDATA[11]));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_40
- (.I0(data_nxt[18]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_29),
- .O(TXDATA[10]));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_41
- (.I0(data_nxt[17]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_30),
- .O(TXDATA[9]));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_42
- (.I0(data_nxt[16]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_31),
- .O(TXDATA[8]));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_43
- (.I0(data_nxt[31]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_16),
- .O(TXDATA[7]));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_44
- (.I0(data_nxt[30]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_17),
- .O(TXDATA[6]));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_45
- (.I0(data_nxt[29]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_18),
- .O(TXDATA[5]));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_46
- (.I0(data_nxt[28]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_19),
- .O(TXDATA[4]));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_47
- (.I0(data_nxt[27]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_20),
- .O(TXDATA[3]));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_48
- (.I0(data_nxt[26]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_21),
- .O(TXDATA[2]));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_49
- (.I0(data_nxt[25]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_22),
- .O(TXDATA[1]));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_50
- (.I0(data_nxt[24]),
- .I1(bypass_r[1]),
- .I2(east_channel_scrambler1_i_n_23),
- .O(TXDATA[0]));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SIDEBAND_OUTPUT" *)
-module east_channel_east_channel_SIDEBAND_OUTPUT
- (SRC_RDY_N_Buffer,
- SR,
- EOF_N_Buffer,
- stage_3_end_storage_r,
- FRAME_ERR_RESULT_Buffer,
- D,
- \RX_REM_Buffer_reg[0]_0 ,
- user_clk,
- EOF_N_Buffer_reg_0,
- end_storage_r0,
- FRAME_ERR_RESULT_Buffer0,
- stage_2_start_with_data_r,
- stage_2_pad_r,
- Q,
- \RX_REM_Buffer_reg[0]_1 ,
- std_bool6_in,
- stage_2_end_before_start_r,
- stage_2_frame_err_r,
- START_RX);
- output SRC_RDY_N_Buffer;
- output [0:0]SR;
- output EOF_N_Buffer;
- output stage_3_end_storage_r;
- output FRAME_ERR_RESULT_Buffer;
- output [0:0]D;
- output [1:0]\RX_REM_Buffer_reg[0]_0 ;
- input user_clk;
- input EOF_N_Buffer_reg_0;
- input end_storage_r0;
- input FRAME_ERR_RESULT_Buffer0;
- input stage_2_start_with_data_r;
- input stage_2_pad_r;
- input [0:0]Q;
- input [0:0]\RX_REM_Buffer_reg[0]_1 ;
- input std_bool6_in;
- input stage_2_end_before_start_r;
- input stage_2_frame_err_r;
- input START_RX;
-
- wire [0:0]D;
- wire EOF_N_Buffer;
- wire EOF_N_Buffer_reg_0;
- wire FRAME_ERR_RESULT_Buffer;
- wire FRAME_ERR_RESULT_Buffer0;
- wire [0:0]Q;
- wire [1:0]\RX_REM_Buffer_reg[0]_0 ;
- wire [0:0]\RX_REM_Buffer_reg[0]_1 ;
- wire [0:0]SR;
- wire SRC_RDY_N_Buffer;
- wire SRC_RDY_N_Buffer_i_2_n_0;
- wire START_RX;
- wire end_storage_r0;
- wire pad_storage_r;
- wire pad_storage_r_i_1_n_0;
- wire [1:0]rx_rem_c;
- wire stage_2_end_before_start_r;
- wire stage_2_frame_err_r;
- wire stage_2_pad_r;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire std_bool6_in;
- wire user_clk;
-
- FDRE EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(EOF_N_Buffer_reg_0),
- .Q(EOF_N_Buffer),
- .R(1'b0));
- FDRE FRAME_ERR_RESULT_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(FRAME_ERR_RESULT_Buffer0),
- .Q(FRAME_ERR_RESULT_Buffer),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair145" *)
- LUT4 #(
- .INIT(16'h1E0F))
- \RX_REM_Buffer[0]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(Q),
- .I3(\RX_REM_Buffer_reg[0]_1 ),
- .O(rx_rem_c[1]));
- LUT4 #(
- .INIT(16'h00EF))
- \RX_REM_Buffer[1]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(stage_2_pad_r),
- .I3(pad_storage_r),
- .O(rx_rem_c[0]));
- FDRE \RX_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_rem_c[1]),
- .Q(\RX_REM_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_REM_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_rem_c[0]),
- .Q(\RX_REM_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- SRC_RDY_N_Buffer_i_1
- (.I0(stage_2_frame_err_r),
- .I1(START_RX),
- .O(SR));
- LUT4 #(
- .INIT(16'h0145))
- SRC_RDY_N_Buffer_i_2
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(std_bool6_in),
- .I3(stage_2_end_before_start_r),
- .O(SRC_RDY_N_Buffer_i_2_n_0));
- FDSE SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(SRC_RDY_N_Buffer_i_2_n_0),
- .Q(SRC_RDY_N_Buffer),
- .S(SR));
- FDRE end_storage_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(end_storage_r0),
- .Q(stage_3_end_storage_r),
- .R(SR));
- LUT6 #(
- .INIT(64'hAAABBABBAAAAAAAA))
- pad_storage_r_i_1
- (.I0(stage_2_pad_r),
- .I1(stage_3_end_storage_r),
- .I2(stage_2_start_with_data_r),
- .I3(std_bool6_in),
- .I4(stage_2_end_before_start_r),
- .I5(pad_storage_r),
- .O(pad_storage_r_i_1_n_0));
- FDRE pad_storage_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(pad_storage_r_i_1_n_0),
- .Q(pad_storage_r),
- .R(SR));
- (* SOFT_HLUTNM = "soft_lutpair145" *)
- LUT4 #(
- .INIT(16'hE1F0))
- \storage_count_r[1]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(\RX_REM_Buffer_reg[0]_1 ),
- .I3(Q),
- .O(D));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_STANDARD_CC_MODULE" *)
-module east_channel_east_channel_STANDARD_CC_MODULE
- (WARN_CC,
- DO_CC_I,
- next_ufc_idle_c,
- DO_CC_reg_0,
- user_clk,
- ufc_idle_r_reg,
- S_AXI_UFC_TX_REQ);
- output WARN_CC;
- output DO_CC_I;
- output next_ufc_idle_c;
- input DO_CC_reg_0;
- input user_clk;
- input ufc_idle_r_reg;
- input S_AXI_UFC_TX_REQ;
-
- wire DO_CC_I;
- wire DO_CC_i_1_n_0;
- wire DO_CC_reg_0;
- wire S_AXI_UFC_TX_REQ;
- wire WARN_CC;
- wire WARN_CC_i_1_n_0;
- wire [5:5]cc_count_r;
- wire cc_idle_count_done_c;
- wire count_13d_flop_r_reg_r_n_0;
- wire \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ;
- wire \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ;
- wire \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ;
- wire count_13d_srl_r_reg_gate_n_0;
- wire count_13d_srl_r_reg_r_0_n_0;
- wire count_13d_srl_r_reg_r_1_n_0;
- wire count_13d_srl_r_reg_r_2_n_0;
- wire count_13d_srl_r_reg_r_3_n_0;
- wire count_13d_srl_r_reg_r_4_n_0;
- wire count_13d_srl_r_reg_r_5_n_0;
- wire count_13d_srl_r_reg_r_6_n_0;
- wire count_13d_srl_r_reg_r_7_n_0;
- wire count_13d_srl_r_reg_r_8_n_0;
- wire count_13d_srl_r_reg_r_9_n_0;
- wire count_13d_srl_r_reg_r_n_0;
- wire count_16d_flop_r;
- wire count_16d_flop_r_i_1_n_0;
- wire count_16d_srl_r0;
- wire \count_16d_srl_r_reg_n_0_[0] ;
- wire \count_16d_srl_r_reg_n_0_[10] ;
- wire \count_16d_srl_r_reg_n_0_[11] ;
- wire \count_16d_srl_r_reg_n_0_[12] ;
- wire \count_16d_srl_r_reg_n_0_[13] ;
- wire \count_16d_srl_r_reg_n_0_[14] ;
- wire \count_16d_srl_r_reg_n_0_[1] ;
- wire \count_16d_srl_r_reg_n_0_[2] ;
- wire \count_16d_srl_r_reg_n_0_[3] ;
- wire \count_16d_srl_r_reg_n_0_[4] ;
- wire \count_16d_srl_r_reg_n_0_[5] ;
- wire \count_16d_srl_r_reg_n_0_[6] ;
- wire \count_16d_srl_r_reg_n_0_[7] ;
- wire \count_16d_srl_r_reg_n_0_[8] ;
- wire \count_16d_srl_r_reg_n_0_[9] ;
- wire count_24d_flop_r;
- wire count_24d_flop_r_i_1_n_0;
- wire count_24d_srl_r0;
- wire \count_24d_srl_r_reg_n_0_[0] ;
- wire \count_24d_srl_r_reg_n_0_[10] ;
- wire \count_24d_srl_r_reg_n_0_[1] ;
- wire \count_24d_srl_r_reg_n_0_[2] ;
- wire \count_24d_srl_r_reg_n_0_[3] ;
- wire \count_24d_srl_r_reg_n_0_[4] ;
- wire \count_24d_srl_r_reg_n_0_[5] ;
- wire \count_24d_srl_r_reg_n_0_[6] ;
- wire \count_24d_srl_r_reg_n_0_[7] ;
- wire \count_24d_srl_r_reg_n_0_[8] ;
- wire \count_24d_srl_r_reg_n_0_[9] ;
- wire next_ufc_idle_c;
- wire [1:0]p_2_in;
- wire [2:2]p_3_out;
- wire \prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_n_0 ;
- wire \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2_n_0 ;
- wire prepare_count_r_reg_gate_n_0;
- wire reset_r;
- wire ufc_idle_r_reg;
- wire user_clk;
-
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- DO_CC_i_1
- (.I0(reset_r),
- .I1(p_2_in[1]),
- .I2(p_3_out),
- .I3(p_2_in[0]),
- .I4(cc_count_r),
- .O(DO_CC_i_1_n_0));
- FDRE DO_CC_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(DO_CC_i_1_n_0),
- .Q(DO_CC_I),
- .R(DO_CC_reg_0));
- LUT5 #(
- .INIT(32'h80FF8080))
- WARN_CC_i_1
- (.I0(\count_24d_srl_r_reg_n_0_[10] ),
- .I1(\count_16d_srl_r_reg_n_0_[14] ),
- .I2(count_16d_srl_r0),
- .I3(p_3_out),
- .I4(WARN_CC),
- .O(WARN_CC_i_1_n_0));
- FDRE WARN_CC_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(WARN_CC_i_1_n_0),
- .Q(WARN_CC),
- .R(DO_CC_reg_0));
- FDRE #(
- .INIT(1'b0))
- \cc_count_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out),
- .Q(p_2_in[1]),
- .R(DO_CC_reg_0));
- FDRE #(
- .INIT(1'b0))
- \cc_count_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_in[1]),
- .Q(p_2_in[0]),
- .R(DO_CC_reg_0));
- FDRE #(
- .INIT(1'b0))
- \cc_count_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_in[0]),
- .Q(cc_count_r),
- .R(DO_CC_reg_0));
- FDRE count_13d_flop_r_reg_r
- (.C(user_clk),
- .CE(1'b1),
- .D(1'b1),
- .Q(count_13d_flop_r_reg_r_n_0),
- .R(DO_CC_reg_0));
- FDRE \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9
- (.C(user_clk),
- .CE(1'b1),
- .D(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ),
- .Q(\count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ),
- .R(1'b0));
- FDRE \count_13d_srl_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_gate_n_0),
- .Q(count_16d_srl_r0),
- .R(DO_CC_reg_0));
- (* srl_bus_name = "U0/\standard_cc_module_i/count_13d_srl_r_reg " *)
- (* srl_name = "U0/\standard_cc_module_i/count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8 " *)
- SRL16E \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ),
- .Q(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair281" *)
- LUT2 #(
- .INIT(4'hE))
- \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1
- (.I0(count_16d_srl_r0),
- .I1(reset_r),
- .O(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- count_13d_srl_r_reg_gate
- (.I0(\count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ),
- .I1(count_13d_srl_r_reg_r_9_n_0),
- .O(count_13d_srl_r_reg_gate_n_0));
- FDRE count_13d_srl_r_reg_r
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_flop_r_reg_r_n_0),
- .Q(count_13d_srl_r_reg_r_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_0
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_n_0),
- .Q(count_13d_srl_r_reg_r_0_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_1
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_0_n_0),
- .Q(count_13d_srl_r_reg_r_1_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_2
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_1_n_0),
- .Q(count_13d_srl_r_reg_r_2_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_3
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_2_n_0),
- .Q(count_13d_srl_r_reg_r_3_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_4
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_3_n_0),
- .Q(count_13d_srl_r_reg_r_4_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_5
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_4_n_0),
- .Q(count_13d_srl_r_reg_r_5_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_6
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_5_n_0),
- .Q(count_13d_srl_r_reg_r_6_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_7
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_6_n_0),
- .Q(count_13d_srl_r_reg_r_7_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_8
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_7_n_0),
- .Q(count_13d_srl_r_reg_r_8_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_9
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_8_n_0),
- .Q(count_13d_srl_r_reg_r_9_n_0),
- .R(DO_CC_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair281" *)
- LUT4 #(
- .INIT(16'hFBF8))
- count_16d_flop_r_i_1
- (.I0(\count_16d_srl_r_reg_n_0_[14] ),
- .I1(count_16d_srl_r0),
- .I2(reset_r),
- .I3(count_16d_flop_r),
- .O(count_16d_flop_r_i_1_n_0));
- FDRE count_16d_flop_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(count_16d_flop_r_i_1_n_0),
- .Q(count_16d_flop_r),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[0]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(count_16d_flop_r),
- .Q(\count_16d_srl_r_reg_n_0_[0] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[10]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[9] ),
- .Q(\count_16d_srl_r_reg_n_0_[10] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[11]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[10] ),
- .Q(\count_16d_srl_r_reg_n_0_[11] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[12]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[11] ),
- .Q(\count_16d_srl_r_reg_n_0_[12] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[13]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[12] ),
- .Q(\count_16d_srl_r_reg_n_0_[13] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[14]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[13] ),
- .Q(\count_16d_srl_r_reg_n_0_[14] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[1]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[0] ),
- .Q(\count_16d_srl_r_reg_n_0_[1] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[2]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[1] ),
- .Q(\count_16d_srl_r_reg_n_0_[2] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[3]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[2] ),
- .Q(\count_16d_srl_r_reg_n_0_[3] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[4]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[3] ),
- .Q(\count_16d_srl_r_reg_n_0_[4] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[5]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[4] ),
- .Q(\count_16d_srl_r_reg_n_0_[5] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[6]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[5] ),
- .Q(\count_16d_srl_r_reg_n_0_[6] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[7]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[6] ),
- .Q(\count_16d_srl_r_reg_n_0_[7] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[8]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[7] ),
- .Q(\count_16d_srl_r_reg_n_0_[8] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[9]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[8] ),
- .Q(\count_16d_srl_r_reg_n_0_[9] ),
- .R(DO_CC_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair280" *)
- LUT5 #(
- .INIT(32'hFFBFFF80))
- count_24d_flop_r_i_1
- (.I0(\count_24d_srl_r_reg_n_0_[10] ),
- .I1(count_16d_srl_r0),
- .I2(\count_16d_srl_r_reg_n_0_[14] ),
- .I3(reset_r),
- .I4(count_24d_flop_r),
- .O(count_24d_flop_r_i_1_n_0));
- FDRE count_24d_flop_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(count_24d_flop_r_i_1_n_0),
- .Q(count_24d_flop_r),
- .R(DO_CC_reg_0));
- LUT2 #(
- .INIT(4'h8))
- \count_24d_srl_r[0]_i_1
- (.I0(count_16d_srl_r0),
- .I1(\count_16d_srl_r_reg_n_0_[14] ),
- .O(count_24d_srl_r0));
- FDRE \count_24d_srl_r_reg[0]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(count_24d_flop_r),
- .Q(\count_24d_srl_r_reg_n_0_[0] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[10]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[9] ),
- .Q(\count_24d_srl_r_reg_n_0_[10] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[1]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[0] ),
- .Q(\count_24d_srl_r_reg_n_0_[1] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[2]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[1] ),
- .Q(\count_24d_srl_r_reg_n_0_[2] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[3]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[2] ),
- .Q(\count_24d_srl_r_reg_n_0_[3] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[4]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[3] ),
- .Q(\count_24d_srl_r_reg_n_0_[4] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[5]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[4] ),
- .Q(\count_24d_srl_r_reg_n_0_[5] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[6]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[5] ),
- .Q(\count_24d_srl_r_reg_n_0_[6] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[7]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[6] ),
- .Q(\count_24d_srl_r_reg_n_0_[7] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[8]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[7] ),
- .Q(\count_24d_srl_r_reg_n_0_[8] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[9]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[8] ),
- .Q(\count_24d_srl_r_reg_n_0_[9] ),
- .R(DO_CC_reg_0));
- (* srl_bus_name = "U0/\standard_cc_module_i/prepare_count_r_reg " *)
- (* srl_name = "U0/\standard_cc_module_i/prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1 " *)
- SRL16E #(
- .INIT(16'h0000))
- \prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1
- (.A0(1'b1),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(cc_idle_count_done_c),
- .Q(\prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair280" *)
- LUT3 #(
- .INIT(8'h80))
- \prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_i_1
- (.I0(count_16d_srl_r0),
- .I1(\count_16d_srl_r_reg_n_0_[14] ),
- .I2(\count_24d_srl_r_reg_n_0_[10] ),
- .O(cc_idle_count_done_c));
- FDRE \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2
- (.C(user_clk),
- .CE(1'b1),
- .D(\prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_n_0 ),
- .Q(\prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2_n_0 ),
- .R(1'b0));
- FDRE \prepare_count_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(prepare_count_r_reg_gate_n_0),
- .Q(p_3_out),
- .R(DO_CC_reg_0));
- LUT2 #(
- .INIT(4'h8))
- prepare_count_r_reg_gate
- (.I0(\prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2_n_0 ),
- .I1(count_13d_srl_r_reg_r_2_n_0),
- .O(prepare_count_r_reg_gate_n_0));
- FDRE reset_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(DO_CC_reg_0),
- .Q(reset_r),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hA8AA))
- ufc_idle_r_i_1
- (.I0(ufc_idle_r_reg),
- .I1(DO_CC_I),
- .I2(WARN_CC),
- .I3(S_AXI_UFC_TX_REQ),
- .O(next_ufc_idle_c));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_STORAGE_CE_CONTROL" *)
-module east_channel_east_channel_STORAGE_CE_CONTROL
- (Q,
- RESET,
- D,
- user_clk);
- output [1:0]Q;
- input RESET;
- input [1:0]D;
- input user_clk;
-
- wire [1:0]D;
- wire [1:0]Q;
- wire RESET;
- wire user_clk;
-
- FDRE \STORAGE_CE_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(Q[1]),
- .R(RESET));
- FDRE \STORAGE_CE_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(Q[0]),
- .R(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_STORAGE_COUNT_CONTROL" *)
-module east_channel_east_channel_STORAGE_COUNT_CONTROL
- (output_select_c,
- Q,
- FRAME_ERR_RESULT_Buffer0,
- end_storage_r_reg,
- stage_2_start_with_data_r,
- stage_3_end_storage_r,
- stage_2_frame_err_r,
- stage_2_end_after_start_r,
- stage_2_end_before_start_r,
- std_bool2_in,
- SR,
- D,
- user_clk);
- output [0:0]output_select_c;
- output [1:0]Q;
- output FRAME_ERR_RESULT_Buffer0;
- output end_storage_r_reg;
- input stage_2_start_with_data_r;
- input stage_3_end_storage_r;
- input stage_2_frame_err_r;
- input stage_2_end_after_start_r;
- input stage_2_end_before_start_r;
- input std_bool2_in;
- input [0:0]SR;
- input [1:0]D;
- input user_clk;
-
- wire [1:0]D;
- wire FRAME_ERR_RESULT_Buffer0;
- wire [1:0]Q;
- wire [0:0]SR;
- wire end_storage_r_reg;
- wire [0:0]output_select_c;
- wire \sideband_output_i/std_bool ;
- wire stage_2_end_after_start_r;
- wire stage_2_end_before_start_r;
- wire stage_2_frame_err_r;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire std_bool2_in;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair174" *)
- LUT5 #(
- .INIT(32'h15151555))
- EOF_N_Buffer_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_end_before_start_r),
- .I2(stage_2_start_with_data_r),
- .I3(Q[1]),
- .I4(Q[0]),
- .O(end_storage_r_reg));
- LUT6 #(
- .INIT(64'hDDFFCCFCDDFCCCFC))
- FRAME_ERR_RESULT_Buffer_i_1
- (.I0(\sideband_output_i/std_bool ),
- .I1(stage_2_frame_err_r),
- .I2(stage_2_end_after_start_r),
- .I3(stage_2_start_with_data_r),
- .I4(stage_2_end_before_start_r),
- .I5(std_bool2_in),
- .O(FRAME_ERR_RESULT_Buffer0));
- LUT2 #(
- .INIT(4'hE))
- FRAME_ERR_RESULT_Buffer_i_2
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\sideband_output_i/std_bool ));
- (* SOFT_HLUTNM = "soft_lutpair174" *)
- LUT3 #(
- .INIT(8'h01))
- \OUTPUT_SELECT_Buffer[9]_i_1
- (.I0(Q[1]),
- .I1(stage_2_start_with_data_r),
- .I2(stage_3_end_storage_r),
- .O(output_select_c));
- FDRE \storage_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(Q[1]),
- .R(SR));
- FDRE \storage_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(Q[0]),
- .R(SR));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_STORAGE_MUX" *)
-module east_channel_east_channel_STORAGE_MUX
- (Q,
- E,
- D,
- user_clk);
- output [31:0]Q;
- input [1:0]E;
- input [31:0]D;
- input user_clk;
-
- wire [31:0]D;
- wire [1:0]E;
- wire [31:0]Q;
- wire user_clk;
-
- FDRE \STORAGE_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[31]),
- .Q(Q[31]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[21]),
- .Q(Q[21]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[20]),
- .Q(Q[20]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[19]),
- .Q(Q[19]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[18]),
- .Q(Q[18]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[17]),
- .Q(Q[17]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[16]),
- .Q(Q[16]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[15]),
- .Q(Q[15]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[14]),
- .Q(Q[14]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[13]),
- .Q(Q[13]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[12]),
- .Q(Q[12]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[30]),
- .Q(Q[30]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[11]),
- .Q(Q[11]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[10]),
- .Q(Q[10]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[9]),
- .Q(Q[9]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[8]),
- .Q(Q[8]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[7]),
- .Q(Q[7]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[6]),
- .Q(Q[6]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[5]),
- .Q(Q[5]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[4]),
- .Q(Q[4]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[3]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[2]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[29]),
- .Q(Q[29]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[0]),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[28]),
- .Q(Q[28]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[27]),
- .Q(Q[27]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[26]),
- .Q(Q[26]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[25]),
- .Q(Q[25]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[24]),
- .Q(Q[24]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[23]),
- .Q(Q[23]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[22]),
- .Q(Q[22]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_STORAGE_SWITCH_CONTROL" *)
-module east_channel_east_channel_STORAGE_SWITCH_CONTROL
- (STORAGE_SELECT_Buffer,
- Q,
- stage_2_start_with_data_r,
- stage_3_end_storage_r,
- user_clk);
- output [1:0]STORAGE_SELECT_Buffer;
- input [0:0]Q;
- input stage_2_start_with_data_r;
- input stage_3_end_storage_r;
- input user_clk;
-
- wire [0:0]Q;
- wire [1:0]STORAGE_SELECT_Buffer;
- wire \STORAGE_SELECT_Buffer[4]_i_1_n_0 ;
- wire \STORAGE_SELECT_Buffer[9]_i_1_n_0 ;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair175" *)
- LUT3 #(
- .INIT(8'h02))
- \STORAGE_SELECT_Buffer[4]_i_1
- (.I0(Q),
- .I1(stage_2_start_with_data_r),
- .I2(stage_3_end_storage_r),
- .O(\STORAGE_SELECT_Buffer[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair175" *)
- LUT3 #(
- .INIT(8'hFD))
- \STORAGE_SELECT_Buffer[9]_i_1
- (.I0(Q),
- .I1(stage_2_start_with_data_r),
- .I2(stage_3_end_storage_r),
- .O(\STORAGE_SELECT_Buffer[9]_i_1_n_0 ));
- FDRE \STORAGE_SELECT_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\STORAGE_SELECT_Buffer[4]_i_1_n_0 ),
- .Q(STORAGE_SELECT_Buffer[1]),
- .R(1'b0));
- FDRE \STORAGE_SELECT_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\STORAGE_SELECT_Buffer[9]_i_1_n_0 ),
- .Q(STORAGE_SELECT_Buffer[0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SYM_DEC_4BYTE" *)
-module east_channel_east_channel_SYM_DEC_4BYTE
- (\left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[1]_0 ,
- rx_sp_descram_in,
- rx_spa_descram_in,
- rx_neg_descram_in,
- got_v_descram_in,
- D,
- rx_pe_data_descram_in,
- first_v_received_r,
- CHANNEL_UP_Buffer_reg,
- Q,
- \RX_PE_DATA_V_Buffer_reg[0]_0 ,
- \RX_PE_DATA_Buffer_reg[16]_0 ,
- BYPASS,
- E,
- \RX_PE_DATA_Buffer_reg[0]_0 ,
- bypass_w_reg,
- \previous_cycle_data_r_reg[7]_0 ,
- \previous_cycle_control_r_reg[0]_0 ,
- \RX_SUF_Buffer_reg[0]_0 ,
- p_9_out,
- p_8_out,
- \left_align_select_r_reg[0]_1 ,
- user_clk,
- \left_align_select_r_reg[1]_1 ,
- \word_aligned_control_bits_r_reg[3]_0 ,
- \word_aligned_control_bits_r_reg[2]_0 ,
- \bypass_r_reg[0] ,
- reset_lanes_i,
- \DOUT_reg[0] ,
- \DOUT_reg[0]_0 ,
- RXDATA,
- RXCHARISK,
- LANE_UP,
- \word_aligned_data_r_reg[24]_0 ,
- \word_aligned_data_r_reg[16]_0 );
- output \left_align_select_r_reg[0]_0 ;
- output \left_align_select_r_reg[1]_0 ;
- output rx_sp_descram_in;
- output rx_spa_descram_in;
- output rx_neg_descram_in;
- output got_v_descram_in;
- output [0:0]D;
- output [0:31]rx_pe_data_descram_in;
- output first_v_received_r;
- output [0:0]CHANNEL_UP_Buffer_reg;
- output [1:0]Q;
- output [1:0]\RX_PE_DATA_V_Buffer_reg[0]_0 ;
- output [15:0]\RX_PE_DATA_Buffer_reg[16]_0 ;
- output BYPASS;
- output [0:0]E;
- output [15:0]\RX_PE_DATA_Buffer_reg[0]_0 ;
- output bypass_w_reg;
- output [7:0]\previous_cycle_data_r_reg[7]_0 ;
- output [0:0]\previous_cycle_control_r_reg[0]_0 ;
- output [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- output [1:0]p_9_out;
- output [1:0]p_8_out;
- input \left_align_select_r_reg[0]_1 ;
- input user_clk;
- input \left_align_select_r_reg[1]_1 ;
- input \word_aligned_control_bits_r_reg[3]_0 ;
- input \word_aligned_control_bits_r_reg[2]_0 ;
- input \bypass_r_reg[0] ;
- input reset_lanes_i;
- input [15:0]\DOUT_reg[0] ;
- input [15:0]\DOUT_reg[0]_0 ;
- input [31:0]RXDATA;
- input [3:0]RXCHARISK;
- input LANE_UP;
- input [7:0]\word_aligned_data_r_reg[24]_0 ;
- input [7:0]\word_aligned_data_r_reg[16]_0 ;
-
- wire BYPASS;
- wire [0:0]CHANNEL_UP_Buffer_reg;
- wire [0:0]D;
- wire [15:0]\DOUT_reg[0] ;
- wire [15:0]\DOUT_reg[0]_0 ;
- wire [0:0]E;
- wire \EXP_IN_inferred__0/i__n_0 ;
- wire \EXP_IN_inferred__1/i__n_0 ;
- wire \EXP_IN_inferred__10/i__n_0 ;
- wire \EXP_IN_inferred__11/i__n_0 ;
- wire \EXP_IN_inferred__12/i__n_0 ;
- wire \EXP_IN_inferred__13/i__n_0 ;
- wire \EXP_IN_inferred__14/i__n_0 ;
- wire \EXP_IN_inferred__15/i__n_0 ;
- wire \EXP_IN_inferred__16/i__n_0 ;
- wire \EXP_IN_inferred__17/i__n_0 ;
- wire \EXP_IN_inferred__18/i__n_0 ;
- wire \EXP_IN_inferred__19/i__n_0 ;
- wire \EXP_IN_inferred__2/i__n_0 ;
- wire \EXP_IN_inferred__20/i__n_0 ;
- wire \EXP_IN_inferred__21/i__n_0 ;
- wire \EXP_IN_inferred__22/i__n_0 ;
- wire \EXP_IN_inferred__23/i__n_0 ;
- wire \EXP_IN_inferred__24/i__n_0 ;
- wire \EXP_IN_inferred__25/i__n_0 ;
- wire \EXP_IN_inferred__26/i__n_0 ;
- wire \EXP_IN_inferred__3/i__n_0 ;
- wire \EXP_IN_inferred__30/i__n_0 ;
- wire \EXP_IN_inferred__31/i__n_0 ;
- wire \EXP_IN_inferred__32/i__n_0 ;
- wire \EXP_IN_inferred__34/i__n_0 ;
- wire \EXP_IN_inferred__35/i__n_0 ;
- wire \EXP_IN_inferred__4/i__n_0 ;
- wire \EXP_IN_inferred__44/i__n_0 ;
- wire \EXP_IN_inferred__45/i__n_0 ;
- wire \EXP_IN_inferred__46/i__n_0 ;
- wire \EXP_IN_inferred__47/i__n_0 ;
- wire \EXP_IN_inferred__5/i__n_0 ;
- wire \EXP_IN_inferred__8/i__n_0 ;
- wire \EXP_IN_inferred__9/i__n_0 ;
- wire EXP_IN_n_0;
- wire GOT_V_Buffer_i_2_n_0;
- wire LANE_UP;
- wire [1:0]Q;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire RX_CC_Buffer_i_1_n_0;
- wire RX_CC_Buffer_i_2_n_0;
- wire RX_CC_Buffer_i_3_n_0;
- wire RX_NEG_Buffer0;
- wire [15:0]\RX_PE_DATA_Buffer_reg[0]_0 ;
- wire [15:0]\RX_PE_DATA_Buffer_reg[16]_0 ;
- wire \RX_PE_DATA_V_Buffer[0]_i_1_n_0 ;
- wire \RX_PE_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\RX_PE_DATA_V_Buffer_reg[0]_0 ;
- wire RX_SPA_Buffer_i_2_n_0;
- wire RX_SP_Buffer_i_2_n_0;
- wire RX_SP_Buffer_i_3_n_0;
- wire [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- wire \bypass_r_reg[0] ;
- wire bypass_w_reg;
- wire first_v_received_r;
- wire first_v_received_r_i_1_n_0;
- wire got_v_descram_in;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1]_0 ;
- wire \left_align_select_r_reg[1]_1 ;
- wire [3:0]p_0_in;
- wire p_0_in14_in;
- wire p_0_in18_in;
- wire p_0_in26_in;
- wire p_0_in28_in;
- wire p_15_in;
- wire p_1_in;
- wire p_21_in;
- wire [7:0]p_2_in;
- wire p_2_in30_in;
- wire [1:0]p_2_out;
- wire p_32_in;
- wire p_3_in;
- wire [1:0]p_5_out;
- wire p_6_in22_in;
- wire p_6_in34_in;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [2:1]previous_cycle_control_r;
- wire [0:0]\previous_cycle_control_r_reg[0]_0 ;
- wire [7:0]\previous_cycle_data_r_reg[7]_0 ;
- wire \previous_cycle_data_r_reg_n_0_[16] ;
- wire \previous_cycle_data_r_reg_n_0_[17] ;
- wire \previous_cycle_data_r_reg_n_0_[18] ;
- wire \previous_cycle_data_r_reg_n_0_[19] ;
- wire \previous_cycle_data_r_reg_n_0_[20] ;
- wire \previous_cycle_data_r_reg_n_0_[21] ;
- wire \previous_cycle_data_r_reg_n_0_[22] ;
- wire \previous_cycle_data_r_reg_n_0_[23] ;
- wire reset_lanes_i;
- wire [1:7]rx_cc_r;
- wire \rx_ecp_d_r_reg_n_0_[3] ;
- wire \rx_ecp_d_r_reg_n_0_[5] ;
- wire \rx_ecp_d_r_reg_n_0_[7] ;
- wire rx_neg_descram_in;
- wire [0:2]rx_pad_d_r;
- wire \rx_pe_control_r_reg_n_0_[3] ;
- wire [0:31]rx_pe_data_descram_in;
- wire [0:31]rx_pe_data_r;
- wire \rx_scp_d_r_reg_n_0_[3] ;
- wire \rx_scp_d_r_reg_n_0_[7] ;
- wire rx_sp_descram_in;
- wire [0:1]rx_sp_neg_d_r;
- wire [0:7]rx_sp_r;
- wire \rx_sp_r[2]_i_1_n_0 ;
- wire \rx_sp_r[3]_i_1_n_0 ;
- wire \rx_sp_r[4]_i_1_n_0 ;
- wire \rx_sp_r[5]_i_1_n_0 ;
- wire \rx_sp_r[6]_i_1_n_0 ;
- wire \rx_sp_r[7]_i_1_n_0 ;
- wire rx_spa_descram_in;
- wire [0:1]rx_spa_neg_d_r;
- wire [2:7]rx_spa_r;
- wire [2:7]rx_v_d_r;
- wire std_bool;
- wire std_bool11_out;
- wire std_bool13_in;
- wire std_bool13_out;
- wire std_bool16_in;
- wire std_bool1_out;
- wire user_clk;
- wire [0:3]word_aligned_control_bits_r;
- wire \word_aligned_control_bits_r[0]_i_1_n_0 ;
- wire \word_aligned_control_bits_r[1]_i_1_n_0 ;
- wire \word_aligned_control_bits_r_reg[2]_0 ;
- wire \word_aligned_control_bits_r_reg[3]_0 ;
- wire \word_aligned_data_r[0]_i_1_n_0 ;
- wire \word_aligned_data_r[10]_i_1_n_0 ;
- wire \word_aligned_data_r[11]_i_1_n_0 ;
- wire \word_aligned_data_r[12]_i_1_n_0 ;
- wire \word_aligned_data_r[13]_i_1_n_0 ;
- wire \word_aligned_data_r[14]_i_1_n_0 ;
- wire \word_aligned_data_r[15]_i_1_n_0 ;
- wire \word_aligned_data_r[1]_i_1_n_0 ;
- wire \word_aligned_data_r[2]_i_1_n_0 ;
- wire \word_aligned_data_r[3]_i_1_n_0 ;
- wire \word_aligned_data_r[4]_i_1_n_0 ;
- wire \word_aligned_data_r[5]_i_1_n_0 ;
- wire \word_aligned_data_r[6]_i_1_n_0 ;
- wire \word_aligned_data_r[7]_i_1_n_0 ;
- wire \word_aligned_data_r[8]_i_1_n_0 ;
- wire \word_aligned_data_r[9]_i_1_n_0 ;
- wire [7:0]\word_aligned_data_r_reg[16]_0 ;
- wire [7:0]\word_aligned_data_r_reg[24]_0 ;
- wire \word_aligned_data_r_reg_n_0_[0] ;
- wire \word_aligned_data_r_reg_n_0_[12] ;
- wire \word_aligned_data_r_reg_n_0_[13] ;
- wire \word_aligned_data_r_reg_n_0_[14] ;
- wire \word_aligned_data_r_reg_n_0_[15] ;
- wire \word_aligned_data_r_reg_n_0_[16] ;
- wire \word_aligned_data_r_reg_n_0_[17] ;
- wire \word_aligned_data_r_reg_n_0_[18] ;
- wire \word_aligned_data_r_reg_n_0_[19] ;
- wire \word_aligned_data_r_reg_n_0_[1] ;
- wire \word_aligned_data_r_reg_n_0_[20] ;
- wire \word_aligned_data_r_reg_n_0_[21] ;
- wire \word_aligned_data_r_reg_n_0_[22] ;
- wire \word_aligned_data_r_reg_n_0_[23] ;
- wire \word_aligned_data_r_reg_n_0_[24] ;
- wire \word_aligned_data_r_reg_n_0_[25] ;
- wire \word_aligned_data_r_reg_n_0_[26] ;
- wire \word_aligned_data_r_reg_n_0_[27] ;
- wire \word_aligned_data_r_reg_n_0_[28] ;
- wire \word_aligned_data_r_reg_n_0_[29] ;
- wire \word_aligned_data_r_reg_n_0_[2] ;
- wire \word_aligned_data_r_reg_n_0_[30] ;
- wire \word_aligned_data_r_reg_n_0_[31] ;
- wire \word_aligned_data_r_reg_n_0_[3] ;
- wire \word_aligned_data_r_reg_n_0_[4] ;
- wire \word_aligned_data_r_reg_n_0_[5] ;
- wire \word_aligned_data_r_reg_n_0_[6] ;
- wire \word_aligned_data_r_reg_n_0_[7] ;
-
- (* SOFT_HLUTNM = "soft_lutpair99" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[31]),
- .I2(\DOUT_reg[0] [15]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [0]));
- (* SOFT_HLUTNM = "soft_lutpair90" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[15]),
- .I2(\DOUT_reg[0]_0 [15]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [0]));
- (* SOFT_HLUTNM = "soft_lutpair87" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[21]),
- .I2(\DOUT_reg[0] [5]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [10]));
- (* SOFT_HLUTNM = "soft_lutpair95" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[5]),
- .I2(\DOUT_reg[0]_0 [5]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [10]));
- (* SOFT_HLUTNM = "soft_lutpair89" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[20]),
- .I2(\DOUT_reg[0] [4]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [11]));
- (* SOFT_HLUTNM = "soft_lutpair94" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[4]),
- .I2(\DOUT_reg[0]_0 [4]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [11]));
- (* SOFT_HLUTNM = "soft_lutpair88" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[19]),
- .I2(\DOUT_reg[0] [3]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [12]));
- (* SOFT_HLUTNM = "soft_lutpair93" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[3]),
- .I2(\DOUT_reg[0]_0 [3]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [12]));
- (* SOFT_HLUTNM = "soft_lutpair88" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[18]),
- .I2(\DOUT_reg[0] [2]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [13]));
- (* SOFT_HLUTNM = "soft_lutpair92" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[2]),
- .I2(\DOUT_reg[0]_0 [2]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [13]));
- (* SOFT_HLUTNM = "soft_lutpair87" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[17]),
- .I2(\DOUT_reg[0] [1]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [14]));
- (* SOFT_HLUTNM = "soft_lutpair91" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[1]),
- .I2(\DOUT_reg[0]_0 [1]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [14]));
- (* SOFT_HLUTNM = "soft_lutpair86" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[16]),
- .I2(\DOUT_reg[0] [0]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [15]));
- (* SOFT_HLUTNM = "soft_lutpair90" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[0]),
- .I2(\DOUT_reg[0]_0 [0]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [15]));
- (* SOFT_HLUTNM = "soft_lutpair100" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[30]),
- .I2(\DOUT_reg[0] [14]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair91" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[14]),
- .I2(\DOUT_reg[0]_0 [14]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair101" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[29]),
- .I2(\DOUT_reg[0] [13]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [2]));
- (* SOFT_HLUTNM = "soft_lutpair92" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[13]),
- .I2(\DOUT_reg[0]_0 [13]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [2]));
- (* SOFT_HLUTNM = "soft_lutpair101" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[28]),
- .I2(\DOUT_reg[0] [12]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [3]));
- (* SOFT_HLUTNM = "soft_lutpair93" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[12]),
- .I2(\DOUT_reg[0]_0 [12]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [3]));
- (* SOFT_HLUTNM = "soft_lutpair100" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[27]),
- .I2(\DOUT_reg[0] [11]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [4]));
- (* SOFT_HLUTNM = "soft_lutpair94" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[11]),
- .I2(\DOUT_reg[0]_0 [11]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [4]));
- (* SOFT_HLUTNM = "soft_lutpair86" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[26]),
- .I2(\DOUT_reg[0] [10]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [5]));
- (* SOFT_HLUTNM = "soft_lutpair95" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[10]),
- .I2(\DOUT_reg[0]_0 [10]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [5]));
- (* SOFT_HLUTNM = "soft_lutpair99" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[25]),
- .I2(\DOUT_reg[0] [9]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [6]));
- (* SOFT_HLUTNM = "soft_lutpair96" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[9]),
- .I2(\DOUT_reg[0]_0 [9]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [6]));
- (* SOFT_HLUTNM = "soft_lutpair98" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[24]),
- .I2(\DOUT_reg[0] [8]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [7]));
- (* SOFT_HLUTNM = "soft_lutpair97" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[8]),
- .I2(\DOUT_reg[0]_0 [8]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [7]));
- (* SOFT_HLUTNM = "soft_lutpair98" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[23]),
- .I2(\DOUT_reg[0] [7]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [8]));
- (* SOFT_HLUTNM = "soft_lutpair97" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[7]),
- .I2(\DOUT_reg[0]_0 [7]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [8]));
- (* SOFT_HLUTNM = "soft_lutpair89" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[22]),
- .I2(\DOUT_reg[0] [6]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [9]));
- (* SOFT_HLUTNM = "soft_lutpair96" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[6]),
- .I2(\DOUT_reg[0]_0 [6]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [9]));
- (* SOFT_HLUTNM = "soft_lutpair71" *)
- LUT4 #(
- .INIT(16'h1000))
- EXP_IN
- (.I0(\word_aligned_data_r_reg_n_0_[6] ),
- .I1(\word_aligned_data_r_reg_n_0_[7] ),
- .I2(\word_aligned_data_r_reg_n_0_[5] ),
- .I3(\word_aligned_data_r_reg_n_0_[4] ),
- .O(EXP_IN_n_0));
- (* SOFT_HLUTNM = "soft_lutpair69" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__0/i_
- (.I0(\word_aligned_data_r_reg_n_0_[1] ),
- .I1(\word_aligned_data_r_reg_n_0_[0] ),
- .I2(\word_aligned_data_r_reg_n_0_[2] ),
- .I3(\word_aligned_data_r_reg_n_0_[3] ),
- .O(\EXP_IN_inferred__0/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair84" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__1/i_
- (.I0(\word_aligned_data_r_reg_n_0_[29] ),
- .I1(\word_aligned_data_r_reg_n_0_[30] ),
- .I2(\word_aligned_data_r_reg_n_0_[28] ),
- .I3(\word_aligned_data_r_reg_n_0_[31] ),
- .O(\EXP_IN_inferred__1/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair72" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__10/i_
- (.I0(\word_aligned_data_r_reg_n_0_[14] ),
- .I1(\word_aligned_data_r_reg_n_0_[15] ),
- .I2(\word_aligned_data_r_reg_n_0_[13] ),
- .I3(\word_aligned_data_r_reg_n_0_[12] ),
- .O(\EXP_IN_inferred__10/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair80" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__11/i_
- (.I0(p_0_in[2]),
- .I1(p_0_in[1]),
- .I2(p_0_in[3]),
- .I3(p_0_in[0]),
- .O(\EXP_IN_inferred__11/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair85" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__12/i_
- (.I0(\word_aligned_data_r_reg_n_0_[29] ),
- .I1(\word_aligned_data_r_reg_n_0_[28] ),
- .I2(\word_aligned_data_r_reg_n_0_[30] ),
- .I3(\word_aligned_data_r_reg_n_0_[31] ),
- .O(\EXP_IN_inferred__12/i__n_0 ));
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__13/i_
- (.I0(\word_aligned_data_r_reg_n_0_[26] ),
- .I1(\word_aligned_data_r_reg_n_0_[27] ),
- .I2(\word_aligned_data_r_reg_n_0_[25] ),
- .I3(\word_aligned_data_r_reg_n_0_[24] ),
- .O(\EXP_IN_inferred__13/i__n_0 ));
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__14/i_
- (.I0(\word_aligned_data_r_reg_n_0_[22] ),
- .I1(\word_aligned_data_r_reg_n_0_[23] ),
- .I2(\word_aligned_data_r_reg_n_0_[21] ),
- .I3(\word_aligned_data_r_reg_n_0_[20] ),
- .O(\EXP_IN_inferred__14/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair78" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__15/i_
- (.I0(\word_aligned_data_r_reg_n_0_[16] ),
- .I1(\word_aligned_data_r_reg_n_0_[18] ),
- .I2(\word_aligned_data_r_reg_n_0_[17] ),
- .I3(\word_aligned_data_r_reg_n_0_[19] ),
- .O(\EXP_IN_inferred__15/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair76" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__16/i_
- (.I0(\word_aligned_data_r_reg_n_0_[13] ),
- .I1(\word_aligned_data_r_reg_n_0_[12] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__16/i__n_0 ));
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__17/i_
- (.I0(p_0_in[1]),
- .I1(p_0_in[0]),
- .I2(p_0_in[2]),
- .I3(p_0_in[3]),
- .O(\EXP_IN_inferred__17/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair70" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__18/i_
- (.I0(\word_aligned_data_r_reg_n_0_[0] ),
- .I1(\word_aligned_data_r_reg_n_0_[2] ),
- .I2(\word_aligned_data_r_reg_n_0_[1] ),
- .I3(\word_aligned_data_r_reg_n_0_[3] ),
- .O(\EXP_IN_inferred__18/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair84" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__19/i_
- (.I0(\word_aligned_data_r_reg_n_0_[31] ),
- .I1(\word_aligned_data_r_reg_n_0_[29] ),
- .I2(\word_aligned_data_r_reg_n_0_[28] ),
- .I3(\word_aligned_data_r_reg_n_0_[30] ),
- .O(\EXP_IN_inferred__19/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair65" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__2/i_
- (.I0(\word_aligned_data_r_reg_n_0_[27] ),
- .I1(\word_aligned_data_r_reg_n_0_[25] ),
- .I2(\word_aligned_data_r_reg_n_0_[24] ),
- .I3(\word_aligned_data_r_reg_n_0_[26] ),
- .O(\EXP_IN_inferred__2/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair83" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__20/i_
- (.I0(\word_aligned_data_r_reg_n_0_[22] ),
- .I1(\word_aligned_data_r_reg_n_0_[21] ),
- .I2(\word_aligned_data_r_reg_n_0_[20] ),
- .I3(\word_aligned_data_r_reg_n_0_[23] ),
- .O(\EXP_IN_inferred__20/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair82" *)
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__21/i_
- (.I0(\word_aligned_data_r_reg_n_0_[18] ),
- .I1(\word_aligned_data_r_reg_n_0_[19] ),
- .I2(\word_aligned_data_r_reg_n_0_[17] ),
- .I3(\word_aligned_data_r_reg_n_0_[16] ),
- .O(\EXP_IN_inferred__21/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair81" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__22/i_
- (.I0(\word_aligned_data_r_reg_n_0_[15] ),
- .I1(\word_aligned_data_r_reg_n_0_[13] ),
- .I2(\word_aligned_data_r_reg_n_0_[12] ),
- .I3(\word_aligned_data_r_reg_n_0_[14] ),
- .O(\EXP_IN_inferred__22/i__n_0 ));
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__23/i_
- (.I0(\word_aligned_data_r_reg_n_0_[6] ),
- .I1(\word_aligned_data_r_reg_n_0_[5] ),
- .I2(\word_aligned_data_r_reg_n_0_[4] ),
- .I3(\word_aligned_data_r_reg_n_0_[7] ),
- .O(\EXP_IN_inferred__23/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair70" *)
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__24/i_
- (.I0(\word_aligned_data_r_reg_n_0_[2] ),
- .I1(\word_aligned_data_r_reg_n_0_[3] ),
- .I2(\word_aligned_data_r_reg_n_0_[1] ),
- .I3(\word_aligned_data_r_reg_n_0_[0] ),
- .O(\EXP_IN_inferred__24/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair82" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__25/i_
- (.I0(\word_aligned_data_r_reg_n_0_[17] ),
- .I1(\word_aligned_data_r_reg_n_0_[18] ),
- .I2(\word_aligned_data_r_reg_n_0_[16] ),
- .I3(\word_aligned_data_r_reg_n_0_[19] ),
- .O(\EXP_IN_inferred__25/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair69" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__26/i_
- (.I0(\word_aligned_data_r_reg_n_0_[1] ),
- .I1(\word_aligned_data_r_reg_n_0_[2] ),
- .I2(\word_aligned_data_r_reg_n_0_[0] ),
- .I3(\word_aligned_data_r_reg_n_0_[3] ),
- .O(\EXP_IN_inferred__26/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair81" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__27/i_
- (.I0(\word_aligned_data_r_reg_n_0_[12] ),
- .I1(\word_aligned_data_r_reg_n_0_[14] ),
- .I2(\word_aligned_data_r_reg_n_0_[13] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(std_bool13_in));
- (* SOFT_HLUTNM = "soft_lutpair80" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__28/i_
- (.I0(p_0_in[2]),
- .I1(p_0_in[3]),
- .I2(p_0_in[1]),
- .I3(p_0_in[0]),
- .O(std_bool16_in));
- (* SOFT_HLUTNM = "soft_lutpair83" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__3/i_
- (.I0(\word_aligned_data_r_reg_n_0_[21] ),
- .I1(\word_aligned_data_r_reg_n_0_[22] ),
- .I2(\word_aligned_data_r_reg_n_0_[20] ),
- .I3(\word_aligned_data_r_reg_n_0_[23] ),
- .O(\EXP_IN_inferred__3/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair79" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__30/i_
- (.I0(\word_aligned_data_r_reg_n_0_[25] ),
- .I1(\word_aligned_data_r_reg_n_0_[24] ),
- .I2(\word_aligned_data_r_reg_n_0_[26] ),
- .I3(\word_aligned_data_r_reg_n_0_[27] ),
- .O(\EXP_IN_inferred__30/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair78" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__31/i_
- (.I0(\word_aligned_data_r_reg_n_0_[17] ),
- .I1(\word_aligned_data_r_reg_n_0_[16] ),
- .I2(\word_aligned_data_r_reg_n_0_[18] ),
- .I3(\word_aligned_data_r_reg_n_0_[19] ),
- .O(\EXP_IN_inferred__31/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair77" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__32/i_
- (.I0(p_0_in[2]),
- .I1(p_0_in[3]),
- .I2(p_0_in[1]),
- .I3(p_0_in[0]),
- .O(\EXP_IN_inferred__32/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair76" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__34/i_
- (.I0(\word_aligned_data_r_reg_n_0_[13] ),
- .I1(\word_aligned_data_r_reg_n_0_[12] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__34/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair75" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__35/i_
- (.I0(p_0_in[1]),
- .I1(p_0_in[2]),
- .I2(p_0_in[3]),
- .I3(p_0_in[0]),
- .O(\EXP_IN_inferred__35/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair66" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__4/i_
- (.I0(\word_aligned_data_r_reg_n_0_[19] ),
- .I1(\word_aligned_data_r_reg_n_0_[17] ),
- .I2(\word_aligned_data_r_reg_n_0_[16] ),
- .I3(\word_aligned_data_r_reg_n_0_[18] ),
- .O(\EXP_IN_inferred__4/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair74" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__44/i_
- (.I0(\word_aligned_data_r_reg_n_0_[28] ),
- .I1(\word_aligned_data_r_reg_n_0_[29] ),
- .I2(\word_aligned_data_r_reg_n_0_[30] ),
- .I3(\word_aligned_data_r_reg_n_0_[31] ),
- .O(\EXP_IN_inferred__44/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair73" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__45/i_
- (.I0(\word_aligned_data_r_reg_n_0_[20] ),
- .I1(\word_aligned_data_r_reg_n_0_[21] ),
- .I2(\word_aligned_data_r_reg_n_0_[22] ),
- .I3(\word_aligned_data_r_reg_n_0_[23] ),
- .O(\EXP_IN_inferred__45/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair72" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__46/i_
- (.I0(\word_aligned_data_r_reg_n_0_[12] ),
- .I1(\word_aligned_data_r_reg_n_0_[13] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__46/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair71" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__47/i_
- (.I0(\word_aligned_data_r_reg_n_0_[4] ),
- .I1(\word_aligned_data_r_reg_n_0_[5] ),
- .I2(\word_aligned_data_r_reg_n_0_[6] ),
- .I3(\word_aligned_data_r_reg_n_0_[7] ),
- .O(\EXP_IN_inferred__47/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair64" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__5/i_
- (.I0(\word_aligned_data_r_reg_n_0_[13] ),
- .I1(\word_aligned_data_r_reg_n_0_[14] ),
- .I2(\word_aligned_data_r_reg_n_0_[12] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__5/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair77" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__6/i_
- (.I0(p_0_in[0]),
- .I1(p_0_in[2]),
- .I2(p_0_in[3]),
- .I3(p_0_in[1]),
- .O(std_bool));
- (* SOFT_HLUTNM = "soft_lutpair85" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__8/i_
- (.I0(\word_aligned_data_r_reg_n_0_[30] ),
- .I1(\word_aligned_data_r_reg_n_0_[31] ),
- .I2(\word_aligned_data_r_reg_n_0_[29] ),
- .I3(\word_aligned_data_r_reg_n_0_[28] ),
- .O(\EXP_IN_inferred__8/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair79" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__9/i_
- (.I0(\word_aligned_data_r_reg_n_0_[25] ),
- .I1(\word_aligned_data_r_reg_n_0_[26] ),
- .I2(\word_aligned_data_r_reg_n_0_[24] ),
- .I3(\word_aligned_data_r_reg_n_0_[27] ),
- .O(\EXP_IN_inferred__9/i__n_0 ));
- LUT6 #(
- .INIT(64'h2000000000000000))
- GOT_V_Buffer_i_1
- (.I0(RX_SP_Buffer_i_2_n_0),
- .I1(GOT_V_Buffer_i_2_n_0),
- .I2(rx_sp_r[0]),
- .I3(rx_sp_r[1]),
- .I4(rx_v_d_r[3]),
- .I5(rx_v_d_r[2]),
- .O(std_bool1_out));
- LUT4 #(
- .INIT(16'h7FFF))
- GOT_V_Buffer_i_2
- (.I0(rx_v_d_r[5]),
- .I1(rx_v_d_r[4]),
- .I2(rx_v_d_r[7]),
- .I3(rx_v_d_r[6]),
- .O(GOT_V_Buffer_i_2_n_0));
- FDRE GOT_V_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool1_out),
- .Q(got_v_descram_in),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0000000000008000))
- RX_CC_Buffer_i_1
- (.I0(p_1_in),
- .I1(\rx_pe_control_r_reg_n_0_[3] ),
- .I2(p_3_in),
- .I3(p_0_in26_in),
- .I4(RX_CC_Buffer_i_2_n_0),
- .I5(RX_CC_Buffer_i_3_n_0),
- .O(RX_CC_Buffer_i_1_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_CC_Buffer_i_2
- (.I0(rx_cc_r[5]),
- .I1(p_0_in18_in),
- .I2(rx_cc_r[7]),
- .I3(p_2_in30_in),
- .O(RX_CC_Buffer_i_2_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_CC_Buffer_i_3
- (.I0(p_21_in),
- .I1(rx_cc_r[1]),
- .I2(rx_cc_r[3]),
- .I3(p_6_in34_in),
- .O(RX_CC_Buffer_i_3_n_0));
- FDRE RX_CC_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_CC_Buffer_i_1_n_0),
- .Q(D),
- .R(1'b0));
- LUT5 #(
- .INIT(32'h0000F888))
- RX_NEG_Buffer_i_1
- (.I0(rx_spa_neg_d_r[1]),
- .I1(rx_spa_neg_d_r[0]),
- .I2(rx_sp_neg_d_r[1]),
- .I3(rx_sp_neg_d_r[0]),
- .I4(p_0_in26_in),
- .O(RX_NEG_Buffer0));
- FDRE RX_NEG_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_NEG_Buffer0),
- .Q(rx_neg_descram_in),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair68" *)
- LUT4 #(
- .INIT(16'h0800))
- \RX_PAD_Buffer[0]_i_1
- (.I0(rx_pad_d_r[0]),
- .I1(rx_spa_r[3]),
- .I2(p_3_in),
- .I3(p_0_in26_in),
- .O(p_2_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair67" *)
- LUT4 #(
- .INIT(16'h0800))
- \RX_PAD_Buffer[1]_i_1
- (.I0(rx_pad_d_r[2]),
- .I1(rx_spa_r[7]),
- .I2(p_1_in),
- .I3(\rx_pe_control_r_reg_n_0_[3] ),
- .O(p_2_out[0]));
- FDRE \RX_PAD_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_out[1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \RX_PAD_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_out[0]),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[0]),
- .Q(rx_pe_data_descram_in[0]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[10]),
- .Q(rx_pe_data_descram_in[10]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[11]),
- .Q(rx_pe_data_descram_in[11]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[12]),
- .Q(rx_pe_data_descram_in[12]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[13]),
- .Q(rx_pe_data_descram_in[13]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[14]),
- .Q(rx_pe_data_descram_in[14]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[15]),
- .Q(rx_pe_data_descram_in[15]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[16]),
- .Q(rx_pe_data_descram_in[16]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[17]),
- .Q(rx_pe_data_descram_in[17]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[18]),
- .Q(rx_pe_data_descram_in[18]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[19]),
- .Q(rx_pe_data_descram_in[19]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[1]),
- .Q(rx_pe_data_descram_in[1]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[20]),
- .Q(rx_pe_data_descram_in[20]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[21]),
- .Q(rx_pe_data_descram_in[21]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[22]),
- .Q(rx_pe_data_descram_in[22]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[23]),
- .Q(rx_pe_data_descram_in[23]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[24]),
- .Q(rx_pe_data_descram_in[24]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[25]),
- .Q(rx_pe_data_descram_in[25]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[26]),
- .Q(rx_pe_data_descram_in[26]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[27]),
- .Q(rx_pe_data_descram_in[27]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[28]),
- .Q(rx_pe_data_descram_in[28]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[29]),
- .Q(rx_pe_data_descram_in[29]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[2]),
- .Q(rx_pe_data_descram_in[2]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[30]),
- .Q(rx_pe_data_descram_in[30]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[31]),
- .Q(rx_pe_data_descram_in[31]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[3]),
- .Q(rx_pe_data_descram_in[3]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[4]),
- .Q(rx_pe_data_descram_in[4]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[5]),
- .Q(rx_pe_data_descram_in[5]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[6]),
- .Q(rx_pe_data_descram_in[6]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[7]),
- .Q(rx_pe_data_descram_in[7]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[8]),
- .Q(rx_pe_data_descram_in[8]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[9]),
- .Q(rx_pe_data_descram_in[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair68" *)
- LUT1 #(
- .INIT(2'h1))
- \RX_PE_DATA_V_Buffer[0]_i_1
- (.I0(p_3_in),
- .O(\RX_PE_DATA_V_Buffer[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair67" *)
- LUT1 #(
- .INIT(2'h1))
- \RX_PE_DATA_V_Buffer[1]_i_1
- (.I0(p_1_in),
- .O(\RX_PE_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \RX_PE_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_Buffer[0]_i_1_n_0 ),
- .Q(\RX_PE_DATA_V_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_PE_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(\RX_PE_DATA_V_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h2000000000000000))
- RX_SPA_Buffer_i_1
- (.I0(RX_SP_Buffer_i_2_n_0),
- .I1(RX_SPA_Buffer_i_2_n_0),
- .I2(rx_sp_r[0]),
- .I3(rx_sp_r[1]),
- .I4(rx_spa_r[3]),
- .I5(rx_spa_r[2]),
- .O(std_bool11_out));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_SPA_Buffer_i_2
- (.I0(rx_spa_r[5]),
- .I1(rx_spa_r[4]),
- .I2(rx_spa_r[7]),
- .I3(rx_spa_r[6]),
- .O(RX_SPA_Buffer_i_2_n_0));
- FDRE RX_SPA_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool11_out),
- .Q(rx_spa_descram_in),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h2000000000000000))
- RX_SP_Buffer_i_1
- (.I0(RX_SP_Buffer_i_2_n_0),
- .I1(RX_SP_Buffer_i_3_n_0),
- .I2(rx_sp_r[0]),
- .I3(rx_sp_r[1]),
- .I4(rx_sp_r[3]),
- .I5(rx_sp_r[2]),
- .O(std_bool13_out));
- LUT4 #(
- .INIT(16'h0010))
- RX_SP_Buffer_i_2
- (.I0(\rx_pe_control_r_reg_n_0_[3] ),
- .I1(p_0_in26_in),
- .I2(p_3_in),
- .I3(p_1_in),
- .O(RX_SP_Buffer_i_2_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_SP_Buffer_i_3
- (.I0(rx_sp_r[5]),
- .I1(rx_sp_r[4]),
- .I2(rx_sp_r[7]),
- .I3(rx_sp_r[6]),
- .O(RX_SP_Buffer_i_3_n_0));
- FDRE RX_SP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool13_out),
- .Q(rx_sp_descram_in),
- .R(1'b0));
- LUT3 #(
- .INIT(8'h80))
- \RX_SUF_Buffer[0]_i_1
- (.I0(p_3_in),
- .I1(p_15_in),
- .I2(rx_sp_r[1]),
- .O(p_5_out[1]));
- LUT3 #(
- .INIT(8'h80))
- \RX_SUF_Buffer[1]_i_1
- (.I0(p_1_in),
- .I1(p_0_in14_in),
- .I2(rx_spa_r[5]),
- .O(p_5_out[0]));
- FDRE \RX_SUF_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_5_out[1]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_SUF_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_5_out[0]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT5 #(
- .INIT(32'hFFFDFFFF))
- \bypass_r[0]_i_1
- (.I0(\RX_PE_DATA_V_Buffer_reg[0]_0 [1]),
- .I1(Q[1]),
- .I2(got_v_descram_in),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(bypass_w_reg));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT5 #(
- .INIT(32'hFFFDFFFF))
- \bypass_r[1]_i_1
- (.I0(\RX_PE_DATA_V_Buffer_reg[0]_0 [0]),
- .I1(Q[0]),
- .I2(got_v_descram_in),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(BYPASS));
- LUT3 #(
- .INIT(8'hA8))
- first_v_received_r_i_1
- (.I0(LANE_UP),
- .I1(first_v_received_r),
- .I2(std_bool1_out),
- .O(first_v_received_r_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- first_v_received_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(first_v_received_r_i_1_n_0),
- .Q(first_v_received_r),
- .R(1'b0));
- FDRE \left_align_select_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\left_align_select_r_reg[0]_1 ),
- .Q(\left_align_select_r_reg[0]_0 ),
- .R(1'b0));
- FDRE \left_align_select_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\left_align_select_r_reg[1]_1 ),
- .Q(\left_align_select_r_reg[1]_0 ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT5 #(
- .INIT(32'h00020000))
- \lfsr[15]_i_1
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(got_v_descram_in),
- .I3(Q[0]),
- .I4(\RX_PE_DATA_V_Buffer_reg[0]_0 [0]),
- .O(CHANNEL_UP_Buffer_reg));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT5 #(
- .INIT(32'h00020000))
- \lfsr[15]_i_2
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(got_v_descram_in),
- .I3(Q[1]),
- .I4(\RX_PE_DATA_V_Buffer_reg[0]_0 [1]),
- .O(E));
- FDRE \previous_cycle_control_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXCHARISK[3]),
- .Q(\previous_cycle_control_r_reg[0]_0 ),
- .R(1'b0));
- FDRE \previous_cycle_control_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXCHARISK[2]),
- .Q(previous_cycle_control_r[1]),
- .R(1'b0));
- FDRE \previous_cycle_control_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXCHARISK[1]),
- .Q(previous_cycle_control_r[2]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[24]),
- .Q(\previous_cycle_data_r_reg[7]_0 [0]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[18]),
- .Q(p_2_in[2]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[19]),
- .Q(p_2_in[3]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[20]),
- .Q(p_2_in[4]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[21]),
- .Q(p_2_in[5]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[22]),
- .Q(p_2_in[6]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[23]),
- .Q(p_2_in[7]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[8]),
- .Q(\previous_cycle_data_r_reg_n_0_[16] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[9]),
- .Q(\previous_cycle_data_r_reg_n_0_[17] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[10]),
- .Q(\previous_cycle_data_r_reg_n_0_[18] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[11]),
- .Q(\previous_cycle_data_r_reg_n_0_[19] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[25]),
- .Q(\previous_cycle_data_r_reg[7]_0 [1]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[12]),
- .Q(\previous_cycle_data_r_reg_n_0_[20] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[13]),
- .Q(\previous_cycle_data_r_reg_n_0_[21] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[14]),
- .Q(\previous_cycle_data_r_reg_n_0_[22] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[15]),
- .Q(\previous_cycle_data_r_reg_n_0_[23] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[26]),
- .Q(\previous_cycle_data_r_reg[7]_0 [2]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[27]),
- .Q(\previous_cycle_data_r_reg[7]_0 [3]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[28]),
- .Q(\previous_cycle_data_r_reg[7]_0 [4]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[29]),
- .Q(\previous_cycle_data_r_reg[7]_0 [5]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[30]),
- .Q(\previous_cycle_data_r_reg[7]_0 [6]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[31]),
- .Q(\previous_cycle_data_r_reg[7]_0 [7]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[16]),
- .Q(p_2_in[0]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[17]),
- .Q(p_2_in[1]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__47/i__n_0 ),
- .Q(rx_cc_r[1]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__46/i__n_0 ),
- .Q(rx_cc_r[3]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__45/i__n_0 ),
- .Q(rx_cc_r[5]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__44/i__n_0 ),
- .Q(rx_cc_r[7]),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__24/i__n_0 ),
- .Q(p_21_in),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__23/i__n_0 ),
- .Q(p_6_in22_in),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__22/i__n_0 ),
- .Q(\rx_ecp_d_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__21/i__n_0 ),
- .Q(p_0_in18_in),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__20/i__n_0 ),
- .Q(\rx_ecp_d_r_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__19/i__n_0 ),
- .Q(\rx_ecp_d_r_reg_n_0_[7] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_ecp_r_reg[0]_srl3_i_1
- (.I0(p_0_in26_in),
- .I1(p_3_in),
- .I2(p_6_in22_in),
- .I3(p_21_in),
- .I4(\rx_ecp_d_r_reg_n_0_[3] ),
- .I5(p_6_in34_in),
- .O(p_9_out[1]));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_ecp_r_reg[1]_srl3_i_1
- (.I0(\rx_pe_control_r_reg_n_0_[3] ),
- .I1(p_1_in),
- .I2(\rx_ecp_d_r_reg_n_0_[5] ),
- .I3(p_0_in18_in),
- .I4(\rx_ecp_d_r_reg_n_0_[7] ),
- .I5(p_2_in30_in),
- .O(p_9_out[0]));
- FDRE \rx_pad_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__11/i__n_0 ),
- .Q(rx_pad_d_r[0]),
- .R(1'b0));
- FDRE \rx_pad_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__9/i__n_0 ),
- .Q(rx_pad_d_r[2]),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[0]),
- .Q(p_3_in),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[1]),
- .Q(p_0_in26_in),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[2]),
- .Q(p_1_in),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[3]),
- .Q(\rx_pe_control_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[0] ),
- .Q(rx_pe_data_r[0]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[1]),
- .Q(rx_pe_data_r[10]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[0]),
- .Q(rx_pe_data_r[11]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[12] ),
- .Q(rx_pe_data_r[12]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[13] ),
- .Q(rx_pe_data_r[13]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[14] ),
- .Q(rx_pe_data_r[14]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[15] ),
- .Q(rx_pe_data_r[15]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[16] ),
- .Q(rx_pe_data_r[16]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[17] ),
- .Q(rx_pe_data_r[17]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[18] ),
- .Q(rx_pe_data_r[18]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[19] ),
- .Q(rx_pe_data_r[19]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[1] ),
- .Q(rx_pe_data_r[1]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[20] ),
- .Q(rx_pe_data_r[20]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[21] ),
- .Q(rx_pe_data_r[21]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[22] ),
- .Q(rx_pe_data_r[22]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[23] ),
- .Q(rx_pe_data_r[23]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[24] ),
- .Q(rx_pe_data_r[24]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[25] ),
- .Q(rx_pe_data_r[25]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[26] ),
- .Q(rx_pe_data_r[26]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[27] ),
- .Q(rx_pe_data_r[27]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[28] ),
- .Q(rx_pe_data_r[28]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[29] ),
- .Q(rx_pe_data_r[29]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[2] ),
- .Q(rx_pe_data_r[2]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[30] ),
- .Q(rx_pe_data_r[30]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[31] ),
- .Q(rx_pe_data_r[31]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[3] ),
- .Q(rx_pe_data_r[3]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[4] ),
- .Q(rx_pe_data_r[4]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[5] ),
- .Q(rx_pe_data_r[5]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[6] ),
- .Q(rx_pe_data_r[6]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[7] ),
- .Q(rx_pe_data_r[7]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[3]),
- .Q(rx_pe_data_r[8]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[2]),
- .Q(rx_pe_data_r[9]),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__18/i__n_0 ),
- .Q(p_32_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__17/i__n_0 ),
- .Q(p_6_in34_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__16/i__n_0 ),
- .Q(\rx_scp_d_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__15/i__n_0 ),
- .Q(p_0_in28_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__13/i__n_0 ),
- .Q(p_2_in30_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__12/i__n_0 ),
- .Q(\rx_scp_d_r_reg_n_0_[7] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_scp_r_reg[0]_srl3_i_1
- (.I0(p_0_in26_in),
- .I1(p_3_in),
- .I2(rx_sp_r[1]),
- .I3(p_32_in),
- .I4(\rx_scp_d_r_reg_n_0_[3] ),
- .I5(p_6_in34_in),
- .O(p_8_out[1]));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_scp_r_reg[1]_srl3_i_1
- (.I0(\rx_pe_control_r_reg_n_0_[3] ),
- .I1(p_1_in),
- .I2(rx_spa_r[5]),
- .I3(p_0_in28_in),
- .I4(\rx_scp_d_r_reg_n_0_[7] ),
- .I5(p_2_in30_in),
- .O(p_8_out[0]));
- FDRE \rx_sp_neg_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool16_in),
- .Q(rx_sp_neg_d_r[0]),
- .R(1'b0));
- FDRE \rx_sp_neg_d_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool13_in),
- .Q(rx_sp_neg_d_r[1]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair75" *)
- LUT4 #(
- .INIT(16'h0180))
- \rx_sp_r[2]_i_1
- (.I0(p_0_in[0]),
- .I1(p_0_in[1]),
- .I2(p_0_in[3]),
- .I3(p_0_in[2]),
- .O(\rx_sp_r[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair64" *)
- LUT4 #(
- .INIT(16'h1008))
- \rx_sp_r[3]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[15] ),
- .I1(\word_aligned_data_r_reg_n_0_[13] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[12] ),
- .O(\rx_sp_r[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair66" *)
- LUT4 #(
- .INIT(16'h0810))
- \rx_sp_r[4]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[18] ),
- .I1(\word_aligned_data_r_reg_n_0_[19] ),
- .I2(\word_aligned_data_r_reg_n_0_[17] ),
- .I3(\word_aligned_data_r_reg_n_0_[16] ),
- .O(\rx_sp_r[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair73" *)
- LUT4 #(
- .INIT(16'h1008))
- \rx_sp_r[5]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[21] ),
- .I1(\word_aligned_data_r_reg_n_0_[23] ),
- .I2(\word_aligned_data_r_reg_n_0_[22] ),
- .I3(\word_aligned_data_r_reg_n_0_[20] ),
- .O(\rx_sp_r[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair65" *)
- LUT4 #(
- .INIT(16'h0810))
- \rx_sp_r[6]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[26] ),
- .I1(\word_aligned_data_r_reg_n_0_[27] ),
- .I2(\word_aligned_data_r_reg_n_0_[25] ),
- .I3(\word_aligned_data_r_reg_n_0_[24] ),
- .O(\rx_sp_r[6]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair74" *)
- LUT4 #(
- .INIT(16'h1008))
- \rx_sp_r[7]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[29] ),
- .I1(\word_aligned_data_r_reg_n_0_[31] ),
- .I2(\word_aligned_data_r_reg_n_0_[30] ),
- .I3(\word_aligned_data_r_reg_n_0_[28] ),
- .O(\rx_sp_r[7]_i_1_n_0 ));
- FDRE \rx_sp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__0/i__n_0 ),
- .Q(rx_sp_r[0]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(EXP_IN_n_0),
- .Q(rx_sp_r[1]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[2]_i_1_n_0 ),
- .Q(rx_sp_r[2]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[3]_i_1_n_0 ),
- .Q(rx_sp_r[3]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[4]_i_1_n_0 ),
- .Q(rx_sp_r[4]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[5]_i_1_n_0 ),
- .Q(rx_sp_r[5]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[6]_i_1_n_0 ),
- .Q(rx_sp_r[6]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[7]_i_1_n_0 ),
- .Q(rx_sp_r[7]),
- .R(1'b0));
- FDRE \rx_spa_neg_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__35/i__n_0 ),
- .Q(rx_spa_neg_d_r[0]),
- .R(1'b0));
- FDRE \rx_spa_neg_d_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__34/i__n_0 ),
- .Q(rx_spa_neg_d_r[1]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__32/i__n_0 ),
- .Q(rx_spa_r[2]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__10/i__n_0 ),
- .Q(rx_spa_r[3]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__31/i__n_0 ),
- .Q(rx_spa_r[4]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__14/i__n_0 ),
- .Q(rx_spa_r[5]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__30/i__n_0 ),
- .Q(rx_spa_r[6]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__8/i__n_0 ),
- .Q(rx_spa_r[7]),
- .R(1'b0));
- FDRE \rx_suf_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__26/i__n_0 ),
- .Q(p_15_in),
- .R(1'b0));
- FDRE \rx_suf_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__25/i__n_0 ),
- .Q(p_0_in14_in),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool),
- .Q(rx_v_d_r[2]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__5/i__n_0 ),
- .Q(rx_v_d_r[3]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__4/i__n_0 ),
- .Q(rx_v_d_r[4]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__3/i__n_0 ),
- .Q(rx_v_d_r[5]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__2/i__n_0 ),
- .Q(rx_v_d_r[6]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__1/i__n_0 ),
- .Q(rx_v_d_r[7]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[0]_i_1
- (.I0(\previous_cycle_control_r_reg[0]_0 ),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(previous_cycle_control_r[1]),
- .I4(previous_cycle_control_r[2]),
- .I5(RXCHARISK[0]),
- .O(\word_aligned_control_bits_r[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[1]_i_1
- (.I0(RXCHARISK[0]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_control_r_reg[0]_0 ),
- .I4(previous_cycle_control_r[1]),
- .I5(RXCHARISK[1]),
- .O(\word_aligned_control_bits_r[1]_i_1_n_0 ));
- FDRE \word_aligned_control_bits_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r[0]_i_1_n_0 ),
- .Q(word_aligned_control_bits_r[0]),
- .R(1'b0));
- FDRE \word_aligned_control_bits_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r[1]_i_1_n_0 ),
- .Q(word_aligned_control_bits_r[1]),
- .R(1'b0));
- FDRE \word_aligned_control_bits_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r_reg[2]_0 ),
- .Q(word_aligned_control_bits_r[2]),
- .R(1'b0));
- FDRE \word_aligned_control_bits_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r_reg[3]_0 ),
- .Q(word_aligned_control_bits_r[3]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[0]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [7]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[7]),
- .I4(\previous_cycle_data_r_reg_n_0_[23] ),
- .I5(RXDATA[7]),
- .O(\word_aligned_data_r[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[10]_i_1
- (.I0(RXDATA[5]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [5]),
- .I4(p_2_in[5]),
- .I5(RXDATA[13]),
- .O(\word_aligned_data_r[10]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[11]_i_1
- (.I0(RXDATA[4]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [4]),
- .I4(p_2_in[4]),
- .I5(RXDATA[12]),
- .O(\word_aligned_data_r[11]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[12]_i_1
- (.I0(RXDATA[3]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [3]),
- .I4(p_2_in[3]),
- .I5(RXDATA[11]),
- .O(\word_aligned_data_r[12]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[13]_i_1
- (.I0(RXDATA[2]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [2]),
- .I4(p_2_in[2]),
- .I5(RXDATA[10]),
- .O(\word_aligned_data_r[13]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[14]_i_1
- (.I0(RXDATA[1]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [1]),
- .I4(p_2_in[1]),
- .I5(RXDATA[9]),
- .O(\word_aligned_data_r[14]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[15]_i_1
- (.I0(RXDATA[0]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [0]),
- .I4(p_2_in[0]),
- .I5(RXDATA[8]),
- .O(\word_aligned_data_r[15]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[1]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [6]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[6]),
- .I4(\previous_cycle_data_r_reg_n_0_[22] ),
- .I5(RXDATA[6]),
- .O(\word_aligned_data_r[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[2]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [5]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[5]),
- .I4(\previous_cycle_data_r_reg_n_0_[21] ),
- .I5(RXDATA[5]),
- .O(\word_aligned_data_r[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[3]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [4]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[4]),
- .I4(\previous_cycle_data_r_reg_n_0_[20] ),
- .I5(RXDATA[4]),
- .O(\word_aligned_data_r[3]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[4]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [3]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[3]),
- .I4(\previous_cycle_data_r_reg_n_0_[19] ),
- .I5(RXDATA[3]),
- .O(\word_aligned_data_r[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[5]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [2]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[2]),
- .I4(\previous_cycle_data_r_reg_n_0_[18] ),
- .I5(RXDATA[2]),
- .O(\word_aligned_data_r[5]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[6]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [1]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[1]),
- .I4(\previous_cycle_data_r_reg_n_0_[17] ),
- .I5(RXDATA[1]),
- .O(\word_aligned_data_r[6]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[7]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [0]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[0]),
- .I4(\previous_cycle_data_r_reg_n_0_[16] ),
- .I5(RXDATA[0]),
- .O(\word_aligned_data_r[7]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[8]_i_1
- (.I0(RXDATA[7]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [7]),
- .I4(p_2_in[7]),
- .I5(RXDATA[15]),
- .O(\word_aligned_data_r[8]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[9]_i_1
- (.I0(RXDATA[6]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [6]),
- .I4(p_2_in[6]),
- .I5(RXDATA[14]),
- .O(\word_aligned_data_r[9]_i_1_n_0 ));
- FDRE \word_aligned_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[0]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[10]_i_1_n_0 ),
- .Q(p_0_in[1]),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[11]_i_1_n_0 ),
- .Q(p_0_in[0]),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[12]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[13]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[14]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[15]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [7]),
- .Q(\word_aligned_data_r_reg_n_0_[16] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [6]),
- .Q(\word_aligned_data_r_reg_n_0_[17] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [5]),
- .Q(\word_aligned_data_r_reg_n_0_[18] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [4]),
- .Q(\word_aligned_data_r_reg_n_0_[19] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[1]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [3]),
- .Q(\word_aligned_data_r_reg_n_0_[20] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [2]),
- .Q(\word_aligned_data_r_reg_n_0_[21] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [1]),
- .Q(\word_aligned_data_r_reg_n_0_[22] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [0]),
- .Q(\word_aligned_data_r_reg_n_0_[23] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [7]),
- .Q(\word_aligned_data_r_reg_n_0_[24] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [6]),
- .Q(\word_aligned_data_r_reg_n_0_[25] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [5]),
- .Q(\word_aligned_data_r_reg_n_0_[26] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [4]),
- .Q(\word_aligned_data_r_reg_n_0_[27] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [3]),
- .Q(\word_aligned_data_r_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [2]),
- .Q(\word_aligned_data_r_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[2]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [1]),
- .Q(\word_aligned_data_r_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [0]),
- .Q(\word_aligned_data_r_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[3]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[4]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[5]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[6]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[7]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[8]_i_1_n_0 ),
- .Q(p_0_in[3]),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[9]_i_1_n_0 ),
- .Q(p_0_in[2]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_SYM_GEN_4BYTE" *)
-module east_channel_east_channel_SYM_GEN_4BYTE
- (gen_spa_r,
- gen_cc_r,
- CHANNEL_UP_Buffer_reg,
- \TX_CHAR_IS_K_Buffer_reg[3]_0 ,
- \TX_DATA_Buffer_reg[31]_0 ,
- BYPASS,
- \TX_DATA_Buffer_reg[31]_1 ,
- E,
- D,
- \TX_CHAR_IS_K_Buffer_reg[1]_0 ,
- gen_spa_i,
- user_clk,
- gen_cc_i,
- \fc_nb_r_reg[0]_0 ,
- \fc_nb_r_reg[1]_0 ,
- \fc_nb_r_reg[2]_0 ,
- \bypass_r_reg[0] ,
- reset_lanes_i,
- gen_v_r2,
- \DOUT_reg[0] ,
- Q,
- \gen_v_r_reg[1]_0 ,
- \gen_pad_r_reg[0]_0 ,
- GEN_SP,
- \tx_pe_data_v_r_reg[0]_0 ,
- GEN_SUF,
- GEN_ECP,
- GEN_SCP,
- \gen_r_r_reg[0]_0 ,
- \gen_k_r_reg[0]_0 ,
- \tx_pe_data_r_reg[0]_0 ,
- GEN_A);
- output gen_spa_r;
- output gen_cc_r;
- output [0:0]CHANNEL_UP_Buffer_reg;
- output [3:0]\TX_CHAR_IS_K_Buffer_reg[3]_0 ;
- output [15:0]\TX_DATA_Buffer_reg[31]_0 ;
- output BYPASS;
- output [31:0]\TX_DATA_Buffer_reg[31]_1 ;
- output [0:0]E;
- output [15:0]D;
- output \TX_CHAR_IS_K_Buffer_reg[1]_0 ;
- input gen_spa_i;
- input user_clk;
- input gen_cc_i;
- input \fc_nb_r_reg[0]_0 ;
- input \fc_nb_r_reg[1]_0 ;
- input \fc_nb_r_reg[2]_0 ;
- input \bypass_r_reg[0] ;
- input reset_lanes_i;
- input gen_v_r2;
- input [15:0]\DOUT_reg[0] ;
- input [15:0]Q;
- input [2:0]\gen_v_r_reg[1]_0 ;
- input [1:0]\gen_pad_r_reg[0]_0 ;
- input GEN_SP;
- input [1:0]\tx_pe_data_v_r_reg[0]_0 ;
- input [0:0]GEN_SUF;
- input [0:0]GEN_ECP;
- input [0:0]GEN_SCP;
- input [3:0]\gen_r_r_reg[0]_0 ;
- input [3:0]\gen_k_r_reg[0]_0 ;
- input [31:0]\tx_pe_data_r_reg[0]_0 ;
- input GEN_A;
-
- wire BYPASS;
- wire [0:0]CHANNEL_UP_Buffer_reg;
- wire [15:0]D;
- wire [15:0]\DOUT_reg[0] ;
- wire [0:0]E;
- wire GEN_A;
- wire [0:0]GEN_ECP;
- wire [0:0]GEN_SCP;
- wire GEN_SP;
- wire [0:0]GEN_SUF;
- wire [15:0]Q;
- wire \TX_CHAR_IS_K_Buffer[2]_i_2_n_0 ;
- wire \TX_CHAR_IS_K_Buffer[3]_i_1_n_0 ;
- wire TX_CHAR_IS_K_Buffer_reg0;
- wire TX_CHAR_IS_K_Buffer_reg03_out;
- wire TX_CHAR_IS_K_Buffer_reg08_out;
- wire \TX_CHAR_IS_K_Buffer_reg[1]_0 ;
- wire [3:0]\TX_CHAR_IS_K_Buffer_reg[3]_0 ;
- wire \TX_DATA_Buffer[0]_i_1_n_0 ;
- wire \TX_DATA_Buffer[0]_i_2_n_0 ;
- wire \TX_DATA_Buffer[10]_i_1_n_0 ;
- wire \TX_DATA_Buffer[10]_i_2_n_0 ;
- wire \TX_DATA_Buffer[10]_i_3_n_0 ;
- wire \TX_DATA_Buffer[11]_i_1_n_0 ;
- wire \TX_DATA_Buffer[12]_i_1_n_0 ;
- wire \TX_DATA_Buffer[12]_i_2_n_0 ;
- wire \TX_DATA_Buffer[13]_i_1_n_0 ;
- wire \TX_DATA_Buffer[13]_i_2_n_0 ;
- wire \TX_DATA_Buffer[14]_i_1_n_0 ;
- wire \TX_DATA_Buffer[14]_i_2_n_0 ;
- wire \TX_DATA_Buffer[14]_i_3_n_0 ;
- wire \TX_DATA_Buffer[14]_i_4_n_0 ;
- wire \TX_DATA_Buffer[15]_i_1_n_0 ;
- wire \TX_DATA_Buffer[15]_i_2_n_0 ;
- wire \TX_DATA_Buffer[15]_i_3_n_0 ;
- wire \TX_DATA_Buffer[16]_i_1_n_0 ;
- wire \TX_DATA_Buffer[17]_i_1_n_0 ;
- wire \TX_DATA_Buffer[18]_i_1_n_0 ;
- wire \TX_DATA_Buffer[18]_i_2_n_0 ;
- wire \TX_DATA_Buffer[18]_i_3_n_0 ;
- wire \TX_DATA_Buffer[19]_i_1_n_0 ;
- wire \TX_DATA_Buffer[1]_i_1_n_0 ;
- wire \TX_DATA_Buffer[20]_i_1_n_0 ;
- wire \TX_DATA_Buffer[20]_i_2_n_0 ;
- wire \TX_DATA_Buffer[21]_i_1_n_0 ;
- wire \TX_DATA_Buffer[21]_i_2_n_0 ;
- wire \TX_DATA_Buffer[22]_i_1_n_0 ;
- wire \TX_DATA_Buffer[22]_i_2_n_0 ;
- wire \TX_DATA_Buffer[23]_i_1_n_0 ;
- wire \TX_DATA_Buffer[23]_i_2_n_0 ;
- wire \TX_DATA_Buffer[23]_i_3_n_0 ;
- wire \TX_DATA_Buffer[23]_i_4_n_0 ;
- wire \TX_DATA_Buffer[24]_i_1_n_0 ;
- wire \TX_DATA_Buffer[25]_i_1_n_0 ;
- wire \TX_DATA_Buffer[26]_i_1_n_0 ;
- wire \TX_DATA_Buffer[27]_i_1_n_0 ;
- wire \TX_DATA_Buffer[28]_i_1_n_0 ;
- wire \TX_DATA_Buffer[29]_i_1_n_0 ;
- wire \TX_DATA_Buffer[29]_i_2_n_0 ;
- wire \TX_DATA_Buffer[2]_i_1_n_0 ;
- wire \TX_DATA_Buffer[2]_i_2_n_0 ;
- wire \TX_DATA_Buffer[30]_i_1_n_0 ;
- wire \TX_DATA_Buffer[30]_i_2_n_0 ;
- wire \TX_DATA_Buffer[31]_i_1_n_0 ;
- wire \TX_DATA_Buffer[31]_i_2_n_0 ;
- wire \TX_DATA_Buffer[31]_i_3_n_0 ;
- wire \TX_DATA_Buffer[31]_i_4_n_0 ;
- wire \TX_DATA_Buffer[3]_i_1_n_0 ;
- wire \TX_DATA_Buffer[4]_i_1_n_0 ;
- wire \TX_DATA_Buffer[4]_i_2_n_0 ;
- wire \TX_DATA_Buffer[5]_i_1_n_0 ;
- wire \TX_DATA_Buffer[5]_i_2_n_0 ;
- wire \TX_DATA_Buffer[6]_i_1_n_0 ;
- wire \TX_DATA_Buffer[6]_i_2_n_0 ;
- wire \TX_DATA_Buffer[7]_i_2_n_0 ;
- wire \TX_DATA_Buffer[7]_i_3_n_0 ;
- wire \TX_DATA_Buffer[7]_i_4_n_0 ;
- wire \TX_DATA_Buffer[8]_i_1_n_0 ;
- wire \TX_DATA_Buffer[9]_i_1_n_0 ;
- wire \TX_DATA_Buffer[9]_i_2_n_0 ;
- wire TX_DATA_Buffer_reg0;
- wire [15:0]\TX_DATA_Buffer_reg[31]_0 ;
- wire [31:0]\TX_DATA_Buffer_reg[31]_1 ;
- wire \bypass_r_reg[0] ;
- wire [7:0]data0;
- wire [7:0]data1;
- wire [0:2]fc_nb_r;
- wire \fc_nb_r_reg[0]_0 ;
- wire \fc_nb_r_reg[1]_0 ;
- wire \fc_nb_r_reg[2]_0 ;
- wire gen_a_r;
- wire gen_cc_i;
- wire gen_cc_r;
- wire \gen_ecp_r_reg_n_0_[1] ;
- wire [3:0]\gen_k_r_reg[0]_0 ;
- wire \gen_k_r_reg_n_0_[3] ;
- wire [1:0]\gen_pad_r_reg[0]_0 ;
- wire \gen_pad_r_reg_n_0_[1] ;
- wire [3:0]\gen_r_r_reg[0]_0 ;
- wire \gen_r_r_reg_n_0_[3] ;
- wire gen_sp_r;
- wire gen_spa_i;
- wire gen_spa_r;
- wire gen_v_r2;
- wire [2:0]\gen_v_r_reg[1]_0 ;
- wire \gen_v_r_reg_n_0_[3] ;
- wire p_0_in;
- wire p_0_in12_in;
- wire p_0_in14_in;
- wire p_0_in16_in;
- wire p_0_in4_in;
- wire p_0_in5_in;
- wire p_0_in6_in;
- wire p_0_in8_in;
- wire p_1_in;
- wire p_1_in11_in;
- wire p_1_in16_in;
- wire p_2_in;
- wire reset_lanes_i;
- wire [31:0]\tx_pe_data_r_reg[0]_0 ;
- wire \tx_pe_data_r_reg_n_0_[0] ;
- wire \tx_pe_data_r_reg_n_0_[1] ;
- wire \tx_pe_data_r_reg_n_0_[24] ;
- wire \tx_pe_data_r_reg_n_0_[25] ;
- wire \tx_pe_data_r_reg_n_0_[26] ;
- wire \tx_pe_data_r_reg_n_0_[27] ;
- wire \tx_pe_data_r_reg_n_0_[28] ;
- wire \tx_pe_data_r_reg_n_0_[29] ;
- wire \tx_pe_data_r_reg_n_0_[2] ;
- wire \tx_pe_data_r_reg_n_0_[30] ;
- wire \tx_pe_data_r_reg_n_0_[31] ;
- wire \tx_pe_data_r_reg_n_0_[3] ;
- wire \tx_pe_data_r_reg_n_0_[4] ;
- wire \tx_pe_data_r_reg_n_0_[5] ;
- wire \tx_pe_data_r_reg_n_0_[6] ;
- wire \tx_pe_data_r_reg_n_0_[7] ;
- wire [1:0]\tx_pe_data_v_r_reg[0]_0 ;
- wire \tx_pe_data_v_r_reg_n_0_[1] ;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair127" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [16]),
- .I2(\DOUT_reg[0] [15]),
- .O(\TX_DATA_Buffer_reg[31]_0 [0]));
- (* SOFT_HLUTNM = "soft_lutpair124" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [0]),
- .I2(Q[15]),
- .O(D[0]));
- (* SOFT_HLUTNM = "soft_lutpair125" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [26]),
- .I2(\DOUT_reg[0] [5]),
- .O(\TX_DATA_Buffer_reg[31]_0 [10]));
- (* SOFT_HLUTNM = "soft_lutpair113" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [10]),
- .I2(Q[5]),
- .O(D[10]));
- (* SOFT_HLUTNM = "soft_lutpair123" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [27]),
- .I2(\DOUT_reg[0] [4]),
- .O(\TX_DATA_Buffer_reg[31]_0 [11]));
- (* SOFT_HLUTNM = "soft_lutpair115" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [11]),
- .I2(Q[4]),
- .O(D[11]));
- (* SOFT_HLUTNM = "soft_lutpair122" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [28]),
- .I2(\DOUT_reg[0] [3]),
- .O(\TX_DATA_Buffer_reg[31]_0 [12]));
- (* SOFT_HLUTNM = "soft_lutpair114" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [12]),
- .I2(Q[3]),
- .O(D[12]));
- (* SOFT_HLUTNM = "soft_lutpair121" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [29]),
- .I2(\DOUT_reg[0] [2]),
- .O(\TX_DATA_Buffer_reg[31]_0 [13]));
- (* SOFT_HLUTNM = "soft_lutpair113" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [13]),
- .I2(Q[2]),
- .O(D[13]));
- (* SOFT_HLUTNM = "soft_lutpair120" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [30]),
- .I2(\DOUT_reg[0] [1]),
- .O(\TX_DATA_Buffer_reg[31]_0 [14]));
- (* SOFT_HLUTNM = "soft_lutpair112" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [14]),
- .I2(Q[1]),
- .O(D[14]));
- (* SOFT_HLUTNM = "soft_lutpair119" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [31]),
- .I2(\DOUT_reg[0] [0]),
- .O(\TX_DATA_Buffer_reg[31]_0 [15]));
- (* SOFT_HLUTNM = "soft_lutpair111" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [15]),
- .I2(Q[0]),
- .O(D[15]));
- (* SOFT_HLUTNM = "soft_lutpair119" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [17]),
- .I2(\DOUT_reg[0] [14]),
- .O(\TX_DATA_Buffer_reg[31]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair124" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [1]),
- .I2(Q[14]),
- .O(D[1]));
- (* SOFT_HLUTNM = "soft_lutpair120" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [18]),
- .I2(\DOUT_reg[0] [13]),
- .O(\TX_DATA_Buffer_reg[31]_0 [2]));
- (* SOFT_HLUTNM = "soft_lutpair112" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [2]),
- .I2(Q[13]),
- .O(D[2]));
- (* SOFT_HLUTNM = "soft_lutpair121" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [19]),
- .I2(\DOUT_reg[0] [12]),
- .O(\TX_DATA_Buffer_reg[31]_0 [3]));
- (* SOFT_HLUTNM = "soft_lutpair115" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [3]),
- .I2(Q[12]),
- .O(D[3]));
- (* SOFT_HLUTNM = "soft_lutpair122" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [20]),
- .I2(\DOUT_reg[0] [11]),
- .O(\TX_DATA_Buffer_reg[31]_0 [4]));
- (* SOFT_HLUTNM = "soft_lutpair117" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [4]),
- .I2(Q[11]),
- .O(D[4]));
- (* SOFT_HLUTNM = "soft_lutpair123" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [21]),
- .I2(\DOUT_reg[0] [10]),
- .O(\TX_DATA_Buffer_reg[31]_0 [5]));
- (* SOFT_HLUTNM = "soft_lutpair117" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [5]),
- .I2(Q[10]),
- .O(D[5]));
- (* SOFT_HLUTNM = "soft_lutpair125" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [22]),
- .I2(\DOUT_reg[0] [9]),
- .O(\TX_DATA_Buffer_reg[31]_0 [6]));
- (* SOFT_HLUTNM = "soft_lutpair116" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [6]),
- .I2(Q[9]),
- .O(D[6]));
- (* SOFT_HLUTNM = "soft_lutpair126" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [23]),
- .I2(\DOUT_reg[0] [8]),
- .O(\TX_DATA_Buffer_reg[31]_0 [7]));
- (* SOFT_HLUTNM = "soft_lutpair116" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [7]),
- .I2(Q[8]),
- .O(D[7]));
- (* SOFT_HLUTNM = "soft_lutpair127" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [24]),
- .I2(\DOUT_reg[0] [7]),
- .O(\TX_DATA_Buffer_reg[31]_0 [8]));
- (* SOFT_HLUTNM = "soft_lutpair114" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [8]),
- .I2(Q[7]),
- .O(D[8]));
- (* SOFT_HLUTNM = "soft_lutpair126" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [25]),
- .I2(\DOUT_reg[0] [6]),
- .O(\TX_DATA_Buffer_reg[31]_0 [9]));
- (* SOFT_HLUTNM = "soft_lutpair111" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [9]),
- .I2(Q[6]),
- .O(D[9]));
- LUT6 #(
- .INIT(64'hFFFFFFFF0000000B))
- \TX_CHAR_IS_K_Buffer[0]_i_1
- (.I0(\gen_pad_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(\gen_v_r_reg_n_0_[3] ),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(TX_CHAR_IS_K_Buffer_reg0));
- (* SOFT_HLUTNM = "soft_lutpair103" *)
- LUT5 #(
- .INIT(32'hFFFF0001))
- \TX_CHAR_IS_K_Buffer[1]_i_1
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(p_1_in),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(gen_cc_r),
- .O(TX_CHAR_IS_K_Buffer_reg03_out));
- LUT6 #(
- .INIT(64'hFF00FF45FF00BA00))
- \TX_CHAR_IS_K_Buffer[2]_i_1
- (.I0(p_0_in5_in),
- .I1(p_0_in12_in),
- .I2(p_1_in11_in),
- .I3(gen_cc_r),
- .I4(p_2_in),
- .I5(\TX_CHAR_IS_K_Buffer[2]_i_2_n_0 ),
- .O(TX_CHAR_IS_K_Buffer_reg08_out));
- (* SOFT_HLUTNM = "soft_lutpair118" *)
- LUT3 #(
- .INIT(8'hF1))
- \TX_CHAR_IS_K_Buffer[2]_i_2
- (.I0(gen_sp_r),
- .I1(gen_spa_r),
- .I2(gen_cc_r),
- .O(\TX_CHAR_IS_K_Buffer[2]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair128" *)
- LUT2 #(
- .INIT(4'hB))
- \TX_CHAR_IS_K_Buffer[3]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .O(\TX_CHAR_IS_K_Buffer[3]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(TX_CHAR_IS_K_Buffer_reg0),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(TX_CHAR_IS_K_Buffer_reg03_out),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(TX_CHAR_IS_K_Buffer_reg08_out),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_CHAR_IS_K_Buffer[3]_i_1_n_0 ),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [3]),
- .R(1'b0));
- LUT3 #(
- .INIT(8'hB8))
- \TX_DATA_Buffer[0]_i_1
- (.I0(\TX_DATA_Buffer[0]_i_2_n_0 ),
- .I1(TX_DATA_Buffer_reg0),
- .I2(\TX_DATA_Buffer_reg[31]_1 [0]),
- .O(\TX_DATA_Buffer[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h000044E4))
- \TX_DATA_Buffer[0]_i_2
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(gen_cc_r),
- .I2(\tx_pe_data_r_reg_n_0_[31] ),
- .I3(\gen_pad_r_reg_n_0_[1] ),
- .I4(\gen_ecp_r_reg_n_0_[1] ),
- .O(\TX_DATA_Buffer[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hBB88BB8BBB88B888))
- \TX_DATA_Buffer[10]_i_1
- (.I0(data0[2]),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(p_0_in4_in),
- .I3(\TX_DATA_Buffer[10]_i_2_n_0 ),
- .I4(p_0_in),
- .I5(\TX_DATA_Buffer[10]_i_3_n_0 ),
- .O(\TX_DATA_Buffer[10]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair106" *)
- LUT4 #(
- .INIT(16'hF0FB))
- \TX_DATA_Buffer[10]_i_2
- (.I0(gen_spa_r),
- .I1(p_1_in),
- .I2(gen_cc_r),
- .I3(gen_sp_r),
- .O(\TX_DATA_Buffer[10]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair128" *)
- LUT3 #(
- .INIT(8'hF4))
- \TX_DATA_Buffer[10]_i_3
- (.I0(gen_sp_r),
- .I1(gen_spa_r),
- .I2(gen_cc_r),
- .O(\TX_DATA_Buffer[10]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair109" *)
- LUT4 #(
- .INIT(16'hEAEF))
- \TX_DATA_Buffer[11]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[3]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[11]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBB88BB8BBB88B888))
- \TX_DATA_Buffer[12]_i_1
- (.I0(data0[4]),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(p_0_in4_in),
- .I3(\TX_DATA_Buffer[12]_i_2_n_0 ),
- .I4(p_0_in),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair103" *)
- LUT4 #(
- .INIT(16'hFF01))
- \TX_DATA_Buffer[12]_i_2
- (.I0(p_1_in),
- .I1(gen_sp_r),
- .I2(gen_spa_r),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[12]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hEFEA))
- \TX_DATA_Buffer[13]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[5]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(\TX_DATA_Buffer[13]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[13]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0000FFFFFEFF))
- \TX_DATA_Buffer[13]_i_2
- (.I0(p_0_in4_in),
- .I1(p_1_in),
- .I2(gen_spa_r),
- .I3(p_0_in),
- .I4(gen_cc_r),
- .I5(gen_sp_r),
- .O(\TX_DATA_Buffer[13]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \TX_DATA_Buffer[14]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .O(\TX_DATA_Buffer[14]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBB88BB8BBB88B888))
- \TX_DATA_Buffer[14]_i_2
- (.I0(data0[6]),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(p_0_in4_in),
- .I3(\TX_DATA_Buffer[14]_i_3_n_0 ),
- .I4(p_0_in),
- .I5(\TX_DATA_Buffer[14]_i_4_n_0 ),
- .O(\TX_DATA_Buffer[14]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair106" *)
- LUT4 #(
- .INIT(16'hFFF4))
- \TX_DATA_Buffer[14]_i_3
- (.I0(gen_spa_r),
- .I1(p_1_in),
- .I2(gen_sp_r),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[14]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair118" *)
- LUT3 #(
- .INIT(8'hFD))
- \TX_DATA_Buffer[14]_i_4
- (.I0(gen_spa_r),
- .I1(gen_sp_r),
- .I2(gen_cc_r),
- .O(\TX_DATA_Buffer[14]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[15]_i_1
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(p_0_in),
- .I2(\TX_DATA_Buffer[7]_i_3_n_0 ),
- .I3(p_1_in),
- .I4(p_0_in4_in),
- .I5(\gen_ecp_r_reg_n_0_[1] ),
- .O(\TX_DATA_Buffer[15]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hEFEA))
- \TX_DATA_Buffer[15]_i_2
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[7]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(\TX_DATA_Buffer[15]_i_3_n_0 ),
- .O(\TX_DATA_Buffer[15]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000EF))
- \TX_DATA_Buffer[15]_i_3
- (.I0(p_0_in4_in),
- .I1(p_1_in),
- .I2(p_0_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[15]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h000044E4))
- \TX_DATA_Buffer[16]_i_1
- (.I0(p_1_in11_in),
- .I1(gen_cc_r),
- .I2(data1[0]),
- .I3(p_0_in12_in),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[16]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000000EFE0E0E))
- \TX_DATA_Buffer[17]_i_1
- (.I0(gen_cc_r),
- .I1(gen_sp_r),
- .I2(p_1_in11_in),
- .I3(p_0_in12_in),
- .I4(data1[1]),
- .I5(p_0_in5_in),
- .O(\TX_DATA_Buffer[17]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0001FFFE0000))
- \TX_DATA_Buffer[18]_i_1
- (.I0(p_0_in5_in),
- .I1(\TX_DATA_Buffer[23]_i_3_n_0 ),
- .I2(p_1_in11_in),
- .I3(p_1_in16_in),
- .I4(\TX_DATA_Buffer[18]_i_2_n_0 ),
- .I5(\TX_DATA_Buffer_reg[31]_1 [18]),
- .O(\TX_DATA_Buffer[18]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000054555400))
- \TX_DATA_Buffer[18]_i_2
- (.I0(p_0_in5_in),
- .I1(data1[2]),
- .I2(p_0_in12_in),
- .I3(p_1_in11_in),
- .I4(\TX_DATA_Buffer[18]_i_3_n_0 ),
- .I5(p_1_in16_in),
- .O(\TX_DATA_Buffer[18]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00FF0032))
- \TX_DATA_Buffer[18]_i_3
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(p_0_in6_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[18]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0000DDD1))
- \TX_DATA_Buffer[19]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(p_0_in12_in),
- .I3(data1[3]),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[19]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAEFFAEFFAEFFAEAA))
- \TX_DATA_Buffer[1]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[30] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(gen_sp_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[1]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFEEE2))
- \TX_DATA_Buffer[20]_i_1
- (.I0(\TX_DATA_Buffer[20]_i_2_n_0 ),
- .I1(p_1_in11_in),
- .I2(p_0_in12_in),
- .I3(data1[4]),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[20]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00030002))
- \TX_DATA_Buffer[20]_i_2
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(p_0_in6_in),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[20]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h88B8BBBB88B88888))
- \TX_DATA_Buffer[21]_i_1
- (.I0(fc_nb_r[2]),
- .I1(p_0_in5_in),
- .I2(data1[5]),
- .I3(p_0_in12_in),
- .I4(p_1_in11_in),
- .I5(\TX_DATA_Buffer[21]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[21]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0000FFFFFEFF))
- \TX_DATA_Buffer[21]_i_2
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(gen_spa_r),
- .I3(p_0_in6_in),
- .I4(gen_cc_r),
- .I5(gen_sp_r),
- .O(\TX_DATA_Buffer[21]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h88B8BBBB88B88888))
- \TX_DATA_Buffer[22]_i_1
- (.I0(fc_nb_r[1]),
- .I1(p_0_in5_in),
- .I2(data1[6]),
- .I3(p_0_in12_in),
- .I4(p_1_in11_in),
- .I5(\TX_DATA_Buffer[22]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[22]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF00CD))
- \TX_DATA_Buffer[22]_i_2
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(p_0_in6_in),
- .I3(gen_spa_r),
- .I4(gen_sp_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[22]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \TX_DATA_Buffer[23]_i_1
- (.I0(p_0_in5_in),
- .I1(\TX_DATA_Buffer[23]_i_3_n_0 ),
- .I2(p_1_in11_in),
- .I3(p_1_in16_in),
- .O(\TX_DATA_Buffer[23]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB8BBBBBBB88888))
- \TX_DATA_Buffer[23]_i_2
- (.I0(fc_nb_r[0]),
- .I1(p_0_in5_in),
- .I2(data1[7]),
- .I3(p_0_in12_in),
- .I4(p_1_in11_in),
- .I5(\TX_DATA_Buffer[23]_i_4_n_0 ),
- .O(\TX_DATA_Buffer[23]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[23]_i_3
- (.I0(p_0_in6_in),
- .I1(gen_cc_r),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(p_2_in),
- .I5(p_0_in8_in),
- .O(\TX_DATA_Buffer[23]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000EF))
- \TX_DATA_Buffer[23]_i_4
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(p_0_in6_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[23]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair108" *)
- LUT4 #(
- .INIT(16'h00E2))
- \TX_DATA_Buffer[24]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[7] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[24]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair108" *)
- LUT4 #(
- .INIT(16'h00E2))
- \TX_DATA_Buffer[25]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[6] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[25]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair107" *)
- LUT4 #(
- .INIT(16'hFFE2))
- \TX_DATA_Buffer[26]_i_1
- (.I0(\TX_DATA_Buffer[31]_i_3_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[5] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[26]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair110" *)
- LUT4 #(
- .INIT(16'hFFD1))
- \TX_DATA_Buffer[27]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[4] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[27]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair107" *)
- LUT4 #(
- .INIT(16'hFFE2))
- \TX_DATA_Buffer[28]_i_1
- (.I0(\TX_DATA_Buffer[31]_i_3_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[3] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[28]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h0000FD0D))
- \TX_DATA_Buffer[29]_i_1
- (.I0(p_0_in14_in),
- .I1(\TX_DATA_Buffer[29]_i_2_n_0 ),
- .I2(p_1_in11_in),
- .I3(\tx_pe_data_r_reg_n_0_[2] ),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[29]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair105" *)
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \TX_DATA_Buffer[29]_i_2
- (.I0(gen_a_r),
- .I1(gen_spa_r),
- .I2(gen_sp_r),
- .I3(gen_cc_r),
- .I4(p_0_in16_in),
- .O(\TX_DATA_Buffer[29]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFEFFFEAA))
- \TX_DATA_Buffer[2]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[29] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[2]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00FF0032))
- \TX_DATA_Buffer[2]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(\gen_r_r_reg_n_0_[3] ),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[2]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h00E2))
- \TX_DATA_Buffer[30]_i_1
- (.I0(\TX_DATA_Buffer[30]_i_2_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[1] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[30]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000CD))
- \TX_DATA_Buffer[30]_i_2
- (.I0(p_0_in14_in),
- .I1(gen_a_r),
- .I2(p_0_in16_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[30]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \TX_DATA_Buffer[31]_i_1
- (.I0(p_0_in5_in),
- .I1(\TX_DATA_Buffer[31]_i_3_n_0 ),
- .I2(p_1_in11_in),
- .I3(p_1_in16_in),
- .O(\TX_DATA_Buffer[31]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFE2))
- \TX_DATA_Buffer[31]_i_2
- (.I0(\TX_DATA_Buffer[31]_i_4_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[0] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[31]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[31]_i_3
- (.I0(p_0_in16_in),
- .I1(gen_cc_r),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(gen_a_r),
- .I5(p_0_in14_in),
- .O(\TX_DATA_Buffer[31]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFF0FFFFFFFB))
- \TX_DATA_Buffer[31]_i_4
- (.I0(p_0_in16_in),
- .I1(p_0_in14_in),
- .I2(gen_cc_r),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_a_r),
- .O(\TX_DATA_Buffer[31]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFEAAFEFF))
- \TX_DATA_Buffer[3]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[28] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(gen_cc_r),
- .O(\TX_DATA_Buffer[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFEFFFEAA))
- \TX_DATA_Buffer[4]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[27] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[4]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00030002))
- \TX_DATA_Buffer[4]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(\gen_r_r_reg_n_0_[3] ),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[4]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hAEFFAEAA))
- \TX_DATA_Buffer[5]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[26] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[5]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[5]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0000FFFFFEFF))
- \TX_DATA_Buffer[5]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(gen_spa_r),
- .I3(\gen_r_r_reg_n_0_[3] ),
- .I4(gen_cc_r),
- .I5(gen_sp_r),
- .O(\TX_DATA_Buffer[5]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hAEFFAEAA))
- \TX_DATA_Buffer[6]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[25] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[6]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[6]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF00CD))
- \TX_DATA_Buffer[6]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(\gen_r_r_reg_n_0_[3] ),
- .I3(gen_spa_r),
- .I4(gen_sp_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[7]_i_1
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(\gen_r_r_reg_n_0_[3] ),
- .I2(\TX_DATA_Buffer[7]_i_3_n_0 ),
- .I3(\gen_v_r_reg_n_0_[3] ),
- .I4(\gen_k_r_reg_n_0_[3] ),
- .I5(\gen_ecp_r_reg_n_0_[1] ),
- .O(TX_DATA_Buffer_reg0));
- LUT5 #(
- .INIT(32'hFEFFFEAA))
- \TX_DATA_Buffer[7]_i_2
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[24] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[7]_i_4_n_0 ),
- .O(\TX_DATA_Buffer[7]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair105" *)
- LUT3 #(
- .INIT(8'hFE))
- \TX_DATA_Buffer[7]_i_3
- (.I0(gen_spa_r),
- .I1(gen_sp_r),
- .I2(gen_cc_r),
- .O(\TX_DATA_Buffer[7]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000EF))
- \TX_DATA_Buffer[7]_i_4
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(\gen_r_r_reg_n_0_[3] ),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[7]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair109" *)
- LUT4 #(
- .INIT(16'hEFEA))
- \TX_DATA_Buffer[8]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[0]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[8]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00E2FFFF00E20000))
- \TX_DATA_Buffer[9]_i_1
- (.I0(\TX_DATA_Buffer[9]_i_2_n_0 ),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(data0[1]),
- .I3(\gen_ecp_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .I5(\TX_DATA_Buffer_reg[31]_1 [9]),
- .O(\TX_DATA_Buffer[9]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair110" *)
- LUT2 #(
- .INIT(4'hE))
- \TX_DATA_Buffer[9]_i_2
- (.I0(gen_sp_r),
- .I1(gen_cc_r),
- .O(\TX_DATA_Buffer[9]_i_2_n_0 ));
- FDRE \TX_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_DATA_Buffer[0]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [0]),
- .R(1'b0));
- FDSE \TX_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[10]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [10]),
- .S(\TX_DATA_Buffer[14]_i_1_n_0 ));
- FDSE \TX_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[11]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [11]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[12]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [12]),
- .S(\TX_DATA_Buffer[14]_i_1_n_0 ));
- FDSE \TX_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[13]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [13]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[14]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [14]),
- .S(\TX_DATA_Buffer[14]_i_1_n_0 ));
- FDSE \TX_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[15]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [15]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[16]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [16]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[17]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [17]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_DATA_Buffer[18]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [18]),
- .R(1'b0));
- FDSE \TX_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[19]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [19]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[1]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [1]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[20]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [20]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[21]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [21]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[22]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [22]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[23]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [23]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[24]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [24]),
- .R(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[25]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [25]),
- .R(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[26]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [26]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[27]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [27]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[28]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [28]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[29]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [29]),
- .R(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[2]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [2]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[30]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [30]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[31]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [31]),
- .R(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[3]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [3]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[4]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [4]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[5]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [5]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[6]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [6]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[7]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [7]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[8]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [8]),
- .S(1'b0));
- FDRE \TX_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_DATA_Buffer[9]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair104" *)
- LUT5 #(
- .INIT(32'hFFFEFFFF))
- \bypass_r[0]_i_1__0
- (.I0(\TX_CHAR_IS_K_Buffer_reg[3]_0 [1]),
- .I1(\TX_CHAR_IS_K_Buffer_reg[3]_0 [0]),
- .I2(gen_v_r2),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(\TX_CHAR_IS_K_Buffer_reg[1]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair102" *)
- LUT5 #(
- .INIT(32'hFFFEFFFF))
- \bypass_r[1]_i_1__0
- (.I0(\TX_CHAR_IS_K_Buffer_reg[3]_0 [3]),
- .I1(\TX_CHAR_IS_K_Buffer_reg[3]_0 [2]),
- .I2(gen_v_r2),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(BYPASS));
- FDRE \fc_nb_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\fc_nb_r_reg[0]_0 ),
- .Q(fc_nb_r[0]),
- .R(1'b0));
- FDRE \fc_nb_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\fc_nb_r_reg[1]_0 ),
- .Q(fc_nb_r[1]),
- .R(1'b0));
- FDRE \fc_nb_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\fc_nb_r_reg[2]_0 ),
- .Q(fc_nb_r[2]),
- .R(1'b0));
- FDRE gen_a_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_A),
- .Q(gen_a_r),
- .R(1'b0));
- FDRE gen_cc_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_cc_i),
- .Q(gen_cc_r),
- .R(1'b0));
- FDRE \gen_ecp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_ECP),
- .Q(\gen_ecp_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \gen_k_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [3]),
- .Q(p_0_in16_in),
- .R(1'b0));
- FDRE \gen_k_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [2]),
- .Q(p_0_in8_in),
- .R(1'b0));
- FDRE \gen_k_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [1]),
- .Q(p_0_in4_in),
- .R(1'b0));
- FDRE \gen_k_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [0]),
- .Q(\gen_k_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \gen_pad_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_pad_r_reg[0]_0 [1]),
- .Q(p_0_in12_in),
- .R(1'b0));
- FDRE \gen_pad_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_pad_r_reg[0]_0 [0]),
- .Q(\gen_pad_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \gen_r_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [3]),
- .Q(p_0_in14_in),
- .R(1'b0));
- FDRE \gen_r_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [2]),
- .Q(p_0_in6_in),
- .R(1'b0));
- FDRE \gen_r_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [1]),
- .Q(p_0_in),
- .R(1'b0));
- FDRE \gen_r_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [0]),
- .Q(\gen_r_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \gen_scp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SCP),
- .Q(p_1_in16_in),
- .R(1'b0));
- FDRE gen_sp_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SP),
- .Q(gen_sp_r),
- .R(1'b0));
- FDRE gen_spa_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_spa_i),
- .Q(gen_spa_r),
- .R(1'b0));
- FDRE \gen_suf_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SUF),
- .Q(p_0_in5_in),
- .R(1'b0));
- FDRE \gen_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_v_r_reg[1]_0 [2]),
- .Q(p_2_in),
- .R(1'b0));
- FDRE \gen_v_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_v_r_reg[1]_0 [1]),
- .Q(p_1_in),
- .R(1'b0));
- FDRE \gen_v_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_v_r_reg[1]_0 [0]),
- .Q(\gen_v_r_reg_n_0_[3] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair102" *)
- LUT5 #(
- .INIT(32'h00000002))
- \lfsr[15]_i_1__1
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(gen_v_r2),
- .I3(\TX_CHAR_IS_K_Buffer_reg[3]_0 [2]),
- .I4(\TX_CHAR_IS_K_Buffer_reg[3]_0 [3]),
- .O(CHANNEL_UP_Buffer_reg));
- (* SOFT_HLUTNM = "soft_lutpair104" *)
- LUT5 #(
- .INIT(32'h00000002))
- \lfsr[15]_i_2__0
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(gen_v_r2),
- .I3(\TX_CHAR_IS_K_Buffer_reg[3]_0 [0]),
- .I4(\TX_CHAR_IS_K_Buffer_reg[3]_0 [1]),
- .O(E));
- FDRE \tx_pe_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [31]),
- .Q(\tx_pe_data_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [21]),
- .Q(data1[5]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [20]),
- .Q(data1[4]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [19]),
- .Q(data1[3]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [18]),
- .Q(data1[2]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [17]),
- .Q(data1[1]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [16]),
- .Q(data1[0]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [15]),
- .Q(data0[7]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [14]),
- .Q(data0[6]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [13]),
- .Q(data0[5]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [12]),
- .Q(data0[4]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [30]),
- .Q(\tx_pe_data_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [11]),
- .Q(data0[3]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [10]),
- .Q(data0[2]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [9]),
- .Q(data0[1]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [8]),
- .Q(data0[0]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [7]),
- .Q(\tx_pe_data_r_reg_n_0_[24] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [6]),
- .Q(\tx_pe_data_r_reg_n_0_[25] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [5]),
- .Q(\tx_pe_data_r_reg_n_0_[26] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [4]),
- .Q(\tx_pe_data_r_reg_n_0_[27] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [3]),
- .Q(\tx_pe_data_r_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [2]),
- .Q(\tx_pe_data_r_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [29]),
- .Q(\tx_pe_data_r_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [1]),
- .Q(\tx_pe_data_r_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [0]),
- .Q(\tx_pe_data_r_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [28]),
- .Q(\tx_pe_data_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [27]),
- .Q(\tx_pe_data_r_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [26]),
- .Q(\tx_pe_data_r_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [25]),
- .Q(\tx_pe_data_r_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [24]),
- .Q(\tx_pe_data_r_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [23]),
- .Q(data1[7]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [22]),
- .Q(data1[6]),
- .R(1'b0));
- FDRE \tx_pe_data_v_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_v_r_reg[0]_0 [1]),
- .Q(p_1_in11_in),
- .R(1'b0));
- FDRE \tx_pe_data_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_v_r_reg[0]_0 [0]),
- .Q(\tx_pe_data_v_r_reg_n_0_[1] ),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_TX_LL" *)
-module east_channel_east_channel_TX_LL
- (gen_cc_i,
- tx_dst_rdy,
- ufc_header_r_reg,
- GEN_SCP,
- GEN_ECP,
- GEN_SUF,
- \s_axi_ufc_tx_tdata[0] ,
- \s_axi_ufc_tx_tdata[1] ,
- \s_axi_ufc_tx_tdata[2] ,
- S_AXI_TX_TREADY,
- \ufc_message_count_r_reg[2] ,
- Q,
- \GEN_PAD_Buffer_reg[0] ,
- \TX_PE_DATA_Buffer_reg[0] ,
- user_clk,
- in_frame_r_reg,
- DO_CC_I,
- next_ufc_idle_c,
- S_AXI_UFC_TX_MS,
- S_AXI_TX_TLAST,
- S_AXI_TX_TKEEP,
- \tx_pe_data_v_r_reg[1] ,
- S_AXI_TX_TVALID,
- WARN_CC,
- S_AXI_UFC_TX_REQ,
- S_AXI_TX_TDATA);
- output gen_cc_i;
- output tx_dst_rdy;
- output ufc_header_r_reg;
- output [0:0]GEN_SCP;
- output [0:0]GEN_ECP;
- output [0:0]GEN_SUF;
- output \s_axi_ufc_tx_tdata[0] ;
- output \s_axi_ufc_tx_tdata[1] ;
- output \s_axi_ufc_tx_tdata[2] ;
- output S_AXI_TX_TREADY;
- output \ufc_message_count_r_reg[2] ;
- output [1:0]Q;
- output [1:0]\GEN_PAD_Buffer_reg[0] ;
- output [31:0]\TX_PE_DATA_Buffer_reg[0] ;
- input user_clk;
- input in_frame_r_reg;
- input DO_CC_I;
- input next_ufc_idle_c;
- input [0:2]S_AXI_UFC_TX_MS;
- input S_AXI_TX_TLAST;
- input [0:3]S_AXI_TX_TKEEP;
- input \tx_pe_data_v_r_reg[1] ;
- input S_AXI_TX_TVALID;
- input WARN_CC;
- input S_AXI_UFC_TX_REQ;
- input [0:31]S_AXI_TX_TDATA;
-
- wire D;
- wire DO_CC_I;
- wire [0:0]GEN_ECP;
- wire [1:0]\GEN_PAD_Buffer_reg[0] ;
- wire [0:0]GEN_SCP;
- wire [0:0]GEN_SUF;
- wire [1:0]Q;
- wire [0:31]S_AXI_TX_TDATA;
- wire [0:3]S_AXI_TX_TKEEP;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TREADY;
- wire S_AXI_TX_TVALID;
- wire [0:2]S_AXI_UFC_TX_MS;
- wire S_AXI_UFC_TX_REQ;
- wire [31:0]\TX_PE_DATA_Buffer_reg[0] ;
- wire WARN_CC;
- wire create_gap_for_scp_c043_out;
- wire gen_cc_i;
- wire in_frame_r_reg;
- wire next_ufc_idle_c;
- wire pdu_ok_c;
- wire \s_axi_ufc_tx_tdata[0] ;
- wire \s_axi_ufc_tx_tdata[1] ;
- wire \s_axi_ufc_tx_tdata[2] ;
- wire tx_dst_rdy;
- wire tx_ll_control_i_n_15;
- wire tx_ll_datapath_i_n_0;
- wire \tx_pe_data_v_r_reg[1] ;
- wire ufc_header_r_reg;
- wire \ufc_message_count_r_reg[2] ;
- wire [1:1]ufc_message_i;
- wire user_clk;
-
- east_channel_east_channel_TX_LL_CONTROL tx_ll_control_i
- (.D(create_gap_for_scp_c043_out),
- .DO_CC_I(DO_CC_I),
- .D_0(D),
- .GEN_ECP(GEN_ECP),
- .GEN_SCP(GEN_SCP),
- .GEN_SUF(GEN_SUF),
- .GEN_SUF_Buffer_reg_0(in_frame_r_reg),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TREADY(S_AXI_TX_TREADY),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .S_AXI_UFC_TX_MS(S_AXI_UFC_TX_MS),
- .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
- .TX_DST_RDY_N_Buffer_reg_0(tx_dst_rdy),
- .WARN_CC(WARN_CC),
- .gen_cc_i(gen_cc_i),
- .in_frame_r_reg(tx_ll_datapath_i_n_0),
- .new_pkt_r_reg(tx_ll_control_i_n_15),
- .next_ufc_idle_c(next_ufc_idle_c),
- .pdu_ok_c(pdu_ok_c),
- .\s_axi_ufc_tx_tdata[0] (\s_axi_ufc_tx_tdata[0] ),
- .\s_axi_ufc_tx_tdata[1] (\s_axi_ufc_tx_tdata[1] ),
- .\s_axi_ufc_tx_tdata[2] (\s_axi_ufc_tx_tdata[2] ),
- .sof_to_eof_1_r_reg_0(\tx_pe_data_v_r_reg[1] ),
- .ufc_header_r_reg_0(ufc_header_r_reg),
- .\ufc_message_count_r_reg[2]_0 (\ufc_message_count_r_reg[2] ),
- .ufc_message_i(ufc_message_i),
- .user_clk(user_clk));
- east_channel_east_channel_TX_LL_DATAPATH tx_ll_datapath_i
- (.D(create_gap_for_scp_c043_out),
- .D_0(D),
- .E(pdu_ok_c),
- .\GEN_PAD_Buffer_reg[0]_0 (\GEN_PAD_Buffer_reg[0] ),
- .Q(Q),
- .S_AXI_TX_TDATA(S_AXI_TX_TDATA),
- .S_AXI_TX_TKEEP(S_AXI_TX_TKEEP),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .\TX_PE_DATA_Buffer_reg[0]_0 (\TX_PE_DATA_Buffer_reg[0] ),
- .in_frame_r_reg_0(tx_ll_datapath_i_n_0),
- .in_frame_r_reg_1(in_frame_r_reg),
- .in_frame_r_reg_2(tx_ll_control_i_n_15),
- .tx_dst_rdy(tx_dst_rdy),
- .\tx_pe_data_v_r_reg[1]_0 (\tx_pe_data_v_r_reg[1] ),
- .ufc_message_i(ufc_message_i),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_TX_LL_CONTROL" *)
-module east_channel_east_channel_TX_LL_CONTROL
- (gen_cc_i,
- D_0,
- TX_DST_RDY_N_Buffer_reg_0,
- ufc_header_r_reg_0,
- pdu_ok_c,
- GEN_SCP,
- GEN_ECP,
- GEN_SUF,
- \s_axi_ufc_tx_tdata[0] ,
- \s_axi_ufc_tx_tdata[1] ,
- \s_axi_ufc_tx_tdata[2] ,
- S_AXI_TX_TREADY,
- \ufc_message_count_r_reg[2]_0 ,
- D,
- ufc_message_i,
- new_pkt_r_reg,
- user_clk,
- GEN_SUF_Buffer_reg_0,
- DO_CC_I,
- next_ufc_idle_c,
- S_AXI_UFC_TX_MS,
- S_AXI_TX_TLAST,
- S_AXI_TX_TVALID,
- sof_to_eof_1_r_reg_0,
- WARN_CC,
- S_AXI_UFC_TX_REQ,
- in_frame_r_reg);
- output gen_cc_i;
- output D_0;
- output TX_DST_RDY_N_Buffer_reg_0;
- output ufc_header_r_reg_0;
- output pdu_ok_c;
- output [0:0]GEN_SCP;
- output [0:0]GEN_ECP;
- output [0:0]GEN_SUF;
- output \s_axi_ufc_tx_tdata[0] ;
- output \s_axi_ufc_tx_tdata[1] ;
- output \s_axi_ufc_tx_tdata[2] ;
- output S_AXI_TX_TREADY;
- output \ufc_message_count_r_reg[2]_0 ;
- output [0:0]D;
- output [0:0]ufc_message_i;
- output new_pkt_r_reg;
- input user_clk;
- input GEN_SUF_Buffer_reg_0;
- input DO_CC_I;
- input next_ufc_idle_c;
- input [0:2]S_AXI_UFC_TX_MS;
- input S_AXI_TX_TLAST;
- input S_AXI_TX_TVALID;
- input sof_to_eof_1_r_reg_0;
- input WARN_CC;
- input S_AXI_UFC_TX_REQ;
- input in_frame_r_reg;
-
- wire [0:0]D;
- wire DO_CC_I;
- wire D_0;
- wire [0:0]GEN_ECP;
- wire GEN_ECP_Buffer0;
- wire [0:0]GEN_SCP;
- wire GEN_SCP_Buffer0;
- wire [0:0]GEN_SUF;
- wire GEN_SUF_Buffer_reg_0;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TREADY;
- wire S_AXI_TX_TVALID;
- wire [0:2]S_AXI_UFC_TX_MS;
- wire S_AXI_UFC_TX_REQ;
- wire TX_DST_RDY_N_Buffer_i_2_n_0;
- wire TX_DST_RDY_N_Buffer_i_3_n_0;
- wire TX_DST_RDY_N_Buffer_i_4_n_0;
- wire TX_DST_RDY_N_Buffer_i_6_n_0;
- wire TX_DST_RDY_N_Buffer_reg_0;
- wire WARN_CC;
- wire data_r;
- wire data_to_eof_1_r;
- wire data_to_eof_2_r;
- wire gen_cc_i;
- wire idle_r;
- wire in_frame_r_reg;
- wire new_pkt_r_reg;
- wire next_data_c;
- wire next_data_to_eof_1_c;
- wire next_idle_c;
- wire next_sof_to_data_c;
- wire next_sof_to_eof_1_c;
- wire next_ufc_header_c;
- wire next_ufc_idle_c;
- wire next_ufc_message1_c;
- wire next_ufc_message2_c;
- wire next_ufc_message3_c;
- wire next_ufc_message4_c;
- wire next_ufc_message5_c;
- wire next_ufc_message6_c;
- wire next_ufc_message7_c;
- wire next_ufc_message8_c;
- wire pdu_ok_c;
- wire \s_axi_ufc_tx_tdata[0] ;
- wire \s_axi_ufc_tx_tdata[1] ;
- wire \s_axi_ufc_tx_tdata[2] ;
- wire sof_to_data_r;
- wire sof_to_data_r_i_2_n_0;
- wire sof_to_eof_1_r;
- wire sof_to_eof_1_r_reg_0;
- wire sof_to_eof_2_r;
- wire suf_delay_1_r;
- wire suf_delay_2_r;
- wire tx_dst_rdy_n_c;
- wire ufc_header_r_i_3_n_0;
- wire ufc_header_r_i_4_n_0;
- wire ufc_header_r_reg_0;
- wire ufc_idle_r;
- wire ufc_message1_r;
- wire ufc_message2_r;
- wire ufc_message3_r;
- wire ufc_message4_r;
- wire ufc_message5_r;
- wire ufc_message6_r;
- wire ufc_message7_r;
- wire ufc_message8_r;
- wire [0:2]ufc_message_count_r;
- wire \ufc_message_count_r[0]_i_1_n_0 ;
- wire \ufc_message_count_r[1]_i_1_n_0 ;
- wire \ufc_message_count_r[2]_i_1_n_0 ;
- wire \ufc_message_count_r_reg[2]_0 ;
- wire [0:0]ufc_message_i;
- wire user_clk;
-
- (* srl_bus_name = "U0/\east_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[0]_srl3 " *)
- SRL16E \FC_NB_Buffer_reg[0]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(S_AXI_UFC_TX_MS[0]),
- .Q(\s_axi_ufc_tx_tdata[0] ));
- (* srl_bus_name = "U0/\east_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[1]_srl3 " *)
- SRL16E \FC_NB_Buffer_reg[1]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(S_AXI_UFC_TX_MS[1]),
- .Q(\s_axi_ufc_tx_tdata[1] ));
- (* srl_bus_name = "U0/\east_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[2]_srl3 " *)
- SRL16E \FC_NB_Buffer_reg[2]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(S_AXI_UFC_TX_MS[2]),
- .Q(\s_axi_ufc_tx_tdata[2] ));
- (* SOFT_HLUTNM = "soft_lutpair224" *)
- LUT3 #(
- .INIT(8'h0E))
- GEN_ECP_Buffer_i_1
- (.I0(data_to_eof_2_r),
- .I1(sof_to_eof_2_r),
- .I2(D_0),
- .O(GEN_ECP_Buffer0));
- FDRE GEN_ECP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_ECP_Buffer0),
- .Q(GEN_ECP),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair224" *)
- LUT3 #(
- .INIT(8'h32))
- GEN_SCP_Buffer_i_1
- (.I0(sof_to_data_r),
- .I1(D_0),
- .I2(sof_to_eof_1_r),
- .O(GEN_SCP_Buffer0));
- FDRE GEN_SCP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SCP_Buffer0),
- .Q(GEN_SCP),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE GEN_SUF_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(suf_delay_2_r),
- .Q(GEN_SUF),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair218" *)
- LUT1 #(
- .INIT(2'h1))
- S_AXI_TX_TREADY_INST_0
- (.I0(TX_DST_RDY_N_Buffer_reg_0),
- .O(S_AXI_TX_TREADY));
- LUT6 #(
- .INIT(64'hFFFFFFFFABAAFFFF))
- TX_DST_RDY_N_Buffer_i_1
- (.I0(TX_DST_RDY_N_Buffer_i_2_n_0),
- .I1(D_0),
- .I2(TX_DST_RDY_N_Buffer_i_3_n_0),
- .I3(TX_DST_RDY_N_Buffer_i_4_n_0),
- .I4(\ufc_message_count_r_reg[2]_0 ),
- .I5(DO_CC_I),
- .O(tx_dst_rdy_n_c));
- LUT6 #(
- .INIT(64'hFFFFFFFFF4F4F444))
- TX_DST_RDY_N_Buffer_i_2
- (.I0(WARN_CC),
- .I1(S_AXI_UFC_TX_REQ),
- .I2(D_0),
- .I3(sof_to_eof_1_r),
- .I4(data_to_eof_1_r),
- .I5(TX_DST_RDY_N_Buffer_i_6_n_0),
- .O(TX_DST_RDY_N_Buffer_i_2_n_0));
- (* SOFT_HLUTNM = "soft_lutpair217" *)
- LUT3 #(
- .INIT(8'hDF))
- TX_DST_RDY_N_Buffer_i_3
- (.I0(S_AXI_TX_TVALID),
- .I1(TX_DST_RDY_N_Buffer_reg_0),
- .I2(S_AXI_TX_TLAST),
- .O(TX_DST_RDY_N_Buffer_i_3_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF5554))
- TX_DST_RDY_N_Buffer_i_4
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(data_to_eof_2_r),
- .I2(sof_to_eof_2_r),
- .I3(idle_r),
- .I4(sof_to_data_r),
- .I5(data_r),
- .O(TX_DST_RDY_N_Buffer_i_4_n_0));
- (* SOFT_HLUTNM = "soft_lutpair225" *)
- LUT3 #(
- .INIT(8'hAE))
- TX_DST_RDY_N_Buffer_i_5
- (.I0(ufc_header_r_i_3_n_0),
- .I1(ufc_message_count_r[2]),
- .I2(ufc_header_r_i_4_n_0),
- .O(\ufc_message_count_r_reg[2]_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- TX_DST_RDY_N_Buffer_i_6
- (.I0(data_r),
- .I1(sof_to_data_r),
- .I2(ufc_idle_r),
- .I3(ufc_header_r_reg_0),
- .I4(sof_to_eof_1_r),
- .I5(data_to_eof_1_r),
- .O(TX_DST_RDY_N_Buffer_i_6_n_0));
- FDSE TX_DST_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_dst_rdy_n_c),
- .Q(TX_DST_RDY_N_Buffer_reg_0),
- .S(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair215" *)
- LUT5 #(
- .INIT(32'hEE0EEEEE))
- data_r_i_1
- (.I0(sof_to_data_r),
- .I1(data_r),
- .I2(S_AXI_TX_TLAST),
- .I3(TX_DST_RDY_N_Buffer_reg_0),
- .I4(S_AXI_TX_TVALID),
- .O(next_data_c));
- FDRE data_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_data_c),
- .Q(data_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair215" *)
- LUT5 #(
- .INIT(32'h00E00000))
- data_to_eof_1_r_i_1
- (.I0(sof_to_data_r),
- .I1(data_r),
- .I2(S_AXI_TX_TLAST),
- .I3(TX_DST_RDY_N_Buffer_reg_0),
- .I4(S_AXI_TX_TVALID),
- .O(next_data_to_eof_1_c));
- FDRE data_to_eof_1_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_data_to_eof_1_c),
- .Q(data_to_eof_1_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE data_to_eof_2_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(data_to_eof_1_r),
- .Q(data_to_eof_2_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE do_cc_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(DO_CC_I),
- .Q(D_0),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FDR" *)
- FDRE #(
- .INIT(1'b0))
- gen_cc_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D_0),
- .Q(gen_cc_i),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hEFEFEFEFEFEFEF00))
- idle_r_i_1
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(TX_DST_RDY_N_Buffer_reg_0),
- .I2(S_AXI_TX_TVALID),
- .I3(idle_r),
- .I4(sof_to_eof_2_r),
- .I5(data_to_eof_2_r),
- .O(next_idle_c));
- FDSE idle_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_idle_c),
- .Q(idle_r),
- .S(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair218" *)
- LUT5 #(
- .INIT(32'hF3FF0100))
- in_frame_r_i_1
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(S_AXI_TX_TLAST),
- .I2(TX_DST_RDY_N_Buffer_reg_0),
- .I3(S_AXI_TX_TVALID),
- .I4(in_frame_r_reg),
- .O(new_pkt_r_reg));
- (* SOFT_HLUTNM = "soft_lutpair217" *)
- LUT5 #(
- .INIT(32'h00040000))
- sof_to_data_r_i_1
- (.I0(S_AXI_TX_TLAST),
- .I1(S_AXI_TX_TVALID),
- .I2(TX_DST_RDY_N_Buffer_reg_0),
- .I3(sof_to_eof_1_r_reg_0),
- .I4(sof_to_data_r_i_2_n_0),
- .O(next_sof_to_data_c));
- (* SOFT_HLUTNM = "soft_lutpair216" *)
- LUT3 #(
- .INIT(8'hFE))
- sof_to_data_r_i_2
- (.I0(data_to_eof_2_r),
- .I1(sof_to_eof_2_r),
- .I2(idle_r),
- .O(sof_to_data_r_i_2_n_0));
- FDRE sof_to_data_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_sof_to_data_c),
- .Q(sof_to_data_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair216" *)
- LUT5 #(
- .INIT(32'h11111110))
- sof_to_eof_1_r_i_1
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(TX_DST_RDY_N_Buffer_i_3_n_0),
- .I2(idle_r),
- .I3(sof_to_eof_2_r),
- .I4(data_to_eof_2_r),
- .O(next_sof_to_eof_1_c));
- FDRE sof_to_eof_1_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_sof_to_eof_1_c),
- .Q(sof_to_eof_1_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE sof_to_eof_2_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(sof_to_eof_1_r),
- .Q(sof_to_eof_2_r),
- .R(GEN_SUF_Buffer_reg_0));
- LUT4 #(
- .INIT(16'hFFFE))
- storage_ufc_v_r_i_1
- (.I0(ufc_message2_r),
- .I1(ufc_message8_r),
- .I2(ufc_message6_r),
- .I3(ufc_message4_r),
- .O(ufc_message_i));
- LUT1 #(
- .INIT(2'h1))
- storage_v_r_i_1
- (.I0(D_0),
- .O(pdu_ok_c));
- FDRE suf_delay_1_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ufc_header_r_reg_0),
- .Q(suf_delay_1_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE suf_delay_2_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(suf_delay_1_r),
- .Q(suf_delay_2_r),
- .R(GEN_SUF_Buffer_reg_0));
- LUT2 #(
- .INIT(4'h1))
- \tx_pe_ufc_v_r[1]_i_1
- (.I0(ufc_idle_r),
- .I1(ufc_header_r_reg_0),
- .O(D));
- LUT6 #(
- .INIT(64'h0008000C00080008))
- ufc_header_r_i_2
- (.I0(ufc_header_r_i_3_n_0),
- .I1(S_AXI_UFC_TX_REQ),
- .I2(WARN_CC),
- .I3(DO_CC_I),
- .I4(ufc_header_r_i_4_n_0),
- .I5(ufc_message_count_r[2]),
- .O(next_ufc_header_c));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- ufc_header_r_i_3
- (.I0(ufc_message1_r),
- .I1(ufc_message7_r),
- .I2(ufc_idle_r),
- .I3(ufc_message5_r),
- .I4(ufc_message3_r),
- .O(ufc_header_r_i_3_n_0));
- LUT6 #(
- .INIT(64'h3030505F3F3F505F))
- ufc_header_r_i_4
- (.I0(ufc_message4_r),
- .I1(ufc_message8_r),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_message2_r),
- .I4(ufc_message_count_r[0]),
- .I5(ufc_message6_r),
- .O(ufc_header_r_i_4_n_0));
- FDRE ufc_header_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_header_c),
- .Q(ufc_header_r_reg_0),
- .R(GEN_SUF_Buffer_reg_0));
- FDSE ufc_idle_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_idle_c),
- .Q(ufc_idle_r),
- .S(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair221" *)
- LUT4 #(
- .INIT(16'h0002))
- ufc_message1_r_i_1
- (.I0(ufc_header_r_reg_0),
- .I1(ufc_message_count_r[0]),
- .I2(ufc_message_count_r[2]),
- .I3(ufc_message_count_r[1]),
- .O(next_ufc_message1_c));
- FDRE ufc_message1_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message1_c),
- .Q(ufc_message1_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair221" *)
- LUT4 #(
- .INIT(16'hFE00))
- ufc_message2_r_i_1
- (.I0(ufc_message_count_r[0]),
- .I1(ufc_message_count_r[2]),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_header_r_reg_0),
- .O(next_ufc_message2_c));
- FDRE ufc_message2_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message2_c),
- .Q(ufc_message2_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair222" *)
- LUT4 #(
- .INIT(16'h0400))
- ufc_message3_r_i_1
- (.I0(ufc_message_count_r[2]),
- .I1(ufc_message_count_r[1]),
- .I2(ufc_message_count_r[0]),
- .I3(ufc_message2_r),
- .O(next_ufc_message3_c));
- FDRE ufc_message3_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message3_c),
- .Q(ufc_message3_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair222" *)
- LUT4 #(
- .INIT(16'hF080))
- ufc_message4_r_i_1
- (.I0(ufc_message_count_r[2]),
- .I1(ufc_message_count_r[1]),
- .I2(ufc_message2_r),
- .I3(ufc_message_count_r[0]),
- .O(next_ufc_message4_c));
- FDRE ufc_message4_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message4_c),
- .Q(ufc_message4_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair219" *)
- LUT4 #(
- .INIT(16'h0008))
- ufc_message5_r_i_1
- (.I0(ufc_message4_r),
- .I1(ufc_message_count_r[0]),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_message_count_r[2]),
- .O(next_ufc_message5_c));
- FDRE ufc_message5_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message5_c),
- .Q(ufc_message5_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair219" *)
- LUT4 #(
- .INIT(16'h8880))
- ufc_message6_r_i_1
- (.I0(ufc_message4_r),
- .I1(ufc_message_count_r[0]),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_message_count_r[2]),
- .O(next_ufc_message6_c));
- FDRE ufc_message6_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message6_c),
- .Q(ufc_message6_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair220" *)
- LUT4 #(
- .INIT(16'h4000))
- ufc_message7_r_i_1
- (.I0(ufc_message_count_r[2]),
- .I1(ufc_message_count_r[1]),
- .I2(ufc_message6_r),
- .I3(ufc_message_count_r[0]),
- .O(next_ufc_message7_c));
- FDRE ufc_message7_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message7_c),
- .Q(ufc_message7_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair220" *)
- LUT4 #(
- .INIT(16'h8000))
- ufc_message8_r_i_1
- (.I0(ufc_message_count_r[1]),
- .I1(ufc_message_count_r[2]),
- .I2(ufc_message6_r),
- .I3(ufc_message_count_r[0]),
- .O(next_ufc_message8_c));
- FDRE ufc_message8_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message8_c),
- .Q(ufc_message8_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair223" *)
- LUT3 #(
- .INIT(8'hB8))
- \ufc_message_count_r[0]_i_1
- (.I0(S_AXI_UFC_TX_MS[0]),
- .I1(next_ufc_header_c),
- .I2(ufc_message_count_r[0]),
- .O(\ufc_message_count_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair223" *)
- LUT3 #(
- .INIT(8'hB8))
- \ufc_message_count_r[1]_i_1
- (.I0(S_AXI_UFC_TX_MS[1]),
- .I1(next_ufc_header_c),
- .I2(ufc_message_count_r[1]),
- .O(\ufc_message_count_r[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair225" *)
- LUT3 #(
- .INIT(8'hB8))
- \ufc_message_count_r[2]_i_1
- (.I0(S_AXI_UFC_TX_MS[2]),
- .I1(next_ufc_header_c),
- .I2(ufc_message_count_r[2]),
- .O(\ufc_message_count_r[2]_i_1_n_0 ));
- FDRE \ufc_message_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\ufc_message_count_r[0]_i_1_n_0 ),
- .Q(ufc_message_count_r[0]),
- .R(1'b0));
- FDRE \ufc_message_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\ufc_message_count_r[1]_i_1_n_0 ),
- .Q(ufc_message_count_r[1]),
- .R(1'b0));
- FDRE \ufc_message_count_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\ufc_message_count_r[2]_i_1_n_0 ),
- .Q(ufc_message_count_r[2]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_TX_LL_DATAPATH" *)
-module east_channel_east_channel_TX_LL_DATAPATH
- (in_frame_r_reg_0,
- Q,
- \GEN_PAD_Buffer_reg[0]_0 ,
- \TX_PE_DATA_Buffer_reg[0]_0 ,
- E,
- user_clk,
- ufc_message_i,
- in_frame_r_reg_1,
- in_frame_r_reg_2,
- S_AXI_TX_TLAST,
- S_AXI_TX_TKEEP,
- \tx_pe_data_v_r_reg[1]_0 ,
- S_AXI_TX_TVALID,
- tx_dst_rdy,
- D_0,
- D,
- S_AXI_TX_TDATA);
- output in_frame_r_reg_0;
- output [1:0]Q;
- output [1:0]\GEN_PAD_Buffer_reg[0]_0 ;
- output [31:0]\TX_PE_DATA_Buffer_reg[0]_0 ;
- input [0:0]E;
- input user_clk;
- input [0:0]ufc_message_i;
- input in_frame_r_reg_1;
- input in_frame_r_reg_2;
- input S_AXI_TX_TLAST;
- input [0:3]S_AXI_TX_TKEEP;
- input \tx_pe_data_v_r_reg[1]_0 ;
- input S_AXI_TX_TVALID;
- input tx_dst_rdy;
- input D_0;
- input [0:0]D;
- input [0:31]S_AXI_TX_TDATA;
-
- wire [0:0]D;
- wire D_0;
- wire [0:0]E;
- wire [1:0]\GEN_PAD_Buffer_reg[0]_0 ;
- wire [1:0]Q;
- wire [0:31]S_AXI_TX_TDATA;
- wire [0:3]S_AXI_TX_TKEEP;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TVALID;
- wire [31:0]\TX_PE_DATA_Buffer_reg[0]_0 ;
- wire \gen_pad_r[1]_i_1_n_0 ;
- wire \gen_pad_r_reg_n_0_[0] ;
- wire \gen_pad_r_reg_n_0_[1] ;
- wire in_frame_r_reg_0;
- wire in_frame_r_reg_1;
- wire in_frame_r_reg_2;
- wire p_13_in;
- wire p_3_in;
- wire [1:0]p_3_out;
- wire [1:0]p_4_out;
- wire storage_pad_r;
- wire storage_pad_r0;
- wire storage_pad_r_i_2_n_0;
- wire [0:15]storage_r;
- wire storage_ufc_v_r;
- wire storage_v_r;
- wire storage_v_r0;
- wire tx_dst_rdy;
- wire [0:31]tx_pe_data_r;
- wire \tx_pe_data_v_r_reg[1]_0 ;
- wire \tx_pe_data_v_r_reg_n_0_[0] ;
- wire \tx_pe_data_v_r_reg_n_0_[1] ;
- wire \tx_pe_ufc_v_r_reg_n_0_[1] ;
- wire [0:0]ufc_message_i;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair228" *)
- LUT3 #(
- .INIT(8'h10))
- \GEN_PAD_Buffer[0]_i_1
- (.I0(D_0),
- .I1(p_3_in),
- .I2(\gen_pad_r_reg_n_0_[0] ),
- .O(p_4_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair229" *)
- LUT3 #(
- .INIT(8'h10))
- \GEN_PAD_Buffer[1]_i_1
- (.I0(D_0),
- .I1(\tx_pe_ufc_v_r_reg_n_0_[1] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .O(p_4_out[0]));
- FDRE \GEN_PAD_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_4_out[1]),
- .Q(\GEN_PAD_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \GEN_PAD_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_4_out[0]),
- .Q(\GEN_PAD_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[0]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [31]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[10]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [21]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[11]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [20]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[12]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [19]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[13]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [18]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[14]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [17]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[15]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [16]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[16]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [15]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[17]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [14]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[18]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [13]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[19]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [12]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[1]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [30]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[20]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [11]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[21]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [10]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[22]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [9]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[23]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [8]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[24]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [7]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[25]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [6]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[26]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [5]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[27]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [4]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[28]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [3]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[29]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [2]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[2]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [29]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[30]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[31]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[3]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [28]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[4]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [27]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[5]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [26]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[6]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [25]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[7]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [24]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[8]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [23]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[9]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [22]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair228" *)
- LUT3 #(
- .INIT(8'hF4))
- \TX_PE_DATA_V_Buffer[0]_i_1
- (.I0(D_0),
- .I1(\tx_pe_data_v_r_reg_n_0_[0] ),
- .I2(p_3_in),
- .O(p_3_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair229" *)
- LUT3 #(
- .INIT(8'hF4))
- \TX_PE_DATA_V_Buffer[1]_i_1
- (.I0(D_0),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(\tx_pe_ufc_v_r_reg_n_0_[1] ),
- .O(p_3_out[0]));
- FDRE \TX_PE_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \TX_PE_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[0]),
- .Q(Q[0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair227" *)
- LUT5 #(
- .INIT(32'h00020228))
- \gen_pad_r[1]_i_1
- (.I0(storage_pad_r_i_2_n_0),
- .I1(S_AXI_TX_TKEEP[2]),
- .I2(S_AXI_TX_TKEEP[3]),
- .I3(S_AXI_TX_TKEEP[0]),
- .I4(S_AXI_TX_TKEEP[1]),
- .O(\gen_pad_r[1]_i_1_n_0 ));
- FDRE \gen_pad_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(storage_pad_r),
- .Q(\gen_pad_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \gen_pad_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(\gen_pad_r[1]_i_1_n_0 ),
- .Q(\gen_pad_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE in_frame_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(in_frame_r_reg_2),
- .Q(in_frame_r_reg_0),
- .R(in_frame_r_reg_1));
- (* SOFT_HLUTNM = "soft_lutpair227" *)
- LUT5 #(
- .INIT(32'h28808000))
- storage_pad_r_i_1
- (.I0(storage_pad_r_i_2_n_0),
- .I1(S_AXI_TX_TKEEP[2]),
- .I2(S_AXI_TX_TKEEP[3]),
- .I3(S_AXI_TX_TKEEP[0]),
- .I4(S_AXI_TX_TKEEP[1]),
- .O(storage_pad_r0));
- (* SOFT_HLUTNM = "soft_lutpair226" *)
- LUT5 #(
- .INIT(32'h00D00000))
- storage_pad_r_i_2
- (.I0(\tx_pe_data_v_r_reg[1]_0 ),
- .I1(in_frame_r_reg_0),
- .I2(S_AXI_TX_TLAST),
- .I3(tx_dst_rdy),
- .I4(S_AXI_TX_TVALID),
- .O(storage_pad_r_i_2_n_0));
- FDRE storage_pad_r_reg
- (.C(user_clk),
- .CE(E),
- .D(storage_pad_r0),
- .Q(storage_pad_r),
- .R(1'b0));
- FDRE \storage_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[16]),
- .Q(storage_r[0]),
- .R(1'b0));
- FDRE \storage_r_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[26]),
- .Q(storage_r[10]),
- .R(1'b0));
- FDRE \storage_r_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[27]),
- .Q(storage_r[11]),
- .R(1'b0));
- FDRE \storage_r_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[28]),
- .Q(storage_r[12]),
- .R(1'b0));
- FDRE \storage_r_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[29]),
- .Q(storage_r[13]),
- .R(1'b0));
- FDRE \storage_r_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[30]),
- .Q(storage_r[14]),
- .R(1'b0));
- FDRE \storage_r_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[31]),
- .Q(storage_r[15]),
- .R(1'b0));
- FDRE \storage_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[17]),
- .Q(storage_r[1]),
- .R(1'b0));
- FDRE \storage_r_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[18]),
- .Q(storage_r[2]),
- .R(1'b0));
- FDRE \storage_r_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[19]),
- .Q(storage_r[3]),
- .R(1'b0));
- FDRE \storage_r_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[20]),
- .Q(storage_r[4]),
- .R(1'b0));
- FDRE \storage_r_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[21]),
- .Q(storage_r[5]),
- .R(1'b0));
- FDRE \storage_r_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[22]),
- .Q(storage_r[6]),
- .R(1'b0));
- FDRE \storage_r_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[23]),
- .Q(storage_r[7]),
- .R(1'b0));
- FDRE \storage_r_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[24]),
- .Q(storage_r[8]),
- .R(1'b0));
- FDRE \storage_r_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[25]),
- .Q(storage_r[9]),
- .R(1'b0));
- FDRE storage_ufc_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ufc_message_i),
- .Q(storage_ufc_v_r),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hAAA2A222A222222A))
- storage_v_r_i_2
- (.I0(p_13_in),
- .I1(S_AXI_TX_TLAST),
- .I2(S_AXI_TX_TKEEP[0]),
- .I3(S_AXI_TX_TKEEP[1]),
- .I4(S_AXI_TX_TKEEP[2]),
- .I5(S_AXI_TX_TKEEP[3]),
- .O(storage_v_r0));
- FDRE storage_v_r_reg
- (.C(user_clk),
- .CE(E),
- .D(storage_v_r0),
- .Q(storage_v_r),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[0]),
- .Q(tx_pe_data_r[0]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[10]),
- .Q(tx_pe_data_r[10]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[11]),
- .Q(tx_pe_data_r[11]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[12]),
- .Q(tx_pe_data_r[12]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[13]),
- .Q(tx_pe_data_r[13]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[14]),
- .Q(tx_pe_data_r[14]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[15]),
- .Q(tx_pe_data_r[15]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[16]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[0]),
- .Q(tx_pe_data_r[16]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[17]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[1]),
- .Q(tx_pe_data_r[17]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[18]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[2]),
- .Q(tx_pe_data_r[18]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[19]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[3]),
- .Q(tx_pe_data_r[19]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[1]),
- .Q(tx_pe_data_r[1]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[20]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[4]),
- .Q(tx_pe_data_r[20]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[21]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[5]),
- .Q(tx_pe_data_r[21]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[22]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[6]),
- .Q(tx_pe_data_r[22]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[23]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[7]),
- .Q(tx_pe_data_r[23]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[24]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[8]),
- .Q(tx_pe_data_r[24]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[25]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[9]),
- .Q(tx_pe_data_r[25]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[26]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[10]),
- .Q(tx_pe_data_r[26]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[27]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[11]),
- .Q(tx_pe_data_r[27]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[28]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[12]),
- .Q(tx_pe_data_r[28]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[29]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[13]),
- .Q(tx_pe_data_r[29]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[2]),
- .Q(tx_pe_data_r[2]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[30]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[14]),
- .Q(tx_pe_data_r[30]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[31]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[15]),
- .Q(tx_pe_data_r[31]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[3]),
- .Q(tx_pe_data_r[3]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[4]),
- .Q(tx_pe_data_r[4]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[5]),
- .Q(tx_pe_data_r[5]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[6]),
- .Q(tx_pe_data_r[6]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[7]),
- .Q(tx_pe_data_r[7]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[8]),
- .Q(tx_pe_data_r[8]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[9]),
- .Q(tx_pe_data_r[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair226" *)
- LUT4 #(
- .INIT(16'h00D0))
- \tx_pe_data_v_r[1]_i_1
- (.I0(\tx_pe_data_v_r_reg[1]_0 ),
- .I1(in_frame_r_reg_0),
- .I2(S_AXI_TX_TVALID),
- .I3(tx_dst_rdy),
- .O(p_13_in));
- FDRE \tx_pe_data_v_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(storage_v_r),
- .Q(\tx_pe_data_v_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \tx_pe_data_v_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(p_13_in),
- .Q(\tx_pe_data_v_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \tx_pe_ufc_v_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(storage_ufc_v_r),
- .Q(p_3_in),
- .R(1'b0));
- FDRE \tx_pe_ufc_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(\tx_pe_ufc_v_r_reg_n_0_[1] ),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_BARREL_SHIFTER" *)
-module east_channel_east_channel_UFC_BARREL_SHIFTER
- (SHIFTED_DATA_Buffer,
- \SHIFTED_DATA_Buffer_reg[15]_0 ,
- \SHIFTED_DATA_Buffer_reg[14]_0 ,
- \SHIFTED_DATA_Buffer_reg[13]_0 ,
- \SHIFTED_DATA_Buffer_reg[12]_0 ,
- \SHIFTED_DATA_Buffer_reg[11]_0 ,
- \SHIFTED_DATA_Buffer_reg[10]_0 ,
- \SHIFTED_DATA_Buffer_reg[9]_0 ,
- \SHIFTED_DATA_Buffer_reg[8]_0 ,
- \SHIFTED_DATA_Buffer_reg[7]_0 ,
- \SHIFTED_DATA_Buffer_reg[6]_0 ,
- \SHIFTED_DATA_Buffer_reg[5]_0 ,
- \SHIFTED_DATA_Buffer_reg[4]_0 ,
- \SHIFTED_DATA_Buffer_reg[3]_0 ,
- \SHIFTED_DATA_Buffer_reg[2]_0 ,
- \SHIFTED_DATA_Buffer_reg[1]_0 ,
- \SHIFTED_DATA_Buffer_reg[0]_0 ,
- \SHIFTED_DATA_Buffer_reg[0]_1 ,
- BARREL_SHIFTER_CONTROL_Buffer,
- user_clk,
- UFC_OUTPUT_SELECT_Buffer,
- \MUXED_DATA_Buffer_reg[31] ,
- \MUXED_DATA_Buffer_reg[30] ,
- \MUXED_DATA_Buffer_reg[29] ,
- \MUXED_DATA_Buffer_reg[28] ,
- \MUXED_DATA_Buffer_reg[27] ,
- \MUXED_DATA_Buffer_reg[26] ,
- \MUXED_DATA_Buffer_reg[25] ,
- \MUXED_DATA_Buffer_reg[24] ,
- \MUXED_DATA_Buffer_reg[23] ,
- \MUXED_DATA_Buffer_reg[22] ,
- \MUXED_DATA_Buffer_reg[21] ,
- \MUXED_DATA_Buffer_reg[20] ,
- \MUXED_DATA_Buffer_reg[19] ,
- \MUXED_DATA_Buffer_reg[18] ,
- \MUXED_DATA_Buffer_reg[17] ,
- \MUXED_DATA_Buffer_reg[16] );
- output [0:31]SHIFTED_DATA_Buffer;
- output \SHIFTED_DATA_Buffer_reg[15]_0 ;
- output \SHIFTED_DATA_Buffer_reg[14]_0 ;
- output \SHIFTED_DATA_Buffer_reg[13]_0 ;
- output \SHIFTED_DATA_Buffer_reg[12]_0 ;
- output \SHIFTED_DATA_Buffer_reg[11]_0 ;
- output \SHIFTED_DATA_Buffer_reg[10]_0 ;
- output \SHIFTED_DATA_Buffer_reg[9]_0 ;
- output \SHIFTED_DATA_Buffer_reg[8]_0 ;
- output \SHIFTED_DATA_Buffer_reg[7]_0 ;
- output \SHIFTED_DATA_Buffer_reg[6]_0 ;
- output \SHIFTED_DATA_Buffer_reg[5]_0 ;
- output \SHIFTED_DATA_Buffer_reg[4]_0 ;
- output \SHIFTED_DATA_Buffer_reg[3]_0 ;
- output \SHIFTED_DATA_Buffer_reg[2]_0 ;
- output \SHIFTED_DATA_Buffer_reg[1]_0 ;
- output \SHIFTED_DATA_Buffer_reg[0]_0 ;
- input [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
- input BARREL_SHIFTER_CONTROL_Buffer;
- input user_clk;
- input [0:0]UFC_OUTPUT_SELECT_Buffer;
- input \MUXED_DATA_Buffer_reg[31] ;
- input \MUXED_DATA_Buffer_reg[30] ;
- input \MUXED_DATA_Buffer_reg[29] ;
- input \MUXED_DATA_Buffer_reg[28] ;
- input \MUXED_DATA_Buffer_reg[27] ;
- input \MUXED_DATA_Buffer_reg[26] ;
- input \MUXED_DATA_Buffer_reg[25] ;
- input \MUXED_DATA_Buffer_reg[24] ;
- input \MUXED_DATA_Buffer_reg[23] ;
- input \MUXED_DATA_Buffer_reg[22] ;
- input \MUXED_DATA_Buffer_reg[21] ;
- input \MUXED_DATA_Buffer_reg[20] ;
- input \MUXED_DATA_Buffer_reg[19] ;
- input \MUXED_DATA_Buffer_reg[18] ;
- input \MUXED_DATA_Buffer_reg[17] ;
- input \MUXED_DATA_Buffer_reg[16] ;
-
- wire BARREL_SHIFTER_CONTROL_Buffer;
- wire \MUXED_DATA_Buffer_reg[16] ;
- wire \MUXED_DATA_Buffer_reg[17] ;
- wire \MUXED_DATA_Buffer_reg[18] ;
- wire \MUXED_DATA_Buffer_reg[19] ;
- wire \MUXED_DATA_Buffer_reg[20] ;
- wire \MUXED_DATA_Buffer_reg[21] ;
- wire \MUXED_DATA_Buffer_reg[22] ;
- wire \MUXED_DATA_Buffer_reg[23] ;
- wire \MUXED_DATA_Buffer_reg[24] ;
- wire \MUXED_DATA_Buffer_reg[25] ;
- wire \MUXED_DATA_Buffer_reg[26] ;
- wire \MUXED_DATA_Buffer_reg[27] ;
- wire \MUXED_DATA_Buffer_reg[28] ;
- wire \MUXED_DATA_Buffer_reg[29] ;
- wire \MUXED_DATA_Buffer_reg[30] ;
- wire \MUXED_DATA_Buffer_reg[31] ;
- wire [0:31]SHIFTED_DATA_Buffer;
- wire \SHIFTED_DATA_Buffer_reg[0]_0 ;
- wire [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
- wire \SHIFTED_DATA_Buffer_reg[10]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[11]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[12]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[13]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[14]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[15]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[1]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[2]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[3]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[4]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[5]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[6]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[7]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[8]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[9]_0 ;
- wire [0:0]UFC_OUTPUT_SELECT_Buffer;
- wire [0:15]shifted_data_c;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair191" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[16]_i_1
- (.I0(SHIFTED_DATA_Buffer[0]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[16] ),
- .O(\SHIFTED_DATA_Buffer_reg[0]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair191" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[17]_i_1
- (.I0(SHIFTED_DATA_Buffer[1]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[17] ),
- .O(\SHIFTED_DATA_Buffer_reg[1]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair190" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[18]_i_1
- (.I0(SHIFTED_DATA_Buffer[2]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[18] ),
- .O(\SHIFTED_DATA_Buffer_reg[2]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair190" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[19]_i_1
- (.I0(SHIFTED_DATA_Buffer[3]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[19] ),
- .O(\SHIFTED_DATA_Buffer_reg[3]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair189" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[20]_i_1
- (.I0(SHIFTED_DATA_Buffer[4]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[20] ),
- .O(\SHIFTED_DATA_Buffer_reg[4]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair189" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[21]_i_1
- (.I0(SHIFTED_DATA_Buffer[5]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[21] ),
- .O(\SHIFTED_DATA_Buffer_reg[5]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair188" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[22]_i_1
- (.I0(SHIFTED_DATA_Buffer[6]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[22] ),
- .O(\SHIFTED_DATA_Buffer_reg[6]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair188" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[23]_i_1
- (.I0(SHIFTED_DATA_Buffer[7]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[23] ),
- .O(\SHIFTED_DATA_Buffer_reg[7]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair187" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[24]_i_1
- (.I0(SHIFTED_DATA_Buffer[8]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[24] ),
- .O(\SHIFTED_DATA_Buffer_reg[8]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair187" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[25]_i_1
- (.I0(SHIFTED_DATA_Buffer[9]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[25] ),
- .O(\SHIFTED_DATA_Buffer_reg[9]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair186" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[26]_i_1
- (.I0(SHIFTED_DATA_Buffer[10]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[26] ),
- .O(\SHIFTED_DATA_Buffer_reg[10]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair186" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[27]_i_1
- (.I0(SHIFTED_DATA_Buffer[11]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[27] ),
- .O(\SHIFTED_DATA_Buffer_reg[11]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair185" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[28]_i_1
- (.I0(SHIFTED_DATA_Buffer[12]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[28] ),
- .O(\SHIFTED_DATA_Buffer_reg[12]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair185" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[29]_i_1
- (.I0(SHIFTED_DATA_Buffer[13]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[29] ),
- .O(\SHIFTED_DATA_Buffer_reg[13]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair184" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[30]_i_1
- (.I0(SHIFTED_DATA_Buffer[14]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[30] ),
- .O(\SHIFTED_DATA_Buffer_reg[14]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair184" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[31]_i_1
- (.I0(SHIFTED_DATA_Buffer[15]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[31] ),
- .O(\SHIFTED_DATA_Buffer_reg[15]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair183" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[0]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [31]),
- .O(shifted_data_c[0]));
- (* SOFT_HLUTNM = "soft_lutpair178" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[10]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [21]),
- .O(shifted_data_c[10]));
- (* SOFT_HLUTNM = "soft_lutpair178" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[11]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [20]),
- .O(shifted_data_c[11]));
- (* SOFT_HLUTNM = "soft_lutpair177" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[12]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [19]),
- .O(shifted_data_c[12]));
- (* SOFT_HLUTNM = "soft_lutpair177" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[13]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [18]),
- .O(shifted_data_c[13]));
- (* SOFT_HLUTNM = "soft_lutpair176" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[14]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [17]),
- .O(shifted_data_c[14]));
- (* SOFT_HLUTNM = "soft_lutpair176" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[15]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [16]),
- .O(shifted_data_c[15]));
- (* SOFT_HLUTNM = "soft_lutpair183" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[1]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [30]),
- .O(shifted_data_c[1]));
- (* SOFT_HLUTNM = "soft_lutpair182" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[2]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [29]),
- .O(shifted_data_c[2]));
- (* SOFT_HLUTNM = "soft_lutpair182" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[3]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [28]),
- .O(shifted_data_c[3]));
- (* SOFT_HLUTNM = "soft_lutpair181" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[4]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [27]),
- .O(shifted_data_c[4]));
- (* SOFT_HLUTNM = "soft_lutpair181" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[5]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [26]),
- .O(shifted_data_c[5]));
- (* SOFT_HLUTNM = "soft_lutpair180" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[6]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [25]),
- .O(shifted_data_c[6]));
- (* SOFT_HLUTNM = "soft_lutpair180" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[7]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [24]),
- .O(shifted_data_c[7]));
- (* SOFT_HLUTNM = "soft_lutpair179" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[8]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [23]),
- .O(shifted_data_c[8]));
- (* SOFT_HLUTNM = "soft_lutpair179" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[9]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [22]),
- .O(shifted_data_c[9]));
- FDRE \SHIFTED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[0]),
- .Q(SHIFTED_DATA_Buffer[0]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[10]),
- .Q(SHIFTED_DATA_Buffer[10]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[11]),
- .Q(SHIFTED_DATA_Buffer[11]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[12]),
- .Q(SHIFTED_DATA_Buffer[12]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[13]),
- .Q(SHIFTED_DATA_Buffer[13]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[14]),
- .Q(SHIFTED_DATA_Buffer[14]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[15]),
- .Q(SHIFTED_DATA_Buffer[15]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
- .Q(SHIFTED_DATA_Buffer[16]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
- .Q(SHIFTED_DATA_Buffer[17]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
- .Q(SHIFTED_DATA_Buffer[18]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
- .Q(SHIFTED_DATA_Buffer[19]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[1]),
- .Q(SHIFTED_DATA_Buffer[1]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
- .Q(SHIFTED_DATA_Buffer[20]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
- .Q(SHIFTED_DATA_Buffer[21]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
- .Q(SHIFTED_DATA_Buffer[22]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
- .Q(SHIFTED_DATA_Buffer[23]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
- .Q(SHIFTED_DATA_Buffer[24]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
- .Q(SHIFTED_DATA_Buffer[25]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
- .Q(SHIFTED_DATA_Buffer[26]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
- .Q(SHIFTED_DATA_Buffer[27]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
- .Q(SHIFTED_DATA_Buffer[28]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
- .Q(SHIFTED_DATA_Buffer[29]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[2]),
- .Q(SHIFTED_DATA_Buffer[2]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
- .Q(SHIFTED_DATA_Buffer[30]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
- .Q(SHIFTED_DATA_Buffer[31]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[3]),
- .Q(SHIFTED_DATA_Buffer[3]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[4]),
- .Q(SHIFTED_DATA_Buffer[4]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[5]),
- .Q(SHIFTED_DATA_Buffer[5]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[6]),
- .Q(SHIFTED_DATA_Buffer[6]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[7]),
- .Q(SHIFTED_DATA_Buffer[7]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[8]),
- .Q(SHIFTED_DATA_Buffer[8]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[9]),
- .Q(SHIFTED_DATA_Buffer[9]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_BARREL_SHIFTER_CONTROL" *)
-module east_channel_east_channel_UFC_BARREL_SHIFTER_CONTROL
- (BARREL_SHIFTER_CONTROL_Buffer,
- barrel_shifter_control_i,
- user_clk);
- output BARREL_SHIFTER_CONTROL_Buffer;
- input barrel_shifter_control_i;
- input user_clk;
-
- wire BARREL_SHIFTER_CONTROL_Buffer;
- wire barrel_shifter_control_i;
- wire user_clk;
-
- FDRE \BARREL_SHIFTER_CONTROL_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(barrel_shifter_control_i),
- .Q(BARREL_SHIFTER_CONTROL_Buffer),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_FILTER" *)
-module east_channel_east_channel_UFC_FILTER
- (UFC_START,
- barrel_shifter_control_i,
- D,
- \PDU_ECP_Buffer_reg[0]_0 ,
- user_clk_0,
- user_clk_1,
- user_clk_2,
- user_clk_3,
- user_clk_4,
- user_clk_5,
- user_clk_6,
- user_clk_7,
- user_clk_8,
- user_clk_9,
- user_clk_10,
- user_clk_11,
- user_clk_12,
- user_clk_13,
- user_clk_14,
- user_clk_15,
- user_clk_16,
- user_clk_17,
- user_clk_18,
- user_clk_19,
- user_clk_20,
- user_clk_21,
- user_clk_22,
- user_clk_23,
- user_clk_24,
- user_clk_25,
- user_clk_26,
- user_clk_27,
- user_clk_28,
- user_clk_29,
- user_clk_30,
- user_clk_31,
- \PDU_PAD_Buffer_reg[0]_0 ,
- \PDU_ECP_Buffer_reg[1]_0 ,
- \PDU_ECP_Buffer_reg[0]_1 ,
- \PDU_DATA_V_Buffer_reg[0]_0 ,
- \UFC_DATA_V_Buffer_reg[0]_0 ,
- \PDU_SCP_Buffer_reg[1]_0 ,
- S1_in,
- RESET,
- neqOp,
- user_clk,
- \rx_suf_r_reg[0]_0 ,
- p_8_out,
- p_9_out,
- Q,
- rx_pe_data_striped_i,
- \stage_1_count_value_r_reg[0]_0 ,
- \stage_1_count_value_r_reg[1]_0 ,
- \stage_1_count_value_r_reg[2]_0 ,
- \stage_1_count_value_r_reg[3]_0 ,
- \rx_data_v_r_reg[0]_0 );
- output UFC_START;
- output barrel_shifter_control_i;
- output [1:0]D;
- output [1:0]\PDU_ECP_Buffer_reg[0]_0 ;
- output user_clk_0;
- output user_clk_1;
- output user_clk_2;
- output user_clk_3;
- output user_clk_4;
- output user_clk_5;
- output user_clk_6;
- output user_clk_7;
- output user_clk_8;
- output user_clk_9;
- output user_clk_10;
- output user_clk_11;
- output user_clk_12;
- output user_clk_13;
- output user_clk_14;
- output user_clk_15;
- output user_clk_16;
- output user_clk_17;
- output user_clk_18;
- output user_clk_19;
- output user_clk_20;
- output user_clk_21;
- output user_clk_22;
- output user_clk_23;
- output user_clk_24;
- output user_clk_25;
- output user_clk_26;
- output user_clk_27;
- output user_clk_28;
- output user_clk_29;
- output user_clk_30;
- output user_clk_31;
- output \PDU_PAD_Buffer_reg[0]_0 ;
- output \PDU_ECP_Buffer_reg[1]_0 ;
- output \PDU_ECP_Buffer_reg[0]_1 ;
- output [1:0]\PDU_DATA_V_Buffer_reg[0]_0 ;
- output [1:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
- output \PDU_SCP_Buffer_reg[1]_0 ;
- output S1_in;
- input RESET;
- input neqOp;
- input user_clk;
- input [1:0]\rx_suf_r_reg[0]_0 ;
- input [1:0]p_8_out;
- input [1:0]p_9_out;
- input [1:0]Q;
- input [0:31]rx_pe_data_striped_i;
- input \stage_1_count_value_r_reg[0]_0 ;
- input \stage_1_count_value_r_reg[1]_0 ;
- input \stage_1_count_value_r_reg[2]_0 ;
- input \stage_1_count_value_r_reg[3]_0 ;
- input [1:0]\rx_data_v_r_reg[0]_0 ;
-
- wire [1:0]D;
- wire [0:1]L;
- wire \PDU_DATA_V_Buffer[0]_i_1_n_0 ;
- wire \PDU_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\PDU_DATA_V_Buffer_reg[0]_0 ;
- wire [1:0]\PDU_ECP_Buffer_reg[0]_0 ;
- wire \PDU_ECP_Buffer_reg[0]_1 ;
- wire \PDU_ECP_Buffer_reg[1]_0 ;
- wire [0:1]PDU_PAD;
- wire \PDU_PAD_Buffer_reg[0]_0 ;
- wire \PDU_SCP_Buffer_reg[1]_0 ;
- wire [1:0]Q;
- wire RESET;
- wire S1_in;
- wire \UFC_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
- wire UFC_START;
- wire UFC_START_Buffer_i_1_n_0;
- wire barrel_shifter_control_i;
- wire load_ufc_control_code_r;
- wire neqOp;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [0:1]rx_data_v_r;
- wire [1:0]\rx_data_v_r_reg[0]_0 ;
- wire \rx_ecp_r_reg[0]_srl3_n_0 ;
- wire \rx_ecp_r_reg[1]_srl3_n_0 ;
- wire \rx_pad_r_reg[0]_srl2_n_0 ;
- wire \rx_pad_r_reg[1]_srl2_n_0 ;
- wire [0:31]rx_pe_data_striped_i;
- wire \rx_scp_r_reg[0]_srl3_n_0 ;
- wire \rx_scp_r_reg[1]_srl3_n_0 ;
- wire [1:0]\rx_suf_r_reg[0]_0 ;
- wire \rx_suf_r_reg_n_0_[1] ;
- wire [0:3]stage_1_count_value_r;
- wire \stage_1_count_value_r_reg[0]_0 ;
- wire \stage_1_count_value_r_reg[1]_0 ;
- wire \stage_1_count_value_r_reg[2]_0 ;
- wire \stage_1_count_value_r_reg[3]_0 ;
- wire [0:3]stage_2_count_value_r;
- wire \stage_2_count_value_r[0]_i_1_n_0 ;
- wire \stage_2_count_value_r[1]_i_1_n_0 ;
- wire \stage_2_count_value_r[2]_i_1_n_0 ;
- wire \stage_2_count_value_r[3]_i_1_n_0 ;
- wire [0:0]stage_2_lane_mask_c__0;
- wire user_clk;
- wire user_clk_0;
- wire user_clk_1;
- wire user_clk_10;
- wire user_clk_11;
- wire user_clk_12;
- wire user_clk_13;
- wire user_clk_14;
- wire user_clk_15;
- wire user_clk_16;
- wire user_clk_17;
- wire user_clk_18;
- wire user_clk_19;
- wire user_clk_2;
- wire user_clk_20;
- wire user_clk_21;
- wire user_clk_22;
- wire user_clk_23;
- wire user_clk_24;
- wire user_clk_25;
- wire user_clk_26;
- wire user_clk_27;
- wire user_clk_28;
- wire user_clk_29;
- wire user_clk_3;
- wire user_clk_30;
- wire user_clk_31;
- wire user_clk_4;
- wire user_clk_5;
- wire user_clk_6;
- wire user_clk_7;
- wire user_clk_8;
- wire user_clk_9;
-
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[0]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[0]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[0]),
- .Q(user_clk_0));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[10]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[10]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[10]),
- .Q(user_clk_10));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[11]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[11]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[11]),
- .Q(user_clk_11));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[12]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[12]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[12]),
- .Q(user_clk_12));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[13]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[13]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[13]),
- .Q(user_clk_13));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[14]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[14]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[14]),
- .Q(user_clk_14));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[15]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[15]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[15]),
- .Q(user_clk_15));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[16]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[16]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[16]),
- .Q(user_clk_16));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[17]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[17]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[17]),
- .Q(user_clk_17));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[18]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[18]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[18]),
- .Q(user_clk_18));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[19]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[19]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[19]),
- .Q(user_clk_19));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[1]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[1]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[1]),
- .Q(user_clk_1));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[20]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[20]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[20]),
- .Q(user_clk_20));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[21]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[21]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[21]),
- .Q(user_clk_21));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[22]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[22]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[22]),
- .Q(user_clk_22));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[23]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[23]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[23]),
- .Q(user_clk_23));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[24]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[24]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[24]),
- .Q(user_clk_24));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[25]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[25]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[25]),
- .Q(user_clk_25));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[26]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[26]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[26]),
- .Q(user_clk_26));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[27]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[27]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[27]),
- .Q(user_clk_27));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[28]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[28]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[28]),
- .Q(user_clk_28));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[29]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[29]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[29]),
- .Q(user_clk_29));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[2]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[2]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[2]),
- .Q(user_clk_2));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[30]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[30]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[30]),
- .Q(user_clk_30));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[31]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[31]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[31]),
- .Q(user_clk_31));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[3]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[3]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[3]),
- .Q(user_clk_3));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[4]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[4]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[4]),
- .Q(user_clk_4));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[5]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[5]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[5]),
- .Q(user_clk_5));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[6]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[6]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[6]),
- .Q(user_clk_6));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[7]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[7]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[7]),
- .Q(user_clk_7));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[8]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[8]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[8]),
- .Q(user_clk_8));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[9]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[9]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[9]),
- .Q(user_clk_9));
- (* SOFT_HLUTNM = "soft_lutpair214" *)
- LUT5 #(
- .INIT(32'h88888882))
- \PDU_DATA_V_Buffer[0]_i_1
- (.I0(rx_data_v_r[0]),
- .I1(stage_2_count_value_r[0]),
- .I2(stage_2_count_value_r[1]),
- .I3(stage_2_count_value_r[2]),
- .I4(stage_2_count_value_r[3]),
- .O(\PDU_DATA_V_Buffer[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00000000AA02A802))
- \PDU_DATA_V_Buffer[1]_i_1
- (.I0(rx_data_v_r[1]),
- .I1(stage_2_count_value_r[2]),
- .I2(stage_2_count_value_r[1]),
- .I3(stage_2_count_value_r[0]),
- .I4(stage_2_count_value_r[3]),
- .I5(L[0]),
- .O(\PDU_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \PDU_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\PDU_DATA_V_Buffer[0]_i_1_n_0 ),
- .Q(\PDU_DATA_V_Buffer_reg[0]_0 [1]),
- .R(RESET));
- FDRE \PDU_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\PDU_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(\PDU_DATA_V_Buffer_reg[0]_0 [0]),
- .R(RESET));
- FDRE \PDU_ECP_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_ecp_r_reg[0]_srl3_n_0 ),
- .Q(\PDU_ECP_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \PDU_ECP_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_ecp_r_reg[1]_srl3_n_0 ),
- .Q(\PDU_ECP_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \PDU_PAD_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_pad_r_reg[0]_srl2_n_0 ),
- .Q(PDU_PAD[0]),
- .R(1'b0));
- FDRE \PDU_PAD_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_pad_r_reg[1]_srl2_n_0 ),
- .Q(PDU_PAD[1]),
- .R(1'b0));
- FDRE \PDU_SCP_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_scp_r_reg[0]_srl3_n_0 ),
- .Q(D[1]),
- .R(1'b0));
- FDRE \PDU_SCP_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_scp_r_reg[1]_srl3_n_0 ),
- .Q(D[0]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hAFAFAFBA))
- \UFC_DATA_V_Buffer[1]_i_1
- (.I0(L[0]),
- .I1(stage_2_count_value_r[3]),
- .I2(stage_2_count_value_r[0]),
- .I3(stage_2_count_value_r[1]),
- .I4(stage_2_count_value_r[2]),
- .O(\UFC_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \UFC_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_2_lane_mask_c__0),
- .Q(\UFC_DATA_V_Buffer_reg[0]_0 [1]),
- .R(RESET));
- FDRE \UFC_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(\UFC_DATA_V_Buffer_reg[0]_0 [0]),
- .R(RESET));
- FDRE \UFC_MESSAGE_START_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(L[0]),
- .Q(barrel_shifter_control_i),
- .R(RESET));
- LUT2 #(
- .INIT(4'hE))
- UFC_START_Buffer_i_1
- (.I0(L[0]),
- .I1(L[1]),
- .O(UFC_START_Buffer_i_1_n_0));
- FDRE UFC_START_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_START_Buffer_i_1_n_0),
- .Q(UFC_START),
- .R(RESET));
- LUT1 #(
- .INIT(2'h1))
- data_after_start_muxcy_0_i_1
- (.I0(D[1]),
- .O(S1_in));
- LUT1 #(
- .INIT(2'h1))
- data_after_start_muxcy_1_i_1
- (.I0(D[0]),
- .O(\PDU_SCP_Buffer_reg[1]_0 ));
- LUT2 #(
- .INIT(4'h1))
- in_frame_muxcy_0_i_1
- (.I0(\PDU_ECP_Buffer_reg[0]_0 [1]),
- .I1(D[1]),
- .O(\PDU_ECP_Buffer_reg[0]_1 ));
- LUT2 #(
- .INIT(4'h1))
- in_frame_muxcy_1_i_1
- (.I0(\PDU_ECP_Buffer_reg[0]_0 [0]),
- .I1(D[0]),
- .O(\PDU_ECP_Buffer_reg[1]_0 ));
- FDRE load_ufc_control_code_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(neqOp),
- .Q(load_ufc_control_code_r),
- .R(RESET));
- FDRE \rx_data_v_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_data_v_r_reg[0]_0 [1]),
- .Q(rx_data_v_r[0]),
- .R(RESET));
- FDRE \rx_data_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_data_v_r_reg[0]_0 [0]),
- .Q(rx_data_v_r[1]),
- .R(RESET));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[0]_srl3 " *)
- SRL16E \rx_ecp_r_reg[0]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_9_out[1]),
- .Q(\rx_ecp_r_reg[0]_srl3_n_0 ));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[1]_srl3 " *)
- SRL16E \rx_ecp_r_reg[1]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_9_out[0]),
- .Q(\rx_ecp_r_reg[1]_srl3_n_0 ));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg[0]_srl2 " *)
- SRL16E \rx_pad_r_reg[0]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(Q[1]),
- .Q(\rx_pad_r_reg[0]_srl2_n_0 ));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg[1]_srl2 " *)
- SRL16E \rx_pad_r_reg[1]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(Q[0]),
- .Q(\rx_pad_r_reg[1]_srl2_n_0 ));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg[0]_srl3 " *)
- SRL16E \rx_scp_r_reg[0]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_8_out[1]),
- .Q(\rx_scp_r_reg[0]_srl3_n_0 ));
- (* srl_bus_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg " *)
- (* srl_name = "U0/\east_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg[1]_srl3 " *)
- SRL16E \rx_scp_r_reg[1]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_8_out[0]),
- .Q(\rx_scp_r_reg[1]_srl3_n_0 ));
- FDRE \rx_suf_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_suf_r_reg[0]_0 [1]),
- .Q(L[0]),
- .R(RESET));
- FDRE \rx_suf_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_suf_r_reg[0]_0 [0]),
- .Q(\rx_suf_r_reg_n_0_[1] ),
- .R(RESET));
- FDRE save_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_suf_r_reg_n_0_[1] ),
- .Q(L[1]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[0]_0 ),
- .Q(stage_1_count_value_r[0]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[1]_0 ),
- .Q(stage_1_count_value_r[1]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[2]_0 ),
- .Q(stage_1_count_value_r[2]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[3]_0 ),
- .Q(stage_1_count_value_r[3]),
- .R(RESET));
- LUT2 #(
- .INIT(4'hE))
- stage_1_pad_r_i_1
- (.I0(PDU_PAD[0]),
- .I1(PDU_PAD[1]),
- .O(\PDU_PAD_Buffer_reg[0]_0 ));
- LUT2 #(
- .INIT(4'h8))
- \stage_2_count_value_r[0]_i_1
- (.I0(load_ufc_control_code_r),
- .I1(stage_1_count_value_r[0]),
- .O(\stage_2_count_value_r[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8B888B88888888B8))
- \stage_2_count_value_r[1]_i_1
- (.I0(stage_1_count_value_r[1]),
- .I1(load_ufc_control_code_r),
- .I2(stage_2_count_value_r[0]),
- .I3(stage_2_count_value_r[1]),
- .I4(stage_2_count_value_r[3]),
- .I5(stage_2_count_value_r[2]),
- .O(\stage_2_count_value_r[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h888B888B88888B88))
- \stage_2_count_value_r[2]_i_1
- (.I0(stage_1_count_value_r[2]),
- .I1(load_ufc_control_code_r),
- .I2(stage_2_count_value_r[2]),
- .I3(stage_2_count_value_r[0]),
- .I4(stage_2_count_value_r[3]),
- .I5(stage_2_count_value_r[1]),
- .O(\stage_2_count_value_r[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8B8B8B8888888888))
- \stage_2_count_value_r[3]_i_1
- (.I0(stage_1_count_value_r[3]),
- .I1(load_ufc_control_code_r),
- .I2(stage_2_count_value_r[0]),
- .I3(stage_2_count_value_r[2]),
- .I4(stage_2_count_value_r[1]),
- .I5(stage_2_count_value_r[3]),
- .O(\stage_2_count_value_r[3]_i_1_n_0 ));
- FDRE \stage_2_count_value_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[0]_i_1_n_0 ),
- .Q(stage_2_count_value_r[0]),
- .R(RESET));
- FDRE \stage_2_count_value_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[1]_i_1_n_0 ),
- .Q(stage_2_count_value_r[1]),
- .R(RESET));
- FDRE \stage_2_count_value_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[2]_i_1_n_0 ),
- .Q(stage_2_count_value_r[2]),
- .R(RESET));
- FDRE \stage_2_count_value_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[3]_i_1_n_0 ),
- .Q(stage_2_count_value_r[3]),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair214" *)
- LUT4 #(
- .INIT(16'h01FE))
- stage_2_lane_mask_c
- (.I0(stage_2_count_value_r[3]),
- .I1(stage_2_count_value_r[2]),
- .I2(stage_2_count_value_r[1]),
- .I3(stage_2_count_value_r[0]),
- .O(stage_2_lane_mask_c__0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_OUTPUT_MUX" *)
-module east_channel_east_channel_UFC_OUTPUT_MUX
- (M_AXI_UFC_RX_TDATA,
- D,
- user_clk,
- UFC_OUTPUT_SELECT_Buffer,
- \MUXED_DATA_Buffer_reg[16]_0 ,
- \MUXED_DATA_Buffer_reg[17]_0 ,
- \MUXED_DATA_Buffer_reg[18]_0 ,
- \MUXED_DATA_Buffer_reg[19]_0 ,
- \MUXED_DATA_Buffer_reg[20]_0 ,
- \MUXED_DATA_Buffer_reg[21]_0 ,
- \MUXED_DATA_Buffer_reg[22]_0 ,
- \MUXED_DATA_Buffer_reg[23]_0 ,
- \MUXED_DATA_Buffer_reg[24]_0 ,
- \MUXED_DATA_Buffer_reg[25]_0 ,
- \MUXED_DATA_Buffer_reg[26]_0 ,
- \MUXED_DATA_Buffer_reg[27]_0 ,
- \MUXED_DATA_Buffer_reg[28]_0 ,
- \MUXED_DATA_Buffer_reg[29]_0 ,
- \MUXED_DATA_Buffer_reg[30]_0 ,
- \MUXED_DATA_Buffer_reg[31]_0 );
- output [0:31]M_AXI_UFC_RX_TDATA;
- input [15:0]D;
- input user_clk;
- input [0:0]UFC_OUTPUT_SELECT_Buffer;
- input \MUXED_DATA_Buffer_reg[16]_0 ;
- input \MUXED_DATA_Buffer_reg[17]_0 ;
- input \MUXED_DATA_Buffer_reg[18]_0 ;
- input \MUXED_DATA_Buffer_reg[19]_0 ;
- input \MUXED_DATA_Buffer_reg[20]_0 ;
- input \MUXED_DATA_Buffer_reg[21]_0 ;
- input \MUXED_DATA_Buffer_reg[22]_0 ;
- input \MUXED_DATA_Buffer_reg[23]_0 ;
- input \MUXED_DATA_Buffer_reg[24]_0 ;
- input \MUXED_DATA_Buffer_reg[25]_0 ;
- input \MUXED_DATA_Buffer_reg[26]_0 ;
- input \MUXED_DATA_Buffer_reg[27]_0 ;
- input \MUXED_DATA_Buffer_reg[28]_0 ;
- input \MUXED_DATA_Buffer_reg[29]_0 ;
- input \MUXED_DATA_Buffer_reg[30]_0 ;
- input \MUXED_DATA_Buffer_reg[31]_0 ;
-
- wire [15:0]D;
- wire \MUXED_DATA_Buffer_reg[16]_0 ;
- wire \MUXED_DATA_Buffer_reg[17]_0 ;
- wire \MUXED_DATA_Buffer_reg[18]_0 ;
- wire \MUXED_DATA_Buffer_reg[19]_0 ;
- wire \MUXED_DATA_Buffer_reg[20]_0 ;
- wire \MUXED_DATA_Buffer_reg[21]_0 ;
- wire \MUXED_DATA_Buffer_reg[22]_0 ;
- wire \MUXED_DATA_Buffer_reg[23]_0 ;
- wire \MUXED_DATA_Buffer_reg[24]_0 ;
- wire \MUXED_DATA_Buffer_reg[25]_0 ;
- wire \MUXED_DATA_Buffer_reg[26]_0 ;
- wire \MUXED_DATA_Buffer_reg[27]_0 ;
- wire \MUXED_DATA_Buffer_reg[28]_0 ;
- wire \MUXED_DATA_Buffer_reg[29]_0 ;
- wire \MUXED_DATA_Buffer_reg[30]_0 ;
- wire \MUXED_DATA_Buffer_reg[31]_0 ;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [0:0]UFC_OUTPUT_SELECT_Buffer;
- wire user_clk;
-
- FDRE \MUXED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[15]),
- .Q(M_AXI_UFC_RX_TDATA[0]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[5]),
- .Q(M_AXI_UFC_RX_TDATA[10]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[4]),
- .Q(M_AXI_UFC_RX_TDATA[11]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[3]),
- .Q(M_AXI_UFC_RX_TDATA[12]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[2]),
- .Q(M_AXI_UFC_RX_TDATA[13]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(M_AXI_UFC_RX_TDATA[14]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(M_AXI_UFC_RX_TDATA[15]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[16]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[16]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[17]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[17]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[18]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[18]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[19]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[19]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[14]),
- .Q(M_AXI_UFC_RX_TDATA[1]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[20]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[20]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[21]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[21]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[22]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[22]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[23]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[23]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[24]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[24]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[25]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[25]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[26]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[26]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[27]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[27]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[28]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[28]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[29]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[29]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[13]),
- .Q(M_AXI_UFC_RX_TDATA[2]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[30]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[30]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[31]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[31]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[12]),
- .Q(M_AXI_UFC_RX_TDATA[3]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[11]),
- .Q(M_AXI_UFC_RX_TDATA[4]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[10]),
- .Q(M_AXI_UFC_RX_TDATA[5]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[9]),
- .Q(M_AXI_UFC_RX_TDATA[6]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[8]),
- .Q(M_AXI_UFC_RX_TDATA[7]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[7]),
- .Q(M_AXI_UFC_RX_TDATA[8]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[6]),
- .Q(M_AXI_UFC_RX_TDATA[9]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_OUTPUT_SWITCH_CONTROL" *)
-module east_channel_east_channel_UFC_OUTPUT_SWITCH_CONTROL
- (UFC_OUTPUT_SELECT_Buffer,
- Q,
- \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ,
- user_clk);
- output [1:0]UFC_OUTPUT_SELECT_Buffer;
- input [1:0]Q;
- input \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ;
- input user_clk;
-
- wire [1:0]Q;
- wire [1:0]UFC_OUTPUT_SELECT_Buffer;
- wire \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ;
- wire \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'h4))
- \UFC_OUTPUT_SELECT_Buffer[5]_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ));
- FDRE \UFC_OUTPUT_SELECT_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ),
- .Q(UFC_OUTPUT_SELECT_Buffer[1]),
- .R(1'b0));
- FDRE \UFC_OUTPUT_SELECT_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ),
- .Q(UFC_OUTPUT_SELECT_Buffer[0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_SIDEBAND_OUTPUT" *)
-module east_channel_east_channel_UFC_SIDEBAND_OUTPUT
- (\UFC_REM_Buffer_reg[0]_0 ,
- UFC_SRC_RDY_N_Buffer,
- UFC_EOF_N_Buffer,
- \UFC_REM_Buffer_reg[0]_1 ,
- user_clk,
- RESET,
- UFC_SRC_RDY_N_Buffer_reg_0,
- UFC_EOF_N_Buffer_reg_0);
- output \UFC_REM_Buffer_reg[0]_0 ;
- output UFC_SRC_RDY_N_Buffer;
- output UFC_EOF_N_Buffer;
- input \UFC_REM_Buffer_reg[0]_1 ;
- input user_clk;
- input RESET;
- input UFC_SRC_RDY_N_Buffer_reg_0;
- input UFC_EOF_N_Buffer_reg_0;
-
- wire RESET;
- wire UFC_EOF_N_Buffer;
- wire UFC_EOF_N_Buffer_reg_0;
- wire \UFC_REM_Buffer_reg[0]_0 ;
- wire \UFC_REM_Buffer_reg[0]_1 ;
- wire UFC_SRC_RDY_N_Buffer;
- wire UFC_SRC_RDY_N_Buffer_reg_0;
- wire user_clk;
-
- FDRE UFC_EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_EOF_N_Buffer_reg_0),
- .Q(UFC_EOF_N_Buffer),
- .R(1'b0));
- FDRE \UFC_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_REM_Buffer_reg[0]_1 ),
- .Q(\UFC_REM_Buffer_reg[0]_0 ),
- .R(1'b0));
- FDSE UFC_SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_SRC_RDY_N_Buffer_reg_0),
- .Q(UFC_SRC_RDY_N_Buffer),
- .S(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_STORAGE_COUNT_CONTROL" *)
-module east_channel_east_channel_UFC_STORAGE_COUNT_CONTROL
- (stage_1_ufc_start_r_reg,
- Q,
- \storage_count_r_reg[1]_0 ,
- \storage_count_r_reg[1]_1 ,
- D,
- \storage_count_r_reg[0]_0 ,
- stage_1_ufc_start_r_reg_0,
- stage_1_ufc_start_r,
- UFC_EOF_N_Buffer_reg,
- RESET,
- user_clk);
- output stage_1_ufc_start_r_reg;
- output [1:0]Q;
- output \storage_count_r_reg[1]_0 ;
- output \storage_count_r_reg[1]_1 ;
- output [0:0]D;
- output \storage_count_r_reg[0]_0 ;
- output stage_1_ufc_start_r_reg_0;
- input stage_1_ufc_start_r;
- input [1:0]UFC_EOF_N_Buffer_reg;
- input RESET;
- input user_clk;
-
- wire [0:0]D;
- wire [1:0]Q;
- wire RESET;
- wire [1:0]UFC_EOF_N_Buffer_reg;
- wire stage_1_ufc_start_r;
- wire stage_1_ufc_start_r_reg;
- wire stage_1_ufc_start_r_reg_0;
- wire [0:1]storage_count_c;
- wire \storage_count_r_reg[0]_0 ;
- wire \storage_count_r_reg[1]_0 ;
- wire \storage_count_r_reg[1]_1 ;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair192" *)
- LUT5 #(
- .INIT(32'h55547733))
- UFC_EOF_N_Buffer_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[0]),
- .I2(UFC_EOF_N_Buffer_reg[0]),
- .I3(UFC_EOF_N_Buffer_reg[1]),
- .I4(Q[1]),
- .O(stage_1_ufc_start_r_reg));
- (* SOFT_HLUTNM = "soft_lutpair194" *)
- LUT4 #(
- .INIT(16'h6433))
- \UFC_REM_Buffer[0]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[0]),
- .I2(Q[1]),
- .I3(UFC_EOF_N_Buffer_reg[0]),
- .O(stage_1_ufc_start_r_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair195" *)
- LUT2 #(
- .INIT(4'h1))
- UFC_SRC_RDY_N_Buffer_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\storage_count_r_reg[0]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair194" *)
- LUT2 #(
- .INIT(4'h8))
- \UFC_STORAGE_SELECT_Buffer[0]_i_2
- (.I0(Q[0]),
- .I1(Q[1]),
- .O(\storage_count_r_reg[1]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair195" *)
- LUT2 #(
- .INIT(4'h9))
- \UFC_STORAGE_SELECT_Buffer[1]_i_1
- (.I0(Q[0]),
- .I1(Q[1]),
- .O(\storage_count_r_reg[1]_1 ));
- (* SOFT_HLUTNM = "soft_lutpair193" *)
- LUT4 #(
- .INIT(16'hABFF))
- \UFC_STORAGE_SELECT_Buffer[5]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[1]),
- .I2(UFC_EOF_N_Buffer_reg[1]),
- .I3(Q[0]),
- .O(D));
- (* SOFT_HLUTNM = "soft_lutpair193" *)
- LUT5 #(
- .INIT(32'h9CC8C8C8))
- \storage_count_r[0]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(UFC_EOF_N_Buffer_reg[1]),
- .I2(Q[1]),
- .I3(Q[0]),
- .I4(UFC_EOF_N_Buffer_reg[0]),
- .O(storage_count_c[0]));
- (* SOFT_HLUTNM = "soft_lutpair192" *)
- LUT5 #(
- .INIT(32'hAAFE5400))
- \storage_count_r[1]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(UFC_EOF_N_Buffer_reg[1]),
- .I2(Q[1]),
- .I3(Q[0]),
- .I4(UFC_EOF_N_Buffer_reg[0]),
- .O(storage_count_c[1]));
- FDRE \storage_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(storage_count_c[0]),
- .Q(Q[1]),
- .R(RESET));
- FDRE \storage_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(storage_count_c[1]),
- .Q(Q[0]),
- .R(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_STORAGE_MUX" *)
-module east_channel_east_channel_UFC_STORAGE_MUX
- (D,
- \MUXED_DATA_Buffer_reg[16]_0 ,
- \MUXED_DATA_Buffer_reg[17]_0 ,
- \MUXED_DATA_Buffer_reg[18]_0 ,
- \MUXED_DATA_Buffer_reg[19]_0 ,
- \MUXED_DATA_Buffer_reg[20]_0 ,
- \MUXED_DATA_Buffer_reg[21]_0 ,
- \MUXED_DATA_Buffer_reg[22]_0 ,
- \MUXED_DATA_Buffer_reg[23]_0 ,
- \MUXED_DATA_Buffer_reg[24]_0 ,
- \MUXED_DATA_Buffer_reg[25]_0 ,
- \MUXED_DATA_Buffer_reg[26]_0 ,
- \MUXED_DATA_Buffer_reg[27]_0 ,
- \MUXED_DATA_Buffer_reg[28]_0 ,
- \MUXED_DATA_Buffer_reg[29]_0 ,
- \MUXED_DATA_Buffer_reg[30]_0 ,
- \MUXED_DATA_Buffer_reg[31]_0 ,
- \MUXED_DATA_Buffer_reg[0]_0 ,
- user_clk,
- UFC_STORAGE_SELECT_Buffer,
- SHIFTED_DATA_Buffer);
- output [15:0]D;
- output \MUXED_DATA_Buffer_reg[16]_0 ;
- output \MUXED_DATA_Buffer_reg[17]_0 ;
- output \MUXED_DATA_Buffer_reg[18]_0 ;
- output \MUXED_DATA_Buffer_reg[19]_0 ;
- output \MUXED_DATA_Buffer_reg[20]_0 ;
- output \MUXED_DATA_Buffer_reg[21]_0 ;
- output \MUXED_DATA_Buffer_reg[22]_0 ;
- output \MUXED_DATA_Buffer_reg[23]_0 ;
- output \MUXED_DATA_Buffer_reg[24]_0 ;
- output \MUXED_DATA_Buffer_reg[25]_0 ;
- output \MUXED_DATA_Buffer_reg[26]_0 ;
- output \MUXED_DATA_Buffer_reg[27]_0 ;
- output \MUXED_DATA_Buffer_reg[28]_0 ;
- output \MUXED_DATA_Buffer_reg[29]_0 ;
- output \MUXED_DATA_Buffer_reg[30]_0 ;
- output \MUXED_DATA_Buffer_reg[31]_0 ;
- input \MUXED_DATA_Buffer_reg[0]_0 ;
- input user_clk;
- input [2:0]UFC_STORAGE_SELECT_Buffer;
- input [0:31]SHIFTED_DATA_Buffer;
-
- wire [15:0]D;
- wire \MUXED_DATA_Buffer[0]_i_2_n_0 ;
- wire \MUXED_DATA_Buffer[10]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[11]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[12]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[13]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[14]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[15]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[16]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[17]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[18]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[19]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[1]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[20]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[21]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[22]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[23]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[24]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[25]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[26]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[27]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[28]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[29]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[2]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[30]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[31]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[3]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[4]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[5]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[6]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[7]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[8]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[9]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer_reg[0]_0 ;
- wire \MUXED_DATA_Buffer_reg[16]_0 ;
- wire \MUXED_DATA_Buffer_reg[17]_0 ;
- wire \MUXED_DATA_Buffer_reg[18]_0 ;
- wire \MUXED_DATA_Buffer_reg[19]_0 ;
- wire \MUXED_DATA_Buffer_reg[20]_0 ;
- wire \MUXED_DATA_Buffer_reg[21]_0 ;
- wire \MUXED_DATA_Buffer_reg[22]_0 ;
- wire \MUXED_DATA_Buffer_reg[23]_0 ;
- wire \MUXED_DATA_Buffer_reg[24]_0 ;
- wire \MUXED_DATA_Buffer_reg[25]_0 ;
- wire \MUXED_DATA_Buffer_reg[26]_0 ;
- wire \MUXED_DATA_Buffer_reg[27]_0 ;
- wire \MUXED_DATA_Buffer_reg[28]_0 ;
- wire \MUXED_DATA_Buffer_reg[29]_0 ;
- wire \MUXED_DATA_Buffer_reg[30]_0 ;
- wire \MUXED_DATA_Buffer_reg[31]_0 ;
- wire [0:31]SHIFTED_DATA_Buffer;
- wire [2:0]UFC_STORAGE_SELECT_Buffer;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair211" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[0]_i_2
- (.I0(SHIFTED_DATA_Buffer[16]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[0]),
- .O(\MUXED_DATA_Buffer[0]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair206" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[10]_i_1
- (.I0(SHIFTED_DATA_Buffer[26]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[10]),
- .O(\MUXED_DATA_Buffer[10]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair206" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[11]_i_1
- (.I0(SHIFTED_DATA_Buffer[27]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[11]),
- .O(\MUXED_DATA_Buffer[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair205" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[12]_i_1
- (.I0(SHIFTED_DATA_Buffer[28]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[12]),
- .O(\MUXED_DATA_Buffer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair205" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[13]_i_1
- (.I0(SHIFTED_DATA_Buffer[29]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[13]),
- .O(\MUXED_DATA_Buffer[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair204" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[14]_i_1
- (.I0(SHIFTED_DATA_Buffer[30]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[14]),
- .O(\MUXED_DATA_Buffer[14]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair204" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[15]_i_1
- (.I0(SHIFTED_DATA_Buffer[31]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[15]),
- .O(\MUXED_DATA_Buffer[15]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair203" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[16]_i_1
- (.I0(SHIFTED_DATA_Buffer[16]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[0]),
- .O(\MUXED_DATA_Buffer[16]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair203" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[17]_i_1
- (.I0(SHIFTED_DATA_Buffer[17]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[1]),
- .O(\MUXED_DATA_Buffer[17]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair202" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[18]_i_1
- (.I0(SHIFTED_DATA_Buffer[18]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[2]),
- .O(\MUXED_DATA_Buffer[18]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair202" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[19]_i_1
- (.I0(SHIFTED_DATA_Buffer[19]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[3]),
- .O(\MUXED_DATA_Buffer[19]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair211" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[1]_i_1
- (.I0(SHIFTED_DATA_Buffer[17]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[1]),
- .O(\MUXED_DATA_Buffer[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair201" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[20]_i_1
- (.I0(SHIFTED_DATA_Buffer[20]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[4]),
- .O(\MUXED_DATA_Buffer[20]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair201" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[21]_i_1
- (.I0(SHIFTED_DATA_Buffer[21]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[5]),
- .O(\MUXED_DATA_Buffer[21]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair200" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[22]_i_1
- (.I0(SHIFTED_DATA_Buffer[22]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[6]),
- .O(\MUXED_DATA_Buffer[22]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair200" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[23]_i_1
- (.I0(SHIFTED_DATA_Buffer[23]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[7]),
- .O(\MUXED_DATA_Buffer[23]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair199" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[24]_i_1
- (.I0(SHIFTED_DATA_Buffer[24]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[8]),
- .O(\MUXED_DATA_Buffer[24]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair199" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[25]_i_1
- (.I0(SHIFTED_DATA_Buffer[25]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[9]),
- .O(\MUXED_DATA_Buffer[25]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair198" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[26]_i_1
- (.I0(SHIFTED_DATA_Buffer[26]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[10]),
- .O(\MUXED_DATA_Buffer[26]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair198" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[27]_i_1
- (.I0(SHIFTED_DATA_Buffer[27]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[11]),
- .O(\MUXED_DATA_Buffer[27]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair197" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[28]_i_1
- (.I0(SHIFTED_DATA_Buffer[28]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[12]),
- .O(\MUXED_DATA_Buffer[28]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair197" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[29]_i_1
- (.I0(SHIFTED_DATA_Buffer[29]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[13]),
- .O(\MUXED_DATA_Buffer[29]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair210" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[2]_i_1
- (.I0(SHIFTED_DATA_Buffer[18]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[2]),
- .O(\MUXED_DATA_Buffer[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair196" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[30]_i_1
- (.I0(SHIFTED_DATA_Buffer[30]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[14]),
- .O(\MUXED_DATA_Buffer[30]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair196" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[31]_i_1
- (.I0(SHIFTED_DATA_Buffer[31]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[15]),
- .O(\MUXED_DATA_Buffer[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair210" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[3]_i_1
- (.I0(SHIFTED_DATA_Buffer[19]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[3]),
- .O(\MUXED_DATA_Buffer[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair209" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[4]_i_1
- (.I0(SHIFTED_DATA_Buffer[20]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[4]),
- .O(\MUXED_DATA_Buffer[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair209" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[5]_i_1
- (.I0(SHIFTED_DATA_Buffer[21]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[5]),
- .O(\MUXED_DATA_Buffer[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair208" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[6]_i_1
- (.I0(SHIFTED_DATA_Buffer[22]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[6]),
- .O(\MUXED_DATA_Buffer[6]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair208" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[7]_i_1
- (.I0(SHIFTED_DATA_Buffer[23]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[7]),
- .O(\MUXED_DATA_Buffer[7]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair207" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[8]_i_1
- (.I0(SHIFTED_DATA_Buffer[24]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[8]),
- .O(\MUXED_DATA_Buffer[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair207" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[9]_i_1
- (.I0(SHIFTED_DATA_Buffer[25]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[9]),
- .O(\MUXED_DATA_Buffer[9]_i_1_n_0 ));
- FDRE \MUXED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[0]_i_2_n_0 ),
- .Q(D[15]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[10]_i_1_n_0 ),
- .Q(D[5]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[11]_i_1_n_0 ),
- .Q(D[4]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[12]_i_1_n_0 ),
- .Q(D[3]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[13]_i_1_n_0 ),
- .Q(D[2]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[14]_i_1_n_0 ),
- .Q(D[1]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[15]_i_1_n_0 ),
- .Q(D[0]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[16]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[16]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[17]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[17]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[18]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[18]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[19]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[19]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[1]_i_1_n_0 ),
- .Q(D[14]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[20]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[20]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[21]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[21]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[22]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[22]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[23]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[23]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[24]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[24]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[25]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[25]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[26]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[26]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[27]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[27]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[28]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[28]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[29]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[29]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[2]_i_1_n_0 ),
- .Q(D[13]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[30]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[30]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[31]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[31]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[3]_i_1_n_0 ),
- .Q(D[12]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[4]_i_1_n_0 ),
- .Q(D[11]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[5]_i_1_n_0 ),
- .Q(D[10]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[6]_i_1_n_0 ),
- .Q(D[9]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[7]_i_1_n_0 ),
- .Q(D[8]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[8]_i_1_n_0 ),
- .Q(D[7]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[9]_i_1_n_0 ),
- .Q(D[6]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_UFC_STORAGE_SWITCH_CONTROL" *)
-module east_channel_east_channel_UFC_STORAGE_SWITCH_CONTROL
- (\UFC_STORAGE_SELECT_Buffer_reg[0]_0 ,
- \UFC_STORAGE_SELECT_Buffer_reg[2]_0 ,
- D,
- user_clk,
- \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ,
- \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ,
- Q,
- \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ,
- stage_1_ufc_start_r,
- \UFC_STORAGE_SELECT_Buffer_reg[4]_1 );
- output \UFC_STORAGE_SELECT_Buffer_reg[0]_0 ;
- output [2:0]\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ;
- input [0:0]D;
- input user_clk;
- input \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ;
- input \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
- input [1:0]Q;
- input \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ;
- input stage_1_ufc_start_r;
- input [1:0]\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ;
-
- wire [0:0]D;
- wire [1:0]Q;
- wire [0:1]UFC_STORAGE_SELECT_Buffer;
- wire \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[0]_0 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
- wire [2:0]\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ;
- wire [1:0]\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ;
- wire stage_1_ufc_start_r;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'hE))
- \MUXED_DATA_Buffer[0]_i_1
- (.I0(UFC_STORAGE_SELECT_Buffer[0]),
- .I1(UFC_STORAGE_SELECT_Buffer[1]),
- .O(\UFC_STORAGE_SELECT_Buffer_reg[0]_0 ));
- LUT5 #(
- .INIT(32'hABABABBF))
- \UFC_STORAGE_SELECT_Buffer[0]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[1]),
- .I2(\UFC_STORAGE_SELECT_Buffer_reg[4]_1 [1]),
- .I3(\UFC_STORAGE_SELECT_Buffer_reg[4]_1 [0]),
- .I4(Q[0]),
- .O(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_STORAGE_SELECT_Buffer_reg[0]_1 ),
- .Q(UFC_STORAGE_SELECT_Buffer[0]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_STORAGE_SELECT_Buffer_reg[1]_0 ),
- .Q(UFC_STORAGE_SELECT_Buffer[1]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[0]),
- .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [2]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_STORAGE_SELECT_Buffer_reg[4]_0 ),
- .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [1]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_VALID_DATA_COUNTER" *)
-module east_channel_east_channel_VALID_DATA_COUNTER
- (\COUNT_Buffer_reg[0]_0 ,
- Q,
- RESET,
- user_clk);
- output [1:0]\COUNT_Buffer_reg[0]_0 ;
- input [1:0]Q;
- input RESET;
- input user_clk;
-
- wire \COUNT_Buffer[0]_i_1_n_0 ;
- wire \COUNT_Buffer[1]_i_1_n_0 ;
- wire [1:0]\COUNT_Buffer_reg[0]_0 ;
- wire [1:0]Q;
- wire RESET;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair212" *)
- LUT2 #(
- .INIT(4'h8))
- \COUNT_Buffer[0]_i_1
- (.I0(Q[0]),
- .I1(Q[1]),
- .O(\COUNT_Buffer[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair212" *)
- LUT2 #(
- .INIT(4'h6))
- \COUNT_Buffer[1]_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\COUNT_Buffer[1]_i_1_n_0 ));
- FDRE \COUNT_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer[0]_i_1_n_0 ),
- .Q(\COUNT_Buffer_reg[0]_0 [1]),
- .R(RESET));
- FDRE \COUNT_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer[1]_i_1_n_0 ),
- .Q(\COUNT_Buffer_reg[0]_0 [0]),
- .R(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_VALID_DATA_COUNTER" *)
-module east_channel_east_channel_VALID_DATA_COUNTER_22
- (D,
- Q,
- end_storage_r_reg,
- end_storage_r0,
- std_bool2_in,
- std_bool6_in,
- \STORAGE_CE_Buffer_reg[0] ,
- stage_3_end_storage_r,
- stage_2_start_with_data_r,
- stage_2_end_before_start_r,
- stage_2_end_after_start_r,
- RESET,
- \COUNT_Buffer_reg[0]_0 ,
- user_clk);
- output [1:0]D;
- output [0:0]Q;
- output [0:0]end_storage_r_reg;
- output end_storage_r0;
- output std_bool2_in;
- output std_bool6_in;
- input [1:0]\STORAGE_CE_Buffer_reg[0] ;
- input stage_3_end_storage_r;
- input stage_2_start_with_data_r;
- input stage_2_end_before_start_r;
- input stage_2_end_after_start_r;
- input RESET;
- input [1:0]\COUNT_Buffer_reg[0]_0 ;
- input user_clk;
-
- wire [1:0]\COUNT_Buffer_reg[0]_0 ;
- wire [1:0]D;
- wire [0:0]Q;
- wire RESET;
- wire [1:0]\STORAGE_CE_Buffer_reg[0] ;
- wire end_storage_r0;
- wire [0:0]end_storage_r_reg;
- wire [0:0]stage_2_data_v_count_r;
- wire stage_2_end_after_start_r;
- wire stage_2_end_before_start_r;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire std_bool2_in;
- wire std_bool6_in;
- wire user_clk;
-
- FDRE \COUNT_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer_reg[0]_0 [1]),
- .Q(stage_2_data_v_count_r),
- .R(RESET));
- FDRE \COUNT_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer_reg[0]_0 [0]),
- .Q(Q),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair149" *)
- LUT4 #(
- .INIT(16'hFEE0))
- SRC_RDY_N_Buffer_i_3
- (.I0(Q),
- .I1(\STORAGE_CE_Buffer_reg[0] [0]),
- .I2(\STORAGE_CE_Buffer_reg[0] [1]),
- .I3(stage_2_data_v_count_r),
- .O(std_bool6_in));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFAEF))
- \STORAGE_CE_Buffer[0]_i_1
- (.I0(stage_2_data_v_count_r),
- .I1(Q),
- .I2(\STORAGE_CE_Buffer_reg[0] [1]),
- .I3(\STORAGE_CE_Buffer_reg[0] [0]),
- .I4(stage_3_end_storage_r),
- .I5(stage_2_start_with_data_r),
- .O(D[1]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFEFF))
- \STORAGE_CE_Buffer[1]_i_1
- (.I0(stage_2_data_v_count_r),
- .I1(\STORAGE_CE_Buffer_reg[0] [0]),
- .I2(Q),
- .I3(\STORAGE_CE_Buffer_reg[0] [1]),
- .I4(stage_3_end_storage_r),
- .I5(stage_2_start_with_data_r),
- .O(D[0]));
- LUT4 #(
- .INIT(16'hF404))
- end_storage_r_i_1
- (.I0(std_bool2_in),
- .I1(stage_2_end_before_start_r),
- .I2(stage_2_start_with_data_r),
- .I3(stage_2_end_after_start_r),
- .O(end_storage_r0));
- (* SOFT_HLUTNM = "soft_lutpair149" *)
- LUT4 #(
- .INIT(16'h0001))
- end_storage_r_i_2
- (.I0(Q),
- .I1(\STORAGE_CE_Buffer_reg[0] [0]),
- .I2(\STORAGE_CE_Buffer_reg[0] [1]),
- .I3(stage_2_data_v_count_r),
- .O(std_bool2_in));
- LUT6 #(
- .INIT(64'hEFFFFEEF10011000))
- \storage_count_r[0]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(Q),
- .I3(\STORAGE_CE_Buffer_reg[0] [0]),
- .I4(\STORAGE_CE_Buffer_reg[0] [1]),
- .I5(stage_2_data_v_count_r),
- .O(end_storage_r_reg));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync
- (out,
- RESET,
- user_clk);
- output out;
- input RESET;
- input user_clk;
-
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- assign p_level_in_int = RESET;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync_16
- (out,
- user_clk);
- output out;
- input user_clk;
-
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync_28
- (out,
- PLL_NOT_LOCKED,
- user_clk);
- output out;
- input PLL_NOT_LOCKED;
- input user_clk;
-
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- assign p_level_in_int = PLL_NOT_LOCKED;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1
- (AR,
- GT_RESET,
- init_clk_in);
- output [0:0]AR;
- input GT_RESET;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign AR[0] = s_level_out_d6;
- assign p_level_in_int = GT_RESET;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_0
- (HPCNT_RESET,
- RESET,
- init_clk_in,
- AR);
- output HPCNT_RESET;
- input RESET;
- input init_clk_in;
- input [0:0]AR;
-
- wire [0:0]AR;
- wire HPCNT_RESET;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign p_level_in_int = RESET;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- \hotplug_count_synth.count_for_reset_r[0]_i_2
- (.I0(s_level_out_d6),
- .I1(AR),
- .O(HPCNT_RESET));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_1
- (E,
- \FSM_sequential_tx_state_reg[0] ,
- quad1_common_lock_in,
- init_clk_in,
- \FSM_sequential_tx_state_reg[0]_0 ,
- reset_time_out_reg,
- \FSM_sequential_tx_state_reg[0]_1 ,
- Q,
- \FSM_sequential_tx_state_reg[3]_i_5_0 ,
- reset_time_out,
- mmcm_lock_reclocked,
- \FSM_sequential_tx_state_reg[3]_i_5_1 ,
- txresetdone_s3,
- \FSM_sequential_tx_state_reg[3]_i_5_2 ,
- \FSM_sequential_tx_state_reg[3]_i_5_3 ,
- reset_time_out_reg_0);
- output [0:0]E;
- output \FSM_sequential_tx_state_reg[0] ;
- input quad1_common_lock_in;
- input init_clk_in;
- input \FSM_sequential_tx_state_reg[0]_0 ;
- input reset_time_out_reg;
- input \FSM_sequential_tx_state_reg[0]_1 ;
- input [3:0]Q;
- input \FSM_sequential_tx_state_reg[3]_i_5_0 ;
- input reset_time_out;
- input mmcm_lock_reclocked;
- input \FSM_sequential_tx_state_reg[3]_i_5_1 ;
- input txresetdone_s3;
- input \FSM_sequential_tx_state_reg[3]_i_5_2 ;
- input \FSM_sequential_tx_state_reg[3]_i_5_3 ;
- input reset_time_out_reg_0;
-
- wire [0:0]E;
- wire \FSM_sequential_tx_state[3]_i_7_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_8_n_0 ;
- wire \FSM_sequential_tx_state_reg[0] ;
- wire \FSM_sequential_tx_state_reg[0]_0 ;
- wire \FSM_sequential_tx_state_reg[0]_1 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_0 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_1 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_2 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_3 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_n_0 ;
- wire [3:0]Q;
- wire init_clk_in;
- wire mmcm_lock_reclocked;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire reset_time_out;
- wire reset_time_out_i_2_n_0;
- wire reset_time_out_i_3_n_0;
- wire reset_time_out_reg;
- wire reset_time_out_reg_0;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire txresetdone_s3;
-
- assign p_level_in_int = quad1_common_lock_in;
- LUT6 #(
- .INIT(64'h000000FFCCCCB8B8))
- \FSM_sequential_tx_state[3]_i_1
- (.I0(\FSM_sequential_tx_state_reg[0]_0 ),
- .I1(reset_time_out_reg),
- .I2(\FSM_sequential_tx_state_reg[0]_1 ),
- .I3(\FSM_sequential_tx_state_reg[3]_i_5_n_0 ),
- .I4(Q[3]),
- .I5(Q[0]),
- .O(E));
- LUT6 #(
- .INIT(64'h0DFF0D000DFF0DFF))
- \FSM_sequential_tx_state[3]_i_7
- (.I0(\FSM_sequential_tx_state_reg[3]_i_5_0 ),
- .I1(reset_time_out),
- .I2(mmcm_lock_reclocked),
- .I3(Q[2]),
- .I4(s_level_out_d6),
- .I5(\FSM_sequential_tx_state_reg[3]_i_5_1 ),
- .O(\FSM_sequential_tx_state[3]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h45004500450045FF))
- \FSM_sequential_tx_state[3]_i_8
- (.I0(txresetdone_s3),
- .I1(reset_time_out),
- .I2(\FSM_sequential_tx_state_reg[3]_i_5_2 ),
- .I3(Q[2]),
- .I4(s_level_out_d6),
- .I5(\FSM_sequential_tx_state_reg[3]_i_5_3 ),
- .O(\FSM_sequential_tx_state[3]_i_8_n_0 ));
- MUXF7 \FSM_sequential_tx_state_reg[3]_i_5
- (.I0(\FSM_sequential_tx_state[3]_i_7_n_0 ),
- .I1(\FSM_sequential_tx_state[3]_i_8_n_0 ),
- .O(\FSM_sequential_tx_state_reg[3]_i_5_n_0 ),
- .S(Q[1]));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT6 #(
- .INIT(64'h8F80FFFF8F800000))
- reset_time_out_i_1
- (.I0(reset_time_out_reg),
- .I1(Q[0]),
- .I2(Q[3]),
- .I3(reset_time_out_i_2_n_0),
- .I4(reset_time_out_i_3_n_0),
- .I5(reset_time_out),
- .O(\FSM_sequential_tx_state_reg[0] ));
- LUT5 #(
- .INIT(32'hFFFF8A80))
- reset_time_out_i_2
- (.I0(Q[1]),
- .I1(txresetdone_s3),
- .I2(Q[2]),
- .I3(s_level_out_d6),
- .I4(reset_time_out_reg_0),
- .O(reset_time_out_i_2_n_0));
- LUT6 #(
- .INIT(64'h22202F2F22202E2E))
- reset_time_out_i_3
- (.I0(Q[0]),
- .I1(Q[3]),
- .I2(Q[2]),
- .I3(s_level_out_d6),
- .I4(Q[1]),
- .I5(\FSM_sequential_tx_state_reg[0]_0 ),
- .O(reset_time_out_i_3_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_11
- (SR,
- mmcm_lock_reclocked_reg,
- init_clk_in,
- mmcm_lock_reclocked,
- mmcm_lock_reclocked_reg_0);
- output [0:0]SR;
- output mmcm_lock_reclocked_reg;
- input init_clk_in;
- input mmcm_lock_reclocked;
- input mmcm_lock_reclocked_reg_0;
-
- wire [0:0]SR;
- wire init_clk_in;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_reg;
- wire mmcm_lock_reclocked_reg_0;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b1),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[9]_i_1__0
- (.I0(s_level_out_d6),
- .O(SR));
- LUT3 #(
- .INIT(8'hE0))
- mmcm_lock_reclocked_i_1__0
- (.I0(mmcm_lock_reclocked),
- .I1(mmcm_lock_reclocked_reg_0),
- .I2(s_level_out_d6),
- .O(mmcm_lock_reclocked_reg));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_2
- (init_clk_in);
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b1),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_21
- (out,
- in0,
- drpclk_in);
- output out;
- input in0;
- input drpclk_in;
-
- wire drpclk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign out = s_level_out_d6;
- assign p_level_in_int = in0;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_4
- (SR,
- mmcm_lock_reclocked_reg,
- init_clk_in,
- PLL_NOT_LOCKED,
- mmcm_lock_reclocked,
- mmcm_lock_reclocked_reg_0);
- output [0:0]SR;
- output mmcm_lock_reclocked_reg;
- input init_clk_in;
- input PLL_NOT_LOCKED;
- input mmcm_lock_reclocked;
- input mmcm_lock_reclocked_reg_0;
-
- wire PLL_NOT_LOCKED;
- wire [0:0]SR;
- wire init_clk_in;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_reg;
- wire mmcm_lock_reclocked_reg_0;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[9]_i_1
- (.I0(s_level_out_d6),
- .O(SR));
- LUT3 #(
- .INIT(8'hE0))
- mmcm_lock_reclocked_i_1
- (.I0(mmcm_lock_reclocked),
- .I1(mmcm_lock_reclocked_reg_0),
- .I2(s_level_out_d6),
- .O(mmcm_lock_reclocked_reg));
- LUT1 #(
- .INIT(2'h1))
- p_level_in_int_inferred_i_1
- (.I0(PLL_NOT_LOCKED),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_8
- (E,
- reset_time_out_reg,
- quad1_common_lock_in,
- init_clk_in,
- Q,
- reset_time_out_reg_0,
- \FSM_sequential_rx_state_reg[0] ,
- \FSM_sequential_rx_state_reg[0]_0 ,
- \FSM_sequential_rx_state_reg[0]_1 ,
- \FSM_sequential_rx_state_reg[0]_2 ,
- \FSM_sequential_rx_state_reg[0]_3 ,
- reset_time_out_reg_1,
- check_tlock_max,
- reset_time_out_reg_2,
- reset_time_out_reg_3,
- reset_time_out_reg_4);
- output [0:0]E;
- output reset_time_out_reg;
- input quad1_common_lock_in;
- input init_clk_in;
- input [3:0]Q;
- input reset_time_out_reg_0;
- input \FSM_sequential_rx_state_reg[0] ;
- input \FSM_sequential_rx_state_reg[0]_0 ;
- input [0:0]\FSM_sequential_rx_state_reg[0]_1 ;
- input \FSM_sequential_rx_state_reg[0]_2 ;
- input \FSM_sequential_rx_state_reg[0]_3 ;
- input reset_time_out_reg_1;
- input check_tlock_max;
- input reset_time_out_reg_2;
- input reset_time_out_reg_3;
- input reset_time_out_reg_4;
-
- wire [0:0]E;
- wire \FSM_sequential_rx_state[3]_i_5_n_0 ;
- wire \FSM_sequential_rx_state_reg[0] ;
- wire \FSM_sequential_rx_state_reg[0]_0 ;
- wire [0:0]\FSM_sequential_rx_state_reg[0]_1 ;
- wire \FSM_sequential_rx_state_reg[0]_2 ;
- wire \FSM_sequential_rx_state_reg[0]_3 ;
- wire [3:0]Q;
- wire check_tlock_max;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire reset_time_out_i_5_n_0;
- wire reset_time_out_reg;
- wire reset_time_out_reg_0;
- wire reset_time_out_reg_1;
- wire reset_time_out_reg_2;
- wire reset_time_out_reg_3;
- wire reset_time_out_reg_4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign p_level_in_int = quad1_common_lock_in;
- LUT6 #(
- .INIT(64'hAAABBBBBAAABAAAB))
- \FSM_sequential_rx_state[3]_i_1
- (.I0(\FSM_sequential_rx_state_reg[0] ),
- .I1(\FSM_sequential_rx_state_reg[0]_0 ),
- .I2(\FSM_sequential_rx_state_reg[0]_1 ),
- .I3(Q[0]),
- .I4(\FSM_sequential_rx_state[3]_i_5_n_0 ),
- .I5(\FSM_sequential_rx_state_reg[0]_2 ),
- .O(E));
- LUT6 #(
- .INIT(64'h5500550055005700))
- \FSM_sequential_rx_state[3]_i_5
- (.I0(Q[0]),
- .I1(\FSM_sequential_rx_state_reg[0]_3 ),
- .I2(s_level_out_d6),
- .I3(Q[1]),
- .I4(Q[3]),
- .I5(Q[2]),
- .O(\FSM_sequential_rx_state[3]_i_5_n_0 ));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT6 #(
- .INIT(64'hFF40FFFFFF400000))
- reset_time_out_i_1__0
- (.I0(reset_time_out_reg_1),
- .I1(check_tlock_max),
- .I2(reset_time_out_reg_2),
- .I3(reset_time_out_i_5_n_0),
- .I4(reset_time_out_reg_3),
- .I5(reset_time_out_reg_4),
- .O(reset_time_out_reg));
- LUT6 #(
- .INIT(64'h10DD10DDDC11DCDD))
- reset_time_out_i_5
- (.I0(Q[2]),
- .I1(Q[3]),
- .I2(s_level_out_d6),
- .I3(Q[1]),
- .I4(Q[0]),
- .I5(reset_time_out_reg_0),
- .O(reset_time_out_i_5_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized1_9
- (init_clk_in);
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b1),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3
- (out,
- run_phase_alignment_int,
- init_clk_in,
- user_clk);
- output out;
- input run_phase_alignment_int;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire run_phase_alignment_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(run_phase_alignment_int),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3_12
- (init_clk_in,
- user_clk);
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(1'b0),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3_13
- (out,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ,
- init_clk_in,
- user_clk);
- output out;
- input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- input init_clk_in;
- input user_clk;
-
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3_14
- (out,
- rx_fsm_reset_done_int,
- init_clk_in,
- user_clk);
- output out;
- input rx_fsm_reset_done_int;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rx_fsm_reset_done_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rx_fsm_reset_done_int),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3_27
- (out,
- link_reset_r,
- init_clk_in,
- user_clk);
- output out;
- input link_reset_r;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- wire link_reset_r;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3_29
- (out,
- tx_lock_comb_r,
- init_clk_in,
- user_clk);
- output out;
- input tx_lock_comb_r;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire tx_lock_comb_r;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_lock_comb_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3_6
- (out,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ,
- tx_fsm_reset_done_int,
- init_clk_in,
- user_clk);
- output out;
- output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ;
- input tx_fsm_reset_done_int;
- input init_clk_in;
- input user_clk;
-
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire tx_fsm_reset_done_int;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_fsm_reset_done_int),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gt_txresetdone_r_i_1
- (.I0(s_level_out_d5),
- .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized3_7
- (out,
- gtrxreset_i,
- init_clk_in,
- user_clk);
- output out;
- input gtrxreset_i;
- input init_clk_in;
- input user_clk;
-
- wire gtrxreset_i;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_i),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6
- (out,
- GTRXRESET_OUT,
- user_clk,
- init_clk_in);
- output out;
- input GTRXRESET_OUT;
- input user_clk;
- input init_clk_in;
-
- wire GTRXRESET_OUT;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GTRXRESET_OUT),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_10
- (out,
- rxfsm_rxresetdone_r,
- user_clk,
- init_clk_in);
- output out;
- input rxfsm_rxresetdone_r;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rxfsm_rxresetdone_r;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxfsm_rxresetdone_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_15
- (rxpmaresetdone_i,
- user_clk,
- init_clk_in);
- input rxpmaresetdone_i;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rxpmaresetdone_i;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxpmaresetdone_i),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_17
- (out,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ,
- user_clk,
- init_clk_in);
- output out;
- input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- input user_clk;
- input init_clk_in;
-
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_18
- (txpmaresetdone_i,
- user_clk,
- init_clk_in);
- input txpmaresetdone_i;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire txpmaresetdone_i;
- wire user_clk;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(txpmaresetdone_i),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_19
- (out,
- SR,
- init_clk_in,
- drpclk_in);
- output out;
- input [0:0]SR;
- input init_clk_in;
- input drpclk_in;
-
- wire [0:0]SR;
- wire drpclk_in;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(SR),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_20
- (AR,
- gt_common_reset_out,
- init_clk_in,
- drpclk_in);
- output [0:0]AR;
- input gt_common_reset_out;
- input init_clk_in;
- input drpclk_in;
-
- wire drpclk_in;
- wire gt_common_reset_out;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign AR[0] = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gt_common_reset_out),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_24
- (O,
- \hotplug_count_synth.count_for_reset_r_reg[7] ,
- \hotplug_count_synth.count_for_reset_r_reg[11] ,
- \hotplug_count_synth.count_for_reset_r_reg[15] ,
- \hotplug_count_synth.count_for_reset_r_reg[19] ,
- \hotplug_count_synth.count_for_reset_r_reg[21] ,
- rx_cc_extend_r2,
- user_clk,
- init_clk_in,
- \hotplug_count_synth.count_for_reset_r_reg );
- output [3:0]O;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
- output [1:0]\hotplug_count_synth.count_for_reset_r_reg[21] ;
- input rx_cc_extend_r2;
- input user_clk;
- input init_clk_in;
- input [21:0]\hotplug_count_synth.count_for_reset_r_reg ;
-
- wire [3:0]O;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ;
- wire [21:0]\hotplug_count_synth.count_for_reset_r_reg ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 ;
- wire [1:0]\hotplug_count_synth.count_for_reset_r_reg[21] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rx_cc_extend_r2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
- wire [3:1]\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_CO_UNCONNECTED ;
- wire [3:2]\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_O_UNCONNECTED ;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r2),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_6
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [1]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h1))
- \hotplug_count_synth.count_for_reset_r[0]_i_7
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [15]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [14]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [13]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [12]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [19]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [18]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [17]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[20]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [21]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[20]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [20]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [5]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [4]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [11]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [9]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[0]_i_1
- (.CI(1'b0),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 }),
- .O(O),
- .S({\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[12]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[15] ),
- .S({\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[16]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[19] ),
- .S({\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[20]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ),
- .CO({\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_CO_UNCONNECTED [3:1],\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_O_UNCONNECTED [3:2],\hotplug_count_synth.count_for_reset_r_reg[21] }),
- .S({1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[4]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[7] ),
- .S({\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[8]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[11] ),
- .S({\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 }));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_3
- (out,
- txfsm_txresetdone_r,
- user_clk,
- init_clk_in);
- output out;
- input txfsm_txresetdone_r;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire txfsm_txresetdone_r;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(txfsm_txresetdone_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_cdc_sync" *)
-module east_channel_east_channel_cdc_sync__parameterized6_5
- (out,
- time_out_wait_bypass,
- user_clk,
- init_clk_in);
- output out;
- input time_out_wait_bypass;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_east_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire time_out_wait_bypass;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(time_out_wait_bypass),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_east_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_east_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_east_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* CC_FREQ_FACTOR = "12" *) (* EXAMPLE_SIMULATION = "0" *) (* ORIG_REF_NAME = "east_channel_core" *)
-(* SIM_GTRESET_SPEEDUP = "FALSE" *)
-module east_channel_east_channel_core
- (S_AXI_TX_TDATA,
- S_AXI_TX_TKEEP,
- S_AXI_TX_TVALID,
- S_AXI_TX_TREADY,
- S_AXI_TX_TLAST,
- M_AXI_RX_TDATA,
- M_AXI_RX_TKEEP,
- M_AXI_RX_TVALID,
- M_AXI_RX_TLAST,
- S_AXI_UFC_TX_REQ,
- S_AXI_UFC_TX_MS,
- S_AXI_UFC_TX_ACK,
- M_AXI_UFC_RX_TDATA,
- M_AXI_UFC_RX_TKEEP,
- M_AXI_UFC_RX_TVALID,
- M_AXI_UFC_RX_TLAST,
- RXP,
- RXN,
- TXP,
- TXN,
- gt_refclk1,
- HARD_ERR,
- SOFT_ERR,
- FRAME_ERR,
- CHANNEL_UP,
- LANE_UP,
- user_clk,
- sync_clk,
- RESET,
- POWER_DOWN,
- LOOPBACK,
- GT_RESET,
- init_clk_in,
- PLL_NOT_LOCKED,
- TX_RESETDONE_OUT,
- RX_RESETDONE_OUT,
- LINK_RESET_OUT,
- drpclk_in,
- DRPADDR_IN,
- DRPDI_IN,
- DRPDO_OUT,
- DRPEN_IN,
- DRPRDY_OUT,
- DRPWE_IN,
- TX_OUT_CLK,
- gt_common_reset_out,
- gt0_pll0refclklost_in,
- quad1_common_lock_in,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- sys_reset_out,
- tx_lock);
- input [0:31]S_AXI_TX_TDATA;
- input [0:3]S_AXI_TX_TKEEP;
- input S_AXI_TX_TVALID;
- output S_AXI_TX_TREADY;
- input S_AXI_TX_TLAST;
- output [0:31]M_AXI_RX_TDATA;
- output [0:3]M_AXI_RX_TKEEP;
- output M_AXI_RX_TVALID;
- output M_AXI_RX_TLAST;
- input S_AXI_UFC_TX_REQ;
- input [0:2]S_AXI_UFC_TX_MS;
- output S_AXI_UFC_TX_ACK;
- output [0:31]M_AXI_UFC_RX_TDATA;
- output [0:3]M_AXI_UFC_RX_TKEEP;
- output M_AXI_UFC_RX_TVALID;
- output M_AXI_UFC_RX_TLAST;
- input RXP;
- input RXN;
- output TXP;
- output TXN;
- input gt_refclk1;
- output HARD_ERR;
- output SOFT_ERR;
- output FRAME_ERR;
- output CHANNEL_UP;
- output LANE_UP;
- input user_clk;
- input sync_clk;
- input RESET;
- input POWER_DOWN;
- input [2:0]LOOPBACK;
- input GT_RESET;
- input init_clk_in;
- input PLL_NOT_LOCKED;
- output TX_RESETDONE_OUT;
- output RX_RESETDONE_OUT;
- output LINK_RESET_OUT;
- input drpclk_in;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- output [15:0]DRPDO_OUT;
- input DRPEN_IN;
- output DRPRDY_OUT;
- input DRPWE_IN;
- output TX_OUT_CLK;
- output gt_common_reset_out;
- input gt0_pll0refclklost_in;
- input quad1_common_lock_in;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- output sys_reset_out;
- output tx_lock;
-
- wire \<const1> ;
- wire CHANNEL_UP;
- wire DO_CC_I;
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN_IN;
- wire DRPRDY_OUT;
- wire DRPWE_IN;
- wire FRAME_ERR;
- wire GEN_SCP;
- wire GEN_SUF;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire GTRXRESET_OUT;
- wire GT_RESET;
- wire HARD_ERR;
- wire HPCNT_RESET;
- wire LANE_UP;
- wire LINK_RESET_OUT;
- wire [2:0]LOOPBACK;
- wire [0:31]M_AXI_RX_TDATA;
- wire [1:3]\^M_AXI_RX_TKEEP ;
- wire M_AXI_RX_TLAST;
- wire M_AXI_RX_TVALID;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [2:2]\^M_AXI_UFC_RX_TKEEP ;
- wire M_AXI_UFC_RX_TLAST;
- wire M_AXI_UFC_RX_TVALID;
- wire PLL_NOT_LOCKED;
- wire POWER_DOWN;
- wire RESET;
- wire RESET_0;
- wire RXN;
- wire RXP;
- wire RX_RESETDONE_OUT;
- wire SOFT_ERR;
- wire START_RX;
- wire [0:31]S_AXI_TX_TDATA;
- wire [0:3]S_AXI_TX_TKEEP;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TREADY;
- wire S_AXI_TX_TVALID;
- wire S_AXI_UFC_TX_ACK;
- wire [0:2]S_AXI_UFC_TX_MS;
- wire S_AXI_UFC_TX_REQ;
- wire [3:0]TXCHARISK_IN;
- wire [31:0]TXDATA_IN;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire TX_RESETDONE_OUT;
- wire WARN_CC;
- wire axi_to_ll_pdu_i_n_0;
- wire \channel_init_sm_i/wait_for_lane_up_r0 ;
- wire drpclk_in;
- wire east_channel_aurora_lane_4byte_0_i_n_12;
- wire east_channel_aurora_lane_4byte_0_i_n_13;
- wire east_channel_aurora_lane_4byte_0_i_n_14;
- wire east_channel_aurora_lane_4byte_0_i_n_15;
- wire east_channel_aurora_lane_4byte_0_i_n_16;
- wire east_channel_aurora_lane_4byte_0_i_n_17;
- wire east_channel_aurora_lane_4byte_0_i_n_18;
- wire east_channel_aurora_lane_4byte_0_i_n_19;
- wire east_channel_aurora_lane_4byte_0_i_n_20;
- wire east_channel_aurora_lane_4byte_0_i_n_3;
- wire east_channel_aurora_lane_4byte_0_i_n_4;
- wire east_channel_aurora_lane_4byte_0_i_n_57;
- wire east_channel_aurora_lane_4byte_0_i_n_58;
- wire east_channel_aurora_lane_4byte_0_i_n_59;
- wire east_channel_aurora_lane_4byte_0_i_n_60;
- wire \east_channel_err_detect_4byte_i/hard_err_gt0 ;
- wire east_channel_global_logic_i_n_19;
- wire east_channel_global_logic_i_n_20;
- wire east_channel_rx_ll_i_n_5;
- wire east_channel_rx_ll_i_n_6;
- wire [1:0]\east_channel_sym_dec_4byte_i/p_8_out ;
- wire [1:0]\east_channel_sym_dec_4byte_i/p_9_out ;
- wire [0:0]\east_channel_sym_dec_4byte_i/previous_cycle_control_r ;
- wire east_channel_tx_ll_i_n_10;
- wire east_channel_tx_ll_i_n_6;
- wire east_channel_tx_ll_i_n_7;
- wire east_channel_tx_ll_i_n_8;
- wire ena_comma_align_i;
- wire gen_a_i;
- wire gen_cc_i;
- wire gen_ecp_i;
- wire [0:3]gen_k_i;
- wire [0:1]gen_pad_i;
- wire [0:3]gen_r_i;
- wire [1:3]gen_v_i;
- wire got_v_i;
- wire gt_common_reset_out;
- wire gt_reset_sync_init_clk;
- wire gt_wrapper_i_n_68;
- wire gt_wrapper_i_n_69;
- wire gt_wrapper_i_n_70;
- wire gt_wrapper_i_n_71;
- wire gt_wrapper_i_n_72;
- wire gt_wrapper_i_n_73;
- wire gt_wrapper_i_n_74;
- wire gt_wrapper_i_n_75;
- wire gt_wrapper_i_n_76;
- wire gt_wrapper_i_n_77;
- wire gt_wrapper_i_n_78;
- wire gt_wrapper_i_n_79;
- wire gt_wrapper_i_n_80;
- wire gt_wrapper_i_n_81;
- wire gt_wrapper_i_n_82;
- wire gt_wrapper_i_n_83;
- wire gt_wrapper_i_n_84;
- wire gt_wrapper_i_n_85;
- wire gt_wrapper_i_n_86;
- wire gt_wrapper_i_n_87;
- wire gt_wrapper_i_n_88;
- wire gt_wrapper_i_n_89;
- wire gt_wrapper_i_n_90;
- wire gt_wrapper_i_n_91;
- wire gt_wrapper_i_n_92;
- wire gt_wrapper_i_n_95;
- wire gt_wrapper_i_n_96;
- wire hard_err_i;
- wire init_clk_in;
- wire link_reset_r;
- wire neqOp;
- wire new_pkt_r;
- wire quad1_common_lock_in;
- wire reset_channel_i;
- wire reset_lanes_i;
- wire reset_sync_user_clk;
- wire rx_cc_i;
- wire [3:0]rx_char_is_comma_i;
- wire [3:0]rx_char_is_k_i;
- wire [31:0]rx_data_i;
- wire [3:0]rx_disp_err_i;
- wire rx_eof;
- wire [3:0]rx_not_in_table_i;
- wire [0:1]rx_pad_descram_in;
- wire [0:31]rx_pe_data_striped_i;
- wire [0:1]rx_pe_data_v_striped_i;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire [0:1]rx_suf_striped_i;
- wire [0:1]soft_err_i;
- wire sync_clk;
- wire sys_reset_out;
- wire tx_dst_rdy;
- wire \tx_ll_control_i/next_ufc_idle_c ;
- wire tx_lock;
- wire [0:31]tx_pe_data_i;
- wire [0:1]tx_pe_data_v_i;
- wire tx_reset_i;
- wire user_clk;
-
- assign M_AXI_RX_TKEEP[0] = \<const1> ;
- assign M_AXI_RX_TKEEP[1:3] = \^M_AXI_RX_TKEEP [1:3];
- assign M_AXI_UFC_RX_TKEEP[0] = \<const1> ;
- assign M_AXI_UFC_RX_TKEEP[1] = \<const1> ;
- assign M_AXI_UFC_RX_TKEEP[2] = \^M_AXI_UFC_RX_TKEEP [2];
- assign M_AXI_UFC_RX_TKEEP[3] = \^M_AXI_UFC_RX_TKEEP [2];
- VCC VCC
- (.P(\<const1> ));
- east_channel_east_channel_AXI_TO_LL axi_to_ll_pdu_i
- (.new_pkt_r(new_pkt_r),
- .new_pkt_r_reg_0(axi_to_ll_pdu_i_n_0),
- .user_clk(user_clk));
- east_channel_east_channel_RESET_LOGIC core_reset_logic_i
- (.LINK_RESET_OUT(LINK_RESET_OUT),
- .PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .SYSTEM_RESET_reg_0(sys_reset_out),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .gt_rxresetdone_r2_reg_0(gt_wrapper_i_n_95),
- .gt_txresetdone_r2_reg_0(gt_wrapper_i_n_96),
- .init_clk_in(init_clk_in),
- .link_reset_r(link_reset_r),
- .new_pkt_r(new_pkt_r),
- .new_pkt_r_reg(CHANNEL_UP),
- .new_pkt_r_reg_0(axi_to_ll_pdu_i_n_0),
- .out(reset_sync_user_clk),
- .reset_channel_i(reset_channel_i),
- .tx_dst_rdy(tx_dst_rdy),
- .tx_lock(tx_lock),
- .user_clk(user_clk),
- .wait_for_lane_up_r0(\channel_init_sm_i/wait_for_lane_up_r0 ));
- east_channel_east_channel_AURORA_LANE_4BYTE east_channel_aurora_lane_4byte_0_i
- (.\CHAR_IS_K_OUT_reg[3] ({TXCHARISK_IN[0],TXCHARISK_IN[1],TXCHARISK_IN[2],TXCHARISK_IN[3]}),
- .D(rx_cc_i),
- .GEN_A(gen_a_i),
- .GEN_ECP(gen_ecp_i),
- .GEN_SCP(GEN_SCP),
- .GEN_SUF(GEN_SUF),
- .HPCNT_RESET(HPCNT_RESET),
- .LANE_UP(LANE_UP),
- .LINK_RESET_OUT(LINK_RESET_OUT),
- .Q({rx_pad_descram_in[0],rx_pad_descram_in[1]}),
- .RXCHARISK(rx_char_is_k_i),
- .RXDATA(rx_data_i),
- .RXDISPERR({rx_disp_err_i[3],rx_disp_err_i[0]}),
- .RXNOTINTABLE({rx_not_in_table_i[3],rx_not_in_table_i[0]}),
- .\RX_CHAR_IS_COMMA_R_reg[3] (rx_char_is_comma_i),
- .\RX_PE_DATA_V_reg[0] ({rx_pe_data_v_striped_i[0],rx_pe_data_v_striped_i[1]}),
- .\RX_SUF_Buffer_reg[0] ({rx_suf_striped_i[0],rx_suf_striped_i[1]}),
- .\RX_SUF_Buffer_reg[1] (east_channel_aurora_lane_4byte_0_i_n_60),
- .\SOFT_ERR_Buffer_reg[0] ({soft_err_i[0],soft_err_i[1]}),
- .SS(east_channel_global_logic_i_n_19),
- .TXDATA(TXDATA_IN),
- .\bypass_r_reg[0] (CHANNEL_UP),
- .\data_nxt2_reg[25] (east_channel_aurora_lane_4byte_0_i_n_59),
- .\data_nxt2_reg[26] (east_channel_aurora_lane_4byte_0_i_n_57),
- .\data_nxt2_reg[26]_0 (east_channel_aurora_lane_4byte_0_i_n_58),
- .ena_comma_align_i(ena_comma_align_i),
- .\fc_nb_r_reg[0] (east_channel_tx_ll_i_n_6),
- .\fc_nb_r_reg[1] (east_channel_tx_ll_i_n_7),
- .\fc_nb_r_reg[2] (east_channel_tx_ll_i_n_8),
- .gen_cc_i(gen_cc_i),
- .\gen_k_r_reg[0] ({gen_k_i[0],gen_k_i[1],gen_k_i[2],gen_k_i[3]}),
- .\gen_pad_r_reg[0] ({gen_pad_i[0],gen_pad_i[1]}),
- .\gen_r_r_reg[0] ({gen_r_i[0],gen_r_i[1],gen_r_i[2],gen_r_i[3]}),
- .\gen_v_r_reg[1] ({gen_v_i[1],gen_v_i[2],gen_v_i[3]}),
- .got_v_i(got_v_i),
- .hard_err_gt0(\east_channel_err_detect_4byte_i/hard_err_gt0 ),
- .hard_err_i(hard_err_i),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (east_channel_aurora_lane_4byte_0_i_n_3),
- .\left_align_select_r_reg[0]_0 (gt_wrapper_i_n_68),
- .\left_align_select_r_reg[1] (east_channel_aurora_lane_4byte_0_i_n_4),
- .\left_align_select_r_reg[1]_0 (gt_wrapper_i_n_69),
- .neqOp(neqOp),
- .p_8_out(\east_channel_sym_dec_4byte_i/p_8_out ),
- .p_9_out(\east_channel_sym_dec_4byte_i/p_9_out ),
- .\previous_cycle_control_r_reg[0] (\east_channel_sym_dec_4byte_i/previous_cycle_control_r ),
- .\previous_cycle_data_r_reg[7] ({east_channel_aurora_lane_4byte_0_i_n_13,east_channel_aurora_lane_4byte_0_i_n_14,east_channel_aurora_lane_4byte_0_i_n_15,east_channel_aurora_lane_4byte_0_i_n_16,east_channel_aurora_lane_4byte_0_i_n_17,east_channel_aurora_lane_4byte_0_i_n_18,east_channel_aurora_lane_4byte_0_i_n_19,east_channel_aurora_lane_4byte_0_i_n_20}),
- .ready_r_reg(east_channel_aurora_lane_4byte_0_i_n_12),
- .reset_count_r_reg(gt_wrapper_i_n_70),
- .reset_lanes_i(reset_lanes_i),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .\soft_err_r_reg[0] (gt_wrapper_i_n_73),
- .\soft_err_r_reg[1] (gt_wrapper_i_n_71),
- .\soft_err_r_reg[2] (gt_wrapper_i_n_72),
- .\soft_err_r_reg[3] (gt_wrapper_i_n_74),
- .\tx_pe_data_r_reg[0] ({tx_pe_data_i[0],tx_pe_data_i[1],tx_pe_data_i[2],tx_pe_data_i[3],tx_pe_data_i[4],tx_pe_data_i[5],tx_pe_data_i[6],tx_pe_data_i[7],tx_pe_data_i[8],tx_pe_data_i[9],tx_pe_data_i[10],tx_pe_data_i[11],tx_pe_data_i[12],tx_pe_data_i[13],tx_pe_data_i[14],tx_pe_data_i[15],tx_pe_data_i[16],tx_pe_data_i[17],tx_pe_data_i[18],tx_pe_data_i[19],tx_pe_data_i[20],tx_pe_data_i[21],tx_pe_data_i[22],tx_pe_data_i[23],tx_pe_data_i[24],tx_pe_data_i[25],tx_pe_data_i[26],tx_pe_data_i[27],tx_pe_data_i[28],tx_pe_data_i[29],tx_pe_data_i[30],tx_pe_data_i[31]}),
- .\tx_pe_data_v_r_reg[0] ({tx_pe_data_v_i[0],tx_pe_data_v_i[1]}),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (gt_wrapper_i_n_91),
- .\word_aligned_control_bits_r_reg[3] (gt_wrapper_i_n_92),
- .\word_aligned_data_r_reg[16] ({gt_wrapper_i_n_75,gt_wrapper_i_n_76,gt_wrapper_i_n_77,gt_wrapper_i_n_78,gt_wrapper_i_n_79,gt_wrapper_i_n_80,gt_wrapper_i_n_81,gt_wrapper_i_n_82}),
- .\word_aligned_data_r_reg[24] ({gt_wrapper_i_n_83,gt_wrapper_i_n_84,gt_wrapper_i_n_85,gt_wrapper_i_n_86,gt_wrapper_i_n_87,gt_wrapper_i_n_88,gt_wrapper_i_n_89,gt_wrapper_i_n_90}));
- east_channel_east_channel_GLOBAL_LOGIC east_channel_global_logic_i
- (.CHANNEL_UP_Buffer_reg(CHANNEL_UP),
- .CHANNEL_UP_Buffer_reg_0(east_channel_global_logic_i_n_20),
- .D(rx_cc_i),
- .GEN_A(gen_a_i),
- .GTRXRESET_OUT(GTRXRESET_OUT),
- .HARD_ERR(HARD_ERR),
- .LANE_UP(LANE_UP),
- .POWER_DOWN(POWER_DOWN),
- .RESET(RESET_0),
- .SOFT_ERR(SOFT_ERR),
- .SS(east_channel_global_logic_i_n_19),
- .START_RX(START_RX),
- .\downcounter_r_reg[2] (sys_reset_out),
- .gen_k_flop_0_i({gen_k_i[0],gen_k_i[1],gen_k_i[2],gen_k_i[3]}),
- .gen_r_flop_0_i({gen_r_i[0],gen_r_i[1],gen_r_i[2],gen_r_i[3]}),
- .gen_v_flop_1_i({gen_v_i[1],gen_v_i[2],gen_v_i[3]}),
- .got_v_i(got_v_i),
- .hard_err_i(hard_err_i),
- .reset_channel_i(reset_channel_i),
- .reset_lanes_i(reset_lanes_i),
- .\soft_err_r_reg[0] ({soft_err_i[0],soft_err_i[1]}),
- .user_clk(user_clk),
- .wait_for_lane_up_r0(\channel_init_sm_i/wait_for_lane_up_r0 ));
- east_channel_east_channel_RX_LL east_channel_rx_ll_i
- (.D({rx_pe_data_v_striped_i[0],rx_pe_data_v_striped_i[1]}),
- .FRAME_ERR(FRAME_ERR),
- .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
- .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
- .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
- .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
- .M_AXI_UFC_RX_TKEEP(\^M_AXI_UFC_RX_TKEEP ),
- .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
- .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
- .Q({rx_pad_descram_in[0],rx_pad_descram_in[1]}),
- .RESET(RESET_0),
- .\RX_REM_Buffer_reg[0] ({east_channel_rx_ll_i_n_5,east_channel_rx_ll_i_n_6}),
- .START_RX(START_RX),
- .neqOp(neqOp),
- .p_8_out(\east_channel_sym_dec_4byte_i/p_8_out ),
- .p_9_out(\east_channel_sym_dec_4byte_i/p_9_out ),
- .rx_eof(rx_eof),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .\rx_suf_r_reg[0] ({rx_suf_striped_i[0],rx_suf_striped_i[1]}),
- .\stage_1_count_value_r_reg[0] (east_channel_aurora_lane_4byte_0_i_n_60),
- .\stage_1_count_value_r_reg[1] (east_channel_aurora_lane_4byte_0_i_n_59),
- .\stage_1_count_value_r_reg[2] (east_channel_aurora_lane_4byte_0_i_n_58),
- .\stage_1_count_value_r_reg[3] (east_channel_aurora_lane_4byte_0_i_n_57),
- .user_clk(user_clk));
- east_channel_east_channel_TX_LL east_channel_tx_ll_i
- (.DO_CC_I(DO_CC_I),
- .GEN_ECP(gen_ecp_i),
- .\GEN_PAD_Buffer_reg[0] ({gen_pad_i[0],gen_pad_i[1]}),
- .GEN_SCP(GEN_SCP),
- .GEN_SUF(GEN_SUF),
- .Q({tx_pe_data_v_i[0],tx_pe_data_v_i[1]}),
- .S_AXI_TX_TDATA(S_AXI_TX_TDATA),
- .S_AXI_TX_TKEEP(S_AXI_TX_TKEEP),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TREADY(S_AXI_TX_TREADY),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .S_AXI_UFC_TX_MS(S_AXI_UFC_TX_MS),
- .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
- .\TX_PE_DATA_Buffer_reg[0] ({tx_pe_data_i[0],tx_pe_data_i[1],tx_pe_data_i[2],tx_pe_data_i[3],tx_pe_data_i[4],tx_pe_data_i[5],tx_pe_data_i[6],tx_pe_data_i[7],tx_pe_data_i[8],tx_pe_data_i[9],tx_pe_data_i[10],tx_pe_data_i[11],tx_pe_data_i[12],tx_pe_data_i[13],tx_pe_data_i[14],tx_pe_data_i[15],tx_pe_data_i[16],tx_pe_data_i[17],tx_pe_data_i[18],tx_pe_data_i[19],tx_pe_data_i[20],tx_pe_data_i[21],tx_pe_data_i[22],tx_pe_data_i[23],tx_pe_data_i[24],tx_pe_data_i[25],tx_pe_data_i[26],tx_pe_data_i[27],tx_pe_data_i[28],tx_pe_data_i[29],tx_pe_data_i[30],tx_pe_data_i[31]}),
- .WARN_CC(WARN_CC),
- .gen_cc_i(gen_cc_i),
- .in_frame_r_reg(east_channel_global_logic_i_n_20),
- .next_ufc_idle_c(\tx_ll_control_i/next_ufc_idle_c ),
- .\s_axi_ufc_tx_tdata[0] (east_channel_tx_ll_i_n_6),
- .\s_axi_ufc_tx_tdata[1] (east_channel_tx_ll_i_n_7),
- .\s_axi_ufc_tx_tdata[2] (east_channel_tx_ll_i_n_8),
- .tx_dst_rdy(tx_dst_rdy),
- .\tx_pe_data_v_r_reg[1] (axi_to_ll_pdu_i_n_0),
- .ufc_header_r_reg(S_AXI_UFC_TX_ACK),
- .\ufc_message_count_r_reg[2] (east_channel_tx_ll_i_n_10),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized1 gt_reset_cdc_sync
- (.AR(gt_reset_sync_init_clk),
- .GT_RESET(GT_RESET),
- .init_clk_in(init_clk_in));
- east_channel_east_channel_GT_WRAPPER gt_wrapper_i
- (.AR(gt_reset_sync_init_clk),
- .DRPADDR_IN(DRPADDR_IN),
- .DRPDI_IN(DRPDI_IN),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE_IN(DRPWE_IN),
- .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg (gt_wrapper_i_n_96),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .GTRXRESET_OUT(GTRXRESET_OUT),
- .LOOPBACK(LOOPBACK),
- .PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .POWER_DOWN(POWER_DOWN),
- .RXCHARISK(rx_char_is_k_i),
- .RXDATA(rx_data_i),
- .RXDISPERR({rx_disp_err_i[3],rx_disp_err_i[0]}),
- .RXN(RXN),
- .RXNOTINTABLE({rx_not_in_table_i[3],rx_not_in_table_i[0]}),
- .RXP(RXP),
- .RX_RESETDONE_OUT(RX_RESETDONE_OUT),
- .TXDATA(TXDATA_IN),
- .TXN(TXN),
- .TXP(TXP),
- .TX_OUT_CLK(TX_OUT_CLK),
- .TX_RESETDONE_OUT(TX_RESETDONE_OUT),
- .drpclk_in(drpclk_in),
- .drpclk_in_0(DRPRDY_OUT),
- .drpclk_in_1(rx_char_is_comma_i),
- .drpclk_in_2(gt_wrapper_i_n_71),
- .drpclk_in_3(gt_wrapper_i_n_72),
- .drpclk_in_4(gt_wrapper_i_n_73),
- .drpclk_in_5(gt_wrapper_i_n_74),
- .drprdy_out({TXCHARISK_IN[0],TXCHARISK_IN[1],TXCHARISK_IN[2],TXCHARISK_IN[3]}),
- .ena_comma_align_i(ena_comma_align_i),
- .gt_common_reset_out(gt_common_reset_out),
- .hard_err_gt0(\east_channel_err_detect_4byte_i/hard_err_gt0 ),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (gt_wrapper_i_n_68),
- .\left_align_select_r_reg[0]_0 (east_channel_aurora_lane_4byte_0_i_n_12),
- .\left_align_select_r_reg[0]_1 (east_channel_aurora_lane_4byte_0_i_n_3),
- .\left_align_select_r_reg[1] (gt_wrapper_i_n_69),
- .\left_align_select_r_reg[1]_0 ({gt_wrapper_i_n_75,gt_wrapper_i_n_76,gt_wrapper_i_n_77,gt_wrapper_i_n_78,gt_wrapper_i_n_79,gt_wrapper_i_n_80,gt_wrapper_i_n_81,gt_wrapper_i_n_82}),
- .\left_align_select_r_reg[1]_1 ({gt_wrapper_i_n_83,gt_wrapper_i_n_84,gt_wrapper_i_n_85,gt_wrapper_i_n_86,gt_wrapper_i_n_87,gt_wrapper_i_n_88,gt_wrapper_i_n_89,gt_wrapper_i_n_90}),
- .\left_align_select_r_reg[1]_2 (gt_wrapper_i_n_91),
- .\left_align_select_r_reg[1]_3 (gt_wrapper_i_n_92),
- .\left_align_select_r_reg[1]_4 (east_channel_aurora_lane_4byte_0_i_n_4),
- .link_reset_r(link_reset_r),
- .quad1_common_lock_in(quad1_common_lock_in),
- .rst_r_reg(gt_wrapper_i_n_70),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .rxfsm_rxresetdone_r3_reg_0(gt_wrapper_i_n_95),
- .sync_clk(sync_clk),
- .tx_lock(tx_lock),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (\east_channel_sym_dec_4byte_i/previous_cycle_control_r ),
- .\word_aligned_data_r_reg[16] ({east_channel_aurora_lane_4byte_0_i_n_13,east_channel_aurora_lane_4byte_0_i_n_14,east_channel_aurora_lane_4byte_0_i_n_15,east_channel_aurora_lane_4byte_0_i_n_16,east_channel_aurora_lane_4byte_0_i_n_17,east_channel_aurora_lane_4byte_0_i_n_18,east_channel_aurora_lane_4byte_0_i_n_19,east_channel_aurora_lane_4byte_0_i_n_20}));
- east_channel_east_channel_cdc_sync__parameterized1_0 hpcnt_reset_cdc_sync
- (.AR(gt_reset_sync_init_clk),
- .HPCNT_RESET(HPCNT_RESET),
- .RESET(RESET),
- .init_clk_in(init_clk_in));
- east_channel_east_channel_LL_TO_AXI ll_to_axi_pdu_i
- (.M_AXI_RX_TKEEP({\^M_AXI_RX_TKEEP [1],\^M_AXI_RX_TKEEP [2],\^M_AXI_RX_TKEEP [3]}),
- .\m_axi_rx_tkeep[1] ({east_channel_rx_ll_i_n_5,east_channel_rx_ll_i_n_6}),
- .rx_eof(rx_eof));
- east_channel_east_channel_cdc_sync reset_sync_user_clk_cdc_sync
- (.RESET(RESET),
- .out(reset_sync_user_clk),
- .user_clk(user_clk));
- east_channel_east_channel_STANDARD_CC_MODULE standard_cc_module_i
- (.DO_CC_I(DO_CC_I),
- .DO_CC_reg_0(sys_reset_out),
- .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
- .WARN_CC(WARN_CC),
- .next_ufc_idle_c(\tx_ll_control_i/next_ufc_idle_c ),
- .ufc_idle_r_reg(east_channel_tx_ll_i_n_10),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_gt" *)
-module east_channel_east_channel_gt
- (drpclk_in_0,
- TXN,
- TXP,
- rx_realign_i,
- drpclk_in_1,
- TX_OUT_CLK,
- drpclk_in_2,
- DRPDO_OUT,
- RXDATA,
- drpclk_in_3,
- RXCHARISK,
- RXDISPERR,
- RXNOTINTABLE,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- rst_r_reg,
- drpclk_in_4,
- drpclk_in_5,
- drpclk_in_6,
- drpclk_in_7,
- \left_align_select_r_reg[1]_0 ,
- \left_align_select_r_reg[1]_1 ,
- \left_align_select_r_reg[1]_2 ,
- \left_align_select_r_reg[1]_3 ,
- hard_err_gt0,
- drpclk_in,
- RXN,
- RXP,
- gt_tx_reset_i,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- ena_comma_align_i,
- rx_polarity_i,
- gt_rxuserrdy_i,
- sync_clk,
- user_clk,
- POWER_DOWN,
- gt_txuserrdy_i,
- LOOPBACK,
- TXDATA,
- drprdy_out,
- gt_common_reset_out,
- init_clk_in,
- SR,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[0]_1 ,
- \left_align_select_r_reg[1]_4 ,
- tx_reset_i,
- \word_aligned_data_r_reg[16] ,
- \word_aligned_control_bits_r_reg[2] ,
- DRPADDR_IN,
- DRPDI_IN,
- DRPWE_IN,
- DRPEN_IN);
- output drpclk_in_0;
- output TXN;
- output TXP;
- output rx_realign_i;
- output drpclk_in_1;
- output TX_OUT_CLK;
- output drpclk_in_2;
- output [15:0]DRPDO_OUT;
- output [31:0]RXDATA;
- output [3:0]drpclk_in_3;
- output [3:0]RXCHARISK;
- output [1:0]RXDISPERR;
- output [1:0]RXNOTINTABLE;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output rst_r_reg;
- output drpclk_in_4;
- output drpclk_in_5;
- output drpclk_in_6;
- output drpclk_in_7;
- output [7:0]\left_align_select_r_reg[1]_0 ;
- output [7:0]\left_align_select_r_reg[1]_1 ;
- output \left_align_select_r_reg[1]_2 ;
- output \left_align_select_r_reg[1]_3 ;
- output hard_err_gt0;
- input drpclk_in;
- input RXN;
- input RXP;
- input gt_tx_reset_i;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- input ena_comma_align_i;
- input rx_polarity_i;
- input gt_rxuserrdy_i;
- input sync_clk;
- input user_clk;
- input POWER_DOWN;
- input gt_txuserrdy_i;
- input [2:0]LOOPBACK;
- input [31:0]TXDATA;
- input [3:0]drprdy_out;
- input gt_common_reset_out;
- input init_clk_in;
- input [0:0]SR;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[0]_1 ;
- input \left_align_select_r_reg[1]_4 ;
- input tx_reset_i;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input [0:0]\word_aligned_control_bits_r_reg[2] ;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- input DRPWE_IN;
- input DRPEN_IN;
-
- wire [4:0]DRPADDR;
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN;
- wire DRPEN_IN;
- wire DRPWE;
- wire DRPWE_IN;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire GTRXRESET;
- wire [2:0]LOOPBACK;
- wire POWER_DOWN;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire RXN;
- wire [1:0]RXNOTINTABLE;
- wire RXP;
- wire [0:0]SR;
- wire [31:0]TXDATA;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire drp_op_done;
- wire drpclk_in;
- wire drpclk_in_0;
- wire drpclk_in_1;
- wire drpclk_in_2;
- wire [3:0]drpclk_in_3;
- wire drpclk_in_4;
- wire drpclk_in_5;
- wire drpclk_in_6;
- wire drpclk_in_7;
- wire [3:0]drprdy_out;
- wire ena_comma_align_i;
- wire gt_common_reset_out;
- wire gt_rxuserrdy_i;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire gtpe2_i_n_1;
- wire gtpe2_i_n_102;
- wire gtpe2_i_n_104;
- wire gtpe2_i_n_105;
- wire gtpe2_i_n_14;
- wire gtpe2_i_n_24;
- wire gtpe2_i_n_28;
- wire gtpe2_i_n_29;
- wire gtpe2_i_n_39;
- wire gtpe2_i_n_40;
- wire gtpe2_i_n_48;
- wire gtpe2_i_n_49;
- wire gtpe2_i_n_50;
- wire gtpe2_i_n_51;
- wire gtpe2_i_n_52;
- wire gtpe2_i_n_53;
- wire gtpe2_i_n_54;
- wire gtpe2_i_n_55;
- wire gtpe2_i_n_56;
- wire gtpe2_i_n_57;
- wire gtpe2_i_n_58;
- wire gtpe2_i_n_59;
- wire gtpe2_i_n_60;
- wire gtpe2_i_n_61;
- wire gtpe2_i_n_62;
- wire gtpe2_i_n_7;
- wire gtpe2_i_n_9;
- wire gtpe2_i_n_95;
- wire gtpe2_i_n_96;
- wire gtrxreset_seq_i_n_10;
- wire gtrxreset_seq_i_n_17;
- wire gtrxreset_seq_i_n_2;
- wire gtrxreset_seq_i_n_4;
- wire gtrxreset_seq_i_n_5;
- wire gtrxreset_seq_i_n_6;
- wire gtrxreset_seq_i_n_7;
- wire gtrxreset_seq_i_n_8;
- wire gtrxreset_seq_i_n_9;
- wire hard_err_gt0;
- wire [15:0]in7;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1] ;
- wire [7:0]\left_align_select_r_reg[1]_0 ;
- wire [7:0]\left_align_select_r_reg[1]_1 ;
- wire \left_align_select_r_reg[1]_2 ;
- wire \left_align_select_r_reg[1]_3 ;
- wire \left_align_select_r_reg[1]_4 ;
- wire p_0_in;
- wire rst_r_reg;
- wire rx_buf_err_i;
- wire [2:1]rx_disp_err_i;
- wire [2:1]rx_not_in_table_i;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire sync_clk;
- wire tx_buf_err_i;
- wire tx_reset_i;
- wire user_clk;
- wire [0:0]\word_aligned_control_bits_r_reg[2] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
- wire NLW_gtpe2_i_PHYSTATUS_UNCONNECTED;
- wire NLW_gtpe2_i_PMARSVDOUT0_UNCONNECTED;
- wire NLW_gtpe2_i_PMARSVDOUT1_UNCONNECTED;
- wire NLW_gtpe2_i_RXCHANBONDSEQ_UNCONNECTED;
- wire NLW_gtpe2_i_RXCHANISALIGNED_UNCONNECTED;
- wire NLW_gtpe2_i_RXCHANREALIGN_UNCONNECTED;
- wire NLW_gtpe2_i_RXCOMINITDET_UNCONNECTED;
- wire NLW_gtpe2_i_RXCOMSASDET_UNCONNECTED;
- wire NLW_gtpe2_i_RXCOMWAKEDET_UNCONNECTED;
- wire NLW_gtpe2_i_RXDLYSRESETDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXELECIDLE_UNCONNECTED;
- wire NLW_gtpe2_i_RXHEADERVALID_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTSTARTED_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
- wire NLW_gtpe2_i_RXOUTCLKFABRIC_UNCONNECTED;
- wire NLW_gtpe2_i_RXOUTCLKPCS_UNCONNECTED;
- wire NLW_gtpe2_i_RXPHALIGNDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXRATEDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXSYNCDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXSYNCOUT_UNCONNECTED;
- wire NLW_gtpe2_i_RXVALID_UNCONNECTED;
- wire NLW_gtpe2_i_TXCOMFINISH_UNCONNECTED;
- wire NLW_gtpe2_i_TXDLYSRESETDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXGEARBOXREADY_UNCONNECTED;
- wire NLW_gtpe2_i_TXPHALIGNDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXPHINITDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXPMARESETDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXRATEDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXSYNCDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXSYNCOUT_UNCONNECTED;
- wire [15:0]NLW_gtpe2_i_PCSRSVDOUT_UNCONNECTED;
- wire [3:0]NLW_gtpe2_i_RXCHBONDO_UNCONNECTED;
- wire [1:0]NLW_gtpe2_i_RXDATAVALID_UNCONNECTED;
- wire [2:0]NLW_gtpe2_i_RXHEADER_UNCONNECTED;
- wire [4:0]NLW_gtpe2_i_RXPHMONITOR_UNCONNECTED;
- wire [4:0]NLW_gtpe2_i_RXPHSLIPMONITOR_UNCONNECTED;
- wire [1:0]NLW_gtpe2_i_RXSTARTOFSEQ_UNCONNECTED;
- wire [2:0]NLW_gtpe2_i_RXSTATUS_UNCONNECTED;
-
- (* BOX_TYPE = "PRIMITIVE" *)
- GTPE2_CHANNEL #(
- .ACJTAG_DEBUG_MODE(1'b0),
- .ACJTAG_MODE(1'b0),
- .ACJTAG_RESET(1'b0),
- .ADAPT_CFG0(20'b00000000000000000000),
- .ALIGN_COMMA_DOUBLE("FALSE"),
- .ALIGN_COMMA_ENABLE(10'b1111111111),
- .ALIGN_COMMA_WORD(2),
- .ALIGN_MCOMMA_DET("TRUE"),
- .ALIGN_MCOMMA_VALUE(10'b1010000011),
- .ALIGN_PCOMMA_DET("TRUE"),
- .ALIGN_PCOMMA_VALUE(10'b0101111100),
- .CBCC_DATA_SOURCE_SEL("DECODED"),
- .CFOK_CFG(43'b1001001000000000000000001000000111010000000),
- .CFOK_CFG2(7'b0100000),
- .CFOK_CFG3(7'b0100000),
- .CFOK_CFG4(1'b0),
- .CFOK_CFG5(2'b00),
- .CFOK_CFG6(4'b0000),
- .CHAN_BOND_KEEP_ALIGN("FALSE"),
- .CHAN_BOND_MAX_SKEW(7),
- .CHAN_BOND_SEQ_1_1(10'b0101111100),
- .CHAN_BOND_SEQ_1_2(10'b0000000000),
- .CHAN_BOND_SEQ_1_3(10'b0000000000),
- .CHAN_BOND_SEQ_1_4(10'b0000000000),
- .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
- .CHAN_BOND_SEQ_2_1(10'b0000000000),
- .CHAN_BOND_SEQ_2_2(10'b0000000000),
- .CHAN_BOND_SEQ_2_3(10'b0000000000),
- .CHAN_BOND_SEQ_2_4(10'b0000000000),
- .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
- .CHAN_BOND_SEQ_2_USE("FALSE"),
- .CHAN_BOND_SEQ_LEN(1),
- .CLK_COMMON_SWING(1'b0),
- .CLK_CORRECT_USE("TRUE"),
- .CLK_COR_KEEP_IDLE("FALSE"),
- .CLK_COR_MAX_LAT(31),
- .CLK_COR_MIN_LAT(24),
- .CLK_COR_PRECEDENCE("TRUE"),
- .CLK_COR_REPEAT_WAIT(0),
- .CLK_COR_SEQ_1_1(10'b0111110111),
- .CLK_COR_SEQ_1_2(10'b0111110111),
- .CLK_COR_SEQ_1_3(10'b0111110111),
- .CLK_COR_SEQ_1_4(10'b0111110111),
- .CLK_COR_SEQ_1_ENABLE(4'b1111),
- .CLK_COR_SEQ_2_1(10'b0100000000),
- .CLK_COR_SEQ_2_2(10'b0100000000),
- .CLK_COR_SEQ_2_3(10'b0100000000),
- .CLK_COR_SEQ_2_4(10'b0100000000),
- .CLK_COR_SEQ_2_ENABLE(4'b1111),
- .CLK_COR_SEQ_2_USE("FALSE"),
- .CLK_COR_SEQ_LEN(4),
- .DEC_MCOMMA_DETECT("TRUE"),
- .DEC_PCOMMA_DETECT("TRUE"),
- .DEC_VALID_COMMA_ONLY("FALSE"),
- .DMONITOR_CFG(24'h000A00),
- .ES_CLK_PHASE_SEL(1'b0),
- .ES_CONTROL(6'b000000),
- .ES_ERRDET_EN("FALSE"),
- .ES_EYE_SCAN_EN("FALSE"),
- .ES_HORZ_OFFSET(12'h010),
- .ES_PMA_CFG(10'b0000000000),
- .ES_PRESCALE(5'b00000),
- .ES_QUALIFIER(80'h00000000000000000000),
- .ES_QUAL_MASK(80'h00000000000000000000),
- .ES_SDATA_MASK(80'h00000000000000000000),
- .ES_VERT_OFFSET(9'b000000000),
- .FTS_DESKEW_SEQ_ENABLE(4'b1111),
- .FTS_LANE_DESKEW_CFG(4'b1111),
- .FTS_LANE_DESKEW_EN("FALSE"),
- .GEARBOX_MODE(3'b000),
- .IS_CLKRSVD0_INVERTED(1'b0),
- .IS_CLKRSVD1_INVERTED(1'b0),
- .IS_DMONITORCLK_INVERTED(1'b0),
- .IS_DRPCLK_INVERTED(1'b0),
- .IS_RXUSRCLK2_INVERTED(1'b0),
- .IS_RXUSRCLK_INVERTED(1'b0),
- .IS_SIGVALIDCLK_INVERTED(1'b0),
- .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
- .IS_TXUSRCLK2_INVERTED(1'b0),
- .IS_TXUSRCLK_INVERTED(1'b0),
- .LOOPBACK_CFG(1'b0),
- .OUTREFCLK_SEL_INV(2'b11),
- .PCS_PCIE_EN("FALSE"),
- .PCS_RSVD_ATTR(48'h000000000000),
- .PD_TRANS_TIME_FROM_P2(12'h03C),
- .PD_TRANS_TIME_NONE_P2(8'h3C),
- .PD_TRANS_TIME_TO_P2(8'h64),
- .PMA_LOOPBACK_CFG(1'b0),
- .PMA_RSV(32'h00000333),
- .PMA_RSV2(32'h00002040),
- .PMA_RSV3(2'b00),
- .PMA_RSV4(4'b0000),
- .PMA_RSV5(1'b0),
- .PMA_RSV6(1'b0),
- .PMA_RSV7(1'b0),
- .RXBUFRESET_TIME(5'b00001),
- .RXBUF_ADDR_MODE("FULL"),
- .RXBUF_EIDLE_HI_CNT(4'b1000),
- .RXBUF_EIDLE_LO_CNT(4'b0000),
- .RXBUF_EN("TRUE"),
- .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
- .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
- .RXBUF_RESET_ON_EIDLE("FALSE"),
- .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
- .RXBUF_THRESH_OVFLW(61),
- .RXBUF_THRESH_OVRD("FALSE"),
- .RXBUF_THRESH_UNDFLW(4),
- .RXCDRFREQRESET_TIME(5'b00001),
- .RXCDRPHRESET_TIME(5'b00001),
- .RXCDR_CFG(83'h0000107FE406001041010),
- .RXCDR_FR_RESET_ON_EIDLE(1'b0),
- .RXCDR_HOLD_DURING_EIDLE(1'b0),
- .RXCDR_LOCK_CFG(6'b001001),
- .RXCDR_PH_RESET_ON_EIDLE(1'b0),
- .RXDLY_CFG(16'h001F),
- .RXDLY_LCFG(9'h030),
- .RXDLY_TAP_CFG(16'h0000),
- .RXGEARBOX_EN("FALSE"),
- .RXISCANRESET_TIME(5'b00001),
- .RXLPMRESET_TIME(7'b0001111),
- .RXLPM_BIAS_STARTUP_DISABLE(1'b0),
- .RXLPM_CFG(4'b0110),
- .RXLPM_CFG1(1'b0),
- .RXLPM_CM_CFG(1'b0),
- .RXLPM_GC_CFG(9'b111100010),
- .RXLPM_GC_CFG2(3'b001),
- .RXLPM_HF_CFG(14'b00001111110000),
- .RXLPM_HF_CFG2(5'b01010),
- .RXLPM_HF_CFG3(4'b0000),
- .RXLPM_HOLD_DURING_EIDLE(1'b0),
- .RXLPM_INCM_CFG(1'b1),
- .RXLPM_IPCM_CFG(1'b0),
- .RXLPM_LF_CFG(18'b000000001111110000),
- .RXLPM_LF_CFG2(5'b01010),
- .RXLPM_OSINT_CFG(3'b100),
- .RXOOB_CFG(7'b0000110),
- .RXOOB_CLK_CFG("PMA"),
- .RXOSCALRESET_TIME(5'b00011),
- .RXOSCALRESET_TIMEOUT(5'b00000),
- .RXOUT_DIV(1),
- .RXPCSRESET_TIME(5'b00001),
- .RXPHDLY_CFG(24'h084020),
- .RXPH_CFG(24'hC00002),
- .RXPH_MONITOR_SEL(5'b00000),
- .RXPI_CFG0(3'b000),
- .RXPI_CFG1(1'b1),
- .RXPI_CFG2(1'b1),
- .RXPMARESET_TIME(5'b00011),
- .RXPRBS_ERR_LOOPBACK(1'b0),
- .RXSLIDE_AUTO_WAIT(7),
- .RXSLIDE_MODE("OFF"),
- .RXSYNC_MULTILANE(1'b0),
- .RXSYNC_OVRD(1'b0),
- .RXSYNC_SKIP_DA(1'b0),
- .RX_BIAS_CFG(16'b0000111100110011),
- .RX_BUFFER_CFG(6'b000000),
- .RX_CLK25_DIV(5),
- .RX_CLKMUX_EN(1'b1),
- .RX_CM_SEL(2'b11),
- .RX_CM_TRIM(4'b1010),
- .RX_DATA_WIDTH(40),
- .RX_DDI_SEL(6'b000000),
- .RX_DEBUG_CFG(14'b00000000000000),
- .RX_DEFER_RESET_BUF_EN("TRUE"),
- .RX_DISPERR_SEQ_MATCH("TRUE"),
- .RX_OS_CFG(13'b0000010000000),
- .RX_SIG_VALID_DLY(10),
- .RX_XCLK_SEL("RXREC"),
- .SAS_MAX_COM(64),
- .SAS_MIN_COM(36),
- .SATA_BURST_SEQ_LEN(4'b0101),
- .SATA_BURST_VAL(3'b100),
- .SATA_EIDLE_VAL(3'b100),
- .SATA_MAX_BURST(8),
- .SATA_MAX_INIT(21),
- .SATA_MAX_WAKE(7),
- .SATA_MIN_BURST(4),
- .SATA_MIN_INIT(12),
- .SATA_MIN_WAKE(4),
- .SATA_PLL_CFG("VCO_3000MHZ"),
- .SHOW_REALIGN_COMMA("TRUE"),
- .SIM_RECEIVER_DETECT_PASS("TRUE"),
- .SIM_RESET_SPEEDUP("FALSE"),
- .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
- .SIM_VERSION("2.0"),
- .TERM_RCAL_CFG(15'b100001000010000),
- .TERM_RCAL_OVRD(3'b000),
- .TRANS_TIME_RATE(8'h0E),
- .TST_RSV(32'h00000000),
- .TXBUF_EN("TRUE"),
- .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
- .TXDLY_CFG(16'h001F),
- .TXDLY_LCFG(9'h030),
- .TXDLY_TAP_CFG(16'h0000),
- .TXGEARBOX_EN("FALSE"),
- .TXOOB_CFG(1'b0),
- .TXOUT_DIV(1),
- .TXPCSRESET_TIME(5'b00001),
- .TXPHDLY_CFG(24'h084020),
- .TXPH_CFG(16'h0780),
- .TXPH_MONITOR_SEL(5'b00000),
- .TXPI_CFG0(2'b00),
- .TXPI_CFG1(2'b00),
- .TXPI_CFG2(2'b00),
- .TXPI_CFG3(1'b0),
- .TXPI_CFG4(1'b0),
- .TXPI_CFG5(3'b000),
- .TXPI_GREY_SEL(1'b0),
- .TXPI_INVSTROBE_SEL(1'b0),
- .TXPI_PPMCLK_SEL("TXUSRCLK2"),
- .TXPI_PPM_CFG(8'b00000000),
- .TXPI_SYNFREQ_PPM(3'b000),
- .TXPMARESET_TIME(5'b00001),
- .TXSYNC_MULTILANE(1'b0),
- .TXSYNC_OVRD(1'b0),
- .TXSYNC_SKIP_DA(1'b0),
- .TX_CLK25_DIV(5),
- .TX_CLKMUX_EN(1'b1),
- .TX_DATA_WIDTH(40),
- .TX_DEEMPH0(6'b000000),
- .TX_DEEMPH1(6'b000000),
- .TX_DRIVE_MODE("DIRECT"),
- .TX_EIDLE_ASSERT_DELAY(3'b110),
- .TX_EIDLE_DEASSERT_DELAY(3'b100),
- .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
- .TX_MAINCURSOR_SEL(1'b0),
- .TX_MARGIN_FULL_0(7'b1001110),
- .TX_MARGIN_FULL_1(7'b1001001),
- .TX_MARGIN_FULL_2(7'b1000101),
- .TX_MARGIN_FULL_3(7'b1000010),
- .TX_MARGIN_FULL_4(7'b1000000),
- .TX_MARGIN_LOW_0(7'b1000110),
- .TX_MARGIN_LOW_1(7'b1000100),
- .TX_MARGIN_LOW_2(7'b1000010),
- .TX_MARGIN_LOW_3(7'b1000000),
- .TX_MARGIN_LOW_4(7'b1000000),
- .TX_PREDRIVER_MODE(1'b0),
- .TX_RXDETECT_CFG(14'h1832),
- .TX_RXDETECT_REF(3'b100),
- .TX_XCLK_SEL("TXOUT"),
- .UCODEER_CLR(1'b0),
- .USE_PCS_CLK_PHASE_SEL(1'b0))
- gtpe2_i
- (.CFGRESET(1'b0),
- .CLKRSVD0(1'b0),
- .CLKRSVD1(1'b0),
- .DMONFIFORESET(1'b0),
- .DMONITORCLK(1'b0),
- .DMONITOROUT({gtpe2_i_n_48,gtpe2_i_n_49,gtpe2_i_n_50,gtpe2_i_n_51,gtpe2_i_n_52,gtpe2_i_n_53,gtpe2_i_n_54,gtpe2_i_n_55,gtpe2_i_n_56,gtpe2_i_n_57,gtpe2_i_n_58,gtpe2_i_n_59,gtpe2_i_n_60,gtpe2_i_n_61,gtpe2_i_n_62}),
- .DRPADDR({gtrxreset_seq_i_n_4,gtrxreset_seq_i_n_5,gtrxreset_seq_i_n_6,gtrxreset_seq_i_n_7,DRPADDR[4],gtrxreset_seq_i_n_8,gtrxreset_seq_i_n_9,gtrxreset_seq_i_n_10,DRPADDR[0]}),
- .DRPCLK(drpclk_in),
- .DRPDI(DRPDI),
- .DRPDO(DRPDO_OUT),
- .DRPEN(DRPEN),
- .DRPRDY(drpclk_in_0),
- .DRPWE(DRPWE),
- .EYESCANDATAERROR(gtpe2_i_n_1),
- .EYESCANMODE(1'b0),
- .EYESCANRESET(1'b0),
- .EYESCANTRIGGER(1'b0),
- .GTPRXN(RXN),
- .GTPRXP(RXP),
- .GTPTXN(TXN),
- .GTPTXP(TXP),
- .GTRESETSEL(1'b0),
- .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .GTRXRESET(GTRXRESET),
- .GTTXRESET(gt_tx_reset_i),
- .LOOPBACK(LOOPBACK),
- .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCSRSVDOUT(NLW_gtpe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
- .PHYSTATUS(NLW_gtpe2_i_PHYSTATUS_UNCONNECTED),
- .PLL0CLK(GT0_PLL0OUTCLK_IN),
- .PLL0REFCLK(GT0_PLL0OUTREFCLK_IN),
- .PLL1CLK(GT0_PLL1OUTCLK_IN),
- .PLL1REFCLK(GT0_PLL1OUTREFCLK_IN),
- .PMARSVDIN0(1'b0),
- .PMARSVDIN1(1'b0),
- .PMARSVDIN2(1'b0),
- .PMARSVDIN3(1'b0),
- .PMARSVDIN4(1'b0),
- .PMARSVDOUT0(NLW_gtpe2_i_PMARSVDOUT0_UNCONNECTED),
- .PMARSVDOUT1(NLW_gtpe2_i_PMARSVDOUT1_UNCONNECTED),
- .RESETOVRD(1'b0),
- .RX8B10BEN(1'b1),
- .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .RXBUFRESET(1'b0),
- .RXBUFSTATUS({rx_buf_err_i,gtpe2_i_n_104,gtpe2_i_n_105}),
- .RXBYTEISALIGNED(gtpe2_i_n_7),
- .RXBYTEREALIGN(rx_realign_i),
- .RXCDRFREQRESET(1'b0),
- .RXCDRHOLD(1'b0),
- .RXCDRLOCK(gtpe2_i_n_9),
- .RXCDROVRDEN(1'b0),
- .RXCDRRESET(1'b0),
- .RXCDRRESETRSV(1'b0),
- .RXCHANBONDSEQ(NLW_gtpe2_i_RXCHANBONDSEQ_UNCONNECTED),
- .RXCHANISALIGNED(NLW_gtpe2_i_RXCHANISALIGNED_UNCONNECTED),
- .RXCHANREALIGN(NLW_gtpe2_i_RXCHANREALIGN_UNCONNECTED),
- .RXCHARISCOMMA(drpclk_in_3),
- .RXCHARISK(RXCHARISK),
- .RXCHBONDEN(1'b0),
- .RXCHBONDI({1'b0,1'b0,1'b0,1'b0}),
- .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
- .RXCHBONDMASTER(1'b0),
- .RXCHBONDO(NLW_gtpe2_i_RXCHBONDO_UNCONNECTED[3:0]),
- .RXCHBONDSLAVE(1'b0),
- .RXCLKCORCNT({gtpe2_i_n_95,gtpe2_i_n_96}),
- .RXCOMINITDET(NLW_gtpe2_i_RXCOMINITDET_UNCONNECTED),
- .RXCOMMADET(gtpe2_i_n_14),
- .RXCOMMADETEN(1'b1),
- .RXCOMSASDET(NLW_gtpe2_i_RXCOMSASDET_UNCONNECTED),
- .RXCOMWAKEDET(NLW_gtpe2_i_RXCOMWAKEDET_UNCONNECTED),
- .RXDATA(RXDATA),
- .RXDATAVALID(NLW_gtpe2_i_RXDATAVALID_UNCONNECTED[1:0]),
- .RXDDIEN(1'b0),
- .RXDFEXYDEN(1'b0),
- .RXDISPERR({RXDISPERR[1],rx_disp_err_i,RXDISPERR[0]}),
- .RXDLYBYPASS(1'b1),
- .RXDLYEN(1'b0),
- .RXDLYOVRDEN(1'b0),
- .RXDLYSRESET(1'b0),
- .RXDLYSRESETDONE(NLW_gtpe2_i_RXDLYSRESETDONE_UNCONNECTED),
- .RXELECIDLE(NLW_gtpe2_i_RXELECIDLE_UNCONNECTED),
- .RXELECIDLEMODE({1'b1,1'b1}),
- .RXGEARBOXSLIP(1'b0),
- .RXHEADER(NLW_gtpe2_i_RXHEADER_UNCONNECTED[2:0]),
- .RXHEADERVALID(NLW_gtpe2_i_RXHEADERVALID_UNCONNECTED),
- .RXLPMHFHOLD(1'b0),
- .RXLPMHFOVRDEN(1'b0),
- .RXLPMLFHOLD(1'b0),
- .RXLPMLFOVRDEN(1'b0),
- .RXLPMOSINTNTRLEN(1'b0),
- .RXLPMRESET(1'b0),
- .RXMCOMMAALIGNEN(ena_comma_align_i),
- .RXNOTINTABLE({RXNOTINTABLE[1],rx_not_in_table_i,RXNOTINTABLE[0]}),
- .RXOOBRESET(1'b0),
- .RXOSCALRESET(1'b0),
- .RXOSHOLD(1'b0),
- .RXOSINTCFG({1'b0,1'b0,1'b1,1'b0}),
- .RXOSINTDONE(NLW_gtpe2_i_RXOSINTDONE_UNCONNECTED),
- .RXOSINTEN(1'b1),
- .RXOSINTHOLD(1'b0),
- .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
- .RXOSINTNTRLEN(1'b0),
- .RXOSINTOVRDEN(1'b0),
- .RXOSINTPD(1'b0),
- .RXOSINTSTARTED(NLW_gtpe2_i_RXOSINTSTARTED_UNCONNECTED),
- .RXOSINTSTROBE(1'b0),
- .RXOSINTSTROBEDONE(NLW_gtpe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
- .RXOSINTSTROBESTARTED(NLW_gtpe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
- .RXOSINTTESTOVRDEN(1'b0),
- .RXOSOVRDEN(1'b0),
- .RXOUTCLK(gtpe2_i_n_24),
- .RXOUTCLKFABRIC(NLW_gtpe2_i_RXOUTCLKFABRIC_UNCONNECTED),
- .RXOUTCLKPCS(NLW_gtpe2_i_RXOUTCLKPCS_UNCONNECTED),
- .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
- .RXPCOMMAALIGNEN(ena_comma_align_i),
- .RXPCSRESET(1'b0),
- .RXPD({POWER_DOWN,POWER_DOWN}),
- .RXPHALIGN(1'b0),
- .RXPHALIGNDONE(NLW_gtpe2_i_RXPHALIGNDONE_UNCONNECTED),
- .RXPHALIGNEN(1'b0),
- .RXPHDLYPD(1'b0),
- .RXPHDLYRESET(1'b0),
- .RXPHMONITOR(NLW_gtpe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
- .RXPHOVRDEN(1'b0),
- .RXPHSLIPMONITOR(NLW_gtpe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
- .RXPMARESET(1'b0),
- .RXPMARESETDONE(gtpe2_i_n_28),
- .RXPOLARITY(rx_polarity_i),
- .RXPRBSCNTRESET(1'b0),
- .RXPRBSERR(gtpe2_i_n_29),
- .RXPRBSSEL({1'b0,1'b0,1'b0}),
- .RXRATE({1'b0,1'b0,1'b0}),
- .RXRATEDONE(NLW_gtpe2_i_RXRATEDONE_UNCONNECTED),
- .RXRATEMODE(1'b0),
- .RXRESETDONE(drpclk_in_1),
- .RXSLIDE(1'b0),
- .RXSTARTOFSEQ(NLW_gtpe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
- .RXSTATUS(NLW_gtpe2_i_RXSTATUS_UNCONNECTED[2:0]),
- .RXSYNCALLIN(1'b0),
- .RXSYNCDONE(NLW_gtpe2_i_RXSYNCDONE_UNCONNECTED),
- .RXSYNCIN(1'b0),
- .RXSYNCMODE(1'b0),
- .RXSYNCOUT(NLW_gtpe2_i_RXSYNCOUT_UNCONNECTED),
- .RXSYSCLKSEL({1'b0,1'b0}),
- .RXUSERRDY(gt_rxuserrdy_i),
- .RXUSRCLK(sync_clk),
- .RXUSRCLK2(user_clk),
- .RXVALID(NLW_gtpe2_i_RXVALID_UNCONNECTED),
- .SETERRSTATUS(1'b0),
- .SIGVALIDCLK(1'b0),
- .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0}),
- .TX8B10BEN(1'b1),
- .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
- .TXBUFSTATUS({tx_buf_err_i,gtpe2_i_n_102}),
- .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0}),
- .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0}),
- .TXCHARISK({drprdy_out[0],drprdy_out[1],drprdy_out[2],drprdy_out[3]}),
- .TXCOMFINISH(NLW_gtpe2_i_TXCOMFINISH_UNCONNECTED),
- .TXCOMINIT(1'b0),
- .TXCOMSAS(1'b0),
- .TXCOMWAKE(1'b0),
- .TXDATA(TXDATA),
- .TXDEEMPH(1'b0),
- .TXDETECTRX(1'b0),
- .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}),
- .TXDIFFPD(1'b0),
- .TXDLYBYPASS(1'b1),
- .TXDLYEN(1'b0),
- .TXDLYHOLD(1'b0),
- .TXDLYOVRDEN(1'b0),
- .TXDLYSRESET(1'b0),
- .TXDLYSRESETDONE(NLW_gtpe2_i_TXDLYSRESETDONE_UNCONNECTED),
- .TXDLYUPDOWN(1'b0),
- .TXELECIDLE(POWER_DOWN),
- .TXGEARBOXREADY(NLW_gtpe2_i_TXGEARBOXREADY_UNCONNECTED),
- .TXHEADER({1'b0,1'b0,1'b0}),
- .TXINHIBIT(1'b0),
- .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXMARGIN({1'b0,1'b0,1'b0}),
- .TXOUTCLK(TX_OUT_CLK),
- .TXOUTCLKFABRIC(gtpe2_i_n_39),
- .TXOUTCLKPCS(gtpe2_i_n_40),
- .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
- .TXPCSRESET(1'b0),
- .TXPD({POWER_DOWN,POWER_DOWN}),
- .TXPDELECIDLEMODE(1'b0),
- .TXPHALIGN(1'b0),
- .TXPHALIGNDONE(NLW_gtpe2_i_TXPHALIGNDONE_UNCONNECTED),
- .TXPHALIGNEN(1'b0),
- .TXPHDLYPD(1'b0),
- .TXPHDLYRESET(1'b0),
- .TXPHDLYTSTCLK(1'b0),
- .TXPHINIT(1'b0),
- .TXPHINITDONE(NLW_gtpe2_i_TXPHINITDONE_UNCONNECTED),
- .TXPHOVRDEN(1'b0),
- .TXPIPPMEN(1'b0),
- .TXPIPPMOVRDEN(1'b0),
- .TXPIPPMPD(1'b0),
- .TXPIPPMSEL(1'b1),
- .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXPISOPD(1'b0),
- .TXPMARESET(1'b0),
- .TXPMARESETDONE(NLW_gtpe2_i_TXPMARESETDONE_UNCONNECTED),
- .TXPOLARITY(1'b0),
- .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXPOSTCURSORINV(1'b0),
- .TXPRBSFORCEERR(1'b0),
- .TXPRBSSEL({1'b0,1'b0,1'b0}),
- .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXPRECURSORINV(1'b0),
- .TXRATE({1'b0,1'b0,1'b0}),
- .TXRATEDONE(NLW_gtpe2_i_TXRATEDONE_UNCONNECTED),
- .TXRATEMODE(1'b0),
- .TXRESETDONE(drpclk_in_2),
- .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXSTARTSEQ(1'b0),
- .TXSWING(1'b0),
- .TXSYNCALLIN(1'b0),
- .TXSYNCDONE(NLW_gtpe2_i_TXSYNCDONE_UNCONNECTED),
- .TXSYNCIN(1'b0),
- .TXSYNCMODE(1'b0),
- .TXSYNCOUT(NLW_gtpe2_i_TXSYNCOUT_UNCONNECTED),
- .TXSYSCLKSEL({1'b0,1'b0}),
- .TXUSERRDY(gt_txuserrdy_i),
- .TXUSRCLK(sync_clk),
- .TXUSRCLK2(user_clk));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_10
- (.I0(DRPDI_IN[8]),
- .I1(in7[8]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[8]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_11
- (.I0(DRPDI_IN[7]),
- .I1(in7[7]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[7]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_12
- (.I0(DRPDI_IN[6]),
- .I1(in7[6]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[6]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_13
- (.I0(DRPDI_IN[5]),
- .I1(in7[5]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[5]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_14
- (.I0(DRPDI_IN[4]),
- .I1(in7[4]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[4]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_15
- (.I0(DRPDI_IN[3]),
- .I1(in7[3]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[3]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_16
- (.I0(DRPDI_IN[2]),
- .I1(in7[2]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[2]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_17
- (.I0(DRPDI_IN[1]),
- .I1(in7[1]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[1]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_18
- (.I0(DRPDI_IN[0]),
- .I1(in7[0]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[0]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_3
- (.I0(DRPDI_IN[15]),
- .I1(in7[15]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[15]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_4
- (.I0(DRPDI_IN[14]),
- .I1(in7[14]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[14]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_5
- (.I0(DRPDI_IN[13]),
- .I1(in7[13]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[13]));
- LUT2 #(
- .INIT(4'hB))
- gtpe2_i_i_55
- (.I0(DRPADDR_IN[4]),
- .I1(drp_op_done),
- .O(DRPADDR[4]));
- (* SOFT_HLUTNM = "soft_lutpair246" *)
- LUT2 #(
- .INIT(4'hB))
- gtpe2_i_i_59
- (.I0(DRPADDR_IN[0]),
- .I1(drp_op_done),
- .O(DRPADDR[0]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_6
- (.I0(DRPDI_IN[12]),
- .I1(in7[12]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[12]));
- (* SOFT_HLUTNM = "soft_lutpair246" *)
- LUT4 #(
- .INIT(16'hAAC0))
- gtpe2_i_i_7
- (.I0(DRPDI_IN[11]),
- .I1(p_0_in),
- .I2(gtrxreset_seq_i_n_17),
- .I3(drp_op_done),
- .O(DRPDI[11]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_8
- (.I0(DRPDI_IN[10]),
- .I1(in7[10]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[10]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_9
- (.I0(DRPDI_IN[9]),
- .I1(in7[9]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[9]));
- east_channel_east_channel_gtrxreset_seq gtrxreset_seq_i
- (.DRPADDR({gtrxreset_seq_i_n_4,gtrxreset_seq_i_n_5,gtrxreset_seq_i_n_6,gtrxreset_seq_i_n_7,gtrxreset_seq_i_n_8,gtrxreset_seq_i_n_9,gtrxreset_seq_i_n_10}),
- .DRPADDR_IN({DRPADDR_IN[8:5],DRPADDR_IN[3:1]}),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN(DRPEN),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE(DRPWE),
- .DRPWE_IN(DRPWE_IN),
- .GTRXRESET(GTRXRESET),
- .Q({gtrxreset_seq_i_n_2,p_0_in}),
- .SR(SR),
- .drp_op_done(drp_op_done),
- .drpclk_in(drpclk_in),
- .gt_common_reset_out(gt_common_reset_out),
- .in0(gtpe2_i_n_28),
- .init_clk_in(init_clk_in),
- .\rd_data_reg[0]_0 (drpclk_in_0),
- .\rd_data_reg[15]_0 ({in7[15:12],gtrxreset_seq_i_n_17,in7[10:0]}));
- LUT3 #(
- .INIT(8'hFE))
- hard_err_gt_i_1
- (.I0(rx_realign_i),
- .I1(tx_buf_err_i),
- .I2(rx_buf_err_i),
- .O(hard_err_gt0));
- LUT6 #(
- .INIT(64'hFFFFFF5700028200))
- \left_align_select_r[0]_i_1
- (.I0(\left_align_select_r_reg[0]_0 ),
- .I1(RXCHARISK[1]),
- .I2(RXCHARISK[0]),
- .I3(RXCHARISK[2]),
- .I4(RXCHARISK[3]),
- .I5(\left_align_select_r_reg[0]_1 ),
- .O(\left_align_select_r_reg[0] ));
- LUT6 #(
- .INIT(64'hFFFF7DDF00020088))
- \left_align_select_r[1]_i_1
- (.I0(\left_align_select_r_reg[0]_0 ),
- .I1(RXCHARISK[1]),
- .I2(RXCHARISK[0]),
- .I3(RXCHARISK[2]),
- .I4(RXCHARISK[3]),
- .I5(\left_align_select_r_reg[1]_4 ),
- .O(\left_align_select_r_reg[1] ));
- (* SOFT_HLUTNM = "soft_lutpair245" *)
- LUT5 #(
- .INIT(32'h0F0F0F0E))
- reset_count_r_i_3
- (.I0(rx_disp_err_i[2]),
- .I1(rx_not_in_table_i[2]),
- .I2(tx_reset_i),
- .I3(rx_disp_err_i[1]),
- .I4(rx_not_in_table_i[1]),
- .O(rst_r_reg));
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[0]_i_2
- (.I0(RXDISPERR[0]),
- .I1(RXNOTINTABLE[0]),
- .O(drpclk_in_6));
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[1]_i_1
- (.I0(rx_disp_err_i[1]),
- .I1(rx_not_in_table_i[1]),
- .O(drpclk_in_4));
- (* SOFT_HLUTNM = "soft_lutpair245" *)
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[2]_i_1
- (.I0(rx_disp_err_i[2]),
- .I1(rx_not_in_table_i[2]),
- .O(drpclk_in_5));
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[3]_i_1
- (.I0(RXDISPERR[1]),
- .I1(RXNOTINTABLE[1]),
- .O(drpclk_in_7));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[2]_i_1
- (.I0(RXCHARISK[1]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXCHARISK[0]),
- .I4(\word_aligned_control_bits_r_reg[2] ),
- .I5(RXCHARISK[2]),
- .O(\left_align_select_r_reg[1]_2 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[3]_i_1
- (.I0(RXCHARISK[2]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXCHARISK[1]),
- .I4(RXCHARISK[0]),
- .I5(RXCHARISK[3]),
- .O(\left_align_select_r_reg[1]_3 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[16]_i_1
- (.I0(RXDATA[15]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[7]),
- .I4(\word_aligned_data_r_reg[16] [7]),
- .I5(RXDATA[23]),
- .O(\left_align_select_r_reg[1]_0 [7]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[17]_i_1
- (.I0(RXDATA[14]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[6]),
- .I4(\word_aligned_data_r_reg[16] [6]),
- .I5(RXDATA[22]),
- .O(\left_align_select_r_reg[1]_0 [6]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[18]_i_1
- (.I0(RXDATA[13]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[5]),
- .I4(\word_aligned_data_r_reg[16] [5]),
- .I5(RXDATA[21]),
- .O(\left_align_select_r_reg[1]_0 [5]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[19]_i_1
- (.I0(RXDATA[12]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[4]),
- .I4(\word_aligned_data_r_reg[16] [4]),
- .I5(RXDATA[20]),
- .O(\left_align_select_r_reg[1]_0 [4]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[20]_i_1
- (.I0(RXDATA[11]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[3]),
- .I4(\word_aligned_data_r_reg[16] [3]),
- .I5(RXDATA[19]),
- .O(\left_align_select_r_reg[1]_0 [3]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[21]_i_1
- (.I0(RXDATA[10]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[2]),
- .I4(\word_aligned_data_r_reg[16] [2]),
- .I5(RXDATA[18]),
- .O(\left_align_select_r_reg[1]_0 [2]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[22]_i_1
- (.I0(RXDATA[9]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[1]),
- .I4(\word_aligned_data_r_reg[16] [1]),
- .I5(RXDATA[17]),
- .O(\left_align_select_r_reg[1]_0 [1]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[23]_i_1
- (.I0(RXDATA[8]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[0]),
- .I4(\word_aligned_data_r_reg[16] [0]),
- .I5(RXDATA[16]),
- .O(\left_align_select_r_reg[1]_0 [0]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[24]_i_1
- (.I0(RXDATA[23]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[15]),
- .I4(RXDATA[7]),
- .I5(RXDATA[31]),
- .O(\left_align_select_r_reg[1]_1 [7]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[25]_i_1
- (.I0(RXDATA[22]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[14]),
- .I4(RXDATA[6]),
- .I5(RXDATA[30]),
- .O(\left_align_select_r_reg[1]_1 [6]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[26]_i_1
- (.I0(RXDATA[21]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[13]),
- .I4(RXDATA[5]),
- .I5(RXDATA[29]),
- .O(\left_align_select_r_reg[1]_1 [5]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[27]_i_1
- (.I0(RXDATA[20]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[12]),
- .I4(RXDATA[4]),
- .I5(RXDATA[28]),
- .O(\left_align_select_r_reg[1]_1 [4]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[28]_i_1
- (.I0(RXDATA[19]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[11]),
- .I4(RXDATA[3]),
- .I5(RXDATA[27]),
- .O(\left_align_select_r_reg[1]_1 [3]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[29]_i_1
- (.I0(RXDATA[18]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[10]),
- .I4(RXDATA[2]),
- .I5(RXDATA[26]),
- .O(\left_align_select_r_reg[1]_1 [2]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[30]_i_1
- (.I0(RXDATA[17]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[9]),
- .I4(RXDATA[1]),
- .I5(RXDATA[25]),
- .O(\left_align_select_r_reg[1]_1 [1]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[31]_i_1
- (.I0(RXDATA[16]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[8]),
- .I4(RXDATA[0]),
- .I5(RXDATA[24]),
- .O(\left_align_select_r_reg[1]_1 [0]));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_gtrxreset_seq" *)
-module east_channel_east_channel_gtrxreset_seq
- (GTRXRESET,
- drp_op_done,
- Q,
- DRPADDR,
- DRPWE,
- DRPEN,
- \rd_data_reg[15]_0 ,
- in0,
- drpclk_in,
- gt_common_reset_out,
- init_clk_in,
- SR,
- \rd_data_reg[0]_0 ,
- DRPADDR_IN,
- DRPWE_IN,
- DRPEN_IN,
- DRPDO_OUT);
- output GTRXRESET;
- output drp_op_done;
- output [1:0]Q;
- output [6:0]DRPADDR;
- output DRPWE;
- output DRPEN;
- output [15:0]\rd_data_reg[15]_0 ;
- input in0;
- input drpclk_in;
- input gt_common_reset_out;
- input init_clk_in;
- input [0:0]SR;
- input \rd_data_reg[0]_0 ;
- input [6:0]DRPADDR_IN;
- input DRPWE_IN;
- input DRPEN_IN;
- input [15:0]DRPDO_OUT;
-
- wire [6:0]DRPADDR;
- wire [6:0]DRPADDR_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN;
- wire DRPEN_IN;
- wire DRPWE;
- wire DRPWE_IN;
- wire \FSM_onehot_state[0]_i_1_n_0 ;
- wire \FSM_onehot_state[1]_i_1_n_0 ;
- wire \FSM_onehot_state[2]_i_1_n_0 ;
- wire \FSM_onehot_state[3]_i_1_n_0 ;
- wire \FSM_onehot_state[4]_i_1_n_0 ;
- wire \FSM_onehot_state[5]_i_1_n_0 ;
- wire \FSM_onehot_state[6]_i_1_n_0 ;
- wire \FSM_onehot_state[7]_i_1_n_0 ;
- wire \FSM_onehot_state_reg_n_0_[1] ;
- wire \FSM_onehot_state_reg_n_0_[3] ;
- wire \FSM_onehot_state_reg_n_0_[4] ;
- wire \FSM_onehot_state_reg_n_0_[7] ;
- wire GTRXRESET;
- wire [1:0]Q;
- wire [0:0]SR;
- wire drp_op_done;
- wire drp_op_done_o_i_1_n_0;
- wire drpclk_in;
- wire flag;
- wire flag_i_1_n_0;
- wire flag_reg_n_0;
- wire gt_common_reset_out;
- wire gtrxreset_f;
- wire gtrxreset_i__0;
- wire gtrxreset_s;
- wire gtrxreset_ss;
- wire in0;
- wire init_clk_in;
- wire next_rd_data;
- wire [15:0]original_rd_data;
- wire original_rd_data0;
- wire p_0_in0_in;
- wire \rd_data[0]_i_1_n_0 ;
- wire \rd_data[10]_i_1_n_0 ;
- wire \rd_data[11]_i_1_n_0 ;
- wire \rd_data[12]_i_1_n_0 ;
- wire \rd_data[13]_i_1_n_0 ;
- wire \rd_data[14]_i_1_n_0 ;
- wire \rd_data[15]_i_2_n_0 ;
- wire \rd_data[1]_i_1_n_0 ;
- wire \rd_data[2]_i_1_n_0 ;
- wire \rd_data[3]_i_1_n_0 ;
- wire \rd_data[4]_i_1_n_0 ;
- wire \rd_data[5]_i_1_n_0 ;
- wire \rd_data[6]_i_1_n_0 ;
- wire \rd_data[7]_i_1_n_0 ;
- wire \rd_data[8]_i_1_n_0 ;
- wire \rd_data[9]_i_1_n_0 ;
- wire \rd_data_reg[0]_0 ;
- wire [15:0]\rd_data_reg[15]_0 ;
- wire rst_ss;
- wire rxpmaresetdone_ss;
- wire rxpmaresetdone_sss;
-
- (* SOFT_HLUTNM = "soft_lutpair240" *)
- LUT3 #(
- .INIT(8'hBA))
- \FSM_onehot_state[0]_i_1
- (.I0(Q[0]),
- .I1(\rd_data_reg[0]_0 ),
- .I2(flag),
- .O(\FSM_onehot_state[0]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h8F88))
- \FSM_onehot_state[1]_i_1
- (.I0(\rd_data_reg[0]_0 ),
- .I1(flag),
- .I2(gtrxreset_ss),
- .I3(\FSM_onehot_state_reg_n_0_[1] ),
- .O(\FSM_onehot_state[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair230" *)
- LUT3 #(
- .INIT(8'h20))
- \FSM_onehot_state[2]_i_1
- (.I0(\FSM_onehot_state_reg_n_0_[3] ),
- .I1(rxpmaresetdone_ss),
- .I2(rxpmaresetdone_sss),
- .O(\FSM_onehot_state[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair230" *)
- LUT5 #(
- .INIT(32'hFFD0D0D0))
- \FSM_onehot_state[3]_i_1
- (.I0(rxpmaresetdone_sss),
- .I1(rxpmaresetdone_ss),
- .I2(\FSM_onehot_state_reg_n_0_[3] ),
- .I3(\rd_data_reg[0]_0 ),
- .I4(\FSM_onehot_state_reg_n_0_[4] ),
- .O(\FSM_onehot_state[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair240" *)
- LUT3 #(
- .INIT(8'hBA))
- \FSM_onehot_state[4]_i_1
- (.I0(Q[1]),
- .I1(\rd_data_reg[0]_0 ),
- .I2(\FSM_onehot_state_reg_n_0_[4] ),
- .O(\FSM_onehot_state[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair241" *)
- LUT2 #(
- .INIT(4'h8))
- \FSM_onehot_state[5]_i_1
- (.I0(p_0_in0_in),
- .I1(\rd_data_reg[0]_0 ),
- .O(\FSM_onehot_state[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair241" *)
- LUT3 #(
- .INIT(8'hBA))
- \FSM_onehot_state[6]_i_1
- (.I0(\FSM_onehot_state_reg_n_0_[7] ),
- .I1(\rd_data_reg[0]_0 ),
- .I2(p_0_in0_in),
- .O(\FSM_onehot_state[6]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \FSM_onehot_state[7]_i_1
- (.I0(\FSM_onehot_state_reg_n_0_[1] ),
- .I1(gtrxreset_ss),
- .O(\FSM_onehot_state[7]_i_1_n_0 ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[0]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[0]_i_1_n_0 ),
- .Q(flag));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDPE #(
- .INIT(1'b1))
- \FSM_onehot_state_reg[1]
- (.C(drpclk_in),
- .CE(1'b1),
- .D(\FSM_onehot_state[1]_i_1_n_0 ),
- .PRE(rst_ss),
- .Q(\FSM_onehot_state_reg_n_0_[1] ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[2]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[2]_i_1_n_0 ),
- .Q(Q[0]));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[3]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[3]_i_1_n_0 ),
- .Q(\FSM_onehot_state_reg_n_0_[3] ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[4]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[4]_i_1_n_0 ),
- .Q(\FSM_onehot_state_reg_n_0_[4] ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[5]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[5]_i_1_n_0 ),
- .Q(Q[1]));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[6]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[6]_i_1_n_0 ),
- .Q(p_0_in0_in));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[7]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[7]_i_1_n_0 ),
- .Q(\FSM_onehot_state_reg_n_0_[7] ));
- (* SOFT_HLUTNM = "soft_lutpair242" *)
- LUT3 #(
- .INIT(8'hF8))
- drp_op_done_o_i_1
- (.I0(\rd_data_reg[0]_0 ),
- .I1(flag),
- .I2(drp_op_done),
- .O(drp_op_done_o_i_1_n_0));
- FDCE drp_op_done_o_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(gtrxreset_f),
- .D(drp_op_done_o_i_1_n_0),
- .Q(drp_op_done));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFF4))
- flag_i_1
- (.I0(flag),
- .I1(flag_reg_n_0),
- .I2(Q[0]),
- .I3(\FSM_onehot_state_reg_n_0_[3] ),
- .I4(Q[1]),
- .I5(\FSM_onehot_state_reg_n_0_[4] ),
- .O(flag_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- flag_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(flag_i_1_n_0),
- .Q(flag_reg_n_0),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hBBBBBBB8))
- gtpe2_i_i_1
- (.I0(DRPEN_IN),
- .I1(drp_op_done),
- .I2(Q[1]),
- .I3(Q[0]),
- .I4(\FSM_onehot_state_reg_n_0_[7] ),
- .O(DRPEN));
- (* SOFT_HLUTNM = "soft_lutpair231" *)
- LUT4 #(
- .INIT(16'hBBB8))
- gtpe2_i_i_2
- (.I0(DRPWE_IN),
- .I1(drp_op_done),
- .I2(Q[0]),
- .I3(Q[1]),
- .O(DRPWE));
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_51
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[6]),
- .O(DRPADDR[6]));
- (* SOFT_HLUTNM = "soft_lutpair243" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_52
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[5]),
- .O(DRPADDR[5]));
- (* SOFT_HLUTNM = "soft_lutpair244" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_53
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[4]),
- .O(DRPADDR[4]));
- (* SOFT_HLUTNM = "soft_lutpair244" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_54
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[3]),
- .O(DRPADDR[3]));
- (* SOFT_HLUTNM = "soft_lutpair243" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_56
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[2]),
- .O(DRPADDR[2]));
- (* SOFT_HLUTNM = "soft_lutpair242" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_57
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[1]),
- .O(DRPADDR[1]));
- (* SOFT_HLUTNM = "soft_lutpair231" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_58
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[0]),
- .O(DRPADDR[0]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFEEE))
- gtrxreset_i
- (.I0(\FSM_onehot_state_reg_n_0_[7] ),
- .I1(\FSM_onehot_state_reg_n_0_[4] ),
- .I2(gtrxreset_ss),
- .I3(\FSM_onehot_state_reg_n_0_[3] ),
- .I4(p_0_in0_in),
- .I5(Q[1]),
- .O(gtrxreset_i__0));
- east_channel_east_channel_cdc_sync__parameterized6_19 gtrxreset_in_cdc_sync
- (.SR(SR),
- .drpclk_in(drpclk_in),
- .init_clk_in(init_clk_in),
- .out(gtrxreset_f));
- FDCE gtrxreset_o_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(gtrxreset_i__0),
- .Q(GTRXRESET));
- FDCE gtrxreset_s_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(gtrxreset_f),
- .Q(gtrxreset_s));
- FDCE gtrxreset_ss_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(gtrxreset_s),
- .Q(gtrxreset_ss));
- LUT3 #(
- .INIT(8'h40))
- \original_rd_data[15]_i_1
- (.I0(flag_reg_n_0),
- .I1(\rd_data_reg[0]_0 ),
- .I2(p_0_in0_in),
- .O(original_rd_data0));
- FDRE \original_rd_data_reg[0]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[0]),
- .Q(original_rd_data[0]),
- .R(1'b0));
- FDRE \original_rd_data_reg[10]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[10]),
- .Q(original_rd_data[10]),
- .R(1'b0));
- FDRE \original_rd_data_reg[11]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[11]),
- .Q(original_rd_data[11]),
- .R(1'b0));
- FDRE \original_rd_data_reg[12]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[12]),
- .Q(original_rd_data[12]),
- .R(1'b0));
- FDRE \original_rd_data_reg[13]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[13]),
- .Q(original_rd_data[13]),
- .R(1'b0));
- FDRE \original_rd_data_reg[14]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[14]),
- .Q(original_rd_data[14]),
- .R(1'b0));
- FDRE \original_rd_data_reg[15]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[15]),
- .Q(original_rd_data[15]),
- .R(1'b0));
- FDRE \original_rd_data_reg[1]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[1]),
- .Q(original_rd_data[1]),
- .R(1'b0));
- FDRE \original_rd_data_reg[2]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[2]),
- .Q(original_rd_data[2]),
- .R(1'b0));
- FDRE \original_rd_data_reg[3]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[3]),
- .Q(original_rd_data[3]),
- .R(1'b0));
- FDRE \original_rd_data_reg[4]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[4]),
- .Q(original_rd_data[4]),
- .R(1'b0));
- FDRE \original_rd_data_reg[5]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[5]),
- .Q(original_rd_data[5]),
- .R(1'b0));
- FDRE \original_rd_data_reg[6]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[6]),
- .Q(original_rd_data[6]),
- .R(1'b0));
- FDRE \original_rd_data_reg[7]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[7]),
- .Q(original_rd_data[7]),
- .R(1'b0));
- FDRE \original_rd_data_reg[8]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[8]),
- .Q(original_rd_data[8]),
- .R(1'b0));
- FDRE \original_rd_data_reg[9]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[9]),
- .Q(original_rd_data[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair239" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[0]_i_1
- (.I0(DRPDO_OUT[0]),
- .I1(original_rd_data[0]),
- .I2(flag_reg_n_0),
- .O(\rd_data[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair232" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[10]_i_1
- (.I0(DRPDO_OUT[10]),
- .I1(original_rd_data[10]),
- .I2(flag_reg_n_0),
- .O(\rd_data[10]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair236" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[11]_i_1
- (.I0(DRPDO_OUT[11]),
- .I1(original_rd_data[11]),
- .I2(flag_reg_n_0),
- .O(\rd_data[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair235" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[12]_i_1
- (.I0(DRPDO_OUT[12]),
- .I1(original_rd_data[12]),
- .I2(flag_reg_n_0),
- .O(\rd_data[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair234" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[13]_i_1
- (.I0(DRPDO_OUT[13]),
- .I1(original_rd_data[13]),
- .I2(flag_reg_n_0),
- .O(\rd_data[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair233" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[14]_i_1
- (.I0(DRPDO_OUT[14]),
- .I1(original_rd_data[14]),
- .I2(flag_reg_n_0),
- .O(\rd_data[14]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \rd_data[15]_i_1
- (.I0(p_0_in0_in),
- .I1(\rd_data_reg[0]_0 ),
- .O(next_rd_data));
- (* SOFT_HLUTNM = "soft_lutpair232" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[15]_i_2
- (.I0(DRPDO_OUT[15]),
- .I1(original_rd_data[15]),
- .I2(flag_reg_n_0),
- .O(\rd_data[15]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair239" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[1]_i_1
- (.I0(DRPDO_OUT[1]),
- .I1(original_rd_data[1]),
- .I2(flag_reg_n_0),
- .O(\rd_data[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair238" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[2]_i_1
- (.I0(DRPDO_OUT[2]),
- .I1(original_rd_data[2]),
- .I2(flag_reg_n_0),
- .O(\rd_data[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair238" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[3]_i_1
- (.I0(DRPDO_OUT[3]),
- .I1(original_rd_data[3]),
- .I2(flag_reg_n_0),
- .O(\rd_data[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair237" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[4]_i_1
- (.I0(DRPDO_OUT[4]),
- .I1(original_rd_data[4]),
- .I2(flag_reg_n_0),
- .O(\rd_data[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair236" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[5]_i_1
- (.I0(DRPDO_OUT[5]),
- .I1(original_rd_data[5]),
- .I2(flag_reg_n_0),
- .O(\rd_data[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair237" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[6]_i_1
- (.I0(DRPDO_OUT[6]),
- .I1(original_rd_data[6]),
- .I2(flag_reg_n_0),
- .O(\rd_data[6]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair235" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[7]_i_1
- (.I0(DRPDO_OUT[7]),
- .I1(original_rd_data[7]),
- .I2(flag_reg_n_0),
- .O(\rd_data[7]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair234" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[8]_i_1
- (.I0(DRPDO_OUT[8]),
- .I1(original_rd_data[8]),
- .I2(flag_reg_n_0),
- .O(\rd_data[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair233" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[9]_i_1
- (.I0(DRPDO_OUT[9]),
- .I1(original_rd_data[9]),
- .I2(flag_reg_n_0),
- .O(\rd_data[9]_i_1_n_0 ));
- FDCE \rd_data_reg[0]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[0]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [0]));
- FDCE \rd_data_reg[10]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[10]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [10]));
- FDCE \rd_data_reg[11]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[11]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [11]));
- FDCE \rd_data_reg[12]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[12]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [12]));
- FDCE \rd_data_reg[13]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[13]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [13]));
- FDCE \rd_data_reg[14]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[14]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [14]));
- FDCE \rd_data_reg[15]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[15]_i_2_n_0 ),
- .Q(\rd_data_reg[15]_0 [15]));
- FDCE \rd_data_reg[1]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[1]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [1]));
- FDCE \rd_data_reg[2]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[2]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [2]));
- FDCE \rd_data_reg[3]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[3]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [3]));
- FDCE \rd_data_reg[4]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[4]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [4]));
- FDCE \rd_data_reg[5]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[5]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [5]));
- FDCE \rd_data_reg[6]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[6]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [6]));
- FDCE \rd_data_reg[7]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[7]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [7]));
- FDCE \rd_data_reg[8]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[8]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [8]));
- FDCE \rd_data_reg[9]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[9]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [9]));
- east_channel_east_channel_cdc_sync__parameterized6_20 rst_cdc_sync
- (.AR(rst_ss),
- .drpclk_in(drpclk_in),
- .gt_common_reset_out(gt_common_reset_out),
- .init_clk_in(init_clk_in));
- east_channel_east_channel_cdc_sync__parameterized1_21 rxpmaresetdone_cdc_sync
- (.drpclk_in(drpclk_in),
- .in0(in0),
- .out(rxpmaresetdone_ss));
- FDCE rxpmaresetdone_sss_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(rxpmaresetdone_ss),
- .Q(rxpmaresetdone_sss));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_multi_gt" *)
-module east_channel_east_channel_multi_gt
- (drpclk_in_0,
- TXN,
- TXP,
- rx_realign_i,
- drpclk_in_1,
- TX_OUT_CLK,
- drpclk_in_2,
- DRPDO_OUT,
- RXDATA,
- drpclk_in_3,
- RXCHARISK,
- RXDISPERR,
- RXNOTINTABLE,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- rst_r_reg,
- drpclk_in_4,
- drpclk_in_5,
- drpclk_in_6,
- drpclk_in_7,
- \left_align_select_r_reg[1]_0 ,
- \left_align_select_r_reg[1]_1 ,
- \left_align_select_r_reg[1]_2 ,
- \left_align_select_r_reg[1]_3 ,
- hard_err_gt0,
- drpclk_in,
- RXN,
- RXP,
- gt_tx_reset_i,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- ena_comma_align_i,
- rx_polarity_i,
- gt_rxuserrdy_i,
- sync_clk,
- user_clk,
- POWER_DOWN,
- gt_txuserrdy_i,
- LOOPBACK,
- TXDATA,
- drprdy_out,
- gt_common_reset_out,
- init_clk_in,
- SR,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[0]_1 ,
- \left_align_select_r_reg[1]_4 ,
- tx_reset_i,
- \word_aligned_data_r_reg[16] ,
- \word_aligned_control_bits_r_reg[2] ,
- DRPADDR_IN,
- DRPDI_IN,
- DRPWE_IN,
- DRPEN_IN);
- output drpclk_in_0;
- output TXN;
- output TXP;
- output rx_realign_i;
- output drpclk_in_1;
- output TX_OUT_CLK;
- output drpclk_in_2;
- output [15:0]DRPDO_OUT;
- output [31:0]RXDATA;
- output [3:0]drpclk_in_3;
- output [3:0]RXCHARISK;
- output [1:0]RXDISPERR;
- output [1:0]RXNOTINTABLE;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output rst_r_reg;
- output drpclk_in_4;
- output drpclk_in_5;
- output drpclk_in_6;
- output drpclk_in_7;
- output [7:0]\left_align_select_r_reg[1]_0 ;
- output [7:0]\left_align_select_r_reg[1]_1 ;
- output \left_align_select_r_reg[1]_2 ;
- output \left_align_select_r_reg[1]_3 ;
- output hard_err_gt0;
- input drpclk_in;
- input RXN;
- input RXP;
- input gt_tx_reset_i;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- input ena_comma_align_i;
- input rx_polarity_i;
- input gt_rxuserrdy_i;
- input sync_clk;
- input user_clk;
- input POWER_DOWN;
- input gt_txuserrdy_i;
- input [2:0]LOOPBACK;
- input [31:0]TXDATA;
- input [3:0]drprdy_out;
- input gt_common_reset_out;
- input init_clk_in;
- input [0:0]SR;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[0]_1 ;
- input \left_align_select_r_reg[1]_4 ;
- input tx_reset_i;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input [0:0]\word_aligned_control_bits_r_reg[2] ;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- input DRPWE_IN;
- input DRPEN_IN;
-
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN_IN;
- wire DRPWE_IN;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire [2:0]LOOPBACK;
- wire POWER_DOWN;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire RXN;
- wire [1:0]RXNOTINTABLE;
- wire RXP;
- wire [0:0]SR;
- wire [31:0]TXDATA;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire drpclk_in;
- wire drpclk_in_0;
- wire drpclk_in_1;
- wire drpclk_in_2;
- wire [3:0]drpclk_in_3;
- wire drpclk_in_4;
- wire drpclk_in_5;
- wire drpclk_in_6;
- wire drpclk_in_7;
- wire [3:0]drprdy_out;
- wire ena_comma_align_i;
- wire gt_common_reset_out;
- wire gt_rxuserrdy_i;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire hard_err_gt0;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1] ;
- wire [7:0]\left_align_select_r_reg[1]_0 ;
- wire [7:0]\left_align_select_r_reg[1]_1 ;
- wire \left_align_select_r_reg[1]_2 ;
- wire \left_align_select_r_reg[1]_3 ;
- wire \left_align_select_r_reg[1]_4 ;
- wire rst_r_reg;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire sync_clk;
- wire tx_reset_i;
- wire user_clk;
- wire [0:0]\word_aligned_control_bits_r_reg[2] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
-
- east_channel_east_channel_gt gt0_east_channel_i
- (.DRPADDR_IN(DRPADDR_IN),
- .DRPDI_IN(DRPDI_IN),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE_IN(DRPWE_IN),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .LOOPBACK(LOOPBACK),
- .POWER_DOWN(POWER_DOWN),
- .RXCHARISK(RXCHARISK),
- .RXDATA(RXDATA),
- .RXDISPERR(RXDISPERR),
- .RXN(RXN),
- .RXNOTINTABLE(RXNOTINTABLE),
- .RXP(RXP),
- .SR(SR),
- .TXDATA(TXDATA),
- .TXN(TXN),
- .TXP(TXP),
- .TX_OUT_CLK(TX_OUT_CLK),
- .drpclk_in(drpclk_in),
- .drpclk_in_0(drpclk_in_0),
- .drpclk_in_1(drpclk_in_1),
- .drpclk_in_2(drpclk_in_2),
- .drpclk_in_3(drpclk_in_3),
- .drpclk_in_4(drpclk_in_4),
- .drpclk_in_5(drpclk_in_5),
- .drpclk_in_6(drpclk_in_6),
- .drpclk_in_7(drpclk_in_7),
- .drprdy_out(drprdy_out),
- .ena_comma_align_i(ena_comma_align_i),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_rxuserrdy_i(gt_rxuserrdy_i),
- .gt_tx_reset_i(gt_tx_reset_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .hard_err_gt0(hard_err_gt0),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (\left_align_select_r_reg[0] ),
- .\left_align_select_r_reg[0]_0 (\left_align_select_r_reg[0]_0 ),
- .\left_align_select_r_reg[0]_1 (\left_align_select_r_reg[0]_1 ),
- .\left_align_select_r_reg[1] (\left_align_select_r_reg[1] ),
- .\left_align_select_r_reg[1]_0 (\left_align_select_r_reg[1]_0 ),
- .\left_align_select_r_reg[1]_1 (\left_align_select_r_reg[1]_1 ),
- .\left_align_select_r_reg[1]_2 (\left_align_select_r_reg[1]_2 ),
- .\left_align_select_r_reg[1]_3 (\left_align_select_r_reg[1]_3 ),
- .\left_align_select_r_reg[1]_4 (\left_align_select_r_reg[1]_4 ),
- .rst_r_reg(rst_r_reg),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .sync_clk(sync_clk),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (\word_aligned_control_bits_r_reg[2] ),
- .\word_aligned_data_r_reg[16] (\word_aligned_data_r_reg[16] ));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_rx_startup_fsm" *)
-module east_channel_east_channel_rx_startup_fsm
- (gtrxreset_i,
- gt_rxuserrdy_i,
- quad1_common_lock_in,
- init_clk_in,
- user_clk,
- rxfsm_rxresetdone_r,
- AR,
- \FSM_sequential_rx_state_reg[0]_0 ,
- gt_txuserrdy_i);
- output gtrxreset_i;
- output gt_rxuserrdy_i;
- input quad1_common_lock_in;
- input init_clk_in;
- input user_clk;
- input rxfsm_rxresetdone_r;
- input [0:0]AR;
- input \FSM_sequential_rx_state_reg[0]_0 ;
- input gt_txuserrdy_i;
-
- wire [0:0]AR;
- wire \FSM_sequential_rx_state[0]_i_2_n_0 ;
- wire \FSM_sequential_rx_state[1]_i_2_n_0 ;
- wire \FSM_sequential_rx_state[2]_i_1_n_0 ;
- wire \FSM_sequential_rx_state[2]_i_2_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_10_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_11_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_3_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_4_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_6_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_7_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_8_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_9_n_0 ;
- wire \FSM_sequential_rx_state_reg[0]_0 ;
- wire RXUSERRDY_i_1_n_0;
- wire check_tlock_max;
- wire check_tlock_max_i_1_n_0;
- wire check_tlock_max_reg_n_0;
- wire gt_rxuserrdy_i;
- wire gt_txuserrdy_i;
- wire gtrxreset_i;
- wire gtrxreset_i_i_1_n_0;
- wire init_clk_in;
- wire init_wait_count;
- wire \init_wait_count[6]_i_3__0_n_0 ;
- wire \init_wait_count[6]_i_4__0_n_0 ;
- wire [6:0]init_wait_count_reg;
- wire init_wait_done_i_1__0_n_0;
- wire init_wait_done_reg_n_0;
- wire \mmcm_lock_count[9]_i_2__0_n_0 ;
- wire \mmcm_lock_count[9]_i_4__0_n_0 ;
- wire [9:0]mmcm_lock_count_reg;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_i_2__0_n_0;
- wire [6:0]p_0_in__1;
- wire [9:0]p_0_in__3;
- wire quad1_common_lock_in;
- wire reset_time_out_i_2__0_n_0;
- wire reset_time_out_i_4__0_n_0;
- wire reset_time_out_i_6_n_0;
- wire reset_time_out_reg_n_0;
- wire run_phase_alignment_int_i_1__0_n_0;
- wire run_phase_alignment_int_reg_n_0;
- wire run_phase_alignment_int_s2;
- wire run_phase_alignment_int_s3_reg_n_0;
- wire rx_fsm_reset_done_int;
- wire rx_fsm_reset_done_int_0;
- wire rx_fsm_reset_done_int_i_1_n_0;
- wire rx_fsm_reset_done_int_i_3_n_0;
- wire rx_fsm_reset_done_int_s3;
- wire [3:0]rx_state;
- wire [3:0]rx_state__0;
- wire rxfsm_rxresetdone_r;
- wire rxpmaresetdone_i;
- wire rxpmaresetdone_rx_s;
- wire rxresetdone_s2;
- wire rxresetdone_s3;
- wire scndry_out;
- wire sync_PLL0LOCK_cdc_sync_n_0;
- wire sync_PLL0LOCK_cdc_sync_n_1;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_0;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_1;
- wire sync_rx_fsm_reset_done_int_cdc_sync_n_0;
- wire time_out_100us_i_1_n_0;
- wire time_out_100us_i_2_n_0;
- wire time_out_100us_i_3_n_0;
- wire time_out_100us_i_4_n_0;
- wire time_out_100us_i_5_n_0;
- wire time_out_100us_reg_n_0;
- wire time_out_1us_i_1_n_0;
- wire time_out_1us_i_2_n_0;
- wire time_out_1us_reg_n_0;
- wire time_out_2ms_i_1_n_0;
- wire time_out_2ms_i_2_n_0;
- wire time_out_2ms_i_3_n_0;
- wire time_out_2ms_reg_n_0;
- wire time_out_counter;
- wire \time_out_counter[0]_i_3_n_0 ;
- wire \time_out_counter[0]_i_4__0_n_0 ;
- wire \time_out_counter[0]_i_5__0_n_0 ;
- wire \time_out_counter[0]_i_6__0_n_0 ;
- wire \time_out_counter[0]_i_7_n_0 ;
- wire \time_out_counter[0]_i_8_n_0 ;
- wire [19:0]time_out_counter_reg;
- wire \time_out_counter_reg[0]_i_2__0_n_0 ;
- wire \time_out_counter_reg[0]_i_2__0_n_1 ;
- wire \time_out_counter_reg[0]_i_2__0_n_2 ;
- wire \time_out_counter_reg[0]_i_2__0_n_3 ;
- wire \time_out_counter_reg[0]_i_2__0_n_4 ;
- wire \time_out_counter_reg[0]_i_2__0_n_5 ;
- wire \time_out_counter_reg[0]_i_2__0_n_6 ;
- wire \time_out_counter_reg[0]_i_2__0_n_7 ;
- wire \time_out_counter_reg[12]_i_1__0_n_0 ;
- wire \time_out_counter_reg[12]_i_1__0_n_1 ;
- wire \time_out_counter_reg[12]_i_1__0_n_2 ;
- wire \time_out_counter_reg[12]_i_1__0_n_3 ;
- wire \time_out_counter_reg[12]_i_1__0_n_4 ;
- wire \time_out_counter_reg[12]_i_1__0_n_5 ;
- wire \time_out_counter_reg[12]_i_1__0_n_6 ;
- wire \time_out_counter_reg[12]_i_1__0_n_7 ;
- wire \time_out_counter_reg[16]_i_1__0_n_1 ;
- wire \time_out_counter_reg[16]_i_1__0_n_2 ;
- wire \time_out_counter_reg[16]_i_1__0_n_3 ;
- wire \time_out_counter_reg[16]_i_1__0_n_4 ;
- wire \time_out_counter_reg[16]_i_1__0_n_5 ;
- wire \time_out_counter_reg[16]_i_1__0_n_6 ;
- wire \time_out_counter_reg[16]_i_1__0_n_7 ;
- wire \time_out_counter_reg[4]_i_1__0_n_0 ;
- wire \time_out_counter_reg[4]_i_1__0_n_1 ;
- wire \time_out_counter_reg[4]_i_1__0_n_2 ;
- wire \time_out_counter_reg[4]_i_1__0_n_3 ;
- wire \time_out_counter_reg[4]_i_1__0_n_4 ;
- wire \time_out_counter_reg[4]_i_1__0_n_5 ;
- wire \time_out_counter_reg[4]_i_1__0_n_6 ;
- wire \time_out_counter_reg[4]_i_1__0_n_7 ;
- wire \time_out_counter_reg[8]_i_1__0_n_0 ;
- wire \time_out_counter_reg[8]_i_1__0_n_1 ;
- wire \time_out_counter_reg[8]_i_1__0_n_2 ;
- wire \time_out_counter_reg[8]_i_1__0_n_3 ;
- wire \time_out_counter_reg[8]_i_1__0_n_4 ;
- wire \time_out_counter_reg[8]_i_1__0_n_5 ;
- wire \time_out_counter_reg[8]_i_1__0_n_6 ;
- wire \time_out_counter_reg[8]_i_1__0_n_7 ;
- wire time_out_wait_bypass_i_1__0_n_0;
- wire time_out_wait_bypass_reg_n_0;
- wire time_out_wait_bypass_s2;
- wire time_out_wait_bypass_s3;
- wire time_tlock_max;
- wire time_tlock_max1;
- wire time_tlock_max1_carry__0_i_1_n_0;
- wire time_tlock_max1_carry__0_i_2_n_0;
- wire time_tlock_max1_carry__0_i_3_n_0;
- wire time_tlock_max1_carry__0_i_4_n_0;
- wire time_tlock_max1_carry__0_i_5_n_0;
- wire time_tlock_max1_carry__0_i_6_n_0;
- wire time_tlock_max1_carry__0_i_7_n_0;
- wire time_tlock_max1_carry__0_n_0;
- wire time_tlock_max1_carry__0_n_1;
- wire time_tlock_max1_carry__0_n_2;
- wire time_tlock_max1_carry__0_n_3;
- wire time_tlock_max1_carry__1_i_1_n_0;
- wire time_tlock_max1_carry__1_i_2_n_0;
- wire time_tlock_max1_carry__1_i_3_n_0;
- wire time_tlock_max1_carry__1_i_4_n_0;
- wire time_tlock_max1_carry__1_n_3;
- wire time_tlock_max1_carry_i_1_n_0;
- wire time_tlock_max1_carry_i_2_n_0;
- wire time_tlock_max1_carry_i_3_n_0;
- wire time_tlock_max1_carry_i_4_n_0;
- wire time_tlock_max1_carry_i_5_n_0;
- wire time_tlock_max1_carry_n_0;
- wire time_tlock_max1_carry_n_1;
- wire time_tlock_max1_carry_n_2;
- wire time_tlock_max1_carry_n_3;
- wire time_tlock_max_i_1_n_0;
- wire txpmaresetdone_i;
- wire user_clk;
- wire \wait_bypass_count[0]_i_1__0_n_0 ;
- wire \wait_bypass_count[0]_i_2__0_n_0 ;
- wire \wait_bypass_count[0]_i_4__0_n_0 ;
- wire \wait_bypass_count[0]_i_5__0_n_0 ;
- wire \wait_bypass_count[0]_i_6__0_n_0 ;
- wire \wait_bypass_count[0]_i_7__0_n_0 ;
- wire [12:0]wait_bypass_count_reg;
- wire \wait_bypass_count_reg[0]_i_3__0_n_0 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_1 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_2 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_3 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_4 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_5 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_6 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_7 ;
- wire \wait_bypass_count_reg[12]_i_1__0_n_7 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_0 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_1 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_2 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_3 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_4 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_5 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_6 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_7 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_0 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_1 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_2 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_3 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_4 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_5 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_6 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_7 ;
- wire [6:0]wait_time_cnt0__0;
- wire \wait_time_cnt[1]_i_1__0_n_0 ;
- wire \wait_time_cnt[6]_i_1_n_0 ;
- wire \wait_time_cnt[6]_i_2__0_n_0 ;
- wire \wait_time_cnt[6]_i_4__0_n_0 ;
- wire [6:0]wait_time_cnt_reg;
- wire [3:3]\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED ;
- wire [3:0]NLW_time_tlock_max1_carry_O_UNCONNECTED;
- wire [3:0]NLW_time_tlock_max1_carry__0_O_UNCONNECTED;
- wire [3:2]NLW_time_tlock_max1_carry__1_CO_UNCONNECTED;
- wire [3:0]NLW_time_tlock_max1_carry__1_O_UNCONNECTED;
- wire [3:0]\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED ;
- wire [3:1]\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED ;
-
- LUT3 #(
- .INIT(8'h74))
- \FSM_sequential_rx_state[0]_i_1
- (.I0(\FSM_sequential_rx_state[1]_i_2_n_0 ),
- .I1(rx_state[3]),
- .I2(\FSM_sequential_rx_state[0]_i_2_n_0 ),
- .O(rx_state__0[0]));
- LUT6 #(
- .INIT(64'h3F200020FFFFFFFF))
- \FSM_sequential_rx_state[0]_i_2
- (.I0(time_tlock_max),
- .I1(reset_time_out_reg_n_0),
- .I2(\FSM_sequential_rx_state[3]_i_11_n_0 ),
- .I3(rx_state[1]),
- .I4(time_out_2ms_reg_n_0),
- .I5(rx_state[0]),
- .O(\FSM_sequential_rx_state[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h8888BBBBBB8B8888))
- \FSM_sequential_rx_state[1]_i_1
- (.I0(\FSM_sequential_rx_state[1]_i_2_n_0 ),
- .I1(rx_state[3]),
- .I2(rx_state[2]),
- .I3(\FSM_sequential_rx_state[2]_i_2_n_0 ),
- .I4(rx_state[0]),
- .I5(rx_state[1]),
- .O(rx_state__0[1]));
- LUT5 #(
- .INIT(32'h0000FB00))
- \FSM_sequential_rx_state[1]_i_2
- (.I0(reset_time_out_reg_n_0),
- .I1(time_out_100us_reg_n_0),
- .I2(gt_rxuserrdy_i),
- .I3(rx_state[0]),
- .I4(\FSM_sequential_rx_state[3]_i_11_n_0 ),
- .O(\FSM_sequential_rx_state[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h050F020005050200))
- \FSM_sequential_rx_state[2]_i_1
- (.I0(rx_state[0]),
- .I1(time_out_2ms_reg_n_0),
- .I2(rx_state[3]),
- .I3(rx_state[1]),
- .I4(rx_state[2]),
- .I5(\FSM_sequential_rx_state[2]_i_2_n_0 ),
- .O(\FSM_sequential_rx_state[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair258" *)
- LUT2 #(
- .INIT(4'hB))
- \FSM_sequential_rx_state[2]_i_2
- (.I0(reset_time_out_reg_n_0),
- .I1(time_tlock_max),
- .O(\FSM_sequential_rx_state[2]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair248" *)
- LUT5 #(
- .INIT(32'hF0F0F0F1))
- \FSM_sequential_rx_state[3]_i_10
- (.I0(rx_state[2]),
- .I1(rx_state[1]),
- .I2(rx_state[3]),
- .I3(init_wait_done_reg_n_0),
- .I4(rx_state[0]),
- .O(\FSM_sequential_rx_state[3]_i_10_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair248" *)
- LUT3 #(
- .INIT(8'hCA))
- \FSM_sequential_rx_state[3]_i_11
- (.I0(rx_state[2]),
- .I1(rx_state[1]),
- .I2(rx_state[3]),
- .O(\FSM_sequential_rx_state[3]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'h33330000DDFD0000))
- \FSM_sequential_rx_state[3]_i_3
- (.I0(rx_state[0]),
- .I1(gt_rxuserrdy_i),
- .I2(time_out_100us_reg_n_0),
- .I3(reset_time_out_reg_n_0),
- .I4(rx_state[3]),
- .I5(rx_state[1]),
- .O(\FSM_sequential_rx_state[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00011101))
- \FSM_sequential_rx_state[3]_i_4
- (.I0(\FSM_sequential_rx_state[3]_i_9_n_0 ),
- .I1(rx_state[1]),
- .I2(\FSM_sequential_rx_state_reg[0]_0 ),
- .I3(rx_state[0]),
- .I4(mmcm_lock_reclocked),
- .I5(\FSM_sequential_rx_state[3]_i_10_n_0 ),
- .O(\FSM_sequential_rx_state[3]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hF1FFF1FFFFFFF1FF))
- \FSM_sequential_rx_state[3]_i_6
- (.I0(rx_state[3]),
- .I1(rx_state[2]),
- .I2(rxresetdone_s3),
- .I3(rx_state[1]),
- .I4(time_out_2ms_reg_n_0),
- .I5(reset_time_out_reg_n_0),
- .O(\FSM_sequential_rx_state[3]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hE000E0000000E000))
- \FSM_sequential_rx_state[3]_i_7
- (.I0(rx_state[3]),
- .I1(rx_state[2]),
- .I2(rx_state[1]),
- .I3(rx_state[0]),
- .I4(time_out_2ms_reg_n_0),
- .I5(reset_time_out_reg_n_0),
- .O(\FSM_sequential_rx_state[3]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFBFB00FF))
- \FSM_sequential_rx_state[3]_i_8
- (.I0(reset_time_out_reg_n_0),
- .I1(time_out_100us_reg_n_0),
- .I2(gt_rxuserrdy_i),
- .I3(time_out_wait_bypass_s3),
- .I4(rx_state[0]),
- .I5(\FSM_sequential_rx_state[3]_i_11_n_0 ),
- .O(\FSM_sequential_rx_state[3]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'h2727FF2727272727))
- \FSM_sequential_rx_state[3]_i_9
- (.I0(rx_state[3]),
- .I1(rx_state[1]),
- .I2(rx_state[2]),
- .I3(rx_state[0]),
- .I4(reset_time_out_reg_n_0),
- .I5(time_tlock_max),
- .O(\FSM_sequential_rx_state[3]_i_9_n_0 ));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[0]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(rx_state__0[0]),
- .Q(rx_state[0]),
- .R(AR));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[1]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(rx_state__0[1]),
- .Q(rx_state[1]),
- .R(AR));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[2]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(\FSM_sequential_rx_state[2]_i_1_n_0 ),
- .Q(rx_state[2]),
- .R(AR));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[3]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(rx_state__0[3]),
- .Q(rx_state[3]),
- .R(AR));
- MUXF7 \FSM_sequential_rx_state_reg[3]_i_2
- (.I0(\FSM_sequential_rx_state[3]_i_7_n_0 ),
- .I1(\FSM_sequential_rx_state[3]_i_8_n_0 ),
- .O(rx_state__0[3]),
- .S(rx_state[3]));
- LUT6 #(
- .INIT(64'hFFFBFFFB40000000))
- RXUSERRDY_i_1
- (.I0(rx_state[3]),
- .I1(rx_state[0]),
- .I2(rx_state[1]),
- .I3(rx_state[2]),
- .I4(gt_txuserrdy_i),
- .I5(gt_rxuserrdy_i),
- .O(RXUSERRDY_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- RXUSERRDY_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(RXUSERRDY_i_1_n_0),
- .Q(gt_rxuserrdy_i),
- .R(AR));
- LUT5 #(
- .INIT(32'hFFEF0020))
- check_tlock_max_i_1
- (.I0(rx_state[2]),
- .I1(rx_state[1]),
- .I2(rx_state[0]),
- .I3(rx_state[3]),
- .I4(check_tlock_max_reg_n_0),
- .O(check_tlock_max_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- check_tlock_max_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(check_tlock_max_i_1_n_0),
- .Q(check_tlock_max_reg_n_0),
- .R(AR));
- east_channel_east_channel_cdc_sync__parameterized3_7 gtrxreset_cdc_sync
- (.gtrxreset_i(gtrxreset_i),
- .init_clk_in(init_clk_in),
- .out(scndry_out),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'hFFFB0002))
- gtrxreset_i_i_1
- (.I0(rx_state[0]),
- .I1(rx_state[2]),
- .I2(rx_state[1]),
- .I3(rx_state[3]),
- .I4(gtrxreset_i),
- .O(gtrxreset_i_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- gtrxreset_i_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_i_i_1_n_0),
- .Q(gtrxreset_i),
- .R(AR));
- LUT1 #(
- .INIT(2'h1))
- \init_wait_count[0]_i_1__0
- (.I0(init_wait_count_reg[0]),
- .O(p_0_in__1[0]));
- (* SOFT_HLUTNM = "soft_lutpair256" *)
- LUT2 #(
- .INIT(4'h6))
- \init_wait_count[1]_i_1__0
- (.I0(init_wait_count_reg[0]),
- .I1(init_wait_count_reg[1]),
- .O(p_0_in__1[1]));
- (* SOFT_HLUTNM = "soft_lutpair253" *)
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[2]_i_1__0
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .O(p_0_in__1[2]));
- (* SOFT_HLUTNM = "soft_lutpair256" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \init_wait_count[3]_i_1__0
- (.I0(init_wait_count_reg[3]),
- .I1(init_wait_count_reg[1]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[2]),
- .O(p_0_in__1[3]));
- (* SOFT_HLUTNM = "soft_lutpair251" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \init_wait_count[4]_i_1__0
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[3]),
- .I4(init_wait_count_reg[4]),
- .O(p_0_in__1[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \init_wait_count[5]_i_1__0
- (.I0(init_wait_count_reg[5]),
- .I1(init_wait_count_reg[2]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[1]),
- .I4(init_wait_count_reg[3]),
- .I5(init_wait_count_reg[4]),
- .O(p_0_in__1[5]));
- LUT4 #(
- .INIT(16'hFFBF))
- \init_wait_count[6]_i_1__0
- (.I0(\init_wait_count[6]_i_3__0_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .O(init_wait_count));
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[6]_i_2__0
- (.I0(init_wait_count_reg[6]),
- .I1(\init_wait_count[6]_i_4__0_n_0 ),
- .I2(init_wait_count_reg[5]),
- .O(p_0_in__1[6]));
- (* SOFT_HLUTNM = "soft_lutpair253" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \init_wait_count[6]_i_3__0
- (.I0(init_wait_count_reg[1]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[4]),
- .I3(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_3__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair251" *)
- LUT5 #(
- .INIT(32'h80000000))
- \init_wait_count[6]_i_4__0
- (.I0(init_wait_count_reg[4]),
- .I1(init_wait_count_reg[3]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[0]),
- .I4(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_4__0_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[0]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[0]),
- .Q(init_wait_count_reg[0]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[1]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[1]),
- .Q(init_wait_count_reg[1]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[2]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[2]),
- .Q(init_wait_count_reg[2]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[3]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[3]),
- .Q(init_wait_count_reg[3]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[4]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[4]),
- .Q(init_wait_count_reg[4]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[5]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[5]),
- .Q(init_wait_count_reg[5]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[6]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[6]),
- .Q(init_wait_count_reg[6]));
- LUT5 #(
- .INIT(32'hFFFF0040))
- init_wait_done_i_1__0
- (.I0(\init_wait_count[6]_i_3__0_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .I4(init_wait_done_reg_n_0),
- .O(init_wait_done_i_1__0_n_0));
- FDCE #(
- .INIT(1'b0))
- init_wait_done_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(AR),
- .D(init_wait_done_i_1__0_n_0),
- .Q(init_wait_done_reg_n_0));
- (* SOFT_HLUTNM = "soft_lutpair259" *)
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[0]_i_1__0
- (.I0(mmcm_lock_count_reg[0]),
- .O(p_0_in__3[0]));
- (* SOFT_HLUTNM = "soft_lutpair259" *)
- LUT2 #(
- .INIT(4'h6))
- \mmcm_lock_count[1]_i_1__0
- (.I0(mmcm_lock_count_reg[0]),
- .I1(mmcm_lock_count_reg[1]),
- .O(p_0_in__3[1]));
- (* SOFT_HLUTNM = "soft_lutpair255" *)
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[2]_i_1__0
- (.I0(mmcm_lock_count_reg[2]),
- .I1(mmcm_lock_count_reg[0]),
- .I2(mmcm_lock_count_reg[1]),
- .O(p_0_in__3[2]));
- (* SOFT_HLUTNM = "soft_lutpair255" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[3]_i_1__0
- (.I0(mmcm_lock_count_reg[3]),
- .I1(mmcm_lock_count_reg[1]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[2]),
- .O(p_0_in__3[3]));
- (* SOFT_HLUTNM = "soft_lutpair247" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[4]_i_1__0
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .O(p_0_in__3[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[5]_i_1__0
- (.I0(mmcm_lock_count_reg[5]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .I5(mmcm_lock_count_reg[4]),
- .O(p_0_in__3[5]));
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[6]_i_1__0
- (.I0(mmcm_lock_count_reg[6]),
- .I1(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I2(mmcm_lock_count_reg[5]),
- .O(p_0_in__3[6]));
- (* SOFT_HLUTNM = "soft_lutpair249" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[7]_i_1__0
- (.I0(mmcm_lock_count_reg[7]),
- .I1(mmcm_lock_count_reg[5]),
- .I2(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I3(mmcm_lock_count_reg[6]),
- .O(p_0_in__3[7]));
- (* SOFT_HLUTNM = "soft_lutpair249" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[8]_i_1__0
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .O(p_0_in__3[8]));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- \mmcm_lock_count[9]_i_2__0
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .I5(mmcm_lock_count_reg[9]),
- .O(\mmcm_lock_count[9]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[9]_i_3__0
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(p_0_in__3[9]));
- (* SOFT_HLUTNM = "soft_lutpair247" *)
- LUT5 #(
- .INIT(32'h80000000))
- \mmcm_lock_count[9]_i_4__0
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[3]),
- .I2(mmcm_lock_count_reg[1]),
- .I3(mmcm_lock_count_reg[0]),
- .I4(mmcm_lock_count_reg[2]),
- .O(\mmcm_lock_count[9]_i_4__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[0]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[0]),
- .Q(mmcm_lock_count_reg[0]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[1]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[1]),
- .Q(mmcm_lock_count_reg[1]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[2]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[2]),
- .Q(mmcm_lock_count_reg[2]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[3]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[3]),
- .Q(mmcm_lock_count_reg[3]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[4]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[4]),
- .Q(mmcm_lock_count_reg[4]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[5]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[5]),
- .Q(mmcm_lock_count_reg[5]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[6]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[6]),
- .Q(mmcm_lock_count_reg[6]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[7]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[7]),
- .Q(mmcm_lock_count_reg[7]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[8]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[8]),
- .Q(mmcm_lock_count_reg[8]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[9]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[9]),
- .Q(mmcm_lock_count_reg[9]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- mmcm_lock_reclocked_i_2__0
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(mmcm_lock_reclocked_i_2__0_n_0));
- FDRE #(
- .INIT(1'b0))
- mmcm_lock_reclocked_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .Q(mmcm_lock_reclocked),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair254" *)
- LUT4 #(
- .INIT(16'h0151))
- reset_time_out_i_2__0
- (.I0(rx_state[1]),
- .I1(\FSM_sequential_rx_state_reg[0]_0 ),
- .I2(rx_state[0]),
- .I3(mmcm_lock_reclocked),
- .O(reset_time_out_i_2__0_n_0));
- (* SOFT_HLUTNM = "soft_lutpair250" *)
- LUT2 #(
- .INIT(4'h2))
- reset_time_out_i_3__0
- (.I0(rx_state[2]),
- .I1(rx_state[3]),
- .O(check_tlock_max));
- (* SOFT_HLUTNM = "soft_lutpair254" *)
- LUT2 #(
- .INIT(4'hB))
- reset_time_out_i_4__0
- (.I0(rxresetdone_s3),
- .I1(rx_state[1]),
- .O(reset_time_out_i_4__0_n_0));
- LUT5 #(
- .INIT(32'h07DC07CC))
- reset_time_out_i_6
- (.I0(rx_state[1]),
- .I1(rx_state[0]),
- .I2(rx_state[2]),
- .I3(rx_state[3]),
- .I4(\FSM_sequential_rx_state_reg[0]_0 ),
- .O(reset_time_out_i_6_n_0));
- FDSE #(
- .INIT(1'b0))
- reset_time_out_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_PLL0LOCK_cdc_sync_n_1),
- .Q(reset_time_out_reg_n_0),
- .S(AR));
- LUT5 #(
- .INIT(32'hFFFD0004))
- run_phase_alignment_int_i_1__0
- (.I0(rx_state[0]),
- .I1(rx_state[3]),
- .I2(rx_state[1]),
- .I3(rx_state[2]),
- .I4(run_phase_alignment_int_reg_n_0),
- .O(run_phase_alignment_int_i_1__0_n_0));
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(run_phase_alignment_int_i_1__0_n_0),
- .Q(run_phase_alignment_int_reg_n_0),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(run_phase_alignment_int_s2),
- .Q(run_phase_alignment_int_s3_reg_n_0),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair250" *)
- LUT5 #(
- .INIT(32'hFFBF0080))
- rx_fsm_reset_done_int_i_1
- (.I0(rx_fsm_reset_done_int_0),
- .I1(rx_fsm_reset_done_int_i_3_n_0),
- .I2(rx_state[3]),
- .I3(rx_state[2]),
- .I4(rx_fsm_reset_done_int),
- .O(rx_fsm_reset_done_int_i_1_n_0));
- LUT5 #(
- .INIT(32'h00100000))
- rx_fsm_reset_done_int_i_2
- (.I0(rx_state[0]),
- .I1(rx_state[2]),
- .I2(time_out_1us_reg_n_0),
- .I3(reset_time_out_reg_n_0),
- .I4(gt_rxuserrdy_i),
- .O(rx_fsm_reset_done_int_0));
- LUT6 #(
- .INIT(64'h00003B3BCFCC0000))
- rx_fsm_reset_done_int_i_3
- (.I0(time_out_1us_reg_n_0),
- .I1(gt_rxuserrdy_i),
- .I2(reset_time_out_reg_n_0),
- .I3(time_out_100us_reg_n_0),
- .I4(rx_state[0]),
- .I5(rx_state[1]),
- .O(rx_fsm_reset_done_int_i_3_n_0));
- FDRE #(
- .INIT(1'b0))
- rx_fsm_reset_done_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rx_fsm_reset_done_int_i_1_n_0),
- .Q(rx_fsm_reset_done_int),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- rx_fsm_reset_done_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
- .Q(rx_fsm_reset_done_int_s3),
- .R(1'b0));
- FDCE #(
- .INIT(1'b0))
- rxpmaresetdone_i_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(scndry_out),
- .D(rxpmaresetdone_rx_s),
- .Q(rxpmaresetdone_i));
- FDRE #(
- .INIT(1'b0))
- rxresetdone_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rxresetdone_s2),
- .Q(rxresetdone_s3),
- .R(1'b0));
- east_channel_east_channel_cdc_sync__parameterized1_8 sync_PLL0LOCK_cdc_sync
- (.E(sync_PLL0LOCK_cdc_sync_n_0),
- .\FSM_sequential_rx_state_reg[0] (\FSM_sequential_rx_state[3]_i_3_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_0 (\FSM_sequential_rx_state[3]_i_4_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_1 (\wait_time_cnt[6]_i_2__0_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_2 (\FSM_sequential_rx_state[3]_i_6_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_3 (time_out_2ms_reg_n_0),
- .Q(rx_state),
- .check_tlock_max(check_tlock_max),
- .init_clk_in(init_clk_in),
- .quad1_common_lock_in(quad1_common_lock_in),
- .reset_time_out_reg(sync_PLL0LOCK_cdc_sync_n_1),
- .reset_time_out_reg_0(gt_rxuserrdy_i),
- .reset_time_out_reg_1(reset_time_out_i_2__0_n_0),
- .reset_time_out_reg_2(reset_time_out_i_4__0_n_0),
- .reset_time_out_reg_3(reset_time_out_i_6_n_0),
- .reset_time_out_reg_4(reset_time_out_reg_n_0));
- east_channel_east_channel_cdc_sync__parameterized1_9 sync_PLL1LOCK_cdc_sync
- (.init_clk_in(init_clk_in));
- east_channel_east_channel_cdc_sync__parameterized6_10 sync_RXRESETDONE_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(rxresetdone_s2),
- .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized1_11 sync_mmcm_lock_reclocked_cdc_sync
- (.SR(sync_mmcm_lock_reclocked_cdc_sync_n_0),
- .init_clk_in(init_clk_in),
- .mmcm_lock_reclocked(mmcm_lock_reclocked),
- .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .mmcm_lock_reclocked_reg_0(mmcm_lock_reclocked_i_2__0_n_0));
- east_channel_east_channel_cdc_sync__parameterized3_12 sync_pmaresetdone_fallingedge_detect_cdc_sync
- (.init_clk_in(init_clk_in),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized3_13 sync_run_phase_alignment_int_cdc_sync
- (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 (run_phase_alignment_int_reg_n_0),
- .init_clk_in(init_clk_in),
- .out(run_phase_alignment_int_s2),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized3_14 sync_rx_fsm_reset_done_int_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
- .rx_fsm_reset_done_int(rx_fsm_reset_done_int),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized6_15 sync_rxpmaresetdone_cdc_sync
- (.init_clk_in(init_clk_in),
- .rxpmaresetdone_i(rxpmaresetdone_i),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync_16 sync_rxpmaresetdone_rx_s_cdc_sync
- (.out(rxpmaresetdone_rx_s),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized6_17 sync_time_out_wait_bypass_cdc_sync
- (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 (time_out_wait_bypass_reg_n_0),
- .init_clk_in(init_clk_in),
- .out(time_out_wait_bypass_s2),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized6_18 sync_txpmaresetdone_cdc_sync
- (.init_clk_in(init_clk_in),
- .txpmaresetdone_i(txpmaresetdone_i),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'hFFFF0010))
- time_out_100us_i_1
- (.I0(time_out_100us_i_2_n_0),
- .I1(time_out_100us_i_3_n_0),
- .I2(time_out_100us_i_4_n_0),
- .I3(time_out_100us_i_5_n_0),
- .I4(time_out_100us_reg_n_0),
- .O(time_out_100us_i_1_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- time_out_100us_i_2
- (.I0(time_out_counter_reg[18]),
- .I1(time_out_counter_reg[19]),
- .I2(time_out_counter_reg[15]),
- .I3(time_out_counter_reg[17]),
- .I4(time_out_counter_reg[16]),
- .O(time_out_100us_i_2_n_0));
- LUT6 #(
- .INIT(64'hFFFBFFFFFFFFFFFF))
- time_out_100us_i_3
- (.I0(time_out_counter_reg[3]),
- .I1(time_out_counter_reg[2]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[14]),
- .I4(time_out_counter_reg[7]),
- .I5(time_out_counter_reg[6]),
- .O(time_out_100us_i_3_n_0));
- LUT4 #(
- .INIT(16'h0010))
- time_out_100us_i_4
- (.I0(time_out_counter_reg[11]),
- .I1(time_out_counter_reg[10]),
- .I2(time_out_counter_reg[2]),
- .I3(time_out_counter_reg[9]),
- .O(time_out_100us_i_4_n_0));
- LUT6 #(
- .INIT(64'hFFFFEFFFFFFFFFFF))
- time_out_100us_i_5
- (.I0(time_out_counter_reg[1]),
- .I1(time_out_counter_reg[0]),
- .I2(time_out_counter_reg[13]),
- .I3(time_out_counter_reg[12]),
- .I4(time_out_counter_reg[5]),
- .I5(time_out_counter_reg[4]),
- .O(time_out_100us_i_5_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_100us_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_100us_i_1_n_0),
- .Q(time_out_100us_reg_n_0),
- .R(reset_time_out_reg_n_0));
- LUT5 #(
- .INIT(32'hFFFF0010))
- time_out_1us_i_1
- (.I0(\time_out_counter[0]_i_6__0_n_0 ),
- .I1(time_out_100us_i_2_n_0),
- .I2(time_out_100us_i_4_n_0),
- .I3(time_out_1us_i_2_n_0),
- .I4(time_out_1us_reg_n_0),
- .O(time_out_1us_i_1_n_0));
- LUT6 #(
- .INIT(64'hFDFFFFFFFFFFFFFF))
- time_out_1us_i_2
- (.I0(time_out_counter_reg[0]),
- .I1(time_out_counter_reg[1]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[4]),
- .I4(time_out_counter_reg[3]),
- .I5(time_out_counter_reg[5]),
- .O(time_out_1us_i_2_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_1us_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_1us_i_1_n_0),
- .Q(time_out_1us_reg_n_0),
- .R(reset_time_out_reg_n_0));
- LUT4 #(
- .INIT(16'hFF01))
- time_out_2ms_i_1
- (.I0(time_out_2ms_i_2_n_0),
- .I1(\time_out_counter[0]_i_5__0_n_0 ),
- .I2(\time_out_counter[0]_i_6__0_n_0 ),
- .I3(time_out_2ms_reg_n_0),
- .O(time_out_2ms_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFF2FF))
- time_out_2ms_i_2
- (.I0(time_out_counter_reg[9]),
- .I1(time_out_counter_reg[10]),
- .I2(time_out_counter_reg[17]),
- .I3(time_out_counter_reg[16]),
- .I4(time_out_2ms_i_3_n_0),
- .I5(\time_out_counter[0]_i_3_n_0 ),
- .O(time_out_2ms_i_2_n_0));
- LUT2 #(
- .INIT(4'h7))
- time_out_2ms_i_3
- (.I0(time_out_counter_reg[3]),
- .I1(time_out_counter_reg[5]),
- .O(time_out_2ms_i_3_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_2ms_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_2ms_i_1_n_0),
- .Q(time_out_2ms_reg_n_0),
- .R(reset_time_out_reg_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFBF))
- \time_out_counter[0]_i_1
- (.I0(\time_out_counter[0]_i_3_n_0 ),
- .I1(time_out_counter_reg[5]),
- .I2(time_out_counter_reg[3]),
- .I3(\time_out_counter[0]_i_4__0_n_0 ),
- .I4(\time_out_counter[0]_i_5__0_n_0 ),
- .I5(\time_out_counter[0]_i_6__0_n_0 ),
- .O(time_out_counter));
- LUT2 #(
- .INIT(4'hE))
- \time_out_counter[0]_i_3
- (.I0(time_out_counter_reg[0]),
- .I1(time_out_counter_reg[1]),
- .O(\time_out_counter[0]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'hDFDD))
- \time_out_counter[0]_i_4__0
- (.I0(time_out_counter_reg[16]),
- .I1(time_out_counter_reg[17]),
- .I2(time_out_counter_reg[10]),
- .I3(time_out_counter_reg[9]),
- .O(\time_out_counter[0]_i_4__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFEFFF))
- \time_out_counter[0]_i_5__0
- (.I0(time_out_counter_reg[10]),
- .I1(time_out_counter_reg[18]),
- .I2(time_out_counter_reg[15]),
- .I3(time_out_counter_reg[19]),
- .I4(\time_out_counter[0]_i_8_n_0 ),
- .O(\time_out_counter[0]_i_5__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFD))
- \time_out_counter[0]_i_6__0
- (.I0(time_out_counter_reg[6]),
- .I1(time_out_counter_reg[14]),
- .I2(time_out_counter_reg[13]),
- .I3(time_out_counter_reg[12]),
- .I4(time_out_counter_reg[7]),
- .O(\time_out_counter[0]_i_6__0_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \time_out_counter[0]_i_7
- (.I0(time_out_counter_reg[0]),
- .O(\time_out_counter[0]_i_7_n_0 ));
- LUT4 #(
- .INIT(16'hEFFF))
- \time_out_counter[0]_i_8
- (.I0(time_out_counter_reg[4]),
- .I1(time_out_counter_reg[2]),
- .I2(time_out_counter_reg[11]),
- .I3(time_out_counter_reg[8]),
- .O(\time_out_counter[0]_i_8_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[0]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_7 ),
- .Q(time_out_counter_reg[0]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[0]_i_2__0
- (.CI(1'b0),
- .CO({\time_out_counter_reg[0]_i_2__0_n_0 ,\time_out_counter_reg[0]_i_2__0_n_1 ,\time_out_counter_reg[0]_i_2__0_n_2 ,\time_out_counter_reg[0]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\time_out_counter_reg[0]_i_2__0_n_4 ,\time_out_counter_reg[0]_i_2__0_n_5 ,\time_out_counter_reg[0]_i_2__0_n_6 ,\time_out_counter_reg[0]_i_2__0_n_7 }),
- .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_7_n_0 }));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[10]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[10]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[11]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[11]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[12]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[12]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[12]_i_1__0
- (.CI(\time_out_counter_reg[8]_i_1__0_n_0 ),
- .CO({\time_out_counter_reg[12]_i_1__0_n_0 ,\time_out_counter_reg[12]_i_1__0_n_1 ,\time_out_counter_reg[12]_i_1__0_n_2 ,\time_out_counter_reg[12]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[12]_i_1__0_n_4 ,\time_out_counter_reg[12]_i_1__0_n_5 ,\time_out_counter_reg[12]_i_1__0_n_6 ,\time_out_counter_reg[12]_i_1__0_n_7 }),
- .S(time_out_counter_reg[15:12]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[13]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[13]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[14]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[14]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[15]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[15]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[16]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[16]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[16]_i_1__0
- (.CI(\time_out_counter_reg[12]_i_1__0_n_0 ),
- .CO({\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED [3],\time_out_counter_reg[16]_i_1__0_n_1 ,\time_out_counter_reg[16]_i_1__0_n_2 ,\time_out_counter_reg[16]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[16]_i_1__0_n_4 ,\time_out_counter_reg[16]_i_1__0_n_5 ,\time_out_counter_reg[16]_i_1__0_n_6 ,\time_out_counter_reg[16]_i_1__0_n_7 }),
- .S(time_out_counter_reg[19:16]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[17]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[17]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[18]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[18]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[19]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[19]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[1]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_6 ),
- .Q(time_out_counter_reg[1]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[2]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_5 ),
- .Q(time_out_counter_reg[2]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[3]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_4 ),
- .Q(time_out_counter_reg[3]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[4]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[4]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[4]_i_1__0
- (.CI(\time_out_counter_reg[0]_i_2__0_n_0 ),
- .CO({\time_out_counter_reg[4]_i_1__0_n_0 ,\time_out_counter_reg[4]_i_1__0_n_1 ,\time_out_counter_reg[4]_i_1__0_n_2 ,\time_out_counter_reg[4]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[4]_i_1__0_n_4 ,\time_out_counter_reg[4]_i_1__0_n_5 ,\time_out_counter_reg[4]_i_1__0_n_6 ,\time_out_counter_reg[4]_i_1__0_n_7 }),
- .S(time_out_counter_reg[7:4]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[5]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[5]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[6]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[6]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[7]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[7]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[8]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[8]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[8]_i_1__0
- (.CI(\time_out_counter_reg[4]_i_1__0_n_0 ),
- .CO({\time_out_counter_reg[8]_i_1__0_n_0 ,\time_out_counter_reg[8]_i_1__0_n_1 ,\time_out_counter_reg[8]_i_1__0_n_2 ,\time_out_counter_reg[8]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[8]_i_1__0_n_4 ,\time_out_counter_reg[8]_i_1__0_n_5 ,\time_out_counter_reg[8]_i_1__0_n_6 ,\time_out_counter_reg[8]_i_1__0_n_7 }),
- .S(time_out_counter_reg[11:8]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[9]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[9]),
- .R(reset_time_out_reg_n_0));
- LUT4 #(
- .INIT(16'hAB00))
- time_out_wait_bypass_i_1__0
- (.I0(time_out_wait_bypass_reg_n_0),
- .I1(\wait_bypass_count[0]_i_4__0_n_0 ),
- .I2(rx_fsm_reset_done_int_s3),
- .I3(run_phase_alignment_int_s3_reg_n_0),
- .O(time_out_wait_bypass_i_1__0_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(time_out_wait_bypass_i_1__0_n_0),
- .Q(time_out_wait_bypass_reg_n_0),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_wait_bypass_s2),
- .Q(time_out_wait_bypass_s3),
- .R(1'b0));
- CARRY4 time_tlock_max1_carry
- (.CI(1'b0),
- .CO({time_tlock_max1_carry_n_0,time_tlock_max1_carry_n_1,time_tlock_max1_carry_n_2,time_tlock_max1_carry_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,time_out_counter_reg[5],time_out_counter_reg[3],time_tlock_max1_carry_i_1_n_0}),
- .O(NLW_time_tlock_max1_carry_O_UNCONNECTED[3:0]),
- .S({time_tlock_max1_carry_i_2_n_0,time_tlock_max1_carry_i_3_n_0,time_tlock_max1_carry_i_4_n_0,time_tlock_max1_carry_i_5_n_0}));
- CARRY4 time_tlock_max1_carry__0
- (.CI(time_tlock_max1_carry_n_0),
- .CO({time_tlock_max1_carry__0_n_0,time_tlock_max1_carry__0_n_1,time_tlock_max1_carry__0_n_2,time_tlock_max1_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({time_tlock_max1_carry__0_i_1_n_0,1'b0,time_tlock_max1_carry__0_i_2_n_0,time_tlock_max1_carry__0_i_3_n_0}),
- .O(NLW_time_tlock_max1_carry__0_O_UNCONNECTED[3:0]),
- .S({time_tlock_max1_carry__0_i_4_n_0,time_tlock_max1_carry__0_i_5_n_0,time_tlock_max1_carry__0_i_6_n_0,time_tlock_max1_carry__0_i_7_n_0}));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__0_i_1
- (.I0(time_out_counter_reg[15]),
- .I1(time_out_counter_reg[14]),
- .O(time_tlock_max1_carry__0_i_1_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__0_i_2
- (.I0(time_out_counter_reg[11]),
- .I1(time_out_counter_reg[10]),
- .O(time_tlock_max1_carry__0_i_2_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__0_i_3
- (.I0(time_out_counter_reg[9]),
- .I1(time_out_counter_reg[8]),
- .O(time_tlock_max1_carry__0_i_3_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__0_i_4
- (.I0(time_out_counter_reg[14]),
- .I1(time_out_counter_reg[15]),
- .O(time_tlock_max1_carry__0_i_4_n_0));
- LUT2 #(
- .INIT(4'h8))
- time_tlock_max1_carry__0_i_5
- (.I0(time_out_counter_reg[12]),
- .I1(time_out_counter_reg[13]),
- .O(time_tlock_max1_carry__0_i_5_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__0_i_6
- (.I0(time_out_counter_reg[10]),
- .I1(time_out_counter_reg[11]),
- .O(time_tlock_max1_carry__0_i_6_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__0_i_7
- (.I0(time_out_counter_reg[8]),
- .I1(time_out_counter_reg[9]),
- .O(time_tlock_max1_carry__0_i_7_n_0));
- CARRY4 time_tlock_max1_carry__1
- (.CI(time_tlock_max1_carry__0_n_0),
- .CO({NLW_time_tlock_max1_carry__1_CO_UNCONNECTED[3:2],time_tlock_max1,time_tlock_max1_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,time_tlock_max1_carry__1_i_1_n_0,time_tlock_max1_carry__1_i_2_n_0}),
- .O(NLW_time_tlock_max1_carry__1_O_UNCONNECTED[3:0]),
- .S({1'b0,1'b0,time_tlock_max1_carry__1_i_3_n_0,time_tlock_max1_carry__1_i_4_n_0}));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__1_i_1
- (.I0(time_out_counter_reg[18]),
- .I1(time_out_counter_reg[19]),
- .O(time_tlock_max1_carry__1_i_1_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__1_i_2
- (.I0(time_out_counter_reg[17]),
- .I1(time_out_counter_reg[16]),
- .O(time_tlock_max1_carry__1_i_2_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__1_i_3
- (.I0(time_out_counter_reg[19]),
- .I1(time_out_counter_reg[18]),
- .O(time_tlock_max1_carry__1_i_3_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__1_i_4
- (.I0(time_out_counter_reg[16]),
- .I1(time_out_counter_reg[17]),
- .O(time_tlock_max1_carry__1_i_4_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry_i_1
- (.I0(time_out_counter_reg[0]),
- .I1(time_out_counter_reg[1]),
- .O(time_tlock_max1_carry_i_1_n_0));
- LUT2 #(
- .INIT(4'h8))
- time_tlock_max1_carry_i_2
- (.I0(time_out_counter_reg[6]),
- .I1(time_out_counter_reg[7]),
- .O(time_tlock_max1_carry_i_2_n_0));
- LUT2 #(
- .INIT(4'h2))
- time_tlock_max1_carry_i_3
- (.I0(time_out_counter_reg[4]),
- .I1(time_out_counter_reg[5]),
- .O(time_tlock_max1_carry_i_3_n_0));
- LUT2 #(
- .INIT(4'h2))
- time_tlock_max1_carry_i_4
- (.I0(time_out_counter_reg[2]),
- .I1(time_out_counter_reg[3]),
- .O(time_tlock_max1_carry_i_4_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry_i_5
- (.I0(time_out_counter_reg[1]),
- .I1(time_out_counter_reg[0]),
- .O(time_tlock_max1_carry_i_5_n_0));
- (* SOFT_HLUTNM = "soft_lutpair258" *)
- LUT3 #(
- .INIT(8'hF8))
- time_tlock_max_i_1
- (.I0(time_tlock_max1),
- .I1(check_tlock_max_reg_n_0),
- .I2(time_tlock_max),
- .O(time_tlock_max_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- time_tlock_max_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_tlock_max_i_1_n_0),
- .Q(time_tlock_max),
- .R(reset_time_out_reg_n_0));
- FDCE #(
- .INIT(1'b0))
- txpmaresetdone_i_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(scndry_out),
- .D(1'b1),
- .Q(txpmaresetdone_i));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_1__0
- (.I0(run_phase_alignment_int_s3_reg_n_0),
- .O(\wait_bypass_count[0]_i_1__0_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \wait_bypass_count[0]_i_2__0
- (.I0(\wait_bypass_count[0]_i_4__0_n_0 ),
- .I1(rx_fsm_reset_done_int_s3),
- .O(\wait_bypass_count[0]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \wait_bypass_count[0]_i_4__0
- (.I0(\wait_bypass_count[0]_i_6__0_n_0 ),
- .I1(wait_bypass_count_reg[4]),
- .I2(wait_bypass_count_reg[3]),
- .I3(wait_bypass_count_reg[6]),
- .I4(wait_bypass_count_reg[5]),
- .I5(\wait_bypass_count[0]_i_7__0_n_0 ),
- .O(\wait_bypass_count[0]_i_4__0_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_5__0
- (.I0(wait_bypass_count_reg[0]),
- .O(\wait_bypass_count[0]_i_5__0_n_0 ));
- LUT4 #(
- .INIT(16'hFF7F))
- \wait_bypass_count[0]_i_6__0
- (.I0(wait_bypass_count_reg[8]),
- .I1(wait_bypass_count_reg[7]),
- .I2(wait_bypass_count_reg[9]),
- .I3(wait_bypass_count_reg[10]),
- .O(\wait_bypass_count[0]_i_6__0_n_0 ));
- LUT5 #(
- .INIT(32'hDFFFFFFF))
- \wait_bypass_count[0]_i_7__0
- (.I0(wait_bypass_count_reg[0]),
- .I1(wait_bypass_count_reg[11]),
- .I2(wait_bypass_count_reg[12]),
- .I3(wait_bypass_count_reg[2]),
- .I4(wait_bypass_count_reg[1]),
- .O(\wait_bypass_count[0]_i_7__0_n_0 ));
- FDRE \wait_bypass_count_reg[0]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_7 ),
- .Q(wait_bypass_count_reg[0]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[0]_i_3__0
- (.CI(1'b0),
- .CO({\wait_bypass_count_reg[0]_i_3__0_n_0 ,\wait_bypass_count_reg[0]_i_3__0_n_1 ,\wait_bypass_count_reg[0]_i_3__0_n_2 ,\wait_bypass_count_reg[0]_i_3__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\wait_bypass_count_reg[0]_i_3__0_n_4 ,\wait_bypass_count_reg[0]_i_3__0_n_5 ,\wait_bypass_count_reg[0]_i_3__0_n_6 ,\wait_bypass_count_reg[0]_i_3__0_n_7 }),
- .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5__0_n_0 }));
- FDRE \wait_bypass_count_reg[10]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_5 ),
- .Q(wait_bypass_count_reg[10]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[11]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_4 ),
- .Q(wait_bypass_count_reg[11]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[12]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1__0_n_7 ),
- .Q(wait_bypass_count_reg[12]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[12]_i_1__0
- (.CI(\wait_bypass_count_reg[8]_i_1__0_n_0 ),
- .CO(\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED [3:0]),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED [3:1],\wait_bypass_count_reg[12]_i_1__0_n_7 }),
- .S({1'b0,1'b0,1'b0,wait_bypass_count_reg[12]}));
- FDRE \wait_bypass_count_reg[1]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_6 ),
- .Q(wait_bypass_count_reg[1]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[2]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_5 ),
- .Q(wait_bypass_count_reg[2]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[3]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_4 ),
- .Q(wait_bypass_count_reg[3]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[4]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_7 ),
- .Q(wait_bypass_count_reg[4]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[4]_i_1__0
- (.CI(\wait_bypass_count_reg[0]_i_3__0_n_0 ),
- .CO({\wait_bypass_count_reg[4]_i_1__0_n_0 ,\wait_bypass_count_reg[4]_i_1__0_n_1 ,\wait_bypass_count_reg[4]_i_1__0_n_2 ,\wait_bypass_count_reg[4]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[4]_i_1__0_n_4 ,\wait_bypass_count_reg[4]_i_1__0_n_5 ,\wait_bypass_count_reg[4]_i_1__0_n_6 ,\wait_bypass_count_reg[4]_i_1__0_n_7 }),
- .S(wait_bypass_count_reg[7:4]));
- FDRE \wait_bypass_count_reg[5]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_6 ),
- .Q(wait_bypass_count_reg[5]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[6]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_5 ),
- .Q(wait_bypass_count_reg[6]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[7]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_4 ),
- .Q(wait_bypass_count_reg[7]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[8]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_7 ),
- .Q(wait_bypass_count_reg[8]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[8]_i_1__0
- (.CI(\wait_bypass_count_reg[4]_i_1__0_n_0 ),
- .CO({\wait_bypass_count_reg[8]_i_1__0_n_0 ,\wait_bypass_count_reg[8]_i_1__0_n_1 ,\wait_bypass_count_reg[8]_i_1__0_n_2 ,\wait_bypass_count_reg[8]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[8]_i_1__0_n_4 ,\wait_bypass_count_reg[8]_i_1__0_n_5 ,\wait_bypass_count_reg[8]_i_1__0_n_6 ,\wait_bypass_count_reg[8]_i_1__0_n_7 }),
- .S(wait_bypass_count_reg[11:8]));
- FDRE \wait_bypass_count_reg[9]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_6 ),
- .Q(wait_bypass_count_reg[9]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \wait_time_cnt[0]_i_1__0
- (.I0(wait_time_cnt_reg[0]),
- .O(wait_time_cnt0__0[0]));
- (* SOFT_HLUTNM = "soft_lutpair257" *)
- LUT2 #(
- .INIT(4'h9))
- \wait_time_cnt[1]_i_1__0
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .O(\wait_time_cnt[1]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'hE1))
- \wait_time_cnt[2]_i_1__0
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[2]),
- .O(wait_time_cnt0__0[2]));
- (* SOFT_HLUTNM = "soft_lutpair257" *)
- LUT4 #(
- .INIT(16'hFE01))
- \wait_time_cnt[3]_i_1__0
- (.I0(wait_time_cnt_reg[2]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[0]),
- .I3(wait_time_cnt_reg[3]),
- .O(wait_time_cnt0__0[3]));
- (* SOFT_HLUTNM = "soft_lutpair252" *)
- LUT5 #(
- .INIT(32'hAAAAAAA9))
- \wait_time_cnt[4]_i_1__0
- (.I0(wait_time_cnt_reg[4]),
- .I1(wait_time_cnt_reg[2]),
- .I2(wait_time_cnt_reg[1]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[3]),
- .O(wait_time_cnt0__0[4]));
- LUT6 #(
- .INIT(64'hAAAAAAAAAAAAAAA9))
- \wait_time_cnt[5]_i_1__0
- (.I0(wait_time_cnt_reg[5]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[1]),
- .I5(wait_time_cnt_reg[2]),
- .O(wait_time_cnt0__0[5]));
- LUT3 #(
- .INIT(8'h04))
- \wait_time_cnt[6]_i_1
- (.I0(rx_state[1]),
- .I1(rx_state[0]),
- .I2(rx_state[3]),
- .O(\wait_time_cnt[6]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFEFF))
- \wait_time_cnt[6]_i_2__0
- (.I0(wait_time_cnt_reg[6]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[5]),
- .I3(\wait_time_cnt[6]_i_4__0_n_0 ),
- .O(\wait_time_cnt[6]_i_2__0_n_0 ));
- LUT4 #(
- .INIT(16'hA9AA))
- \wait_time_cnt[6]_i_3__0
- (.I0(wait_time_cnt_reg[6]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[5]),
- .I3(\wait_time_cnt[6]_i_4__0_n_0 ),
- .O(wait_time_cnt0__0[6]));
- (* SOFT_HLUTNM = "soft_lutpair252" *)
- LUT4 #(
- .INIT(16'h0001))
- \wait_time_cnt[6]_i_4__0
- (.I0(wait_time_cnt_reg[3]),
- .I1(wait_time_cnt_reg[0]),
- .I2(wait_time_cnt_reg[1]),
- .I3(wait_time_cnt_reg[2]),
- .O(\wait_time_cnt[6]_i_4__0_n_0 ));
- FDRE \wait_time_cnt_reg[0]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[0]),
- .Q(wait_time_cnt_reg[0]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDRE \wait_time_cnt_reg[1]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(\wait_time_cnt[1]_i_1__0_n_0 ),
- .Q(wait_time_cnt_reg[1]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDSE \wait_time_cnt_reg[2]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[2]),
- .Q(wait_time_cnt_reg[2]),
- .S(\wait_time_cnt[6]_i_1_n_0 ));
- FDRE \wait_time_cnt_reg[3]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[3]),
- .Q(wait_time_cnt_reg[3]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDRE \wait_time_cnt_reg[4]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[4]),
- .Q(wait_time_cnt_reg[4]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDSE \wait_time_cnt_reg[5]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[5]),
- .Q(wait_time_cnt_reg[5]),
- .S(\wait_time_cnt[6]_i_1_n_0 ));
- FDSE \wait_time_cnt_reg[6]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[6]),
- .Q(wait_time_cnt_reg[6]),
- .S(\wait_time_cnt[6]_i_1_n_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "east_channel_tx_startup_fsm" *)
-module east_channel_east_channel_tx_startup_fsm
- (out,
- gt_tx_reset_i,
- gt_common_reset_out,
- gt_txuserrdy_i,
- tx_lock,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ,
- quad1_common_lock_in,
- init_clk_in,
- user_clk,
- txfsm_txresetdone_r,
- AR,
- PLL_NOT_LOCKED);
- output out;
- output gt_tx_reset_i;
- output gt_common_reset_out;
- output gt_txuserrdy_i;
- output tx_lock;
- output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- input quad1_common_lock_in;
- input init_clk_in;
- input user_clk;
- input txfsm_txresetdone_r;
- input [0:0]AR;
- input PLL_NOT_LOCKED;
-
- wire [0:0]AR;
- wire \FSM_sequential_tx_state[0]_i_2_n_0 ;
- wire \FSM_sequential_tx_state[0]_i_3_n_0 ;
- wire \FSM_sequential_tx_state[1]_i_1_n_0 ;
- wire \FSM_sequential_tx_state[1]_i_2_n_0 ;
- wire \FSM_sequential_tx_state[2]_i_1_n_0 ;
- wire \FSM_sequential_tx_state[2]_i_2_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_3_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_4_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_6_n_0 ;
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- wire MMCM_RESET;
- wire MMCM_RESET_i_1_n_0;
- wire PLL0_RESET_i_1_n_0;
- wire PLL_NOT_LOCKED;
- wire TXUSERRDY_i_1_n_0;
- wire clear;
- wire gt_common_reset_out;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire gttxreset_i_i_1_n_0;
- wire init_clk_in;
- wire init_wait_count;
- wire \init_wait_count[6]_i_3_n_0 ;
- wire \init_wait_count[6]_i_4_n_0 ;
- wire [6:0]init_wait_count_reg;
- wire init_wait_done_i_1_n_0;
- wire init_wait_done_reg_n_0;
- wire \mmcm_lock_count[9]_i_2_n_0 ;
- wire \mmcm_lock_count[9]_i_4_n_0 ;
- wire [9:0]mmcm_lock_count_reg;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_i_2_n_0;
- wire out;
- wire [6:0]p_0_in;
- wire [9:0]p_0_in__0;
- wire pll_reset_asserted_i_1_n_0;
- wire pll_reset_asserted_reg_n_0;
- wire quad1_common_lock_in;
- wire reset_time_out;
- wire reset_time_out_i_4_n_0;
- wire run_phase_alignment_int;
- wire run_phase_alignment_int_i_1_n_0;
- wire run_phase_alignment_int_s3;
- wire scndry_out;
- wire sel;
- wire sync_PLL0LOCK_cdc_sync_n_0;
- wire sync_PLL0LOCK_cdc_sync_n_1;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_0;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_1;
- wire time_out_2ms_i_1__0_n_0;
- wire time_out_2ms_i_2__0_n_0;
- wire time_out_2ms_reg_n_0;
- wire time_out_500us_i_1_n_0;
- wire time_out_500us_i_2_n_0;
- wire time_out_500us_i_3_n_0;
- wire time_out_500us_i_4_n_0;
- wire time_out_500us_i_5_n_0;
- wire time_out_500us_reg_n_0;
- wire time_out_counter;
- wire \time_out_counter[0]_i_3__0_n_0 ;
- wire \time_out_counter[0]_i_4_n_0 ;
- wire \time_out_counter[0]_i_5_n_0 ;
- wire \time_out_counter[0]_i_6_n_0 ;
- wire \time_out_counter[0]_i_7__0_n_0 ;
- wire [17:0]time_out_counter_reg;
- wire \time_out_counter_reg[0]_i_2_n_0 ;
- wire \time_out_counter_reg[0]_i_2_n_1 ;
- wire \time_out_counter_reg[0]_i_2_n_2 ;
- wire \time_out_counter_reg[0]_i_2_n_3 ;
- wire \time_out_counter_reg[0]_i_2_n_4 ;
- wire \time_out_counter_reg[0]_i_2_n_5 ;
- wire \time_out_counter_reg[0]_i_2_n_6 ;
- wire \time_out_counter_reg[0]_i_2_n_7 ;
- wire \time_out_counter_reg[12]_i_1_n_0 ;
- wire \time_out_counter_reg[12]_i_1_n_1 ;
- wire \time_out_counter_reg[12]_i_1_n_2 ;
- wire \time_out_counter_reg[12]_i_1_n_3 ;
- wire \time_out_counter_reg[12]_i_1_n_4 ;
- wire \time_out_counter_reg[12]_i_1_n_5 ;
- wire \time_out_counter_reg[12]_i_1_n_6 ;
- wire \time_out_counter_reg[12]_i_1_n_7 ;
- wire \time_out_counter_reg[16]_i_1_n_3 ;
- wire \time_out_counter_reg[16]_i_1_n_6 ;
- wire \time_out_counter_reg[16]_i_1_n_7 ;
- wire \time_out_counter_reg[4]_i_1_n_0 ;
- wire \time_out_counter_reg[4]_i_1_n_1 ;
- wire \time_out_counter_reg[4]_i_1_n_2 ;
- wire \time_out_counter_reg[4]_i_1_n_3 ;
- wire \time_out_counter_reg[4]_i_1_n_4 ;
- wire \time_out_counter_reg[4]_i_1_n_5 ;
- wire \time_out_counter_reg[4]_i_1_n_6 ;
- wire \time_out_counter_reg[4]_i_1_n_7 ;
- wire \time_out_counter_reg[8]_i_1_n_0 ;
- wire \time_out_counter_reg[8]_i_1_n_1 ;
- wire \time_out_counter_reg[8]_i_1_n_2 ;
- wire \time_out_counter_reg[8]_i_1_n_3 ;
- wire \time_out_counter_reg[8]_i_1_n_4 ;
- wire \time_out_counter_reg[8]_i_1_n_5 ;
- wire \time_out_counter_reg[8]_i_1_n_6 ;
- wire \time_out_counter_reg[8]_i_1_n_7 ;
- wire time_out_wait_bypass;
- wire time_out_wait_bypass_i_1_n_0;
- wire time_out_wait_bypass_s2;
- wire time_out_wait_bypass_s3;
- wire time_tlock_max_i_1__0_n_0;
- wire time_tlock_max_i_2_n_0;
- wire time_tlock_max_i_3_n_0;
- wire time_tlock_max_reg_n_0;
- wire tx_fsm_reset_done_int;
- wire tx_fsm_reset_done_int_i_1_n_0;
- wire tx_fsm_reset_done_int_s3;
- wire tx_lock;
- wire [3:0]tx_state;
- wire [3:0]tx_state__0;
- wire txfsm_txresetdone_r;
- wire txresetdone_s2;
- wire txresetdone_s3;
- wire user_clk;
- wire \wait_bypass_count[0]_i_2_n_0 ;
- wire \wait_bypass_count[0]_i_4_n_0 ;
- wire \wait_bypass_count[0]_i_5_n_0 ;
- wire \wait_bypass_count[0]_i_6_n_0 ;
- wire \wait_bypass_count[0]_i_7_n_0 ;
- wire \wait_bypass_count[0]_i_8_n_0 ;
- wire \wait_bypass_count[0]_i_9_n_0 ;
- wire [15:0]wait_bypass_count_reg;
- wire \wait_bypass_count_reg[0]_i_3_n_0 ;
- wire \wait_bypass_count_reg[0]_i_3_n_1 ;
- wire \wait_bypass_count_reg[0]_i_3_n_2 ;
- wire \wait_bypass_count_reg[0]_i_3_n_3 ;
- wire \wait_bypass_count_reg[0]_i_3_n_4 ;
- wire \wait_bypass_count_reg[0]_i_3_n_5 ;
- wire \wait_bypass_count_reg[0]_i_3_n_6 ;
- wire \wait_bypass_count_reg[0]_i_3_n_7 ;
- wire \wait_bypass_count_reg[12]_i_1_n_1 ;
- wire \wait_bypass_count_reg[12]_i_1_n_2 ;
- wire \wait_bypass_count_reg[12]_i_1_n_3 ;
- wire \wait_bypass_count_reg[12]_i_1_n_4 ;
- wire \wait_bypass_count_reg[12]_i_1_n_5 ;
- wire \wait_bypass_count_reg[12]_i_1_n_6 ;
- wire \wait_bypass_count_reg[12]_i_1_n_7 ;
- wire \wait_bypass_count_reg[4]_i_1_n_0 ;
- wire \wait_bypass_count_reg[4]_i_1_n_1 ;
- wire \wait_bypass_count_reg[4]_i_1_n_2 ;
- wire \wait_bypass_count_reg[4]_i_1_n_3 ;
- wire \wait_bypass_count_reg[4]_i_1_n_4 ;
- wire \wait_bypass_count_reg[4]_i_1_n_5 ;
- wire \wait_bypass_count_reg[4]_i_1_n_6 ;
- wire \wait_bypass_count_reg[4]_i_1_n_7 ;
- wire \wait_bypass_count_reg[8]_i_1_n_0 ;
- wire \wait_bypass_count_reg[8]_i_1_n_1 ;
- wire \wait_bypass_count_reg[8]_i_1_n_2 ;
- wire \wait_bypass_count_reg[8]_i_1_n_3 ;
- wire \wait_bypass_count_reg[8]_i_1_n_4 ;
- wire \wait_bypass_count_reg[8]_i_1_n_5 ;
- wire \wait_bypass_count_reg[8]_i_1_n_6 ;
- wire \wait_bypass_count_reg[8]_i_1_n_7 ;
- wire [6:0]wait_time_cnt0;
- wire \wait_time_cnt[1]_i_1_n_0 ;
- wire \wait_time_cnt[6]_i_1__0_n_0 ;
- wire \wait_time_cnt[6]_i_4_n_0 ;
- wire \wait_time_cnt[6]_i_5_n_0 ;
- wire [6:0]wait_time_cnt_reg;
- wire [3:1]\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED ;
- wire [3:2]\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED ;
- wire [3:3]\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED ;
-
- LUT6 #(
- .INIT(64'h00000000DD0D0D0D))
- \FSM_sequential_tx_state[0]_i_1
- (.I0(\FSM_sequential_tx_state[0]_i_2_n_0 ),
- .I1(\FSM_sequential_tx_state[1]_i_2_n_0 ),
- .I2(\FSM_sequential_tx_state[0]_i_3_n_0 ),
- .I3(tx_state[1]),
- .I4(time_out_2ms_reg_n_0),
- .I5(\FSM_sequential_tx_state[3]_i_6_n_0 ),
- .O(tx_state__0[0]));
- (* SOFT_HLUTNM = "soft_lutpair264" *)
- LUT2 #(
- .INIT(4'h2))
- \FSM_sequential_tx_state[0]_i_2
- (.I0(tx_state[2]),
- .I1(tx_state[3]),
- .O(\FSM_sequential_tx_state[0]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair260" *)
- LUT3 #(
- .INIT(8'h02))
- \FSM_sequential_tx_state[0]_i_3
- (.I0(tx_state[0]),
- .I1(tx_state[2]),
- .I2(tx_state[3]),
- .O(\FSM_sequential_tx_state[0]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h05105555))
- \FSM_sequential_tx_state[1]_i_1
- (.I0(tx_state[3]),
- .I1(tx_state[2]),
- .I2(tx_state[0]),
- .I3(tx_state[1]),
- .I4(\FSM_sequential_tx_state[1]_i_2_n_0 ),
- .O(\FSM_sequential_tx_state[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair267" *)
- LUT5 #(
- .INIT(32'hDDDDDFDD))
- \FSM_sequential_tx_state[1]_i_2
- (.I0(tx_state[0]),
- .I1(tx_state[1]),
- .I2(reset_time_out),
- .I3(time_tlock_max_reg_n_0),
- .I4(mmcm_lock_reclocked),
- .O(\FSM_sequential_tx_state[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0505100005551000))
- \FSM_sequential_tx_state[2]_i_1
- (.I0(tx_state[3]),
- .I1(time_out_2ms_reg_n_0),
- .I2(tx_state[0]),
- .I3(tx_state[1]),
- .I4(tx_state[2]),
- .I5(\FSM_sequential_tx_state[2]_i_2_n_0 ),
- .O(\FSM_sequential_tx_state[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair267" *)
- LUT3 #(
- .INIT(8'h04))
- \FSM_sequential_tx_state[2]_i_2
- (.I0(mmcm_lock_reclocked),
- .I1(time_tlock_max_reg_n_0),
- .I2(reset_time_out),
- .O(\FSM_sequential_tx_state[2]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hBA))
- \FSM_sequential_tx_state[3]_i_2
- (.I0(\FSM_sequential_tx_state[3]_i_6_n_0 ),
- .I1(time_out_wait_bypass_s3),
- .I2(tx_state[3]),
- .O(tx_state__0[3]));
- (* SOFT_HLUTNM = "soft_lutpair261" *)
- LUT2 #(
- .INIT(4'h1))
- \FSM_sequential_tx_state[3]_i_3
- (.I0(tx_state[1]),
- .I1(tx_state[2]),
- .O(\FSM_sequential_tx_state[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \FSM_sequential_tx_state[3]_i_4
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[6]),
- .I2(wait_time_cnt_reg[4]),
- .I3(wait_time_cnt_reg[5]),
- .I4(\wait_time_cnt[6]_i_4_n_0 ),
- .I5(wait_time_cnt_reg[1]),
- .O(\FSM_sequential_tx_state[3]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h0000D00000000000))
- \FSM_sequential_tx_state[3]_i_6
- (.I0(time_out_500us_reg_n_0),
- .I1(reset_time_out),
- .I2(tx_state[2]),
- .I3(tx_state[1]),
- .I4(tx_state[3]),
- .I5(tx_state[0]),
- .O(\FSM_sequential_tx_state[3]_i_6_n_0 ));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[0]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(tx_state__0[0]),
- .Q(tx_state[0]),
- .R(AR));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[1]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(\FSM_sequential_tx_state[1]_i_1_n_0 ),
- .Q(tx_state[1]),
- .R(AR));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[2]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(\FSM_sequential_tx_state[2]_i_1_n_0 ),
- .Q(tx_state[2]),
- .R(AR));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[3]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(tx_state__0[3]),
- .Q(tx_state[3]),
- .R(AR));
- (* SOFT_HLUTNM = "soft_lutpair260" *)
- LUT5 #(
- .INIT(32'hFFDF0010))
- MMCM_RESET_i_1
- (.I0(tx_state[2]),
- .I1(tx_state[1]),
- .I2(tx_state[0]),
- .I3(tx_state[3]),
- .I4(MMCM_RESET),
- .O(MMCM_RESET_i_1_n_0));
- FDRE #(
- .INIT(1'b1))
- MMCM_RESET_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(MMCM_RESET_i_1_n_0),
- .Q(MMCM_RESET),
- .R(AR));
- LUT6 #(
- .INIT(64'hFFFFFDFF00000100))
- PLL0_RESET_i_1
- (.I0(pll_reset_asserted_reg_n_0),
- .I1(tx_state[2]),
- .I2(tx_state[1]),
- .I3(tx_state[0]),
- .I4(tx_state[3]),
- .I5(gt_common_reset_out),
- .O(PLL0_RESET_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- PLL0_RESET_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(PLL0_RESET_i_1_n_0),
- .Q(gt_common_reset_out),
- .R(AR));
- (* SOFT_HLUTNM = "soft_lutpair264" *)
- LUT5 #(
- .INIT(32'hFEFF0800))
- TXUSERRDY_i_1
- (.I0(tx_state[1]),
- .I1(tx_state[2]),
- .I2(tx_state[3]),
- .I3(tx_state[0]),
- .I4(gt_txuserrdy_i),
- .O(TXUSERRDY_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- TXUSERRDY_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(TXUSERRDY_i_1_n_0),
- .Q(gt_txuserrdy_i),
- .R(AR));
- LUT5 #(
- .INIT(32'hFFEF0100))
- gttxreset_i_i_1
- (.I0(tx_state[3]),
- .I1(tx_state[1]),
- .I2(tx_state[2]),
- .I3(tx_state[0]),
- .I4(gt_tx_reset_i),
- .O(gttxreset_i_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- gttxreset_i_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gttxreset_i_i_1_n_0),
- .Q(gt_tx_reset_i),
- .R(AR));
- LUT1 #(
- .INIT(2'h1))
- \init_wait_count[0]_i_1
- (.I0(init_wait_count_reg[0]),
- .O(p_0_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair270" *)
- LUT2 #(
- .INIT(4'h6))
- \init_wait_count[1]_i_1
- (.I0(init_wait_count_reg[0]),
- .I1(init_wait_count_reg[1]),
- .O(p_0_in[1]));
- (* SOFT_HLUTNM = "soft_lutpair269" *)
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[2]_i_1
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .O(p_0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair270" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \init_wait_count[3]_i_1
- (.I0(init_wait_count_reg[3]),
- .I1(init_wait_count_reg[1]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[2]),
- .O(p_0_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair263" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \init_wait_count[4]_i_1
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[3]),
- .I4(init_wait_count_reg[4]),
- .O(p_0_in[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \init_wait_count[5]_i_1
- (.I0(init_wait_count_reg[5]),
- .I1(init_wait_count_reg[2]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[1]),
- .I4(init_wait_count_reg[3]),
- .I5(init_wait_count_reg[4]),
- .O(p_0_in[5]));
- LUT4 #(
- .INIT(16'hFFBF))
- \init_wait_count[6]_i_1
- (.I0(\init_wait_count[6]_i_3_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .O(init_wait_count));
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[6]_i_2
- (.I0(init_wait_count_reg[6]),
- .I1(\init_wait_count[6]_i_4_n_0 ),
- .I2(init_wait_count_reg[5]),
- .O(p_0_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair269" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \init_wait_count[6]_i_3
- (.I0(init_wait_count_reg[1]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[4]),
- .I3(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair263" *)
- LUT5 #(
- .INIT(32'h80000000))
- \init_wait_count[6]_i_4
- (.I0(init_wait_count_reg[4]),
- .I1(init_wait_count_reg[3]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[0]),
- .I4(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_4_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[0]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[0]),
- .Q(init_wait_count_reg[0]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[1]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[1]),
- .Q(init_wait_count_reg[1]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[2]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[2]),
- .Q(init_wait_count_reg[2]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[3]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[3]),
- .Q(init_wait_count_reg[3]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[4]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[4]),
- .Q(init_wait_count_reg[4]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[5]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[5]),
- .Q(init_wait_count_reg[5]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[6]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[6]),
- .Q(init_wait_count_reg[6]));
- LUT5 #(
- .INIT(32'hFFFF0040))
- init_wait_done_i_1
- (.I0(\init_wait_count[6]_i_3_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .I4(init_wait_done_reg_n_0),
- .O(init_wait_done_i_1_n_0));
- FDCE #(
- .INIT(1'b0))
- init_wait_done_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(AR),
- .D(init_wait_done_i_1_n_0),
- .Q(init_wait_done_reg_n_0));
- (* SOFT_HLUTNM = "soft_lutpair274" *)
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[0]_i_1
- (.I0(mmcm_lock_count_reg[0]),
- .O(p_0_in__0[0]));
- (* SOFT_HLUTNM = "soft_lutpair274" *)
- LUT2 #(
- .INIT(4'h6))
- \mmcm_lock_count[1]_i_1
- (.I0(mmcm_lock_count_reg[0]),
- .I1(mmcm_lock_count_reg[1]),
- .O(p_0_in__0[1]));
- (* SOFT_HLUTNM = "soft_lutpair271" *)
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[2]_i_1
- (.I0(mmcm_lock_count_reg[2]),
- .I1(mmcm_lock_count_reg[0]),
- .I2(mmcm_lock_count_reg[1]),
- .O(p_0_in__0[2]));
- (* SOFT_HLUTNM = "soft_lutpair271" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[3]_i_1
- (.I0(mmcm_lock_count_reg[3]),
- .I1(mmcm_lock_count_reg[1]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[2]),
- .O(p_0_in__0[3]));
- (* SOFT_HLUTNM = "soft_lutpair262" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[4]_i_1
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .O(p_0_in__0[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[5]_i_1
- (.I0(mmcm_lock_count_reg[5]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .I5(mmcm_lock_count_reg[4]),
- .O(p_0_in__0[5]));
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[6]_i_1
- (.I0(mmcm_lock_count_reg[6]),
- .I1(\mmcm_lock_count[9]_i_4_n_0 ),
- .I2(mmcm_lock_count_reg[5]),
- .O(p_0_in__0[6]));
- (* SOFT_HLUTNM = "soft_lutpair265" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[7]_i_1
- (.I0(mmcm_lock_count_reg[7]),
- .I1(mmcm_lock_count_reg[5]),
- .I2(\mmcm_lock_count[9]_i_4_n_0 ),
- .I3(mmcm_lock_count_reg[6]),
- .O(p_0_in__0[7]));
- (* SOFT_HLUTNM = "soft_lutpair265" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[8]_i_1
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .O(p_0_in__0[8]));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- \mmcm_lock_count[9]_i_2
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .I5(mmcm_lock_count_reg[9]),
- .O(\mmcm_lock_count[9]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[9]_i_3
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(p_0_in__0[9]));
- (* SOFT_HLUTNM = "soft_lutpair262" *)
- LUT5 #(
- .INIT(32'h80000000))
- \mmcm_lock_count[9]_i_4
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[3]),
- .I2(mmcm_lock_count_reg[1]),
- .I3(mmcm_lock_count_reg[0]),
- .I4(mmcm_lock_count_reg[2]),
- .O(\mmcm_lock_count[9]_i_4_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[0]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[0]),
- .Q(mmcm_lock_count_reg[0]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[1]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[1]),
- .Q(mmcm_lock_count_reg[1]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[2]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[2]),
- .Q(mmcm_lock_count_reg[2]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[3]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[3]),
- .Q(mmcm_lock_count_reg[3]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[4]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[4]),
- .Q(mmcm_lock_count_reg[4]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[5]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[5]),
- .Q(mmcm_lock_count_reg[5]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[6]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[6]),
- .Q(mmcm_lock_count_reg[6]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[7]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[7]),
- .Q(mmcm_lock_count_reg[7]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[8]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[8]),
- .Q(mmcm_lock_count_reg[8]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[9]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[9]),
- .Q(mmcm_lock_count_reg[9]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- mmcm_lock_reclocked_i_2
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(mmcm_lock_reclocked_i_2_n_0));
- FDRE #(
- .INIT(1'b0))
- mmcm_lock_reclocked_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .Q(mmcm_lock_reclocked),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hEFFF0010))
- pll_reset_asserted_i_1
- (.I0(tx_state[3]),
- .I1(tx_state[2]),
- .I2(tx_state[0]),
- .I3(tx_state[1]),
- .I4(pll_reset_asserted_reg_n_0),
- .O(pll_reset_asserted_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- pll_reset_asserted_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(pll_reset_asserted_i_1_n_0),
- .Q(pll_reset_asserted_reg_n_0),
- .R(AR));
- LUT5 #(
- .INIT(32'h40FF4040))
- reset_time_out_i_4
- (.I0(tx_state[1]),
- .I1(tx_state[2]),
- .I2(mmcm_lock_reclocked),
- .I3(tx_state[0]),
- .I4(init_wait_done_reg_n_0),
- .O(reset_time_out_i_4_n_0));
- FDRE #(
- .INIT(1'b0))
- reset_time_out_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_PLL0LOCK_cdc_sync_n_1),
- .Q(reset_time_out),
- .R(AR));
- LUT5 #(
- .INIT(32'hFEFF0010))
- run_phase_alignment_int_i_1
- (.I0(tx_state[2]),
- .I1(tx_state[1]),
- .I2(tx_state[3]),
- .I3(tx_state[0]),
- .I4(run_phase_alignment_int),
- .O(run_phase_alignment_int_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(run_phase_alignment_int_i_1_n_0),
- .Q(run_phase_alignment_int),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(scndry_out),
- .Q(run_phase_alignment_int_s3),
- .R(1'b0));
- east_channel_east_channel_cdc_sync__parameterized1_1 sync_PLL0LOCK_cdc_sync
- (.E(sync_PLL0LOCK_cdc_sync_n_0),
- .\FSM_sequential_tx_state_reg[0] (sync_PLL0LOCK_cdc_sync_n_1),
- .\FSM_sequential_tx_state_reg[0]_0 (init_wait_done_reg_n_0),
- .\FSM_sequential_tx_state_reg[0]_1 (\FSM_sequential_tx_state[3]_i_4_n_0 ),
- .\FSM_sequential_tx_state_reg[3]_i_5_0 (time_tlock_max_reg_n_0),
- .\FSM_sequential_tx_state_reg[3]_i_5_1 (pll_reset_asserted_reg_n_0),
- .\FSM_sequential_tx_state_reg[3]_i_5_2 (time_out_500us_reg_n_0),
- .\FSM_sequential_tx_state_reg[3]_i_5_3 (time_out_2ms_reg_n_0),
- .Q(tx_state),
- .init_clk_in(init_clk_in),
- .mmcm_lock_reclocked(mmcm_lock_reclocked),
- .quad1_common_lock_in(quad1_common_lock_in),
- .reset_time_out(reset_time_out),
- .reset_time_out_reg(\FSM_sequential_tx_state[3]_i_3_n_0 ),
- .reset_time_out_reg_0(reset_time_out_i_4_n_0),
- .txresetdone_s3(txresetdone_s3));
- east_channel_east_channel_cdc_sync__parameterized1_2 sync_PLL1LOCK_cdc_sync
- (.init_clk_in(init_clk_in));
- east_channel_east_channel_cdc_sync__parameterized6_3 sync_TXRESETDONE_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(txresetdone_s2),
- .txfsm_txresetdone_r(txfsm_txresetdone_r),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized1_4 sync_mmcm_lock_reclocked_cdc_sync
- (.PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .SR(sync_mmcm_lock_reclocked_cdc_sync_n_0),
- .init_clk_in(init_clk_in),
- .mmcm_lock_reclocked(mmcm_lock_reclocked),
- .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .mmcm_lock_reclocked_reg_0(mmcm_lock_reclocked_i_2_n_0));
- east_channel_east_channel_cdc_sync__parameterized3 sync_run_phase_alignment_int_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(scndry_out),
- .run_phase_alignment_int(run_phase_alignment_int),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized6_5 sync_time_out_wait_bypass_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(time_out_wait_bypass_s2),
- .time_out_wait_bypass(time_out_wait_bypass),
- .user_clk(user_clk));
- east_channel_east_channel_cdc_sync__parameterized3_6 sync_tx_fsm_reset_done_int_cdc_sync
- (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ),
- .init_clk_in(init_clk_in),
- .out(out),
- .tx_fsm_reset_done_int(tx_fsm_reset_done_int),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'h0000AAAB))
- time_out_2ms_i_1__0
- (.I0(time_out_2ms_reg_n_0),
- .I1(\time_out_counter[0]_i_5_n_0 ),
- .I2(time_out_2ms_i_2__0_n_0),
- .I3(\time_out_counter[0]_i_3__0_n_0 ),
- .I4(reset_time_out),
- .O(time_out_2ms_i_1__0_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFF8FFFFFF))
- time_out_2ms_i_2__0
- (.I0(time_out_counter_reg[7]),
- .I1(time_out_counter_reg[6]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[16]),
- .I4(time_out_counter_reg[17]),
- .I5(time_out_counter_reg[2]),
- .O(time_out_2ms_i_2__0_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_2ms_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_2ms_i_1__0_n_0),
- .Q(time_out_2ms_reg_n_0),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h00000000AAAAAAAE))
- time_out_500us_i_1
- (.I0(time_out_500us_reg_n_0),
- .I1(time_out_500us_i_2_n_0),
- .I2(time_out_500us_i_3_n_0),
- .I3(time_out_500us_i_4_n_0),
- .I4(time_out_500us_i_5_n_0),
- .I5(reset_time_out),
- .O(time_out_500us_i_1_n_0));
- LUT6 #(
- .INIT(64'h0000000000000008))
- time_out_500us_i_2
- (.I0(time_out_counter_reg[12]),
- .I1(time_out_counter_reg[13]),
- .I2(time_out_counter_reg[16]),
- .I3(time_out_counter_reg[17]),
- .I4(time_out_counter_reg[9]),
- .I5(time_out_counter_reg[11]),
- .O(time_out_500us_i_2_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF0DFF))
- time_out_500us_i_3
- (.I0(time_out_counter_reg[15]),
- .I1(time_out_counter_reg[16]),
- .I2(time_out_counter_reg[17]),
- .I3(time_out_counter_reg[2]),
- .I4(time_out_counter_reg[0]),
- .I5(time_out_counter_reg[1]),
- .O(time_out_500us_i_3_n_0));
- LUT4 #(
- .INIT(16'hDFFF))
- time_out_500us_i_4
- (.I0(time_out_counter_reg[14]),
- .I1(time_out_counter_reg[6]),
- .I2(time_out_counter_reg[10]),
- .I3(time_out_counter_reg[5]),
- .O(time_out_500us_i_4_n_0));
- (* SOFT_HLUTNM = "soft_lutpair268" *)
- LUT4 #(
- .INIT(16'hFFFE))
- time_out_500us_i_5
- (.I0(time_out_counter_reg[7]),
- .I1(time_out_counter_reg[4]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[3]),
- .O(time_out_500us_i_5_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_500us_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_500us_i_1_n_0),
- .Q(time_out_500us_reg_n_0),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFEFFF))
- \time_out_counter[0]_i_1__0
- (.I0(\time_out_counter[0]_i_3__0_n_0 ),
- .I1(time_out_counter_reg[2]),
- .I2(time_out_counter_reg[17]),
- .I3(time_out_counter_reg[16]),
- .I4(\time_out_counter[0]_i_4_n_0 ),
- .I5(\time_out_counter[0]_i_5_n_0 ),
- .O(time_out_counter));
- LUT6 #(
- .INIT(64'hFFFFEFFFFFFFFFFF))
- \time_out_counter[0]_i_3__0
- (.I0(time_out_counter_reg[1]),
- .I1(time_out_counter_reg[0]),
- .I2(time_out_counter_reg[12]),
- .I3(time_out_counter_reg[14]),
- .I4(time_out_counter_reg[13]),
- .I5(time_out_counter_reg[15]),
- .O(\time_out_counter[0]_i_3__0_n_0 ));
- LUT3 #(
- .INIT(8'hEA))
- \time_out_counter[0]_i_4
- (.I0(time_out_counter_reg[8]),
- .I1(time_out_counter_reg[6]),
- .I2(time_out_counter_reg[7]),
- .O(\time_out_counter[0]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \time_out_counter[0]_i_5
- (.I0(time_out_counter_reg[9]),
- .I1(time_out_counter_reg[11]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[10]),
- .I4(\time_out_counter[0]_i_7__0_n_0 ),
- .O(\time_out_counter[0]_i_5_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \time_out_counter[0]_i_6
- (.I0(time_out_counter_reg[0]),
- .O(\time_out_counter[0]_i_6_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair268" *)
- LUT4 #(
- .INIT(16'hEFFF))
- \time_out_counter[0]_i_7__0
- (.I0(time_out_counter_reg[5]),
- .I1(time_out_counter_reg[3]),
- .I2(time_out_counter_reg[7]),
- .I3(time_out_counter_reg[4]),
- .O(\time_out_counter[0]_i_7__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[0]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_7 ),
- .Q(time_out_counter_reg[0]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[0]_i_2
- (.CI(1'b0),
- .CO({\time_out_counter_reg[0]_i_2_n_0 ,\time_out_counter_reg[0]_i_2_n_1 ,\time_out_counter_reg[0]_i_2_n_2 ,\time_out_counter_reg[0]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\time_out_counter_reg[0]_i_2_n_4 ,\time_out_counter_reg[0]_i_2_n_5 ,\time_out_counter_reg[0]_i_2_n_6 ,\time_out_counter_reg[0]_i_2_n_7 }),
- .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_6_n_0 }));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[10]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_5 ),
- .Q(time_out_counter_reg[10]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[11]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_4 ),
- .Q(time_out_counter_reg[11]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[12]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_7 ),
- .Q(time_out_counter_reg[12]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[12]_i_1
- (.CI(\time_out_counter_reg[8]_i_1_n_0 ),
- .CO({\time_out_counter_reg[12]_i_1_n_0 ,\time_out_counter_reg[12]_i_1_n_1 ,\time_out_counter_reg[12]_i_1_n_2 ,\time_out_counter_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[12]_i_1_n_4 ,\time_out_counter_reg[12]_i_1_n_5 ,\time_out_counter_reg[12]_i_1_n_6 ,\time_out_counter_reg[12]_i_1_n_7 }),
- .S(time_out_counter_reg[15:12]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[13]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_6 ),
- .Q(time_out_counter_reg[13]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[14]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_5 ),
- .Q(time_out_counter_reg[14]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[15]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_4 ),
- .Q(time_out_counter_reg[15]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[16]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1_n_7 ),
- .Q(time_out_counter_reg[16]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[16]_i_1
- (.CI(\time_out_counter_reg[12]_i_1_n_0 ),
- .CO({\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED [3:1],\time_out_counter_reg[16]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED [3:2],\time_out_counter_reg[16]_i_1_n_6 ,\time_out_counter_reg[16]_i_1_n_7 }),
- .S({1'b0,1'b0,time_out_counter_reg[17:16]}));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[17]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1_n_6 ),
- .Q(time_out_counter_reg[17]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[1]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_6 ),
- .Q(time_out_counter_reg[1]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[2]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_5 ),
- .Q(time_out_counter_reg[2]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[3]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_4 ),
- .Q(time_out_counter_reg[3]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[4]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_7 ),
- .Q(time_out_counter_reg[4]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[4]_i_1
- (.CI(\time_out_counter_reg[0]_i_2_n_0 ),
- .CO({\time_out_counter_reg[4]_i_1_n_0 ,\time_out_counter_reg[4]_i_1_n_1 ,\time_out_counter_reg[4]_i_1_n_2 ,\time_out_counter_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[4]_i_1_n_4 ,\time_out_counter_reg[4]_i_1_n_5 ,\time_out_counter_reg[4]_i_1_n_6 ,\time_out_counter_reg[4]_i_1_n_7 }),
- .S(time_out_counter_reg[7:4]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[5]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_6 ),
- .Q(time_out_counter_reg[5]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[6]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_5 ),
- .Q(time_out_counter_reg[6]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[7]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_4 ),
- .Q(time_out_counter_reg[7]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[8]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_7 ),
- .Q(time_out_counter_reg[8]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[8]_i_1
- (.CI(\time_out_counter_reg[4]_i_1_n_0 ),
- .CO({\time_out_counter_reg[8]_i_1_n_0 ,\time_out_counter_reg[8]_i_1_n_1 ,\time_out_counter_reg[8]_i_1_n_2 ,\time_out_counter_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[8]_i_1_n_4 ,\time_out_counter_reg[8]_i_1_n_5 ,\time_out_counter_reg[8]_i_1_n_6 ,\time_out_counter_reg[8]_i_1_n_7 }),
- .S(time_out_counter_reg[11:8]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[9]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_6 ),
- .Q(time_out_counter_reg[9]),
- .R(reset_time_out));
- LUT4 #(
- .INIT(16'hAB00))
- time_out_wait_bypass_i_1
- (.I0(time_out_wait_bypass),
- .I1(\wait_bypass_count[0]_i_4_n_0 ),
- .I2(tx_fsm_reset_done_int_s3),
- .I3(run_phase_alignment_int_s3),
- .O(time_out_wait_bypass_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(time_out_wait_bypass_i_1_n_0),
- .Q(time_out_wait_bypass),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_wait_bypass_s2),
- .Q(time_out_wait_bypass_s3),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h00000000AAAAAABA))
- time_tlock_max_i_1__0
- (.I0(time_tlock_max_reg_n_0),
- .I1(time_tlock_max_i_2_n_0),
- .I2(\time_out_counter[0]_i_4_n_0 ),
- .I3(time_tlock_max_i_3_n_0),
- .I4(\time_out_counter[0]_i_5_n_0 ),
- .I5(reset_time_out),
- .O(time_tlock_max_i_1__0_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFDFFFD))
- time_tlock_max_i_2
- (.I0(time_out_counter_reg[2]),
- .I1(time_out_counter_reg[0]),
- .I2(time_out_counter_reg[1]),
- .I3(time_out_counter_reg[15]),
- .I4(time_out_counter_reg[16]),
- .I5(time_out_counter_reg[17]),
- .O(time_tlock_max_i_2_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFF7))
- time_tlock_max_i_3
- (.I0(time_out_counter_reg[12]),
- .I1(time_out_counter_reg[13]),
- .I2(time_out_counter_reg[16]),
- .I3(time_out_counter_reg[17]),
- .I4(time_out_counter_reg[14]),
- .O(time_tlock_max_i_3_n_0));
- FDRE #(
- .INIT(1'b0))
- time_tlock_max_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_tlock_max_i_1__0_n_0),
- .Q(time_tlock_max_reg_n_0),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair261" *)
- LUT5 #(
- .INIT(32'hFFFF0200))
- tx_fsm_reset_done_int_i_1
- (.I0(tx_state[0]),
- .I1(tx_state[2]),
- .I2(tx_state[1]),
- .I3(tx_state[3]),
- .I4(tx_fsm_reset_done_int),
- .O(tx_fsm_reset_done_int_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- tx_fsm_reset_done_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_fsm_reset_done_int_i_1_n_0),
- .Q(tx_fsm_reset_done_int),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- tx_fsm_reset_done_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(out),
- .Q(tx_fsm_reset_done_int_s3),
- .R(1'b0));
- LUT2 #(
- .INIT(4'h2))
- tx_lock_INST_0
- (.I0(quad1_common_lock_in),
- .I1(MMCM_RESET),
- .O(tx_lock));
- FDRE #(
- .INIT(1'b0))
- txresetdone_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(txresetdone_s2),
- .Q(txresetdone_s3),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_1
- (.I0(run_phase_alignment_int_s3),
- .O(clear));
- LUT2 #(
- .INIT(4'h2))
- \wait_bypass_count[0]_i_2
- (.I0(\wait_bypass_count[0]_i_4_n_0 ),
- .I1(tx_fsm_reset_done_int_s3),
- .O(\wait_bypass_count[0]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \wait_bypass_count[0]_i_4
- (.I0(\wait_bypass_count[0]_i_6_n_0 ),
- .I1(\wait_bypass_count[0]_i_7_n_0 ),
- .I2(\wait_bypass_count[0]_i_8_n_0 ),
- .I3(\wait_bypass_count[0]_i_9_n_0 ),
- .O(\wait_bypass_count[0]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_5
- (.I0(wait_bypass_count_reg[0]),
- .O(\wait_bypass_count[0]_i_5_n_0 ));
- LUT4 #(
- .INIT(16'h7FFF))
- \wait_bypass_count[0]_i_6
- (.I0(wait_bypass_count_reg[5]),
- .I1(wait_bypass_count_reg[4]),
- .I2(wait_bypass_count_reg[7]),
- .I3(wait_bypass_count_reg[6]),
- .O(\wait_bypass_count[0]_i_6_n_0 ));
- LUT4 #(
- .INIT(16'h7FFF))
- \wait_bypass_count[0]_i_7
- (.I0(wait_bypass_count_reg[1]),
- .I1(wait_bypass_count_reg[0]),
- .I2(wait_bypass_count_reg[3]),
- .I3(wait_bypass_count_reg[2]),
- .O(\wait_bypass_count[0]_i_7_n_0 ));
- LUT4 #(
- .INIT(16'hFF7F))
- \wait_bypass_count[0]_i_8
- (.I0(wait_bypass_count_reg[13]),
- .I1(wait_bypass_count_reg[12]),
- .I2(wait_bypass_count_reg[15]),
- .I3(wait_bypass_count_reg[14]),
- .O(\wait_bypass_count[0]_i_8_n_0 ));
- LUT4 #(
- .INIT(16'hFFFD))
- \wait_bypass_count[0]_i_9
- (.I0(wait_bypass_count_reg[9]),
- .I1(wait_bypass_count_reg[8]),
- .I2(wait_bypass_count_reg[11]),
- .I3(wait_bypass_count_reg[10]),
- .O(\wait_bypass_count[0]_i_9_n_0 ));
- FDRE \wait_bypass_count_reg[0]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_7 ),
- .Q(wait_bypass_count_reg[0]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[0]_i_3
- (.CI(1'b0),
- .CO({\wait_bypass_count_reg[0]_i_3_n_0 ,\wait_bypass_count_reg[0]_i_3_n_1 ,\wait_bypass_count_reg[0]_i_3_n_2 ,\wait_bypass_count_reg[0]_i_3_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\wait_bypass_count_reg[0]_i_3_n_4 ,\wait_bypass_count_reg[0]_i_3_n_5 ,\wait_bypass_count_reg[0]_i_3_n_6 ,\wait_bypass_count_reg[0]_i_3_n_7 }),
- .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5_n_0 }));
- FDRE \wait_bypass_count_reg[10]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_5 ),
- .Q(wait_bypass_count_reg[10]),
- .R(clear));
- FDRE \wait_bypass_count_reg[11]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_4 ),
- .Q(wait_bypass_count_reg[11]),
- .R(clear));
- FDRE \wait_bypass_count_reg[12]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_7 ),
- .Q(wait_bypass_count_reg[12]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[12]_i_1
- (.CI(\wait_bypass_count_reg[8]_i_1_n_0 ),
- .CO({\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED [3],\wait_bypass_count_reg[12]_i_1_n_1 ,\wait_bypass_count_reg[12]_i_1_n_2 ,\wait_bypass_count_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[12]_i_1_n_4 ,\wait_bypass_count_reg[12]_i_1_n_5 ,\wait_bypass_count_reg[12]_i_1_n_6 ,\wait_bypass_count_reg[12]_i_1_n_7 }),
- .S(wait_bypass_count_reg[15:12]));
- FDRE \wait_bypass_count_reg[13]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_6 ),
- .Q(wait_bypass_count_reg[13]),
- .R(clear));
- FDRE \wait_bypass_count_reg[14]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_5 ),
- .Q(wait_bypass_count_reg[14]),
- .R(clear));
- FDRE \wait_bypass_count_reg[15]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_4 ),
- .Q(wait_bypass_count_reg[15]),
- .R(clear));
- FDRE \wait_bypass_count_reg[1]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_6 ),
- .Q(wait_bypass_count_reg[1]),
- .R(clear));
- FDRE \wait_bypass_count_reg[2]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_5 ),
- .Q(wait_bypass_count_reg[2]),
- .R(clear));
- FDRE \wait_bypass_count_reg[3]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_4 ),
- .Q(wait_bypass_count_reg[3]),
- .R(clear));
- FDRE \wait_bypass_count_reg[4]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_7 ),
- .Q(wait_bypass_count_reg[4]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[4]_i_1
- (.CI(\wait_bypass_count_reg[0]_i_3_n_0 ),
- .CO({\wait_bypass_count_reg[4]_i_1_n_0 ,\wait_bypass_count_reg[4]_i_1_n_1 ,\wait_bypass_count_reg[4]_i_1_n_2 ,\wait_bypass_count_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[4]_i_1_n_4 ,\wait_bypass_count_reg[4]_i_1_n_5 ,\wait_bypass_count_reg[4]_i_1_n_6 ,\wait_bypass_count_reg[4]_i_1_n_7 }),
- .S(wait_bypass_count_reg[7:4]));
- FDRE \wait_bypass_count_reg[5]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_6 ),
- .Q(wait_bypass_count_reg[5]),
- .R(clear));
- FDRE \wait_bypass_count_reg[6]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_5 ),
- .Q(wait_bypass_count_reg[6]),
- .R(clear));
- FDRE \wait_bypass_count_reg[7]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_4 ),
- .Q(wait_bypass_count_reg[7]),
- .R(clear));
- FDRE \wait_bypass_count_reg[8]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_7 ),
- .Q(wait_bypass_count_reg[8]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[8]_i_1
- (.CI(\wait_bypass_count_reg[4]_i_1_n_0 ),
- .CO({\wait_bypass_count_reg[8]_i_1_n_0 ,\wait_bypass_count_reg[8]_i_1_n_1 ,\wait_bypass_count_reg[8]_i_1_n_2 ,\wait_bypass_count_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[8]_i_1_n_4 ,\wait_bypass_count_reg[8]_i_1_n_5 ,\wait_bypass_count_reg[8]_i_1_n_6 ,\wait_bypass_count_reg[8]_i_1_n_7 }),
- .S(wait_bypass_count_reg[11:8]));
- FDRE \wait_bypass_count_reg[9]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_6 ),
- .Q(wait_bypass_count_reg[9]),
- .R(clear));
- LUT1 #(
- .INIT(2'h1))
- \wait_time_cnt[0]_i_1
- (.I0(wait_time_cnt_reg[0]),
- .O(wait_time_cnt0[0]));
- (* SOFT_HLUTNM = "soft_lutpair272" *)
- LUT2 #(
- .INIT(4'h9))
- \wait_time_cnt[1]_i_1
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .O(\wait_time_cnt[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair273" *)
- LUT3 #(
- .INIT(8'hE1))
- \wait_time_cnt[2]_i_1
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[2]),
- .O(wait_time_cnt0[2]));
- (* SOFT_HLUTNM = "soft_lutpair272" *)
- LUT4 #(
- .INIT(16'hFE01))
- \wait_time_cnt[3]_i_1
- (.I0(wait_time_cnt_reg[2]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[0]),
- .I3(wait_time_cnt_reg[3]),
- .O(wait_time_cnt0[3]));
- (* SOFT_HLUTNM = "soft_lutpair266" *)
- LUT5 #(
- .INIT(32'hAAAAAAA9))
- \wait_time_cnt[4]_i_1
- (.I0(wait_time_cnt_reg[4]),
- .I1(wait_time_cnt_reg[2]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[1]),
- .O(wait_time_cnt0[4]));
- LUT6 #(
- .INIT(64'hFFFFFFFE00000001))
- \wait_time_cnt[5]_i_1
- (.I0(wait_time_cnt_reg[4]),
- .I1(wait_time_cnt_reg[2]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[1]),
- .I5(wait_time_cnt_reg[5]),
- .O(wait_time_cnt0[5]));
- LUT4 #(
- .INIT(16'h1300))
- \wait_time_cnt[6]_i_1__0
- (.I0(tx_state[1]),
- .I1(tx_state[3]),
- .I2(tx_state[2]),
- .I3(tx_state[0]),
- .O(\wait_time_cnt[6]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \wait_time_cnt[6]_i_2
- (.I0(wait_time_cnt_reg[1]),
- .I1(\wait_time_cnt[6]_i_4_n_0 ),
- .I2(wait_time_cnt_reg[5]),
- .I3(wait_time_cnt_reg[4]),
- .I4(wait_time_cnt_reg[6]),
- .I5(wait_time_cnt_reg[0]),
- .O(sel));
- LUT4 #(
- .INIT(16'hA9AA))
- \wait_time_cnt[6]_i_3
- (.I0(wait_time_cnt_reg[6]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[5]),
- .I3(\wait_time_cnt[6]_i_5_n_0 ),
- .O(wait_time_cnt0[6]));
- (* SOFT_HLUTNM = "soft_lutpair273" *)
- LUT2 #(
- .INIT(4'hE))
- \wait_time_cnt[6]_i_4
- (.I0(wait_time_cnt_reg[2]),
- .I1(wait_time_cnt_reg[3]),
- .O(\wait_time_cnt[6]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair266" *)
- LUT4 #(
- .INIT(16'h0001))
- \wait_time_cnt[6]_i_5
- (.I0(wait_time_cnt_reg[1]),
- .I1(wait_time_cnt_reg[0]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[2]),
- .O(\wait_time_cnt[6]_i_5_n_0 ));
- FDRE \wait_time_cnt_reg[0]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[0]),
- .Q(wait_time_cnt_reg[0]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDRE \wait_time_cnt_reg[1]
- (.C(init_clk_in),
- .CE(sel),
- .D(\wait_time_cnt[1]_i_1_n_0 ),
- .Q(wait_time_cnt_reg[1]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDSE \wait_time_cnt_reg[2]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[2]),
- .Q(wait_time_cnt_reg[2]),
- .S(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDRE \wait_time_cnt_reg[3]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[3]),
- .Q(wait_time_cnt_reg[3]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDRE \wait_time_cnt_reg[4]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[4]),
- .Q(wait_time_cnt_reg[4]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDSE \wait_time_cnt_reg[5]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[5]),
- .Q(wait_time_cnt_reg[5]),
- .S(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDSE \wait_time_cnt_reg[6]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[6]),
- .Q(wait_time_cnt_reg[6]),
- .S(\wait_time_cnt[6]_i_1__0_n_0 ));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_stub.v b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_stub.v
deleted file mode 100644
index 708f0d1c1f35d5f2f002a4f861f6223bb52cae91..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_stub.v
+++ /dev/null
@@ -1,81 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 28 10:23:57 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_stub.v
-// Design : east_channel
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-module east_channel(s_axi_tx_tdata, s_axi_tx_tvalid,
- s_axi_tx_tready, s_axi_tx_tkeep, s_axi_tx_tlast, m_axi_rx_tdata, m_axi_rx_tvalid,
- m_axi_rx_tkeep, m_axi_rx_tlast, s_axi_ufc_tx_tvalid, s_axi_ufc_tx_tdata,
- s_axi_ufc_tx_tready, m_axi_ufc_rx_tdata, m_axi_ufc_rx_tkeep, m_axi_ufc_rx_tvalid,
- m_axi_ufc_rx_tlast, rxp, rxn, txp, txn, gt_refclk1, frame_err, hard_err, soft_err, channel_up,
- lane_up, user_clk, sync_clk, reset, power_down, loopback, gt_reset, tx_lock, sys_reset_out,
- init_clk_in, tx_resetdone_out, rx_resetdone_out, link_reset_out, drpclk_in, drpaddr_in,
- drpdi_in, drpdo_out, drpen_in, drprdy_out, drpwe_in, gt_common_reset_out,
- gt0_pll0refclklost_in, quad1_common_lock_in, GT0_PLL0OUTCLK_IN, GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN, GT0_PLL1OUTREFCLK_IN, tx_out_clk, pll_not_locked)
-/* synthesis syn_black_box black_box_pad_pin="s_axi_tx_tdata[0:31],s_axi_tx_tvalid,s_axi_tx_tready,s_axi_tx_tkeep[0:3],s_axi_tx_tlast,m_axi_rx_tdata[0:31],m_axi_rx_tvalid,m_axi_rx_tkeep[0:3],m_axi_rx_tlast,s_axi_ufc_tx_tvalid,s_axi_ufc_tx_tdata[0:2],s_axi_ufc_tx_tready,m_axi_ufc_rx_tdata[0:31],m_axi_ufc_rx_tkeep[0:3],m_axi_ufc_rx_tvalid,m_axi_ufc_rx_tlast,rxp[0:0],rxn[0:0],txp[0:0],txn[0:0],gt_refclk1,frame_err,hard_err,soft_err,channel_up,lane_up[0:0],user_clk,sync_clk,reset,power_down,loopback[2:0],gt_reset,tx_lock,sys_reset_out,init_clk_in,tx_resetdone_out,rx_resetdone_out,link_reset_out,drpclk_in,drpaddr_in[8:0],drpdi_in[15:0],drpdo_out[15:0],drpen_in,drprdy_out,drpwe_in,gt_common_reset_out,gt0_pll0refclklost_in,quad1_common_lock_in,GT0_PLL0OUTCLK_IN,GT0_PLL1OUTCLK_IN,GT0_PLL0OUTREFCLK_IN,GT0_PLL1OUTREFCLK_IN,tx_out_clk,pll_not_locked" */;
- input [0:31]s_axi_tx_tdata;
- input s_axi_tx_tvalid;
- output s_axi_tx_tready;
- input [0:3]s_axi_tx_tkeep;
- input s_axi_tx_tlast;
- output [0:31]m_axi_rx_tdata;
- output m_axi_rx_tvalid;
- output [0:3]m_axi_rx_tkeep;
- output m_axi_rx_tlast;
- input s_axi_ufc_tx_tvalid;
- input [0:2]s_axi_ufc_tx_tdata;
- output s_axi_ufc_tx_tready;
- output [0:31]m_axi_ufc_rx_tdata;
- output [0:3]m_axi_ufc_rx_tkeep;
- output m_axi_ufc_rx_tvalid;
- output m_axi_ufc_rx_tlast;
- input [0:0]rxp;
- input [0:0]rxn;
- output [0:0]txp;
- output [0:0]txn;
- input gt_refclk1;
- output frame_err;
- output hard_err;
- output soft_err;
- output channel_up;
- output [0:0]lane_up;
- input user_clk;
- input sync_clk;
- input reset;
- input power_down;
- input [2:0]loopback;
- input gt_reset;
- output tx_lock;
- output sys_reset_out;
- input init_clk_in;
- output tx_resetdone_out;
- output rx_resetdone_out;
- output link_reset_out;
- input drpclk_in;
- input [8:0]drpaddr_in;
- input [15:0]drpdi_in;
- output [15:0]drpdo_out;
- input drpen_in;
- output drprdy_out;
- input drpwe_in;
- output gt_common_reset_out;
- input gt0_pll0refclklost_in;
- input quad1_common_lock_in;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- output tx_out_clk;
- input pll_not_locked;
-endmodule
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/doc/aurora_8b10b_v11_1_changelog.txt b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/doc/aurora_8b10b_v11_1_changelog.txt
deleted file mode 100755
index 7216ee36fdca3a760aa5afc7696e627329ff4e39..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/doc/aurora_8b10b_v11_1_changelog.txt
+++ /dev/null
@@ -1,294 +0,0 @@
-2019.2:
- * Version 11.1 (Rev. 8)
- * Revision change in one or more subcores
-
-2019.1.3:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1.2:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1.1:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1:
- * Version 11.1 (Rev. 7)
- * General: Added support for AKINTEX7 devices
- * Revision change in one or more subcores
-
-2018.3.1:
- * Version 11.1 (Rev. 6)
- * No changes
-
-2018.3:
- * Version 11.1 (Rev. 6)
- * General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
- * General: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
- * Revision change in one or more subcores
-
-2018.2:
- * Version 11.1 (Rev. 5)
- * Bug Fix: Fixed display only issue showing improper clock frequencies for tx_out_clk and sync_clk in IPI flow for GTP devices.
- * Revision change in one or more subcores
-
-2018.1:
- * Version 11.1 (Rev. 4)
- * Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection
- * Bug Fix: Fixed a bug that generated unexpected error messages during re-customization of IP in IP Integrator
- * Other: Added support for Artix-7 XA7A12TCPG238/CSG325 and XA7A25TCPG238/CSG325 devices
- * Revision change in one or more subcores
-
-2017.4:
- * Version 11.1 (Rev. 3)
- * General: Added support for CPG238 packages in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * Revision change in one or more subcores
-
-2017.3:
- * Version 11.1 (Rev. 2)
- * General: GTP attribute update in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * General: Standard CC logic is enabled after lane-up itself instead of waiting till channel-up condition
- * General: Added optional parameter C_DOUBLE_GTRXRESET to assert additional reset for handling errors during lane initialisation in duplex links with very high ppm differences
- * General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides
- * Revision change in one or more subcores
-
-2017.2:
- * Version 11.1 (Rev. 1)
- * Bug Fix: Unused gtrxresetseq drp signals removed from TX-simplex based designs
- * Other: UltraScale GT Wizard version upgrade.
-
-2017.1:
- * Version 11.1
- * New Feature: US GT Wizard Instance can be brought out of Aurora IP for UltraScale devices
- * Other: gt_powergood from US GT Wizard is made an output port on Aurora core when GT is inside Aurora IP
- * Other: gt_powergood from US GT Wizard is brought to gt wrapper in example design when the GT is in example design, outside Aurora IP
- * Revision change in one or more subcores
-
-2016.4:
- * Version 11.0 (Rev. 7)
- * General: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti devices
- * Revision change in one or more subcores
-
-2016.3:
- * Version 11.0 (Rev. 6)
- * Bug Fix: Fixed issue in failure due to floating point precision difference of gt_refclk in validate BD design in IPI
- * Bug Fix: Fixed TXDIFFCTRL and DMONITOROUT port widths for UltraScale devices in IP symbol
- * Feature Enhancement: Added Advanced RX GT Options selection in GUI
- * Other: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * Revision change in one or more subcores
-
-2016.2:
- * Version 11.0 (Rev. 5)
- * Fixed Artix7 periodic channel up toggle issue
- * Revision change in one or more subcores
-
-2016.1:
- * Version 11.0 (Rev. 4)
- * Fixed preserving Equalizer selection issue when additional transceiver ports option is enabled
- * Adjusted line rate and associated frequency limits for -1,-1H,1HV,-1L,-1LV, -2LV speed grade devices to match UltraScale FPGAs Data Sheet
- * Revision change in one or more subcores
-
-2015.4.2:
- * Version 11.0 (Rev. 3)
- * No changes
-
-2015.4.1:
- * Version 11.0 (Rev. 3)
- * No changes
-
-2015.4:
- * Version 11.0 (Rev. 3)
- * Added support for new speedgrades of XQ7K325T and XQ7K410T devices
- * Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices
- * Added support for new speedgrade of XQ7A050T, XQ7A100T and XQ7A200T devices
- * Revision change in one or more subcores
-
-2015.3:
- * Version 11.0 (Rev. 2)
- * Updated RTL to fix CDC warnings
- * Added support for UltraScale+ devices
- * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
-
-2015.2.1:
- * Version 11.0 (Rev. 1)
- * No changes
-
-2015.2:
- * Version 11.0 (Rev. 1)
- * Added support for XQ7VX690T, XQ7Z045 and XQ7Z100 devices
- * BUFG removed on DRP Clock input
- * TXPMARESETDONE used in rxstartupfsm for GTP RX-onlySimplex configuration
- * set_false_path constrain on synchronizers updated
-
-2015.1:
- * Version 11.0
- * Added support for 7 Series devices with FFV and FBV Pb-Free RoHs package
- * Added txinhibit and pcsrsvdin optional transceiver control and status ports
- * Both reset and gt_reset ports made asynchronous to the core
- * Standard CC module made part of IP, do_cc and warn_cc ports removed
- * Flow control ports grouped into AXI4 Stream interfaces
- * Control and status ports are grouped as display interfaces
- * Added support for single ended clocking option to INIT_CLK and GTREFCLK
- * Added support for contiguous lane selection for Ultrascale devices
- * CRC resource utilization optimized
- * GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator
- * Line rate value restricted to 4 decimal digits for Ultrascale devices
- * INIT clock frequency value restricted to 6 decimal digits
-
-2014.4.1:
- * Version 10.3 (Rev. 2)
- * Ultrascale GT Wizard version updated
-
-2014.4:
- * Version 10.3 (Rev. 1)
- * Added support for new XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices
- * Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices
- * Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices
- * BUFG added to DRP Clock input
- * Line rate range for -2L speed grade 1.0V Artix devices updated to 6.25Gbps
- * Location constraint changed for Xilinx Evaluation platform boards
-
-2014.3:
- * Version 10.3
- * Ultrascale GT Wizard version updated
- * Added support for new Ultrascale devices
- * Added support for XQ7A50 devices
- * Added support for XA7Z030 devices
- * Added support for user configurable DRP clock and INIT clock through IP GUI
- * Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup
- * set_max_delay constrain changed to set_false_path constrains to destination flops
- * XDCs compliant with updated timing constraining guidelines
- * Added support for Xilinx Evaluation platform boards
- * User selectable option enabled for GT DRP interface in IPI systems
- * Added support for auto propagate to INIT and DRP clock in IPI systems
- * Fixed gt_dmonitorout_out data width mismatch issue for Zynq devices
- * Differential INIT clock input added to Ultrascale example design
- * Addressed CPLL power down circuit requirement for 7 series Transceivers - refer AR
- * GT startup fsms updated to be complain with 7 Series GT Wizard
- * Addressed update to GTH/GTP Production RX reset sequence implementation- refer AR
- * Parameter declaration issue with IES simulator addressed
-
-2014.2:
- * Version 10.2 (Rev. 1)
- * Ultrascale GT Wizard version change
- * Added support for XQ7Z045 RF900 devices
- * Fixed hold violation timing issues in Ultrascale device based designs
- * Updated channel bonding levels logic for >= 13 lanes in 4 byte mode
- * Fixed gt0_dmonitorout_out port width for GTX devices in transceiver debug ports
- * Free running INIT CLK is connected to VIO core in example design
- * Fixed latch inference issue in crc modules for VHDL designs
- * Updated CLK_COR_MIN_LAT and CLK_COR_MAX_LAT values for 16-GT (GTHE3_CHANNEL) in Ultrascale device
-
-2014.1:
- * Version 10.2
- * Added support for Ultrascale devices
- * Added support for XC7Z015, XC7A50T, XC7A35T devices
- * Added support for automotive aartix XA7A35, XA7A50T, XA7A75T & XA7A100T devices
- * Enhanced support for IP Integrator
- * Added Little endian support for data & flow control interfaces as non-default GUI selectable option
- * Fixed VHDL syntax issue on rxpmaresetdone_t signal for 7-series based designs
- * Updated OOC XDC with all the available clocks for the selected IP configuration
- * Fixed TXCRC and RXCRC modules to operate upon valid data and report correct CRC status
- * Updated core reset logic with tx_lock synchronization
- * Updated the simplex timer values for 7-series production silicon logic updates
- * Updated the hot-plug logic to handle clock domain crossing efficiently
- * Added recovery mechanism for channel bonding failure
-
-2013.4:
- * Version 10.1
- * Increased the number of optional transceiver control and status ports
-
-2013.3:
- * Version 10.0
- * Added support for XC7A75T device
- * Added startup FSM integration for 7-series GT reset sequence
- * Added GUI option to include or exclude Vivado Labtools support for debug
- * Updated line rate for A7 wire bond package devices for speed grade -2 and -3
- * Added GUI option to include or exclude shareable logic resources in the core. For details, refer to Migrating section of Product Guide - pg046-aurora-8b10b.pdf
- * Added optional transceiver control and status ports - Refer to pg046-aurora-8b10b.pdf
- * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
- * Reduced warnings in synthesis and simulation
- * Added support for Cadence IES and Synopsys VCS simulators
- * Added support for IP Integrator level 0
-
-2013.2:
- * Version 9.1
- * Artix-7 GTP and Virtex-7 GTH production attributes updates
- * XDC constraints processing order changed
- * Update for UFC packet drop in back to back data transfer
- * XQ7Z030-RB484 device support
-
-2013.1:
- * Version 9.0
- * Lower case IP level ports
- * Hot-plug timer update
- * CDC fixes
- * New reset sequence for GTRXRESET in Artix-7 GTP Production silicon
- * New reset sequence for GTRXRESET in Virtex-7 GTH Production silicon
- * Out-of-context (OOC) flow support
- * Zynq-7000 family support
-
-2012.4:
- * Version 8.3 (Rev. 1)
- * Artix-7 IES silicon support
- * Autoupgrade feature
-
-2012.3:
- * Version 8.3
- * Artix-7 family support
-
-2012.2:
- * Version 8.2
- * Virtex-7 HT device support
- * CRC feature addition
- * Hot-plug support for 7-series
- * XSIM simulator support
- * Native Vivado release
-
-(c) Copyright 2010 - 2019 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.dcp b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.dcp
deleted file mode 100644
index 42c94ffe4293ab4c9dc0f05d4b23df5822bcc5dc..0000000000000000000000000000000000000000
Binary files a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.dcp and /dev/null differ
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.vhd
deleted file mode 100644
index 84cbd0c7925c7644d3b4fbcb2cf74b41ed9ea2d0..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.vhd
+++ /dev/null
@@ -1,346 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
-------------------------------------------------------------------------------/
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_misc.all;
- use IEEE.numeric_std.all;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
-
-entity north_channel is
- port (
- -- AXI TX Interface
-
- s_axi_tx_tdata : in std_logic_vector(0 to 31);
-
- s_axi_tx_tvalid : in std_logic;
- s_axi_tx_tready : out std_logic;
-
- s_axi_tx_tkeep : in std_logic_vector(0 to 3);
-
- s_axi_tx_tlast : in std_logic;
-
-
- -- AXI RX Interface
-
- m_axi_rx_tdata : out std_logic_vector(0 to 31);
-
- m_axi_rx_tvalid : out std_logic;
-
- m_axi_rx_tkeep : out std_logic_vector(0 to 3);
-
- m_axi_rx_tlast : out std_logic;
-
-
- -- User Flow Control TX Interface
- s_axi_ufc_tx_tvalid : in std_logic;
-
- s_axi_ufc_tx_tdata : in std_logic_vector(0 to 2);
- s_axi_ufc_tx_tready : out std_logic;
-
-
- -- User Flow Control RX Inteface
-
- m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31);
- m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3);
- m_axi_ufc_rx_tvalid : out std_logic;
- m_axi_ufc_rx_tlast : out std_logic;
-
-
-
- -- GT Serial I/O
- rxp : in std_logic_vector(0 downto 0);
- rxn : in std_logic_vector(0 downto 0);
-
- txp : out std_logic_vector(0 downto 0);
- txn : out std_logic_vector(0 downto 0);
-
- -- GT Reference Clock Interface
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
-
- frame_err : out std_logic;
- hard_err : out std_logic;
- soft_err : out std_logic;
- channel_up : out std_logic;
- lane_up : out std_logic_vector(0 downto 0);
-
-
-
-
- -- System Interface
- user_clk : in std_logic;
- sync_clk : in std_logic;
- reset : in std_logic;
-
- power_down : in std_logic;
- loopback : in std_logic_vector(2 downto 0);
- gt_reset : in std_logic;
- tx_lock : out std_logic;
- sys_reset_out : out std_logic;
- init_clk_in : in std_logic;
- tx_resetdone_out : out std_logic;
- rx_resetdone_out : out std_logic;
- link_reset_out : out std_logic;
-
- --DRP Ports
-
- drpclk_in : in std_logic;
- drpaddr_in : in std_logic_vector(8 downto 0);
- drpdi_in : in std_logic_vector(15 downto 0);
- drpdo_out : out std_logic_vector(15 downto 0);
- drpen_in : in std_logic;
- drprdy_out : out std_logic;
- drpwe_in : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- tx_out_clk : out std_logic;
- pll_not_locked : in std_logic
-
- );
-
-end north_channel;
-
-
-architecture STRUCTURE of north_channel is
- attribute core_generation_info : string;
- attribute core_generation_info of STRUCTURE : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- component north_channel_core
- port (
- -- TX Stream Interface
- S_AXI_TX_TDATA : in std_logic_vector(0 to 31);
- S_AXI_TX_TKEEP : in std_logic_vector(0 to 3);
- S_AXI_TX_TVALID : in std_logic;
- S_AXI_TX_TREADY : out std_logic;
- S_AXI_TX_TLAST : in std_logic;
-
- -- RX Stream Interface
- M_AXI_RX_TDATA : out std_logic_vector(0 to 31);
- M_AXI_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_RX_TVALID : out std_logic;
- M_AXI_RX_TLAST : out std_logic;
- -- User Flow Control TX Interface
-
- S_AXI_UFC_TX_REQ : in std_logic;
- S_AXI_UFC_TX_MS : in std_logic_vector(0 to 2);
- S_AXI_UFC_TX_ACK : out std_logic;
-
- -- User Flow Control RX Inteface
-
- M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31);
- M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_UFC_RX_TVALID : out std_logic;
- M_AXI_UFC_RX_TLAST : out std_logic;
-
- -- GTX Serial I/O
- RXP : in std_logic;
- RXN : in std_logic;
- TXP : out std_logic;
- TXN : out std_logic;
-
- -- GT Reference Clock Interface
-
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
- HARD_ERR : out std_logic;
- SOFT_ERR : out std_logic;
-
- -- Status
- CHANNEL_UP : out std_logic;
- LANE_UP : out std_logic;
-
-
- FRAME_ERR : out std_logic;
-
-
-
- -- Clock Compensation Control Interface
-
- -- System Interface
-
- USER_CLK : in std_logic;
- SYNC_CLK : in std_logic;
- GT_RESET : in std_logic;
- RESET : in std_logic;
- sys_reset_out : out std_logic;
- POWER_DOWN : in std_logic;
- LOOPBACK : in std_logic_vector(2 downto 0);
- TX_OUT_CLK : out std_logic;
- INIT_CLK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- TX_RESETDONE_OUT : out std_logic;
- RX_RESETDONE_OUT : out std_logic;
- LINK_RESET_OUT : out std_logic;
-
-
- drpclk_in : in std_logic;
- DRPADDR_IN : in std_logic_vector(8 downto 0);
- DRPDI_IN : in std_logic_vector(15 downto 0);
- DRPDO_OUT : out std_logic_vector(15 downto 0);
- DRPEN_IN : in std_logic;
- DRPRDY_OUT : out std_logic;
- DRPWE_IN : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- TX_LOCK : out std_logic
- );
-
- end component;
-
-begin
-
- --*********************************Main Body of Code**********************************
-
- U0 : north_channel_core
- port map (
- -- AXI TX Interface
- s_axi_tx_tdata => s_axi_tx_tdata,
- s_axi_tx_tkeep => s_axi_tx_tkeep,
- s_axi_tx_tvalid => s_axi_tx_tvalid,
- s_axi_tx_tlast => s_axi_tx_tlast,
- s_axi_tx_tready => s_axi_tx_tready,
-
- -- AXI RX Interface
- m_axi_rx_tdata => m_axi_rx_tdata,
- m_axi_rx_tkeep => m_axi_rx_tkeep,
- m_axi_rx_tvalid => m_axi_rx_tvalid,
- m_axi_rx_tlast => m_axi_rx_tlast,
-
- -- User Flow Control TX Interface
- s_axi_ufc_tx_req => s_axi_ufc_tx_tvalid,
- s_axi_ufc_tx_ms => s_axi_ufc_tx_tdata,
- s_axi_ufc_tx_ack => s_axi_ufc_tx_tready,
-
- -- User Flow Control RX Inteface
- m_axi_ufc_rx_tdata => m_axi_ufc_rx_tdata,
- m_axi_ufc_rx_tkeep => m_axi_ufc_rx_tkeep,
- m_axi_ufc_rx_tvalid => m_axi_ufc_rx_tvalid,
- m_axi_ufc_rx_tlast => m_axi_ufc_rx_tlast,
-
- -- GT Serial I/O
- rxp => rxp(0),
- rxn => rxn(0),
- txp => txp(0),
- txn => txn(0),
-
- -- GT Reference Clock Interface
- gt_refclk1 => gt_refclk1,
- -- Error Detection Interface
- frame_err => frame_err,
-
- -- Error Detection Interface
- hard_err => hard_err,
- soft_err => soft_err,
-
- -- Status
- channel_up => channel_up,
- lane_up => lane_up(0),
-
-
-
-
- -- System Interface
- user_clk => user_clk,
- sync_clk => sync_clk,
- reset => reset,
- sys_reset_out => sys_reset_out,
- power_down => power_down,
- loopback => loopback,
- gt_reset => gt_reset,
- tx_lock => tx_lock,
- init_clk_in => init_clk_in,
- pll_not_locked => pll_not_locked,
- tx_resetdone_out => tx_resetdone_out,
- rx_resetdone_out => rx_resetdone_out,
- link_reset_out => link_reset_out,
- drpclk_in => drpclk_in,
- drpaddr_in => drpaddr_in,
- drpen_in => drpen_in,
- drpdi_in => drpdi_in,
- drprdy_out => drprdy_out,
- drpdo_out => drpdo_out,
- drpwe_in => drpwe_in,
---------------------{
- gt_common_reset_out => gt_common_reset_out,
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in => gt0_pll0refclklost_in,
- quad1_common_lock_in => quad1_common_lock_in,
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
---____________________________COMMON PORTS_______________________________}
---------------------}
- tx_out_clk => tx_out_clk
-
- );
-
- end STRUCTURE;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xdc b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xdc
deleted file mode 100644
index 8400a85e0e1b6179d35256ca3aebea7cb8a6f2d0..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xdc
+++ /dev/null
@@ -1,67 +0,0 @@
-
-################################################################################
-##
-## (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-## north_channel.xdc generated for xc7z015-clg485-2 device
-# TXOUTCLK Constraint: Value is selected based on the line rate (5.0 Gbps) and lane width (4-Byte)
-create_clock -period 4.0 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt_wrapper_i*north_channel_multi_gt_i*gt0_north_channel_i*gtpe2_i*}]]
-
-
-#### CDC Path #####
-set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *north_channel_cdc_to*}]]
-
-
-####################### GT reference clock LOC (For use in top level design) #######################
-# set_property LOC V5 [get_ports GTPQ0_N]
-# set_property LOC U5 [get_ports GTPQ0_P]
-
-############################### GT LOC (For use in top level design) ###################################
-# set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells aurora_module_i/north_channel_i/U0/gt_wrapper_i/north_channel_multi_gt_i/gt0_north_channel_i/gtpe2_i]
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xml b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xml
deleted file mode 100644
index 4c5ed9a6de9d9b5b733804caf352e4118fba6d46..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xml
+++ /dev/null
@@ -1,41348 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>customized_ip</spirit:library>
- <spirit:name>north_channel</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>USER_DATA_S_AXI_TX</spirit:name>
- <spirit:displayName>USER_DATA_S_AXI_TX</spirit:displayName>
- <spirit:description>User data AXI-Stream TX interface</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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- <spirit:slave/>
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- </spirit:logicalPort>
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- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TKEEP</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_tx_tkeep</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TLAST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_tx_tlast</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
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- <spirit:name>s_axi_tx_tready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
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- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
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- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
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- <spirit:name>TDATA_NUM_BYTES</spirit:name>
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- <spirit:vendorExtensions>
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- <spirit:name>TDEST_WIDTH</spirit:name>
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- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.user_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>sync_clk</spirit:name>
- <spirit:displayName>sync_clk</spirit:displayName>
- <spirit:description>sync_clk frequency depends on line rate and user_clk should be shorted with sync_clk</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>sync_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sync_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>init_clk_out</spirit:name>
- <spirit:displayName>init_clk_out</spirit:displayName>
- <spirit:description>200 MHz independent system clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_BUSIF">gt_reset_out</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.init_clk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>sys_reset_out</spirit:name>
- <spirit:displayName>sys_reset_out</spirit:displayName>
- <spirit:description>system reset available when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>sys_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.SYS_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_reset</spirit:name>
- <spirit:displayName>gt_reset</spirit:displayName>
- <spirit:description>GT reset sampled in INIT_CLK and asserted for 6 clock cycles and after assertion of reset</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_reset_out</spirit:name>
- <spirit:displayName>gt_reset_out</spirit:displayName>
- <spirit:description>GT reset generated when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_reset_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>link_reset_out</spirit:name>
- <spirit:displayName>link_reset_out</spirit:displayName>
- <spirit:description>Link reset is generated when IP is not receiving valid data for longer time</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>link_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.LINK_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.LINK_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.link_reset_out" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))!="TX-only_Simplex"">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>init_clk_in</spirit:name>
- <spirit:displayName>init_clk_in</spirit:displayName>
- <spirit:description>Free running System clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_BUSIF">gt_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.init_clk_in" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true)) or ((spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="kintexu") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="virtexu") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="zynquplus") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="kintexuplus")) or (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=true))">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk1_out</spirit:name>
- <spirit:displayName>gt_refclk1_out</spirit:displayName>
- <spirit:description>GT REFCLK1 when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk1_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk2_out</spirit:name>
- <spirit:displayName>gt_refclk2_out</spirit:displayName>
- <spirit:description>GT REFCLK2 when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk2_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None") and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk1</spirit:name>
- <spirit:displayName>~</spirit:displayName>
- <spirit:description>GT REFCLK1 when shared logic is in example design</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk1" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.c_gtwiz_out'))=false)) or (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=true))">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk2</spirit:name>
- <spirit:displayName>~</spirit:displayName>
- <spirit:description>GT REFCLK2 when shared logic is in example design</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk2" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.c_gtwiz_out'))=false)) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None")) or ((spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None") and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=true)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>GT_DIFF_REFCLK1</spirit:name>
- <spirit:displayName>GT_DIFF_REFCLK1</spirit:displayName>
- <spirit:description>Differential GT REFCLK1 and depends on line rate</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GT_DIFF_REFCLK1" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>GT_DIFF_REFCLK2</spirit:name>
- <spirit:displayName>GT_DIFF_REFCLK2</spirit:displayName>
- <spirit:description>Differential GT REFCLK2 and depends on line rate</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GT_DIFF_REFCLK2" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None")) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>INIT_DIFF_CLK</spirit:name>
- <spirit:displayName>INIT_DIFF_CLK</spirit:displayName>
- <spirit:description>200 MHz independent system clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.ASSOCIATED_RESET">gt_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INIT_DIFF_CLK" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rx_system_reset</spirit:name>
- <spirit:displayName>rx_system_reset</spirit:displayName>
- <spirit:description>Aurora IP reset for Simplex-RX config</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rx_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.RX_SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RX_SYSTEM_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_system_reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))="RX-only_Simplex")">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>tx_system_reset</spirit:name>
- <spirit:displayName>tx_system_reset</spirit:displayName>
- <spirit:description>Aurora IP reset for Simplex-TX config</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>tx_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_system_reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))="TX-only_Simplex")">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_drp_clk_in</spirit:name>
- <spirit:displayName>gt_drp_clk_in</spirit:displayName>
- <spirit:description>DRP clock for 7-series transceiver</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>drpclk_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_BUSIF">GT0_DRP_IF:GT1_DRP_IF:GT2_DRP_IF:GT3_DRP_IF:GT4_DRP_IF:GT5_DRP_IF:GT6_DRP_IF:GT7_DRP_IF:GT8_DRP_IF:GT9_DRP_IF:GT10_DRP_IF:GT11_DRP_IF:GT12_DRP_IF:GT13_DRP_IF:GT14_DRP_IF:GT15_DRP_IF</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_RESET"/>
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- <spirit:description>Transceiver debug interface for GT1</spirit:description>
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- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="transceiver_debug_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>cplllock</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_cplllock_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>dmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_dmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescandataerror</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_eyescandataerror_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescanreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_eyescanreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescantrigger</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_eyescantrigger_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxbufreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbyteisaligned</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxbyteisaligned_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxcdrhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxcdrovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcommadet</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxcommadet_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdfelpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxdfelpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdisperr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_disp_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmen</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmen_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmhfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmhfovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmlfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmlfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorsel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxmonitorsel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxnotintable</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_not_in_table_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpcsreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxpcsreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmareset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxpmareset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmaresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxpmaresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbscntreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxprbscntreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbserr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxprbserr_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbssel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxprbssel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxrealign</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_realign_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_tx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispmode</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txchardispmode_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispval</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txchardispval_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txdiffctrl</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txdiffctrl_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txinhibit</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txinhibit_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txmaincursor</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txmaincursor_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpcsreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpcsreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpmareset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpmareset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpolarity</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpolarity_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpostcursor</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpostcursor_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txprbsforceerr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txprbsforceerr_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txprbssel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txprbssel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txprecursor</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txprecursor_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.TRANSCEIVER_DEBUG1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true) and (spirit:decode(id('MODELPARAM_VALUE.TransceiverControl'))=true) and ((spirit:decode(id('MODELPARAM_VALUE.C_AURORA_LANES')))>1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>TRANSCEIVER_DEBUG2</spirit:name>
- <spirit:displayName>TRANSCEIVER_DEBUG2</spirit:displayName>
- <spirit:description>Transceiver debug interface for gt2</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="transceiver_debug" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="transceiver_debug_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>cplllock</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_cplllock_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>dmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_dmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescandataerror</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_eyescandataerror_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescanreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_eyescanreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescantrigger</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_eyescantrigger_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxbufreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbyteisaligned</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxbyteisaligned_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxcdrhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxcdrovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcommadet</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxcommadet_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdfelpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxdfelpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdisperr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_disp_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmen</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmen_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmhfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmhfovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmlfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmlfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorsel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxmonitorsel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxnotintable</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_not_in_table_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpcsreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxpcsreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmareset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxpmareset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmaresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxpmaresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbscntreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxprbscntreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbserr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxprbserr_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbssel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxprbssel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxrealign</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_realign_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_tx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispmode</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txchardispmode_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispval</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txchardispval_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txdiffctrl</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txdiffctrl_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
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- <spirit:name>rxnotintable</spirit:name>
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- <spirit:name>rxprbscntreset</spirit:name>
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- <spirit:name>rxprbssel</spirit:name>
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- <spirit:name>gt15_rxprbssel_in</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>rxrealign</spirit:name>
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- <spirit:name>gt15_rx_realign_out</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>rxresetdone</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txbuferr</spirit:name>
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- <spirit:name>gt15_tx_buf_err_out</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txbufstatus</spirit:name>
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- <spirit:name>gt15_txbufstatus_out</spirit:name>
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- <spirit:name>txchardispmode</spirit:name>
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- <spirit:name>txchardispval</spirit:name>
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- <spirit:name>gt15_txchardispval_in</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txdiffctrl</spirit:name>
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- <spirit:name>txinhibit</spirit:name>
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- <spirit:name>gt15_txinhibit_in</spirit:name>
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- <spirit:name>txmaincursor</spirit:name>
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- <spirit:name>txpcsreset</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txpmareset</spirit:name>
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- <spirit:name>txpolarity</spirit:name>
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- <spirit:name>txprbsforceerr</spirit:name>
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- <spirit:name>txprbssel</spirit:name>
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- <spirit:name>txresetdone</spirit:name>
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- <spirit:name>gt15_txresetdone_out</spirit:name>
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- <spirit:name>RX_SIDEBAND_SIGNALS</spirit:name>
- <spirit:displayName>RX_SIDEBAND_SIGNALS</spirit:displayName>
- <spirit:description>RX SIDEBAND Signals must be connected with TX_SIDEBAND_SIGNALS</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="SIDEBAND_Pins_RX" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="SIDEBAND_Pins_RX_rtl" spirit:version="1.0"/>
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- <spirit:name>rx_aligned</spirit:name>
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- <spirit:name>rx_reset</spirit:name>
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- <spirit:name>rx_verify</spirit:name>
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- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RX_SIDEBAND_SIGNALS" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))!="Duplex") and (spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))!="TX-only_Simplex") and (spirit:decode(id('MODELPARAM_VALUE.BACKCHANNEL_MODE'))!="Timer"))">false</xilinx:isEnabled>
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- <spirit:name>CORE_STATUS</spirit:name>
- <spirit:displayName>CORE_STATUS</spirit:displayName>
- <spirit:description>Aurora Core Status pins</spirit:description>
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- <spirit:name>C_REFCLK_LOC_P</spirit:name>
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- <spirit:name>c_column_used</spirit:name>
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- <spirit:name>c_ucolumn_used</spirit:name>
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- <spirit:name>c_xpackage</spirit:name>
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- <spirit:name>c_xspeedgrade</spirit:name>
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- <spirit:name>c_lane_width</spirit:name>
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- <spirit:name>C_active_transceiverquads</spirit:name>
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- <spirit:name>c_stream</spirit:name>
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- <spirit:name>backchannel_mode</spirit:name>
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- <spirit:name>c_line_rate</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_line_rate">50000</spirit:value>
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- <spirit:name>c_refclk_frequency</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_refclk_frequency">125000</spirit:value>
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- <spirit:name>cc_refclk_frequency</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.cc_refclk_frequency">125.000</spirit:value>
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- <spirit:name>c_init_clk</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_init_clk">125.0</spirit:value>
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- <spirit:name>drp_freq</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.drp_freq">125.0</spirit:value>
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- <spirit:name>c_gt_loc_1</spirit:name>
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- <spirit:name>c_gt_loc_2</spirit:name>
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- <spirit:name>c_gt_loc_3</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_3">X</spirit:value>
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- <spirit:name>c_gt_loc_4</spirit:name>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_6">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_7">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_8">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_26">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_27">X</spirit:value>
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- <spirit:name>c_gt_loc_31</spirit:name>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_33">X</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_35">X</spirit:value>
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- <spirit:name>c_gt_loc_36</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc_36">X</spirit:value>
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- <spirit:modelParameter spirit:dataType="boolean">
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- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_use_byteswap">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>c_rxoutdiv</spirit:name>
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- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>c_txoutdiv</spirit:name>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.user_interface">AXI_4_Streaming</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
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- <spirit:modelParameter spirit:dataType="boolean">
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- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SINGLEEND_GTREFCLK">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="boolean">
- <spirit:name>C_DOUBLE_GTRXRESET</spirit:name>
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- <spirit:name>C_DOCCPORT_ENABLE</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOCCPORT_ENABLE">false</spirit:value>
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- <spirit:modelParameter spirit:dataType="string">
- <spirit:name>is_board</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.is_board">None</spirit:value>
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- <spirit:modelParameter spirit:dataType="integer">
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USDRPADDR_WIDTH">8</spirit:value>
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- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.rx_termination">PROGRAMMABLE</spirit:value>
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- <spirit:name>rx_ppm_offset</spirit:name>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:name>north_channel/src/north_channel_rx_ll_deframer.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:name>north_channel/src/north_channel_rx_ll_ufc_datapath.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:file>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:file>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_14" spirit:choiceRef="choice_list_9bee990d" spirit:order="25">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_14">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_13</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_13" spirit:choiceRef="choice_list_9bee990d" spirit:order="24">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_13">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_12</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_12" spirit:choiceRef="choice_list_9bee990d" spirit:order="23">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_12">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_11</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_11" spirit:choiceRef="choice_list_9bee990d" spirit:order="22">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_11">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_10</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_10" spirit:choiceRef="choice_list_9bee990d" spirit:order="21">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_10">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_9</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_9" spirit:choiceRef="choice_list_9bee990d" spirit:order="20">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_9">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_8</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_8" spirit:choiceRef="choice_list_9bee990d" spirit:order="19">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_8">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_7</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_7" spirit:choiceRef="choice_list_9bee990d" spirit:order="18">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_7">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_6</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_6" spirit:choiceRef="choice_list_9bee990d" spirit:order="17">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_6">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_5</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_5" spirit:choiceRef="choice_list_9bee990d" spirit:order="16">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_5">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_4</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_4" spirit:choiceRef="choice_list_ddf7a1a5" spirit:order="15">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_4">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_3</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_3" spirit:choiceRef="choice_list_ddf7a1a5" spirit:order="14">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_3">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_2</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_2" spirit:choiceRef="choice_list_628aac54" spirit:order="13">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_2">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_LOC_1</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_LOC_1" spirit:choiceRef="choice_list_9bee990d" spirit:order="12">X</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_LOC_1">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_CLOCK_1</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_CLOCK_1" spirit:choiceRef="choice_list_852ec6a0" spirit:order="60">GTPQ0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_CLOCK_1">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GT_CLOCK_2</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_GT_CLOCK_2" spirit:choiceRef="choice_list_6f5507b7" spirit:order="61">None</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GT_CLOCK_2">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_CHIPSCOPE</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CHIPSCOPE" spirit:order="62">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_CHIPSCOPE">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_START_QUAD</spirit:name>
- <spirit:displayName>Starting GT Quad</spirit:displayName>
- <spirit:description>Select the quad from which lane assignment begins</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_START_QUAD" spirit:choiceRef="choice_list_949abb3f" spirit:order="63">X0Y0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_START_QUAD">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_START_LANE</spirit:name>
- <spirit:displayName>Starting GT Lane</spirit:displayName>
- <spirit:description>Select the starting lane location.Lane Assignment will begin from this Lane of the Quad selected earlier.</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_START_LANE" spirit:choiceRef="choice_list_949abb3f" spirit:order="64">X0Y0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_START_LANE">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_REFCLK_SOURCE</spirit:name>
- <spirit:displayName>GT Refclk Selection</spirit:displayName>
- <spirit:description>Select a reference clock input</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_REFCLK_SOURCE" spirit:choiceRef="choice_list_4d962a2a" spirit:order="65">none</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_REFCLK_SOURCE">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SINGLEEND_INITCLK</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SINGLEEND_INITCLK" spirit:order="1000">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.SINGLEEND_INITCLK">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SINGLEEND_GTREFCLK</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SINGLEEND_GTREFCLK" spirit:order="1001">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.SINGLEEND_GTREFCLK">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_SCRAMBLER</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_SCRAMBLER" spirit:order="63">true</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_SCRAMBLER">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_CRC</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CRC" spirit:order="64">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_CRC">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SupportLevel</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SupportLevel" spirit:choiceRef="choice_pairs_27553a04" spirit:order="65">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.SupportLevel">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TransceiverControl</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.TransceiverControl" spirit:order="66">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TransceiverControl">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_DOUBLE_GTRXRESET</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DOUBLE_GTRXRESET" spirit:order="167">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DOUBLE_GTRXRESET">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_DOCCPORT_ENABLE</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DOCCPORT_ENABLE" spirit:order="167">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DOCCPORT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_EXAMPLE_SIMULATION</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXAMPLE_SIMULATION" spirit:order="67">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_EXAMPLE_SIMULATION">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_USE_BYTESWAP</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_BYTESWAP" spirit:order="67">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_BYTESWAP">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CHANNEL_ENABLE</spirit:name>
- <spirit:displayName>Enable channel</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CHANNEL_ENABLE" spirit:order="68">X0Y0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CHANNEL_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_DRP_IF</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_DRP_IF" spirit:order="68">true</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DRP_IF">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INS_LOSS_NYQ</spirit:name>
- <spirit:displayName>Insertion loss at Nyquist (dB)</spirit:displayName>
- <spirit:description>Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB</spirit:description>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.INS_LOSS_NYQ" spirit:order="69" spirit:minimum="0" spirit:maximum="4294967295">14</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_EQ_MODE</spirit:name>
- <spirit:displayName>Equalization mode</spirit:displayName>
- <spirit:description>Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes.</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_EQ_MODE" spirit:choiceRef="choice_pairs_aa541099" spirit:order="70">AUTO</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_COUPLING</spirit:name>
- <spirit:displayName>Link coupling</spirit:displayName>
- <spirit:description>Select the link coupling</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COUPLING" spirit:choiceRef="choice_list_24871ac1" spirit:order="71">AC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_TERMINATION</spirit:name>
- <spirit:displayName>Termination</spirit:displayName>
- <spirit:description>Select the receiver termination</spirit:description>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_TERMINATION" spirit:choiceRef="choice_pairs_1040277f" spirit:order="72">PROGRAMMABLE</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_TERMINATION_PROG_VALUE</spirit:name>
- <spirit:displayName>Programmable termination voltage (mV)</spirit:displayName>
- <spirit:description>Select the termination voltage (in mV) when in programmable mode</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_TERMINATION_PROG_VALUE" spirit:choiceRef="choice_list_f490bbca" spirit:order="73">800</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>RX_PPM_OFFSET</spirit:name>
- <spirit:displayName>PPM offset between receiver and transmitter</spirit:displayName>
- <spirit:description>Specify the PPM offset between received data and transmitted data</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PPM_OFFSET" spirit:order="74" spirit:minimum="0" spirit:maximum="1250" spirit:rangeType="long">200</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_GTWIZ_OUT</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GTWIZ_OUT" spirit:order="75">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GTWIZ_OUT">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:coreExtensions>
- <xilinx:displayName>Aurora 8B10B</xilinx:displayName>
- <xilinx:coreRevision>8</xilinx:coreRevision>
- <xilinx:configElementInfos>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TKEEP" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TREADY" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.HAS_TSTRB" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TDEST_WIDTH" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TID_WIDTH" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TUSER_WIDTH" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY" xilinx:valueSource="auto"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
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diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_gt.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_gt.vhd
deleted file mode 100644
index 9b0083e08b6ecbf60b312b51c22df615eff762a9..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_gt.vhd
+++ /dev/null
@@ -1,960 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
---***************************** Entity Declaration ****************************
-
-entity north_channel_gt is
-generic
-(
- -- Simulation attributes
- GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
- TXSYNC_OVRD_IN : bit := '0';
- TXSYNC_MULTILANE_IN : bit := '0'
-);
-port
-(
- STABLE_CLOCK : IN std_logic; -- System Clock
- RST_IN : in std_logic; -- Connect to System Reset
- DRP_BUSY_OUT : out std_logic; -- Indicates that the DRP bus is not accessible to the User
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- DRPADDR_IN : in std_logic_vector(8 downto 0);
- DRPCLK_IN : in std_logic;
- DRPDI_IN : in std_logic_vector(15 downto 0);
- DRPDO_OUT : out std_logic_vector(15 downto 0);
- DRPEN_IN : in std_logic;
- DRPRDY_OUT : out std_logic;
- DRPWE_IN : in std_logic;
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK_IN : in std_logic;
- PLL0REFCLK_IN : in std_logic;
- PLL1CLK_IN : in std_logic;
- PLL1REFCLK_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK_IN : in std_logic_vector(2 downto 0);
- RXPD_IN : in std_logic_vector(1 downto 0);
- TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- eyescanreset_in : in std_logic;
- RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- rxprbserr_out : out std_logic;
- rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- eyescandataerror_out : out std_logic;
- eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN_IN : in std_logic;
- GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
- rxbyteisaligned_out : out std_logic;
- RXBYTEREALIGN_OUT : out std_logic;
- rxcommadet_out : out std_logic;
- RXMCOMMAALIGNEN_IN : in std_logic;
- RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET_IN : in std_logic;
- rxpcsreset_in : in std_logic;
- rxpmareset_in : in std_logic;
- rxlpmreset_in : in std_logic;
- RXDATA_OUT : out std_logic_vector(31 downto 0);
- RXOUTCLK_OUT : out std_logic;
- RXUSRCLK_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRLOCK_OUT : out std_logic;
- RXLPMHFHOLD_IN : in std_logic;
- RXLPMLFHOLD_IN : in std_logic;
- rxlpmhfovrden_in : in std_logic;
- rxcdrhold_in : in std_logic;
- dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- rxbufreset_in : in std_logic;
- RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRESETDONE_OUT : out std_logic;
- RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- txpostcursor_in : in std_logic_vector(4 downto 0);
- txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- txchardispmode_in : in std_logic_vector(3 downto 0);
- txchardispval_in : in std_logic_vector(3 downto 0);
- TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET_IN : in std_logic;
- TXDATA_IN : in std_logic_vector(31 downto 0);
- TXOUTCLK_OUT : out std_logic;
- TXOUTCLKFABRIC_OUT : out std_logic;
- TXOUTCLKPCS_OUT : out std_logic;
- TXUSRCLK_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN_OUT : out std_logic;
- GTPTXP_OUT : out std_logic;
- txdiffctrl_in : in std_logic_vector(3 downto 0);
- txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- txpcsreset_in : in std_logic;
- txpmareset_in : in std_logic;
- txinhibit_in : in std_logic;
- TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- txpolarity_in : in std_logic
-
-);
-
-
-end north_channel_gt;
-
-architecture MAPPED of north_channel_gt is
-
---*************************** Component Declarations **************************
-component north_channel_gtrxreset_seq
- port (
- RST : IN std_logic;
- GTRXRESET_IN : IN std_logic;
- RXPMARESETDONE: IN std_logic;
- GTRXRESET_OUT : OUT std_logic;
- STABLE_CLOCK : IN std_logic;
-
- DRPCLK : IN std_logic;
- DRPADDR : OUT std_logic_vector(8 downto 0);
- DRPDO : IN std_logic_vector(15 downto 0);
- DRPDI : OUT std_logic_vector(15 downto 0);
- DRPRDY : IN std_logic;
- DRPEN : OUT std_logic;
- DRPWE : OUT std_logic;
- DRP_OP_DONE : OUT std_logic
-);
-end component;
---**************************** Signal Declarations ****************************
-
- -- ground and tied_to_vcc_i signals
- signal tied_to_ground_i : std_logic;
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
- signal tied_to_vcc_i : std_logic;
-
- signal rxpmaresetdone_t : std_logic;
- signal gtrxreset_out : std_logic;
- signal rxpmareset_out : std_logic;
- signal rxrate_out : std_logic_vector(2 downto 0);
- signal drp_op_done : std_logic;
- signal drp_pma_busy : std_logic;
- signal drp_rate_busy : std_logic;
- signal drp_busy_i1 : std_logic:= '0';
- signal drp_busy_i2 : std_logic:= '0';
- signal drpen_rst_t : std_logic;
- signal drpaddr_rst_t : std_logic_vector(8 downto 0);
- signal drpwe_rst_t : std_logic;
- signal drpdo_rst_t : std_logic_vector(15 downto 0);
- signal drpdi_rst_t : std_logic_vector(15 downto 0);
- signal drprdy_rst_t : std_logic;
- signal drpen_pma_t : std_logic;
- signal drpaddr_pma_t : std_logic_vector(8 downto 0);
- signal drpwe_pma_t : std_logic;
- signal drpdo_pma_t : std_logic_vector(15 downto 0);
- signal drpdi_pma_t : std_logic_vector(15 downto 0);
- signal drprdy_pma_t : std_logic;
- signal drpen_rate_t : std_logic;
- signal drpaddr_rate_t : std_logic_vector(8 downto 0);
- signal drpwe_rate_t : std_logic;
- signal drpdo_rate_t : std_logic_vector(15 downto 0);
- signal drpdi_rate_t : std_logic_vector(15 downto 0);
- signal drprdy_rate_t : std_logic;
- signal drpen_i : std_logic;
- signal drpaddr_i : std_logic_vector(8 downto 0);
- signal drpwe_i : std_logic;
- signal drpdo_i : std_logic_vector(15 downto 0);
- signal drpdi_i : std_logic_vector(15 downto 0);
- signal drprdy_i : std_logic;
-
- -- RX Datapath signals
- signal rxdata_i : std_logic_vector(31 downto 0);
-
- -- TX Datapath signals
- signal txdata_i : std_logic_vector(31 downto 0);
- signal rxdatavalid_float_i : std_logic;
-
---******************************** Main Body of Code***************************
-
-begin
-
- --------------------------- Static signal Assignments ---------------------
-
- tied_to_ground_i <= '0';
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');
- tied_to_vcc_i <= '1';
-
- ------------------- GT Datapath byte mapping -----------------
-
- -- The GT provides little endian data (first byte received on RXDATA(7 downto 0))
- RXDATA_OUT <= rxdata_i(31 downto 0);
-
- txdata_i <= (TXDATA_IN);
-
-
-
- ----------------------------- GTPE2 Instance --------------------------
-
- gtpe2_i : GTPE2_CHANNEL
- generic map
- (
-
- --_______________________ Simulation-Only Attributes ___________________
-
- SIM_RECEIVER_DETECT_PASS => ("TRUE"),
- SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
- SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
- SIM_VERSION => ("2.0"),
-
-
- ------------------RX Byte and Word Alignment Attributes---------------
- ALIGN_COMMA_DOUBLE => ("FALSE"),
- ALIGN_COMMA_ENABLE => ("1111111111"),
- ALIGN_COMMA_WORD => (2),
- ALIGN_MCOMMA_DET => ("TRUE"),
- ALIGN_MCOMMA_VALUE => ("1010000011"),
- ALIGN_PCOMMA_DET => ("TRUE"),
- ALIGN_PCOMMA_VALUE => ("0101111100"),
- SHOW_REALIGN_COMMA => ("TRUE"),
- RXSLIDE_AUTO_WAIT => (7),
- RXSLIDE_MODE => ("OFF"),
- RX_SIG_VALID_DLY => (10),
-
- ------------------RX 8B/10B Decoder Attributes---------------
- RX_DISPERR_SEQ_MATCH => ("TRUE"),
- DEC_MCOMMA_DETECT => ("TRUE"),
- DEC_PCOMMA_DETECT => ("TRUE"),
- DEC_VALID_COMMA_ONLY => ("FALSE"),
-
- ------------------------RX Clock Correction Attributes----------------------
- CBCC_DATA_SOURCE_SEL => ("DECODED"),
- CLK_COR_SEQ_2_USE => ("FALSE"),
- CLK_COR_KEEP_IDLE => ("FALSE"),
-CLK_COR_MAX_LAT => (31),
-CLK_COR_MIN_LAT => (24),
- CLK_COR_PRECEDENCE => ("TRUE"),
- CLK_COR_REPEAT_WAIT => (0),
- CLK_COR_SEQ_LEN => (4),
- CLK_COR_SEQ_1_ENABLE => ("1111"),
- CLK_COR_SEQ_1_1 => ("0111110111"),
- CLK_COR_SEQ_1_2 => ("0111110111"),
- CLK_COR_SEQ_1_3 => ("0111110111"),
- CLK_COR_SEQ_1_4 => ("0111110111"),
- CLK_CORRECT_USE => ("TRUE"),
- CLK_COR_SEQ_2_ENABLE => ("1111"),
- CLK_COR_SEQ_2_1 => ("0100000000"),
- CLK_COR_SEQ_2_2 => ("0100000000"),
- CLK_COR_SEQ_2_3 => ("0100000000"),
- CLK_COR_SEQ_2_4 => ("0100000000"),
-
- ------------------------RX Channel Bonding Attributes----------------------
- CHAN_BOND_KEEP_ALIGN => ("FALSE"),
- CHAN_BOND_MAX_SKEW => (7),
- CHAN_BOND_SEQ_LEN => (1),
- CHAN_BOND_SEQ_1_1 => ("0101111100"),
- CHAN_BOND_SEQ_1_2 => ("0000000000"),
- CHAN_BOND_SEQ_1_3 => ("0000000000"),
- CHAN_BOND_SEQ_1_4 => ("0000000000"),
- CHAN_BOND_SEQ_1_ENABLE => ("0001"),
- CHAN_BOND_SEQ_2_1 => ("0000000000"),
- CHAN_BOND_SEQ_2_2 => ("0000000000"),
- CHAN_BOND_SEQ_2_3 => ("0000000000"),
- CHAN_BOND_SEQ_2_4 => ("0000000000"),
- CHAN_BOND_SEQ_2_ENABLE => ("0000"),
- CHAN_BOND_SEQ_2_USE => ("FALSE"),
- FTS_DESKEW_SEQ_ENABLE => ("1111"),
- FTS_LANE_DESKEW_CFG => ("1111"),
- FTS_LANE_DESKEW_EN => ("FALSE"),
-
- ---------------------------RX Margin Analysis Attributes----------------------------
- ES_CONTROL => ("000000"),
- ES_ERRDET_EN => ("FALSE"),
- ES_EYE_SCAN_EN => ("FALSE"),
- ES_HORZ_OFFSET => (x"010"),
- ES_PMA_CFG => ("0000000000"),
- ES_PRESCALE => ("00000"),
- ES_QUALIFIER => (x"00000000000000000000"),
- ES_QUAL_MASK => (x"00000000000000000000"),
- ES_SDATA_MASK => (x"00000000000000000000"),
- ES_VERT_OFFSET => ("000000000"),
-
- -------------------------FPGA RX Interface Attributes-------------------------
- RX_DATA_WIDTH => (40),
-
- ---------------------------PMA Attributes----------------------------
- OUTREFCLK_SEL_INV => ("11"),
- PMA_RSV => (x"00000333"),
- PMA_RSV2 => (x"00002040"),
- PMA_RSV3 => ("00"),
- PMA_RSV4 => ("0000"),
- RX_BIAS_CFG => ("0000111100110011"),
- DMONITOR_CFG => (x"000A00"),
- RX_CM_SEL => ("11"),
- RX_CM_TRIM => ("1010"),
- RX_DEBUG_CFG => ("00000000000000"),
- RX_OS_CFG => ("0000010000000"),
- TERM_RCAL_CFG => ("100001000010000"),
- TERM_RCAL_OVRD => ("000"),
- TST_RSV => (x"00000000"),
-RX_CLK25_DIV => (5),
-TX_CLK25_DIV => (5),
- UCODEER_CLR => ('0'),
-
- ---------------------------PCI Express Attributes----------------------------
- PCS_PCIE_EN => ("FALSE"),
-
- ---------------------------PCS Attributes----------------------------
- PCS_RSVD_ATTR => (x"000000000000"),
-
- -------------RX Buffer Attributes------------
- RXBUF_ADDR_MODE => ("FULL"),
- RXBUF_EIDLE_HI_CNT => ("1000"),
- RXBUF_EIDLE_LO_CNT => ("0000"),
- RXBUF_EN => ("TRUE"),
- RX_BUFFER_CFG => ("000000"),
- RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
- RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
- RXBUF_RESET_ON_EIDLE => ("FALSE"),
- RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
- RXBUFRESET_TIME => ("00001"),
- RXBUF_THRESH_OVFLW => (61),
- RXBUF_THRESH_OVRD => ("FALSE"),
- RXBUF_THRESH_UNDFLW => (4),
- RXDLY_CFG => (x"001F"),
- RXDLY_LCFG => (x"030"),
- RXDLY_TAP_CFG => (x"0000"),
- RXPH_CFG => (x"C00002"),
- RXPHDLY_CFG => (x"084020"),
- RXPH_MONITOR_SEL => ("00000"),
- RX_XCLK_SEL => ("RXREC"),
- RX_DDI_SEL => ("000000"),
- RX_DEFER_RESET_BUF_EN => ("TRUE"),
-
- -----------------------CDR Attributes-------------------------
- RXCDR_CFG => (x"0000107FE406001041010"),
- RXCDR_FR_RESET_ON_EIDLE => ('0'),
- RXCDR_HOLD_DURING_EIDLE => ('0'),
- RXCDR_PH_RESET_ON_EIDLE => ('0'),
- RXCDR_LOCK_CFG => ("001001"),
-
- -------------------RX Initialization and Reset Attributes-------------------
- RXCDRFREQRESET_TIME => ("00001"),
- RXCDRPHRESET_TIME => ("00001"),
- RXISCANRESET_TIME => ("00001"),
- RXPCSRESET_TIME => ("00001"),
- RXPMARESET_TIME => ("00011"),
-
- -------------------RX OOB Signaling Attributes-------------------
- RXOOB_CFG => ("0000110"),
-
- -------------------------RX Gearbox Attributes---------------------------
- RXGEARBOX_EN => ("FALSE"),
- GEARBOX_MODE => ("000"),
-
- -------------------------PRBS Detection Attribute-----------------------
- RXPRBS_ERR_LOOPBACK => ('0'),
-
- -------------Power-Down Attributes----------
- PD_TRANS_TIME_FROM_P2 => (x"03c"),
- PD_TRANS_TIME_NONE_P2 => (x"3c"),
- PD_TRANS_TIME_TO_P2 => (x"64"),
-
- -------------RX OOB Signaling Attributes----------
- SAS_MAX_COM => (64),
- SAS_MIN_COM => (36),
- SATA_BURST_SEQ_LEN => ("0101"),
- SATA_BURST_VAL => ("100"),
- SATA_EIDLE_VAL => ("100"),
- SATA_MAX_BURST => (8),
- SATA_MAX_INIT => (21),
- SATA_MAX_WAKE => (7),
- SATA_MIN_BURST => (4),
- SATA_MIN_INIT => (12),
- SATA_MIN_WAKE => (4),
-
- -------------RX Fabric Clock Output Control Attributes----------
- TRANS_TIME_RATE => (x"0E"),
-
- --------------TX Buffer Attributes----------------
- TXBUF_EN => ("TRUE"),
- TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
- TXDLY_CFG => (x"001F"),
- TXDLY_LCFG => (x"030"),
- TXDLY_TAP_CFG => (x"0000"),
- TXPH_CFG => (x"0780"),
- TXPHDLY_CFG => (x"084020"),
- TXPH_MONITOR_SEL => ("00000"),
- TX_XCLK_SEL => ("TXOUT"),
-
- -------------------------FPGA TX Interface Attributes-------------------------
- TX_DATA_WIDTH => (40),
-
- -------------------------TX Configurable Driver Attributes-------------------------
- TX_DEEMPH0 => ("000000"),
- TX_DEEMPH1 => ("000000"),
- TX_EIDLE_ASSERT_DELAY => ("110"),
- TX_EIDLE_DEASSERT_DELAY => ("100"),
- TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
- TX_MAINCURSOR_SEL => ('0'),
- TX_DRIVE_MODE => ("DIRECT"),
- TX_MARGIN_FULL_0 => ("1001110"),
- TX_MARGIN_FULL_1 => ("1001001"),
- TX_MARGIN_FULL_2 => ("1000101"),
- TX_MARGIN_FULL_3 => ("1000010"),
- TX_MARGIN_FULL_4 => ("1000000"),
- TX_MARGIN_LOW_0 => ("1000110"),
- TX_MARGIN_LOW_1 => ("1000100"),
- TX_MARGIN_LOW_2 => ("1000010"),
- TX_MARGIN_LOW_3 => ("1000000"),
- TX_MARGIN_LOW_4 => ("1000000"),
-
- -------------------------TX Gearbox Attributes--------------------------
- TXGEARBOX_EN => ("FALSE"),
-
- -------------------------TX Initialization and Reset Attributes--------------------------
- TXPCSRESET_TIME => ("00001"),
- TXPMARESET_TIME => ("00001"),
-
- -------------------------TX Receiver Detection Attributes--------------------------
- TX_RXDETECT_CFG => (x"1832"),
- TX_RXDETECT_REF => ("100"),
-
- ------------------ JTAG Attributes ---------------
- ACJTAG_DEBUG_MODE => ('0'),
- ACJTAG_MODE => ('0'),
- ACJTAG_RESET => ('0'),
-
- ------------------ CDR Attributes ---------------
- CFOK_CFG => (x"49000040E80"),
- CFOK_CFG2 => ("0100000"),
- CFOK_CFG3 => ("0100000"),
- CFOK_CFG4 => ('0'),
- CFOK_CFG5 => (x"0"),
- CFOK_CFG6 => ("0000"),
- RXOSCALRESET_TIME => ("00011"),
- RXOSCALRESET_TIMEOUT => ("00000"),
-
- ------------------ PMA Attributes ---------------
- CLK_COMMON_SWING => ('0'),
- RX_CLKMUX_EN => ('1'),
- TX_CLKMUX_EN => ('1'),
- ES_CLK_PHASE_SEL => ('0'),
- USE_PCS_CLK_PHASE_SEL => ('0'),
- PMA_RSV6 => ('0'),
- PMA_RSV7 => ('0'),
-
- ------------------ TX Configuration Driver Attributes ---------------
- TX_PREDRIVER_MODE => ('0'),
- PMA_RSV5 => ('0'),
- SATA_PLL_CFG => ("VCO_3000MHZ"),
-
- ------------------ RX Fabric Clock Output Control Attributes ---------------
- RXOUT_DIV => (1),
-
- ------------------ TX Fabric Clock Output Control Attributes ---------------
- TXOUT_DIV => (1),
-
- ------------------ RX Phase Interpolator Attributes---------------
- RXPI_CFG0 => ("000"),
- RXPI_CFG1 => ('1'),
- RXPI_CFG2 => ('1'),
-
- --------------RX Equalizer Attributes-------------
- ADAPT_CFG0 => (x"00000"),
- RXLPMRESET_TIME => ("0001111"),
-
- RXLPM_BIAS_STARTUP_DISABLE => ('0'),
-
- RXLPM_CFG => ("0110"),
- RXLPM_CFG1 => ('0'),
- RXLPM_CM_CFG => ('0'),
- RXLPM_GC_CFG => ("111100010"),
- RXLPM_GC_CFG2 => ("001"),
- RXLPM_HF_CFG => ("00001111110000"),
- RXLPM_HF_CFG2 => ("01010"),
- RXLPM_HF_CFG3 => ("0000"),
- RXLPM_HOLD_DURING_EIDLE => ('0'),
- RXLPM_INCM_CFG => ('1'),
- RXLPM_IPCM_CFG => ('0'),
- RXLPM_LF_CFG => ("000000001111110000"),
- RXLPM_LF_CFG2 => ("01010"),
- RXLPM_OSINT_CFG => ("100"),
-
- ------------------ TX Phase Interpolator PPM Controller Attributes---------------
- TXPI_CFG0 => ("00"),
- TXPI_CFG1 => ("00"),
- TXPI_CFG2 => ("00"),
- TXPI_CFG3 => ('0'),
- TXPI_CFG4 => ('0'),
- TXPI_CFG5 => ("000"),
- TXPI_GREY_SEL => ('0'),
- TXPI_INVSTROBE_SEL => ('0'),
- TXPI_PPMCLK_SEL => ("TXUSRCLK2"),
- TXPI_PPM_CFG => (x"00"),
- TXPI_SYNFREQ_PPM => ("000"),
-
- ------------------ LOOPBACK Attributes---------------
- LOOPBACK_CFG => ('0'),
- PMA_LOOPBACK_CFG => ('0'),
-
- ------------------RX OOB Signalling Attributes---------------
- RXOOB_CLK_CFG => ("PMA"),
-
- ------------------TX OOB Signalling Attributes---------------
- TXOOB_CFG => ('0'),
-
- ------------------RX Buffer Attributes---------------
- RXSYNC_MULTILANE => ('0'),
- RXSYNC_OVRD => ('0'),
- RXSYNC_SKIP_DA => ('0'),
-
- ------------------TX Buffer Attributes---------------
- TXSYNC_MULTILANE => (TXSYNC_MULTILANE_IN),
- TXSYNC_OVRD => (TXSYNC_OVRD_IN),
- TXSYNC_SKIP_DA => ('0')
-
-
- )
- port map
- (
- ---------------------------------- Channel ---------------------------------
- CFGRESET => tied_to_ground_i,
- GTRESETSEL => tied_to_ground_i,
- GTRSVD => "0000000000000000",
- RESETOVRD => tied_to_ground_i,
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- DRPADDR => drpaddr_i,
- DRPCLK => DRPCLK_IN,
- DRPDI => drpdi_i,
- DRPDO => drpdo_i,
- DRPEN => drpen_i,
- DRPRDY => drprdy_i,
- DRPWE => drpwe_i,
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK => PLL0CLK_IN,
- PLL0REFCLK => PLL0REFCLK_IN,
- PLL1CLK => PLL1CLK_IN,
- PLL1REFCLK => PLL1REFCLK_IN,
- RXSYSCLKSEL => "00",
- TXSYSCLKSEL => "00",
- ------------------------------- Eye Scan Ports -----------------------------
- EYESCANDATAERROR => EYESCANDATAERROR_OUT,
- EYESCANMODE => tied_to_ground_i,
- EYESCANRESET => eyescanreset_in,
- EYESCANTRIGGER => eyescantrigger_in,
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK => LOOPBACK_IN,
- RXPD => RXPD_IN,
- TXPD => TXPD_IN,
- ----------------------------- PCS Reserved Ports ---------------------------
- PCSRSVDIN => "0000000000000000",
- PCSRSVDOUT => open,
- ----------------------------- PMA Reserved Ports ---------------------------
- PMARSVDIN3 => '0',
- PMARSVDIN4 => '0',
- ------------------------------- Receive Ports ------------------------------
- CLKRSVD0 => tied_to_ground_i,
- CLKRSVD1 => tied_to_ground_i,
- DMONFIFORESET => tied_to_ground_i,
- DMONITORCLK => tied_to_ground_i,
- RXPMARESETDONE => rxpmaresetdone_t,
- RXUSERRDY => RXUSERRDY_IN,
- SIGVALIDCLK => tied_to_ground_i,
- -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
- RXDATAVALID => open,
- RXGEARBOXSLIP => tied_to_ground_i,
- RXHEADER => open,
- RXHEADERVALID => open,
- RXSTARTOFSEQ => open,
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RX8B10BEN => tied_to_vcc_i,
- RXCHARISCOMMA => RXCHARISCOMMA_OUT,
- RXCHARISK => RXCHARISK_OUT,
- RXDISPERR => RXDISPERR_OUT,
- RXNOTINTABLE => RXNOTINTABLE_OUT,
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN => GTPRXN_IN,
- GTPRXP => GTPRXP_IN,
- PMARSVDIN2 => '0',
- PMARSVDOUT0 => open,
- PMARSVDOUT1 => open,
- ------------------- Receive Ports - Channel Bonding Ports ------------------
- RXCHANBONDSEQ => open,
- RXCHBONDEN => tied_to_ground_i,
- RXCHBONDI => "0000",
- RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
- RXCHBONDMASTER => tied_to_ground_i,
- RXCHBONDO => open,
- RXCHBONDSLAVE => tied_to_ground_i,
- ------------------- Receive Ports - Channel Bonding Ports -----------------
- RXCHANISALIGNED => open,
- RXCHANREALIGN => open,
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT => RXCLKCORCNT_OUT,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- RXBYTEISALIGNED => rxbyteisaligned_out,
- RXBYTEREALIGN => RXBYTEREALIGN_OUT,
- RXCOMMADET => rxcommadet_out,
- RXCOMMADETEN => tied_to_vcc_i,
- RXMCOMMAALIGNEN => RXMCOMMAALIGNEN_IN,
- RXPCOMMAALIGNEN => RXPCOMMAALIGNEN_IN,
- RXSLIDE => tied_to_ground_i,
- ----------------------- Receive Ports - PRBS Detection ---------------------
- RXPRBSCNTRESET => rxprbscntreset_in,
- RXPRBSERR => rxprbserr_out,
- RXPRBSSEL => rxprbssel_in,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET => gtrxreset_out,
- RXDATA => rxdata_i,
- RXOUTCLK => RXOUTCLK_OUT,
- RXOUTCLKFABRIC => open,
- RXOUTCLKPCS => open,
- RXOUTCLKSEL => "010",
- RXPCSRESET => rxpcsreset_in,
- RXPMARESET => rxpmareset_in,
- RXUSRCLK => RXUSRCLK_IN,
- RXUSRCLK2 => RXUSRCLK2_IN,
- ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
- DMONITOROUT => dmonitorout_out,
- RXADAPTSELTEST => tied_to_ground_vec_i(13 downto 0),
- RXDFEXYDEN => tied_to_ground_i,
- RXOSCALRESET => tied_to_ground_i,
- RXOSHOLD => tied_to_ground_i,
- RXOSINTCFG => "0010",
- RXOSINTDONE => open,
- RXOSINTEN => tied_to_vcc_i,
- RXOSINTHOLD => tied_to_ground_i,
- RXOSINTID0 => tied_to_ground_vec_i(3 downto 0),
- RXOSINTNTRLEN => tied_to_ground_i,
- RXOSINTOVRDEN => tied_to_ground_i,
- RXOSINTPD => tied_to_ground_i,
- RXOSINTSTARTED => open,
- RXOSINTSTROBE => tied_to_ground_i,
- RXOSINTSTROBEDONE => open,
- RXOSINTSTROBESTARTED => open,
- RXOSINTTESTOVRDEN => tied_to_ground_i,
- RXOSOVRDEN => tied_to_ground_i,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRFREQRESET => tied_to_ground_i,
- RXCDRHOLD => rxcdrhold_in,
- RXCDRLOCK => RXCDRLOCK_OUT,
- RXCDROVRDEN => tied_to_ground_i,
- RXCDRRESET => tied_to_ground_i,
- RXCDRRESETRSV => tied_to_ground_i,
- RXELECIDLE => open,
- RXELECIDLEMODE => "11",
- RXLPMHFHOLD => RXLPMHFHOLD_IN,
- RXLPMHFOVRDEN => rxlpmhfovrden_in,
- RXLPMLFHOLD => RXLPMLFHOLD_IN,
- RXLPMLFOVRDEN => tied_to_ground_i,
- RXLPMOSINTNTRLEN => tied_to_ground_i,
- RXLPMRESET => rxlpmreset_in,
- RXOOBRESET => tied_to_ground_i,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- RXBUFRESET => rxbufreset_in,
- RXBUFSTATUS => RXBUFSTATUS_OUT,
- RXDDIEN => tied_to_ground_i,
- RXDLYBYPASS => tied_to_vcc_i,
- RXDLYEN => tied_to_ground_i,
- RXDLYOVRDEN => tied_to_ground_i,
- RXDLYSRESET => tied_to_ground_i,
- RXDLYSRESETDONE => open,
- RXPHALIGN => tied_to_ground_i,
- RXPHALIGNDONE => open,
- RXPHALIGNEN => tied_to_ground_i,
- RXPHDLYPD => tied_to_ground_i,
- RXPHDLYRESET => tied_to_ground_i,
- RXPHMONITOR => open,
- RXPHOVRDEN => tied_to_ground_i,
- RXPHSLIPMONITOR => open,
- RXSTATUS => open,
- RXSYNCALLIN => tied_to_ground_i,
- RXSYNCDONE => open,
- RXSYNCIN => tied_to_ground_i,
- RXSYNCMODE => tied_to_ground_i,
- RXSYNCOUT => open,
- ----------- Receive Ports - RX Fabric Clock Output Control Ports ----------
- RXRATEMODE => '0',
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRATE => tied_to_ground_vec_i(2 downto 0),
- RXRATEDONE => open,
- RXRESETDONE => RXRESETDONE_OUT,
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- PHYSTATUS => open,
- RXVALID => open,
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY => RXPOLARITY_IN,
- --------------------- Receive Ports - RX Ports for SATA --------------------
- RXCOMINITDET => open,
- RXCOMSASDET => open,
- RXCOMWAKEDET => open,
- ------------------------------- Transmit Ports -----------------------------
- SETERRSTATUS => tied_to_ground_i,
- TSTIN => "11111111111111111111",
- TXPHDLYTSTCLK => tied_to_ground_i,
- TXPIPPMEN => tied_to_ground_i,
- TXPIPPMOVRDEN => tied_to_ground_i,
- TXPIPPMPD => tied_to_ground_i,
- TXPIPPMSEL => tied_to_vcc_i,
- TXPIPPMSTEPSIZE => tied_to_ground_vec_i(4 downto 0),
- TXPMARESETDONE => open,
- TXPOSTCURSOR => txpostcursor_in,
- TXPOSTCURSORINV => tied_to_ground_i,
- TXPRECURSOR => txprecursor_in,
- TXPRECURSORINV => tied_to_ground_i,
- TXRATEMODE => tied_to_ground_i,
- TXUSERRDY => TXUSERRDY_IN,
- -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
- TXGEARBOXREADY => open,
- TXHEADER => tied_to_ground_vec_i(2 downto 0),
- TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
- TXSTARTSEQ => tied_to_ground_i,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- TX8B10BBYPASS => tied_to_ground_vec_i(3 downto 0),
- TX8B10BEN => tied_to_vcc_i,
- TXCHARDISPMODE => txchardispmode_in,
- TXCHARDISPVAL => txchardispval_in,
- TXCHARISK => TXCHARISK_IN,
- ----------------- Transmit Ports - Configurable Driver Ports ---------------
- PMARSVDIN0 => '0',
- PMARSVDIN1 => '0',
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS => TXBUFSTATUS_OUT,
- TXDLYBYPASS => tied_to_vcc_i,
- TXDLYEN => tied_to_ground_i,
- TXDLYHOLD => tied_to_ground_i,
- TXDLYOVRDEN => tied_to_ground_i,
- TXDLYSRESET => tied_to_ground_i,
- TXDLYSRESETDONE => open,
- TXDLYUPDOWN => tied_to_ground_i,
- TXPHALIGN => tied_to_ground_i,
- TXPHALIGNDONE => open,
- TXPHALIGNEN => tied_to_ground_i,
- TXPHDLYPD => tied_to_ground_i,
- TXPHDLYRESET => tied_to_ground_i,
- TXPHINIT => tied_to_ground_i,
- TXPHINITDONE => open,
- TXPHOVRDEN => tied_to_ground_i,
- TXSYNCALLIN => tied_to_ground_i,
- TXSYNCDONE => open,
- TXSYNCIN => tied_to_ground_i,
- TXSYNCMODE => tied_to_ground_i,
- TXSYNCOUT => open,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET => GTTXRESET_IN,
- TXDATA => txdata_i,
- TXOUTCLK => TXOUTCLK_OUT,
- TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT,
- TXOUTCLKPCS => TXOUTCLKPCS_OUT,
- TXOUTCLKSEL => "010",
- TXPCSRESET => txpcsreset_in,
- TXPMARESET => txpmareset_in,
- TXUSRCLK => TXUSRCLK_IN,
- TXUSRCLK2 => TXUSRCLK2_IN,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN => GTPTXN_OUT,
- GTPTXP => GTPTXP_OUT,
- TXBUFDIFFCTRL => "100",
- TXDIFFCTRL => txdiffctrl_in,
- TXDIFFPD => tied_to_ground_i,
- TXINHIBIT => txinhibit_in,
- TXMAINCURSOR => txmaincursor_in,
- TXPDELECIDLEMODE => tied_to_ground_i,
- TXPISOPD => tied_to_ground_i,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- TXRATE => tied_to_ground_vec_i(2 downto 0),
- TXRATEDONE => open,
- TXRESETDONE => TXRESETDONE_OUT,
- --------------------- Transmit Ports - TX PRBS Generator -------------------
- TXPRBSFORCEERR => txprbsforceerr_in,
- TXPRBSSEL => txprbssel_in,
- -------------------- Transmit Ports - TX Polarity Control ------------------
- TXPOLARITY => txpolarity_in,
- ----------------- Transmit Ports - TX Ports for PCI Express ----------------
- TXDEEMPH => tied_to_ground_i,
- TXDETECTRX => tied_to_ground_i,
- TXELECIDLE => txelecidle_in,
- TXMARGIN => tied_to_ground_vec_i(2 downto 0),
- TXSWING => tied_to_ground_i,
- --------------------- Transmit Ports - TX Ports for SATA -------------------
- TXCOMFINISH => open,
- TXCOMINIT => tied_to_ground_i,
- TXCOMSAS => tied_to_ground_i,
- TXCOMWAKE => tied_to_ground_i
-
- );
-
- RXPMARESETDONE_OUT <= rxpmaresetdone_t;
-
- ------------------------- Soft Fix for Production Silicon----------------------
- gtrxreset_seq_i : north_channel_gtrxreset_seq
- port map
- (
- RST => RST_IN,
- STABLE_CLOCK => STABLE_CLOCK,
- GTRXRESET_IN => GTRXRESET_IN,
- RXPMARESETDONE => rxpmaresetdone_t,
- GTRXRESET_OUT => gtrxreset_out,
- DRP_OP_DONE => drp_op_done,
- DRPCLK => DRPCLK_IN,
- DRPEN => drpen_rst_t,
- DRPADDR => drpaddr_rst_t,
- DRPWE => drpwe_rst_t,
- DRPDO => drpdo_rst_t,
- DRPDI => drpdi_rst_t,
- DRPRDY => drprdy_rst_t
-
- );
-
- drpen_pma_t <= '0';
- drpaddr_pma_t <= "000000000";
- drpwe_pma_t <= '0';
- drpdi_pma_t <= x"0000";
- drpen_rate_t <= '0';
- drpaddr_rate_t <= "000000000";
- drpwe_rate_t <= '0';
- drpdi_rate_t <= x"0000";
- drpen_i <= drpen_rst_t when drp_op_done ='0' else
- drpen_pma_t when drp_pma_busy = '1' else
- drpen_rate_t when drp_rate_busy ='1' else DRPEN_IN;
-
-
- drpaddr_i <= drpaddr_rst_t when drp_op_done ='0' else
- drpaddr_pma_t when drp_pma_busy = '1' else
- drpaddr_rate_t when drp_rate_busy ='1' else DRPADDR_IN;
-
-
- drpwe_i <= drpwe_rst_t when drp_op_done ='0' else
- drpwe_pma_t when drp_pma_busy = '1' else
- drpwe_rate_t when drp_rate_busy ='1' else DRPWE_IN;
-
-
-
- DRPDO_OUT <= drpdo_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else x"0000";
-
- drpdo_rst_t <= drpdo_i;
-
- drpdo_pma_t <= drpdo_i;
-
- drpdo_rate_t <= drpdo_i;
-
-
- drpdi_i <= drpdi_rst_t when drp_op_done ='0' else
- drpdi_pma_t when drp_pma_busy = '1' else
- drpdi_rate_t when drp_rate_busy ='1' else DRPDI_IN;
-
-
- DRPRDY_OUT <= drprdy_i when (drp_op_done='1' or drp_pma_busy='0' or drp_rate_busy='0') else '0';
-
- drprdy_rst_t <= drprdy_i;
-
- drprdy_pma_t <= drprdy_i;
-
- drprdy_rate_t <= drprdy_i;
-
-
- drp_pma_busy <= '0';
- drp_rate_busy <= '0';
-
- process (DRPCLK_IN)
- begin
- if(rising_edge(DRPCLK_IN)) then
- if(drp_op_done = '0' or drp_rate_busy='1') then
- drp_busy_i1 <= '1';
- else
- drp_busy_i1 <= '0';
- end if;
- end if;
- end process;
-
- process (DRPCLK_IN)
- begin
- if(rising_edge(DRPCLK_IN)) then
- if(drp_op_done = '0' or drp_pma_busy='1') then
- drp_busy_i2 <= '1';
- else
- drp_busy_i2 <= '0';
- end if;
- end if;
- end process;
-
- DRP_BUSY_OUT <= drp_busy_i1 or drp_busy_i2;
-
-
- end MAPPED;
-
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_gtrxreset_seq.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_gtrxreset_seq.vhd
deleted file mode 100644
index dfb0912b28504d96dca2bea7c29d2bc7dad1c179..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_gtrxreset_seq.vhd
+++ /dev/null
@@ -1,416 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-ENTITY north_channel_gtrxreset_seq IS
- port (
- RST : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
- GTRXRESET_IN : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
- RXPMARESETDONE: IN std_logic;
- GTRXRESET_OUT : OUT std_logic;
-
- STABLE_CLOCK : IN std_logic;
- DRPCLK : IN std_logic;
- DRPADDR : OUT std_logic_vector(8 downto 0);
- DRPDO : IN std_logic_vector(15 downto 0);
- DRPDI : OUT std_logic_vector(15 downto 0);
- DRPRDY : IN std_logic;
- DRPEN : OUT std_logic;
- DRPWE : OUT std_logic;
- DRP_OP_DONE : OUT std_logic
-);
-END north_channel_gtrxreset_seq;
-
-ARCHITECTURE Behavioral of north_channel_gtrxreset_seq is
-
- component north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
- constant DLY : time := 1 ns;
- type state_type is (idle,
- drp_rd,
- wait_rd_data,
- wr_16,
- wait_wr_done1,
- wait_pmareset,
- wr_20,
- wait_wr_done2);
-
- signal state : state_type := idle;
- signal next_state : state_type := idle;
- signal gtrxreset_f : std_logic;
- signal gtrxreset_s : std_logic;
- signal gtrxreset_ss : std_logic;
- signal rst_ss : std_logic;
- signal rxpmaresetdone_ss : std_logic;
- signal rxpmaresetdone_sss : std_logic;
- signal rd_data : std_logic_vector(15 downto 0);
- signal next_rd_data : std_logic_vector(15 downto 0);
- signal pmarstdone_fall_edge: std_logic;
- signal gtrxreset_i : std_logic;
- signal gtrxreset_o : std_logic;
- signal drpen_o : std_logic;
- signal drpwe_o : std_logic;
- signal drpaddr_o : std_logic_vector(8 downto 0);
- signal drpdi_o : std_logic_vector(15 downto 0);
- signal drp_op_done_o : std_logic;
- signal flag : std_logic :='0';
- signal original_rd_data : std_logic_vector(15 downto 0);
-
-BEGIN
-
-flag_gen : PROCESS(DRPCLK)
-BEGIN
- IF (DRPCLK = '1' and DRPCLK'event) THEN
- IF (state = wr_16 or state = wait_pmareset or state = wr_20 or state = wait_wr_done1) THEN
- flag <= '1';
- ELSIF(state = wait_wr_done2) THEN
- flag <= '0';
- END IF;
- END IF;
-END PROCESS flag_gen;
-
-org_data_gen : PROCESS(DRPCLK)
-BEGIN
- IF (DRPCLK = '1' and DRPCLK'event) THEN
- IF ( state = wait_rd_data and DRPRDY = '1' and flag = '0') THEN
- original_rd_data <= DRPDO;
- END IF;
- END IF;
-END PROCESS org_data_gen;
-
-
- rxpmaresetdone_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => RXPMARESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => DRPCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxpmaresetdone_ss ,
- scndry_vect_out => open
- );
-
- rst_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => RST ,
- prmry_vect_in => "00" ,
- scndry_aclk => DRPCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rst_ss ,
- scndry_vect_out => open
- );
-
- gtrxreset_in_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => GTRXRESET_IN ,
- prmry_vect_in => "00" ,
- scndry_aclk => DRPCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gtrxreset_f ,
- scndry_vect_out => open
- );
-
-
---output assignment
- GTRXRESET_OUT <= gtrxreset_o;
- DRPEN <= drpen_o;
- DRPWE <= drpwe_o;
- DRPADDR <= drpaddr_o;
- DRPDI <= drpdi_o;
- DRP_OP_DONE <= drp_op_done_o;
-
- PROCESS (DRPCLK, rst_ss)
- BEGIN
- IF (rst_ss = '1') THEN
- state <= idle after DLY;
- gtrxreset_s <= '0' after DLY;
- gtrxreset_ss <= '0' after DLY;
- rxpmaresetdone_sss <= '0' after DLY;
- rd_data <= x"0000" after DLY;
- gtrxreset_o <= '0' after DLY;
- ELSIF (DRPCLK'event and DRPCLK='1') THEN
- state <= next_state after DLY;
- gtrxreset_s <= gtrxreset_f after DLY;
- gtrxreset_ss <= gtrxreset_s after DLY;
- rxpmaresetdone_sss <= rxpmaresetdone_ss after DLY;
- rd_data <= next_rd_data after DLY;
- gtrxreset_o <= gtrxreset_i after DLY;
- END IF;
- END PROCESS;
-
- PROCESS (DRPCLK, gtrxreset_f)
- BEGIN
- IF (gtrxreset_f = '1') THEN
- drp_op_done_o <= '0' after DLY;
-
- ELSIF (DRPCLK'event and DRPCLK='1') THEN
- IF (state = wait_wr_done2 and DRPRDY = '1') THEN
- drp_op_done_o <= '1' after DLY;
- ELSE
- drp_op_done_o <= drp_op_done_o after DLY;
- END IF;
- END IF;
- END PROCESS;
-
- pmarstdone_fall_edge <= (not rxpmaresetdone_ss) and (rxpmaresetdone_sss);
-
- PROCESS (gtrxreset_ss,DRPRDY,state,pmarstdone_fall_edge)
- BEGIN
- CASE state IS
-
- WHEN idle =>
- IF (gtrxreset_ss='1') THEN
- next_state <= drp_rd;
- ELSE
- next_state <= idle;
- END IF;
-
- WHEN drp_rd =>
- next_state<= wait_rd_data;
-
- WHEN wait_rd_data =>
- IF (DRPRDY='1')THEN
- next_state <= wr_16;
- ELSE
- next_state <= wait_rd_data;
- END IF;
-
- WHEN wr_16 =>
- next_state <= wait_wr_done1;
-
- WHEN wait_wr_done1 =>
- IF (DRPRDY='1') THEN
- next_state <= wait_pmareset;
- ELSE
- next_state <= wait_wr_done1;
- END IF;
-
- WHEN wait_pmareset =>
- IF (pmarstdone_fall_edge='1') THEN
- next_state <= wr_20;
- ELSE
- next_state <= wait_pmareset;
- END IF;
-
- WHEN wr_20 =>
- next_state <= wait_wr_done2;
-
- WHEN wait_wr_done2 =>
- IF (DRPRDY='1') THEN
- next_state <= idle;
- ELSE
- next_state <= wait_wr_done2;
- END IF;
-
- WHEN others=>
- next_state <= idle;
-
- END CASE;
- END PROCESS;
-
--- drives DRP interface and GTRXRESET_OUT
- PROCESS(DRPRDY,state,rd_data,DRPDO,gtrxreset_ss,flag,original_rd_data)
- BEGIN
--- assert gtrxreset_out until wr to 16-bit is complete
--- RX_DATA_WIDTH is located at addr x"0011", [13 downto 11]
--- encoding is this : /16 = x "2", /20 = x"3", /32 = x"4", /40 = x"5"
- gtrxreset_i <= '0';
- drpaddr_o <= '0'& x"11"; -- 000010001
- drpen_o <= '0';
- drpwe_o <= '0';
- drpdi_o <= x"0000";
- next_rd_data <= rd_data;
-
- CASE state IS
-
- --do nothing to DRP or reset
- WHEN idle => null;
-
- --assert reset and issue rd
- WHEN drp_rd =>
- gtrxreset_i <= '1';
- drpen_o <= '1';
- drpwe_o <= '0';
-
- --assert reset and wait to load rd data
- WHEN wait_rd_data =>
- gtrxreset_i <= '1';
-
- IF (DRPRDY = '1' and flag = '0') THEN
- next_rd_data <= DRPDO;
- ELSIF (DRPRDY = '1' and flag = '1') THEN
- next_rd_data <= original_rd_data;
- ELSE
- next_rd_data <= rd_data;
- END IF;
-
- --assert reset and write to 16-bit mode
- WHEN wr_16=>
- gtrxreset_i<= '1';
- drpen_o <= '1';
- drpwe_o <= '1';
- -- Addr "00001001" [11] = '0' puts width mode in /16 or /32
- drpdi_o <= rd_data(15 downto 12) & '0' & rd_data(10 downto 0);
-
- --keep asserting reset until write to 16-bit mode is complete
- WHEN wait_wr_done1=>
- gtrxreset_i <= '1';
-
- --deassert reset and no DRP access until 2nd pmareset
- WHEN wait_pmareset => null;
- IF (gtrxreset_ss='1') THEN
- gtrxreset_i <= '1';
- ELSE
- gtrxreset_i <= '0';
- END IF;
-
- --write to 20-bit mode
- WHEN wr_20 =>
- drpen_o <='1';
- drpwe_o <= '1';
- drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read
-
- --wait to complete write to 20-bit mode
- WHEN wait_wr_done2 => null;
-
- WHEN others => null;
-
- END CASE;
- END PROCESS;
-
-END Behavioral;
-
-
-
-
-
-
-
-
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_multi_gt.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_multi_gt.vhd
deleted file mode 100644
index f4e1f927d1fef3515ba60d5413767d9c095951b4..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_multi_gt.vhd
+++ /dev/null
@@ -1,479 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
--- Module north_channel_GT_WRAPPER
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
---***************************** Entity Declaration ****************************
-
-entity north_channel_multi_gt is
-generic
-(
- -- Simulation attributes
- WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
-);
-port
-(
- STABLE_CLOCK : in std_logic; -- System Clock
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- --____________________________CHANNEL PORTS________________________________
- GT0_DRP_BUSY_OUT : out std_logic;
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
- GT0_DRPCLK_IN : in std_logic;
- GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
- GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
- GT0_DRPEN_IN : in std_logic;
- GT0_DRPRDY_OUT : out std_logic;
- GT0_DRPWE_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
- GT0_RXPD_IN : in std_logic_vector(1 downto 0);
- GT0_TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- GT0_eyescanreset_in : in std_logic;
- GT0_RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- GT0_rxprbserr_out : out std_logic;
- GT0_rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- GT0_rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- GT0_eyescandataerror_out : out std_logic;
- GT0_eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GT0_GTPRXN_IN : in std_logic;
- GT0_GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GT0_rxbyteisaligned_out : out std_logic;
- GT0_RXBYTEREALIGN_OUT : out std_logic;
- GT0_rxcommadet_out : out std_logic;
- GT0_RXMCOMMAALIGNEN_IN : in std_logic;
- GT0_RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GT0_GTRXRESET_IN : in std_logic;
- GT0_rxpcsreset_in : in std_logic;
- GT0_rxpmareset_in : in std_logic;
- GT0_rxlpmreset_in : in std_logic;
- GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
- GT0_RXOUTCLK_OUT : out std_logic;
- GT0_RXUSRCLK_IN : in std_logic;
- GT0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GT0_RXCDRLOCK_OUT : out std_logic;
- GT0_RXLPMHFHOLD_IN : in std_logic;
- GT0_RXLPMLFHOLD_IN : in std_logic;
- GT0_rxlpmhfovrden_in : in std_logic;
- GT0_rxcdrhold_in : in std_logic;
- GT0_dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GT0_rxbufreset_in : in std_logic;
- GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GT0_RXRESETDONE_OUT : out std_logic;
- GT0_RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- GT0_txpostcursor_in : in std_logic_vector(4 downto 0);
- GT0_txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- GT0_RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- GT0_TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GT0_txchardispmode_in : in std_logic_vector(3 downto 0);
- GT0_txchardispval_in : in std_logic_vector(3 downto 0);
- GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- GT0_TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GT0_GTTXRESET_IN : in std_logic;
- GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
- GT0_TXOUTCLK_OUT : out std_logic;
- GT0_TXOUTCLKFABRIC_OUT : out std_logic;
- GT0_TXOUTCLKPCS_OUT : out std_logic;
- GT0_TXUSRCLK_IN : in std_logic;
- GT0_TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- GT0_txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- GT0_txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GT0_GTPTXN_OUT : out std_logic;
- GT0_GTPTXP_OUT : out std_logic;
- GT0_txdiffctrl_in : in std_logic_vector(3 downto 0);
- GT0_txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GT0_txpcsreset_in : in std_logic;
- GT0_txinhibit_in : in std_logic;
- GT0_txpmareset_in : in std_logic;
- GT0_TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- GT0_txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- GT0_txpolarity_in : in std_logic;
-
-
-
- --____________________________COMMON PORTS________________________________
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
- GT0_PLL0RESET_IN : in std_logic
-
-
-);
-
-
-end north_channel_multi_gt;
-
-architecture MAPPED of north_channel_multi_gt is
- attribute core_generation_info : string;
-attribute core_generation_info of MAPPED : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
---***********************************Parameter Declarations********************
-
- constant DLY : time := 1 ns;
-
---***************************** Signal Declarations *****************************
-
- -- ground and tied_to_vcc_i signals
- signal tied_to_ground_i : std_logic;
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
- signal tied_to_vcc_i : std_logic;
-
- signal gt0_pll0clk_i : std_logic;
- signal gt0_pll0refclk_i : std_logic;
- signal gt0_pll1clk_i : std_logic;
- signal gt0_pll1refclk_i : std_logic;
- signal gt0_rst_i : std_logic;
-
---*************************** Component Declarations **************************
-component north_channel_gt
-generic
-(
- -- Simulation attributes
- GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
- TXSYNC_OVRD_IN : bit := '0';
- TXSYNC_MULTILANE_IN : bit := '0'
-);
-port
-(
- STABLE_CLOCK : in std_logic; -- System Clock
- RST_IN : in std_logic; -- Connect to System Reset
- DRP_BUSY_OUT : out std_logic; -- Indicates that the DRP bus is not accessible to the User
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- DRPADDR_IN : in std_logic_vector(8 downto 0);
- DRPCLK_IN : in std_logic;
- DRPDI_IN : in std_logic_vector(15 downto 0);
- DRPDO_OUT : out std_logic_vector(15 downto 0);
- DRPEN_IN : in std_logic;
- DRPRDY_OUT : out std_logic;
- DRPWE_IN : in std_logic;
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK_IN : in std_logic;
- PLL0REFCLK_IN : in std_logic;
- PLL1CLK_IN : in std_logic;
- PLL1REFCLK_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK_IN : in std_logic_vector(2 downto 0);
- RXPD_IN : in std_logic_vector(1 downto 0);
- TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- eyescanreset_in : in std_logic;
- RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- rxprbserr_out : out std_logic;
- rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- eyescandataerror_out : out std_logic;
- eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN_IN : in std_logic;
- GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
- rxbyteisaligned_out : out std_logic;
- RXBYTEREALIGN_OUT : out std_logic;
- rxcommadet_out : out std_logic;
- RXMCOMMAALIGNEN_IN : in std_logic;
- RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET_IN : in std_logic;
- rxpcsreset_in : in std_logic;
- rxpmareset_in : in std_logic;
- rxlpmreset_in : in std_logic;
- RXDATA_OUT : out std_logic_vector(31 downto 0);
- RXOUTCLK_OUT : out std_logic;
- RXUSRCLK_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRLOCK_OUT : out std_logic;
- RXLPMHFHOLD_IN : in std_logic;
- RXLPMLFHOLD_IN : in std_logic;
- rxlpmhfovrden_in : in std_logic;
- rxcdrhold_in : in std_logic;
- dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- rxbufreset_in : in std_logic;
- RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRESETDONE_OUT : out std_logic;
- RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- txpostcursor_in : in std_logic_vector(4 downto 0);
- txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- txchardispmode_in : in std_logic_vector(3 downto 0);
- txchardispval_in : in std_logic_vector(3 downto 0);
- TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET_IN : in std_logic;
- TXDATA_IN : in std_logic_vector(31 downto 0);
- TXOUTCLK_OUT : out std_logic;
- TXOUTCLKFABRIC_OUT : out std_logic;
- TXOUTCLKPCS_OUT : out std_logic;
- TXUSRCLK_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN_OUT : out std_logic;
- GTPTXP_OUT : out std_logic;
- txdiffctrl_in : in std_logic_vector(3 downto 0);
- txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- txpcsreset_in : in std_logic;
- txinhibit_in : in std_logic;
- txpmareset_in : in std_logic;
- TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- txpolarity_in : in std_logic
-
-);
-end component;
-
---********************************* Main Body of Code**************************
-
-begin
-
- tied_to_ground_i <= '0';
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');
- tied_to_vcc_i <= '1';
-
- gt0_pll0clk_i <= GT0_PLL0OUTCLK_IN;
- gt0_pll0refclk_i <= GT0_PLL0OUTREFCLK_IN;
- gt0_pll1clk_i <= GT0_PLL1OUTCLK_IN;
- gt0_pll1refclk_i <= GT0_PLL1OUTREFCLK_IN;
- gt0_rst_i <= GT0_PLL0RESET_IN;
-
- --------------------------- GT Instances -------------------------------
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- gt0_north_channel_i : north_channel_gt
- generic map
- (
- -- Simulation attributes
- GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
- TXSYNC_OVRD_IN => ('0'),
- TXSYNC_MULTILANE_IN => ('0')
- )
- port map
- (
-
- STABLE_CLOCK => STABLE_CLOCK,
- RST_IN => gt0_rst_i,
- DRP_BUSY_OUT => GT0_DRP_BUSY_OUT,
-
- ---------------------------- Channel - DRP Ports --------------------------
- DRPADDR_IN => GT0_DRPADDR_IN,
- DRPCLK_IN => GT0_DRPCLK_IN,
- DRPDI_IN => GT0_DRPDI_IN,
- DRPDO_OUT => GT0_DRPDO_OUT,
- DRPEN_IN => GT0_DRPEN_IN,
- DRPRDY_OUT => GT0_DRPRDY_OUT,
- DRPWE_IN => GT0_DRPWE_IN,
- ------------------------------- Clocking Ports -----------------------------
- PLL0CLK_IN => gt0_pll0clk_i,
- PLL0REFCLK_IN => gt0_pll0refclk_i,
- PLL1CLK_IN => gt0_pll1clk_i,
- PLL1REFCLK_IN => gt0_pll1refclk_i,
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK_IN => GT0_LOOPBACK_IN,
- RXPD_IN => GT0_RXPD_IN,
- TXPD_IN => GT0_TXPD_IN,
- ------------------------------- Receive Ports ------------------------------
- eyescanreset_in => gt0_eyescanreset_in,
- RXUSERRDY_IN => GT0_RXUSERRDY_IN,
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- rxprbserr_out => gt0_rxprbserr_out,
- rxprbssel_in => gt0_rxprbssel_in,
- ------------------- Receive Ports - Pattern Checker ports ------------------
- rxprbscntreset_in => gt0_rxprbscntreset_in,
- -------------------------- RX Margin Analysis Ports ------------------------
- eyescandataerror_out => gt0_eyescandataerror_out,
- eyescantrigger_in => gt0_eyescantrigger_in,
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT,
- RXCHARISK_OUT => GT0_RXCHARISK_OUT,
- RXDISPERR_OUT => GT0_RXDISPERR_OUT,
- RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT,
- ------------------------- Receive Ports - AFE Ports ------------------------
- GTPRXN_IN => GT0_GTPRXN_IN,
- GTPRXP_IN => GT0_GTPRXP_IN,
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- rxbyteisaligned_out => gt0_rxbyteisaligned_out,
- RXBYTEREALIGN_OUT => GT0_RXBYTEREALIGN_OUT,
- rxcommadet_out => gt0_rxcommadet_out,
- RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN,
- RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTRXRESET_IN => GT0_GTRXRESET_IN,
- rxpcsreset_in => gt0_rxpcsreset_in,
- rxpmareset_in => gt0_rxpmareset_in,
- rxlpmreset_in => gt0_rxlpmreset_in,
- RXDATA_OUT => GT0_RXDATA_OUT,
- RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
- RXUSRCLK_IN => GT0_RXUSRCLK_IN,
- RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
- RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN,
- RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN,
- rxlpmhfovrden_in => gt0_rxlpmhfovrden_in,
- rxcdrhold_in => gt0_rxcdrhold_in,
- dmonitorout_out => gt0_dmonitorout_out,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- rxbufreset_in => gt0_rxbufreset_in,
- RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- RXRESETDONE_OUT => GT0_RXRESETDONE_OUT,
- RXPMARESETDONE_OUT => GT0_RXPMARESETDONE_OUT,
- ------------------------ TX Configurable Driver Ports ----------------------
- txpostcursor_in => gt0_txpostcursor_in,
- txprecursor_in => gt0_txprecursor_in,
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY_IN => GT0_RXPOLARITY_IN,
- ------------------------------- Transmit Ports -----------------------------
- TXUSERRDY_IN => GT0_TXUSERRDY_IN,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- txchardispmode_in => gt0_txchardispmode_in,
- txchardispval_in => gt0_txchardispval_in,
- TXCHARISK_IN => GT0_TXCHARISK_IN,
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- TXBUFSTATUS_OUT => GT0_TXBUFSTATUS_OUT,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTTXRESET_IN => GT0_GTTXRESET_IN,
- TXDATA_IN => GT0_TXDATA_IN,
- TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
- TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT,
- TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT,
- TXUSRCLK_IN => GT0_TXUSRCLK_IN,
- TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
- --------------------- Transmit Ports - PCI Express Ports -------------------
- txelecidle_in => gt0_txelecidle_in,
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- txprbsforceerr_in => gt0_txprbsforceerr_in,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTPTXN_OUT => GT0_GTPTXN_OUT,
- GTPTXP_OUT => GT0_GTPTXP_OUT,
- txdiffctrl_in => gt0_txdiffctrl_in,
- txmaincursor_in => gt0_txmaincursor_in,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- txpcsreset_in => gt0_txpcsreset_in,
- txinhibit_in => GT0_txinhibit_in,
- txpmareset_in => gt0_txpmareset_in,
- TXRESETDONE_OUT => GT0_TXRESETDONE_OUT,
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- txprbssel_in => gt0_txprbssel_in,
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- txpolarity_in => gt0_txpolarity_in
-
-
- );
-
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_rx_startup_fsm.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_rx_startup_fsm.vhd
deleted file mode 100644
index 9177c243c5bb274dd410413c02cdd6876df65a76..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_rx_startup_fsm.vhd
+++ /dev/null
@@ -1,978 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity north_channel_rx_startup_fsm is
- Generic(
- EXAMPLE_SIMULATION : integer := 0;
- GT_TYPE : string := "GTP";
- STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- RXPMARESETDONE : in STD_LOGIC;
- RXOUTCLK : in STD_LOGIC;
- TXPMARESETDONE : in STD_LOGIC;
- TXOUTCLK : in STD_LOGIC;
-
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- RXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- RECCLK_STABLE : in STD_LOGIC;
- RECCLK_MONITOR_RESTART : in STD_LOGIC:='0';
- DATA_VALID : in STD_LOGIC;
- TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
- DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected
- GTRXRESET : out STD_LOGIC;
- MMCM_RESET : out STD_LOGIC;
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0 (only if RX uses PLL0)
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1 (only if RX uses PLL1)
- RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
- RXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC;
- PHALIGNMENT_DONE : in STD_LOGIC;
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end north_channel_RX_STARTUP_FSM;
-
---Interdependencies:
--- * Timing depends on the frequency of the stable clock. Hence counters-sizes
--- are calculated at design-time based on the Generics
---
--- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
--- => signal which PLL has been reset
--- *
-
-
-
-architecture RTL of north_channel_RX_STARTUP_FSM is
-
- component north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
- type rx_rst_fsm_type is(
- INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
- RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
- MONITOR_DATA_VALID, FSM_DONE);
-
- signal rx_state : rx_rst_fsm_type := INIT;
-
- constant MMCM_LOCK_CNT_MAX : integer := 1024;
- constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
- constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
- constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
- constant WAIT_TIMEOUT_2ms : integer := 5000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
- constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
- constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out
- constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out
- constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
- constant WAIT_TIME_ADAPT : integer := (37000000 /integer(5.0))/STABLE_CLOCK_PERIOD;
- constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
-
- signal init_wait_count : integer range 0 to WAIT_MAX:=0;
- signal init_wait_done : std_logic := '0';
- signal pll_reset_asserted : std_logic := '0';
- signal rx_fsm_reset_done_int : std_logic := '0';
- signal rx_fsm_reset_done_int_s2 : std_logic := '0';
- signal rx_fsm_reset_done_int_s3 : std_logic := '0';
-
- signal rxresetdone_s2 : std_logic := '0';
- signal rxresetdone_s3 : std_logic := '0';
-
- constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
- signal retry_counter_int : integer range 0 to MAX_RETRIES := 0;
- signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
- signal recclk_mon_restart_count : integer range 0 to 3:= 0;
- signal recclk_mon_count_reset : std_logic := '0';
-
- signal reset_time_out : std_logic := '0';
- signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
- signal time_tlock_max : std_logic := '0';--|have been reached.
- signal time_out_500us : std_logic := '0';--|
- signal time_out_1us : std_logic := '0';--/
- signal time_out_100us : std_logic := '0';--/
- signal check_tlock_max : std_logic := '0';
-
- signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
- signal mmcm_lock_int : std_logic := '0';
- signal mmcm_lock_i : std_logic := '0';
- signal mmcm_lock_reclocked : std_logic := '0';
- signal gtrxreset_i : std_logic := '0';
- signal gtrxreset_s : std_logic := '0';
- signal mmcm_reset_i : std_logic := '1';
- signal rxpmaresetdone_i : std_logic := '0';
- signal txpmaresetdone_i : std_logic := '0';
- signal rxpmaresetdone_ss : std_logic := '0';
- signal rxpmaresetdone_sync : std_logic ;
- signal txpmaresetdone_sync : std_logic ;
- signal rxpmaresetdone_s : std_logic ;
- signal rxpmaresetdone_rx_s : std_logic ;
- signal pmaresetdone_fallingedge_detect : std_logic ;
- signal pmaresetdone_fallingedge_detect_s : std_logic ;
-
- signal run_phase_alignment_int: std_logic := '0';
- signal run_phase_alignment_int_s2 : std_logic := '0';
- signal run_phase_alignment_int_s3 : std_logic := '0';
-
- constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
- signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
- signal time_out_wait_bypass : std_logic := '0';
- signal time_out_wait_bypass_s2 : std_logic := '0';
- signal time_out_wait_bypass_s3 : std_logic := '0';
-
- signal refclk_lost : std_logic;
-
- signal data_valid_sync: std_logic := '0';
- signal pll0lock_sync: std_logic := '0';
- signal pll1lock_sync: std_logic := '0';
- signal pll0lock_prev: std_logic := '0';
- signal pll1lock_prev: std_logic := '0';
- signal pll0lock_ris_edge: std_logic := '0';
- signal pll1lock_ris_edge: std_logic := '0';
- signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
- signal wait_time_done : std_logic;
-begin
- --Alias section, signals used within this module mapped to output ports:
- RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
- RUN_PHALIGNMENT <= run_phase_alignment_int;
- RX_FSM_RESET_DONE <= rx_fsm_reset_done_int_s2;
- GTRXRESET <= gtrxreset_i;
- MMCM_RESET <= mmcm_reset_i;
- process(STABLE_CLOCK,SOFT_RESET)
- begin
- if (SOFT_RESET = '1') then
- init_wait_done <= '0';
- init_wait_count <= 0 ;
- elsif rising_edge(STABLE_CLOCK) then
- -- The counter starts running when configuration has finished and
- -- the clock is stable. When its maximum count-value has been reached,
- -- the 500 ns from Answer Record 43482 have been passed.
- if init_wait_count = WAIT_MAX then
- init_wait_done <= '1';
- else
- init_wait_count <= init_wait_count + 1;
- end if;
- end if;
- end process;
-
-
-
-
- process(RXOUTCLK,gtrxreset_s)
- begin
- if (gtrxreset_s = '1') then
- rxpmaresetdone_i <= '0';
- elsif rising_edge(RXOUTCLK) then
- rxpmaresetdone_i <= rxpmaresetdone_rx_s;
- end if;
- end process;
-
-gtrxreset_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => gtrxreset_i ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXOUTCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gtrxreset_s ,
- scndry_vect_out => open
- );
-
-sync_pmaresetdone_fallingedge_detect_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => pmaresetdone_fallingedge_detect ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXOUTCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pmaresetdone_fallingedge_detect_s ,
- scndry_vect_out => open
- );
-
-sync_rxpmaresetdone_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => RXOUTCLK ,
- prmry_resetn => '1' ,
- prmry_in => rxpmaresetdone_i ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxpmaresetdone_sync ,
- scndry_vect_out => open
- );
-
-sync_rxpmaresetdone_rx_s_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => RXPMARESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXOUTCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxpmaresetdone_rx_s ,
- scndry_vect_out => open
- );
-
-
-
- process(TXOUTCLK,gtrxreset_s)
- begin
- if (gtrxreset_s = '1') then
- txpmaresetdone_i <= '0';
- elsif rising_edge(TXOUTCLK) then
- txpmaresetdone_i <= TXPMARESETDONE;
- end if;
- end process;
-
-sync_txpmaresetdone_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => TXOUTCLK ,
- prmry_resetn => '1' ,
- prmry_in => txpmaresetdone_i ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => txpmaresetdone_sync ,
- scndry_vect_out => open
- );
-
- pmaresetdone_fallingedge_detect <= '0';
- retries_recclk_monitor:process(STABLE_CLOCK)
- begin
- --This counter monitors, how many retries the RECCLK monitor
- --runs. If during startup too many retries are necessary, the whole
- --initialisation-process of the transceivers gets restarted.
- if rising_edge(STABLE_CLOCK) then
- if recclk_mon_count_reset = '1' then
- recclk_mon_restart_count <= 0;
- elsif RECCLK_MONITOR_RESTART = '1' then
- if recclk_mon_restart_count = 3 then
- recclk_mon_restart_count <= 0;
- else
- recclk_mon_restart_count <= recclk_mon_restart_count + 1;
- end if;
- end if;
- end if;
- end process;
-
- timeouts:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- -- One common large counter for generating three time-out signals.
- -- Intermediate time-outs are derived from calculated values, based
- -- on the period of the provided clock.
- if reset_time_out = '1' then
- time_out_counter <= 0;
- time_out_2ms <= '0';
- time_tlock_max <= '0';
- time_out_500us <= '0';
- time_out_1us <= '0';
- time_out_100us <= '0';
- else
- if time_out_counter = WAIT_TIMEOUT_2ms then
- time_out_2ms <= '1';
- else
- time_out_counter <= time_out_counter + 1;
- end if;
-
- if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
- time_tlock_max <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_500us then
- time_out_500us <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_1us then
- time_out_1us <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_100us then
- time_out_100us <= '1';
- end if;
-
- end if;
- end if;
- end process;
-
-
-
- mmcm_lock_wait:process(STABLE_CLOCK)
- begin
- --The lock-signal from the MMCM is not immediately used but
- --enabling a counter. Only when the counter hits its maximum,
- --the MMCM is considered as "really" locked.
- --The counter avoids that the FSM already starts on only a
- --coarse lock of the MMCM (=toggling of the LOCK-signal).
- if rising_edge(STABLE_CLOCK) then
- if mmcm_lock_i = '0' then
- mmcm_lock_count <= 0;
- mmcm_lock_reclocked <= '0';
- else
- if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
- mmcm_lock_count <= mmcm_lock_count + 1;
- else
- mmcm_lock_reclocked <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
- -- Clock Domain Crossing
-
-sync_run_phase_alignment_int_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => run_phase_alignment_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => run_phase_alignment_int_s2 ,
- scndry_vect_out => open
- );
-
-sync_rx_fsm_reset_done_int_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => rx_fsm_reset_done_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => RXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rx_fsm_reset_done_int_s2 ,
- scndry_vect_out => open
- );
-
- process(RXUSERCLK)
- begin
- if rising_edge(RXUSERCLK) then
- run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
-
- rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
- end if;
- end process;
-
-sync_RXRESETDONE_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => RXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => RXRESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => rxresetdone_s2 ,
- scndry_vect_out => open
- );
-
-sync_time_out_wait_bypass_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => RXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => time_out_wait_bypass ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => time_out_wait_bypass_s2 ,
- scndry_vect_out => open
- );
-
-sync_mmcm_lock_reclocked_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => MMCM_LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => mmcm_lock_i ,
- scndry_vect_out => open
- );
-
- data_valid_sync <= DATA_VALID;
-
- process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- rxresetdone_s3 <= rxresetdone_s2;
-
- time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
- pll0lock_prev <= pll0lock_sync;
- pll1lock_prev <= pll1lock_sync;
- end if;
- end process;
-
-
-
-sync_PLL0LOCK_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL0LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll0lock_sync ,
- scndry_vect_out => open
- );
-
-sync_PLL1LOCK_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL1LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll1lock_sync ,
- scndry_vect_out => open
- );
-
-
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll0lock_ris_edge <= '0';
- elsif((pll0lock_prev = '0') and (pll0lock_sync = '1')) then
- pll0lock_ris_edge <= '1';
- elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
- pll0lock_ris_edge <= pll0lock_ris_edge;
- else
- pll0lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll1lock_ris_edge <= '0';
- elsif((pll1lock_prev = '0') and (pll1lock_sync = '1')) then
- pll1lock_ris_edge <= '1';
- elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
- pll1lock_ris_edge <= pll1lock_ris_edge;
- else
- pll1lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
- timeout_buffer_bypass:process(RXUSERCLK)
- begin
- if rising_edge(RXUSERCLK) then
- if run_phase_alignment_int_s3 = '0' then
- wait_bypass_count <= 0;
- time_out_wait_bypass <= '0';
- elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
- if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
- time_out_wait_bypass <= '1';
- else
- wait_bypass_count <= wait_bypass_count + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- refclk_lost <= '1' when ((RX_PLL0_USED and PLL0REFCLKLOST = '1') or (not RX_PLL0_USED and PLL1REFCLKLOST = '1')) else '0';
-
-
- timeout_max:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if((rx_state = ASSERT_ALL_RESETS) or
- (rx_state = RELEASE_MMCM_RESET)) then
- wait_time_cnt <= WAIT_TIME_MAX;
- elsif (wait_time_cnt > 0 ) then
- wait_time_cnt <= wait_time_cnt - 1;
- end if;
- end if;
- end process;
-
- wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
-
- --FSM for resetting the GTX/GTH/GTP in the 7-series.
- --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- --
- -- Following steps are performed:
- -- 1) After configuration wait for approximately 500 ns as specified in
- -- answer-record 43482
- -- 2) Assert all resets on the GT and on an MMCM potentially connected.
- -- After that wait until a reference-clock has been detected.
- -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
- -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
- -- Also get info from the TX-side which PLL has been reset.
- -- 5) Wait for the RESET_DONE-signal from the GT.
- -- 6) Signal to start the phase-alignment procedure and wait for it to
- -- finish.
- -- 7) Reset-sequence has successfully run through. Signal this to the
- -- rest of the design by asserting RX_FSM_RESET_DONE.
-
- reset_fsm:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if (SOFT_RESET = '1' ) then
- --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
- rx_state <= INIT;
- RXUSERRDY <= '0';
- gtrxreset_i <= '0';
- mmcm_reset_i <= '1';
- rx_fsm_reset_done_int <= '0';
- PLL0_RESET <= '0';
- PLL1_RESET <= '0';
- pll_reset_asserted <= '0';
- reset_time_out <= '1';
- retry_counter_int <= 0;
- run_phase_alignment_int <= '0';
- check_tlock_max <= '0';
- RESET_PHALIGNMENT <= '1';
- recclk_mon_count_reset <= '1';
-
- else
-
- case rx_state is
- when INIT =>
- --Initial state after configuration. This state will be left after
- --approx. 500 ns and not be re-entered.
- if init_wait_done = '1' then
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when ASSERT_ALL_RESETS =>
- --This is the state into which the FSM will always jump back if any
- --time-outs will occur.
- --The number of retries is reported on the output RETRY_COUNTER. In
- --case the transceiver never comes up for some reason, this machine
- --will still continue its best and rerun until the FPGA is turned off
- --or the transceivers come up correctly.
- if RX_PLL0_USED and not TX_PLL0_USED then
- if pll_reset_asserted = '0' then
- PLL0_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL0_RESET <= '0';
- end if;
- elsif not RX_PLL0_USED and TX_PLL0_USED then
- if pll_reset_asserted = '0' then
- PLL1_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL1_RESET <= '0';
- end if;
- end if;
-
- RXUSERRDY <= '0';
- gtrxreset_i <= '1';
- mmcm_reset_i <= '1';
- run_phase_alignment_int <= '0';
- RESET_PHALIGNMENT <= '1';
- check_tlock_max <= '0';
- recclk_mon_count_reset <= '1';
- if (RX_PLL0_USED and not TX_PLL0_USED and (pll0lock_sync = '0') and pll_reset_asserted = '1') or
- (not RX_PLL0_USED and TX_PLL0_USED and (pll1lock_sync = '0') and pll_reset_asserted = '1') or
- (RX_PLL0_USED and TX_PLL0_USED ) or
- (not RX_PLL0_USED and not TX_PLL0_USED ) then
- rx_state <= WAIT_FOR_PLL_LOCK;
- reset_time_out <= '1';
- end if;
-
- when WAIT_FOR_PLL_LOCK =>
- if(wait_time_done = '1') then
- rx_state <= RELEASE_PLL_RESET;
- end if;
-
- when RELEASE_PLL_RESET =>
- --PLL-Reset of the GTX gets released and the time-out counter
- --starts running.
- pll_reset_asserted <= '0';
- reset_time_out <= '0';
-
- if (RX_PLL0_USED and not TX_PLL0_USED and (pll0lock_sync = '1')) or
- (not RX_PLL0_USED and TX_PLL0_USED and (pll1lock_sync = '1')) then
- rx_state <= VERIFY_RECCLK_STABLE;
- reset_time_out <= '1';
- recclk_mon_count_reset <= '0';
- elsif (RX_PLL0_USED and (pll0lock_sync = '1')) or
- (not RX_PLL0_USED and (pll1lock_sync = '1')) then
- rx_state <= VERIFY_RECCLK_STABLE;
- reset_time_out <= '1';
- recclk_mon_count_reset <= '0';
- end if;
-
- if time_out_2ms = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when VERIFY_RECCLK_STABLE =>
- --reset_time_out <= '0';
- --Time-out counter is not released in this state as here the FSM
- --does not wait for a certain period of time but checks on the number
- --of retries in the RECCLK monitor
- gtrxreset_i <= '0';
- if RECCLK_STABLE = '1' then
- rx_state <= RELEASE_MMCM_RESET;
- reset_time_out <= '1';
-
- end if;
-
- if recclk_mon_restart_count = 2 then
- --If two retries are performed in the RECCLK monitor
- --the whole initialisation-sequence gets restarted.
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when RELEASE_MMCM_RESET =>
- --Release of the MMCM-reset. Waiting for the MMCM to lock.
- check_tlock_max <= '1';
-
- mmcm_reset_i <= '0';
- reset_time_out <= '0';
-
- if mmcm_lock_reclocked = '1' then
- rx_state <= WAIT_FOR_RXUSRCLK;
- reset_time_out <= '1';
- end if;
-
- if (time_tlock_max = '1' and reset_time_out = '0' )then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when WAIT_FOR_RXUSRCLK =>
- if wait_time_done = '1' then
- rx_state <= WAIT_RESET_DONE;
- end if;
-
- when WAIT_RESET_DONE =>
- --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
- --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
- if TXUSERRDY = '1' then
- RXUSERRDY <= '1';
- end if;
- reset_time_out <= '0';
- if rxresetdone_s3 = '1' then
- rx_state <= DO_PHASE_ALIGNMENT;
- reset_time_out <= '1';
- end if;
-
- if time_out_2ms = '1' and reset_time_out = '0' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when DO_PHASE_ALIGNMENT =>
- --The direct handling of the signals for the Phase Alignment is done outside
- --this state-machine.
- RESET_PHALIGNMENT <= '0';
- run_phase_alignment_int <= '1';
- reset_time_out <= '0';
-
- if PHALIGNMENT_DONE = '1' then
- rx_state <= MONITOR_DATA_VALID;
- reset_time_out <= '1';
- end if;
-
- if time_out_wait_bypass_s3 = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- rx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when MONITOR_DATA_VALID =>
- reset_time_out <= '0';
-
- if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then
- rx_state <= ASSERT_ALL_RESETS;
- rx_fsm_reset_done_int <= '0';
- elsif (data_valid_sync = '1') then
- rx_state <= FSM_DONE;
- rx_fsm_reset_done_int <= '0';
- reset_time_out <= '1';
- end if;
-
- when FSM_DONE =>
- reset_time_out <= '0';
- if data_valid_sync = '0' then
- rx_fsm_reset_done_int <= '0';
- reset_time_out <= '1';
- rx_state <= MONITOR_DATA_VALID;
- elsif(time_out_1us = '1' and reset_time_out = '0') then
- rx_fsm_reset_done_int <= '1';
- end if;
-
- when OTHERS =>
- rx_state <= INIT;
- end case;
- end if;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_transceiver_wrapper.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_transceiver_wrapper.vhd
deleted file mode 100644
index 70a5ef20f24a56165658e3107bc2e7b25a37cfd8..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_transceiver_wrapper.vhd
+++ /dev/null
@@ -1,849 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
--- Module north_channel_GT_WRAPPER
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
-entity north_channel_GT_WRAPPER is
-generic
-(
- QPLL_FBDIV_TOP : integer := 40;
- -- Simulation attribute
- EXAMPLE_SIMULATION : integer := 0;
- SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
-);
-
-port
-(
-
----------------------- Loopback and Powerdown Ports ----------------------
-LOOPBACK_IN : in std_logic_vector (2 downto 0);
---------------------- Receive Ports - 8b10b Decoder ----------------------
-RXCHARISCOMMA_OUT : out std_logic_vector (3 downto 0);
-RXCHARISK_OUT : out std_logic_vector (3 downto 0);
-RXDISPERR_OUT : out std_logic_vector (3 downto 0);
-RXNOTINTABLE_OUT : out std_logic_vector (3 downto 0);
------------------ Receive Ports - Channel Bonding Ports -----------------
-ENCHANSYNC_IN : in std_logic;
-CHBONDDONE_OUT : out std_logic;
------------------ Receive Ports - Clock Correction Ports -----------------
-RXBUFERR_OUT : out std_logic;
-------------- Receive Ports - Comma Detection and Alignment --------------
-RXREALIGN_OUT : out std_logic;
-ENMCOMMAALIGN_IN : in std_logic;
-ENPCOMMAALIGN_IN : in std_logic;
------------------ Receive Ports - RX Data Path interface -----------------
-RXDATA_OUT : out std_logic_vector (31 downto 0);
-RXRESET_IN : in std_logic;
-RXUSRCLK_IN : in std_logic;
-RXUSRCLK2_IN : in std_logic;
------ Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-RX1N_IN : in std_logic;
-RX1P_IN : in std_logic;
---------------- Receive Ports - RX Polarity Control Ports ----------------
-RXPOLARITY_IN : in std_logic;
-------------------- Shared Ports - Tile and PLL Ports --------------------
-REFCLK : in std_logic;
-INIT_CLK_IN : in std_logic;
-PLL_NOT_LOCKED : in std_logic;
-GTRESET_IN : in std_logic;
-PLLLKDET_OUT : out std_logic;
- gt0_txresetdone_out : out std_logic;
- gt0_rxresetdone_out : out std_logic;
- gt0_rxpmaresetdone_out : out std_logic;
- gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
- gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
-TX_RESETDONE_OUT : out std_logic;
-RX_RESETDONE_OUT : out std_logic;
--------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-TXCHARISK_IN : in std_logic_vector (3 downto 0);
----------------- Transmit Ports - TX Data Path interface -----------------
-TXDATA_IN : in std_logic_vector (31 downto 0);
-TXOUTCLK1_OUT : out std_logic;
-TXRESET_IN : in std_logic;
-TXUSRCLK_IN : in std_logic;
-TXUSRCLK2_IN : in std_logic;
-TXBUFERR_OUT : out std_logic;
-------------- Transmit Ports - TX Driver and OOB signalling --------------
-TX1N_OUT : out std_logic;
-TX1P_OUT : out std_logic;
----------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
-DRPADDR_IN : in std_logic_vector(8 downto 0);
-DRPCLK_IN : in std_logic;
-DRPDI_IN : in std_logic_vector(15 downto 0);
-DRPDO_OUT : out std_logic_vector(15 downto 0);
-DRPEN_IN : in std_logic;
-DRPRDY_OUT : out std_logic;
-DRPWE_IN : in std_logic;
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
-
-GTRXRESET_IN : in std_logic;
-LINK_RESET_IN : in std_logic;
-RXFSM_DATA_VALID : in std_logic;
-POWERDOWN_IN : in std_logic
-);
-
-end north_channel_GT_WRAPPER;
-
-
-architecture MAPPED of north_channel_GT_WRAPPER is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
- attribute core_generation_info : string;
-attribute core_generation_info of MAPPED : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- -- Parameter Declarations --
- constant DLY : time := 1 ns;
-
- component north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
-
---***************************** Compopnent Declaration ****************************
-
-component north_channel_tx_startup_fsm
- Generic(
- GT_TYPE : string := "GTP";
- STABLE_CLOCK_PERIOD : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- TXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- GTTXRESET : out STD_LOGIC:='0';
- MMCM_RESET : out STD_LOGIC:='0';
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1
- TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
- TXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC:='0';
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- PHALIGNMENT_DONE : in STD_LOGIC;
-
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end component;
-
-component north_channel_rx_startup_fsm
- Generic(
- EXAMPLE_SIMULATION : integer := 0;
- GT_TYPE : string := "GTP";
- STABLE_CLOCK_PERIOD : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- RXPMARESETDONE : in STD_LOGIC;
- RXOUTCLK : in STD_LOGIC;
- TXPMARESETDONE : in STD_LOGIC;
- TXOUTCLK : in STD_LOGIC;
-
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- RXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- RECCLK_STABLE : in STD_LOGIC;
- RECCLK_MONITOR_RESTART : in STD_LOGIC;
- DATA_VALID : in STD_LOGIC;
- TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
- DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
- GTRXRESET : out STD_LOGIC:='0';
- MMCM_RESET : out STD_LOGIC:='0';
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0 (only if RX uses PLL0)
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1 (only if RX uses PLL1)
- RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
- RXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC;
- PHALIGNMENT_DONE : in STD_LOGIC;
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end component;
-
-component north_channel_multi_gt is
-generic
-(
- -- Simulation attributes
- WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
-);
-port
-(
- STABLE_CLOCK : in std_logic; -- System Clock
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- --____________________________CHANNEL PORTS________________________________
- GT0_DRP_BUSY_OUT : out std_logic;
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
- GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
- GT0_DRPCLK_IN : in std_logic;
- GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
- GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
- GT0_DRPEN_IN : in std_logic;
- GT0_DRPRDY_OUT : out std_logic;
- GT0_DRPWE_IN : in std_logic;
- ------------------------ Loopback and Powerdown Ports ----------------------
- GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
- GT0_RXPD_IN : in std_logic_vector(1 downto 0);
- GT0_TXPD_IN : in std_logic_vector(1 downto 0);
- ------------------------------- Receive Ports ------------------------------
- GT0_eyescanreset_in : in std_logic;
- GT0_RXUSERRDY_IN : in std_logic;
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- GT0_rxprbserr_out : out std_logic;
- GT0_rxprbssel_in : in std_logic_vector(2 downto 0);
- ------------------- Receive Ports - Pattern Checker ports ------------------
- GT0_rxprbscntreset_in : in std_logic;
- -------------------------- RX Margin Analysis Ports ------------------------
- GT0_eyescandataerror_out : out std_logic;
- GT0_eyescantrigger_in : in std_logic;
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
- GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
- GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
- GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
- ------------------------- Receive Ports - AFE Ports ------------------------
- GT0_GTPRXN_IN : in std_logic;
- GT0_GTPRXP_IN : in std_logic;
- ------------------- Receive Ports - Clock Correction Ports -----------------
- GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GT0_rxbyteisaligned_out : out std_logic;
- GT0_RXBYTEREALIGN_OUT : out std_logic;
- GT0_rxcommadet_out : out std_logic;
- GT0_RXMCOMMAALIGNEN_IN : in std_logic;
- GT0_RXPCOMMAALIGNEN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GT0_GTRXRESET_IN : in std_logic;
- GT0_rxpcsreset_in : in std_logic;
- GT0_rxpmareset_in : in std_logic;
- GT0_rxlpmreset_in : in std_logic;
- GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
- GT0_RXOUTCLK_OUT : out std_logic;
- GT0_RXUSRCLK_IN : in std_logic;
- GT0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GT0_RXCDRLOCK_OUT : out std_logic;
- GT0_RXLPMHFHOLD_IN : in std_logic;
- GT0_RXLPMLFHOLD_IN : in std_logic;
- GT0_rxlpmhfovrden_in : in std_logic;
- GT0_rxcdrhold_in : in std_logic;
- GT0_dmonitorout_out : out std_logic_vector(14 downto 0);
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GT0_rxbufreset_in : in std_logic;
- GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GT0_RXRESETDONE_OUT : out std_logic;
- GT0_RXPMARESETDONE_OUT : out std_logic;
- ------------------------ TX Configurable Driver Ports ----------------------
- GT0_txpostcursor_in : in std_logic_vector(4 downto 0);
- GT0_txprecursor_in : in std_logic_vector(4 downto 0);
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- GT0_RXPOLARITY_IN : in std_logic;
- ------------------------------- Transmit Ports -----------------------------
- GT0_TXUSERRDY_IN : in std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GT0_txchardispmode_in : in std_logic_vector(3 downto 0);
- GT0_txchardispval_in : in std_logic_vector(3 downto 0);
- GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
- GT0_TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GT0_GTTXRESET_IN : in std_logic;
- GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
- GT0_TXOUTCLK_OUT : out std_logic;
- GT0_TXOUTCLKFABRIC_OUT : out std_logic;
- GT0_TXOUTCLKPCS_OUT : out std_logic;
- GT0_TXUSRCLK_IN : in std_logic;
- GT0_TXUSRCLK2_IN : in std_logic;
- --------------------- Transmit Ports - PCI Express Ports -------------------
- GT0_txelecidle_in : in std_logic;
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- GT0_txprbsforceerr_in : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GT0_GTPTXN_OUT : out std_logic;
- GT0_GTPTXP_OUT : out std_logic;
- GT0_txdiffctrl_in : in std_logic_vector(3 downto 0);
- GT0_txmaincursor_in : in std_logic_vector(6 downto 0);
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GT0_txpcsreset_in : in std_logic;
- GT0_txinhibit_in : in std_logic;
- GT0_txpmareset_in : in std_logic;
- GT0_TXRESETDONE_OUT : out std_logic;
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- GT0_txprbssel_in : in std_logic_vector(2 downto 0);
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- GT0_txpolarity_in : in std_logic;
-
-
- --____________________________COMMON PORTS________________________________
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
- GT0_PLL0RESET_IN : in std_logic
-
-);
-end component;
-
-
- function get_cdrlock_time(is_sim : in integer) return integer is
- variable lock_time: integer;
- begin
- if (is_sim = 1) then
- lock_time := 1000;
- else
- lock_time := 50000 / integer(5.0); --Typical CDR lock time is 50,000UI as per DS181
- end if;
- return lock_time;
- end function;
-
---***********************************Parameter Declarations********************
-
- constant STABLE_CLOCK_PERIOD : integer := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
- constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
-
- signal tied_to_ground_i : std_logic;
- signal tied_to_ground_vec_i : std_logic_vector (63 downto 0);
- signal tied_to_vcc_i : std_logic;
-signal chbondi : std_logic_vector (3 downto 0);
-signal chbondo : std_logic_vector (3 downto 0);
- signal chbondi_unused_i : std_logic_vector (3 downto 0);
-
- signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
- signal rx_cdrlocked : std_logic;
- signal gt_recclk_stable_i : std_logic;
- signal gt_pll0refclklost_i : std_logic;
- signal gt_pll_lock_i : std_logic;
- signal gt0_txresetdone_i : std_logic;
- signal gt0_rxresetdone_i : std_logic;
- signal txfsm_txresetdone_i : std_logic;
- signal rxfsm_rxresetdone_i : std_logic;
- signal txfsm_txresetdone_r : std_logic;
- signal rxfsm_rxresetdone_r : std_logic;
- signal rxfsm_rxresetdone_r1 : std_logic;
- signal rxfsm_rxresetdone_r2 : std_logic;
- signal rxfsm_rxresetdone_r3 : std_logic;
- signal gt_tx_reset_i : std_logic;
- signal gt_rx_reset_i : std_logic;
- signal fsm_gt_rx_reset_t : std_logic;
- signal rxfsm_soft_reset_r : std_logic;
- signal gt_txuserrdy_i : std_logic;
- signal gt_rxuserrdy_i : std_logic;
- signal mmcm_lock_i : std_logic;
- signal mmcm_reset_i : std_logic;
-
- signal gtrxreset_sync : std_logic;
- signal gtrxreset_r1 : std_logic;
- signal gtrxreset_r2 : std_logic;
- signal gtrxreset_r3 : std_logic;
- signal gtrxreset_pulse : std_logic;
-
-
---Timing closure flipflops
- signal gt0_txresetdone_r : std_logic;
- signal gt0_txresetdone_r2 : std_logic;
- signal gt0_txresetdone_r3 : std_logic;
- signal gt0_rxresetdone_r : std_logic;
- signal gt0_rxresetdone_r2 : std_logic;
- signal gt0_rxresetdone_r3 : std_logic;
-
- signal link_reset_r : std_logic;
- signal link_reset_r2 : std_logic;
-
- signal common_reset_i : std_logic;
-
- --concatenation or temp signals
- signal powerdown_i : std_logic_vector(1 downto 0);
-signal rx_buf_status_i : std_logic_vector(2 downto 0);
-signal tx_buf_status_i : std_logic_vector(1 downto 0);
-
- signal gt0_txpmaresetdone_o : std_logic;
- signal TXOUTCLK_OUT : std_logic;
- signal gt_txpmaresetdone_i : std_logic;
- signal gt_txoutclk_out : std_logic;
-
-begin
-
- tied_to_ground_i <= '0';
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');
- tied_to_vcc_i <= '1';
-
-
- powerdown_i <= POWERDOWN_IN & POWERDOWN_IN;
- RXBUFERR_OUT <= rx_buf_status_i(2);
- TXBUFERR_OUT <= tx_buf_status_i(1);
- TXOUTCLK1_OUT <= TXOUTCLK_OUT;
-
-
- chbondi_unused_i <= "0000";
-
-
- --Connect channel bonding bus
-
- chbondi <= chbondi_unused_i;
- CHBONDDONE_OUT <= '1';
-
- gtrxreset_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => RXUSRCLK2_IN ,
- prmry_resetn => '1' ,
- prmry_in => GTRXRESET_IN ,
- prmry_vect_in => "00" ,
- scndry_aclk => INIT_CLK_IN ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gtrxreset_sync ,
- scndry_vect_out => open
- );
-
- process(INIT_CLK_IN)
- begin
- if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
- gtrxreset_r1 <= gtrxreset_sync after DLY;
- gtrxreset_r2 <= gtrxreset_r1 after DLY;
- gtrxreset_r3 <= gtrxreset_r2 after DLY;
- gtrxreset_pulse <= gtrxreset_r2 AND (NOT gtrxreset_r3) after DLY;
- end if;
- end process;
-
- process(INIT_CLK_IN)
- begin
- if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
- link_reset_r <= LINK_RESET_IN after DLY;
- link_reset_r2 <= link_reset_r after DLY;
- gt_rx_reset_i <= fsm_gt_rx_reset_t after DLY;
- rxfsm_soft_reset_r <= link_reset_r2 or GTRESET_IN or gtrxreset_pulse after DLY;
- end if;
- end process;
-
- mmcm_lock_i <= (not PLL_NOT_LOCKED);
-
- gt_common_reset_out <= common_reset_i;
-
- gt_pll0refclklost_i <= gt0_pll0refclklost_in;
-
- PLLLKDET_OUT <= quad1_common_lock_in and (not mmcm_reset_i);
-
- gt_pll_lock_i <= quad1_common_lock_in;
-
- gt0_txresetdone_out <= gt0_txresetdone_i;
- gt0_rxresetdone_out <= gt0_rxresetdone_i;
- gt0_txbufstatus_out <= tx_buf_status_i;
- gt0_rxbufstatus_out <= rx_buf_status_i;
-
- --TXRESETDONE for lane0
- process(TXUSRCLK2_IN)
- begin
- if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
- gt0_txresetdone_r <= gt0_txresetdone_i after DLY;
- gt0_txresetdone_r2 <= gt0_txresetdone_r after DLY;
- gt0_txresetdone_r3 <= gt0_txresetdone_r2 after DLY;
- end if;
- end process;
-
- --RXRESETDONE for lane0
- process(RXUSRCLK2_IN)
- begin
- if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
- gt0_rxresetdone_r <= gt0_rxresetdone_i after DLY;
- gt0_rxresetdone_r2 <= gt0_rxresetdone_r after DLY;
- gt0_rxresetdone_r3 <= gt0_rxresetdone_r2 after DLY;
- end if;
- end process;
-
-
- txfsm_txresetdone_i <= gt0_txresetdone_r3 ;
- rxfsm_rxresetdone_i <= gt0_rxresetdone_r3 ;
-
- process(TXUSRCLK2_IN)
- begin
- if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
- txfsm_txresetdone_r <= txfsm_txresetdone_i after DLY;
- end if;
- end process;
-
- process(RXUSRCLK2_IN)
- begin
- if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
- rxfsm_rxresetdone_r <= rxfsm_rxresetdone_i after DLY;
- rxfsm_rxresetdone_r2 <= rxfsm_rxresetdone_r after DLY;
- rxfsm_rxresetdone_r3 <= rxfsm_rxresetdone_r2 after DLY;
- end if;
- end process;
-
-
- process(RXUSRCLK2_IN)
- begin
- if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
- rxfsm_rxresetdone_r1 <= rxfsm_rxresetdone_i after DLY;
- end if;
- end process;
-
- RX_RESETDONE_OUT <= rxfsm_rxresetdone_r3;
-
- gt_txpmaresetdone_i <= '0';
-
-
-gt_txresetfsm_i: north_channel_tx_startup_fsm
-
- generic map(
- GT_TYPE => "GTP", --GTX or GTH or GTP
- STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH => 8,
- TX_PLL0_USED => TRUE , -- the TX and RX Reset FSMs must
- RX_PLL0_USED => TRUE, -- share these two generic values
- PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- )
- port map (
-
- STABLE_CLOCK => INIT_CLK_IN,
- TXUSERCLK => TXUSRCLK2_IN,
- SOFT_RESET => GTRESET_IN,
- PLL0REFCLKLOST => gt_pll0refclklost_i,
- PLL0LOCK => gt_pll_lock_i,
- PLL1REFCLKLOST => tied_to_ground_i,
- PLL1LOCK => tied_to_vcc_i,
- TXRESETDONE => txfsm_txresetdone_r,
- MMCM_LOCK => mmcm_lock_i,
- GTTXRESET => gt_tx_reset_i,
- MMCM_RESET => mmcm_reset_i,
- PLL0_RESET => common_reset_i,
- PLL1_RESET => open,
- TX_FSM_RESET_DONE => TX_RESETDONE_OUT,
- TXUSERRDY => gt_txuserrdy_i,
- RUN_PHALIGNMENT => open,
- RESET_PHALIGNMENT => open ,
- PHALIGNMENT_DONE => tied_to_vcc_i,
- RETRY_COUNTER => open
- );
-
-
-
-gt_rxresetfsm_i: north_channel_rx_startup_fsm
-
- generic map(
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
- GT_TYPE => "GTP", --GTX or GTH or GTP
- STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH => 8,
- TX_PLL0_USED => TRUE , -- the TX and RX Reset FSMs must
- RX_PLL0_USED => TRUE, -- share these two generic values
- PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- )
- port map (
- STABLE_CLOCK => INIT_CLK_IN,
- RXUSERCLK => RXUSRCLK2_IN,
- SOFT_RESET => rxfsm_soft_reset_r,
- RXPMARESETDONE => gt_txpmaresetdone_i,
- RXOUTCLK => RXUSRCLK2_IN,
- TXPMARESETDONE => tied_to_vcc_i,
- TXOUTCLK => TXUSRCLK2_IN,
-
- DONT_RESET_ON_DATA_ERROR => '0',
- PLL0REFCLKLOST => gt_pll0refclklost_i,
- PLL0LOCK => gt_pll_lock_i,
- PLL1REFCLKLOST => tied_to_ground_i,
- PLL1LOCK => tied_to_vcc_i,
- RXRESETDONE => rxfsm_rxresetdone_r1,
- MMCM_LOCK => tied_to_vcc_i,
- RECCLK_STABLE => gt_recclk_stable_i,
- RECCLK_MONITOR_RESTART => tied_to_ground_i,
- DATA_VALID => gt_rxuserrdy_i,
- TXUSERRDY => gt_txuserrdy_i,
- GTRXRESET => fsm_gt_rx_reset_t,
- MMCM_RESET => open,
- PLL0_RESET => open,
- PLL1_RESET => open,
- RX_FSM_RESET_DONE => open,
- RXUSERRDY => gt_rxuserrdy_i,
- RUN_PHALIGNMENT => open,
- RESET_PHALIGNMENT => open,
- PHALIGNMENT_DONE => tied_to_vcc_i,
- RETRY_COUNTER => open
- );
-
- cdrlock_timeout:process(INIT_CLK_IN)
- begin
- if rising_edge(INIT_CLK_IN) then
- if(gt_rx_reset_i = '1') then
- rx_cdrlocked <= '0';
- rx_cdrlock_counter <= 0 after DLY;
- elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
- rx_cdrlocked <= '1';
- rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
- else
- rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
- end if;
- end if;
- end process;
-
-gt_recclk_stable_i <= rx_cdrlocked;
-
-
- north_channel_multi_gt_i : north_channel_multi_gt
- generic map
- (
- -- Simulation attributes
- WRAPPER_SIM_GTRESET_SPEEDUP => SIM_GTRESET_SPEEDUP
-
- )
- port map
- (
- STABLE_CLOCK => INIT_CLK_IN,
- --_________________________________________________________________________
- --_________________________________________________________________________
- --GT0
- --____________________________CHANNEL PORTS________________________________
- GT0_DRP_BUSY_OUT => open,
- ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
-GT0_DRPADDR_IN => DRPADDR_IN,
-GT0_DRPCLK_IN => DRPCLK_IN,
-GT0_DRPDI_IN => DRPDI_IN,
-GT0_DRPDO_OUT => DRPDO_OUT,
-GT0_DRPEN_IN => DRPEN_IN,
-GT0_DRPRDY_OUT => DRPRDY_OUT,
-GT0_DRPWE_IN => DRPWE_IN,
- ------------------------ Loopback and Powerdown Ports ----------------------
- GT0_LOOPBACK_IN => LOOPBACK_IN,
- GT0_RXPD_IN => powerdown_i,
- GT0_TXPD_IN => powerdown_i,
- ------------------------------- Receive Ports ------------------------------
- GT0_RXUSERRDY_IN => gt_rxuserrdy_i,
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
-GT0_RXCHARISCOMMA_OUT => RXCHARISCOMMA_OUT,
-GT0_RXCHARISK_OUT => RXCHARISK_OUT,
-GT0_RXDISPERR_OUT => RXDISPERR_OUT,
-GT0_RXNOTINTABLE_OUT => RXNOTINTABLE_OUT,
- ------------------------- Receive Ports - AFE Ports ------------------------
-GT0_GTPRXN_IN => RX1N_IN,
-GT0_GTPRXP_IN => RX1P_IN,
- ------------------- Receive Ports - Clock Correction Ports -----------------
- GT0_RXCLKCORCNT_OUT => open,
- --------------- Receive Ports - Comma Detection and Alignment --------------
-GT0_RXBYTEREALIGN_OUT => RXREALIGN_OUT,
-GT0_RXMCOMMAALIGNEN_IN => ENMCOMMAALIGN_IN,
-GT0_RXPCOMMAALIGNEN_IN => ENPCOMMAALIGN_IN,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GT0_GTRXRESET_IN => gt_rx_reset_i,
-GT0_RXDATA_OUT => RXDATA_OUT,
- GT0_RXOUTCLK_OUT => open,
- GT0_RXUSRCLK_IN => RXUSRCLK_IN,
- GT0_RXUSRCLK2_IN => RXUSRCLK2_IN,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GT0_RXCDRLOCK_OUT => open,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-GT0_RXBUFSTATUS_OUT => rx_buf_status_i,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
- GT0_RXPMARESETDONE_OUT => gt0_rxpmaresetdone_out,
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
-GT0_RXPOLARITY_IN => RXPOLARITY_IN,
- ------------------------------- Transmit Ports -----------------------------
- GT0_TXUSERRDY_IN => gt_txuserrdy_i,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-GT0_TXCHARISK_IN => TXCHARISK_IN,
- ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
-GT0_TXBUFSTATUS_OUT => tx_buf_status_i,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GT0_GTTXRESET_IN => gt_tx_reset_i,
-GT0_TXDATA_IN => TXDATA_IN,
-GT0_TXOUTCLK_OUT => TXOUTCLK_OUT,
- GT0_TXOUTCLKFABRIC_OUT => open,
- GT0_TXOUTCLKPCS_OUT => open,
- GT0_TXUSRCLK_IN => TXUSRCLK_IN,
- GT0_TXUSRCLK2_IN => TXUSRCLK2_IN,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-GT0_GTPTXN_OUT => TX1N_OUT,
-GT0_GTPTXP_OUT => TX1P_OUT,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
- --------------------- Transmit Ports - PCI Express Ports -------------------
- gt0_txelecidle_in => POWERDOWN_IN,
-
- gt0_rxlpmhfhold_in => tied_to_ground_i,
- gt0_rxlpmlfhold_in => tied_to_ground_i,
- gt0_eyescanreset_in => tied_to_ground_i,
- -------------------------- RX Margin Analysis Ports ------------------------
- gt0_eyescandataerror_out => open,
- gt0_eyescantrigger_in => tied_to_ground_i,
- gt0_rxbyteisaligned_out => open,
- gt0_rxcommadet_out => open,
- ------------------------ TX Configurable Driver Ports ----------------------
- gt0_txpostcursor_in => "00000",
- gt0_txprecursor_in => "00000",
- ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
- gt0_txchardispmode_in => "0000",
- gt0_txchardispval_in => "0000",
- gt0_txdiffctrl_in => "1000",
- gt0_txmaincursor_in => "0000000",
- ----------------- Transmit Ports - TX Polarity Control Ports ---------------
- gt0_txpolarity_in => tied_to_ground_i,
- ------------------- Receive Ports - Pattern Checker Ports ------------------
- gt0_rxprbserr_out => open,
- gt0_rxprbssel_in => "000",
- ------------------- Receive Ports - Pattern Checker ports ------------------
- gt0_rxprbscntreset_in => tied_to_ground_i,
- ------------------- Receive Ports - RX Data Path interface -----------------
- gt0_rxpcsreset_in => tied_to_ground_i,
- gt0_rxpmareset_in => tied_to_ground_i,
- gt0_rxlpmreset_in => tied_to_ground_i,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- gt0_rxlpmhfovrden_in => tied_to_ground_i,
- gt0_rxcdrhold_in => tied_to_ground_i,
- gt0_dmonitorout_out => open,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- gt0_rxbufreset_in => tied_to_ground_i,
- ------------------ Transmit Ports - Pattern Generator Ports ----------------
- gt0_txprbsforceerr_in => tied_to_ground_i,
- gt0_txprbssel_in => "000",
- ------------------- Transmit Ports - TX Data Path interface -----------------
- gt0_txpcsreset_in => tied_to_ground_i,
- gt0_txinhibit_in => tied_to_ground_i,
- gt0_txpmareset_in => tied_to_ground_i,
- --____________________________COMMON PORTS________________________________
- GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
- GT0_PLL0RESET_IN => common_reset_i
- );
-
-end MAPPED;
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_tx_startup_fsm.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_tx_startup_fsm.vhd
deleted file mode 100644
index 21375471531a95c5cd523e387af2e2dce6651c83..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/gt/north_channel_tx_startup_fsm.vhd
+++ /dev/null
@@ -1,724 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity north_channel_tx_startup_fsm is
- Generic(
- GT_TYPE : string := "GTP";
- EXAMPLE_SIMULATION : integer := 0;
-
- STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
- RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
- TX_PLL0_USED : boolean := False; -- the TX and RX Reset FSMs must
- RX_PLL0_USED : boolean := False; -- share these two generic values
- PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
- -- is enough. For single-lane applications the automatic alignment is
- -- sufficient
- );
- Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
- --or reference-clock present at startup.
- TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
- SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
- PLL0REFCLKLOST : in STD_LOGIC; --PLL0 Reference-clock for the GT is lost
- PLL1REFCLKLOST : in STD_LOGIC; --PLL1 Reference-clock for the GT is lost
- PLL0LOCK : in STD_LOGIC; --Lock Detect from the PLL0 of the GT
- PLL1LOCK : in STD_LOGIC; --Lock Detect from the PLL1 of the GT
- TXRESETDONE : in STD_LOGIC;
- MMCM_LOCK : in STD_LOGIC;
- GTTXRESET : out STD_LOGIC;
- MMCM_RESET : out STD_LOGIC:='1';
- PLL0_RESET : out STD_LOGIC:='0'; --Reset PLL0
- PLL1_RESET : out STD_LOGIC:='0'; --Reset PLL1
- TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
- TXUSERRDY : out STD_LOGIC:='0';
- RUN_PHALIGNMENT : out STD_LOGIC:='0';
- RESET_PHALIGNMENT : out STD_LOGIC:='0';
- PHALIGNMENT_DONE : in STD_LOGIC;
-
- RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
- -- Retries it took to get the transceiver up and running
- );
-end north_channel_TX_STARTUP_FSM;
-
---Interdependencies:
--- * Timing depends on the frequency of the stable clock. Hence counters-sizes
--- are calculated at design-time based on the Generics
---
--- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
--- => signal which PLL has been reset
--- *
-
-
-
-architecture RTL of north_channel_TX_STARTUP_FSM is
-
- component north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
- type tx_rst_fsm_type is(
- INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
- WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
- RESET_FSM_DONE);
-
- signal tx_state : tx_rst_fsm_type := INIT;
-
- constant MMCM_LOCK_CNT_MAX : integer := 1024;
- constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
- constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
- constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
-
- constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
- constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
- constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out
- constant WAIT_1us_cycles : integer := 1000 / STABLE_CLOCK_PERIOD;--1 us time-out
- constant WAIT_1us : integer := WAIT_1us_cycles+ 10; -- 1us plus some additional margin
-
- signal init_wait_count : integer range 0 to WAIT_MAX:=0;
- signal init_wait_done : std_logic := '0';
- signal pll_reset_asserted : std_logic := '0';
-
- signal tx_fsm_reset_done_int : std_logic := '0';
- signal tx_fsm_reset_done_int_s2 : std_logic := '0';
- signal tx_fsm_reset_done_int_s3 : std_logic := '0';
-
- signal txresetdone_s2 : std_logic := '0';
- signal txresetdone_s3 : std_logic := '0';
-
- constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
- signal retry_counter_int : integer range 0 to MAX_RETRIES;
- signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
-
- signal reset_time_out : std_logic := '0';
- signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
- signal time_tlock_max : std_logic := '0';--|have been reached.
- signal time_out_500us : std_logic := '0';--/
-
- signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
- signal mmcm_lock_int : std_logic := '0';
- signal mmcm_lock_i : std_logic := '0';
- signal mmcm_lock_reclocked : std_logic := '0';
-
- signal run_phase_alignment_int : std_logic := '0';
- signal run_phase_alignment_int_s2 : std_logic := '0';
- signal run_phase_alignment_int_s3 : std_logic := '0';
- constant MAX_WAIT_BYPASS : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
-
- constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
-
- signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
- signal time_out_wait_bypass : std_logic := '0';
- signal time_out_wait_bypass_s2 : std_logic := '0';
- signal time_out_wait_bypass_s3 : std_logic := '0';
- signal txuserrdy_i : std_logic := '0';
- signal refclk_lost : std_logic;
- signal gttxreset_i : std_logic := '0';
- signal txpmaresetdone_i : std_logic := '0';
- signal txpmaresetdone_sync : std_logic ;
-
- signal pll0lock_sync: std_logic := '0';
- signal pll1lock_sync: std_logic := '0';
- signal pll0lock_prev: std_logic := '0';
- signal pll1lock_prev: std_logic := '0';
- signal pll0lock_ris_edge: std_logic := '0';
- signal pll1lock_ris_edge: std_logic := '0';
- signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
- signal wait_time_done :std_logic;
-
-begin
- --Alias section, signals used within this module mapped to output ports:
- RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
- RUN_PHALIGNMENT <= run_phase_alignment_int;
- TX_FSM_RESET_DONE <= tx_fsm_reset_done_int_s2;
- GTTXRESET <= gttxreset_i;
-
- process(STABLE_CLOCK,SOFT_RESET)
- begin
- if (SOFT_RESET = '1') then
- init_wait_done <= '0';
- init_wait_count <= 0 ;
- elsif rising_edge(STABLE_CLOCK) then
- -- The counter starts running when configuration has finished and
- -- the clock is stable. When its maximum count-value has been reached,
- -- the 500 ns from Answer Record 43482 have been passed.
- if init_wait_count = WAIT_MAX then
- init_wait_done <= '1';
- else
- init_wait_count <= init_wait_count + 1;
- end if;
- end if;
- end process;
-
- timeouts:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- -- One common large counter for generating three time-out signals.
- -- Intermediate time-outs are derived from calculated values, based
- -- on the period of the provided clock.
- if reset_time_out = '1' then
- time_out_counter <= 0;
- time_out_2ms <= '0';
- time_tlock_max <= '0';
- time_out_500us <= '0';
- else
- if time_out_counter = WAIT_TIMEOUT_2ms then
- time_out_2ms <= '1';
- else
- time_out_counter <= time_out_counter + 1;
- end if;
-
- if time_out_counter = WAIT_TLOCK_MAX then
- time_tlock_max <= '1';
- end if;
-
- if time_out_counter = WAIT_TIMEOUT_500us then
- time_out_500us <= '1';
- end if;
- end if;
- end if;
- end process;
-
- mmcm_lock_wait:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if mmcm_lock_i = '0' then
- mmcm_lock_count <= 0;
- mmcm_lock_reclocked <= '0';
- else
- if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
- mmcm_lock_count <= mmcm_lock_count + 1;
- else
- mmcm_lock_reclocked <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
-
- -- Clock Domain Crossing
-
-sync_run_phase_alignment_int_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => run_phase_alignment_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => TXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => run_phase_alignment_int_s2 ,
- scndry_vect_out => open
- );
-
-sync_tx_fsm_reset_done_int_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
-port map
- (
- prmry_aclk => STABLE_CLOCK ,
- prmry_resetn => '1' ,
- prmry_in => tx_fsm_reset_done_int ,
- prmry_vect_in => "00" ,
- scndry_aclk => TXUSERCLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => tx_fsm_reset_done_int_s2 ,
- scndry_vect_out => open
- );
-
- process(TXUSERCLK)
- begin
- if rising_edge(TXUSERCLK) then
- run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
-
- tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2;
- end if;
- end process;
-
-sync_TXRESETDONE_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => TXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => TXRESETDONE ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => txresetdone_s2 ,
- scndry_vect_out => open
- );
-
-sync_time_out_wait_bypass_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => TXUSERCLK ,
- prmry_resetn => '1' ,
- prmry_in => time_out_wait_bypass ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => time_out_wait_bypass_s2 ,
- scndry_vect_out => open
- );
-
-sync_mmcm_lock_reclocked_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => MMCM_LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => mmcm_lock_i ,
- scndry_vect_out => open
- );
-
- process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- txresetdone_s3 <= txresetdone_s2;
-
- time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
- pll0lock_prev <= pll0lock_sync;
- pll1lock_prev <= pll1lock_sync;
- end if;
- end process;
-
-
-
-sync_PLL0LOCK_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL0LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll0lock_sync ,
- scndry_vect_out => open
- );
-
-sync_PLL1LOCK_cdc_sync : north_channel_cdc_sync
-generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
-port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => PLL1LOCK ,
- prmry_vect_in => "00" ,
- scndry_aclk => STABLE_CLOCK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll1lock_sync ,
- scndry_vect_out => open
- );
-
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll0lock_ris_edge <= '0';
- elsif((pll0lock_prev = '0') and (pll0lock_sync = '1')) then
- pll0lock_ris_edge <= '1';
- elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
- pll0lock_ris_edge <= pll0lock_ris_edge;
- else
- pll0lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
- process (STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1' ) then
- pll1lock_ris_edge <= '0';
- elsif((pll1lock_prev = '0') and (pll1lock_sync = '1')) then
- pll1lock_ris_edge <= '1';
- elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
- pll1lock_ris_edge <= pll1lock_ris_edge;
- else
- pll1lock_ris_edge <= '0';
- end if;
- end if;
- end process;
-
-
- timeout_buffer_bypass:process(TXUSERCLK)
- begin
- if rising_edge(TXUSERCLK) then
- if run_phase_alignment_int_s3 = '0' then
- wait_bypass_count <= 0;
- time_out_wait_bypass <= '0';
- elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then
- if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
- time_out_wait_bypass <= '1';
- else
- wait_bypass_count <= wait_bypass_count + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- refclk_lost <= '1' when ((TX_PLL0_USED and PLL0REFCLKLOST = '1') or (not TX_PLL0_USED and PLL1REFCLKLOST = '1')) else '0';
-
- timeout_max:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if((tx_state = ASSERT_ALL_RESETS) or
- (tx_state = RELEASE_PLL_RESET) or
- (tx_state = RELEASE_MMCM_RESET)) then
- wait_time_cnt <= WAIT_TIME_MAX;
- elsif (wait_time_cnt > 0 ) then
- wait_time_cnt <= wait_time_cnt - 1;
- end if;
- end if;
- end process;
-
- wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
-
- --FSM for resetting the GTX/GTH/GTP in the 7-series.
- --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- --
- -- Following steps are performed:
- -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
- -- answer-record 43482
- -- 2) Assert all resets on the GT and on an MMCM potentially connected.
- -- After that wait until a reference-clock has been detected.
- -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
- -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
- -- Also signal to the RX-side which PLL has been reset.
- -- 5) Wait for the RESET_DONE-signal from the GT.
- -- 6) Signal to start the phase-alignment procedure and wait for it to
- -- finish.
- -- 7) Reset-sequence has successfully run through. Signal this to the
- -- rest of the design by asserting TX_FSM_RESET_DONE.
-
- reset_fsm:process(STABLE_CLOCK)
- begin
- if rising_edge(STABLE_CLOCK) then
- if(SOFT_RESET = '1') then
- --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
- tx_state <= INIT;
- TXUSERRDY <= '0';
- gttxreset_i <= '0';
- MMCM_RESET <= '0';
- tx_fsm_reset_done_int <= '0';
- PLL0_RESET <= '0';
- PLL1_RESET <= '0';
- pll_reset_asserted <= '0';
- reset_time_out <= '0';
- retry_counter_int <= 0;
- run_phase_alignment_int <= '0';
- RESET_PHALIGNMENT <= '1';
- else
-
- case tx_state is
- when INIT =>
- --Initial state after configuration. This state will be left after
- --approx. 500 ns and not be re-entered.
- if init_wait_done = '1' then
- tx_state <= ASSERT_ALL_RESETS;
- reset_time_out <= '1';
- end if;
-
- when ASSERT_ALL_RESETS =>
- --This is the state into which the FSM will always jump back if any
- --time-outs will occur.
- --The number of retries is reported on the output RETRY_COUNTER. In
- --case the transceiver never comes up for some reason, this machine
- --will still continue its best and rerun until the FPGA is turned off
- --or the transceivers come up correctly.
- if TX_PLL0_USED then
- if pll_reset_asserted = '0' then
- PLL0_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL0_RESET <= '0';
- end if;
- else
- if pll_reset_asserted = '0' then
- PLL1_RESET <= '1';
- pll_reset_asserted <= '1';
- else
- PLL1_RESET <= '0';
- end if;
- end if;
- TXUSERRDY <= '0';
- gttxreset_i <= '1';
- MMCM_RESET <= '1';
- reset_time_out <= '0';
- run_phase_alignment_int <= '0';
- RESET_PHALIGNMENT <= '1';
-
- if (TX_PLL0_USED and (pll0lock_sync = '0') and pll_reset_asserted = '1') or
- (not TX_PLL0_USED and (pll1lock_sync = '0') and pll_reset_asserted = '1') then
- tx_state <= WAIT_FOR_PLL_LOCK;
- end if;
-
- when WAIT_FOR_PLL_LOCK =>
- if(wait_time_done = '1') then
- tx_state <= RELEASE_PLL_RESET;
- end if;
-
- when RELEASE_PLL_RESET =>
- --PLL-Reset of the GTX gets released and the time-out counter
- --starts running.
- pll_reset_asserted <= '0';
-
- if (TX_PLL0_USED and (pll0lock_sync = '1')) or
- (not TX_PLL0_USED and (pll1lock_sync = '1')) then
- tx_state <= WAIT_FOR_TXOUTCLK;
- reset_time_out <= '1';
- end if;
-
- if time_out_2ms = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when WAIT_FOR_TXOUTCLK =>
- gttxreset_i <= '0';
- if(wait_time_done = '1') then
- tx_state <= RELEASE_MMCM_RESET;
- end if;
-
- when RELEASE_MMCM_RESET =>
- --Release of the MMCM-reset. Waiting for the MMCM to lock.
- MMCM_RESET <= '0';
- reset_time_out <= '0';
- if mmcm_lock_reclocked = '1' then
- tx_state <= WAIT_FOR_TXUSRCLK;
- reset_time_out <= '1';
- end if;
-
- if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when WAIT_FOR_TXUSRCLK =>
- if(wait_time_done = '1') then
- tx_state <= WAIT_RESET_DONE;
- end if;
-
- when WAIT_RESET_DONE =>
- TXUSERRDY <= '1';
- reset_time_out <= '0';
- if txresetdone_s3 = '1' then
- tx_state <= DO_PHASE_ALIGNMENT;
- reset_time_out <= '1';
- end if;
-
- if (time_out_500us = '1' and reset_time_out = '0') then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when DO_PHASE_ALIGNMENT =>
- --The direct handling of the signals for the Phase Alignment is done outside
- --this state-machine.
- RESET_PHALIGNMENT <= '0';
- run_phase_alignment_int <= '1';
- reset_time_out <= '0';
-
- if PHALIGNMENT_DONE = '1' then
- tx_state <= RESET_FSM_DONE;
- end if;
-
- if time_out_wait_bypass_s3 = '1' then
- if retry_counter_int = MAX_RETRIES then
- -- If too many retries are performed compared to what is specified in
- -- the generic, the counter simply wraps around.
- retry_counter_int <= 0;
- else
- retry_counter_int <= retry_counter_int + 1;
- end if;
- tx_state <= ASSERT_ALL_RESETS;
- end if;
-
- when RESET_FSM_DONE =>
- reset_time_out <= '1';
- tx_fsm_reset_done_int <= '1';
-
- when OTHERS =>
- tx_state <= INIT;
-
- end case;
- end if;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_aurora_lane_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_aurora_lane_4byte.vhd
deleted file mode 100644
index 7c89ffcf875cae06baa31add586e011bfdc69e85..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_aurora_lane_4byte.vhd
+++ /dev/null
@@ -1,786 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------/
---
--- AURORA_LANE_4BYTE
---
---
--- Description: the AURORA_LANE_4BYTE module provides a full duplex 4-byte
--- aurora lane connection using a single GTX. The module handles
--- lane initialization, symbol generation and decoding and error
--- detection. It also decodes some of the channel bonding
--- indicator signals needed by the Global logic.
---
--- * Supports Virtex-5
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_AURORA_LANE_4BYTE is
- generic (
- EXAMPLE_SIMULATION : integer := 0
- );
- port (
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- 4-byte data bus from the GTX.
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- Invalid 10-bit code was recieved.
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- Disparity error detected on RX interface.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Indicates which bytes of RX_DATA are control.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Comma received on given byte.
- RX_STATUS : in std_logic_vector(5 downto 0); -- Part of GT_11 status and error bus
- RX_BUF_ERR : in std_logic; -- Overflow/Underflow of RX buffer detected.
- TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
- RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
- RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
- RX_RESET : out std_logic; -- Reset RX side of GTX logic.
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- TX_DATA byte is a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- 4-byte data bus to the GTX.
- TX_RESET : out std_logic; -- Reset TX side of GTX logic.
- LINK_RESET_OUT : out std_logic; -- Link reset for hotplug scenerio.
- HPCNT_RESET : in std_logic; -- Hotplug count reset input.
- INIT_CLK : in std_logic;
-
- -- Comma Detect Phase Align Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
-
- -- TX_LL Interface
-
- GEN_SCP : in std_logic_vector(0 to 1); -- SCP generation request from TX_LL.
- GEN_ECP : in std_logic_vector(0 to 1); -- ECP generation request from TX_LL.
- GEN_SUF : in std_logic_vector(0 to 1); -- SUF generation request from TX_LL
- GEN_PAD : in std_logic_vector(0 to 1); -- PAD generation request from TX_LL
- FC_NB : in std_logic_vector(0 to 7); -- Size code for SUF and SNF messages
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data from TX_LL to send over lane.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Indicates TX_PE_DATA is Valid.
- GEN_CC : in std_logic; -- CC generation request from TX_LL.
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- Indicates lane received PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- RX data from lane to RX_LL.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- RX_PE_DATA is data, not control symbol.
- RX_SCP : out std_logic_vector(0 to 1); -- Indicates lane received SCP.
- RX_ECP : out std_logic_vector(0 to 1); -- Indicates lane received ECP
- RX_SUF : out std_logic_vector(0 to 1); -- Indicates lane received SUF
- RX_FC_NB : out std_logic_vector(0 to 7); -- Size code for SNF or SUF
-
- -- Global Logic Interface
-
- GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
- GEN_K : in std_logic_vector(0 to 3); -- 'K character' generation request from Global Logic.
- GEN_R : in std_logic_vector(0 to 3); -- 'R character' generation request from Global Logic.
- GEN_V : in std_logic_vector(0 to 3); -- Verification data generation request.
- LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
- SOFT_ERR : out std_logic_vector(0 to 1); -- Soft error detected.
- HARD_ERR : out std_logic; -- Hard error detected.
- CHANNEL_BOND_LOAD : out std_logic; -- Channel Bongding done code recieved.
- GOT_A : out std_logic_vector(0 to 3); -- Indicates lane recieved 'A character' bytes.
- GOT_V : out std_logic; -- Verification symbols received.
- CHANNEL_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET_SYMGEN : in std_logic; -- Reset the SYM_GEN module.
- RESET : in std_logic -- Reset the lane.
-
- );
-
-end north_channel_AURORA_LANE_4BYTE;
-
-architecture RTL of north_channel_AURORA_LANE_4BYTE is
-
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- Wire Declarations --
-
- signal rx_cc_i : std_logic;
- signal ena_comma_align_i : std_logic;
- signal gen_sp_i : std_logic;
- signal gen_spa_i : std_logic;
- signal rx_sp_i : std_logic;
- signal rx_spa_i : std_logic;
- signal rx_neg_i : std_logic;
- signal enable_err_detect_i : std_logic;
- signal do_word_align_i : std_logic;
- signal hard_err_reset_i : std_logic;
-
- signal tx_char_is_k_i : std_logic_vector(3 downto 0);
- signal tx_data_i : std_logic_vector(31 downto 0);
- signal rx_data_i : std_logic_vector(31 downto 0);
- signal rx_char_is_k_i : std_logic_vector(3 downto 0);
- signal rx_char_is_comma_i : std_logic_vector(3 downto 0);
- signal rx_disp_err_i : std_logic_vector(3 downto 0);
- signal rx_not_in_table_i : std_logic_vector(3 downto 0);
- signal LANE_UP_Buffer : std_logic;
-
- -- Scrambler signals
- signal gen_v_r : std_logic;
- signal gen_v_r2 : std_logic;
- signal scrambler_reset_i : std_logic;
- signal TX_DATA_Buffer : std_logic_vector(31 downto 0);
- signal TX_CHAR_IS_K_Buffer : std_logic_vector(3 downto 0);
-
- -- Descrambler signals
- signal descrambler_reset_i : std_logic;
- signal rx_pad_descram_in : std_logic_vector(0 to 1);
- signal rx_pe_data_descram_in : std_logic_vector(0 to 31);
- signal rx_pe_data_v_descram_in : std_logic_vector(0 to 1);
- signal rx_scp_descram_in : std_logic_vector(0 to 1);
- signal rx_ecp_descram_in : std_logic_vector(0 to 1);
- signal rx_suf_descram_in : std_logic_vector(0 to 1);
- signal rx_fc_nb_descram_in : std_logic_vector(0 to 7);
- signal rx_sp_descram_in : std_logic;
- signal rx_spa_descram_in : std_logic;
- signal rx_neg_descram_in : std_logic;
- signal got_a_descram_in : std_logic_vector(0 to 3);
- signal got_v_descram_in : std_logic;
-
-
--- Component Declarations --
-
- component north_channel_LANE_INIT_SM_4BYTE
-
- port (
-
- -- GTX Interface
-
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- GTX received invalid 10b code
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- GTX received 10b code w/ wrong disparity
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- GTX received a Comma
- RX_REALIGN : in std_logic; -- GTX had to change alignment due to new comma
- RX_RESET : out std_logic; -- Reset the RX side of the GTX
- TX_RESET : out std_logic; -- Reset the TX side of the GTX
- RX_POLARITY : out std_logic; -- Sets polarity used to interpet rx'ed symbols
-
- -- Comma Detect Phase Alignment Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Turn on SERDES Alignment in GTX
-
- -- Symbol Generator Interface
-
- GEN_SP : out std_logic; -- Generate SP symbol
- GEN_SPA : out std_logic; -- Generate SPA symbol
-
- -- Symbol Decoder Interface
-
- RX_SP : in std_logic; -- Lane rx'ed SP sequence w/ + or - data
- RX_SPA : in std_logic; -- Lane rx'ed SPA sequence
- RX_NEG : in std_logic; -- Lane rx'ed inverted SP or SPA data
- DO_WORD_ALIGN : out std_logic; -- Enable word alignment
-
- -- Error Detection Logic Interface
-
- ENABLE_ERR_DETECT : out std_logic; -- Turn on Soft Error detection
- HARD_ERR_RESET : in std_logic; -- Reset lane due to hard error
-
- -- Global Logic Interface
-
- LANE_UP : out std_logic; -- Lane is initialized
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora logic
- RESET : in std_logic -- Reset Aurora Lane
-
- );
-
- end component;
-
-
- component north_channel_CHBOND_COUNT_DEC_4BYTE
-
- port (
-
- RX_STATUS : in std_logic_vector(5 downto 0);
- CHANNEL_BOND_LOAD : out std_logic;
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_SYM_GEN_4BYTE
-
- port (
-
- -- TX_LL Interface -- See description for info about GEN_PAD and TX_PE_DATA_V.
-
- GEN_SCP : in std_logic_vector(0 to 1); -- Generate SCP.
- GEN_ECP : in std_logic_vector(0 to 1); -- Generate ECP.
- GEN_SUF : in std_logic_vector(0 to 1); -- Generate SUF using code given by FC_NB.
- GEN_PAD : in std_logic_vector(0 to 1); -- Replace LSB with Pad character.
- FC_NB : in std_logic_vector(0 to 7); -- Size code for Flow Control messages.
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data. Transmitted when TX_PE_DATA_V is asserted.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Transmit data.
- GEN_CC : in std_logic; -- Generate Clock Correction symbols.
-
- -- Global Logic Interface -- See description for info about GEN_K,GEN_R and GEN_A.
-
- GEN_A : in std_logic; -- Generate A character for MSBYTE
- GEN_K : in std_logic_vector(0 to 3); -- Generate K character for selected bytes.
- GEN_R : in std_logic_vector(0 to 3); -- Generate R character for selected bytes.
- GEN_V : in std_logic_vector(0 to 3); -- Generate Ver data character on selected bytes.
-
- -- Lane Init SM Interface
-
- GEN_SP : in std_logic; -- Generate SP pattern.
- GEN_SPA : in std_logic; -- Generate SPA pattern.
-
- -- GTX Interface
-
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- Transmit TX_DATA as a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- Data to GTX for transmission to channel partner.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora Logic.
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_SYM_DEC_4BYTE
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed.
- LANE_UP : in std_logic; -- Lane is up
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- Raw RX data from GTX.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Bits indicating which bytes are control characters.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Rx'ed a comma.
- RX_CC : out std_logic; -- CC pattern.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_ERR_DETECT_4BYTE is
-
- port (
-
- -- Lane Init SM Interface
-
- ENABLE_ERR_DETECT : in std_logic;
- HARD_ERR_RESET : out std_logic;
-
- -- Global Logic Interface
-
- SOFT_ERR : out std_logic_vector(0 to 1);
- HARD_ERR : out std_logic;
-
- -- GTX Interface
-
- RX_DISP_ERR : in std_logic_vector(3 downto 0);
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0);
- RX_BUF_ERR : in std_logic;
- TX_BUF_ERR : in std_logic;
- RX_REALIGN : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-component north_channel_HOTPLUG
-generic
-(
- ENABLE_HOTPLUG : integer := 1;
- EXAMPLE_SIMULATION : integer := 0
-);
-port
-(
-
- ---------------------- Sym Dec Interface -------------------------------
- RX_CC : in std_logic;
- RX_SP : in std_logic;
- RX_SPA : in std_logic;
-
- ---------------------- GT Wrapper Interface ----------------------------
- LINK_RESET_OUT : out std_logic;
- HPCNT_RESET : in std_logic;
-
- ---------------------- System Interface ----------------------------
- INIT_CLK : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
-
-);
-end component;
-
-
- component north_channel_SCRAMBLER_TOP
-
- port (
-
- DATA_OUT : OUT std_logic_vector(31 downto 0);
- CHAR_IS_K_OUT : OUT std_logic_vector(3 downto 0);
-
- DATA : IN std_logic_vector(31 downto 0);
- CHAR_IS_K : IN std_logic_vector(3 downto 0);
- CLEAR : IN std_logic;
- RESET : IN std_logic;
- USER_CLK : IN std_logic
-
- );
-
- end component;
-
- component north_channel_DESCRAMBLER_TOP
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- RX_PAD_IN : in std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA_IN : in std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V_IN : in std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP_IN : in std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP_IN : in std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF_IN : in std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB_IN : in std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- RX_SP_IN : in std_logic; -- SP sequence received with positive or negative data.
- RX_SPA_IN : in std_logic; -- SPA sequence received.
- RX_NEG_IN : in std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- RX_CC : out std_logic; -- CC sequence received.
-
- GOT_A_IN : in std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V_IN : in std_logic; -- V sequence received.
-
- RX_CC_IN : in std_logic; -- CC sequence received.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- CLEAR : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
-begin
-
-
- -- Buffers for twisting data from GTX --
- -- To reuse the Pro Aurora logic, we twist the data to make it compatible.
- TX_CHAR_IS_K <= TX_CHAR_IS_K_Buffer(0) & TX_CHAR_IS_K_Buffer(1) & TX_CHAR_IS_K_Buffer(2) & TX_CHAR_IS_K_Buffer(3);
- TX_DATA <= TX_DATA_Buffer(7 downto 0) & TX_DATA_Buffer(15 downto 8) & TX_DATA_Buffer(23 downto 16) & TX_DATA_Buffer(31 downto 24);
- rx_data_i <= RX_DATA(7 downto 0) & RX_DATA(15 downto 8) & RX_DATA(23 downto 16) & RX_DATA(31 downto 24);
- rx_char_is_k_i <= RX_CHAR_IS_K(0) & RX_CHAR_IS_K(1) & RX_CHAR_IS_K(2) & RX_CHAR_IS_K(3);
- rx_char_is_comma_i <= RX_CHAR_IS_COMMA(0) & RX_CHAR_IS_COMMA(1) & RX_CHAR_IS_COMMA(2) & RX_CHAR_IS_COMMA(3);
- rx_disp_err_i <= RX_DISP_ERR(0) & RX_DISP_ERR(1) & RX_DISP_ERR(2) & RX_DISP_ERR(3);
- rx_not_in_table_i <= RX_NOT_IN_TABLE(0) & RX_NOT_IN_TABLE(1) & RX_NOT_IN_TABLE(2) & RX_NOT_IN_TABLE(3);
-
- LANE_UP <= LANE_UP_Buffer;
-
--- Main Body of Code --
-
- -- Lane Initialization state machine
-
- north_channel_lane_init_sm_4byte_i : north_channel_LANE_INIT_SM_4BYTE
-
- port map (
-
- -- GTX Interface
-
- RX_NOT_IN_TABLE => RX_NOT_IN_TABLE,
- RX_DISP_ERR => RX_DISP_ERR,
- RX_CHAR_IS_COMMA => RX_CHAR_IS_COMMA,
- RX_REALIGN => RX_REALIGN,
- RX_RESET => RX_RESET,
- TX_RESET => TX_RESET,
- RX_POLARITY => RX_POLARITY,
-
- -- Comma Detect Phase Alignment Interface
-
- ENA_COMMA_ALIGN => ENA_COMMA_ALIGN,
-
- -- Symbol Generator Interface
-
- GEN_SP => gen_sp_i,
- GEN_SPA => gen_spa_i,
-
- -- Symbol Decoder Interface
-
- RX_SP => rx_sp_i,
- RX_SPA => rx_spa_i,
- RX_NEG => rx_neg_i,
- DO_WORD_ALIGN => do_word_align_i,
-
- -- Error Detection Logic Interface
-
- HARD_ERR_RESET => hard_err_reset_i,
- ENABLE_ERR_DETECT => enable_err_detect_i,
-
- -- Global Logic Interface
-
- LANE_UP => LANE_UP_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
- -- Channel Bonding Count Decode module
-
- north_channel_chbond_count_dec_4byte_i : north_channel_CHBOND_COUNT_DEC_4BYTE
-
- port map (
-
- RX_STATUS => RX_STATUS,
- CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
- USER_CLK => USER_CLK
-
- );
-
-
- -- Symbol Generation module
-
- north_channel_sym_gen_4byte_i : north_channel_SYM_GEN_4BYTE
-
- port map (
-
- -- TX_LL Interface
-
- GEN_SCP => GEN_SCP,
- GEN_ECP => GEN_ECP,
- GEN_SUF => GEN_SUF,
- GEN_PAD => GEN_PAD,
- FC_NB => FC_NB,
- TX_PE_DATA => TX_PE_DATA,
- TX_PE_DATA_V => TX_PE_DATA_V,
- GEN_CC => GEN_CC,
-
- -- Global Logic Interface
-
- GEN_A => GEN_A,
- GEN_K => GEN_K,
- GEN_R => GEN_R,
- GEN_V => GEN_V,
-
- -- Lane Init SM Interface
-
- GEN_SP => gen_sp_i,
- GEN_SPA => gen_spa_i,
-
- -- GT Interface
-
- TX_CHAR_IS_K => tx_char_is_k_i,
- TX_DATA => tx_data_i,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET_SYMGEN
-
- );
-
-
- -- Symbol Decode module
-
- north_channel_sym_dec_4byte_i : north_channel_SYM_DEC_4BYTE
-
- port map (
-
- -- RX_LL Interface
-
- RX_PAD => rx_pad_descram_in,
- RX_PE_DATA => rx_pe_data_descram_in,
- RX_PE_DATA_V => rx_pe_data_v_descram_in,
- RX_SCP => rx_scp_descram_in,
- RX_ECP => rx_ecp_descram_in,
- RX_SUF => rx_suf_descram_in,
- RX_FC_NB => rx_fc_nb_descram_in,
-
- -- Lane Init SM Interface
-
- DO_WORD_ALIGN => do_word_align_i,
- LANE_UP => LANE_UP_Buffer,
- RX_SP => rx_sp_descram_in,
- RX_SPA => rx_spa_descram_in,
- RX_NEG => rx_neg_descram_in,
-
- -- Global Logic Interface
-
- GOT_A => got_a_descram_in,
- GOT_V => got_v_descram_in,
-
- -- GT Interface
-
- RX_DATA => rx_data_i,
- RX_CHAR_IS_K => rx_char_is_k_i,
- RX_CHAR_IS_COMMA => rx_char_is_comma_i,
- RX_CC => rx_cc_i,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
- -- Error Detection module
-
- north_channel_err_detect_4byte_i : north_channel_ERR_DETECT_4BYTE
-
- port map (
-
- -- Lane Init SM Interface
-
- ENABLE_ERR_DETECT => enable_err_detect_i,
- HARD_ERR_RESET => hard_err_reset_i,
-
- -- Global Logic Interface
-
- SOFT_ERR => SOFT_ERR,
- HARD_ERR => HARD_ERR,
-
- -- GTX Interface
-
- RX_DISP_ERR => rx_disp_err_i,
- RX_NOT_IN_TABLE => rx_not_in_table_i,
- RX_BUF_ERR => RX_BUF_ERR,
- TX_BUF_ERR => TX_BUF_ERR,
- RX_REALIGN => RX_REALIGN,
-
- -- System Interface
-
- USER_CLK => USER_CLK
-
- );
-
- -- Hot Plug module
- north_channel_hotplug_i : north_channel_HOTPLUG
- generic map
- (
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION
- )
- port map
- (
- -- Sym Dec Interface
- RX_CC => rx_cc_i,
- RX_SP => rx_sp_i,
- RX_SPA => rx_spa_i,
-
- -- GT Wrapper Interface
- LINK_RESET_OUT => LINK_RESET_OUT,
- HPCNT_RESET => HPCNT_RESET,
-
- -- System Interface
- INIT_CLK => INIT_CLK,
- USER_CLK => USER_CLK,
- RESET => RESET
- );
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- gen_v_r <= OR_REDUCE(GEN_V) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- gen_v_r2 <= gen_v_r after DLY;
-
- end if;
-
- end process;
-
- scrambler_reset_i <= gen_v_r2 or (not CHANNEL_UP) or RESET;
-
- -- Scrambler
- north_channel_scrambler_top_i : north_channel_SCRAMBLER_TOP
-
- port map
- (
- DATA_OUT => TX_DATA_Buffer,
- CHAR_IS_K_OUT => TX_CHAR_IS_K_Buffer,
-
- DATA => tx_data_i,
- CHAR_IS_K => tx_char_is_k_i,
- CLEAR => GEN_CC,
- RESET => scrambler_reset_i, -- Applied during initialization; not expected after scrambler started operation
- USER_CLK => USER_CLK
- );
-
- descrambler_reset_i <= (not CHANNEL_UP) or RESET;
-
- -- Descrambler
- north_channel_descrambler_top_i : north_channel_DESCRAMBLER_TOP
-
- port map
- (
- -- RX_LL Interface
-
-
- RX_PAD => RX_PAD,
- RX_PE_DATA => RX_PE_DATA,
- RX_PE_DATA_V => RX_PE_DATA_V,
- RX_SCP => RX_SCP,
- RX_ECP => RX_ECP,
- RX_SUF => RX_SUF,
- RX_FC_NB => RX_FC_NB,
-
- RX_PAD_IN => rx_pad_descram_in,
- RX_PE_DATA_IN => rx_pe_data_descram_in,
- RX_PE_DATA_V_IN => rx_pe_data_v_descram_in,
- RX_SCP_IN => rx_scp_descram_in,
- RX_ECP_IN => rx_ecp_descram_in,
- RX_SUF_IN => rx_suf_descram_in,
- RX_FC_NB_IN => rx_fc_nb_descram_in,
-
- -- Lane Init SM Interface
-
- RX_SP => rx_sp_i,
- RX_SPA => rx_spa_i,
- RX_NEG => rx_neg_i,
-
- RX_SP_IN => rx_sp_descram_in,
- RX_SPA_IN => rx_spa_descram_in,
- RX_NEG_IN => rx_neg_descram_in,
-
- -- Global Logic Interface
-
- GOT_A_IN => got_a_descram_in,
- GOT_V_IN => got_v_descram_in,
-
- RX_CC_IN => rx_cc_i,
-
- GOT_A => GOT_A,
- GOT_V => GOT_V,
-
- RX_CC => OPEN,
- CLEAR => '0',
- RESET => descrambler_reset_i, -- Applied during initialization; not expected after descrambler started operation
- USER_CLK => USER_CLK
- );
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_aurora_pkg.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_aurora_pkg.vhd
deleted file mode 100644
index 3ceea680decbfd6f230abcc76b7e3d705970f0fb..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_aurora_pkg.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- AURORA
---
---
--- Description: Aurora Package Definition
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use STD.TEXTIO.all;
-
-package AURORA_PKG is
-
- function std_bool (EXP_IN : in boolean) return std_logic;
-
-end;
-
-package body AURORA_PKG is
-
- function std_bool (EXP_IN : in boolean) return std_logic is
-
- begin
-
- if (EXP_IN) then
-
- return('1');
-
- else
-
- return('0');
-
- end if;
-
- end std_bool;
-
-end;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_axi_to_ll.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_axi_to_ll.vhd
deleted file mode 100644
index a1f353a98c49725e598094a42bacbc2163e9d760..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_axi_to_ll.vhd
+++ /dev/null
@@ -1,165 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
---
--- AXI_TO_LL
---
---
--- Description: This light wrapper/shim convertes Legacy LocalLink interface
--- signals from AXI-4 Stream protocol signals
---
---
-------------------------------------------------------------------------------/
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_AXI_TO_LL is
-generic
-(
- DATA_WIDTH : integer := 16; -- DATA bus width
- STRB_WIDTH : integer := 2; -- STROBE bus width
- REM_WIDTH : integer := 1; -- REM bus width
- USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC
- USE_UFC_REM : integer := 0 -- UFC REM bus width identifier
-);
-
-port
-(
-
- ---------------------- AXI4-S Interface -------------------------------
-
- AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_IP_TX_TVALID : in std_logic;
- AXI4_S_IP_TX_TLAST : in std_logic;
- AXI4_S_OP_TX_TREADY : out std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1);
- LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1);
- LL_OP_SRC_RDY_N : out std_logic;
- LL_OP_SOF_N : out std_logic;
- LL_OP_EOF_N : out std_logic;
- LL_IP_DST_RDY_N : in std_logic;
-
- ---------------------- System Interface ----------------------------
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : in std_logic
-
-);
-
-end north_channel_AXI_TO_LL;
-
-architecture BEHAVIORAL of north_channel_AXI_TO_LL is
- attribute core_generation_info : string;
-attribute core_generation_info of BEHAVIORAL : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
- signal new_pkt_r : std_logic;
- signal new_pkt : std_logic;
- signal temp_cond : std_logic;
- signal ll_op_sof : std_logic;
- signal ll_ip_dst_rdy : std_logic;
- signal AXI4_S_IP_TX_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1);
-
-begin
-
---*********************************Main Body of Code**********************************
-
-
-
- ll_ip_dst_rdy <= not LL_IP_DST_RDY_N;
-
- LL_OP_DATA <= AXI4_S_IP_TX_TDATA;
-
-
- AXI4_S_IP_TX_TKEEP_i <= AXI4_S_IP_TX_TKEEP;
-
-
-
-
- LL_OP_SRC_RDY_N <= not AXI4_S_IP_TX_TVALID;
- LL_OP_EOF_N <= not AXI4_S_IP_TX_TLAST;
-
-LL_OP_REM <= ("0" & AXI4_S_IP_TX_TKEEP_i(0)) + ("0" & AXI4_S_IP_TX_TKEEP_i(1)) + ("0" & AXI4_S_IP_TX_TKEEP_i(2)) + ("0" & AXI4_S_IP_TX_TKEEP_i(3)) - '1';
-
- new_pkt <= '0' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
- '1' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND not AXI4_S_IP_TX_TLAST) = '1') else
- new_pkt_r;
-
- temp_cond <= '0' when (new_pkt_r = '1') else
- '1';
- ll_op_sof <= temp_cond when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
- (new_pkt and (not new_pkt_r));
-
- LL_OP_SOF_N <= not ll_op_sof;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- if(RESET = '1') then
- new_pkt_r <= '0' after DLY;
- elsif(CHANNEL_UP = '1') then
- new_pkt_r <= new_pkt after DLY;
- else
- new_pkt_r <= '0' after DLY;
- end if;
- end if;
- end process;
-
- -- Assign output from temp signal
- AXI4_S_OP_TX_TREADY <= ll_ip_dst_rdy;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_cdc_sync.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_cdc_sync.vhd
deleted file mode 100644
index d0d23bda2e7c48c7ff7bbb0001a6e2875baa0e7e..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_cdc_sync.vhd
+++ /dev/null
@@ -1,741 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------
-
---Generic Help
---C_CDC_TYPE : Defines the type of CDC needed
--- 0 means pulse synchronizer. Used to transfer one clock pulse
--- from prmry domain to scndry domain.
--- 1 means level synchronizer. Used to transfer level signal.
--- 2 means level synchronizer with ack. Used to transfer level
--- signal. Input signal should change only when prmry_ack is detected
---
---C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
--- Set to 0 when incoming signal is purely floped signal.
---
---C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
--- it might be needed.
--- 0 means reset not needed for sync flops
--- 1 means reset needed for sync flops. i
--- In this case prmry_resetn should be in prmry clock,
--- while scndry_reset should be in scndry clock.
---
---C_SINGLE_BIT : CDC should normally be done for single bit signals only.
--- However, based on design buses can also be CDC'ed.
--- 0 means it is a bus. In this case input be connected to prmry_vect_in.
--- Output is on scndry_vect_out.
--- 1 means it is a single bit. In this case input be connected to prmry_in.
--- Output is on scndry_out.
---
---C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
---
---C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
--- Value of 0, 1 is allowed only for level CDC.
--- Min value for Pulse CDC is 2
---
---Whenever this file is used following XDC constraint has to be added
-
--- set_false_path -to [get_pins -hier *north_channel_cdc_to*/D]
-
-
---IO Ports
---
--- prmry_aclk : clock of originating domain (source domain)
--- prmry_resetn : sync reset of originating clock domain (source domain)
--- prmry_in : input signal bit. This should be a pure flop output without
--- any combi logic. This is source.
--- prmry_vect_in : bus signal. From Source domain.
--- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
--- Used only when C_CDC_TYPE = 2
--- scndry_aclk : destination clock.
--- scndry_resetn : sync reset of destination domain
--- scndry_out : sync'ed output in destination domain. Single bit.
--- scndry_vect_out : sync'ed output in destination domain. bus.
-
-
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_misc.all;
-
-
-
-entity north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
-end north_channel_cdc_sync;
-
--------------------------------------------------------------------------------
--- Architecture
--------------------------------------------------------------------------------
-architecture implementation of north_channel_cdc_sync is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-
--------------------------------------------------------------------------------
--- Functions
--------------------------------------------------------------------------------
-
--- No Functions Declared
-
--------------------------------------------------------------------------------
--- Constants Declarations
--------------------------------------------------------------------------------
-
--- No Constants Declared
-
--------------------------------------------------------------------------------
--- Begin architecture logic
--------------------------------------------------------------------------------
-begin
--- Generate PULSE clock domain crossing
-GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-
--- Primary to Secondary
-signal s_out_d1_north_channel_cdc_to : std_logic := '0';
-signal s_out_d2 : std_logic := '0';
-signal s_out_d3 : std_logic := '0';
-signal s_out_d4 : std_logic := '0';
-signal s_out_d5 : std_logic := '0';
-signal s_out_d6 : std_logic := '0';
-signal s_out_d7 : std_logic := '0';
-signal s_out_re : std_logic := '0';
-signal prmry_in_xored : std_logic := '0';
-signal p_in_d1_cdc_from : std_logic := '0';
-
-
-
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_out_d1_north_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d6 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_out_d7 : SIGNAL IS "true";
-
- ATTRIBUTE shift_extract : STRING;
- ATTRIBUTE shift_extract OF s_out_d1_north_channel_cdc_to : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d2 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d3 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d4 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d5 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d6 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_out_d7 : SIGNAL IS "no";
-
-begin
-
- --*****************************************************************************
- --** Asynchronous Pulse Clock Crossing **
- --** PRIMARY TO SECONDARY OPEN-ENDED **
- --*****************************************************************************
-
-prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
-
- REG_P_IN : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_in_d1_cdc_from <= '0';
- else
- p_in_d1_cdc_from <= prmry_in_xored;
- end if;
- end if;
- end process REG_P_IN;
-
-
- P_IN_CROSS2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_out_d1_north_channel_cdc_to <= '0';
- s_out_d2 <= '0';
- s_out_d3 <= '0';
- s_out_d4 <= '0';
- s_out_d5 <= '0';
- s_out_d6 <= '0';
- s_out_d7 <= '0';
- scndry_out <= '0';
- else
- s_out_d1_north_channel_cdc_to <= p_in_d1_cdc_from;
- s_out_d2 <= s_out_d1_north_channel_cdc_to;
- s_out_d3 <= s_out_d2;
- s_out_d4 <= s_out_d3;
- s_out_d5 <= s_out_d4;
- s_out_d6 <= s_out_d5;
- s_out_d7 <= s_out_d6;
- scndry_out <= s_out_re;
- end if;
- end if;
- end process P_IN_CROSS2SCNDRY;
-
-MTBF_2 : if C_MTBF_STAGES = 2 generate
-begin
- s_out_re <= s_out_d2 xor s_out_d3;
-
-end generate MTBF_2;
-
-MTBF_3 : if C_MTBF_STAGES = 3 generate
-begin
- s_out_re <= s_out_d3 xor s_out_d4;
-
-end generate MTBF_3;
-
-MTBF_4 : if C_MTBF_STAGES = 4 generate
-begin
- s_out_re <= s_out_d4 xor s_out_d5;
-
-end generate MTBF_4;
-
-MTBF_5 : if C_MTBF_STAGES = 5 generate
-begin
- s_out_re <= s_out_d5 xor s_out_d6;
-
-end generate MTBF_5;
-
-MTBF_6 : if C_MTBF_STAGES = 6 generate
-begin
- s_out_re <= s_out_d6 xor s_out_d7;
-
-end generate MTBF_6;
-
- -- Feed secondary pulse out
-
-end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-
-
--- Generate LEVEL clock domain crossing with reset state = 0
-GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
-begin
--- Primary to Secondary
-
-SINGLE_BIT : if C_SINGLE_BIT = 1 generate
-
-signal p_level_in_d1_cdc_from : std_logic := '0';
-signal p_level_in_int : std_logic := '0';
-signal s_level_out_d1_north_channel_cdc_to : std_logic := '0';
-signal s_level_out_d2 : std_logic := '0';
-signal s_level_out_d3 : std_logic := '0';
-signal s_level_out_d4 : std_logic := '0';
-signal s_level_out_d5 : std_logic := '0';
-signal s_level_out_d6 : std_logic := '0';
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_level_out_d1_north_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
-
- ATTRIBUTE shift_extract : STRING;
- ATTRIBUTE shift_extract OF s_level_out_d1_north_channel_cdc_to : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d2 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d3 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d4 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d5 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_d6 : SIGNAL IS "no";
-
- ATTRIBUTE keep : STRING;
- ATTRIBUTE keep OF p_level_in_d1_cdc_from : SIGNAL IS "true";
-begin
-
- --*****************************************************************************
- --** Asynchronous Level Clock Crossing **
- --** PRIMARY TO SECONDARY **
- --*****************************************************************************
- -- register is scndry to provide clean ff output to clock crossing logic
-
-INPUT_FLOP : if C_FLOP_INPUT = 1 generate
-begin
-
- REG_PLEVEL_IN : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_level_in_d1_cdc_from <= '0';
- else
- p_level_in_d1_cdc_from <= prmry_in;
- end if;
- end if;
- end process REG_PLEVEL_IN;
-
- p_level_in_int <= p_level_in_d1_cdc_from;
-
-end generate INPUT_FLOP;
-
-
-NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
-begin
-
- p_level_in_int <= prmry_in;
-
-end generate NO_INPUT_FLOP;
-
- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_level_out_d1_north_channel_cdc_to <= '0';
- s_level_out_d2 <= '0';
- s_level_out_d3 <= '0';
- s_level_out_d4 <= '0';
- s_level_out_d5 <= '0';
- s_level_out_d6 <= '0';
- else
- s_level_out_d1_north_channel_cdc_to <= p_level_in_int;
- s_level_out_d2 <= s_level_out_d1_north_channel_cdc_to;
- s_level_out_d3 <= s_level_out_d2;
- s_level_out_d4 <= s_level_out_d3;
- s_level_out_d5 <= s_level_out_d4;
- s_level_out_d6 <= s_level_out_d5;
- end if;
- end if;
- end process CROSS_PLEVEL_IN2SCNDRY;
-
-
-
-
-MTBF_L1 : if C_MTBF_STAGES = 1 generate
-begin
- scndry_out <= s_level_out_d1_north_channel_cdc_to;
-
-
-end generate MTBF_L1;
-
-MTBF_L2 : if C_MTBF_STAGES = 2 generate
-begin
-
- scndry_out <= s_level_out_d2;
-
-
-end generate MTBF_L2;
-
-MTBF_L3 : if C_MTBF_STAGES = 3 generate
-begin
-
- scndry_out <= s_level_out_d3;
-
-
-
-end generate MTBF_L3;
-
-MTBF_L4 : if C_MTBF_STAGES = 4 generate
-begin
- scndry_out <= s_level_out_d4;
-
-
-
-end generate MTBF_L4;
-
-MTBF_L5 : if C_MTBF_STAGES = 5 generate
-begin
-
- scndry_out <= s_level_out_d5;
-
-
-end generate MTBF_L5;
-
-MTBF_L6 : if C_MTBF_STAGES = 6 generate
-begin
-
- scndry_out <= s_level_out_d6;
-
-
-end generate MTBF_L6;
-
-end generate SINGLE_BIT;
-
-
-
-MULTI_BIT : if C_SINGLE_BIT = 0 generate
-
-signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d1_north_channel_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_level_out_bus_d1_north_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
-
- ATTRIBUTE shift_extract : STRING;
- ATTRIBUTE shift_extract OF s_level_out_bus_d1_north_channel_cdc_to : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d2 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d3 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d4 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d5 : SIGNAL IS "no";
- ATTRIBUTE shift_extract OF s_level_out_bus_d6 : SIGNAL IS "no";
-
-begin
-
- --*****************************************************************************
- --** Asynchronous Level Clock Crossing **
- --** PRIMARY TO SECONDARY **
- --*****************************************************************************
- -- register is scndry to provide clean ff output to clock crossing logic
--- REG_PLEVEL_IN : process(prmry_aclk)
--- begin
--- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
--- p_level_in_bus_d1_cdc_from <= (others => '0');
--- else
--- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
--- end if;
--- end if;
--- end process REG_PLEVEL_IN;
-
- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_level_out_bus_d1_north_channel_cdc_to <= (others => '0');
- s_level_out_bus_d2 <= (others => '0');
- s_level_out_bus_d3 <= (others => '0');
- s_level_out_bus_d4 <= (others => '0');
- s_level_out_bus_d5 <= (others => '0');
- s_level_out_bus_d6 <= (others => '0');
- else
- s_level_out_bus_d1_north_channel_cdc_to <= prmry_vect_in;
- s_level_out_bus_d2 <= s_level_out_bus_d1_north_channel_cdc_to;
- s_level_out_bus_d3 <= s_level_out_bus_d2;
- s_level_out_bus_d4 <= s_level_out_bus_d3;
- s_level_out_bus_d5 <= s_level_out_bus_d4;
- s_level_out_bus_d6 <= s_level_out_bus_d5;
- end if;
- end if;
- end process CROSS_PLEVEL_IN2SCNDRY;
-
-
-
-MTBF_L1 : if C_MTBF_STAGES = 1 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d1_north_channel_cdc_to;
-
-
-end generate MTBF_L1;
-
-MTBF_L2 : if C_MTBF_STAGES = 2 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d2;
-
-
-end generate MTBF_L2;
-
-MTBF_L3 : if C_MTBF_STAGES = 3 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d3;
-
-
-
-end generate MTBF_L3;
-
-MTBF_L4 : if C_MTBF_STAGES = 4 generate
-begin
- scndry_vect_out <= s_level_out_bus_d4;
-
-
-
-end generate MTBF_L4;
-
-MTBF_L5 : if C_MTBF_STAGES = 5 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d5;
-
-
-end generate MTBF_L5;
-
-MTBF_L6 : if C_MTBF_STAGES = 6 generate
-begin
-
- scndry_vect_out <= s_level_out_bus_d6;
-
-
-end generate MTBF_L6;
-
-end generate MULTI_BIT;
-
-
-end generate GENERATE_LEVEL_P_S_CDC;
-
-
-GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
--- Primary to Secondary
-
-
-signal p_level_in_d1_cdc_from : std_logic := '0';
-signal p_level_in_int : std_logic := '0';
-signal s_level_out_d1_north_channel_cdc_to : std_logic := '0';
-signal s_level_out_d2 : std_logic := '0';
-signal s_level_out_d3 : std_logic := '0';
-signal s_level_out_d4 : std_logic := '0';
-signal s_level_out_d5 : std_logic := '0';
-signal s_level_out_d6 : std_logic := '0';
-signal p_level_out_d1_north_channel_cdc_to : std_logic := '0';
-signal p_level_out_d2 : std_logic := '0';
-signal p_level_out_d3 : std_logic := '0';
-signal p_level_out_d4 : std_logic := '0';
-signal p_level_out_d5 : std_logic := '0';
-signal p_level_out_d6 : std_logic := '0';
-signal p_level_out_d7 : std_logic := '0';
-signal scndry_out_int : std_logic := '0';
-signal prmry_pulse_ack : std_logic := '0';
- -----------------------------------------------------------------------------
- -- ATTRIBUTE Declarations
- -----------------------------------------------------------------------------
- -- Prevent x-propagation on clock-domain crossing register
- ATTRIBUTE async_reg : STRING;
- ATTRIBUTE async_reg OF s_level_out_d1_north_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
-
- ATTRIBUTE async_reg OF p_level_out_d1_north_channel_cdc_to : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d3 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d4 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d5 : SIGNAL IS "true";
- ATTRIBUTE async_reg OF p_level_out_d6 : SIGNAL IS "true";
-
-begin
-
- --*****************************************************************************
- --** Asynchronous Level Clock Crossing **
- --** PRIMARY TO SECONDARY **
- --*****************************************************************************
- -- register is scndry to provide clean ff output to clock crossing logic
-INPUT_FLOP : if C_FLOP_INPUT = 1 generate
-begin
-
- REG_PLEVEL_IN : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_level_in_d1_cdc_from <= '0';
- else
- p_level_in_d1_cdc_from <= prmry_in;
- end if;
- end if;
- end process REG_PLEVEL_IN;
-
- p_level_in_int <= p_level_in_d1_cdc_from;
-
-end generate INPUT_FLOP;
-
-
-NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
-begin
-
- p_level_in_int <= prmry_in;
-
-end generate NO_INPUT_FLOP;
-
- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
- begin
- if(scndry_aclk'EVENT and scndry_aclk ='1')then
- if(scndry_resetn = '0' and C_RESET_STATE = 1)then
- s_level_out_d1_north_channel_cdc_to <= '0';
- s_level_out_d2 <= '0';
- s_level_out_d3 <= '0';
- s_level_out_d4 <= '0';
- s_level_out_d5 <= '0';
- s_level_out_d6 <= '0';
- else
- s_level_out_d1_north_channel_cdc_to <= p_level_in_int;
- s_level_out_d2 <= s_level_out_d1_north_channel_cdc_to;
- s_level_out_d3 <= s_level_out_d2;
- s_level_out_d4 <= s_level_out_d3;
- s_level_out_d5 <= s_level_out_d4;
- s_level_out_d6 <= s_level_out_d5;
- end if;
- end if;
- end process CROSS_PLEVEL_IN2SCNDRY;
-
-
- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
- begin
- if(prmry_aclk'EVENT and prmry_aclk ='1')then
- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
- p_level_out_d1_north_channel_cdc_to <= '0';
- p_level_out_d2 <= '0';
- p_level_out_d3 <= '0';
- p_level_out_d4 <= '0';
- p_level_out_d5 <= '0';
- p_level_out_d6 <= '0';
- p_level_out_d7 <= '0';
- prmry_ack <= '0';
- else
- p_level_out_d1_north_channel_cdc_to <= scndry_out_int;
- p_level_out_d2 <= p_level_out_d1_north_channel_cdc_to;
- p_level_out_d3 <= p_level_out_d2;
- p_level_out_d4 <= p_level_out_d3;
- p_level_out_d5 <= p_level_out_d4;
- p_level_out_d6 <= p_level_out_d5;
- p_level_out_d7 <= p_level_out_d6;
- prmry_ack <= prmry_pulse_ack;
- end if;
- end if;
- end process CROSS_PLEVEL_SCNDRY2PRMRY;
-
-
-
-
-MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
-begin
-
- scndry_out_int <= s_level_out_d2;
- prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
-
-
-end generate MTBF_L2;
-
-MTBF_L3 : if C_MTBF_STAGES = 3 generate
-begin
-
- scndry_out_int <= s_level_out_d3;
- prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
-
-
-
-end generate MTBF_L3;
-
-MTBF_L4 : if C_MTBF_STAGES = 4 generate
-begin
- scndry_out_int <= s_level_out_d4;
- prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
-
-
-
-end generate MTBF_L4;
-
-MTBF_L5 : if C_MTBF_STAGES = 5 generate
-begin
-
- scndry_out_int <= s_level_out_d5;
- prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
-
-
-end generate MTBF_L5;
-
-MTBF_L6 : if C_MTBF_STAGES = 6 generate
-begin
-
- scndry_out_int <= s_level_out_d6;
- prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
-
-
-end generate MTBF_L6;
-
- scndry_out <= scndry_out_int;
-
-
-end generate GENERATE_LEVEL_ACK_P_S_CDC;
-
-
-end implementation;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_channel_err_detect.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_channel_err_detect.vhd
deleted file mode 100644
index 4156a0dbe00da415738b8887b72575cf01c953f1..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_channel_err_detect.vhd
+++ /dev/null
@@ -1,202 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- CHANNEL_ERR_DETECT
---
---
--- Description: the CHANNEL_ERR_DETECT module monitors the error signals
--- from the Aurora Lanes in the channel. If one or more errors
--- are detected, the error is reported as a channel error. If
--- a hard error is detected, it sends a message to the channel
--- initialization state machine to reset the channel.
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity north_channel_CHANNEL_ERR_DETECT is
-
- port (
-
- -- Aurora Lane Interface
-
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-LANE_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- POWER_DOWN : in std_logic;
-
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic;
-
- -- Channel Init SM Interface
-
- RESET_CHANNEL : out std_logic
-
- );
-
-end north_channel_CHANNEL_ERR_DETECT;
-
-architecture RTL of north_channel_CHANNEL_ERR_DETECT is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal CHANNEL_SOFT_ERR_Buffer : std_logic := '1';
- signal CHANNEL_HARD_ERR_Buffer : std_logic := '1';
- signal RESET_CHANNEL_Buffer : std_logic := '1';
-
--- Internal Register Declarations --
-
-signal soft_err_r : std_logic_vector(0 to 1);
-signal hard_err_r : std_logic;
-signal lane_up_r : std_logic;
-
--- Wire Declarations --
-
- signal channel_soft_err_c : std_logic;
- signal channel_hard_err_c : std_logic;
- signal reset_channel_c : std_logic;
-
-begin
-
- CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer;
- CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;
- RESET_CHANNEL <= RESET_CHANNEL_Buffer;
-
--- Main Body of Code --
-
- -- Register all of the incoming error signals. This is neccessary for timing.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- soft_err_r <= SOFT_ERR after DLY;
- hard_err_r <= HARD_ERR after DLY;
-
- end if;
-
- end process;
-
-
- -- Assert Channel soft error if any of the soft error signals are asserted.
-
- channel_soft_err_c <= soft_err_r(0) or
- soft_err_r(1);
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- CHANNEL_SOFT_ERR_Buffer <= channel_soft_err_c after DLY;
-
- end if;
-
- end process;
-
-
- -- Assert Channel hard error if any of the hard error signals are asserted.
-
- channel_hard_err_c <= hard_err_r;
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- CHANNEL_HARD_ERR_Buffer <= channel_hard_err_c after DLY;
-
- end if;
-
- end process;
-
- -- FF stage added for timing closure
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- lane_up_r <= LANE_UP after DLY;
-
- end if;
-
- end process;
-
- -- "reset_channel_c" is asserted when any of the LANE_UP signals are low.
-
- reset_channel_c <= not lane_up_r;
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RESET_CHANNEL_Buffer <= reset_channel_c or POWER_DOWN after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_channel_init_sm.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_channel_init_sm.vhd
deleted file mode 100644
index c4b75a50fc6b878087076c10232800256adf518d..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_channel_init_sm.vhd
+++ /dev/null
@@ -1,557 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- CHANNEL_INIT_SM
---
---
---
--- Description: the CHANNEL_INIT_SM module is a state machine for managing channel
--- bonding and verification.
---
--- The channel init state machine is reset until the lane up signals
--- of all the lanes that constitute the channel are asserted. It then
--- requests channel bonding until the lanes have been bonded and
--- checks to make sure the bonding was successful. Channel bonding is
--- skipped if there is only one lane in the channel. If bonding is
--- unsuccessful, the lanes are reset.
---
--- After the bonding phase is complete, the state machine sends
--- verification sequences through the channel until it is clear that
--- the channel is ready to be used. If verification is successful,
--- the CHANNEL_UP signal is asserted. If it is unsuccessful, the
--- lanes are reset.
---
--- After CHANNEL_UP goes high, the state machine is quiescent, and will
--- reset only if one of the lanes goes down, a hard error is detected, or
--- a general reset is requested.
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.NUMERIC_STD.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-
-library UNISIM;
-use UNISIM.all;
-
--- synthesis translate_on
-
-entity north_channel_CHANNEL_INIT_SM is
-
- generic (
- WATCHDOG_TIMEOUT : integer := 14
- );
- port (
-
- -- GTP Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-RESET_LANES : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
-
- -- Idle and Verification Sequence Generator Interface
-
- DID_VER : in std_logic;
- GEN_VER : out std_logic;
-
- -- Channel Init State Machine Interface
-
- GTRXRESET_OUT : out std_logic;
- RESET_CHANNEL : in std_logic
-
- );
-
-end north_channel_CHANNEL_INIT_SM;
-
-architecture RTL of north_channel_CHANNEL_INIT_SM is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal EN_CHAN_SYNC_Buffer : std_logic;
-signal RESET_LANES_Buffer : std_logic;
- signal CHANNEL_UP_Buffer : std_logic;
- signal START_RX_Buffer : std_logic;
- signal GEN_VER_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal free_count_done_w : std_logic;
- signal verify_watchdog_r : std_logic_vector(0 to 15);
- signal all_lanes_v_r : std_logic;
- signal got_first_v_r : std_logic;
- signal v_count_r : std_logic_vector(0 to 15);
- signal bad_v_r : std_logic;
- signal rxver_count_r : std_logic_vector(0 to 2);
- signal txver_count_r : std_logic_vector(0 to 7);
- signal free_count_r : std_logic_vector(0 to WATCHDOG_TIMEOUT-1);
-
- -- State registers
-
- signal wait_for_lane_up_r : std_logic;
- signal verify_r : std_logic;
- signal ready_r : std_logic;
-
- -- FF for timing closure
- signal ready_r2 : std_logic;
-
-
- signal gtreset_c : std_logic;
- signal gtrxreset_nxt : std_logic;
- signal gtrxreset_extend_r : std_logic_vector(7 downto 0) := "00000000";
-
-
--- Wire Declarations --
-
- signal insert_ver_c : std_logic;
- signal verify_watchdog_done_r : std_logic;
- signal rxver_3d_done_r : std_logic;
- signal txver_8d_done_r : std_logic;
- signal reset_lanes_c : std_logic;
-
- -- Next state signals
-
- signal next_verify_c : std_logic;
- signal next_ready_c : std_logic;
-
- -- VHDL utility signals
-
- signal tied_to_vcc : std_logic;
- signal tied_to_gnd : std_logic;
-
--- Component Declarations
-
- component FD
-
- -- synthesis translate_off
-
- generic (INIT : bit := '0');
-
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic
-
- );
-
- end component;
-
-begin
-
- EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
- RESET_LANES <= RESET_LANES_Buffer;
- CHANNEL_UP <= CHANNEL_UP_Buffer;
- START_RX <= START_RX_Buffer;
- GEN_VER <= GEN_VER_Buffer;
-
- tied_to_vcc <= '1';
- tied_to_gnd <= '0';
-
--- Main Body of Code --
-
- -- Main state machine for bonding and verification --
-
- -- State registers
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or RESET_CHANNEL) = '1') then
-
- wait_for_lane_up_r <= '1' after DLY;
- verify_r <= '0' after DLY;
- ready_r <= '0' after DLY;
-
- else
-
- wait_for_lane_up_r <= '0' after DLY;
- verify_r <= next_verify_c after DLY;
- ready_r <= next_ready_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Next state logic
-
- next_verify_c <= wait_for_lane_up_r or
- (verify_r and (not rxver_3d_done_r or not txver_8d_done_r));
-
- next_ready_c <= ((verify_r and txver_8d_done_r) and rxver_3d_done_r) or
- ready_r;
-
-
- -- Output Logic
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- ready_r2 <= ready_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Channel up is high as long as the Global Logic is in the ready state.
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- CHANNEL_UP_Buffer <= ready_r2 after DLY;
-
- end if;
-
- end process;
-
-
- -- Turn the receive engine on as soon as all the lanes are up.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- START_RX_Buffer <= '0' after DLY;
-
- else
-
- START_RX_Buffer <= not wait_for_lane_up_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate the Verification sequence when in the verify state.
-
- GEN_VER_Buffer <= verify_r;
-
-
- -- Channel Reset --
-
- -- Some problems during channel bonding and verification require the lanes to
- -- be reset. When this happens, we assert the Reset Lanes signal, which gets
- -- sent to all Aurora Lanes. When the Aurora Lanes reset, their LANE_UP signals
- -- go down. This causes the Channel Error Detector to assert the Reset Channel
- -- signal.
-
- reset_lanes_c <= (verify_r and verify_watchdog_done_r) or
- (verify_r and bad_v_r and not rxver_3d_done_r) or
- (RESET_CHANNEL and not wait_for_lane_up_r) or
- RESET;
-
- reset_lanes_flop_i : FD
-
- -- synthesis translate_off
-
- generic map (INIT => '1')
-
- -- synthesis translate_on
-
- port map (
-
- D => reset_lanes_c,
- C => USER_CLK,
- Q => RESET_LANES_Buffer
-
- );
-
-
-
- gtreset_c <= (verify_r and verify_watchdog_done_r) or
- ((verify_r and bad_v_r) and not rxver_3d_done_r);
-
-
- gtreset_flop_0_i : FD
-
- -- synthesis translate_off
-
- generic map (INIT => '1')
-
- -- synthesis translate_on
-
- port map (
-
- D => gtreset_c,
- C => USER_CLK,
- Q => gtrxreset_nxt
-
- );
-
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- if (RESET = '1') then
- gtrxreset_extend_r <= (others => '0') after DLY;
- else
- gtrxreset_extend_r <= (gtrxreset_nxt & gtrxreset_extend_r(7 downto 1)) after DLY;
- end if;
- end if;
- end process;
-
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- GTRXRESET_OUT <= OR_REDUCE(gtrxreset_extend_r) after DLY;
- end if;
- end process;
-
-
- -- Watchdog timers --
-
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- if ((RESET or RESET_CHANNEL) = '1') then
- free_count_r <= (others => '1') after DLY;
- else
- free_count_r <= free_count_r - '1' after DLY;
- end if;
- end if;
- end process;
-
-
- free_count_done_w <= (std_bool(free_count_r = 0));
-
- -- We use the free running count as a CE for the verify watchdog. The
- -- count runs continuously so the watchdog will vary between a count of 4096
- -- and 3840 cycles - acceptable for this application.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((free_count_done_w or not verify_r) = '1') then
-
- verify_watchdog_r <= verify_r & verify_watchdog_r(0 to 14) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- verify_watchdog_done_r <= verify_watchdog_r(15);
-
-
- -- Channel Bonding --
-
- -- We don't use channel bonding for the single lane case, so we tie the
- -- EN_CHAN_SYNC signal low.
-
- EN_CHAN_SYNC_Buffer <= '0';
-
-
- -- Verification --
-
- -- Vs need to appear on all lanes simultaneously.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- all_lanes_v_r <= GOT_V after DLY;
-
- end if;
-
- end process;
-
-
- -- Vs need to be decoded by the aurora lane and then checked by the
- -- Global logic. They must appear periodically.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (verify_r = '0') then
-
- got_first_v_r <= '0' after DLY;
-
- else
-
- if (all_lanes_v_r = '1') then
-
- got_first_v_r <= '1' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- insert_ver_c <= (all_lanes_v_r and not got_first_v_r) or (v_count_r(15) and verify_r);
-
-
- -- Shift register for measuring the time between V counts.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- v_count_r <= insert_ver_c & v_count_r(0 to 14) after DLY;
-
- end if;
-
- end process;
-
-
- -- Assert bad_v_r if a V does not arrive when expected.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- bad_v_r <= (v_count_r(15) xor all_lanes_v_r) and got_first_v_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Count the number of Ver sequences received. You're done after you receive four.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (((v_count_r(15) and all_lanes_v_r) or not verify_r) = '1') then
-
- rxver_count_r <= verify_r & rxver_count_r(0 to 1) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- rxver_3d_done_r <= rxver_count_r(2);
-
-
- -- Count the number of Ver sequences transmitted. You're done after you send eight.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((DID_VER or not verify_r) = '1') then
-
- txver_count_r <= verify_r & txver_count_r(0 to 6) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- txver_8d_done_r <= txver_count_r(7);
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_chbond_count_dec_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_chbond_count_dec_4byte.vhd
deleted file mode 100644
index cd542eecd0f18280c5b58627b72020e0b60ff42e..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_chbond_count_dec_4byte.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- CHBOND_COUNT_DEC_4BYTE
---
---
---
--- Description: This module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
--- that Channel Bonding is complete
---
--- * Supports Virtex-5
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_CHBOND_COUNT_DEC_4BYTE is
-
- port (
-
- RX_STATUS : in std_logic_vector(5 downto 0);
- CHANNEL_BOND_LOAD : out std_logic;
- USER_CLK : in std_logic
-
- );
-
-end north_channel_CHBOND_COUNT_DEC_4BYTE;
-
-architecture RTL of north_channel_CHBOND_COUNT_DEC_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
- constant CHANNEL_BOND_LOAD_CODE : std_logic_vector(5 downto 0) := "100111"; -- Status bus code: Channel Bond load complete
-
--- External Register Declarations
-
- signal CHANNEL_BOND_LOAD_Buffer : std_logic;
-
-begin
-
- CHANNEL_BOND_LOAD <= CHANNEL_BOND_LOAD_Buffer;
-
--- Main Body of Code --
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK'event and USER_CLK = '1') then
-
- CHANNEL_BOND_LOAD_Buffer <= std_bool(RX_STATUS = CHANNEL_BOND_LOAD_CODE) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_descrambler_top.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_descrambler_top.vhd
deleted file mode 100644
index bfcbf25490ac33258f10c92ba19cee49c032d0af..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_descrambler_top.vhd
+++ /dev/null
@@ -1,246 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
-
---***************************** Module Declaration ****************************
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_DESCRAMBLER_TOP is
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- RX_PAD_IN : in std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA_IN : in std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V_IN : in std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP_IN : in std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP_IN : in std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF_IN : in std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB_IN : in std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- RX_SP_IN : in std_logic; -- SP sequence received with positive or negative data.
- RX_SPA_IN : in std_logic; -- SPA sequence received.
- RX_NEG_IN : in std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- RX_CC : out std_logic; -- CC sequence received.
-
- GOT_A_IN : in std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V_IN : in std_logic; -- V sequence received.
-
- RX_CC_IN : in std_logic; -- CC sequence received.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- CLEAR : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_DESCRAMBLER_TOP;
-
-architecture BEHAVIORAL of north_channel_DESCRAMBLER_TOP is
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
---**************************************Signal Declarations***************************
-
- signal en_scrambler : std_logic_vector(1 downto 0);
- signal bypass_w : std_logic_vector(1 downto 0);
- signal bypass_r : std_logic_vector(1 downto 0);
- signal user_data : std_logic_vector(31 downto 0);
- signal scrambled_data : std_logic_vector(31 downto 0);
- signal data_nxt2 : std_logic_vector(0 to 31);
- signal RX_PE_DATA_Buffer : std_logic_vector(0 to 31);
- signal RX_SUF_Buffer : std_logic_vector(0 to 1);
-
- component north_channel_SCRAMBLER is
-
- generic
- (
- C_SEED : std_logic_vector := X"FFFF"
- );
-
- port
- (
- DOUT : out std_logic_vector(15 downto 0);
-
- DIN : in std_logic_vector(15 downto 0);
- BYPASS : in std_logic;
- EN : in std_logic;
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- CLK : in std_logic
- );
-
- end component;
-
-
-begin
-
---*********************************Main Body of Code**********************************
-
- -- pipeline all SYM DEC inputs
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- RX_PAD <= RX_PAD_IN after DLY;
- data_nxt2 <= RX_PE_DATA_IN after DLY;
- RX_PE_DATA_V <= RX_PE_DATA_V_IN after DLY;
- RX_SCP <= RX_SCP_IN after DLY;
- RX_ECP <= RX_ECP_IN after DLY;
- RX_SUF_Buffer <= RX_SUF_IN after DLY;
- RX_FC_NB <= RX_FC_NB_IN after DLY;
- RX_SP <= RX_SP_IN after DLY;
- RX_SPA <= RX_SPA_IN after DLY;
- RX_NEG <= RX_NEG_IN after DLY;
- GOT_A <= GOT_A_IN after DLY;
- GOT_V <= GOT_V_IN after DLY;
- RX_CC <= RX_CC_IN after DLY;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- bypass_r <= bypass_w;
- end if;
- end process;
-
- bypass_w(0) <= '1' when ((NOT RX_PE_DATA_V_IN(0) or RX_PAD_IN(0) or GOT_V_IN or RESET) = '1') else
- '0';
-
- bypass_w(1) <= '1' when ((NOT RX_PE_DATA_V_IN(1) or RX_PAD_IN(1) or GOT_V_IN or RESET) = '1') else
- '0';
-
- user_data(15 downto 0) <= X"0000" when (bypass_w(0) = '1') else
- RX_PE_DATA_IN(0 to 15);
-
- user_data(31 downto 16) <= X"0000" when (bypass_w(1) = '1') else
- RX_PE_DATA_IN(16 to 31);
-
- en_scrambler(0) <= NOT bypass_w(0);
-
- en_scrambler(1) <= NOT bypass_w(1);
-
- north_channel_descrambler0_i : north_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(15 downto 0),
- DIN => user_data(15 downto 0),
- EN => en_scrambler(0),
- BYPASS => bypass_w(0),
- CLEAR => RX_CC_IN,
- RESET => RESET,
- CLK => USER_CLK
- );
-
- north_channel_descrambler1_i : north_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(31 downto 16),
- DIN => user_data(31 downto 16),
- EN => en_scrambler(1),
- BYPASS => bypass_w(1),
- CLEAR => RX_CC_IN,
- RESET => RESET,
- CLK => USER_CLK
- );
-
-
- -- Outputs
-
- RX_PE_DATA_Buffer(0 to 15) <= data_nxt2(0 to 15) when (bypass_r(0) = '1') else
- scrambled_data(15 downto 0);
-
- RX_PE_DATA_buffer(16 to 31) <= data_nxt2(16 to 31) when (bypass_r(1) = '1') else
- scrambled_data(31 downto 16);
-
- RX_PE_DATA(0 to 15) <= RX_PE_DATA_Buffer(0 to 15);
-
- RX_PE_DATA(16 to 31) <= RX_PE_DATA_Buffer(16 to 31);
-
- RX_SUF <= RX_SUF_Buffer;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_err_detect_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_err_detect_4byte.vhd
deleted file mode 100644
index 30091c94c9d1034ee59395a4169228f7509042e5..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_err_detect_4byte.vhd
+++ /dev/null
@@ -1,295 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
---
--- ERR_DETECT_4BYTE
---
---
--- Description : The ERR_DETECT module monitors the GTX to detect hard errors.
--- It accumulates the Soft errors according to the leaky bucket
--- algorithm described in the Aurora Specification to detect Hard
--- errors. All errors are reported to the Global Logic Interface.
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use IEEE.STD_LOGIC_MISC.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_ERR_DETECT_4BYTE is
-generic
-(
- ENABLE_SOFT_ERR_MONITOR : integer := 1
-);
-port (
- -- Lane Init SM Interface
-
- ENABLE_ERR_DETECT : in std_logic;
- HARD_ERR_RESET : out std_logic;
-
- -- Global Logic Interface
-
- SOFT_ERR : out std_logic_vector(0 to 1);
- HARD_ERR : out std_logic;
-
- -- GTX Interface
-
- RX_BUF_ERR : in std_logic;
- RX_DISP_ERR : in std_logic_vector(3 downto 0);
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0);
- TX_BUF_ERR : in std_logic;
- RX_REALIGN : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
- );
-
-end north_channel_ERR_DETECT_4BYTE;
-
-architecture RTL of north_channel_ERR_DETECT_4BYTE is
-
---Constant Declarations --
-
- constant DLY : time := 1 ns;
-
--- VHDL out buffer logic --
-
- signal SOFT_ERR_Buffer : std_logic_vector(0 to 1);
- signal HARD_ERR_Buffer : std_logic;
-
-
--- Internal Register Declarations --
-
- signal hard_err_gt : std_logic;
- signal hard_err_frm_soft_err : std_logic;
- signal err_cnt_r : std_logic_vector(2 downto 0);
- signal good_cnt_r : std_logic_vector(3 downto 0);
- signal soft_err_r : std_logic_vector(0 to 3);
-
- -- FSM registers
- signal start_r : std_logic;
- signal cnt_soft_err_r : std_logic;
- signal cnt_good_code_r : std_logic;
-
- signal next_start_c : std_logic;
- signal next_soft_err_c : std_logic;
- signal next_good_code_c : std_logic;
-
-begin
-
- -- VHDL Output Buffers --
-
- SOFT_ERR <= SOFT_ERR_Buffer;
- HARD_ERR <= HARD_ERR_Buffer;
-
--- Main Body of Code --
-
- -- Error Processing --
-
- -- Detect Soft Errors. The lane is divided into 2 2-byte sublanes for this purpose.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- -- Sublane 0
- soft_err_r(0) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(3) or RX_NOT_IN_TABLE(3)) after DLY;
- soft_err_r(1) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(2) or RX_NOT_IN_TABLE(2)) after DLY;
-
- -- Sublane 1
- soft_err_r(2) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(1) or RX_NOT_IN_TABLE(1)) after DLY;
- soft_err_r(3) <= ENABLE_ERR_DETECT and (RX_DISP_ERR(0) or RX_NOT_IN_TABLE(0)) after DLY;
-
- end if;
-
- end process;
-
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- -- Sublane 0
- SOFT_ERR_Buffer(0) <= soft_err_r(0) or soft_err_r(1) after DLY;
-
- -- Sublane 1
- SOFT_ERR_Buffer(1) <= soft_err_r(2) or soft_err_r(3) after DLY;
-
- end if;
-
- end process;
-
-
- -- Detect Hard Errors
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(ENABLE_ERR_DETECT = '1') then
-
- hard_err_gt <= (RX_BUF_ERR or TX_BUF_ERR or RX_REALIGN) after DLY;
-
- else
-
- hard_err_gt <= '0' after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(ENABLE_ERR_DETECT = '0') then
-
- hard_err_frm_soft_err <= '0' after DLY;
-
- else
-
- hard_err_frm_soft_err <= err_cnt_r(2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-soft_err_mon_enable : if ENABLE_SOFT_ERR_MONITOR = 1 generate
-
- HARD_ERR_Buffer <= hard_err_gt or (err_cnt_r(2) AND (NOT hard_err_frm_soft_err));
-
-end generate soft_err_mon_enable;
-
-
-soft_err_mon_disable : if ENABLE_SOFT_ERR_MONITOR = 0 generate
-
- HARD_ERR_Buffer <= hard_err_gt;
-
-end generate soft_err_mon_disable;
-
-
- -- Assert hard error reset when there is a hard error. This assignment
- -- just renames the two fanout branches of the hard error signal.
-
- HARD_ERR_RESET <= HARD_ERR_Buffer;
-
- --State registers for 1-hot state machine
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(ENABLE_ERR_DETECT = '0') then
- start_r <= '1' after DLY;
- cnt_soft_err_r <= '0' after DLY;
- cnt_good_code_r <= '0' after DLY;
- else
- start_r <= next_start_c after DLY;
- cnt_soft_err_r <= next_soft_err_c after DLY;
- cnt_good_code_r <= next_good_code_c after DLY;
- end if;
- end if;
- end process;
-
-
- next_start_c <= (start_r AND not(OR_REDUCE(soft_err_r))) OR
- (cnt_good_code_r AND not(OR_REDUCE(soft_err_r)) AND (AND_REDUCE(good_cnt_r)));
-
- next_soft_err_c <= (start_r AND (OR_REDUCE(soft_err_r))) OR
- (cnt_soft_err_r AND (OR_REDUCE(soft_err_r))) OR
- (cnt_good_code_r AND (OR_REDUCE(soft_err_r)));
-
- next_good_code_c <= (cnt_good_code_r AND NOT(OR_REDUCE(soft_err_r)) AND (NOT(AND_REDUCE(good_cnt_r)))) OR
- (cnt_soft_err_r AND NOT(OR_REDUCE(soft_err_r)));
-
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(ENABLE_ERR_DETECT = '0') then
- err_cnt_r <= (others => '0') after DLY;
- elsif((err_cnt_r(2) OR ((std_bool(good_cnt_r=X"4") OR std_bool(good_cnt_r=X"8") OR std_bool(good_cnt_r=X"C")) AND std_bool(cnt_soft_err_r='1'))) = '1') then
- err_cnt_r <= err_cnt_r after DLY;
- elsif(((OR_REDUCE(err_cnt_r)) AND (std_bool(good_cnt_r=X"4") OR std_bool(good_cnt_r=X"8") OR std_bool(good_cnt_r=X"C"))) = '1') then
- err_cnt_r <= err_cnt_r - 1 after DLY;
- elsif(cnt_soft_err_r = '1') then
- err_cnt_r <= err_cnt_r + 1 after DLY;
- end if;
- end if;
- end process;
-
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(((NOT ENABLE_ERR_DETECT) OR cnt_soft_err_r OR start_r) = '1') then
- good_cnt_r <= (others => '0') after DLY;
- elsif(cnt_good_code_r = '1') then
- good_cnt_r <= good_cnt_r + 1 after DLY;
- else
- good_cnt_r <= (others => '0') after DLY;
- end if;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_global_logic.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_global_logic.vhd
deleted file mode 100644
index 8927d2dc551bc3848e4b2379db3797f3cd731d57..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_global_logic.vhd
+++ /dev/null
@@ -1,318 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- GLOBAL_LOGIC
---
---
---
--- Description: The GLOBAL_LOGIC module handles channel bonding, channel
--- verification, channel error manangement and idle generation.
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity north_channel_GLOBAL_LOGIC is
-
- port (
-
- -- GTP Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-LANE_UP : in std_logic;
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-RESET_LANES : out std_logic;
-
- GTRXRESET_OUT : out std_logic;
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- POWER_DOWN : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic
-
- );
-
-end north_channel_GLOBAL_LOGIC;
-
-architecture MAPPED of north_channel_GLOBAL_LOGIC is
-
--- External Register Declarations --
-
- signal EN_CHAN_SYNC_Buffer : std_logic;
-signal GEN_A_Buffer : std_logic;
-signal GEN_K_Buffer : std_logic_vector(0 to 3);
-signal GEN_R_Buffer : std_logic_vector(0 to 3);
-signal GEN_V_Buffer : std_logic_vector(0 to 3);
-signal RESET_LANES_Buffer : std_logic;
- signal CHANNEL_UP_Buffer : std_logic;
- signal START_RX_Buffer : std_logic;
- signal CHANNEL_SOFT_ERR_Buffer : std_logic;
- signal CHANNEL_HARD_ERR_Buffer : std_logic;
-
--- Wire Declarations --
-
- signal gen_ver_i : std_logic;
- signal reset_channel_i : std_logic;
- signal did_ver_i : std_logic;
-
--- Component Declarations --
-
- component north_channel_CHANNEL_INIT_SM
-
- port (
-
- -- GTP Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-RESET_LANES : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
-
- -- Idle and Verification Sequence Generator Interface
-
- DID_VER : in std_logic;
- GEN_VER : out std_logic;
-
- -- Channel Init State Machine Interface
-
- GTRXRESET_OUT : out std_logic;
- RESET_CHANNEL : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_IDLE_AND_VER_GEN
-
- port (
-
- -- Channel Init SM Interface
-
- GEN_VER : in std_logic;
- DID_VER : out std_logic;
-
- -- Aurora Lane Interface
-
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-
- -- System Interface
-
- RESET : in std_logic;
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_CHANNEL_ERR_DETECT
-
- port (
-
- -- Aurora Lane Interface
-
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-LANE_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- POWER_DOWN : in std_logic;
-
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic;
-
- -- Channel Init SM Interface
-
- RESET_CHANNEL : out std_logic
-
- );
-
- end component;
-
-begin
-
- EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
- GEN_A <= GEN_A_Buffer;
- GEN_K <= GEN_K_Buffer;
- GEN_R <= GEN_R_Buffer;
- GEN_V <= GEN_V_Buffer;
- RESET_LANES <= RESET_LANES_Buffer;
- CHANNEL_UP <= CHANNEL_UP_Buffer;
- START_RX <= START_RX_Buffer;
- CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer;
- CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;
-
--- Main Body of Code --
-
- -- State Machine for channel bonding and verification.
-
- channel_init_sm_i : north_channel_CHANNEL_INIT_SM
-
- port map (
-
- -- GTP Interface
-
- CH_BOND_DONE => CH_BOND_DONE,
- EN_CHAN_SYNC => EN_CHAN_SYNC_Buffer,
-
- -- Aurora Lane Interface
-
- CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
- GOT_A => GOT_A,
- GOT_V => GOT_V,
- RESET_LANES => RESET_LANES_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => RESET,
- START_RX => START_RX_Buffer,
- CHANNEL_UP => CHANNEL_UP_Buffer,
-
- -- Idle and Verification Sequence Generator Interface
-
- DID_VER => did_ver_i,
- GEN_VER => gen_ver_i,
-
- -- Channel Error Management Module Interface
- GTRXRESET_OUT => GTRXRESET_OUT,
- RESET_CHANNEL => reset_channel_i
-
- );
-
-
- -- Idle and verification sequence generator module.
-
- idle_and_ver_gen_i : north_channel_IDLE_AND_VER_GEN
-
- port map (
-
- -- Channel Init SM Interface
-
- GEN_VER => gen_ver_i,
- DID_VER => did_ver_i,
-
- -- Aurora Lane Interface
-
- GEN_A => GEN_A_Buffer,
- GEN_K => GEN_K_Buffer,
- GEN_R => GEN_R_Buffer,
- GEN_V => GEN_V_Buffer,
-
- -- System Interface
-
- RESET => RESET,
- USER_CLK => USER_CLK
-
- );
-
-
-
- -- Channel Error Management module.
-
- channel_err_detect_i : north_channel_CHANNEL_ERR_DETECT
-
- port map (
-
- -- Aurora Lane Interface
-
- SOFT_ERR => SOFT_ERR,
- HARD_ERR => HARD_ERR,
- LANE_UP => LANE_UP,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- POWER_DOWN => POWER_DOWN,
- CHANNEL_SOFT_ERR => CHANNEL_SOFT_ERR_Buffer,
- CHANNEL_HARD_ERR => CHANNEL_HARD_ERR_Buffer,
-
- -- Channel Init State Machine Interface
-
- RESET_CHANNEL => reset_channel_i
-
- );
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_hotplug.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_hotplug.vhd
deleted file mode 100644
index 99a0028218aa10735c38ec3745f96c18ceeb1449..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_hotplug.vhd
+++ /dev/null
@@ -1,264 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
--- Hot-plug logic
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_HOTPLUG is
-generic
-(
- ENABLE_HOTPLUG : integer := 1;
- EXAMPLE_SIMULATION : integer := 0
-);
-port
-(
-
- ---------------------- Sym Dec Interface -------------------------------
- RX_CC : in std_logic;
- RX_SP : in std_logic;
- RX_SPA : in std_logic;
-
- ---------------------- GT Wrapper Interface ----------------------------
- LINK_RESET_OUT : out std_logic := '0';
- HPCNT_RESET : in std_logic;
-
- ---------------------- System Interface ----------------------------
- INIT_CLK : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
-
-);
-
-end north_channel_HOTPLUG;
-
-architecture BEHAVIORAL of north_channel_HOTPLUG is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of BEHAVIORAL : architecture is "yes";
- attribute core_generation_info : string;
-attribute core_generation_info of BEHAVIORAL : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- component north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
- signal link_reset_0 : std_logic;
- signal link_reset_r : std_logic;
- signal count_for_reset_r : std_logic_vector(21 downto 0) := "0000000000000000000000";
- signal rx_cc_extend_r : std_logic_vector(7 downto 0) := "00000000";
- signal rx_cc_extend_r2 : std_logic;
- signal cc_sync : std_logic;
-
-begin
-
---*********************************Main Body of Code**********************************
-
---Extend the RX_CC pulse for 8 clock cycles
---This RX_CC extension is required when INIT_CLK is slower than USER_CLK
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- rx_cc_extend_r <= (others => '0') after DLY;
- else
- rx_cc_extend_r <= RX_CC & rx_cc_extend_r(7 downto 1) after DLY;
- end if;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- rx_cc_extend_r2 <= OR_REDUCE(rx_cc_extend_r) after DLY;
- end if;
- end process;
-
- -- Clock domain crossing from USER_CLK to INIT_CLK
- rx_cc_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => USER_CLK ,
- prmry_resetn => '1' ,
- prmry_in => rx_cc_extend_r2 ,
- prmry_vect_in => "00" ,
- scndry_aclk => INIT_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => cc_sync ,
- scndry_vect_out => open
- );
-
- -- Incoming control characters are decoded to detmine CC reception
- -- Reset the link if CC is not detected for longer time
- -- Wait for sufficient time to allow the link recovery and CC consumption
- -- link_reset_0 is used to reset the GT & Aurora core
-
- -- RX_CC is used as the reset for the count_for_reset_r
-hotplug_count_synth : if EXAMPLE_SIMULATION = 0 generate
- process(INIT_CLK,HPCNT_RESET)
- begin
- if(HPCNT_RESET = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- elsif(INIT_CLK'event and INIT_CLK = '1') then
- if(cc_sync = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- else
- count_for_reset_r <= count_for_reset_r + 1 after DLY;
- end if;
- end if;
- end process;
-end generate hotplug_count_synth;
-
-hotplug_count_sim : if EXAMPLE_SIMULATION = 1 generate
-process(INIT_CLK,HPCNT_RESET)
-begin
- if(HPCNT_RESET = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- elsif(INIT_CLK'event and INIT_CLK = '1') then
- if(cc_sync = '1') then
- count_for_reset_r <= (others => '0') after DLY;
- else
- if (count_for_reset_r = X"FFFFF") then
- count_for_reset_r <= (others => '0') after DLY;
- else
- count_for_reset_r <= count_for_reset_r + 1 after DLY;
- end if;
- end if;
- end if;
-end process;
-end generate hotplug_count_sim;
-
-link_reset_synth : if EXAMPLE_SIMULATION = 0 generate
- link_reset_0 <= '1' when ((count_for_reset_r > X"3FFFEB") AND (count_for_reset_r < X"3FFFFF")) else
- '0'; -- 4194283 to 4194303
-end generate link_reset_synth;
-
-link_reset_sim : if EXAMPLE_SIMULATION = 1 generate
- -- Wait for sufficient time : 2^20 = 1048576 for simulation
- link_reset_0 <= '1' when ((count_for_reset_r > X"FF447") AND (count_for_reset_r < X"FFFFA")) else
- '0'; -- 1045575 to 1048570
-end generate link_reset_sim;
-
- process(INIT_CLK)
- begin
- if(INIT_CLK'event and INIT_CLK = '1') then
- link_reset_r <= link_reset_0 after DLY;
- end if;
- end process;
-
-hotplug_enable : if ENABLE_HOTPLUG = 1 generate
-
- process(INIT_CLK)
- begin
- if(INIT_CLK'event and INIT_CLK = '1') then
- LINK_RESET_OUT <= link_reset_r after DLY;
- end if;
- end process;
-
-end generate hotplug_enable;
-
-
-hotplug_disable : if ENABLE_HOTPLUG = 0 generate
-
- LINK_RESET_OUT <= '0';
-
-end generate hotplug_disable;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_idle_and_ver_gen.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_idle_and_ver_gen.vhd
deleted file mode 100644
index ce97d6ed459c0a151c9ca22b4c96a5ff54ceb5c2..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_idle_and_ver_gen.vhd
+++ /dev/null
@@ -1,599 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- IDLE_AND_VER_GEN
---
---
--- Description: the IDLE_AND_VER_GEN module generates idle sequences and
--- verification sequences for the Aurora channel. The idle sequences
--- are constantly generated by a pseudorandom generator and a counter
--- to make the sequence Aurora compliant. If the gen_ver signal is high,
--- verification symbols are added to the mix at appropriate intervals
---
--- This module supports 1 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-
-entity north_channel_IDLE_AND_VER_GEN is
-
- port (
-
- -- Channel Init SM Interface
-
- GEN_VER : in std_logic;
- DID_VER : out std_logic;
-
- -- Aurora Lane Interface
-
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-
- -- System Interface
-
- RESET : in std_logic;
- USER_CLK : in std_logic
-
- );
-
-end north_channel_IDLE_AND_VER_GEN;
-
-architecture RTL of north_channel_IDLE_AND_VER_GEN is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal DID_VER_Buffer : std_logic;
-signal GEN_A_Buffer : std_logic;
-signal GEN_K_Buffer : std_logic_vector(0 to 3);
-signal GEN_R_Buffer : std_logic_vector(0 to 3);
-signal GEN_V_Buffer : std_logic_vector(0 to 3);
-
--- Internal Register Declarations --
-
- signal lfsr_reg : std_logic_vector(0 to 3) := "0000";
- signal down_count_r : std_logic_vector(0 to 2) := "000";
- signal downcounter_r : std_logic_vector(0 to 2) := "000";
- signal prev_cycle_gen_ver_r : std_logic;
-
--- Wire Declarations --
-
- signal gen_k_c : std_logic_vector(0 to 3);
- signal gen_r_c : std_logic_vector(0 to 3);
- signal ver_counter_c : std_logic;
- signal gen_k_flop_c : std_logic_vector(0 to 3);
- signal gen_r_flop_c : std_logic_vector(0 to 3);
- signal gen_a_flop_c : std_logic;
- signal downcounter_done_c : std_logic;
- signal gen_ver_edge_c : std_logic;
- signal recycle_gen_ver_c : std_logic;
- signal insert_ver_c : std_logic;
-
- signal tied_to_gnd : std_logic;
- signal tied_to_vcc : std_logic;
-
--- Component Declaration --
-
- component FD
-
- -- synthesis translate_off
- generic (INIT : bit := '0');
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic
-
- );
-
- end component;
-
- component FDR
-
- -- synthesis translate_off
- generic (INIT : bit := '0');
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic;
- R : in std_ulogic
-
- );
-
- end component;
-
- component SRL16
-
- -- synthesis translate_off
- generic (INIT : bit_vector := X"0000");
- -- synthesis translate_on
-
- port (
-
- Q : out std_ulogic;
- A0 : in std_ulogic;
- A1 : in std_ulogic;
- A2 : in std_ulogic;
- A3 : in std_ulogic;
- CLK : in std_ulogic;
- D : in std_ulogic
-
- );
-
- end component;
-
-begin
-
- DID_VER <= DID_VER_Buffer;
- GEN_A <= GEN_A_Buffer;
- GEN_K <= GEN_K_Buffer;
- GEN_R <= GEN_R_Buffer;
- GEN_V <= GEN_V_Buffer;
-
- tied_to_gnd <= '0';
- tied_to_vcc <= '1';
-
--- Main Body of Code --
-
- -- Use an LFSR to create pseudorandom patterns. This is a 4-bit LFSR from
- -- the Aurora 401. Taps on bits 0 and 3 are XORed with the OR of bits 1:3
- -- to make the input to the register.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- lfsr_reg(0) <= lfsr_reg(1);
- lfsr_reg(1) <= lfsr_reg(2);
- lfsr_reg(2) <= lfsr_reg(3);
- lfsr_reg(3) <= (lfsr_reg(0) xor lfsr_reg(3) xor
- (not (lfsr_reg(1) or lfsr_reg(2) or lfsr_reg(3))));
-
- end if;
-
- end process;
-
-
- -- A constants generator is used to limit the downcount range to values
- -- between 3 and 6 (4 to 7 clocks, 16 to 28 bytes).
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case lfsr_reg(1 to 3) is
-
- when "000" => down_count_r <= "011";
- when "001" => down_count_r <= "100";
- when "010" => down_count_r <= "101";
- when "011" => down_count_r <= "110";
- when "100" => down_count_r <= "011";
- when "101" => down_count_r <= "100";
- when "110" => down_count_r <= "101";
- when "111" => down_count_r <= "110";
- when others => down_count_r <= "XXX";
-
- end case;
-
- end if;
-
- end process;
-
- -- Use a downcounter to determine when A's should be added to the idle pattern.
- -- Load the counter with the 3 least significant bits of the lfsr whenever the
- -- counter reaches 0.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- downcounter_r <= "000" after DLY;
-
- else
-
- if (downcounter_done_c = '1') then
-
- downcounter_r <= down_count_r after DLY;
-
- else
-
- downcounter_r <= downcounter_r - "001" after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- downcounter_done_c <= std_bool(downcounter_r = "000");
-
-
- -- The LFSR's pseudo random patterns are also used to generate the sequence of
- -- K and R characters that make up the rest of the idle sequence. Note that
- -- R characters are used whenever K characters are not.
-
- gen_r_c <= lfsr_reg;
- gen_k_c <= not lfsr_reg;
-
- -- Verification Sequence Generation --
-
- -- Use a counter to generate the verification sequence every 64 bytes
- -- (16 clocks), starting from when verification is enabled.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- prev_cycle_gen_ver_r <= GEN_VER after DLY;
-
- end if;
-
- end process;
-
-
- -- Detect the positive edge of the GEN_VER signal.
-
- gen_ver_edge_c <= GEN_VER and not prev_cycle_gen_ver_r;
-
-
- -- If GEN_VER is still high after generating a verification sequence,
- -- indicate that the gen_ver signal can be generated again.
-
- recycle_gen_ver_c <= DID_VER_Buffer and GEN_VER;
-
-
- -- Prime the verification counter SRL16 with a 1. When this 1 reaches the end
- -- of the register, it will become the gen_ver_word signal. Prime the counter
- -- only if there was a positive edge on GEN_VER to start the sequence, or if
- -- the sequence has just ended and another must be generated.
-
- insert_ver_c <= gen_ver_edge_c or recycle_gen_ver_c;
-
-
- -- Main Body of the verification counter. It is implemented as a shift register
- -- made from an SRL16. The register is 15 cycles long, and operates by
- -- taking the 1 from the insert_ver_c signal and passing it though its stages.
-
- ver_counter_i : SRL16
-
-
- -- synthesis translate_off
- generic map (INIT => X"0000")
- -- synthesis translate_on
- port map (
-
- Q => ver_counter_c,
- A0 => tied_to_gnd,
- A1 => tied_to_vcc,
- A2 => tied_to_vcc,
- A3 => tied_to_vcc,
- CLK => USER_CLK,
- D => insert_ver_c
-
- );
-
-
- -- Generate the 4 bytes of the verification sequence on the cycle after
- -- the verification counter reaches '15'. Also signals that the verification
- -- sequence has been generated.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- DID_VER_Buffer <= ver_counter_c after DLY;
-
- end if;
-
- end process;
-
- -- Output Signals --
-
- -- Assert GEN_V in the LSBytes of each lane when DID_VER is asserted. We use
- -- a seperate register for each output to provide enough slack to allow the
- -- Global logic to communicate with all lanes without causing timing problems.
-
- GEN_V_Buffer(0) <= '0';
-
-
- gen_v_flop_1_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
- port map (
-
- D => recycle_gen_ver_c,
- C => USER_CLK,
- Q => GEN_V_Buffer(1)
-
- );
-
-
- gen_v_flop_2_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
- D => recycle_gen_ver_c,
- C => USER_CLK,
- Q => GEN_V_Buffer(2)
- );
-
-
- gen_v_flop_3_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
- D => recycle_gen_ver_c,
- C => USER_CLK,
- Q => GEN_V_Buffer(3)
- );
-
-
- -- Assert GEN_A in the MSByte of each lane when the GEN_A downcounter reaches 0.
- -- Note that the signal has a register for each output for the same reason as the
- -- GEN_V signal. GEN_A is ignored when it collides with other non-idle
- -- generation requests at the Aurora Lane, but we qualify the signal with
- -- the gen_ver_word_1_r signal so it does not overwrite the K used in the
- -- MSByte of the first word of the Verification sequence.
-
- gen_a_flop_c <= downcounter_done_c and not recycle_gen_ver_c;
-
-
- gen_a_flop_0_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_a_flop_c,
- C => USER_CLK,
- Q => GEN_A_Buffer
-
- );
-
-
- -- Assert GEN_K in the MSByte when the lfsr dictates. Turn off the assertion if an
- -- /A/ symbol is being generated on the byte. Assert the signal without qualifications
- -- if GEN_V is asserted. Assert GEN_K in the LSBytes when the lfsr dictates.
- -- There are no qualifications because only the GEN_R signal can collide with it, and
- -- this is prevented by the way the gen_k_c signal is generated. All other GEN signals
- -- will override this signal at the AURORA_LANE.
-
- gen_k_flop_c(0) <= (gen_k_c(0) and not downcounter_done_c) or recycle_gen_ver_c;
-
-
- gen_k_flop_0_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(0),
- C => USER_CLK,
- Q => GEN_K_Buffer(0)
-
- );
-
-
-
- gen_k_flop_c(1) <= gen_k_c(1);
-
-
- gen_k_flop_1_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(1),
- C => USER_CLK,
- Q => GEN_K_Buffer(1)
-
- );
-
-
- gen_k_flop_c(2) <= gen_k_c(2);
-
-
- gen_k_flop_2_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(2),
- C => USER_CLK,
- Q => GEN_K_Buffer(2)
-
- );
-
-
- gen_k_flop_c(3) <= gen_k_c(3);
-
-
- gen_k_flop_3_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_k_flop_c(3),
- C => USER_CLK,
- Q => GEN_K_Buffer(3)
-
- );
-
-
- -- Assert GEN_R in the MSByte when the lfsr dictates. Turn off the assertion if an
- -- /A/ symbol, or the first verification word is being generated. Assert GEN_R in the
- -- LSByte when the lfsr dictates, with no qualifications (same reason as the GEN_K LSByte).
-
- gen_r_flop_c(0) <= gen_r_c(0) and not downcounter_done_c and not recycle_gen_ver_c;
-
-
- gen_r_flop_0_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_r_flop_c(0),
- C => USER_CLK,
- Q => GEN_R_Buffer(0)
-
- );
-
-
- gen_r_flop_c(1) <= gen_r_c(1);
-
-
- gen_r_flop_1_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_r_flop_c(1),
- C => USER_CLK,
- Q => GEN_R_Buffer(1)
-
- );
-
-
- gen_r_flop_c(2) <= gen_r_c(2);
-
-
- gen_r_flop_2_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
-
- D => gen_r_flop_c(2),
- C => USER_CLK,
- Q => GEN_R_Buffer(2)
-
- );
-
-
- gen_r_flop_c(3) <= gen_r_c(3);
-
-
- gen_r_flop_3_i : FD
-
- -- synthesis translate_off
- generic map (INIT => '0')
- -- synthesis translate_on
-
- port map (
- D => gen_r_flop_c(3),
- C => USER_CLK,
- Q => GEN_R_Buffer(3)
- );
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_lane_init_sm_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_lane_init_sm_4byte.vhd
deleted file mode 100644
index 0d93d57b746210970e76b48cd6baf857c9787616..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_lane_init_sm_4byte.vhd
+++ /dev/null
@@ -1,667 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- LANE_INIT_SM_4BYTE
---
---
---
--- Description: This logic manages the initialization of the GTX in 2-byte mode.
--- It consists of a small state machine, a set of counters for
--- tracking the progress of initializtion and detecting problems,
--- and some additional support logic.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
---synthesis translate_on
-
-entity north_channel_LANE_INIT_SM_4BYTE is
- port (
-
- -- GTX Interface
-
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- GTX received invalid 10b code
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- GTX received 10b code w/ wrong disparity
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- GTX received a Comma
- RX_REALIGN : in std_logic; -- GTX had to change alignment due to new comma
- RX_RESET : out std_logic; -- Reset the RX side of the GTX
- TX_RESET : out std_logic; -- Reset the TX side of the GTX
- RX_POLARITY : out std_logic; -- Sets polarity used to interpet rx'ed symbols
-
- -- Comma Detect Phase Alignment Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Turn on SERDES Alignment in GTX
-
- -- Symbol Generator Interface
-
- GEN_SP : out std_logic; -- Generate SP symbol
- GEN_SPA : out std_logic; -- Generate SPA symbol
-
- -- Symbol Decoder Interface
-
- RX_SP : in std_logic; -- Lane rx'ed SP sequence w/ + or - data
- RX_SPA : in std_logic; -- Lane rx'ed SPA sequence
- RX_NEG : in std_logic; -- Lane rx'ed inverted SP or SPA data
- DO_WORD_ALIGN : out std_logic; -- Enable word alignment
-
- -- Error Detection Logic Interface
-
- ENABLE_ERR_DETECT : out std_logic; -- Turn on Soft Error detection
- HARD_ERR_RESET : in std_logic; -- Reset lane due to hard error
-
- -- Global Logic Interface
-
- LANE_UP : out std_logic; -- Lane is initialized
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora logic
- RESET : in std_logic -- Reset Aurora Lane
-
- );
-
-end north_channel_LANE_INIT_SM_4BYTE;
-
-architecture RTL of north_channel_LANE_INIT_SM_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal RX_RESET_Buffer : std_logic;
- signal TX_RESET_Buffer : std_logic;
- signal RX_POLARITY_Buffer : std_logic;
- signal ENA_COMMA_ALIGN_Buffer : std_logic;
- signal GEN_SP_Buffer : std_logic;
- signal GEN_SPA_Buffer : std_logic;
- signal DO_WORD_ALIGN_Buffer : std_logic;
- signal ENABLE_ERR_DETECT_Buffer : std_logic;
- signal LANE_UP_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- -- counter1 is intitialized to ensure that the counter comes up at some value other than X.
- -- We have tried different initial values and it does not matter what the value is, as long
- -- as it is not X since X breaks the state machine
- signal counter1_r : unsigned(0 to 7) := "00000001";
- signal counter2_r : std_logic_vector(0 to 15);
- signal counter3_r : std_logic_vector(0 to 3);
- signal counter4_r : std_logic_vector(0 to 15);
- signal counter5_r : std_logic_vector(0 to 15);
- signal rx_polarity_r : std_logic := '0';
- signal RX_CHAR_IS_COMMA_R : std_logic_vector(3 downto 0);
- signal prev_char_was_comma_r : std_logic;
- signal consecutive_commas_r : std_logic;
- signal prev_count_128d_done_r : std_logic;
- signal do_watchdog_count_r : std_logic;
-
- -- FSM states, encoded for one-hot implementation.
-
- signal begin_r : std_logic;
- signal rst_r : std_logic; -- Reset GTXs
- signal align_r : std_logic; -- Align SERDES
- signal realign_r : std_logic; -- Verify no spurious realignment
- signal polarity_r : std_logic; -- Verify polarity of rx'ed symbols
- signal ack_r : std_logic; -- Ack initialization with partner
- signal ready_r : std_logic; -- Lane ready for Bonding/Verification
-
--- Wire Declarations --
-
- signal count_8d_done_r : std_logic;
- signal count_32d_done_r : std_logic;
- signal count_128d_done_r : std_logic;
- signal reset_count_r : std_logic;
- signal symbol_err_c : std_logic;
- signal txack_16d_done_r : std_logic;
- signal rxack_4d_done_r : std_logic;
- signal sp_polarity_c : std_logic;
- signal inc_count_c : std_logic;
- signal change_in_state_c : std_logic;
- signal watchdog_done_r : std_logic;
- signal remote_reset_watchdog_done_r : std_logic;
-
- signal next_begin_c : std_logic;
- signal next_rst_c : std_logic;
- signal next_align_c : std_logic;
- signal next_realign_c : std_logic;
- signal next_polarity_c : std_logic;
- signal next_ack_c : std_logic;
- signal next_ready_c : std_logic;
-
- component FDR
-
- port (
- D : in std_logic;
- C : in std_logic;
- R : in std_logic;
- Q : out std_logic
- );
-
- end component;
-
-begin
-
- RX_RESET <= RX_RESET_Buffer;
- TX_RESET <= TX_RESET_Buffer;
- RX_POLARITY <= RX_POLARITY_Buffer;
- ENA_COMMA_ALIGN <= ENA_COMMA_ALIGN_Buffer;
- GEN_SP <= GEN_SP_Buffer;
- GEN_SPA <= GEN_SPA_Buffer;
- DO_WORD_ALIGN <= DO_WORD_ALIGN_Buffer;
- ENABLE_ERR_DETECT <= ENABLE_ERR_DETECT_Buffer;
- LANE_UP <= LANE_UP_Buffer;
-
--- Main Body of Code --
-
- -- Main state machine for managing initialization --
-
- -- State registers
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or HARD_ERR_RESET ) = '1') then
-
- begin_r <= '1' after DLY;
- rst_r <= '0' after DLY;
- align_r <= '0' after DLY;
- realign_r <= '0' after DLY;
- polarity_r <= '0' after DLY;
- ack_r <= '0' after DLY;
- ready_r <= '0' after DLY;
-
- else
-
- begin_r <= next_begin_c after DLY;
- rst_r <= next_rst_c after DLY;
- align_r <= next_align_c after DLY;
- realign_r <= next_realign_c after DLY;
- polarity_r <= next_polarity_c after DLY;
- ack_r <= next_ack_c after DLY;
- ready_r <= next_ready_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
- -- Next state logic
-
- next_begin_c <= (realign_r and RX_REALIGN) or
- (polarity_r and not sp_polarity_c) or
- (ack_r and watchdog_done_r) or
- (ready_r and remote_reset_watchdog_done_r);
-
- next_rst_c <= (rst_r and not count_8d_done_r) or begin_r;
-
-
- next_align_c <= (rst_r and count_8d_done_r) or
- (align_r and not count_128d_done_r);
-
-
- next_realign_c <= (align_r and count_128d_done_r) or
- ((realign_r and not count_32d_done_r) and not RX_REALIGN);
-
-
- next_polarity_c <= ((realign_r and count_32d_done_r) and not RX_REALIGN);
-
-
- next_ack_c <= (polarity_r and sp_polarity_c) or
- ((ack_r and (not txack_16d_done_r or not rxack_4d_done_r)) and not watchdog_done_r);
-
-
- next_ready_c <= (ack_r and txack_16d_done_r and rxack_4d_done_r and not watchdog_done_r) or
- (ready_r and not remote_reset_watchdog_done_r);
-
-
- -- Output Logic
-
- -- Enable comma align when in the ALIGN state.
-
- ENA_COMMA_ALIGN_Buffer <= align_r;
-
-
- -- Hold RX_RESET when in the RST state.
-
- RX_RESET_Buffer <= rst_r;
-
-
- -- Hold TX_RESET when in the RST state.
-
- TX_RESET_Buffer <= rst_r;
-
-
- -- LANE_UP is asserted when in the READY state. The FDR flop is
- -- instantiated to ensure that the LANE_UP signal is initialised
- -- to '0' at start-up.
-
- lane_up_flop_i : FDR
-
- port map (
- D => ready_r,
- C => USER_CLK,
- R => RESET,
- Q => LANE_UP_Buffer
- );
-
-
- -- ENABLE_ERR_DETECT is asserted when in the ACK or READY states. Asserting
- -- it earlier will result in too many false errors. After it is asserted,
- -- higher level modules can respond to Hard Errors by resetting the Aurora Lane.
- -- We register the signal before it leaves the lane_init_sm submodule.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- ENABLE_ERR_DETECT_Buffer <= ack_r or ready_r after DLY;
-
- end if;
-
- end process;
-
-
- -- The Aurora Lane should transmit SP sequences when not ACKing or Ready.
-
- GEN_SP_Buffer <= not (ack_r or ready_r);
-
-
- -- The Aurora Lane transmits SPA sequences while in the ACK state.
-
- GEN_SPA_Buffer <= ack_r;
-
-
- -- Do word alignment in the ALIGN state and then again in the ready state. Align
- -- state word alignment makes SP and SPA decodes less expensive. Ready state word
- -- alignment is needed to correct any shifts due to channel bonding : it runs
- -- until it is shut off by arrival of the first /V/ sequence in the sym_dec module.
-
- DO_WORD_ALIGN_Buffer <= align_r or ready_r;
-
-
- -- Counter 1, for reset cycles, align cycles and realign cycles --
-
- -- Core of the counter.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((reset_count_r or ready_r) = '1') then
-
- counter1_r <= "00000001" after DLY;
-
- else
-
- if (inc_count_c = '1') then
-
- counter1_r <= counter1_r + "00000001" after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Assert count_8d_done_r when the 2^4 flop in the register first goes high.
-
- count_8d_done_r <= counter1_r(4);
-
-
- -- Assert count_32d_done_r when the 2^6 flop in the register first goes high.
-
- count_32d_done_r <= counter1_r(2);
-
-
- -- Assert count_128d_done_r when the 2^8 flop in the register first goes high.
-
- count_128d_done_r <= counter1_r(0);
-
-
- -- The counter resets any time the RESET signal is asserted, there is a change in
- -- state, there is a symbol error, or commas are not consecutive in the align state.
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- reset_count_r <= RESET or change_in_state_c or ( not rst_r and (symbol_err_c or not consecutive_commas_r));
-
- end if;
-
- end process;
-
-
- -- The counter should be reset when entering and leaving the reset state.
-
- change_in_state_c <= std_bool(rst_r /= next_rst_c);
-
-
- -- Symbol error is asserted whenever there is a disparity error or an invalid
- -- 10b code.
-
- symbol_err_c <= std_bool((RX_DISP_ERR /= "0000") or (RX_NOT_IN_TABLE /= "0000"));
-
- -- Pipeline stage to meet timing
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_CHAR_IS_COMMA_R <= RX_CHAR_IS_COMMA after DLY;
-
- end if;
-
- end process;
-
- -- Previous cycle comma is used to check for consecutive commas.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- prev_char_was_comma_r <= (RX_CHAR_IS_COMMA_R(3) or RX_CHAR_IS_COMMA_R(2) or
- RX_CHAR_IS_COMMA_R(1) or RX_CHAR_IS_COMMA_R(0)) after DLY;
-
- end if;
-
- end process;
-
-
- -- Check to see that commas are consecutive in the align state.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- consecutive_commas_r <= (RX_CHAR_IS_COMMA_R(3) or RX_CHAR_IS_COMMA_R(2) or
- RX_CHAR_IS_COMMA_R(1) or RX_CHAR_IS_COMMA_R(0)) or not align_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Increment count is always asserted, except in the ALIGN state when it is asserted
- -- only upon the arrival of a comma character.
-
- inc_count_c <= not align_r or (align_r and (RX_CHAR_IS_COMMA_R(3) or RX_CHAR_IS_COMMA_R(2) or
- RX_CHAR_IS_COMMA_R(1) or RX_CHAR_IS_COMMA_R(0)));
-
-
- -- Counter 2, for counting tx_acks --
-
- -- This counter is implemented as a shift register. It is constantly shifting. As a
- -- result, when the state machine is not in the ack state, the register clears out.
- -- When the state machine goes into the ack state, the count is incremented every
- -- cycle. The txack_16d_done signal goes high and stays high after 16 cycles in the
- -- ack state. The signal deasserts only after its had enough time for all the ones
- -- to clear out after the machine leaves the ack state, but this is tolerable because
- -- the machine will spend at least 8 cycles in reset, 256 in ALIGN and 32 in REALIGN.
-
- -- The counter is implemented seperately from the main counter because it is required
- -- to stop counting when it reaches the end of its count. Adding this functionality
- -- to the main counter is more expensive and more complex than implementing it seperately.
-
- -- Counter Logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- counter2_r <= ack_r & counter2_r(0 to 14) after DLY;
-
- end if;
-
- end process;
-
-
- -- The counter is done when a 1 reaches the end of the shift register.
-
- txack_16d_done_r <= counter2_r(15);
-
-
- -- Counter 3, for counting rx_acks --
-
- -- This counter is also implemented as a shift register. It is always shifting when
- -- the state machine is not in the ack state to clear it out. When the state machine
- -- goes into the ack state, the register shifts only when a SPA is received. When
- -- 4 SPAs have been received in the ACK state, the rxack_4d_done_r signal is triggered.
-
- -- This counter is implemented seperately from the main counter because it is required
- -- to increment only when ACKs are received, and then hold its count. Adding this
- -- functionality to the main counter is more expensive than creating a second counter,
- -- and more complex.
-
- -- Counter Logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RX_SPA or not ack_r) = '1') then
-
- counter3_r <= ack_r & counter3_r(0 to 2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The counter is done when a 1 reaches the end of the shift register.
-
- rxack_4d_done_r <= counter3_r(3);
-
-
- -- Counter 4, remote reset watchdog timer --
-
- -- Another counter implemented as a shift register. This counter puts an upper
- -- limit on the number of SPs that can be recieved in the Ready state. If the
- -- number of SPs exceeds the limit, the Aurora Lane resets itself. The Global
- -- logic module will reset all the lanes if this occurs while they are all in
- -- the lane ready state (ie lane_up is asserted for all).
-
- -- Counter logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RX_SP or not ready_r) = '1') then
-
- counter4_r <= ready_r & counter4_r(0 to 14) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The counter is done when a 1 reaches the end of the shift register.
-
- remote_reset_watchdog_done_r <= counter4_r(15);
-
-
- -- Counter 5, internal watchdog timer --
-
- -- This counter puts an upper limit on the number of cycles the state machine can
- -- spend in the ack state before it gives up and resets.
-
- -- The counter is implemented as a shift register extending counter 1. The counter
- -- clears out in all non-ack cycles by keeping CE asserted. When it gets into the
- -- ack state, CE is asserted only when there is a transition on the most
- -- significant bit of counter 1. This happens every 128 cycles. We count out 32 of
- -- these transitions to get a count of approximately 4096 cycles. The actual
- -- number of cycles is less than this because we don't reset counter1, so it
- -- starts off about 34 cycles into its count.
-
- -- Counter logic
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((do_watchdog_count_r or not ack_r) = '1') then
-
- counter5_r <= ack_r & counter5_r(0 to 14) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Store the count_128d_done_r result from the previous cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- prev_count_128d_done_r <= count_128d_done_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Trigger CE only when the previous 128d_done is not the same as the
- -- current one, and the current value is high.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- do_watchdog_count_r <= count_128d_done_r and not prev_count_128d_done_r after DLY;
-
- end if;
-
- end process;
-
-
- -- The counter is done when bit 15 is high.
-
- watchdog_done_r <= counter5_r(15);
-
-
- -- Polarity Control --
-
- -- sp_polarity_c, is low if neg symbols received, otherwise high.
-
- sp_polarity_c <= not RX_NEG;
-
-
- -- The Polarity flop drives the polarity setting of the GTX. We initialize it for the
- -- sake of simulation. We Initialize it after configuration for the hardware version.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((polarity_r and not sp_polarity_c) = '1') then
-
- rx_polarity_r <= not rx_polarity_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Drive the rx_polarity register value on the interface.
-
- RX_POLARITY_Buffer <= rx_polarity_r;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_left_align_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_left_align_control.vhd
deleted file mode 100644
index 08484e678e413f1faa98a4840a0da21042a910f3..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_left_align_control.vhd
+++ /dev/null
@@ -1,243 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- LEFT_ALIGN_CONTROL
---
---
---
--- Description: The LEFT_ALIGN_CONTROL is used to control the Left Align Muxes in
--- the RX_LL module. Each module supports up to 8 lanes. Modules can
--- be combined in stages to support channels with more than 8 lanes.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_LEFT_ALIGN_CONTROL is
-
- port (
-
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
- MUX_SELECT : out std_logic_vector(0 to 5);
- VALID : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_LEFT_ALIGN_CONTROL;
-
-architecture RTL of north_channel_LEFT_ALIGN_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal MUX_SELECT_Buffer : std_logic_vector(0 to 5);
- signal VALID_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal mux_select_c : std_logic_vector(0 to 5);
- signal valid_c : std_logic_vector(0 to 1);
-
-begin
-
- MUX_SELECT <= MUX_SELECT_Buffer;
- VALID <= VALID_Buffer;
-
--- Main Body of Code --
-
- -- SELECT --
-
- -- Lane 0
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "01" =>
-
-mux_select_c(0 to 2) <= conv_std_logic_vector(1,3);
-
-when "10" =>
-
-mux_select_c(0 to 2) <= conv_std_logic_vector(0,3);
-
-when "11" =>
-
-mux_select_c(0 to 2) <= conv_std_logic_vector(0,3);
-
- when others =>
-
- mux_select_c(0 to 2) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Lane 1
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "11" =>
-
-mux_select_c(3 to 5) <= conv_std_logic_vector(0,3);
-
- when others =>
-
- mux_select_c(3 to 5) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the select signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- MUX_SELECT_Buffer <= mux_select_c after DLY;
-
- end if;
-
- end process;
-
-
- -- VALID --
-
- -- Lane 0
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "01" =>
-
- valid_c(0) <= '1';
-
-when "10" =>
-
- valid_c(0) <= '1';
-
-when "11" =>
-
- valid_c(0) <= '1';
-
- when others =>
-
- valid_c(0) <= '0';
-
- end case;
-
- end process;
-
-
- -- Lane 1
-
- process (PREVIOUS_STAGE_VALID(0 to 1))
-
- begin
-
- case PREVIOUS_STAGE_VALID(0 to 1) is
-
-when "11" =>
-
- valid_c(1) <= '1';
-
- when others =>
-
- valid_c(1) <= '0';
-
- end case;
-
- end process;
-
-
- -- Register the valid signals for the next stage.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- VALID_Buffer <= (others => '0') after DLY;
-
- else
-
- VALID_Buffer <= valid_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_left_align_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_left_align_mux.vhd
deleted file mode 100644
index 8cfb45b1558481857c22eacaaa976c719d66e897..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_left_align_mux.vhd
+++ /dev/null
@@ -1,163 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- LEFT_ALIGN_MUX
---
---
---
--- Description: The left align mux is used to shift incoming data symbols
--- leftwards in the channel during the RX_LL left align step.
--- It consists of a set of muxes, one for each position in the
--- channel. The number of inputs for each mux decrements as the
--- position gets further from the left: the muxes for the leftmost
--- position are N:1. The 'muxes' for the rightmost position are 1:1
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_LEFT_ALIGN_MUX is
-
- port (
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end north_channel_LEFT_ALIGN_MUX;
-
-architecture RTL of north_channel_LEFT_ALIGN_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal MUXED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal muxed_data_c : std_logic_vector(0 to 31);
-
-begin
-
- MUXED_DATA <= MUXED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create muxes for each of the lanes.
-
- -- Mux for lane 0
-
- process (MUX_SELECT(0 to 2), RAW_DATA)
-
- begin
-
- case MUX_SELECT(0 to 2) is
-
-when "000" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "001" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (MUX_SELECT(3 to 5), RAW_DATA)
-
- begin
-
- case MUX_SELECT(3 to 5) is
-
-when "000" =>
-
- muxed_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the muxed data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- MUXED_DATA_Buffer <= muxed_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ll_to_axi.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ll_to_axi.vhd
deleted file mode 100644
index e35ca3366006f2db2fbc1ed21b1d2f20bafb226d..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ll_to_axi.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-------------------------------------------------------------------------------
---
--- AXI_TO_LL
---
---
--- Description: This light wrapper/shim convertes Legacy LocalLink interface
--- signals from AXI-4 Stream protocol signals
---
---
-------------------------------------------------------------------------------/
-library IEEE;
-use IEEE.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-
-entity north_channel_LL_TO_AXI is
-generic
-(
- DATA_WIDTH : integer := 16; -- DATA bus width
- STRB_WIDTH : integer := 2; -- STROBE bus width
- USE_UFC_REM : integer := 0; -- UFC REM bus width identifier
- REM_WIDTH : integer := 1 -- REM bus width
-);
-
-port
-(
-
- ---------------------- AXI4-S Interface -------------------------------
- AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_OP_TVALID : out std_logic;
- AXI4_S_OP_TLAST : out std_logic;
- AXI4_S_IP_TREADY : in std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1);
- LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1);
- LL_IP_SRC_RDY_N : in std_logic;
- LL_IP_SOF_N : in std_logic;
- LL_IP_EOF_N : in std_logic;
- LL_OP_DST_RDY_N : out std_logic
-
-);
-
-end north_channel_LL_TO_AXI;
-
-architecture BEHAVIORAL of north_channel_LL_TO_AXI is
- attribute core_generation_info : string;
-attribute core_generation_info of BEHAVIORAL : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
- signal ll_ip_rem_inc_shift : std_logic_vector(0 to STRB_WIDTH-1);
- signal rem_int : integer range 0 to 4;
- signal ufc_rem_int : integer range 0 to 16;
- signal AXI4_S_OP_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1);
-
-begin
-
---*********************************Main Body of Code**********************************
-
- AXI4_S_OP_TDATA <= LL_IP_DATA;
-
-
- AXI4_S_OP_TKEEP <= AXI4_S_OP_TKEEP_i when (LL_IP_EOF_N = '0') else
- (others => '1');
-
-
-
-pdu_rem : if USE_UFC_REM = 0 generate
- rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
-ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl rem_int);
-AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else
- (not ll_ip_rem_inc_shift);
-end generate pdu_rem;
-
-ufc_rem : if USE_UFC_REM = 1 generate
- ufc_rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
-ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl ufc_rem_int);
-AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else
- (not ll_ip_rem_inc_shift);
-end generate ufc_rem;
-
- AXI4_S_OP_TVALID <= not LL_IP_SRC_RDY_N;
- AXI4_S_OP_TLAST <= not LL_IP_EOF_N;
- LL_OP_DST_RDY_N <= not AXI4_S_IP_TREADY;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_output_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_output_mux.vhd
deleted file mode 100644
index 3e2e4908ac0be7b2f200270ef6472c424326aad8..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_output_mux.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- OUTPUT_MUX
---
---
---
--- Description: The OUTPUT_MUX controls the flow of data to the LocalLink output
--- for user PDUs.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_OUTPUT_MUX is
-
- port (
-
- STORAGE_DATA : in std_logic_vector(0 to 31);
- LEFT_ALIGNED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- USER_CLK : in std_logic;
- OUTPUT_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end north_channel_OUTPUT_MUX;
-
-architecture RTL of north_channel_OUTPUT_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal OUTPUT_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal output_data_c : std_logic_vector(0 to 31);
-
-begin
-
- OUTPUT_DATA <= OUTPUT_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create a set of muxes for each lane. The number of inputs for each set of
- -- muxes increases as the lane index increases: lane 0 has one input only, the
- -- rightmost lane has 2 inputs. Note that the 0th input connection
- -- is always to the storage lane with the same index as the output lane: the
- -- remaining inputs connect to the left_aligned data register, starting at index 0.
-
- -- Mux for lane 0
-
- process (MUX_SELECT(0 to 4), STORAGE_DATA)
-
- begin
-
- case MUX_SELECT(0 to 4) is
-
-when "00000" =>
-
- output_data_c(0 to 15) <= STORAGE_DATA(0 to 15);
-
- when others =>
-
- output_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (MUX_SELECT(5 to 9), STORAGE_DATA, LEFT_ALIGNED_DATA)
-
- begin
-
- case MUX_SELECT(5 to 9) is
-
-when "00000" =>
-
- output_data_c(16 to 31) <= STORAGE_DATA(16 to 31);
-
-when "00001" =>
-
- output_data_c(16 to 31) <= LEFT_ALIGNED_DATA(0 to 15);
-
- when others =>
-
- output_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the output data
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- OUTPUT_DATA_Buffer <= output_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_output_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_output_switch_control.vhd
deleted file mode 100644
index 4cd97a747b1200e09f9ba26496a5d1b828d40f3b..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_output_switch_control.vhd
+++ /dev/null
@@ -1,150 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--------------------------------------------------------------------------------
---
--- OUTPUT_SWITCH_CONTROL
---
--------------------------------------------------------------------------------
---
---
--- Description: OUTPUT_SWITCH_CONTROL selects the input chunk for each muxed output chunk.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_OUTPUT_SWITCH_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- OUTPUT_SELECT : out std_logic_vector(0 to 9);
- USER_CLK : in std_logic
-
- );
-
-end north_channel_OUTPUT_SWITCH_CONTROL;
-
-architecture RTL of north_channel_OUTPUT_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal OUTPUT_SELECT_Buffer : std_logic_vector(0 to 9);
-
--- Internal Register Declarations --
-
- signal output_select_c : std_logic_vector(0 to 9);
-
--- Wire Declarations --
-
- signal take_storage_c : std_logic;
-
-begin
-
- OUTPUT_SELECT <= OUTPUT_SELECT_Buffer;
-
-
--- *************************** Main Body of Code ****************************
-
- -- Combine the End signals --
-
- take_storage_c <= END_STORAGE or START_WITH_DATA;
-
-
- -- Generate switch signals --
-
- -- Lane 0 is always connected to storage lane 0.
-
- -- Calculate switch setting for lane 1.
- process (take_storage_c, LEFT_ALIGNED_COUNT, STORAGE_COUNT)
- variable vec : std_logic_vector(0 to 3);
- begin
- if (take_storage_c = '1') then
- output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
- else
- vec := LEFT_ALIGNED_COUNT & STORAGE_COUNT;
- case vec is
-when "0001" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-when "0010" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
-when "0101" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-when "0110" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
-when "1001" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-when "1010" =>
-output_select_c(5 to 9) <= conv_std_logic_vector(0,5);
- when others =>
- output_select_c(5 to 9) <= (others => 'X');
- end case;
- end if;
- end process;
-
-
- -- Register the output select values.
- process (USER_CLK)
- begin
- if (USER_CLK 'event and USER_CLK = '1') then
- OUTPUT_SELECT_Buffer <= "00000" & output_select_c(5 to 9) after DLY;
- end if;
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_reset_logic.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_reset_logic.vhd
deleted file mode 100644
index 9621175b7a4ce9a3e981cfb417bc17ec6f732956..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_reset_logic.vhd
+++ /dev/null
@@ -1,301 +0,0 @@
-
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
----------------------------------------------------------------------------------------------
--- AURORA RESET LOGIC
---
---
--- Description: RESET logic using Debouncer
---
---
-
-library IEEE;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_1164.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
--- synthesis translate_on
-
-entity north_channel_RESET_LOGIC is
- port (
- RESET : in std_logic;
- USER_CLK : in std_logic;
- INIT_CLK_IN : in std_logic;
- TX_LOCK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- LINK_RESET_IN : in std_logic;
- TX_RESETDONE_IN : in std_logic;
- RX_RESETDONE_IN : in std_logic;
- SYSTEM_RESET : out std_logic
- );
-
-end north_channel_RESET_LOGIC;
-
-architecture MAPPED of north_channel_RESET_LOGIC is
- attribute DowngradeIPIdentifiedWarnings: string;
- attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
- attribute core_generation_info : string;
- attribute core_generation_info of MAPPED : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- Internal Register Declarations --
-
- signal link_reset_sync : std_logic;
- signal link_reset_comb_r : std_logic;
- signal pll_not_locked_sync: std_logic;
- signal tx_lock_sync : std_logic;
- signal tx_lock_comb_r : std_logic;
- signal gt_rxresetdone_r : std_logic;
- signal gt_rxresetdone_r2 : std_logic;
- signal gt_rxresetdone_r3 : std_logic;
- signal gt_txresetdone_r : std_logic;
- signal gt_txresetdone_r2 : std_logic;
- signal gt_txresetdone_r3 : std_logic;
- signal tx_resetdone_sync : std_logic;
- signal tied_to_ground_i : std_logic;
-
--- Component Declarations --
-
- component north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
-
- end component;
-
-
- component IBUFDS
- port (
-
- O : out std_ulogic;
- I : in std_ulogic;
- IB : in std_ulogic);
-
- end component;
-
-begin
-
- -- Tie off top level constants.
- tied_to_ground_i <= '0';
-
- -- ___________________________Debouncing circuit for GT_RESET_IN________________________
-
- process (USER_CLK, RX_RESETDONE_IN)
- begin
- if (RX_RESETDONE_IN = '0') then
- gt_rxresetdone_r <= '0' after DLY;
- gt_rxresetdone_r2 <= '0' after DLY;
- elsif (USER_CLK 'event and USER_CLK = '1') then
- gt_rxresetdone_r <= RX_RESETDONE_IN after DLY;
- gt_rxresetdone_r2 <= gt_rxresetdone_r after DLY;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- gt_rxresetdone_r3 <= gt_rxresetdone_r2 after DLY;
- end if;
- end process;
-
-
- tx_resetdone_sync <= TX_RESETDONE_IN;
-
- process (USER_CLK, tx_resetdone_sync)
- begin
- if (tx_resetdone_sync = '0') then
- gt_txresetdone_r <= '0' after DLY;
- gt_txresetdone_r2 <= '0' after DLY;
- elsif (USER_CLK 'event and USER_CLK = '1') then
- gt_txresetdone_r <= tx_resetdone_sync after DLY;
- gt_txresetdone_r2 <= gt_txresetdone_r after DLY;
- end if;
- end process;
-
- --FF for slack violations fix
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- gt_txresetdone_r3 <= gt_txresetdone_r2 after DLY;
- end if;
- end process;
-
-
- --This flop will pipeline wide-OR in case of multi-lane
- process(INIT_CLK_IN)
- begin
- if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
- link_reset_comb_r <= LINK_RESET_IN after DLY;
- end if;
- end process;
-
- link_reset_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => INIT_CLK_IN ,
- prmry_resetn => '1' ,
- prmry_in => link_reset_comb_r ,
- prmry_vect_in => "00" ,
- scndry_aclk => USER_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => link_reset_sync ,
- scndry_vect_out => open
- );
-
- pll_not_locked_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 0 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => INIT_CLK_IN ,
- prmry_resetn => '1' ,
- prmry_in => PLL_NOT_LOCKED ,
- prmry_vect_in => "00" ,
- scndry_aclk => USER_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => pll_not_locked_sync ,
- scndry_vect_out => open
- );
-
- --This flop will pipeline wide-OR in case of multi-lane
- process (INIT_CLK_IN)
- begin
- if (INIT_CLK_IN = '1' and INIT_CLK_IN'event) then
- tx_lock_comb_r <= TX_LOCK_IN after DLY;
- end if;
- end process;
-
-
- tx_lock_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1 ,
- c_flop_input => 1 ,
- c_reset_state => 0 ,
- c_single_bit => 1 ,
- c_vector_width => 2 ,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => INIT_CLK_IN ,
- prmry_resetn => '1' ,
- prmry_in => tx_lock_comb_r ,
- prmry_vect_in => "00" ,
- scndry_aclk => USER_CLK ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => tx_lock_sync ,
- scndry_vect_out => open
- );
-
-process (USER_CLK)
-begin
- if (USER_CLK = '1' and USER_CLK'event) then
- SYSTEM_RESET <= (RESET or (not gt_rxresetdone_r3) or (not gt_txresetdone_r3)) or link_reset_sync or (not tx_lock_sync) or pll_not_locked_sync;
- end if;
-end process;
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll.vhd
deleted file mode 100644
index 9adb8f6c90b7d9835cc34d57e23abdb0a7a7eb9f..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll.vhd
+++ /dev/null
@@ -1,366 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- RX_LL
---
---
---
--- Description: The RX_LL module receives data from the Aurora Channel,
--- converts it to LocalLink and sends it to the user interface.
--- It also handles NFC and UFC messages.
---
--- This module supports 2 4-byte lane designs.
---
--- This module supports User Flow Control.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity north_channel_RX_LL is
-
- port (
-
- -- LocalLink PDU Interface
-
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- -- Global Logic Interface
-
- START_RX : in std_logic;
-
- -- Aurora Lane Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
-end north_channel_RX_LL;
-
-architecture MAPPED of north_channel_RX_LL is
-
--- External Register Declarations --
-
-signal RX_D_Buffer : std_logic_vector(0 to 31);
-signal RX_REM_Buffer : std_logic_vector(0 to 1);
- signal RX_SRC_RDY_N_Buffer : std_logic;
- signal RX_SOF_N_Buffer : std_logic;
- signal RX_EOF_N_Buffer : std_logic;
-signal UFC_RX_DATA_Buffer : std_logic_vector(0 to 31);
-signal UFC_RX_REM_Buffer : std_logic_vector(0 to 1);
- signal UFC_RX_SRC_RDY_N_Buffer : std_logic;
- signal UFC_RX_SOF_N_Buffer : std_logic;
- signal UFC_RX_EOF_N_Buffer : std_logic;
- signal FRAME_ERR_Buffer : std_logic;
-
--- Wire Declarations --
-
-signal pdu_pad_i : std_logic_vector(0 to 1);
-signal pdu_data_i : std_logic_vector(0 to 31);
-signal pdu_data_v_i : std_logic_vector(0 to 1);
-signal pdu_scp_i : std_logic_vector(0 to 1);
-signal pdu_ecp_i : std_logic_vector(0 to 1);
-signal ufc_message_start_i : std_logic_vector(0 to 1);
-signal ufc_data_i : std_logic_vector(0 to 31);
-signal ufc_data_v_i : std_logic_vector(0 to 1);
- signal ufc_start_i : std_logic;
-
- signal start_rx_i : std_logic;
-
--- Component Declarations --
-
- component north_channel_UFC_FILTER
-
- port (
-
- -- Aurora Channel Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- PDU Datapath Interface
-
-PDU_DATA : out std_logic_vector(0 to 31);
-PDU_DATA_V : out std_logic_vector(0 to 1);
-PDU_PAD : out std_logic_vector(0 to 1);
-PDU_SCP : out std_logic_vector(0 to 1);
-PDU_ECP : out std_logic_vector(0 to 1);
-
- -- UFC Datapath Interface
-
-UFC_DATA : out std_logic_vector(0 to 31);
-UFC_DATA_V : out std_logic_vector(0 to 1);
-UFC_MESSAGE_START : out std_logic_vector(0 to 1);
- UFC_START : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_RX_LL_PDU_DATAPATH
-
- port (
-
- -- Traffic Separator Interface
-
-PDU_DATA : in std_logic_vector(0 to 31);
-PDU_DATA_V : in std_logic_vector(0 to 1);
-PDU_PAD : in std_logic_vector(0 to 1);
-PDU_SCP : in std_logic_vector(0 to 1);
-PDU_ECP : in std_logic_vector(0 to 1);
-
- -- LocalLink PDU Interface
-
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_RX_LL_UFC_DATAPATH
-
- port (
-
- --Traffic Separator Interface
-
-UFC_DATA : in std_logic_vector(0 to 31);
-UFC_DATA_V : in std_logic_vector(0 to 1);
-UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
-
- --LocalLink UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- --System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
-begin
-
- RX_D <= RX_D_Buffer;
- RX_REM <= RX_REM_Buffer;
- RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
- RX_SOF_N <= RX_SOF_N_Buffer;
- RX_EOF_N <= RX_EOF_N_Buffer;
- UFC_RX_DATA <= UFC_RX_DATA_Buffer;
- UFC_RX_REM <= UFC_RX_REM_Buffer;
- UFC_RX_SRC_RDY_N <= UFC_RX_SRC_RDY_N_Buffer;
- UFC_RX_SOF_N <= UFC_RX_SOF_N_Buffer;
- UFC_RX_EOF_N <= UFC_RX_EOF_N_Buffer;
- FRAME_ERR <= FRAME_ERR_Buffer;
-
- start_rx_i <= not START_RX;
-
--- Main Body of Code --
-
- -- Separate UFC traffic from regular data --
-
- ufc_filter_i : north_channel_UFC_FILTER
-
- port map (
-
- -- Aurora Channel Interface
-
- RX_PAD => RX_PAD,
- RX_PE_DATA => RX_PE_DATA,
- RX_PE_DATA_V => RX_PE_DATA_V,
- RX_SCP => RX_SCP,
- RX_ECP => RX_ECP,
- RX_SUF => RX_SUF,
- RX_FC_NB => RX_FC_NB,
-
- -- PDU Datapath Interface
-
- PDU_DATA => pdu_data_i,
- PDU_DATA_V => pdu_data_v_i,
- PDU_PAD => pdu_pad_i,
- PDU_SCP => pdu_scp_i,
- PDU_ECP => pdu_ecp_i,
-
- -- UFC Datapath Interface
-
- UFC_DATA => ufc_data_i,
- UFC_DATA_V => ufc_data_v_i,
- UFC_MESSAGE_START => ufc_message_start_i,
- UFC_START => ufc_start_i,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => start_rx_i
-
- );
-
-
- -- Datapath for user PDUs --
-
- rx_ll_pdu_datapath_i : north_channel_RX_LL_PDU_DATAPATH
-
- port map (
-
- -- Traffic Separator Interface
-
- PDU_DATA => pdu_data_i,
- PDU_DATA_V => pdu_data_v_i,
- PDU_PAD => pdu_pad_i,
- PDU_SCP => pdu_scp_i,
- PDU_ECP => pdu_ecp_i,
-
- -- LocalLink PDU Interface
-
- RX_D => RX_D_Buffer,
- RX_REM => RX_REM_Buffer,
- RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer,
- RX_SOF_N => RX_SOF_N_Buffer,
- RX_EOF_N => RX_EOF_N_Buffer,
-
- -- Error Interface
-
- FRAME_ERR => FRAME_ERR_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => start_rx_i
-
- );
-
-
- -- Datapath for UFC PDUs --
-
- rx_ll_ufc_datapath_i : north_channel_RX_LL_UFC_DATAPATH
-
- port map (
-
- -- Traffic Separator Interface
-
- UFC_DATA => ufc_data_i,
- UFC_DATA_V => ufc_data_v_i,
- UFC_MESSAGE_START => ufc_message_start_i,
- UFC_START => ufc_start_i,
-
- -- LocalLink PDU Interface
-
- UFC_RX_DATA => UFC_RX_DATA_Buffer,
- UFC_RX_REM => UFC_RX_REM_Buffer,
- UFC_RX_SRC_RDY_N => UFC_RX_SRC_RDY_N_Buffer,
- UFC_RX_SOF_N => UFC_RX_SOF_N_Buffer,
- UFC_RX_EOF_N => UFC_RX_EOF_N_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK,
- RESET => start_rx_i
-
- );
-
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_deframer.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_deframer.vhd
deleted file mode 100644
index 8ad1b302e32aa9e3729ca643088f8b17b79074c7..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_deframer.vhd
+++ /dev/null
@@ -1,297 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- RX_LL_DEFRAMER
---
---
---
--- Description: The RX_LL_DEFRAMER extracts framing information from incoming channel
--- data beats. It detects the start and end of frames, invalidates data
--- that is outside of a frame, and generates signals that go to the Output
--- and Storage blocks to indicate when the end of a frame has been detected.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-
-entity north_channel_RX_LL_DEFRAMER is
-
- port (
-
- PDU_DATA_V : in std_logic_vector(0 to 1);
- PDU_SCP : in std_logic_vector(0 to 1);
- PDU_ECP : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
- DEFRAMED_DATA_V : out std_logic_vector(0 to 1);
- IN_FRAME : out std_logic_vector(0 to 1);
- AFTER_SCP : out std_logic_vector(0 to 1)
-
- );
-
-end north_channel_RX_LL_DEFRAMER;
-
-architecture RTL of north_channel_RX_LL_DEFRAMER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal DEFRAMED_DATA_V_Buffer : std_logic_vector(0 to 1);
- signal IN_FRAME_Buffer : std_logic_vector(0 to 1);
- signal AFTER_SCP_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal in_frame_r : std_logic;
- signal tied_gnd : std_logic;
- signal tied_vcc : std_logic;
-
--- Wire Declarations --
-
- signal carry_select_c : std_logic_vector(0 to 1);
- signal after_scp_select_c : std_logic_vector(0 to 1);
- signal in_frame_c : std_logic_vector(0 to 1);
- signal after_scp_c : std_logic_vector(0 to 1);
-
- component MUXCY
-
- port (
-
- O : out std_logic;
- CI : in std_logic;
- DI : in std_logic;
- S : in std_logic
-
- );
-
- end component;
-
-begin
-
- DEFRAMED_DATA_V <= DEFRAMED_DATA_V_Buffer;
- IN_FRAME <= IN_FRAME_Buffer;
- AFTER_SCP <= AFTER_SCP_Buffer;
-
- tied_gnd <= '0';
- tied_vcc <= '1';
-
--- Main Body of Code --
-
- -- Mask Invalid data --
-
- -- Keep track of inframe status between clock cycles.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(RESET = '1') then
-
- in_frame_r <= '0' after DLY;
-
- else
-
- in_frame_r <= in_frame_c(1) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Combinatorial inframe detect for lane 0.
-
- carry_select_c(0) <= not PDU_ECP(0) and not PDU_SCP(0);
-
- in_frame_muxcy_0 : MUXCY
-
- port map (
-
- O => in_frame_c(0),
- CI => in_frame_r,
- DI => PDU_SCP(0),
- S => carry_select_c(0)
-
- );
-
-
- -- Combinatorial inframe detect for 2-byte chunk 1.
-
- carry_select_c(1) <= not PDU_ECP(1) and not PDU_SCP(1);
-
- in_frame_muxcy_1 : MUXCY
-
- port map (
-
- O => in_frame_c(1),
- CI => in_frame_c(0),
- DI => PDU_SCP(1),
- S => carry_select_c(1)
-
- );
-
-
- -- The data from a lane is valid if its valid signal is asserted and it is
- -- inside a frame. Note the use of Bitwise AND.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- DEFRAMED_DATA_V_Buffer <= (others => '0') after DLY;
-
- else
-
- DEFRAMED_DATA_V_Buffer <= (in_frame_c and PDU_DATA_V) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Register the inframe status.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- IN_FRAME_Buffer <= conv_std_logic_vector(0,2) after DLY;
-
- else
-
- IN_FRAME_Buffer <= in_frame_r & in_frame_c(0 to 0) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Mark lanes that could contain data that occurs after an SCP. --
-
- -- Combinatorial data after start detect for lane 0.
-
- after_scp_select_c(0) <= not PDU_SCP(0);
-
- data_after_start_muxcy_0:MUXCY
-
- port map (
-
- O => after_scp_c(0),
- CI => tied_gnd,
- DI => tied_vcc,
- S => after_scp_select_c(0)
-
- );
-
-
- -- Combinatorial data after start detect for lane1.
-
- after_scp_select_c(1) <= not PDU_SCP(1);
-
- data_after_start_muxcy_1:MUXCY
-
- port map (
-
- O => after_scp_c(1),
- CI => after_scp_c(0),
- DI => tied_vcc,
- S => after_scp_select_c(1)
- );
-
-
- -- Register the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- AFTER_SCP_Buffer <= (others => '0');
-
- else
-
- AFTER_SCP_Buffer <= after_scp_c;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_pdu_datapath.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_pdu_datapath.vhd
deleted file mode 100644
index 2a8cbefe124b768ef0902c199758d307f9fad64c..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_pdu_datapath.vhd
+++ /dev/null
@@ -1,712 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
---
--- RX_LL_PDU_DATAPATH
---
---
--- Description: the RX_LL_PDU_DATAPATH module takes regular PDU data in Aurora format
--- and transforms it to LocalLink formatted data
---
--- This module supports 2 4-byte lane designs
---
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_RX_LL_PDU_DATAPATH is
-
- port (
-
- -- Traffic Separator Interface
-
-PDU_DATA : in std_logic_vector(0 to 31);
-PDU_DATA_V : in std_logic_vector(0 to 1);
-PDU_PAD : in std_logic_vector(0 to 1);
-PDU_SCP : in std_logic_vector(0 to 1);
-PDU_ECP : in std_logic_vector(0 to 1);
-
- -- LocalLink PDU Interface
-
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_RX_LL_PDU_DATAPATH;
-
-
-architecture RTL of north_channel_RX_LL_PDU_DATAPATH is
-
---****************************Parameter Declarations**************************
-
- constant DLY : time := 1 ns;
-
-
---****************************External Register Declarations**************************
-
-signal RX_D_Buffer : std_logic_vector(0 to 31);
-signal RX_REM_Buffer : std_logic_vector(0 to 1);
- signal RX_SRC_RDY_N_Buffer : std_logic;
- signal RX_SOF_N_Buffer : std_logic;
- signal RX_EOF_N_Buffer : std_logic;
- signal FRAME_ERR_Buffer : std_logic;
-
-
---****************************Internal Register Declarations**************************
- --Stage 1
- signal stage_1_data_r : std_logic_vector(0 to 31);
- signal stage_1_pad_r : std_logic;
- signal stage_1_ecp_r : std_logic_vector(0 to 1);
- signal stage_1_scp_r : std_logic_vector(0 to 1);
- signal stage_1_start_detected_r : std_logic;
-
-
- --Stage 2
- signal stage_2_data_r : std_logic_vector(0 to 31);
- signal stage_2_pad_r : std_logic;
- signal stage_2_start_with_data_r : std_logic;
- signal stage_2_end_before_start_r : std_logic;
- signal stage_2_end_after_start_r : std_logic;
- signal stage_2_start_detected_r : std_logic;
- signal stage_2_frame_err_r : std_logic;
-
-
-
-
-
-
-
---*********************************Wire Declarations**********************************
- --Stage 1
- signal stage_1_data_v_r : std_logic_vector(0 to 1);
- signal stage_1_after_scp_r : std_logic_vector(0 to 1);
- signal stage_1_in_frame_r : std_logic_vector(0 to 1);
-
- --Stage 2
- signal stage_2_left_align_select_r : std_logic_vector(0 to 5);
- signal stage_2_data_v_r : std_logic_vector(0 to 1);
-
- signal stage_2_data_v_count_r : std_logic_vector(0 to 1);
- signal stage_2_frame_err_c : std_logic;
-
- --Stage 3
- signal stage_3_data_r : std_logic_vector(0 to 31);
-
-
-
- signal stage_3_storage_count_r : std_logic_vector(0 to 1);
- signal stage_3_storage_ce_r : std_logic_vector(0 to 1);
- signal stage_3_end_storage_r : std_logic;
- signal stage_3_storage_select_r : std_logic_vector(0 to 9);
- signal stage_3_output_select_r : std_logic_vector(0 to 9);
- signal stage_3_src_rdy_n_r : std_logic;
- signal stage_3_sof_n_r : std_logic;
- signal stage_3_eof_n_r : std_logic;
- signal stage_3_rem_r : std_logic_vector(0 to 1);
- signal stage_3_frame_err_r : std_logic;
-
-
-
- --Stage 4
- signal storage_data_r : std_logic_vector(0 to 31);
-
-
-
--- ********************************** Component Declarations ************************************--
-
- component north_channel_RX_LL_DEFRAMER
- port (
- PDU_DATA_V : in std_logic_vector(0 to 1);
- PDU_SCP : in std_logic_vector(0 to 1);
- PDU_ECP : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- DEFRAMED_DATA_V : out std_logic_vector(0 to 1);
- IN_FRAME : out std_logic_vector(0 to 1);
- AFTER_SCP : out std_logic_vector(0 to 1)
- );
- end component;
-
-
- component north_channel_LEFT_ALIGN_CONTROL
- port (
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
-
- MUX_SELECT : out std_logic_vector(0 to 5);
- VALID : out std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
- end component;
-
-
- component north_channel_VALID_DATA_COUNTER
- port (
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- COUNT : out std_logic_vector(0 to 1)
- );
- end component;
-
-
- component north_channel_LEFT_ALIGN_MUX
- port (
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
-
- USER_CLK : in std_logic;
-
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
- end component;
-
-
- component north_channel_STORAGE_COUNT_CONTROL
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- FRAME_ERR : in std_logic;
-
- STORAGE_COUNT : out std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic
- );
- end component;
-
-
- component north_channel_STORAGE_CE_CONTROL
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
-
- STORAGE_CE : out std_logic_vector(0 to 1);
-
- USER_CLK : in std_logic;
- RESET : in std_logic
- );
- end component;
-
-
- component north_channel_STORAGE_SWITCH_CONTROL
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
-
- STORAGE_SELECT : out std_logic_vector(0 to 9);
-
- USER_CLK : in std_logic
- );
- end component;
-
-
- component north_channel_OUTPUT_SWITCH_CONTROL
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
-
- OUTPUT_SELECT : out std_logic_vector(0 to 9);
-
- USER_CLK : in std_logic
- );
- end component;
-
-
- component north_channel_SIDEBAND_OUTPUT
- port (
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_BEFORE_START : in std_logic;
- END_AFTER_START : in std_logic;
- START_DETECTED : in std_logic;
- START_WITH_DATA : in std_logic;
- PAD : in std_logic;
- FRAME_ERR : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- END_STORAGE : out std_logic;
- SRC_RDY_N : out std_logic;
- SOF_N : out std_logic;
- EOF_N : out std_logic;
- RX_REM : out std_logic_vector(0 to 1);
- FRAME_ERR_RESULT : out std_logic
- );
- end component;
-
-
- component north_channel_STORAGE_MUX
- port (
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- STORAGE_CE : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
-
- STORAGE_DATA : out std_logic_vector(0 to 31)
- );
- end component;
-
-
- component north_channel_OUTPUT_MUX
- port (
- STORAGE_DATA : in std_logic_vector(0 to 31);
- LEFT_ALIGNED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- USER_CLK : in std_logic;
-
- OUTPUT_DATA : out std_logic_vector(0 to 31)
- );
- end component;
-
-
-begin
-
---*********************************Main Body of Code**********************************
-
- -- VHDL Helper Logic
- RX_D <= RX_D_Buffer;
- RX_REM <= RX_REM_Buffer;
- RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
- RX_SOF_N <= RX_SOF_N_Buffer;
- RX_EOF_N <= RX_EOF_N_Buffer;
- FRAME_ERR <= FRAME_ERR_Buffer;
-
-
-
-
- --_____Stage 1: Decode Frame Encapsulation and remove unframed data ________
-
-
- stage_1_rx_ll_deframer_i : north_channel_RX_LL_DEFRAMER
- port map
- (
- PDU_DATA_V => PDU_DATA_V,
- PDU_SCP => PDU_SCP,
- PDU_ECP => PDU_ECP,
- USER_CLK => USER_CLK,
- RESET => RESET,
-
- DEFRAMED_DATA_V => stage_1_data_v_r,
- IN_FRAME => stage_1_in_frame_r,
- AFTER_SCP => stage_1_after_scp_r
-
- );
-
-
- --Determine whether there were any SCPs detected, regardless of data
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_1_start_detected_r <= '0' after DLY;
- else
-stage_1_start_detected_r <= std_bool(PDU_SCP /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
- --Pipeline the data signal, and register a signal to indicate whether the data in
- -- the current cycle contained a Pad character.
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- stage_1_data_r <= PDU_DATA after DLY;
-stage_1_pad_r <= std_bool(PDU_PAD /= "00") after DLY;
- stage_1_ecp_r <= PDU_ECP after DLY;
- stage_1_scp_r <= PDU_SCP after DLY;
- end if;
- end process;
-
-
-
- --_______________________Stage 2: First Control Stage ___________________________
-
-
- --We instantiate a LEFT_ALIGN_CONTROL module to drive the select signals for the
- --left align mux in the next stage, and to compute the next stage valid signals
-
- stage_2_left_align_control_i : north_channel_LEFT_ALIGN_CONTROL
- port map(
- PREVIOUS_STAGE_VALID => stage_1_data_v_r,
-
- MUX_SELECT => stage_2_left_align_select_r,
- VALID => stage_2_data_v_r,
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
-
- --Count the number of valid data lanes: this count is used to select which data
- -- is stored and which data is sent to output in later stages
- stage_2_valid_data_counter_i : north_channel_VALID_DATA_COUNTER
- port map(
- PREVIOUS_STAGE_VALID => stage_1_data_v_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
-
- COUNT => stage_2_data_v_count_r
- );
-
-
-
- --Pipeline the data and pad bits
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- stage_2_data_r <= stage_1_data_r after DLY;
- stage_2_pad_r <= stage_1_pad_r after DLY;
- end if;
- end process;
-
-
-
-
- --Determine whether there was any valid data after any SCP characters
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_start_with_data_r <= '0' after DLY;
- else
-stage_2_start_with_data_r <= std_bool((stage_1_data_v_r and stage_1_after_scp_r) /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
-
- --Determine whether there were any ECPs detected before any SPC characters
- -- arrived
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_end_before_start_r <= '0' after DLY;
- else
-stage_2_end_before_start_r <= std_bool((stage_1_ecp_r and not stage_1_after_scp_r) /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
- --Determine whether there were any ECPs detected at all
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_end_after_start_r <= '0' after DLY;
- else
-stage_2_end_after_start_r <= std_bool((stage_1_ecp_r and stage_1_after_scp_r) /= "00") after DLY;
- end if;
- end if;
- end process;
-
-
- --Pipeline the SCP detected signal
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_start_detected_r <= '0' after DLY;
- else
- stage_2_start_detected_r <= stage_1_start_detected_r after DLY;
- end if;
- end if;
- end process;
-
-
-
- --Detect frame errors. Note that the frame error signal is held until the start of
- -- a frame following the data beat that caused the frame error
-stage_2_frame_err_c <= std_bool( (stage_1_ecp_r and not stage_1_in_frame_r) /= "00" ) or
-std_bool( (stage_1_scp_r and stage_1_in_frame_r) /= "00" );
-
-
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- stage_2_frame_err_r <= '0' after DLY;
- elsif(stage_2_frame_err_c = '1') then
- stage_2_frame_err_r <= '1' after DLY;
- elsif((stage_1_start_detected_r or stage_2_frame_err_r) = '1') then
- stage_2_frame_err_r <= '0' after DLY;
- end if;
- end if;
- end process;
-
-
-
-
-
-
-
- --_______________________________ Stage 3 Left Alignment _________________________
-
-
- --We instantiate a left align mux to shift all lanes with valid data in the channel leftward
- --The data is seperated into groups of 8 lanes, and all valid data within each group is left
- --aligned.
- stage_3_left_align_datapath_mux_i : north_channel_LEFT_ALIGN_MUX
- port map(
- RAW_DATA => stage_2_data_r,
- MUX_SELECT => stage_2_left_align_select_r,
- USER_CLK => USER_CLK,
-
- MUXED_DATA => stage_3_data_r
- );
-
-
-
-
-
-
-
- --Determine the number of valid data lanes that will be in storage on the next cycle
- stage_3_storage_count_control_i : north_channel_STORAGE_COUNT_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
- FRAME_ERR => stage_2_frame_err_r,
-
- STORAGE_COUNT => stage_3_storage_count_r,
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
-
- --Determine the CE settings for the storage module for the next cycle
- stage_3_storage_ce_control_i : north_channel_STORAGE_CE_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
-
- STORAGE_CE => stage_3_storage_ce_r,
-
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
-
- --Determine the appropriate switch settings for the storage module for the next cycle
- stage_3_storage_switch_control_i : north_channel_STORAGE_SWITCH_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
-
- STORAGE_SELECT => stage_3_storage_select_r,
-
- USER_CLK => USER_CLK
-
- );
-
-
-
- --Determine the appropriate switch settings for the output module for the next cycle
- stage_3_output_switch_control_i : north_channel_OUTPUT_SWITCH_CONTROL
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_STORAGE => stage_3_end_storage_r,
- START_WITH_DATA => stage_2_start_with_data_r,
-
- OUTPUT_SELECT => stage_3_output_select_r,
-
- USER_CLK => USER_CLK
-
- );
-
-
- --Instantiate a sideband output controller
- sideband_output_i : north_channel_SIDEBAND_OUTPUT
- port map(
- LEFT_ALIGNED_COUNT => stage_2_data_v_count_r,
- STORAGE_COUNT => stage_3_storage_count_r,
- END_BEFORE_START => stage_2_end_before_start_r,
- END_AFTER_START => stage_2_end_after_start_r,
- START_DETECTED => stage_2_start_detected_r,
- START_WITH_DATA => stage_2_start_with_data_r,
- PAD => stage_2_pad_r,
- FRAME_ERR => stage_2_frame_err_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
-
- END_STORAGE => stage_3_end_storage_r,
- SRC_RDY_N => stage_3_src_rdy_n_r,
- SOF_N => stage_3_sof_n_r,
- EOF_N => stage_3_eof_n_r,
- RX_REM => stage_3_rem_r,
- FRAME_ERR_RESULT => stage_3_frame_err_r
- );
-
-
-
-
-
- --________________________________ Stage 4: Storage and Output_______________________
-
-
- --Storage: Data is moved to storage when it cannot be sent directly to the output.
-
- stage_4_storage_mux_i : north_channel_STORAGE_MUX
- port map(
- RAW_DATA => stage_3_data_r,
- MUX_SELECT => stage_3_storage_select_r,
- STORAGE_CE => stage_3_storage_ce_r,
- USER_CLK => USER_CLK,
-
- STORAGE_DATA => storage_data_r
-
- );
-
-
-
- --Output: Data is moved to the locallink output when a full word of valid data is ready,
- -- or the end of a frame is reached
-
- output_mux_i : north_channel_OUTPUT_MUX
- port map(
- STORAGE_DATA => storage_data_r,
- LEFT_ALIGNED_DATA => stage_3_data_r,
- MUX_SELECT => stage_3_output_select_r,
- USER_CLK => USER_CLK,
-
- OUTPUT_DATA => RX_D_Buffer
-
- );
-
-
- --Pipeline LocalLink sideband signals
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- RX_SOF_N_Buffer <= stage_3_sof_n_r after DLY;
- RX_EOF_N_Buffer <= stage_3_eof_n_r after DLY;
- RX_REM_Buffer <= stage_3_rem_r after DLY;
- end if;
- end process;
-
-
- --Pipeline the LocalLink source Ready signal
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- RX_SRC_RDY_N_Buffer <= '1' after DLY;
- else
- RX_SRC_RDY_N_Buffer <= stage_3_src_rdy_n_r after DLY;
- end if;
- end if;
- end process;
-
-
-
- --Pipeline the Frame error signal
- process(USER_CLK)
- begin
- if(USER_CLK 'event and USER_CLK = '1') then
- if(RESET = '1') then
- FRAME_ERR_Buffer <= '0' after DLY;
- else
- FRAME_ERR_Buffer <= stage_3_frame_err_r after DLY;
- end if;
- end if;
- end process;
-
-
-
-end RTL;
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_ufc_datapath.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_ufc_datapath.vhd
deleted file mode 100644
index b28eee77e576d96df2731b9a64fa5925851e3030..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_rx_ll_ufc_datapath.vhd
+++ /dev/null
@@ -1,507 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- RX_LL_UFC_DATAPATH
---
---
---
--- Description: the RX_LL_UFC_DATAPATH module takes UFC data in Aurora format
--- and transforms it to LocalLink formatted data
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_RX_LL_UFC_DATAPATH is
-
- port (
-
- --Traffic Separator Interface
-
-UFC_DATA : in std_logic_vector(0 to 31);
-UFC_DATA_V : in std_logic_vector(0 to 1);
-UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
-
- --LocalLink UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- --System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_RX_LL_UFC_DATAPATH;
-
-architecture RTL of north_channel_RX_LL_UFC_DATAPATH is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
-signal UFC_RX_DATA_Buffer : std_logic_vector(0 to 31);
-signal UFC_RX_REM_Buffer : std_logic_vector(0 to 1);
- signal UFC_RX_SRC_RDY_N_Buffer : std_logic;
- signal UFC_RX_SOF_N_Buffer : std_logic;
- signal UFC_RX_EOF_N_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- -- Stage 1
-
- signal stage_1_data_r : std_logic_vector(0 to 31);
- signal stage_1_ufc_start_r : std_logic;
-
- -- Stage 1
-
- signal barrel_shifter_control_r : std_logic_vector(0 to 1);
- signal barrel_shifted_count_r : std_logic_vector(0 to 1);
-
- -- Stage 2
-
- signal barrel_shifted_data_r : std_logic_vector(0 to 31);
- signal ufc_storage_count_r : std_logic_vector(0 to 1);
- signal ufc_storage_select_r : std_logic_vector(0 to 5);
- signal ufc_output_select_r : std_logic_vector(0 to 5);
- signal stage_2_ufc_src_rdy_n_r : std_logic;
- signal stage_2_ufc_sof_n_r : std_logic;
- signal stage_2_ufc_eof_n_r : std_logic;
- signal stage_2_ufc_rem_r : std_logic_vector(0 to 1);
-
- -- Stage 3
-
- signal ufc_storage_data_r : std_logic_vector(0 to 31);
-
-
--- Component Declarations
-
- component north_channel_UFC_BARREL_SHIFTER_CONTROL
-
- port (
-
- UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- BARREL_SHIFTER_CONTROL : out std_logic_vector(0 to 1)
-
- );
-
- end component;
-
-
- component north_channel_VALID_DATA_COUNTER
-
- port (
-
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
- COUNT : out std_logic_vector(0 to 1)
- );
-
- end component;
-
-
- component north_channel_UFC_BARREL_SHIFTER
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTER_CONTROL : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- -- Mux output
-
- SHIFTED_DATA : out std_logic_vector(0 to 31)
-
- );
-
- end component;
-
-
- component north_channel_UFC_STORAGE_COUNT_CONTROL
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- UFC_STORAGE_COUNT : out std_logic_vector(0 to 1)
-
- );
-
- end component;
-
-
- component north_channel_UFC_STORAGE_SWITCH_CONTROL
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- UFC_STORAGE_SELECT : out std_logic_vector(0 to 5)
-
- );
-
- end component;
-
-
- component north_channel_UFC_OUTPUT_SWITCH_CONTROL
-
- port (
-
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- UFC_OUTPUT_SELECT : out std_logic_vector(0 to 5)
-
- );
-
- end component;
-
-
- component north_channel_UFC_SIDEBAND_OUTPUT
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- UFC_SRC_RDY_N : out std_logic;
- UFC_SOF_N : out std_logic;
- UFC_EOF_N : out std_logic;
- UFC_REM : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_UFC_STORAGE_MUX
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
-
- -- Mux output
-
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
- end component;
-
-
- component north_channel_UFC_OUTPUT_MUX
-
- port (
-
- -- Input interface to the muxes
-
- UFC_STORAGE_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
- end component;
-
-begin
-
- UFC_RX_DATA <= UFC_RX_DATA_Buffer;
- UFC_RX_REM <= UFC_RX_REM_Buffer;
- UFC_RX_SRC_RDY_N <= UFC_RX_SRC_RDY_N_Buffer;
- UFC_RX_SOF_N <= UFC_RX_SOF_N_Buffer;
- UFC_RX_EOF_N <= UFC_RX_EOF_N_Buffer;
-
--- Main Body of Code --
-
- -- Stage 1: Shifter Control and Count --
-
- -- Instantiate a barrel shifter control module.
-
- ufc_barrel_shifter_control_i : north_channel_UFC_BARREL_SHIFTER_CONTROL
-
- port map (
-
- UFC_MESSAGE_START => UFC_MESSAGE_START,
- USER_CLK => USER_CLK,
- BARREL_SHIFTER_CONTROL => barrel_shifter_control_r
-
- );
-
-
- -- Instantiate a Valid Data counter to count the number of valid UFC data lanes
- -- that will be barrel-shifted in the cycle.
-
- ufc_valid_data_counter : north_channel_VALID_DATA_COUNTER
-
- port map (
-
- PREVIOUS_STAGE_VALID => UFC_DATA_V,
- USER_CLK => USER_CLK,
- RESET => RESET,
- COUNT => barrel_shifted_count_r
-
- );
-
-
- -- Pipeline the data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- stage_1_data_r <= UFC_DATA after DLY;
-
- end if;
-
- end process;
-
-
- -- Pipeline the UFC_START signal.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_1_ufc_start_r <= '0' after DLY;
-
- else
-
- stage_1_ufc_start_r <= UFC_START after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Stage 2: Barrel Shifter, control for storage and output --
-
- -- Instantiate a barrel shifter for the UFC data.
-
- ufc_barrel_shifter_i : north_channel_UFC_BARREL_SHIFTER
-
- port map (
-
- RAW_DATA => stage_1_data_r,
- BARREL_SHIFTER_CONTROL => barrel_shifter_control_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
- SHIFTED_DATA => barrel_shifted_data_r
-
- );
-
-
- -- Instantiate a ufc_storage_count controller.
-
- ufc_storage_count_control_i : north_channel_UFC_STORAGE_COUNT_CONTROL
-
- port map (
-
- BARREL_SHIFTED_COUNT => barrel_shifted_count_r,
- UFC_START => stage_1_ufc_start_r,
- USER_CLK => USER_CLK,
- RESET => RESET,
- UFC_STORAGE_COUNT => ufc_storage_count_r
-
- );
-
-
- -- Instantiate a control module for the storage switch.
-
- ufc_storage_switch_control_i : north_channel_UFC_STORAGE_SWITCH_CONTROL
-
- port map (
-
- BARREL_SHIFTED_COUNT => barrel_shifted_count_r,
- UFC_STORAGE_COUNT => ufc_storage_count_r,
- UFC_START => stage_1_ufc_start_r,
- USER_CLK => USER_CLK,
- UFC_STORAGE_SELECT => ufc_storage_select_r
-
- );
-
-
- -- Instantiate a control module for the output switch.
-
- ufc_output_switch_control_i:north_channel_UFC_OUTPUT_SWITCH_CONTROL
-
- port map (
-
- UFC_STORAGE_COUNT => ufc_storage_count_r,
- USER_CLK => USER_CLK,
- UFC_OUTPUT_SELECT => ufc_output_select_r
-
- );
-
-
- -- Instantiate a control module for the sideband signals.
-
- ufc_sideband_output_i : north_channel_UFC_SIDEBAND_OUTPUT
-
- port map (
-
- BARREL_SHIFTED_COUNT => barrel_shifted_count_r,
- UFC_STORAGE_COUNT => ufc_storage_count_r,
- UFC_START => stage_1_ufc_start_r,
- UFC_SRC_RDY_N => stage_2_ufc_src_rdy_n_r,
- UFC_SOF_N => stage_2_ufc_sof_n_r,
- UFC_EOF_N => stage_2_ufc_eof_n_r,
- UFC_REM => stage_2_ufc_rem_r,
- USER_CLK => USER_CLK,
- RESET => RESET
-
- );
-
-
- -- Stage 3:Storage and Output --
-
- -- Instantiate the storage mux.
-
- ufc_storage_mux_i : north_channel_UFC_STORAGE_MUX
-
- port map (
-
- RAW_DATA => barrel_shifted_data_r,
- MUX_SELECT => ufc_storage_select_r,
- USER_CLK => USER_CLK,
- MUXED_DATA => ufc_storage_data_r
-
- );
-
-
- -- Instantiate the output mux.
-
- ufc_output_mux_i : north_channel_UFC_OUTPUT_MUX
-
- port map (
-
- UFC_STORAGE_DATA => ufc_storage_data_r,
- BARREL_SHIFTED_DATA => barrel_shifted_data_r,
- MUX_SELECT => ufc_output_select_r,
- USER_CLK => USER_CLK,
- MUXED_DATA => UFC_RX_DATA_Buffer
-
- );
-
-
- -- Pipeline the LocalLink SRC_RDY_N output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_RX_SRC_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- UFC_RX_SRC_RDY_N_Buffer <= stage_2_ufc_src_rdy_n_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the remaining LocalLink signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_RX_SOF_N_Buffer <= stage_2_ufc_sof_n_r after DLY;
- UFC_RX_EOF_N_Buffer <= stage_2_ufc_eof_n_r after DLY;
- UFC_RX_REM_Buffer <= stage_2_ufc_rem_r after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_scrambler.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_scrambler.vhd
deleted file mode 100644
index 7a37a58d8367e02e6916c263b1b0e26c5e5ab011..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_scrambler.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
-
---***************************** Module Declaration ****************************
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity north_channel_SCRAMBLER is
-
-generic
-(
- C_SEED : std_logic_vector := X"FFFF"
-);
-port
-(
- DOUT : out std_logic_vector(15 downto 0) := X"0000";
-
- DIN : in std_logic_vector(15 downto 0);
- BYPASS : in std_logic;
- EN : in std_logic;
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- CLK : in std_logic
-);
-
-end north_channel_SCRAMBLER;
-
-architecture BEHAVIORAL of north_channel_SCRAMBLER is
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
---**************************************Signal Declarations***************************
-
- signal dataNext : std_logic_vector(15 downto 0);
- signal lfsrNext : std_logic_vector(15 downto 0);
- signal lfsr : std_logic_vector(15 downto 0) :=X"0000";
- signal dout_temp : std_logic_vector(15 downto 0);
-
-begin
-
---*********************************Main Body of Code**********************************
-
- dout_temp <= DIN when (BYPASS = '1') else
- dataNext;
-
- -----------------------------------------------------------------------------
- -- Scrambler / De-Scrambler Register
- -----------------------------------------------------------------------------
- process(CLK)
- begin
- if(CLK'event and CLK='1') then
- if(EN = '1') then
- DOUT <= dout_temp after DLY;
- end if;
- end if;
- end process;
-
- -----------------------------------------------------------------------------
- -- 16-bit LFSR
- -----------------------------------------------------------------------------
- process(CLK)
- begin
- if(CLK'event and CLK='1') then
- if((RESET OR CLEAR)= '1') then
- lfsr <= C_SEED;
- elsif(EN = '1') then
- lfsr <= lfsrNext;
- end if;
- end if;
- end process;
-
- -----------------------------------------------------------------------------
- -- LFSR XORs
- -----------------------------------------------------------------------------
- lfsrNext(0) <= lfsr(8) ;
- lfsrNext(1) <= lfsr(9) ;
- lfsrNext(2) <= lfsr(10) ;
- lfsrNext(3) <= lfsr(8) XOR lfsr(11) ;
- lfsrNext(4) <= lfsr(8) XOR lfsr(9) XOR lfsr(12) ;
- lfsrNext(5) <= lfsr(8) XOR lfsr(9) XOR lfsr(10) XOR lfsr(13) ;
- lfsrNext(6) <= lfsr(9) XOR lfsr(10) XOR lfsr(11) XOR lfsr(14) ;
- lfsrNext(7) <= lfsr(10) XOR lfsr(11) XOR lfsr(12) XOR lfsr(15) ;
- lfsrNext(8) <= lfsr(0) XOR lfsr(11) XOR lfsr(12) XOR lfsr(13) ;
- lfsrNext(9) <= lfsr(1) XOR lfsr(12) XOR lfsr(13) XOR lfsr(14) ;
- lfsrNext(10) <= lfsr(2) XOR lfsr(13) XOR lfsr(14) XOR lfsr(15) ;
- lfsrNext(11) <= lfsr(3) XOR lfsr(14) XOR lfsr(15) ;
- lfsrNext(12) <= lfsr(4) XOR lfsr(15) ;
- lfsrNext(13) <= lfsr(5) ;
- lfsrNext(14) <= lfsr(6) ;
- lfsrNext(15) <= lfsr(7) ;
-
- -----------------------------------------------------------------------------
- -- Additive Scrambler / De-Scrambler XORs
- -----------------------------------------------------------------------------
- dataNext(0) <= EN AND (DIN(0) XOR lfsr(15)) ;
- dataNext(1) <= EN AND (DIN(1) XOR lfsr(14)) ;
- dataNext(2) <= EN AND (DIN(2) XOR lfsr(13)) ;
- dataNext(3) <= EN AND (DIN(3) XOR lfsr(12)) ;
- dataNext(4) <= EN AND (DIN(4) XOR lfsr(11)) ;
- dataNext(5) <= EN AND (DIN(5) XOR lfsr(10)) ;
- dataNext(6) <= EN AND (DIN(6) XOR lfsr(9)) ;
- dataNext(7) <= EN AND (DIN(7) XOR lfsr(8)) ;
- dataNext(8) <= EN AND (DIN(8) XOR lfsr(7)) ;
- dataNext(9) <= EN AND (DIN(9) XOR lfsr(6)) ;
- dataNext(10) <= EN AND (DIN(10) XOR lfsr(5)) ;
- dataNext(11) <= EN AND (DIN(11) XOR lfsr(4)) ;
- dataNext(12) <= EN AND (DIN(12) XOR lfsr(3)) ;
- dataNext(13) <= EN AND (DIN(13) XOR lfsr(2)) ;
- dataNext(14) <= EN AND (DIN(14) XOR lfsr(1)) ;
- dataNext(15) <= EN AND (DIN(15) XOR lfsr(0)) ;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_scrambler_top.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_scrambler_top.vhd
deleted file mode 100644
index a9446bd24bb835d2d7babfbd8718aa3bbc17c71c..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_scrambler_top.vhd
+++ /dev/null
@@ -1,213 +0,0 @@
--------------------------------------------------------------------------------
--- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
--------------------------------------------------------------------------------
-
---***************************** Module Declaration ****************************
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-
-entity north_channel_SCRAMBLER_TOP is
-
-port
-(
- DATA_OUT : out std_logic_vector(31 downto 0);
- CHAR_IS_K_OUT : out std_logic_vector(3 downto 0);
-
- DATA : in std_logic_vector(31 downto 0);
- CHAR_IS_K : in std_logic_vector(3 downto 0);
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- USER_CLK : in std_logic
-);
-
-end north_channel_SCRAMBLER_TOP;
-
-architecture BEHAVIORAL of north_channel_SCRAMBLER_TOP is
-
---***********************************Parameter Declarations***************************
-
- constant DLY : time := 1 ns;
-
---**************************************Signal Declarations***************************
-
- signal en_scrambler : std_logic_vector(1 downto 0);
- signal bypass_w : std_logic_vector(1 downto 0);
- signal bypass_r : std_logic_vector(1 downto 0);
- signal seed_lfsr : std_logic;
- signal user_data : std_logic_vector(31 downto 0);
- signal scrambled_data : std_logic_vector(31 downto 0);
- signal clear_nxt : std_logic;
- signal clear_nxt2 : std_logic;
- signal data_nxt : std_logic_vector(31 downto 0);
-
- component north_channel_SCRAMBLER is
-
- generic
- (
- C_SEED : std_logic_vector := X"FFFF"
- );
-
- port
- (
- DOUT : out std_logic_vector(15 downto 0);
-
- DIN : in std_logic_vector(15 downto 0);
- BYPASS : in std_logic;
- EN : in std_logic;
-
- ---------------------- System Interface ----------------------------
- CLEAR : in std_logic;
- RESET : in std_logic;
- CLK : in std_logic
- );
-
- end component;
-
-
-begin
-
---*********************************Main Body of Code**********************************
-
- -- data pipeline
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- data_nxt <= DATA after DLY;
- end if;
- end process;
-
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- bypass_r <= bypass_w after DLY;
- end if;
- end process;
-
- -- register clear to reset scrambler when CC is being sent from SYM_GEN
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- clear_nxt <= CLEAR after DLY;
- clear_nxt2 <= clear_nxt after DLY;
- end if;
- end process;
-
- seed_lfsr <= clear_nxt2;
-
- bypass_w(0) <= '1' when (RESET = '1') else
- '1' when ((OR_REDUCE(CHAR_IS_K(1 downto 0))) = '1') else
- '0';
-
- bypass_w(1) <= '1' when (RESET = '1') else
- '1' when ((OR_REDUCE(CHAR_IS_K(3 downto 2))) = '1') else
- '0';
-
- user_data(15 downto 0) <= X"0000" when (bypass_w(0) = '1') else
- DATA(15 downto 0);
-
- user_data(31 downto 16) <= X"0000" when (bypass_w(1) = '1') else
- DATA(31 downto 16);
-
- en_scrambler(0) <= NOT bypass_w(0);
-
- en_scrambler(1) <= NOT bypass_w(1);
-
- north_channel_scrambler0_i : north_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(15 downto 0),
- DIN => user_data(15 downto 0),
- EN => en_scrambler(0),
- BYPASS => bypass_w(0),
- CLEAR => seed_lfsr,
- RESET => RESET,
- CLK => USER_CLK
- );
-
- north_channel_scrambler1_i : north_channel_SCRAMBLER
- generic map
- (
- C_SEED => X"FFFF"
- )
- port map
- (
- DOUT => scrambled_data(31 downto 16),
- DIN => user_data(31 downto 16),
- EN => en_scrambler(1),
- BYPASS => bypass_w(1),
- CLEAR => seed_lfsr,
- RESET => RESET,
- CLK => USER_CLK
- );
-
- -- Outputs
-
- DATA_OUT(15 downto 0) <= data_nxt(15 downto 0) when (bypass_r(0) = '1') else
- scrambled_data(15 downto 0);
-
- DATA_OUT(31 downto 16) <= data_nxt(31 downto 16) when (bypass_r(1) = '1') else
- scrambled_data(31 downto 16);
-
- -- CHAR_IS_K pipeline
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK='1') then
- CHAR_IS_K_OUT <= CHAR_IS_K after DLY;
- end if;
- end process;
-
-end BEHAVIORAL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sideband_output.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sideband_output.vhd
deleted file mode 100644
index c12a8b8608927c84cf3d4134c31baa2429841d6f..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sideband_output.vhd
+++ /dev/null
@@ -1,439 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- SIDEBAND_OUTPUT
---
---
--- Description: SIDEBAND_OUTPUT generates the SRC_RDY_N, EOF_N, SOF_N and
--- RX_REM signals for the RX localLink interface.
---
--- This module supports 2 4-byte lane designs.
---
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_SIDEBAND_OUTPUT is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_BEFORE_START : in std_logic;
- END_AFTER_START : in std_logic;
- START_DETECTED : in std_logic;
- START_WITH_DATA : in std_logic;
- PAD : in std_logic;
- FRAME_ERR : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- END_STORAGE : out std_logic;
- SRC_RDY_N : out std_logic;
- SOF_N : out std_logic;
- EOF_N : out std_logic;
- RX_REM : out std_logic_vector(0 to 1);
- FRAME_ERR_RESULT : out std_logic
-
- );
-
-end north_channel_SIDEBAND_OUTPUT;
-
-architecture RTL of north_channel_SIDEBAND_OUTPUT is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal END_STORAGE_Buffer : std_logic;
- signal SRC_RDY_N_Buffer : std_logic;
- signal SOF_N_Buffer : std_logic;
- signal EOF_N_Buffer : std_logic;
- signal RX_REM_Buffer : std_logic_vector(0 to 1);
- signal FRAME_ERR_RESULT_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal start_next_r : std_logic;
- signal start_storage_r : std_logic;
- signal end_storage_r : std_logic;
- signal pad_storage_r : std_logic;
- signal rx_rem_c : std_logic_vector(0 to 2);
-
--- Wire Declarations --
-
- signal word_valid_c : std_logic;
- signal total_lanes_c : std_logic_vector(0 to 2);
- signal excess_c : std_logic;
- signal storage_not_empty_c : std_logic;
-
-begin
-
- END_STORAGE <= END_STORAGE_Buffer;
- SRC_RDY_N <= SRC_RDY_N_Buffer;
- SOF_N <= SOF_N_Buffer;
- EOF_N <= EOF_N_Buffer;
- RX_REM <= RX_REM_Buffer;
- FRAME_ERR_RESULT <= FRAME_ERR_RESULT_Buffer;
-
--- Main Body of Code --
-
- -- Storage not Empty --
-
- -- Determine whether there is any data in storage.
-
- storage_not_empty_c <= std_bool(STORAGE_COUNT /= conv_std_logic_vector(0,2));
-
-
- -- Start Next Register --
-
- -- start_next_r indicates that the Start Storage Register should be set on the next
- -- cycle. This condition occurs when an old frame ends, filling storage with ending
- -- data, and the SCP for the next cycle arrives on the same cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- start_next_r <= '0' after DLY;
-
- else
-
- start_next_r <= (START_DETECTED and
- not START_WITH_DATA) and
- not END_AFTER_START after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Start Storage Register --
-
- -- Setting the start storage register indicates the data in storage is from
- -- the start of a frame. The register is cleared when the data in storage is sent
- -- to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- start_storage_r <= '0' after DLY;
-
- else
-
- if ((start_next_r or START_WITH_DATA) = '1') then
-
- start_storage_r <= '1' after DLY;
-
- else
-
- if (word_valid_c = '1') then
-
- start_storage_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- End Storage Register --
-
- -- Setting the end storage register indicates the data in storage is from the end
- -- of a frame. The register is cleared when the data in storage is sent to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- end_storage_r <= '0' after DLY;
-
- else
-
-if ((((END_BEFORE_START and not START_WITH_DATA) and std_bool(total_lanes_c /= "000")) or
- (END_AFTER_START and START_WITH_DATA)) = '1') then
-
- end_storage_r <= '1' after DLY;
-
- else
-
- end_storage_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- END_STORAGE_Buffer <= end_storage_r;
-
-
- -- Pad Storage Register --
-
- -- Setting the pad storage register indicates that the data in storage had a pad
- -- character associated with it. The register is cleared when the data in storage
- -- is sent to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- pad_storage_r <= '0' after DLY;
-
- else
-
- if (PAD = '1') then
-
- pad_storage_r <= '1' after DLY;
-
- else
-
- if (word_valid_c = '1') then
-
- pad_storage_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Word Valid signal and SRC_RDY register --
-
- -- The word valid signal indicates that the output word has valid data. This can
- -- only occur when data is removed from storage. Furthermore, the data must be
- -- marked as valid so that the user knows to read the data as it appears on the
- -- LocalLink interface.
-
- word_valid_c <= (END_BEFORE_START and START_WITH_DATA) or
- (excess_c and not START_WITH_DATA) or
- (end_storage_r);
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- SRC_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- SRC_RDY_N_Buffer <= not word_valid_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Frame error result signal --
- -- Indicate a frame error whenever the deframer detects a frame error, or whenever
- -- a frame without data is detected.
- -- Empty frames are detected by looking for frames that end while the storage
- -- register is empty. We must be careful not to confuse the data from seperate
- -- frames.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- FRAME_ERR_RESULT_Buffer <= FRAME_ERR or (END_AFTER_START and not START_WITH_DATA) or
-(END_BEFORE_START and std_bool(total_lanes_c = "000") and not START_WITH_DATA) or
- (END_BEFORE_START and START_WITH_DATA and not storage_not_empty_c) after DLY;
-
- end if;
-
- end process;
-
-
-
-
- -- The total_lanes and excess signals --
-
- -- When there is too much data to put into storage, the excess signal is asserted.
-
- total_lanes_c <= conv_std_logic_vector(0,3) + LEFT_ALIGNED_COUNT + STORAGE_COUNT;
-
- excess_c <= std_bool(total_lanes_c > conv_std_logic_vector(2,3));
-
-
- -- The Start of Frame signal --
-
- -- To save logic, start of frame is asserted from the time the start of a frame
- -- is placed in storage to the time it is placed on the locallink output register.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- SOF_N_Buffer <= not start_storage_r after DLY;
-
- end if;
-
- end process;
-
-
- -- The end of frame signal --
-
- -- End of frame is asserted when storage contains ended data, or when an ECP arrives
- -- at the same time as new data that must replace old data in storage.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- EOF_N_Buffer <= not (end_storage_r or ((END_BEFORE_START and
- START_WITH_DATA) and storage_not_empty_c)) after DLY;
-
- end if;
-
- end process;
-
-
- -- The RX_REM signal --
-
- -- RX_REM is equal to the number of bytes written to the output, minus 1 if there is
- -- a pad.
-
- process (PAD, pad_storage_r, START_WITH_DATA, end_storage_r, STORAGE_COUNT, total_lanes_c)
-
- begin
-
- if ((end_storage_r or START_WITH_DATA) = '1') then
-
- if (pad_storage_r = '1') then
-
- rx_rem_c <= conv_std_logic_vector(0,3) + ((STORAGE_COUNT & '0') - conv_std_logic_vector(2,3));
-
- else
-
- rx_rem_c <= conv_std_logic_vector(0,3) + ((STORAGE_COUNT & '0') - conv_std_logic_vector(1,3));
-
- end if;
-
-
- else
-
- if ((PAD or pad_storage_r) = '1') then
-
- rx_rem_c <= (total_lanes_c(1 to 2) & '0') - conv_std_logic_vector(2,3);
-
- else
-
- rx_rem_c <= (total_lanes_c(1 to 2) & '0') - conv_std_logic_vector(1,3);
-
- end if;
-
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_REM_Buffer <= rx_rem_c(1 to 2) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_standard_cc_module.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_standard_cc_module.vhd
deleted file mode 100644
index c6c8022ce5bd5f2ac18bc3e00daeed9012c7cd74..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_standard_cc_module.vhd
+++ /dev/null
@@ -1,314 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STANDARD_CC_MODULE
---
---
--- Description: This module drives the Aurora module's Clock Compensation
--- interface. Clock Compensation sequences are generated according
--- to the requirements in the Aurora Protocol specification.
---
--- This module supports modules with User Flow Control and
--- 1 4-byte lanes.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-entity north_channel_STANDARD_CC_MODULE is
-generic
-(
- CC_FREQ_FACTOR : integer := 12
-);
-port
-(
- -- Clock Compensation Control Interface
- WARN_CC : out std_logic;
- DO_CC : out std_logic;
-
- -- System Interface
- PLL_NOT_LOCKED : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
-
-);
-end north_channel_STANDARD_CC_MODULE;
-
-architecture RTL of north_channel_STANDARD_CC_MODULE is
- attribute core_generation_info : string;
-attribute core_generation_info of RTL : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
---******************************Parameter Declarations*******************************
-
- constant DLY : time := 1 ns;
-
---************************** Internal Register Declarations **************************
-
- signal prepare_count_r : std_logic_vector(0 to 9) := "0000000000";
- signal cc_count_r : std_logic_vector(0 to 5) := "000000";
- signal reset_r : std_logic;
-
- signal count_13d_srl_r : std_logic_vector(0 to 11);
- signal count_13d_flop_r : std_logic;
- signal count_16d_srl_r : std_logic_vector(0 to 14);
- signal count_16d_flop_r : std_logic;
- signal count_24d_srl_r : std_logic_vector(0 to CC_FREQ_FACTOR-2);
- signal count_24d_flop_r : std_logic;
-
---*********************************Wire Declarations**********************************
- signal enable_cc_c : std_logic;
-
- signal start_cc_c : std_logic;
- signal inner_count_done_r : std_logic;
- signal middle_count_done_c : std_logic;
- signal cc_idle_count_done_c : std_logic;
-
---*********************************Main Body of Code**********************************
-begin
-
- --________________________Clock Correction State Machine__________________________
- enable_cc_c <= not RESET;
-
- -- The clock correction state machine is a counter with three sections. The first
- -- section counts out the idle period before a clock correction occurs. The second
- -- section counts out a period when NFC and UFC operations should not be attempted
- -- because they will not be completed. The last section counts out the cycles of
- -- the clock correction sequence.
-
- -- The inner count for the CC counter counts to 13. It is implemented using
- -- an SRL16 and a flop
-
- -- The SRL counts 12 bits of the count
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_13d_srl_r <= "000000000000" after DLY;
- else
- count_13d_srl_r <= (count_13d_flop_r & count_13d_srl_r(0 to 10)) after DLY;
- end if;
- end if;
- end process;
-
- -- The inner count is done when a 1 reaches the end of the SRL
- inner_count_done_r <= count_13d_srl_r(11);
-
- -- The flop extends the shift register to 13 bits for counting. It is held at
- -- zero while channel up is low to clear the register, and is seeded with a
- -- single 1 when channel up transitions from 0 to 1
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_13d_flop_r <= '0' after DLY;
- elsif( (enable_cc_c and reset_r)= '1') then
- count_13d_flop_r <= '1' after DLY;
- else
- count_13d_flop_r <= inner_count_done_r after DLY;
- end if;
- end if;
- end process;
-
- -- The middle count for the CC counter counts to 16. Its count increments only
- -- when the inner count is done. It is implemented using an SRL16 and a flop
-
- -- The SRL counts 15 bits of the count. It is enabled only when the inner count
- -- is done
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if (RESET = '1') then
- count_16d_srl_r <= "000000000000000" after DLY;
- elsif((inner_count_done_r or not enable_cc_c ) = '1') then
- count_16d_srl_r <= ( count_16d_flop_r & count_16d_srl_r(0 to 13) ) after DLY;
- end if;
- end if;
- end process;
-
- -- The middle count is done when a 1 reaches the end of the SRL and the inner
- -- count finishes
- middle_count_done_c <= inner_count_done_r and count_16d_srl_r(14);
-
- -- The flop extends the shift register to 16 bits for counting. It is held at
- -- zero while channel up is low to clear the register, and is seeded with a
- -- single 1 when channel up transitions from 0 to 1
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_16d_flop_r <= '0' after DLY;
- elsif((enable_cc_c and reset_r)='1') then
- count_16d_flop_r <= '1' after DLY;
- elsif(inner_count_done_r = '1') then
- count_16d_flop_r <= middle_count_done_c after DLY;
- end if;
- end if;
- end process;
-
-
- -- The outer count (aka the cc idle count) is done when it reaches 12. Its count
- -- increments only when the middle count is done. It is implemented with an
- -- SRL16 and a flop
-
- -- The SRL counts 23 bits of the count. It is enabled only when the middle count is
- -- done
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_24d_srl_r <= (others => '0') after DLY;
- elsif((middle_count_done_c or not enable_cc_c ) = '1') then
- count_24d_srl_r <= (count_24d_flop_r & count_24d_srl_r(0 to CC_FREQ_FACTOR - 3)) after DLY;
- end if;
- end if;
- end process;
-
- -- The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
- cc_idle_count_done_c <= middle_count_done_c and count_24d_srl_r(CC_FREQ_FACTOR - 2);
-
- -- The flop extends the shift register to 12 bits for counting. It is held at
- -- zero while channel up is low to clear the register, and is seeded with a single
- -- 1 when channel up transitions from 0 to 1
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- count_24d_flop_r <= '0' after DLY;
- elsif( (enable_cc_c and reset_r) = '1') then
- count_24d_flop_r <= '1' after DLY;
- elsif( middle_count_done_c = '1') then
- count_24d_flop_r <= cc_idle_count_done_c after DLY;
- end if;
- end if;
- end process;
-
-
- -- Because UFC and CC sequences are not allowed to preempt one another, there
- -- there is a warning signal to indicate an impending CC sequence. This signal
- -- is used to prevent UFC messages from starting.
-
- -- For 1 lane, we use a 6-cycle count.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- prepare_count_r <= "0000000000" after DLY;
- else
- prepare_count_r <= ("0000" & cc_idle_count_done_c & prepare_count_r(4 to 8)) after DLY;
- end if;
- end if;
- end process;
-
-
- -- The state machine stays in the prepare_cc state from when the cc idle
- -- count finishes, to when the prepare count has finished. While in this
- -- state, UFC operations cannot start, which prevents them from having to
- -- be pre-empted by CC sequences.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- WARN_CC <= '0' after DLY;
- elsif(cc_idle_count_done_c = '1') then
- WARN_CC <= '1' after DLY;
- elsif(prepare_count_r(9) = '1') then
- WARN_CC <= '0' after DLY;
- end if;
- end if;
- end process;
-
- -- Track the state of channel up on the previous cycle. We use this signal to determine
- -- when to seed the shift register counters with ones
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- reset_r <= RESET after DLY;
- end if;
- end process;
-
- --Do a CC after enable_cc_c is asserted or CC_warning is complete.
- start_cc_c <= prepare_count_r(9) or (enable_cc_c and reset_r);
-
- -- This SRL counter keeps track of the number of cycles spent in the CC
- -- sequence. It starts counting when the prepare_cc state ends, and
- -- finishes counting after 3 cycles have passed.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- cc_count_r <= "000000" after DLY;
- else
- cc_count_r <= ( "000" & (not enable_cc_c or prepare_count_r(9)) & cc_count_r(3 to 4) ) after DLY;
- end if;
- end if;
- end process;
-
- -- The TX_LL module stays in the do_cc state for 3 cycles. It starts
- -- when the prepare_cc state ends.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(RESET = '1') then
- DO_CC <= '0' after DLY;
- elsif(start_cc_c = '1') then
- DO_CC <= '1' after DLY;
- elsif(cc_count_r /= "000000" ) then
- DO_CC <= '1' after DLY;
- elsif(cc_count_r = "000000") then
- DO_CC <= '0' after DLY;
- end if;
- end if;
- end process;
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_ce_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_ce_control.vhd
deleted file mode 100644
index e8cf79bba09a6541c1c10e2b3f443965c6f16a6d..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_ce_control.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STORAGE_CE_CONTROL
---
---
---
--- Description: the STORAGE_CE controls the enable signals of the the Storage register
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_STORAGE_CE_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- STORAGE_CE : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_STORAGE_CE_CONTROL;
-
-architecture RTL of north_channel_STORAGE_CE_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_CE_Buffer : std_logic_vector(0 to 1);
-
--- Wire Declarations --
-
- signal overwrite_c : std_logic;
- signal excess_c : std_logic;
- signal ce_command_c : std_logic_vector(0 to 1);
-
-begin
-
- STORAGE_CE <= STORAGE_CE_Buffer;
-
--- Main Body of Code --
-
- -- Combine the end signals.
-
- overwrite_c <= END_STORAGE or START_WITH_DATA;
-
-
- -- For each lane, determine the appropriate CE value.
-
- excess_c <= std_bool(( ("1" & LEFT_ALIGNED_COUNT) + ("1" & STORAGE_COUNT) ) > conv_std_logic_vector(2,3));
-
- ce_command_c(0) <= excess_c or std_bool(STORAGE_COUNT < conv_std_logic_vector(1,2)) or overwrite_c;
- ce_command_c(1) <= excess_c or std_bool(STORAGE_COUNT < conv_std_logic_vector(2,2)) or overwrite_c;
-
-
- -- Register the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- STORAGE_CE_Buffer <= (others => '0') after DLY;
-
- else
-
- STORAGE_CE_Buffer <= ce_command_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_count_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_count_control.vhd
deleted file mode 100644
index cebcb936d615da68169918ab2f55998762843972..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_count_control.vhd
+++ /dev/null
@@ -1,181 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STORAGE_COUNT_CONTROL
---
---
---
--- Description: STORAGE_COUNT_CONTROL sets the storage count value for the next clock
--- cycle
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_STORAGE_COUNT_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- FRAME_ERR : in std_logic;
- STORAGE_COUNT : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_STORAGE_COUNT_CONTROL;
-
-architecture RTL of north_channel_STORAGE_COUNT_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_COUNT_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal storage_count_c : std_logic_vector(0 to 1);
- signal storage_count_r : std_logic_vector(0 to 1);
-
--- Wire Declarations --
-
- signal overwrite_c : std_logic;
- signal sum_c : std_logic_vector(0 to 2);
- signal remainder_c : std_logic_vector(0 to 2);
- signal overflow_c : std_logic;
-
-begin
-
- STORAGE_COUNT <= STORAGE_COUNT_Buffer;
-
--- Main Body of Code --
-
- -- Calculate the value that will be used for the switch.
-
- sum_c <= conv_std_logic_vector(0,3) + LEFT_ALIGNED_COUNT + storage_count_r;
- remainder_c <= sum_c - conv_std_logic_vector(2,3);
-
- overwrite_c <= END_STORAGE or START_WITH_DATA;
- overflow_c <= std_bool(sum_c > conv_std_logic_vector(2,3));
-
-
- process (overwrite_c, overflow_c, sum_c, remainder_c, LEFT_ALIGNED_COUNT)
-
- variable vec : std_logic_vector(0 to 1);
-
- begin
-
- vec := overwrite_c & overflow_c;
-
- case vec is
-
- when "00" =>
-
- storage_count_c <= sum_c(1 to 2);
-
- when "01" =>
-
- storage_count_c <= remainder_c(1 to 2);
-
- when "10" =>
-
- storage_count_c <= LEFT_ALIGNED_COUNT;
-
- when "11" =>
-
- storage_count_c <= LEFT_ALIGNED_COUNT;
-
- when others =>
-
- storage_count_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the Storage Count for the next cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK'event and USER_CLK = '1') then
-
- if ((RESET or FRAME_ERR) = '1') then
-
- storage_count_r <= (others => '0') after DLY;
-
- else
-
- storage_count_r <= storage_count_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Make the output of the storage count register available to other modules.
-
- STORAGE_COUNT_Buffer <= storage_count_r;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_mux.vhd
deleted file mode 100644
index f20567a1536935e3e08da703982c9d3c7510557c..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_mux.vhd
+++ /dev/null
@@ -1,174 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- STORAGE_MUX
---
---
---
--- Description: The STORAGE_MUX has a set of 16 bit muxes to control the
--- flow of data. Every output position has its own N:1 mux.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_STORAGE_MUX is
-
- port (
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 9);
- STORAGE_CE : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- STORAGE_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end north_channel_STORAGE_MUX;
-
-architecture RTL of north_channel_STORAGE_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal storage_data_c : std_logic_vector(0 to 31);
-
-begin
-
- STORAGE_DATA <= STORAGE_DATA_Buffer;
-
--- Main Body of Code --
-
- -- Each lane has a set of 16 N:1 muxes connected to all the raw data lanes.
-
- -- Muxes for Lane 0
-
- process (MUX_SELECT(0 to 4), RAW_DATA)
-
- begin
-
- case MUX_SELECT(0 to 4) is
-
-when "00000" =>
-
- storage_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "00001" =>
-
- storage_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- storage_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Muxes for Lane 1
-
- process (MUX_SELECT(5 to 9), RAW_DATA)
-
- begin
-
- case MUX_SELECT(5 to 9) is
-
-when "00000" =>
-
- storage_data_c(16 to 31) <= RAW_DATA(0 to 15);
-
-when "00001" =>
-
- storage_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- storage_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the stored data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (STORAGE_CE(0) = '1') then
-
- STORAGE_DATA_Buffer(0 to 15) <= storage_data_c(0 to 15) after DLY;
-
- end if;
-
- if (STORAGE_CE(1) = '1') then
-
- STORAGE_DATA_Buffer(16 to 31) <= storage_data_c(16 to 31) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_switch_control.vhd
deleted file mode 100644
index 6913ef8f9b1d8ea31593ff7de2c6a0d5c5b90d7e..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_storage_switch_control.vhd
+++ /dev/null
@@ -1,223 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--------------------------------------------------------------------------------
---
--- STORAGE_SWITCH_CONTROL
---
---
---
--- Description: STORAGE_SWITCH_CONTROL selects the input chunk for each storage chunk mux
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_STORAGE_SWITCH_CONTROL is
-
- port (
-
- LEFT_ALIGNED_COUNT : in std_logic_vector(0 to 1);
- STORAGE_COUNT : in std_logic_vector(0 to 1);
- END_STORAGE : in std_logic;
- START_WITH_DATA : in std_logic;
- STORAGE_SELECT : out std_logic_vector(0 to 9);
- USER_CLK : in std_logic
-
- );
-
-end north_channel_STORAGE_SWITCH_CONTROL;
-
-architecture RTL of north_channel_STORAGE_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal STORAGE_SELECT_Buffer : std_logic_vector(0 to 9);
-
--- Internal Register Declarations --
-
- signal end_r : std_logic;
- signal lac_r : std_logic_vector(0 to 1);
- signal stc_r : std_logic_vector(0 to 1);
- signal storage_select_c : std_logic_vector(0 to 9);
-
--- Wire Declarations --
-
- signal overwrite_c : std_logic;
-
-
-
-begin
-
- STORAGE_SELECT <= STORAGE_SELECT_Buffer;
-
--- Main Body of Code --
-
- -- Combine the end signals.
-
- overwrite_c <= END_STORAGE or START_WITH_DATA;
-
-
- -- Generate switch signals --
-
- process (overwrite_c, LEFT_ALIGNED_COUNT, STORAGE_COUNT)
-
- variable vec : std_logic_vector(0 to 3);
-
- begin
-
- if (overwrite_c = '1') then
-
- storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
- else
-
- vec := LEFT_ALIGNED_COUNT & STORAGE_COUNT;
-
- case vec is
-
-when "0100" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
-when "0110" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
-when "1000" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
-when "1001" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(1,5);
-
-when "1010" =>
-
-storage_select_c(0 to 4) <= conv_std_logic_vector(0,5);
-
- when others =>
-
- storage_select_c(0 to 4) <= (others => 'X');
-
- end case;
-
- end if;
-
- end process;
-
-
- process (overwrite_c, LEFT_ALIGNED_COUNT, STORAGE_COUNT)
-
- variable vec : std_logic_vector(0 to 3);
-
- begin
-
- if (overwrite_c = '1') then
-
- storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
- else
-
- vec := LEFT_ALIGNED_COUNT & STORAGE_COUNT;
-
- case vec is
-
-when "0100" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
-when "0101" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(0,5);
-
-when "0110" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
-when "1000" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
-when "1010" =>
-
-storage_select_c(5 to 9) <= conv_std_logic_vector(1,5);
-
- when others =>
-
- storage_select_c(5 to 9) <= (others => 'X');
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Register the storage select signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- STORAGE_SELECT_Buffer <= storage_select_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sym_dec_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sym_dec_4byte.vhd
deleted file mode 100644
index cd407f9fc565c291d85001e2c3c0c2c347bb1a33..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sym_dec_4byte.vhd
+++ /dev/null
@@ -1,958 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- SYM_DEC_4BYTE
---
---
--- Description: The SYM_DEC_4BYTE module is a symbol decoder for the
--- 4-byte Aurora Lane. Its inputs are the raw data from
--- the GTX. It word-aligns the regular data and decodes
--- all of the Aurora control symbols. Its outputs are the
--- word-aligned data and signals indicating the arrival of
--- specific control characters.
---
--- This module supports User Flow Control
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_SYM_DEC_4BYTE is
-
- port (
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- LSByte is PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- Word aligned data from channel partner.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- Data is valid data and not a control character.
- RX_SCP : out std_logic_vector(0 to 1); -- SCP symbol received.
- RX_ECP : out std_logic_vector(0 to 1); -- ECP symbol received.
- RX_SUF : out std_logic_vector(0 to 1); -- SUF symbol reveived.
- RX_FC_NB : out std_logic_vector(0 to 7); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-
- -- Lane Init SM Interface
-
- DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed.
- LANE_UP : in std_logic;
- RX_SP : out std_logic; -- SP sequence received with positive or negative data.
- RX_SPA : out std_logic; -- SPA sequence received.
- RX_NEG : out std_logic; -- Inverted data for SP or SPA received.
-
- -- Global Logic Interface
-
- GOT_A : out std_logic_vector(0 to 3); -- A character received on indicated byte(s).
- GOT_V : out std_logic; -- V sequence received.
-
- RX_CC : out std_logic; -- CC sequence received.
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- Raw RX data from GTX.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Bits indicating which bytes are control characters.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Rx'ed a comma.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET : in std_logic
-
- );
-
-end north_channel_SYM_DEC_4BYTE;
-
-architecture RTL of north_channel_SYM_DEC_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
- constant K_CHAR_0 : std_logic_vector(0 to 3) := X"B";
- constant K_CHAR_1 : std_logic_vector(0 to 3) := X"C";
- constant SP_DATA_0 : std_logic_vector(0 to 3) := X"4";
- constant SP_DATA_1 : std_logic_vector(0 to 3) := X"A";
- constant SPA_DATA_0 : std_logic_vector(0 to 3) := X"2";
- constant SPA_DATA_1 : std_logic_vector(0 to 3) := X"C";
- constant SP_NEG_DATA_0 : std_logic_vector(0 to 3) := X"B";
- constant SP_NEG_DATA_1 : std_logic_vector(0 to 3) := X"5";
- constant SPA_NEG_DATA_0 : std_logic_vector(0 to 3) := X"D";
- constant SPA_NEG_DATA_1 : std_logic_vector(0 to 3) := X"3";
- constant PAD_0 : std_logic_vector(0 to 3) := X"9";
- constant PAD_1 : std_logic_vector(0 to 3) := X"C";
- constant SCP_0 : std_logic_vector(0 to 3) := X"5";
- constant SCP_1 : std_logic_vector(0 to 3) := X"C";
- constant SCP_2 : std_logic_vector(0 to 3) := X"F";
- constant SCP_3 : std_logic_vector(0 to 3) := X"B";
- constant ECP_0 : std_logic_vector(0 to 3) := X"F";
- constant ECP_1 : std_logic_vector(0 to 3) := X"D";
- constant ECP_2 : std_logic_vector(0 to 3) := X"F";
- constant ECP_3 : std_logic_vector(0 to 3) := X"E";
- constant SUF_0 : std_logic_vector(0 to 3) := X"9";
- constant SUF_1 : std_logic_vector(0 to 3) := X"C";
- constant A_CHAR_0 : std_logic_vector(0 to 3) := X"7";
- constant A_CHAR_1 : std_logic_vector(0 to 3) := X"C";
- constant VER_DATA_0 : std_logic_vector(0 to 3) := X"E";
- constant VER_DATA_1 : std_logic_vector(0 to 3) := X"8";
- constant CC_CHAR_0 : std_logic_vector(0 to 3) := X"F";
- constant CC_CHAR_1 : std_logic_vector(0 to 3) := X"7";
-
--- External Register Declarations --
-
- signal RX_PAD_Buffer : std_logic_vector(0 to 1);
- signal RX_PE_DATA_Buffer : std_logic_vector(0 to 31);
- signal RX_PE_DATA_V_Buffer : std_logic_vector(0 to 1);
- signal RX_SCP_Buffer : std_logic_vector(0 to 1);
- signal RX_ECP_Buffer : std_logic_vector(0 to 1);
- signal RX_SUF_Buffer : std_logic_vector(0 to 1);
- signal RX_FC_NB_Buffer : std_logic_vector(0 to 7);
- signal RX_SP_Buffer : std_logic;
- signal RX_SPA_Buffer : std_logic;
- signal RX_NEG_Buffer : std_logic;
- signal GOT_A_Buffer : std_logic_vector(0 to 3);
- signal GOT_V_Buffer : std_logic;
- signal RX_CC_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal left_align_select_r : std_logic_vector(0 to 1);
- signal previous_cycle_data_r : std_logic_vector(23 downto 0);
- signal previous_cycle_control_r : std_logic_vector(2 downto 0);
- signal word_aligned_data_r : std_logic_vector(0 to 31);
- signal word_aligned_control_bits_r : std_logic_vector(0 to 3);
- signal rx_pe_data_r : std_logic_vector(0 to 31);
- signal rx_pe_control_r : std_logic_vector(0 to 3);
- signal rx_pad_d_r : std_logic_vector(0 to 3);
- signal rx_scp_d_r : std_logic_vector(0 to 7);
- signal rx_ecp_d_r : std_logic_vector(0 to 7);
- signal rx_suf_d_r : std_logic_vector(0 to 3);
- signal rx_sp_r : std_logic_vector(0 to 7);
- signal rx_spa_r : std_logic_vector(0 to 7);
- signal rx_sp_neg_d_r : std_logic_vector(0 to 1);
- signal rx_spa_neg_d_r : std_logic_vector(0 to 1);
- signal rx_v_d_r : std_logic_vector(0 to 7);
- signal got_a_d_r : std_logic_vector(0 to 7);
- signal first_v_received_r : std_logic := '0';
- signal rx_cc_r : std_logic_vector(0 to 7);
-
--- Wire Declarations --
-
- signal got_v_c : std_logic;
-
-begin
-
- RX_PAD <= RX_PAD_Buffer;
- RX_PE_DATA <= RX_PE_DATA_Buffer;
- RX_PE_DATA_V <= RX_PE_DATA_V_Buffer;
- RX_SCP <= RX_SCP_Buffer;
- RX_ECP <= RX_ECP_Buffer;
- RX_SUF <= RX_SUF_Buffer;
- RX_FC_NB <= RX_FC_NB_Buffer;
- RX_SP <= RX_SP_Buffer;
- RX_SPA <= RX_SPA_Buffer;
- RX_NEG <= RX_NEG_Buffer;
- GOT_A <= GOT_A_Buffer;
- GOT_V <= GOT_V_Buffer;
- RX_CC <= RX_CC_Buffer;
-
--- Main Body of Code --
-
- -- Word Alignment --
-
- -- Determine whether the lane is aligned to the left byte (MSByte) or the
- -- right byte (LSByte). This information is used for word alignment. To
- -- prevent the word align from changing during normal operation, we do word
- -- alignment only when it is allowed by the lane_init_sm.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if ((DO_WORD_ALIGN and not first_v_received_r) = '1') then
-
- case RX_CHAR_IS_K is
-
- when "1000" => left_align_select_r <= "00" after DLY;
- when "0100" => left_align_select_r <= "01" after DLY;
- when "0010" => left_align_select_r <= "10" after DLY;
- when "1100" => left_align_select_r <= "01" after DLY;
- when "1110" => left_align_select_r <= "10" after DLY;
- when "0001" => left_align_select_r <= "11" after DLY;
- when others => left_align_select_r <= left_align_select_r after DLY;
-
- end case;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Store bytes 1, 2 and 3 from the previous cycle. If the lane is aligned
- -- on one of those bytes, we use the data in the current cycle.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- previous_cycle_data_r <= RX_DATA(23 downto 0) after DLY;
-
- end if;
-
- end process;
-
-
- -- Store the control bits from bytes 1, 2 and 3 from the previous cycle. If
- -- we align on one of those bytes, we will also need to use their previous
- -- value control bits.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- previous_cycle_control_r <= RX_CHAR_IS_K(2 downto 0) after DLY;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 0.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(0 to 7) <= RX_DATA(31 downto 24) after DLY;
- when "01" => word_aligned_data_r(0 to 7) <= previous_cycle_data_r(23 downto 16) after DLY;
- when "10" => word_aligned_data_r(0 to 7) <= previous_cycle_data_r(15 downto 8) after DLY;
- when "11" => word_aligned_data_r(0 to 7) <= previous_cycle_data_r(7 downto 0) after DLY;
- when others => word_aligned_data_r(0 to 7) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 1.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(8 to 15) <= RX_DATA(23 downto 16) after DLY;
- when "01" => word_aligned_data_r(8 to 15) <= previous_cycle_data_r(15 downto 8) after DLY;
- when "10" => word_aligned_data_r(8 to 15) <= previous_cycle_data_r(7 downto 0) after DLY;
- when "11" => word_aligned_data_r(8 to 15) <= RX_DATA(31 downto 24) after DLY;
- when others => word_aligned_data_r(8 to 15) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 2.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(16 to 23) <= RX_DATA(15 downto 8) after DLY;
- when "01" => word_aligned_data_r(16 to 23) <= previous_cycle_data_r(7 downto 0) after DLY;
- when "10" => word_aligned_data_r(16 to 23) <= RX_DATA(31 downto 24) after DLY;
- when "11" => word_aligned_data_r(16 to 23) <= RX_DATA(23 downto 16) after DLY;
- when others => word_aligned_data_r(16 to 23) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned data byte 3.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_data_r(24 to 31) <= RX_DATA(7 downto 0) after DLY;
- when "01" => word_aligned_data_r(24 to 31) <= RX_DATA(31 downto 24) after DLY;
- when "10" => word_aligned_data_r(24 to 31) <= RX_DATA(23 downto 16) after DLY;
- when "11" => word_aligned_data_r(24 to 31) <= RX_DATA(15 downto 8) after DLY;
- when others => word_aligned_data_r(24 to 31) <= "00000000" after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 0.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(0) <= RX_CHAR_IS_K(3) after DLY;
- when "01" => word_aligned_control_bits_r(0) <= previous_cycle_control_r(2) after DLY;
- when "10" => word_aligned_control_bits_r(0) <= previous_cycle_control_r(1) after DLY;
- when "11" => word_aligned_control_bits_r(0) <= previous_cycle_control_r(0) after DLY;
- when others => word_aligned_control_bits_r(0) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 1.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(2) after DLY;
- when "01" => word_aligned_control_bits_r(1) <= previous_cycle_control_r(1) after DLY;
- when "10" => word_aligned_control_bits_r(1) <= previous_cycle_control_r(0) after DLY;
- when "11" => word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(3) after DLY;
- when others => word_aligned_control_bits_r(1) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 2.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(2) <= RX_CHAR_IS_K(1) after DLY;
- when "01" => word_aligned_control_bits_r(2) <= previous_cycle_control_r(0) after DLY;
- when "10" => word_aligned_control_bits_r(2) <= RX_CHAR_IS_K(3) after DLY;
- when "11" => word_aligned_control_bits_r(2) <= RX_CHAR_IS_K(2) after DLY;
- when others => word_aligned_control_bits_r(2) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Select the word-aligned control bit 3.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- case left_align_select_r is
-
- when "00" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(0) after DLY;
- when "01" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(3) after DLY;
- when "10" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(2) after DLY;
- when "11" => word_aligned_control_bits_r(3) <= RX_CHAR_IS_K(1) after DLY;
- when others => word_aligned_control_bits_r(3) <= '0' after DLY;
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Pipeline the word-aligned data for 1 cycle to match the Decodes.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pe_data_r <= word_aligned_data_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Register the pipelined word-aligned data for the RX_LL interface.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_PE_DATA_Buffer <= rx_pe_data_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode Control Symbols --
-
- -- All decodes are pipelined to keep the number of logic levels to a minimum.
-
- -- Delay the control bits: they are most often used in the second stage of the
- -- decoding process.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pe_control_r <= word_aligned_control_bits_r after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode PAD.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pad_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = PAD_0) after DLY;
- rx_pad_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = PAD_1) after DLY;
- rx_pad_d_r(2) <= std_bool(word_aligned_data_r(24 to 27) = PAD_0) after DLY;
- rx_pad_d_r(3) <= std_bool(word_aligned_data_r(28 to 31) = PAD_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_PAD_Buffer(0) <= std_bool((rx_pad_d_r(0 to 1) = "11") and (rx_pe_control_r(0 to 1)) = "01") after DLY;
- RX_PAD_Buffer(1) <= std_bool((rx_pad_d_r(2 to 3) = "11") and (rx_pe_control_r(2 to 3)) = "01") after DLY;
-
- end if;
-
- end process;
-
-
-
- -- Decode RX_PE_DATA_V.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_PE_DATA_V_Buffer(0) <= not rx_pe_control_r(0) after DLY;
- RX_PE_DATA_V_Buffer(1) <= not rx_pe_control_r(2) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode RX_SCP.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_scp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SCP_0) after DLY;
- rx_scp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SCP_1) after DLY;
- rx_scp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SCP_2) after DLY;
- rx_scp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SCP_3) after DLY;
- rx_scp_d_r(4) <= std_bool(word_aligned_data_r(16 to 19) = SCP_0) after DLY;
- rx_scp_d_r(5) <= std_bool(word_aligned_data_r(20 to 23) = SCP_1) after DLY;
- rx_scp_d_r(6) <= std_bool(word_aligned_data_r(24 to 27) = SCP_2) after DLY;
- rx_scp_d_r(7) <= std_bool(word_aligned_data_r(28 to 31) = SCP_3) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SCP_Buffer(0) <= rx_pe_control_r(0) and
- rx_pe_control_r(1) and
- rx_scp_d_r(0) and
- rx_scp_d_r(1) and
- rx_scp_d_r(2) and
- rx_scp_d_r(3) after DLY;
-
- RX_SCP_Buffer(1) <= rx_pe_control_r(2) and
- rx_pe_control_r(3) and
- rx_scp_d_r(4) and
- rx_scp_d_r(5) and
- rx_scp_d_r(6) and
- rx_scp_d_r(7) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode RX_ECP.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_ecp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = ECP_0) after DLY;
- rx_ecp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = ECP_1) after DLY;
- rx_ecp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = ECP_2) after DLY;
- rx_ecp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = ECP_3) after DLY;
- rx_ecp_d_r(4) <= std_bool(word_aligned_data_r(16 to 19) = ECP_0) after DLY;
- rx_ecp_d_r(5) <= std_bool(word_aligned_data_r(20 to 23) = ECP_1) after DLY;
- rx_ecp_d_r(6) <= std_bool(word_aligned_data_r(24 to 27) = ECP_2) after DLY;
- rx_ecp_d_r(7) <= std_bool(word_aligned_data_r(28 to 31) = ECP_3) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_ECP_Buffer(0) <= rx_pe_control_r(0) and
- rx_pe_control_r(1) and
- rx_ecp_d_r(0) and
- rx_ecp_d_r(1) and
- rx_ecp_d_r(2) and
- rx_ecp_d_r(3) after DLY;
-
- RX_ECP_Buffer(1) <= rx_pe_control_r(2) and
- rx_pe_control_r(3) and
- rx_ecp_d_r(4) and
- rx_ecp_d_r(5) and
- rx_ecp_d_r(6) and
- rx_ecp_d_r(7) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode RX_SUF.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_suf_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SUF_0) after DLY;
- rx_suf_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SUF_1) after DLY;
- rx_suf_d_r(2) <= std_bool(word_aligned_data_r(16 to 19) = SUF_0) after DLY;
- rx_suf_d_r(3) <= std_bool(word_aligned_data_r(20 to 23) = SUF_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SUF_Buffer(0) <= rx_pe_control_r(0) and
- rx_suf_d_r(0) and
- rx_suf_d_r(1) after DLY;
-
- RX_SUF_Buffer(1) <= rx_pe_control_r(2) and
- rx_suf_d_r(2) and
- rx_suf_d_r(3) after DLY;
-
- end if;
-
- end process;
-
-
- -- Extract the Flow Control Size code and register it for the RX_LL interface.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_FC_NB_Buffer(0 to 3) <= rx_pe_data_r(8 to 11) after DLY;
- RX_FC_NB_Buffer(4 to 7) <= rx_pe_data_r(24 to 27) after DLY;
-
- end if;
-
- end process;
-
-
- -- Indicate the SP sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_sp_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
- rx_sp_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
-
- rx_sp_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
- (word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
-
- rx_sp_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
- (word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
-
- rx_sp_r(4) <= std_bool((word_aligned_data_r(16 to 19) = SP_DATA_0) or
- (word_aligned_data_r(16 to 19) = SP_NEG_DATA_0)) after DLY;
-
- rx_sp_r(5) <= std_bool((word_aligned_data_r(20 to 23) = SP_DATA_1) or
- (word_aligned_data_r(20 to 23) = SP_NEG_DATA_1)) after DLY;
-
- rx_sp_r(6) <= std_bool((word_aligned_data_r(24 to 27) = SP_DATA_0) or
- (word_aligned_data_r(24 to 27) = SP_NEG_DATA_0)) after DLY;
-
- rx_sp_r(7) <= std_bool((word_aligned_data_r(28 to 31) = SP_DATA_1) or
- (word_aligned_data_r(28 to 31) = SP_NEG_DATA_1)) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SP_Buffer <= std_bool((rx_pe_control_r = "1000") and (rx_sp_r = X"FF")) after DLY;
-
- end if;
-
- end process;
-
-
- -- Indicate the SPA sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_spa_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
- rx_spa_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
- rx_spa_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
- rx_spa_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
- rx_spa_r(4) <= std_bool(word_aligned_data_r(16 to 19) = SPA_DATA_0) after DLY;
- rx_spa_r(5) <= std_bool(word_aligned_data_r(20 to 23) = SPA_DATA_1) after DLY;
- rx_spa_r(6) <= std_bool(word_aligned_data_r(24 to 27) = SPA_DATA_0) after DLY;
- rx_spa_r(7) <= std_bool(word_aligned_data_r(28 to 31) = SPA_DATA_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_SPA_Buffer <= std_bool((rx_pe_control_r = "1000") and (rx_spa_r = X"FF")) after DLY;
-
- end if;
-
- end process;
-
-
- -- Indicate reversed data received. We look only at the word aligned LSByte
- -- which, during an SP or SPA sequence, will always contain a data byte.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_sp_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0) after DLY;
- rx_sp_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1) after DLY;
-
- rx_spa_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SPA_NEG_DATA_0) after DLY;
- rx_spa_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SPA_NEG_DATA_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_NEG_Buffer <= not rx_pe_control_r(1) and
- std_bool((rx_sp_neg_d_r = "11") or
- (rx_spa_neg_d_r = "11")) after DLY;
-
- end if;
-
- end process;
-
-
- -- Decode GOT_A.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- got_a_d_r(0) <= std_bool(RX_DATA(31 downto 28) = A_CHAR_0) after DLY;
- got_a_d_r(1) <= std_bool(RX_DATA(27 downto 24) = A_CHAR_1) after DLY;
- got_a_d_r(2) <= std_bool(RX_DATA(23 downto 20) = A_CHAR_0) after DLY;
- got_a_d_r(3) <= std_bool(RX_DATA(19 downto 16) = A_CHAR_1) after DLY;
- got_a_d_r(4) <= std_bool(RX_DATA(15 downto 12) = A_CHAR_0) after DLY;
- got_a_d_r(5) <= std_bool(RX_DATA(11 downto 8) = A_CHAR_1) after DLY;
- got_a_d_r(6) <= std_bool(RX_DATA(7 downto 4) = A_CHAR_0) after DLY;
- got_a_d_r(7) <= std_bool(RX_DATA(3 downto 0) = A_CHAR_1) after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- GOT_A_Buffer(0) <= RX_CHAR_IS_K(3) and std_bool(got_a_d_r(0 to 1) = "11") after DLY;
- GOT_A_Buffer(1) <= RX_CHAR_IS_K(2) and std_bool(got_a_d_r(2 to 3) = "11") after DLY;
- GOT_A_Buffer(2) <= RX_CHAR_IS_K(1) and std_bool(got_a_d_r(4 to 5) = "11") after DLY;
- GOT_A_Buffer(3) <= RX_CHAR_IS_K(0) and std_bool(got_a_d_r(6 to 7) = "11") after DLY;
-
- end if;
-
- end process;
-
-
- -- Verification symbol decode --
-
- -- Indicate the SP sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
- rx_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
- rx_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
- rx_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
- rx_v_d_r(4) <= std_bool(word_aligned_data_r(16 to 19) = VER_DATA_0) after DLY;
- rx_v_d_r(5) <= std_bool(word_aligned_data_r(20 to 23) = VER_DATA_1) after DLY;
- rx_v_d_r(6) <= std_bool(word_aligned_data_r(24 to 27) = VER_DATA_0) after DLY;
- rx_v_d_r(7) <= std_bool(word_aligned_data_r(28 to 31) = VER_DATA_1) after DLY;
-
- end if;
-
- end process;
-
-
- got_v_c <= std_bool((rx_pe_control_r = "1000") and (rx_v_d_r = X"FF"));
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- GOT_V_Buffer <= got_v_c after DLY;
-
- end if;
-
- end process;
-
-
- -- Remember that the first V sequence has been detected.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (LANE_UP = '0') then
-
- first_v_received_r <= '0' after DLY;
-
- else
-
- if (got_v_c = '1') then
-
- first_v_received_r <= '1' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
- -- Indicate the CC sequence was received.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_cc_r(0) <= std_bool(word_aligned_data_r(0 to 3) = CC_CHAR_0) after DLY;
- rx_cc_r(1) <= std_bool(word_aligned_data_r(4 to 7) = CC_CHAR_1) after DLY;
- rx_cc_r(2) <= std_bool(word_aligned_data_r(8 to 11) = CC_CHAR_0) after DLY;
- rx_cc_r(3) <= std_bool(word_aligned_data_r(12 to 15) = CC_CHAR_1) after DLY;
- rx_cc_r(4) <= std_bool(word_aligned_data_r(16 to 19) = CC_CHAR_0) after DLY;
- rx_cc_r(5) <= std_bool(word_aligned_data_r(20 to 23) = CC_CHAR_1) after DLY;
- rx_cc_r(6) <= std_bool(word_aligned_data_r(24 to 27) = CC_CHAR_0) after DLY;
- rx_cc_r(7) <= std_bool(word_aligned_data_r(28 to 31) = CC_CHAR_1) after DLY;
-
- end if;
-
- end process;
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- RX_CC_Buffer <= std_bool((rx_pe_control_r = "1111") and
- (rx_cc_r = X"FF")) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sym_gen_4byte.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sym_gen_4byte.vhd
deleted file mode 100644
index 5f6f2c4ed575cf12a131e6e369c7c7352f591fff..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_sym_gen_4byte.vhd
+++ /dev/null
@@ -1,562 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- SYM_GEN_4BYTE
---
---
---
--- Description: The SYM_GEN module is a symbol generator for 4-byte Aurora Lanes.
--- Its inputs request the transmission of specific symbols, and its
--- outputs drive the GTX interface to fulfill those requests.
---
--- All generation request inputs must be asserted exclusively
--- except for the GEN_K, GEN_R and GEN_A signals from the Global
--- Logic, and the GEN_PAD and TX_PE_DATA_V signals from TX_LL.
---
--- GEN_K, GEN_R and GEN_A can be asserted anytime, but they are
--- ignored when other signals are being asserted. This allows the
--- idle generator in the Global Logic to run continuously without
--- feedback, but requires the TX_LL and Lane Init SM modules to
--- be quiescent during Channel Bonding and Verification.
---
--- The GEN_PAD signal is only valid while the TX_PE_DATA_V signal
--- is asserted. This allows padding to be specified for the LSB
--- of the data transmission. GEN_PAD must not be asserted when
--- TX_PE_DATA_V is not asserted - this will generate errors.
---
--- This module supports User Flow Control.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity north_channel_SYM_GEN_4BYTE is
-
- port (
-
- -- TX_LL Interface -- See description for info about GEN_PAD and TX_PE_DATA_V.
-
- GEN_SCP : in std_logic_vector(0 to 1); -- Generate SCP.
- GEN_ECP : in std_logic_vector(0 to 1); -- Generate ECP.
- GEN_SUF : in std_logic_vector(0 to 1); -- Generate SUF using code given by FC_NB.
- GEN_PAD : in std_logic_vector(0 to 1); -- Replace LSB with Pad character.
- FC_NB : in std_logic_vector(0 to 7); -- Size code for Flow Control messages.
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data. Transmitted when TX_PE_DATA_V is asserted.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Transmit data.
- GEN_CC : in std_logic; -- Generate Clock Correction symbols.
-
- -- Global Logic Interface -- See description for info about GEN_K,GEN_R and GEN_A.
-
- GEN_A : in std_logic; -- Generate A character for MSBYTE
- GEN_K : in std_logic_vector(0 to 3); -- Generate K character for selected bytes.
- GEN_R : in std_logic_vector(0 to 3); -- Generate R character for selected bytes.
- GEN_V : in std_logic_vector(0 to 3); -- Generate Ver data character on selected bytes.
-
- -- Lane Init SM Interface
-
- GEN_SP : in std_logic; -- Generate SP pattern.
- GEN_SPA : in std_logic; -- Generate SPA pattern.
-
- -- GTX Interface
-
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- Transmit TX_DATA as a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- Data to GTX for transmission to channel partner.
-
- -- System Interface
-
- USER_CLK : in std_logic; -- Clock for all non-GTX Aurora Logic.
- RESET : in std_logic -- RESET signal to drive TX_CHAR_IS_K to known value
- );
-
-end north_channel_SYM_GEN_4BYTE;
-
-architecture RTL of north_channel_SYM_GEN_4BYTE is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal TX_CHAR_IS_K_Buffer : std_logic_vector(3 downto 0) := "0000";
- signal TX_DATA_Buffer : std_logic_vector(31 downto 0);
-
--- Internal Register Declarations --
-
- -- Slack registers. These registers allow slack for routing delay and automatic retiming.
-
- signal gen_scp_r : std_logic_vector(0 to 1);
- signal gen_ecp_r : std_logic_vector(0 to 1);
- signal gen_suf_r : std_logic_vector(0 to 1);
- signal gen_pad_r : std_logic_vector(0 to 1);
- signal fc_nb_r : std_logic_vector(0 to 7);
- signal tx_pe_data_r : std_logic_vector(0 to 31);
- signal tx_pe_data_v_r : std_logic_vector(0 to 1);
- signal gen_cc_r : std_logic;
- signal gen_a_r : std_logic;
- signal gen_k_r : std_logic_vector(0 to 3);
- signal gen_r_r : std_logic_vector(0 to 3);
- signal gen_v_r : std_logic_vector(0 to 3);
- signal gen_sp_r : std_logic;
- signal gen_spa_r : std_logic;
-
--- Wire Declarations --
-
- signal idle_c : std_logic_vector(0 to 3);
-
-begin
-
- TX_CHAR_IS_K <= TX_CHAR_IS_K_Buffer;
- TX_DATA <= TX_DATA_Buffer;
-
--- Main Body of Code --
-
- -- Register all inputs with the slack registers.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- gen_scp_r <= GEN_SCP after DLY;
- gen_ecp_r <= GEN_ECP after DLY;
- gen_suf_r <= GEN_SUF after DLY;
- gen_pad_r <= GEN_PAD after DLY;
- fc_nb_r <= FC_NB after DLY;
- tx_pe_data_r <= TX_PE_DATA after DLY;
- tx_pe_data_v_r <= TX_PE_DATA_V after DLY;
- gen_cc_r <= GEN_CC after DLY;
- gen_a_r <= GEN_A after DLY;
- gen_k_r <= GEN_K after DLY;
- gen_r_r <= GEN_R after DLY;
- gen_v_r <= GEN_V after DLY;
- gen_sp_r <= GEN_SP after DLY;
- gen_spa_r <= GEN_SPA after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 0 --
-
- -- When none of the byte0 non_idle inputs are asserted, allow idle characters.
-
- idle_c(0) <= not (gen_scp_r(0) or
- gen_ecp_r(0) or
- gen_suf_r(0) or
- tx_pe_data_v_r(0) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(0));
-
-
-
- -- Generate data for byte0. Note that all inputs must be asserted exclusively, except
- -- for the GEN_A, GEN_K and GEN_R inputs which are ignored when other characters
- -- are asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"5C" after DLY; -- K28.2(SCP)
-
- elsif (gen_ecp_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"FD" after DLY; -- K29.7(ECP)
-
- elsif (gen_suf_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"9C" after DLY; -- K28.4(SUF)
-
- elsif (tx_pe_data_v_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= tx_pe_data_r(0 to 7) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(0) and gen_a_r) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"7C" after DLY; -- K28.3(A)
-
- elsif ((idle_c(0) and gen_k_r(0)) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(0) and gen_r_r(0)) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"BC" after DLY; -- K28.5(K)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"BC" after DLY; -- K28.5(K)
-
- elsif (gen_v_r(0) = '1') then
-
- TX_DATA_Buffer(31 downto 24) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for MSB.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(3) <= not (tx_pe_data_v_r(0) or
- gen_v_r(0)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 1 --
-
- -- When none of the byte1 non_idle inputs are asserted, allow idle characters. Note
- -- that because gen_pad is only valid with the data valid signal, we only look at
- -- the data valid signal.
-
- idle_c(1) <= not (gen_scp_r(0) or
- gen_ecp_r(0) or
- gen_suf_r(0) or
- tx_pe_data_v_r(0) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(1));
-
-
- -- Generate data for byte1. Note that all inputs must be asserted exclusively except
- -- for the GEN_PAD signal and the GEN_K and GEN_R set. GEN_PAD can be asserted
- -- at the same time as TX_DATA_VALID. This will override TX_DATA valid and replace
- -- the lsb user data with a PAD character. The GEN_K and GEN_R inputs are
- -- ignored if any other input is asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(0) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"FB" after DLY; -- K27.7(SCP)
-
- elsif (gen_ecp_r(0) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"FE" after DLY; -- K30.7(ECP)
-
- elsif (gen_suf_r(0) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= fc_nb_r(0 to 3) & "0000" after DLY; -- SUF Data
-
- elsif ((tx_pe_data_v_r(0) and gen_pad_r(0)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"9C" after DLY; -- K28.4(PAD)
-
- elsif ((tx_pe_data_v_r(0) and not gen_pad_r(0)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= tx_pe_data_r(8 to 15) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(1) and gen_k_r(1)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(1) and gen_r_r(1)) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"4A" after DLY; -- D10.2(SP data)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"2C" after DLY; -- D12.1(SPA data)
-
- elsif (gen_v_r(1) = '1') then
-
- TX_DATA_Buffer(23 downto 16) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for byte1.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(2) <= not ((tx_pe_data_v_r(0) and not gen_pad_r(0)) or
- gen_suf_r(0) or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(1)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 2 --
-
- -- When none of the byte2 non_idle inputs are asserted, allow idle characters.
-
- idle_c(2) <= not (gen_scp_r(1) or
- gen_ecp_r(1) or
- gen_suf_r(1) or
- tx_pe_data_v_r(1) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(2));
-
-
-
- -- Generate data for byte2. Note that all inputs must be asserted exclusively,
- -- except for the GEN_K and GEN_R inputs which are ignored when other
- -- characters are asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"5C" after DLY; -- K28.2(SCP)
-
- elsif (gen_ecp_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"FD" after DLY; -- K29.7(ECP)
-
- elsif (gen_suf_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"9C" after DLY; -- K28.4(SUF)
-
- elsif (tx_pe_data_v_r(1) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= tx_pe_data_r(16 to 23) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(2) and gen_k_r(2)) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(2) and gen_r_r(2)) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"4A" after DLY; -- D10.2(SP data)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"2C" after DLY; -- D12.1(SPA data)
-
- elsif (gen_v_r(2) = '1') then
-
- TX_DATA_Buffer(15 downto 8) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for MSB.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(1) <= not (tx_pe_data_v_r(1) or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(2)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-
- -- Byte 3 --
-
- -- When none of the byte3 non_idle inputs are asserted, allow idle characters.
- -- Note that because gen_pad is only valid with the data valid signal, we only
- -- look at the data valid signal.
-
- idle_c(3) <= not (gen_scp_r(1) or
- gen_ecp_r(1) or
- gen_suf_r(1) or
- tx_pe_data_v_r(1) or
- gen_cc_r or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(3));
-
-
-
- -- Generate data for byte3. Note that all inputs must be asserted exclusively
- -- except for the GEN_PAD signal and the GEN_K and GEN_R set. GEN_PAD
- -- can be asserted at the same time as TX_DATA_VALID. This will override
- -- TX_DATA valid and replace the lsb user data with a PAD character. The GEN_K
- -- and GEN_R inputs are ignored if any other input is asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (gen_scp_r(1) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"FB" after DLY; -- K27.7(SCP)
-
- elsif (gen_ecp_r(1) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"FE" after DLY; -- K30.7(ECP)
-
- elsif (gen_suf_r(1) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= fc_nb_r(4 to 7) & "0000" after DLY; -- SUF Data
-
- elsif ((tx_pe_data_v_r(1) and gen_pad_r(1)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"9C" after DLY; -- K28.4(PAD)
-
- elsif ((tx_pe_data_v_r(1) and not gen_pad_r(1)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= tx_pe_data_r(24 to 31) after DLY; -- DATA
-
- elsif (gen_cc_r = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"F7" after DLY; -- K23.7(CC)
-
- elsif ((idle_c(3) and gen_k_r(3)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"BC" after DLY; -- K28.5(K)
-
- elsif ((idle_c(3) and gen_r_r(3)) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"1C" after DLY; -- K28.0(R)
-
- elsif (gen_sp_r = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"4A" after DLY; -- D10.2(SP data)
-
- elsif (gen_spa_r = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"2C" after DLY; -- D12.1(SPA data)
-
- elsif (gen_v_r(3) = '1') then
-
- TX_DATA_Buffer(7 downto 0) <= X"E8" after DLY; -- D8.7(Ver data)
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate control signal for byte3.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- TX_CHAR_IS_K_Buffer(0) <= not ((tx_pe_data_v_r(1) and not gen_pad_r(1)) or
- gen_suf_r(1) or
- gen_sp_r or
- gen_spa_r or
- gen_v_r(3)) or (gen_cc_r) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll.vhd
deleted file mode 100644
index 826f2c5aa85ec7343b24125eec0b754570c1441d..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll.vhd
+++ /dev/null
@@ -1,320 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- TX_LL
---
---
--- Description: The TX_LL module converts user data from the LocalLink interface
--- to Aurora Data, then sends it to the Aurora Channel for transmission.
--- It also handles NFC and UFC messages.
---
--- This module supports 2 4-byte lane designs
---
--- This module supports User Flow Control
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity north_channel_TX_LL is
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
-
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
-
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
-end north_channel_TX_LL;
-
-architecture MAPPED of north_channel_TX_LL is
-
--- External Register Declarations --
-
- signal TX_DST_RDY_N_Buffer : std_logic;
- signal UFC_TX_ACK_N_Buffer : std_logic;
- signal GEN_SCP_Buffer : std_logic;
- signal GEN_ECP_Buffer : std_logic;
- signal GEN_SUF_Buffer : std_logic;
- signal FC_NB_Buffer : std_logic_vector(0 to 3);
-signal TX_PE_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal GEN_PAD_Buffer : std_logic_vector(0 to 1);
-signal TX_PE_DATA_Buffer : std_logic_vector(0 to 31);
-signal GEN_CC_Buffer : std_logic;
-
--- Wire Declarations --
-
- signal halt_c_i : std_logic;
- signal tx_dst_rdy_n_i : std_logic;
-signal ufc_message_i : std_logic_vector(0 to 1);
-
--- Component Declarations --
-
- component north_channel_TX_LL_DATAPATH
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-
- -- Aurora Lane Interface
-
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-
- -- TX_LL Control Module Interface
-
- HALT_C : in std_logic;
- TX_DST_RDY_N : in std_logic;
-UFC_MESSAGE : in std_logic_vector(0 to 1);
-
- -- System Interface
-
- CHANNEL_UP : in std_logic;
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-
- component north_channel_TX_LL_CONTROL
-
- port (
-
- -- LocalLink PDU Interface
-
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-TX_REM : in std_logic_vector(0 to 1);
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
-
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
-
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- TX_LL Control Module Interface
-
- HALT_C : out std_logic;
-UFC_MESSAGE : out std_logic_vector(0 to 1);
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-begin
-
- TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
- UFC_TX_ACK_N <= UFC_TX_ACK_N_Buffer;
- GEN_SCP <= GEN_SCP_Buffer;
- GEN_ECP <= GEN_ECP_Buffer;
- GEN_SUF <= GEN_SUF_Buffer;
- FC_NB <= FC_NB_Buffer;
- TX_PE_DATA_V <= TX_PE_DATA_V_Buffer;
- GEN_PAD <= GEN_PAD_Buffer;
- TX_PE_DATA <= TX_PE_DATA_Buffer;
- GEN_CC <= GEN_CC_Buffer;
-
--- Main Body of Code --
-
- -- TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
- -- external modules to regulate incoming pdu data signals.
-
- TX_DST_RDY_N_Buffer <= tx_dst_rdy_n_i;
-
-
- -- TX_LL_Datapath module
-
- tx_ll_datapath_i : north_channel_TX_LL_DATAPATH
-
- port map (
-
- -- LocalLink PDU Interface
-
- TX_D => TX_D,
- TX_REM => TX_REM,
- TX_SRC_RDY_N => TX_SRC_RDY_N,
- TX_SOF_N => TX_SOF_N,
- TX_EOF_N => TX_EOF_N,
-
- -- Aurora Lane Interface
-
- TX_PE_DATA_V => TX_PE_DATA_V_Buffer,
- GEN_PAD => GEN_PAD_Buffer,
- TX_PE_DATA => TX_PE_DATA_Buffer,
-
- -- TX_LL Control Module Interface
-
- HALT_C => halt_c_i,
- TX_DST_RDY_N => tx_dst_rdy_n_i,
- UFC_MESSAGE => ufc_message_i,
-
- -- System Interface
-
- CHANNEL_UP => CHANNEL_UP,
- USER_CLK => USER_CLK
-
- );
-
-
- -- TX_LL_Control module
-
- tx_ll_control_i : north_channel_TX_LL_CONTROL
-
- port map (
-
- -- LocalLink PDU Interface
-
- TX_SRC_RDY_N => TX_SRC_RDY_N,
- TX_SOF_N => TX_SOF_N,
- TX_EOF_N => TX_EOF_N,
- TX_REM => TX_REM,
- TX_DST_RDY_N => tx_dst_rdy_n_i,
-
- -- UFC Interface
-
- UFC_TX_REQ_N => UFC_TX_REQ_N,
- UFC_TX_MS => UFC_TX_MS,
- UFC_TX_ACK_N => UFC_TX_ACK_N_Buffer,
-
- -- Clock Compensation Interface
-
- WARN_CC => WARN_CC,
- DO_CC => DO_CC,
-
- -- Global Logic Interface
-
- CHANNEL_UP => CHANNEL_UP,
-
- -- TX_LL Control Module Interface
-
- HALT_C => halt_c_i,
- UFC_MESSAGE => ufc_message_i,
-
- -- Aurora Lane Interface
-
- GEN_SCP => GEN_SCP_Buffer,
- GEN_ECP => GEN_ECP_Buffer,
- GEN_SUF => GEN_SUF_Buffer,
- FC_NB => FC_NB_Buffer,
- GEN_CC => GEN_CC_Buffer,
-
- -- System Interface
-
- USER_CLK => USER_CLK
-
- );
-
-end MAPPED;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll_control.vhd
deleted file mode 100644
index 3eecbf96185ab1e43fbb5a9ce7917d2852d327c3..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll_control.vhd
+++ /dev/null
@@ -1,761 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- TX_LL_CONTROL
---
---
---
--- Description: This module provides the transmitter state machine
--- control logic to connect the LocalLink interface to
--- the Aurora Channel.
---
--- This module supports 2 4-byte lane designs
---
--- This module supports User Flow Control.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use WORK.AURORA_PKG.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
--- synthesis translate_on
-
-entity north_channel_TX_LL_CONTROL is
-
- port (
-
- -- LocalLink PDU Interface
-
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-TX_REM : in std_logic_vector(0 to 1);
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
-
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
-
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- TX_LL Control Module Interface
-
- HALT_C : out std_logic;
-UFC_MESSAGE : out std_logic_vector(0 to 1);
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
-end north_channel_TX_LL_CONTROL;
-
-architecture RTL of north_channel_TX_LL_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal TX_DST_RDY_N_Buffer : std_logic;
- signal UFC_TX_ACK_N_Buffer : std_logic;
- signal HALT_C_Buffer : std_logic;
-signal UFC_MESSAGE_Buffer : std_logic_vector(0 to 1);
- signal GEN_SCP_Buffer : std_logic;
- signal GEN_ECP_Buffer : std_logic;
- signal GEN_SUF_Buffer : std_logic;
- signal FC_NB_Buffer : std_logic_vector(0 to 3);
-signal GEN_CC_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal do_cc_r : std_logic;
- signal ufc_idle_r : std_logic;
- signal ufc_header_r : std_logic;
- signal ufc_message1_r : std_logic;
- signal ufc_message2_r : std_logic;
- signal ufc_message3_r : std_logic;
- signal ufc_message4_r : std_logic;
- signal ufc_message5_r : std_logic;
- signal ufc_message6_r : std_logic;
- signal ufc_message7_r : std_logic;
- signal ufc_message8_r : std_logic;
-
- signal ufc_message_count_r : std_logic_vector(0 to 2);
-
- signal suf_delay_1_r : std_logic;
- signal suf_delay_2_r : std_logic;
-
- signal delay_ms_1_r : std_logic_vector(0 to 3);
- signal delay_ms_2_r : std_logic_vector(0 to 3);
-
- signal previous_cycle_ufc_message_r : std_logic;
- signal create_gap_for_scp_r : std_logic;
-
- signal idle_r : std_logic;
- signal sof_to_data_r : std_logic;
- signal data_r : std_logic;
- signal data_to_eof_1_r : std_logic;
- signal data_to_eof_2_r : std_logic;
- signal eof_r : std_logic;
- signal sof_to_eof_1_r : std_logic;
- signal sof_to_eof_2_r : std_logic;
- signal sof_and_eof_r : std_logic;
-
--- Wire Declarations --
-
- signal next_ufc_idle_c : std_logic;
- signal next_ufc_header_c : std_logic;
- signal next_ufc_message1_c : std_logic;
- signal next_ufc_message2_c : std_logic;
- signal next_ufc_message3_c : std_logic;
- signal next_ufc_message4_c : std_logic;
- signal next_ufc_message5_c : std_logic;
- signal next_ufc_message6_c : std_logic;
- signal next_ufc_message7_c : std_logic;
- signal next_ufc_message8_c : std_logic;
- signal ufc_ok_c : std_logic;
- signal create_gap_for_scp_c : std_logic;
-
- signal next_idle_c : std_logic;
- signal next_sof_to_data_c : std_logic;
- signal next_data_c : std_logic;
- signal next_data_to_eof_1_c : std_logic;
- signal next_data_to_eof_2_c : std_logic;
- signal next_eof_c : std_logic;
- signal next_sof_to_eof_1_c : std_logic;
- signal next_sof_to_eof_2_c : std_logic;
- signal next_sof_and_eof_c : std_logic;
-
- signal fc_nb_c : std_logic_vector(0 to 3);
- signal tx_dst_rdy_n_c : std_logic;
- signal do_sof_c : std_logic;
- signal do_eof_c : std_logic;
- signal channel_full_c : std_logic;
- signal pdu_ok_c : std_logic;
-
--- Declarations to handle VHDL limitations
- signal reset_i : std_logic;
-
--- Component Declarations --
-
- component FDR
-
- generic (INIT : bit := '0');
-
- port (
-
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic;
- R : in std_ulogic
-
- );
-
- end component;
-
-begin
-
- TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
- UFC_TX_ACK_N <= UFC_TX_ACK_N_Buffer;
- HALT_C <= HALT_C_Buffer;
- UFC_MESSAGE <= UFC_MESSAGE_Buffer;
- GEN_SCP <= GEN_SCP_Buffer;
- GEN_ECP <= GEN_ECP_Buffer;
- GEN_SUF <= GEN_SUF_Buffer;
- FC_NB <= FC_NB_Buffer;
- GEN_CC <= GEN_CC_Buffer;
-
--- Main Body of Code --
-
-
-
- reset_i <= not CHANNEL_UP;
-
-
- -- Clock Compensation --
-
- -- Register the DO_CC and WARN_CC signals for internal use. Note that the raw DO_CC
- -- signal is used for some logic so the DO_CC signal should be driven directly
- -- from a register whenever possible.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
- do_cc_r <= DO_CC after DLY;
- end if;
-
- end process;
-
-
-
- -- UFC State Machine --
-
- -- The UFC state machine has 10 states: waiting for a UFC request, sending
- -- a UFC header, and 8 states for sending up to 8 words of a UFC message.
- -- It can take over the channel at any time except when there is an NFC
- -- message or a CC sequence being sent.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- ufc_idle_r <= '1' after DLY;
- ufc_header_r <= '0' after DLY;
- ufc_message1_r <= '0' after DLY;
- ufc_message2_r <= '0' after DLY;
- ufc_message3_r <= '0' after DLY;
- ufc_message4_r <= '0' after DLY;
- ufc_message5_r <= '0' after DLY;
- ufc_message6_r <= '0' after DLY;
- ufc_message7_r <= '0' after DLY;
- ufc_message8_r <= '0' after DLY;
-
- else
-
- ufc_idle_r <= next_ufc_idle_c after DLY;
- ufc_header_r <= next_ufc_header_c after DLY;
- ufc_message1_r <= next_ufc_message1_c after DLY;
- ufc_message2_r <= next_ufc_message2_c after DLY;
- ufc_message3_r <= next_ufc_message3_c after DLY;
- ufc_message4_r <= next_ufc_message4_c after DLY;
- ufc_message5_r <= next_ufc_message5_c after DLY;
- ufc_message6_r <= next_ufc_message6_c after DLY;
- ufc_message7_r <= next_ufc_message7_c after DLY;
- ufc_message8_r <= next_ufc_message8_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Capture the message count so it can be used to determine the appropriate
- -- next state.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (next_ufc_header_c = '1') then
-
- ufc_message_count_r <= UFC_TX_MS(0 to 2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
-
- next_ufc_idle_c <= ((UFC_TX_REQ_N or not ufc_ok_c) and
- ((ufc_idle_r) or
- (ufc_message1_r) or
- (ufc_message2_r and std_bool(ufc_message_count_r = "001")) or
- (ufc_message3_r) or
- (ufc_message4_r and std_bool(ufc_message_count_r = "011")) or
- (ufc_message5_r) or
- (ufc_message6_r and std_bool(ufc_message_count_r = "101")) or
- (ufc_message7_r) or
- (ufc_message8_r and std_bool(ufc_message_count_r = "111"))));
-
-
- next_ufc_header_c <= ((not UFC_TX_REQ_N and ufc_ok_c) and
- ((ufc_idle_r) or
- (ufc_message1_r) or
- (ufc_message2_r and std_bool(ufc_message_count_r = "001")) or
- (ufc_message3_r) or
- (ufc_message4_r and std_bool(ufc_message_count_r = "011")) or
- (ufc_message5_r) or
- (ufc_message6_r and std_bool(ufc_message_count_r = "101")) or
- (ufc_message7_r) or
- (ufc_message8_r and std_bool(ufc_message_count_r = "111"))));
-
-
- next_ufc_message1_c <= ufc_header_r and std_bool(ufc_message_count_r = "000");
-
- next_ufc_message2_c <= ufc_header_r and std_bool(ufc_message_count_r > "000");
-
- next_ufc_message3_c <= ufc_message2_r and std_bool(ufc_message_count_r = "010");
-
- next_ufc_message4_c <= ufc_message2_r and std_bool(ufc_message_count_r > "010");
-
- next_ufc_message5_c <= ufc_message4_r and std_bool(ufc_message_count_r = "100");
-
- next_ufc_message6_c <= ufc_message4_r and std_bool(ufc_message_count_r > "100");
-
- next_ufc_message7_c <= ufc_message6_r and std_bool(ufc_message_count_r = "110");
-
- next_ufc_message8_c <= ufc_message6_r and std_bool(ufc_message_count_r = "111");
-
- UFC_MESSAGE_Buffer(0) <= not ufc_idle_r and not ufc_header_r;
-
- UFC_MESSAGE_Buffer(1) <= ufc_message2_r or
- ufc_message4_r or
- ufc_message6_r or
- ufc_message8_r;
-
-
- ufc_ok_c <= not DO_CC and not WARN_CC;
-
-
- UFC_TX_ACK_N_Buffer <= not ufc_header_r;
-
-
- -- Delay UFC_TX_MS so it arrives at the lanes at the same time as the
- -- UFC header.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- delay_ms_1_r <= UFC_TX_MS after DLY;
- delay_ms_2_r <= delay_ms_1_r after DLY;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- previous_cycle_ufc_message_r <= not ufc_idle_r and not ufc_header_r after DLY;
-
- end if;
-
- end process;
-
-
- -- PDU State Machine --
-
- -- The PDU state machine handles the encapsulation and transmission of user
- -- PDUs. It can use the channel when there is no CC, NFC message, UFC header,
- -- UFC message or remote NFC request.
-
- -- State Registers
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- idle_r <= '1' after DLY;
- sof_to_data_r <= '0' after DLY;
- data_r <= '0' after DLY;
- data_to_eof_1_r <= '0' after DLY;
- data_to_eof_2_r <= '0' after DLY;
- eof_r <= '0' after DLY;
- sof_to_eof_1_r <= '0' after DLY;
- sof_to_eof_2_r <= '0' after DLY;
- sof_and_eof_r <= '0' after DLY;
-
- else
-
- if (pdu_ok_c = '1') then
-
- idle_r <= next_idle_c after DLY;
- sof_to_data_r <= next_sof_to_data_c after DLY;
- data_r <= next_data_c after DLY;
- data_to_eof_1_r <= next_data_to_eof_1_c after DLY;
- data_to_eof_2_r <= next_data_to_eof_2_c after DLY;
- eof_r <= next_eof_c after DLY;
- sof_to_eof_1_r <= next_sof_to_eof_1_c after DLY;
- sof_to_eof_2_r <= next_sof_to_eof_2_c after DLY;
- sof_and_eof_r <= next_sof_and_eof_c after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Next State Logic
-
- next_idle_c <= (idle_r and not do_sof_c) or
- (data_to_eof_2_r and not do_sof_c) or
- (eof_r and not do_sof_c ) or
- (sof_to_eof_2_r and not do_sof_c) or
- (sof_and_eof_r and not do_sof_c);
-
-
- next_sof_to_data_c <= ((idle_r and do_sof_c) and not do_eof_c) or
- ((data_to_eof_2_r and do_sof_c) and not do_eof_c) or
- ((eof_r and do_sof_c) and not do_eof_c) or
- ((sof_to_eof_2_r and do_sof_c) and not do_eof_c) or
- ((sof_and_eof_r and do_sof_c) and not do_eof_c);
-
-
- next_data_c <= (sof_to_data_r and not do_eof_c) or
- (data_r and not do_eof_c);
-
-
- next_data_to_eof_1_c <= (sof_to_data_r and do_eof_c and channel_full_c) or
- (data_r and do_eof_c and channel_full_c);
-
-
- next_data_to_eof_2_c <= data_to_eof_1_r;
-
-
- next_eof_c <= (sof_to_data_r and do_eof_c and not channel_full_c) or
- (data_r and do_eof_c and not channel_full_c);
-
-
- next_sof_to_eof_1_c <= (idle_r and do_sof_c and do_eof_c and channel_full_c) or
- (data_to_eof_2_r and do_sof_c and do_eof_c and channel_full_c) or
- (eof_r and do_sof_c and do_eof_c and channel_full_c) or
- (sof_to_eof_2_r and do_sof_c and do_eof_c and channel_full_c) or
- (sof_and_eof_r and do_sof_c and do_eof_c and channel_full_c);
-
-
- next_sof_to_eof_2_c <= sof_to_eof_1_r;
-
-
- next_sof_and_eof_c <= (idle_r and do_sof_c and do_eof_c and not channel_full_c) or
- (data_to_eof_2_r and do_sof_c and do_eof_c and not channel_full_c) or
- (eof_r and do_sof_c and do_eof_c and not channel_full_c) or
- (sof_to_eof_2_r and do_sof_c and do_eof_c and not channel_full_c) or
- (sof_and_eof_r and do_sof_c and do_eof_c and not channel_full_c);
-
-
- -- Drive the GEN_SCP signal when in an SOF state with the PDU state machine active.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- GEN_SCP_Buffer <= '0' after DLY;
-
- else
-
- GEN_SCP_Buffer <= (sof_to_data_r or
- sof_to_eof_1_r or
- sof_and_eof_r) and
- pdu_ok_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Drive the GEN_ECP signal when in an EOF state with the PDU state machine active.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- GEN_ECP_Buffer <= '0' after DLY;
-
- else
-
- GEN_ECP_Buffer <= (data_to_eof_2_r or
- eof_r or
- sof_to_eof_2_r or
- sof_and_eof_r) and
- pdu_ok_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- TX_DST_RDY is the critical path in this module. It must be deasserted (high)
- -- whenever an event occurs that prevents the pdu state machine from using the
- -- Aurora channel to transmit PDUs.
-
- tx_dst_rdy_n_c <= (next_data_to_eof_1_c and pdu_ok_c) or
- not next_ufc_idle_c or
- DO_CC or
- create_gap_for_scp_c or
- (next_sof_to_eof_1_c and pdu_ok_c) or
- (sof_to_eof_1_r and not pdu_ok_c) or
- (data_to_eof_1_r and not pdu_ok_c);
-
-
- -- SCP characters can only be added when the first lane position is open. After UFC messages,
- -- data gets deliberately held off for one cycle to create this gap. No gap is added if no
- -- SCP character is needed.
-
- create_gap_for_scp_c <= (not ufc_idle_r and not ufc_header_r) and
- not (data_r or
- sof_to_data_r or
- data_to_eof_1_r or
- sof_to_eof_1_r);
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- create_gap_for_scp_r <= create_gap_for_scp_c after DLY;
-
- end if;
-
- end process;
-
-
- -- The flops for the GEN_CC signal are replicated for timing and instantiated to allow us
- -- to set their value reliably on powerup.
-
- gen_cc_flop_0_i : FDR
-
- port map (
-
- D => do_cc_r,
- C => USER_CLK,
- R => '0',
- -- R => reset_i,
- Q => GEN_CC_Buffer
-
- );
-
-
- -- The UFC header state triggers the generation of SUF characters in the lane. The signal is
- -- delayed to match up with the datapath delay so that SUF always appears on the cycle
- -- before the first data byte.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- suf_delay_1_r <= '0' after DLY;
-
- else
-
- suf_delay_1_r <= ufc_header_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(CHANNEL_UP = '0') then
-
- suf_delay_2_r <= '0' after DLY;
-
- else
-
- suf_delay_2_r <= suf_delay_1_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- GEN_SUF_Buffer <= '0' after DLY;
-
- else
-
- GEN_SUF_Buffer <= suf_delay_2_r after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- FC_NB carries flow control codes to the Lane Logic.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- FC_NB_Buffer <= fc_nb_c after DLY;
-
- end if;
-
- end process;
-
-
- -- Flow control codes come from the UFC_TX_MS input delayed to match the UFC data delay.
-
- fc_nb_c <= delay_ms_2_r;
-
-
- -- The TX_DST_RDY_N signal is registered.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (CHANNEL_UP = '0') then
-
- TX_DST_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- TX_DST_RDY_N_Buffer <= tx_dst_rdy_n_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Helper Logic
-
- -- SOF requests are valid when TX_SRC_RDY_N. TX_DST_RDY_N and TX_SOF_N are asserted
-
- do_sof_c <= not TX_SRC_RDY_N and
- not TX_DST_RDY_N_Buffer and
- not TX_SOF_N;
-
-
- -- EOF requests are valid when TX_SRC_RDY_N, TX_DST_RDY_N and TX_EOF_N are asserted
-
- do_eof_c <= not TX_SRC_RDY_N and
- not TX_DST_RDY_N_Buffer and
- not TX_EOF_N;
-
-
-
- -- Freeze the PDU state machine when CCs must be handled. Note that the PDU state machine
- -- does not freeze for UFCs - instead, logic is provided to allow the two datastreams
- -- to cooperate.
-
- pdu_ok_c <= not do_cc_r;
-
-
- -- Halt the flow of data through the datastream when the PDU state machine is frozen or
- -- when an SCP character has been delayed due to UFC collision.
-
- HALT_C_Buffer <= not pdu_ok_c;
-
-
- -- The aurora channel is 'full' if there is more than enough data to fit into
- -- a channel that is already carrying an SCP and an ECP character.
-
- channel_full_c <= '1';
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll_datapath.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll_datapath.vhd
deleted file mode 100644
index bc3c3cfeef038a293c41afde352451e41a519ab4..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_tx_ll_datapath.vhd
+++ /dev/null
@@ -1,399 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- TX_LL_DATAPATH
---
---
--- Description: This module pipelines the data path while handling the PAD
--- character placement and valid data flags.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity north_channel_TX_LL_DATAPATH is
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
-
- -- Aurora Lane Interface
-
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-
- -- TX_LL Control Module Interface
-
- HALT_C : in std_logic;
- TX_DST_RDY_N : in std_logic;
-UFC_MESSAGE : in std_logic_vector(0 to 1);
-
- -- System Interface
-
- CHANNEL_UP : in std_logic;
- USER_CLK : in std_logic
-
- );
-
-end north_channel_TX_LL_DATAPATH;
-
-architecture RTL of north_channel_TX_LL_DATAPATH is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
-signal TX_PE_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal GEN_PAD_Buffer : std_logic_vector(0 to 1);
-signal TX_PE_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
-signal in_frame_r : std_logic;
-signal storage_r : std_logic_vector(0 to 15);
-signal storage_v_r : std_logic;
-signal storage_ufc_v_r : std_logic;
-signal storage_pad_r : std_logic;
-signal tx_pe_data_r : std_logic_vector(0 to 31);
-signal valid_c : std_logic_vector(0 to 1);
-signal tx_pe_data_v_r : std_logic_vector(0 to 1);
-signal tx_pe_ufc_v_r : std_logic_vector(0 to 1);
-signal gen_pad_c : std_logic_vector(0 to 1);
-signal gen_pad_r : std_logic_vector(0 to 1);
-
--- Internal Wire Declarations --
-
-signal ll_valid_c : std_logic;
-signal in_frame_c : std_logic;
-
-begin
-
- TX_PE_DATA_V <= TX_PE_DATA_V_Buffer;
- GEN_PAD <= GEN_PAD_Buffer;
- TX_PE_DATA <= TX_PE_DATA_Buffer;
-
--- Main Body of Code --
-
-
-
- -- LocalLink input is only valid when TX_SRC_RDY_N and TX_DST_RDY_N are both asserted
- ll_valid_c <= not TX_SRC_RDY_N and not TX_DST_RDY_N;
-
-
- -- Data must only be read if it is within a frame. If a frame will last multiple cycles
- -- we assert in_frame_r as long as the frame is open.
- process(USER_CLK)
- begin
- if(USER_CLK'event and USER_CLK = '1') then
- if(CHANNEL_UP = '0') then
- in_frame_r <= '0' after DLY;
- elsif(ll_valid_c = '1') then
- if( (TX_SOF_N = '0') and (TX_EOF_N = '1') ) then
- in_frame_r <= '1' after DLY;
- elsif( TX_EOF_N = '0') then
- in_frame_r <= '0' after DLY;
- end if;
- end if;
- end if;
- end process;
-
-
- in_frame_c <= ll_valid_c and (in_frame_r or not TX_SOF_N);
-
-
-
-
- -- The last 2 bytes of data from the LocalLink interface must be stored
- -- for the next cycle to make room for the SCP character that must be
- -- placed at the beginning of the lane.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- storage_r <= TX_D(16 to 31) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
-
- -- All of the remaining bytes (except the last two) must be shifted
- -- and registered to be sent to the Channel. The stored bytes go
- -- into the first position.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- tx_pe_data_r <= storage_r & TX_D(0 to 15) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- We generate the valid_c signal based on the REM signal and the EOF signal.
-
- process (TX_EOF_N, TX_REM)
-
- begin
-
- if (TX_EOF_N = '1') then
-
-valid_c <= "11";
-
- else
-
- case TX_REM(0 to 1) is
-
-when "00" => valid_c <= "10";
-when "01" => valid_c <= "10";
-when "10" => valid_c <= "11";
-when "11" => valid_c <= "11";
-when others => valid_c <= "11";
-
- end case;
-
- end if;
-
- end process;
-
-
- -- If the last 2 bytes in the word are valid, they are placed in the storage register and
- -- storage_v_r is asserted to indicate the data is valid. Note that data is only moved to
- -- storage if the PDU datapath is not halted, the data is valid and both TX_SRC_RDY_N
- -- and TX_DST_RDY_N are asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C ='0') then
-
- storage_v_r <= valid_c(1) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The storage_ufc_v_r register is asserted when valid UFC data is placed in the storage register.
- -- Note that UFC data cannot be halted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- storage_ufc_v_r <= UFC_MESSAGE(1) after DLY;
-
- end if;
-
- end process;
-
-
- -- The tx_pe_data_v_r registers track valid data in the TX_PE_DATA register. The data is valid
- -- if it was valid in the previous stage. Since the first 2 bytes come from storage, validity is
- -- determined from the storage_v_r signal. The remaining bytes are valid if their valid signal
- -- is asserted, and both TX_SRC_RDY_N and TX_DST_RDY_N are asserted.
- -- Note that pdu data movement can be frozen by the halt signal.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- tx_pe_data_v_r(0) <= storage_v_r after DLY;
- tx_pe_data_v_r(1) <= valid_c(0) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- The tx_pe_ufc_v_r register tracks valid ufc data in the tx_pe_data_register. The first 2 bytes
- -- come from storage: they are valid if storage_ufc_v_r was asserted. The remaining bytes come from
- -- the TX_D input. They are valid if UFC_MESSAGE was high when they were exampled. Note that UFC data
- -- cannot be halted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- tx_pe_ufc_v_r(0) <= storage_ufc_v_r after DLY;
- tx_pe_ufc_v_r(1) <= UFC_MESSAGE(0) after DLY;
-
- end if;
-
- end process;
-
-
- -- We generate the gen_pad_c signal based on the REM signal and the EOF signal.
-
- process (TX_EOF_N, TX_REM)
-
- begin
-
- if (TX_EOF_N = '1') then
-
-gen_pad_c <= "00";
-
- else
-
- case TX_REM(0 to 1) is
-
-when "00" => gen_pad_c <= "10";
-when "01" => gen_pad_c <= "00";
-when "10" => gen_pad_c <= "01";
-when "11" => gen_pad_c <= "00";
-when others => gen_pad_c <= "00";
-
- end case;
-
- end if;
-
- end process;
-
-
- -- Store a byte with a pad if TX_DST_RDY_N and TX_SRC_RDY_N is asserted.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- storage_pad_r <= gen_pad_c(1) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Register the gen_pad_r signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (HALT_C = '0') then
-
- gen_pad_r(0) <= storage_pad_r after DLY;
- gen_pad_r(1) <= gen_pad_c(0) and in_frame_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Implement the data out register.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- TX_PE_DATA_Buffer <= tx_pe_data_r after DLY;
- TX_PE_DATA_V_Buffer(0) <= (tx_pe_data_v_r(0) and not HALT_C) or tx_pe_ufc_v_r(0) after DLY;
- TX_PE_DATA_V_Buffer(1) <= (tx_pe_data_v_r(1) and not HALT_C) or tx_pe_ufc_v_r(1) after DLY;
- GEN_PAD_Buffer(0) <= (gen_pad_r(0) and not HALT_C) and not tx_pe_ufc_v_r(0) after DLY;
- GEN_PAD_Buffer(1) <= (gen_pad_r(1) and not HALT_C) and not tx_pe_ufc_v_r(1) after DLY;
-
- end if;
-
- end process;
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_barrel_shifter.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_barrel_shifter.vhd
deleted file mode 100644
index f8e3fcff17b5c54d319082923f7e731a6e080772..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_barrel_shifter.vhd
+++ /dev/null
@@ -1,166 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_BARREL_SHIFTER
---
---
---
--- Description: the UFC_BARREL shifter is a barrel shifter that takes UFC
--- message data from the Aurora channel and left aligns it.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_UFC_BARREL_SHIFTER is
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTER_CONTROL : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
-
- -- Mux output
-
- SHIFTED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end north_channel_UFC_BARREL_SHIFTER;
-
-architecture RTL of north_channel_UFC_BARREL_SHIFTER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal SHIFTED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal ufc_select_c : std_logic_vector(0 to 1);
- signal shifted_data_c : std_logic_vector(0 to 31);
-
-begin
-
- SHIFTED_DATA <= SHIFTED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- Muxes for barrel shifting --
-
- -- Mux for lane 0
-
- process (BARREL_SHIFTER_CONTROL, RAW_DATA)
-
- begin
-
- case BARREL_SHIFTER_CONTROL is
-
-when "00" =>
-
- shifted_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "01" =>
-
- shifted_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- shifted_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (BARREL_SHIFTER_CONTROL, RAW_DATA)
-
- begin
-
- case BARREL_SHIFTER_CONTROL is
-
-when "00" =>
-
- shifted_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- shifted_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the output.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- SHIFTED_DATA_Buffer <= shifted_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_barrel_shifter_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_barrel_shifter_control.vhd
deleted file mode 100644
index a90eb9c5d4faa06be1f13d363d1e8abd8392945f..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_barrel_shifter_control.vhd
+++ /dev/null
@@ -1,131 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_BARREL_SHIFTER_CONTROL
---
---
---
--- Description: this module controls the UFC barrel shifter
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_UFC_BARREL_SHIFTER_CONTROL is
-
- port (
-
- UFC_MESSAGE_START : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- BARREL_SHIFTER_CONTROL : out std_logic_vector(0 to 1)
-
- );
-
-end north_channel_UFC_BARREL_SHIFTER_CONTROL;
-
-architecture RTL of north_channel_UFC_BARREL_SHIFTER_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal BARREL_SHIFTER_CONTROL_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal barrel_shifter_control_i : std_logic_vector(0 to 1);
-
-begin
-
- BARREL_SHIFTER_CONTROL <= BARREL_SHIFTER_CONTROL_Buffer;
-
--- Main Body of Code --
-
- -- Control for barrel shifting --
-
- -- Generate a barrel shift control number, which indicates how far to the left all the
- -- lane data should be shifted.
-
- process (UFC_MESSAGE_START)
-
- begin
-
- if (UFC_MESSAGE_START(0) = '1') then
-
- barrel_shifter_control_i <= conv_std_logic_vector(1,2);
-
- else
-
- barrel_shifter_control_i <= (others => '0');
-
- end if;
-
- end process;
-
-
- -- Register the barrel shifter control number
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- BARREL_SHIFTER_CONTROL_Buffer <= barrel_shifter_control_i after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_filter.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_filter.vhd
deleted file mode 100644
index dced66439743223f622ac9bdf38396f2062f3258..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_filter.vhd
+++ /dev/null
@@ -1,757 +0,0 @@
-------------------------------------------------------------------------------
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--------------------------------------------------------------------------------
---
--- UFC_FILTER
---
---
---
--- Description: The UFC module separates data into UFC data and regular data.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_UFC_FILTER is
-
- port (
-
- -- Aurora Channel Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- PDU Datapath Interface
-
-PDU_DATA : out std_logic_vector(0 to 31);
-PDU_DATA_V : out std_logic_vector(0 to 1);
-PDU_PAD : out std_logic_vector(0 to 1);
-PDU_SCP : out std_logic_vector(0 to 1);
-PDU_ECP : out std_logic_vector(0 to 1);
-
- -- UFC Datapath Interface
-
-UFC_DATA : out std_logic_vector(0 to 31);
-UFC_DATA_V : out std_logic_vector(0 to 1);
-UFC_MESSAGE_START : out std_logic_vector(0 to 1);
- UFC_START : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_UFC_FILTER;
-
-architecture RTL of north_channel_UFC_FILTER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
-signal PDU_DATA_Buffer : std_logic_vector(0 to 31);
-signal PDU_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal PDU_PAD_Buffer : std_logic_vector(0 to 1);
-signal PDU_SCP_Buffer : std_logic_vector(0 to 1);
-signal PDU_ECP_Buffer : std_logic_vector(0 to 1);
-signal UFC_DATA_Buffer : std_logic_vector(0 to 31);
-signal UFC_DATA_V_Buffer : std_logic_vector(0 to 1);
-signal UFC_MESSAGE_START_Buffer : std_logic_vector(0 to 1);
- signal UFC_START_Buffer : std_logic;
-
--- Internal Register Declarations --
-
- signal stage_1_lane_mask_0_c : std_logic_vector(0 to 1);
- signal stage_1_count_value_0_c : std_logic_vector(0 to 3);
- signal stage_1_lane_mask_1_c : std_logic_vector(0 to 1);
- signal stage_1_count_value_1_c : std_logic_vector(0 to 3);
-signal stage_1_lane_mask_r : std_logic_vector(0 to 1);
- signal stage_1_count_value_r : std_logic_vector(0 to 3);
- signal load_ufc_control_code_r : std_logic;
-signal rx_data_v_r : std_logic_vector(0 to 1);
-signal rx_suf_r : std_logic_vector(0 to 1);
-signal rx_pad_r : std_logic_vector(0 to 1);
-signal rx_pe_data_r : std_logic_vector(0 to 31);
-signal rx_scp_r : std_logic_vector(0 to 1);
-signal rx_ecp_r : std_logic_vector(0 to 1);
- signal stage_2_count_value_r : std_logic_vector(0 to 3);
-signal stage_2_lane_mask_c : std_logic_vector(0 to 1);
- signal stage_2_count_value_c : std_logic_vector(0 to 3);
- signal save_start_r : std_logic;
-
-begin
-
- PDU_DATA <= PDU_DATA_Buffer;
- PDU_DATA_V <= PDU_DATA_V_Buffer;
- PDU_PAD <= PDU_PAD_Buffer;
- PDU_SCP <= PDU_SCP_Buffer;
- PDU_ECP <= PDU_ECP_Buffer;
- UFC_DATA <= UFC_DATA_Buffer;
- UFC_DATA_V <= UFC_DATA_V_Buffer;
- UFC_MESSAGE_START <= UFC_MESSAGE_START_Buffer;
- UFC_START <= UFC_START_Buffer;
-
--- Main Body of Code --
-
- -- Stage 1 --
-
- -- Decode a lane mask value for each lane. The lane mask indicates which lanes in the
- -- current cycle contain UFC data.
-
- -- Lane mask for lane 0.
-
- process (RX_FC_NB(0 to 2))
-
- begin
-
- case RX_FC_NB(0 to 2) is
-
- when "000" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "001" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "010" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "011" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "100" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "101" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "110" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when "111" =>
-
-stage_1_lane_mask_0_c <= conv_std_logic_vector(1,2);
-
- when others =>
-
- stage_1_lane_mask_0_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Lane mask for lane 1.
-
- process (RX_FC_NB(4 to 6))
-
- begin
-
- case RX_FC_NB(4 to 6) is
-
- when "000" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "001" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "010" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "011" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "100" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "101" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "110" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when "111" =>
-
-stage_1_lane_mask_1_c <= conv_std_logic_vector(0,2);
-
- when others =>
-
- stage_1_lane_mask_1_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Decode a count value for each lane. The count value indicates the number of lanes in
- -- the cycles that will follow will contain UFC data, based on the current FC_NB value
- -- and its lane position.
-
- -- Count value for lane 0.
-
- process (RX_FC_NB(0 to 2))
-
- begin
-
- case RX_FC_NB(0 to 2) is
-
- when "000" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(0,4);
-
- when "001" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(1,4);
-
- when "010" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(2,4);
-
- when "011" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(3,4);
-
- when "100" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(4,4);
-
- when "101" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(5,4);
-
- when "110" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(6,4);
-
- when "111" =>
-
-stage_1_count_value_0_c <= conv_std_logic_vector(7,4);
-
- when others =>
-
- stage_1_count_value_0_c <= "0000";
-
- end case;
-
- end process;
-
-
- -- Count value for lane 1.
-
- process (RX_FC_NB(4 to 6))
-
- begin
-
- case RX_FC_NB(4 to 6) is
-
- when "000" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(1,4);
-
- when "001" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(2,4);
-
- when "010" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(3,4);
-
- when "011" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(4,4);
-
- when "100" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(5,4);
-
- when "101" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(6,4);
-
- when "110" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(7,4);
-
- when "111" =>
-
-stage_1_count_value_1_c <= conv_std_logic_vector(8,4);
-
- when others =>
-
- stage_1_count_value_1_c <= "0000";
-
- end case;
-
- end process;
-
-
- -- Select and store the lane mask from the lane that contained the UFC message header.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_1_lane_mask_r <= (others => '0') after DLY;
-
- else
-
- if (RX_SUF(0) = '1') then
-
- stage_1_lane_mask_r <= stage_1_lane_mask_0_c after DLY;
-
- elsif (RX_SUF(1) = '1') then
-
- stage_1_lane_mask_r <= stage_1_lane_mask_1_c after DLY;
-
- else
-
- stage_1_lane_mask_r <= (others => '0') after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Select and store the count value from the lane that contained the UFC message header.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_1_count_value_r <= "0000" after DLY;
-
- else
-
- if (RX_SUF(1) = '1') then
-
- stage_1_count_value_r <= stage_1_count_value_1_c after DLY;
-
- elsif (RX_SUF(0) = '1') then
-
- stage_1_count_value_r <= stage_1_count_value_0_c after DLY;
-
- else
-
- stage_1_count_value_r <= "0000" after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Register a load flag if any of the SUF flags are high.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- load_ufc_control_code_r <= '0' after DLY;
-
- else
-
-if (RX_SUF /= "00") then
-
- load_ufc_control_code_r <= '1' after DLY;
-
- else
-
- load_ufc_control_code_r <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the data valid signal and the RX_SUF signal: they need reset.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- rx_data_v_r <= (others => '0') after DLY;
- rx_suf_r <= (others => '0') after DLY;
-
- else
-
- rx_data_v_r <= RX_PE_DATA_V after DLY;
- rx_suf_r <= RX_SUF after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the remaining signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- rx_pad_r <= RX_PAD after DLY;
- rx_pe_data_r <= RX_PE_DATA after DLY;
- rx_scp_r <= RX_SCP after DLY;
- rx_ecp_r <= RX_ECP after DLY;
-
- end if;
-
- end process;
-
-
- -- Stage 2 --
-
- -- If a new message was started in the previous cycle, load the new message size value into a
- -- counter. Otherwise, continue to process the previous count.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- stage_2_count_value_r <= "0000" after DLY;
-
- else
-
- if (load_ufc_control_code_r = '1') then
-
- stage_2_count_value_r <= stage_1_count_value_r after DLY;
-
- else
-
- stage_2_count_value_r <= stage_2_count_value_c after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate a lane mask based on previous count.
-
- process (stage_2_count_value_r)
-
- begin
-
- case stage_2_count_value_r is
-
- when "0001" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(2,2);
-
- when "0010" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0011" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0100" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0101" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0110" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "0111" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when "1000" =>
-
-stage_2_lane_mask_c <= conv_std_logic_vector(3,2);
-
- when others =>
-
- stage_2_lane_mask_c <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Generate a new lane count based on previous count.
-
- process (stage_2_count_value_r)
-
- begin
-
- case stage_2_count_value_r is
-
- when "0001" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(0,4);
-
- when "0010" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(0,4);
-
- when "0011" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(1,4);
-
- when "0100" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(2,4);
-
- when "0101" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(3,4);
-
- when "0110" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(4,4);
-
- when "0111" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(5,4);
-
- when "1000" =>
-
-stage_2_count_value_c <= conv_std_logic_vector(6,4);
-
- when others =>
-
- stage_2_count_value_c <= "0000";
-
- end case;
-
- end process;
-
-
- -- For each lane, mask the valid bit based on the incoming valid signal and the stage 1 and stage 2 lane masks.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- PDU_DATA_V_Buffer <= (others => '0') after DLY;
-
- else
-
- PDU_DATA_V_Buffer <= rx_data_v_r and (not stage_1_lane_mask_r and not stage_2_lane_mask_c) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- For each lane, the lane mask serves as a data valid signal for the UFC data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_DATA_V_Buffer <= (others => '0') after DLY;
-
- else
-
- UFC_DATA_V_Buffer <= stage_1_lane_mask_r or stage_2_lane_mask_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Save start signals from ufc headers that appeared at the end of previous cycles.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- save_start_r <= '0' after DLY;
-
- else
-
- save_start_r <= rx_suf_r(1) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Generate the UFC_MESSAGE_START and the UFC_START signals
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_MESSAGE_START_Buffer <= (others => '0') after DLY;
- UFC_START_Buffer <= '0' after DLY;
-
- else
-
- UFC_MESSAGE_START_Buffer <= rx_suf_r after DLY;
-
-if (rx_suf_r(0 to 0) & save_start_r /= "00") then
-
- UFC_START_Buffer <= '1' after DLY;
-
- else
-
- UFC_START_Buffer <= '0' after DLY;
-
- end if;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Pipeline the remaining signals.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- PDU_PAD_Buffer <= rx_pad_r after DLY;
- PDU_DATA_Buffer <= rx_pe_data_r after DLY;
- UFC_DATA_Buffer <= rx_pe_data_r after DLY;
- PDU_SCP_Buffer <= rx_scp_r after DLY;
- PDU_ECP_Buffer <= rx_ecp_r after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_output_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_output_mux.vhd
deleted file mode 100644
index 7500eb79bf2ed4f6d4591530bd3a75158dee62aa..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_output_mux.vhd
+++ /dev/null
@@ -1,150 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_OUTPUT_MUX
---
---
---
--- Description: the UFC_OUTPUT mux moves selected data from ufc storage and the
--- ufc barrel shifter to the ufc LocalLink output register. It
--- is made up of a series of muxes, one set for each lane. The
--- number of selections available for each mux increments with
--- lane position. The first lane has only one possible input, the
--- nth lane has N inputs.
--- Note that the 0th selection for each mux is connected to the
--- UFC storage input, and the remaining selections are connected
--- to the barrel-shifted input lanes in incrementing order.
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_UFC_OUTPUT_MUX is
-
- port (
-
- -- Input interface to the muxes
-
- UFC_STORAGE_DATA : in std_logic_vector(0 to 31);
- BARREL_SHIFTED_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end north_channel_UFC_OUTPUT_MUX;
-
-architecture RTL of north_channel_UFC_OUTPUT_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal MUXED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal muxed_data_c : std_logic_vector(0 to 31);
-
-begin
-
- MUXED_DATA <= MUXED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create a set of muxes for each lane.
-
- -- Lane 0 needs no mux, it is always connected to the storage lane.
-
- -- Mux for lane 1
-
- process (MUX_SELECT(3 to 5), UFC_STORAGE_DATA, BARREL_SHIFTED_DATA)
-
- begin
-
- case MUX_SELECT(3 to 5) is
-
-when "000" =>
-
- muxed_data_c(16 to 31) <= UFC_STORAGE_DATA(16 to 31);
-
-when "001" =>
-
- muxed_data_c(16 to 31) <= BARREL_SHIFTED_DATA(0 to 15);
-
- when others =>
-
- muxed_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the data.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- MUXED_DATA_Buffer <= UFC_STORAGE_DATA(0 to 15) & muxed_data_c(16 to 31) after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_output_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_output_switch_control.vhd
deleted file mode 100644
index 2a3ab576a14330c04ed1bc57ed02ecc9c6735567..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_output_switch_control.vhd
+++ /dev/null
@@ -1,159 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_OUTPUT_SWITCH_CONTROL
---
---
---
--- Description: UFC_OUTPUT_SWITCH_CONTROL selects the input chunk for each ufc output mux
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_UFC_OUTPUT_SWITCH_CONTROL is
-
- port (
-
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- UFC_OUTPUT_SELECT : out std_logic_vector(0 to 5)
-
- );
-
-end north_channel_UFC_OUTPUT_SWITCH_CONTROL;
-
-architecture RTL of north_channel_UFC_OUTPUT_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal UFC_OUTPUT_SELECT_Buffer : std_logic_vector(0 to 5);
-
--- Internal Register Declarations --
-
- signal ufc_output_select_c : std_logic_vector(0 to 5);
-
--- Wire Declarations --
-
- signal overflow_c : std_logic;
- signal sum_c : std_logic_vector(0 to 7);
-
-begin
-
- UFC_OUTPUT_SELECT <= UFC_OUTPUT_SELECT_Buffer;
-
--- Main Body of Code --
-
- -- Generate switch signals --
-
- -- Select for Lane 0
-
- sum_c(0 to 3) <= conv_std_logic_vector(1,4) - UFC_STORAGE_COUNT;
-
- process (sum_c)
-
- begin
-
- if (sum_c(0) = '1') then
-
- ufc_output_select_c(0 to 2) <= (others => '0');
-
- else
-
- ufc_output_select_c(0 to 2) <= sum_c(1 to 3);
-
- end if;
-
- end process;
-
-
- -- Select for Lane 1
-
- sum_c(4 to 7) <= conv_std_logic_vector(2,4) - UFC_STORAGE_COUNT;
-
- process (sum_c)
-
- begin
-
- if (sum_c(4) = '1') then
-
- ufc_output_select_c(3 to 5) <= (others => '0');
-
- else
-
- ufc_output_select_c(3 to 5) <= sum_c(5 to 7);
-
- end if;
-
- end process;
-
-
- -- Register the output
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_OUTPUT_SELECT_Buffer <= ufc_output_select_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_sideband_output.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_sideband_output.vhd
deleted file mode 100644
index ac2f6abf7ac3e96f5efd5184226eb6ae16d0596c..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_sideband_output.vhd
+++ /dev/null
@@ -1,230 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_SIDEBAND_OUTPUT
---
---
---
--- Description: UFC_SIDEBAND_OUTPUT generates the UFC_SRC_RDY_N, UFC_EOF_N,
--- UFC_SOF_N and UFC_REM signals for the RX localLink interface.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_UFC_SIDEBAND_OUTPUT is
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- UFC_SRC_RDY_N : out std_logic;
- UFC_SOF_N : out std_logic;
- UFC_EOF_N : out std_logic;
- UFC_REM : out std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic
-
- );
-
-end north_channel_UFC_SIDEBAND_OUTPUT;
-
-architecture RTL of north_channel_UFC_SIDEBAND_OUTPUT is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal UFC_SRC_RDY_N_Buffer : std_logic;
- signal UFC_SOF_N_Buffer : std_logic;
- signal UFC_EOF_N_Buffer : std_logic;
- signal UFC_REM_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal ufc_sof_early_r : std_logic;
-
--- Wire Declarations --
-
- signal sum_c : std_logic_vector(0 to 2);
- signal storage_count_2x_c : std_logic_vector(0 to 2);
- signal sum_2x_c : std_logic_vector(0 to 2);
- signal back_to_back_rem_c : std_logic_vector(0 to 2);
- signal non_back_to_back_rem_c : std_logic_vector(0 to 2);
- signal storage_empty_c : std_logic;
- signal message_finished_c : std_logic;
- signal back_to_back_ufc_c : std_logic;
-
-begin
-
- UFC_SRC_RDY_N <= UFC_SRC_RDY_N_Buffer;
- UFC_SOF_N <= UFC_SOF_N_Buffer;
- UFC_EOF_N <= UFC_EOF_N_Buffer;
- UFC_REM <= UFC_REM_Buffer;
-
--- Main Body of Code --
-
- -- Calculate the output --
-
- -- Assert ufc_src_rdy_n whenever data is moved to the output.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- UFC_SRC_RDY_N_Buffer <= '1' after DLY;
-
- else
-
- UFC_SRC_RDY_N_Buffer <= not std_bool(UFC_STORAGE_COUNT > conv_std_logic_vector(0,2)) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- -- Assert ufc_sof one cycle after a new frame is delivered to storage.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- ufc_sof_early_r <= UFC_START after DLY;
-
- UFC_SOF_N_Buffer <= not ufc_sof_early_r after DLY;
-
- end if;
-
- end process;
-
-
- sum_c <= conv_std_logic_vector(0,3) + UFC_STORAGE_COUNT + BARREL_SHIFTED_COUNT;
-
-
- -- Detect empty storage.
-
- storage_empty_c <= std_bool(not (UFC_STORAGE_COUNT > conv_std_logic_vector(0,2)));
-
-
- -- Detect back to back ufc messages.
-
- back_to_back_ufc_c <= not storage_empty_c and UFC_START;
-
-
- -- Detect messages that are finishing.
-
- message_finished_c <= not storage_empty_c and (std_bool(sum_c <= conv_std_logic_vector(2,3)) or UFC_START);
-
-
- -- Assert eof_n when the storage will empty or a new frame arrives.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_EOF_N_Buffer <= not message_finished_c after DLY;
-
- end if;
-
- end process;
-
-
- -- REM calculations
-
- storage_count_2x_c <= UFC_STORAGE_COUNT & '0';
-
- sum_2x_c <= sum_c(1 to 2) & '0';
-
- back_to_back_rem_c <= storage_count_2x_c - conv_std_logic_vector(1,3);
-
- non_back_to_back_rem_c <= sum_2x_c - conv_std_logic_vector(1,3);
-
-
- -- Rem depends on the number of valid bytes being transferred to output
- -- on the eof cycle.
-
- process(USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (back_to_back_ufc_c = '1') then
-
- UFC_REM_Buffer <= back_to_back_rem_c(1 to 2) after DLY;
-
- else
-
- UFC_REM_Buffer <= non_back_to_back_rem_c(1 to 2) after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_count_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_count_control.vhd
deleted file mode 100644
index b25de7e1848069eff4cf12dc8fa30826d5811cca..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_count_control.vhd
+++ /dev/null
@@ -1,156 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_STORAGE_COUNT_CONTROL
---
---
---
--- Description: UFC_STORAGE_COUNT_CONTROL sets the ufc storage count value for the next clock
--- cycle
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_UFC_STORAGE_COUNT_CONTROL is
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic;
- UFC_STORAGE_COUNT : out std_logic_vector(0 to 1)
-
- );
-
-end north_channel_UFC_STORAGE_COUNT_CONTROL;
-
-architecture RTL of north_channel_UFC_STORAGE_COUNT_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal UFC_STORAGE_COUNT_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal storage_count_c : std_logic_vector(0 to 1);
- signal storage_count_r : std_logic_vector(0 to 1);
-
--- Wire Declarations --
-
- signal sum_c : std_logic_vector(0 to 2);
- signal reduced_sum_c : std_logic_vector(0 to 2);
- signal next_storage_count_c : std_logic_vector(0 to 1);
-
-begin
-
- UFC_STORAGE_COUNT <= UFC_STORAGE_COUNT_Buffer;
-
--- Main Body of Code --
-
- -- Calculate the value that will be used for the switch.
-
- sum_c <= conv_std_logic_vector(0,3) + BARREL_SHIFTED_COUNT + storage_count_r;
- reduced_sum_c <= sum_c - conv_std_logic_vector(2,3);
-
- next_storage_count_c <= reduced_sum_c(1 to 2) when (sum_c > conv_std_logic_vector(2,3)) else (others =>'0');
-
-
- process (UFC_START, next_storage_count_c, BARREL_SHIFTED_COUNT)
-
- begin
-
- if (UFC_START = '1') then
-
- storage_count_c <= BARREL_SHIFTED_COUNT;
-
- else
-
- storage_count_c <= next_storage_count_c;
-
- end if;
-
- end process;
-
-
- -- Register the storage count and make it available to the outside world.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if(RESET = '1') then
-
- storage_count_r <= (others => '0') after DLY;
-
- else
-
- storage_count_r <= storage_count_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
- UFC_STORAGE_COUNT_Buffer <= storage_count_r;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_mux.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_mux.vhd
deleted file mode 100644
index b8f6516639fbe43875c9a79e2682e6ef3ed813f4..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_mux.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_STORAGE_MUX
---
---
---
--- Description: the UFC_STORAGE_MUX is a series of N:1 muxes used to determine
--- which input lanes feed which storage register.
---
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-entity north_channel_UFC_STORAGE_MUX is
-
- port (
-
- -- Input interface to the muxes
-
- RAW_DATA : in std_logic_vector(0 to 31);
- MUX_SELECT : in std_logic_vector(0 to 5);
- USER_CLK : in std_logic;
-
- -- Mux output
-
- MUXED_DATA : out std_logic_vector(0 to 31)
-
- );
-
-end north_channel_UFC_STORAGE_MUX;
-
-architecture RTL of north_channel_UFC_STORAGE_MUX is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal MUXED_DATA_Buffer : std_logic_vector(0 to 31);
-
--- Internal Register Declarations --
-
- signal muxed_data_c : std_logic_vector(0 to 31);
-
-begin
-
- MUXED_DATA <= MUXED_DATA_Buffer;
-
--- Main Body of Code --
-
- -- We create muxes for each lane
-
- -- Mux for lane 0
-
- process (MUX_SELECT(0 to 2), RAW_DATA)
-
- begin
-
- case MUX_SELECT(0 to 2) is
-
-when "000" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(0 to 15);
-
-when "001" =>
-
- muxed_data_c(0 to 15) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(0 to 15) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Mux for lane 1
-
- process (MUX_SELECT(3 to 5), RAW_DATA)
-
- begin
-
- case MUX_SELECT(3 to 5) is
-
-when "000" =>
-
- muxed_data_c(16 to 31) <= RAW_DATA(0 to 15);
-
-when "001" =>
-
- muxed_data_c(16 to 31) <= RAW_DATA(16 to 31);
-
- when others =>
-
- muxed_data_c(16 to 31) <= (others => '0');
-
- end case;
-
- end process;
-
-
- -- Register the data
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK'event and USER_CLK = '1') then
-
- MUXED_DATA_Buffer <= muxed_data_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
-
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_switch_control.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_switch_control.vhd
deleted file mode 100644
index ecc352de4c25ee76b5fefb75acfcd8074125b02c..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_ufc_storage_switch_control.vhd
+++ /dev/null
@@ -1,167 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- UFC_STORAGE_SWITCH_CONTROL
---
---
---
--- Description: UFC_STORAGE_SWITCH_CONTROL selects the input chunk for each ufc storage chunk mux
---
--- This module supports 2 4-byte lane designs
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use WORK.AURORA_PKG.all;
-
-entity north_channel_UFC_STORAGE_SWITCH_CONTROL is
-
- port (
-
- BARREL_SHIFTED_COUNT : in std_logic_vector(0 to 1);
- UFC_STORAGE_COUNT : in std_logic_vector(0 to 1);
- UFC_START : in std_logic;
- USER_CLK : in std_logic;
- UFC_STORAGE_SELECT : out std_logic_vector(0 to 5)
-
- );
-
-end north_channel_UFC_STORAGE_SWITCH_CONTROL;
-
-architecture RTL of north_channel_UFC_STORAGE_SWITCH_CONTROL is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations
-
- signal UFC_STORAGE_SELECT_Buffer : std_logic_vector(0 to 5);
-
--- Internal Register Declarations --
-
- signal ufc_storage_select_c : std_logic_vector(0 to 5);
-
--- Wire Declarations --
-
- signal sum_c : std_logic_vector(0 to 3);
- signal overflow_c : std_logic;
- signal overflow_value_c : std_logic_vector(0 to 7);
-
-begin
-
- UFC_STORAGE_SELECT <= UFC_STORAGE_SELECT_Buffer;
-
--- Main Body of Code --
-
- sum_c <= "0000" + BARREL_SHIFTED_COUNT + UFC_STORAGE_COUNT;
- overflow_c <= std_bool(sum_c > conv_std_logic_vector(2,3)) and not UFC_START;
-
-
- -- Generate switch signals --
-
- -- Select for Lane 0
-
- overflow_value_c(0 to 3) <= conv_std_logic_vector(2,4) - UFC_STORAGE_COUNT;
-
- process (overflow_c, overflow_value_c)
-
- begin
-
- if (overflow_c = '1') then
-
- ufc_storage_select_c(0 to 2) <= overflow_value_c(1 to 3);
-
- else
-
- ufc_storage_select_c(0 to 2) <= conv_std_logic_vector(0,3);
-
- end if;
-
- end process;
-
-
- -- Select for Lane 1
-
- overflow_value_c(4 to 7) <= conv_std_logic_vector(3,4) - UFC_STORAGE_COUNT;
-
- process (overflow_c, overflow_value_c)
-
- begin
-
- if (overflow_c = '1') then
-
- ufc_storage_select_c(3 to 5) <= overflow_value_c(5 to 7);
-
- else
-
- ufc_storage_select_c(3 to 5) <= conv_std_logic_vector(1,3);
-
- end if;
-
- end process;
-
-
- -- Register the storage selection.
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- UFC_STORAGE_SELECT_Buffer <= ufc_storage_select_c after DLY;
-
- end if;
-
- end process;
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_valid_data_counter.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_valid_data_counter.vhd
deleted file mode 100644
index f4f1127fd09c725595d40f66bebcc117dead8066..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/src/north_channel_valid_data_counter.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
--- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
-
---
--- VALID_DATA_COUNTER
---
---
---
--- Description: The VALID_DATA_COUNTER module counts the number of ones in a register filled
--- with ones and zeros.
---
--- This module supports 2 4-byte lane designs.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity north_channel_VALID_DATA_COUNTER is
-
- port (
-
- PREVIOUS_STAGE_VALID : in std_logic_vector(0 to 1);
- USER_CLK : in std_logic;
- RESET : in std_logic;
- COUNT : out std_logic_vector(0 to 1)
-
- );
-
-end north_channel_VALID_DATA_COUNTER;
-
-architecture RTL of north_channel_VALID_DATA_COUNTER is
-
--- Parameter Declarations --
-
- constant DLY : time := 1 ns;
-
--- External Register Declarations --
-
- signal COUNT_Buffer : std_logic_vector(0 to 1);
-
--- Internal Register Declarations --
-
- signal count_c : std_logic_vector(0 to 1);
-
-begin
-
- COUNT <= COUNT_Buffer;
-
--- Main Body of Code --
-
- -- Return the number of 1's in the binary representation of the input value.
-
- process (PREVIOUS_STAGE_VALID)
-
- begin
-
- count_c <= (
-
- conv_std_logic_vector(0,2)
- + PREVIOUS_STAGE_VALID(0)
- + PREVIOUS_STAGE_VALID(1)
-
- );
-
- end process;
-
-
- --Register the count
-
- process (USER_CLK)
-
- begin
-
- if (USER_CLK 'event and USER_CLK = '1') then
-
- if (RESET = '1') then
-
- COUNT_Buffer <= (others => '0') after DLY;
-
- else
-
- COUNT_Buffer <= count_c after DLY;
-
- end if;
-
- end if;
-
- end process;
-
-
-end RTL;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_clocks.xdc b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_clocks.xdc
deleted file mode 100644
index 506366b85030f86066672fbf0b54d503752eca6b..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_clocks.xdc
+++ /dev/null
@@ -1,76 +0,0 @@
-
-################################################################################
-##
-## (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-## north_channel.xdc generated for xc7z015-clg485-2 device
-#
-#
-#
-## TXOUTCLK Constraint: Value is selected based on the line rate (5.0 Gbps) and lane width (4-Byte)
-#
-#create_clock -period 4.0 [get_pins -hier -filter {name=~*gt_wrapper_i*north_channel_multi_gt_i*gt0_north_channel_i*gtpe2_i*TXOUTCLK}]
-#
-#
-#
-#
-#
-
-##### CDC Path #####
-#set_false_path -to [get_pins -hier *north_channel_cdc_to*/D]
-#
-#
-#
-####################### GT reference clock LOC (For use in top level design) #######################
-# set_property LOC V5 [get_ports GTPQ0_N]
-# set_property LOC U5 [get_ports GTPQ0_P]
-
-############################### GT LOC (For use in top level design) ###################################
-# set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells aurora_module_i/north_channel_i/U0/gt_wrapper_i/north_channel_multi_gt_i/gt0_north_channel_i/gtpe2_i]
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_core.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_core.vhd
deleted file mode 100644
index b71c9918eaea4c81b3cda8e3605b96f12f3988d7..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_core.vhd
+++ /dev/null
@@ -1,1368 +0,0 @@
----------------------------------------------------------------------------------------------
--- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---
---------------------------------------------------------------------------------------------
---
--- north_channel
---
---
--- Description: This is the top level module for a 1 4-byte lane Aurora
--- reference design module. This module supports the following features:
---
--- * User Flow Control
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_MISC.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
--- synthesis translate_off
-library UNISIM;
-use UNISIM.all;
---synthesis translate_on
-
-entity north_channel_core is
- generic (
-
- SIM_GTRESET_SPEEDUP : string := "FALSE";
- CC_FREQ_FACTOR : integer := 12;
- EXAMPLE_SIMULATION : integer := 0
- );
- port (
-
- -- TX Stream Interface
-
-S_AXI_TX_TDATA : in std_logic_vector(0 to 31);
-S_AXI_TX_TKEEP : in std_logic_vector(0 to 3);
-
- S_AXI_TX_TVALID : in std_logic;
- S_AXI_TX_TREADY : out std_logic;
- S_AXI_TX_TLAST : in std_logic;
-
- -- RX Stream Interface
-
-M_AXI_RX_TDATA : out std_logic_vector(0 to 31);
-M_AXI_RX_TKEEP : out std_logic_vector(0 to 3);
-
- M_AXI_RX_TVALID : out std_logic;
- M_AXI_RX_TLAST : out std_logic;
-
- -- User Flow Control TX Interface
-
- S_AXI_UFC_TX_REQ : in std_logic;
- S_AXI_UFC_TX_MS : in std_logic_vector(0 to 2);
- S_AXI_UFC_TX_ACK : out std_logic;
-
- -- User Flow Control RX Inteface
-
-M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31);
-M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_UFC_RX_TVALID : out std_logic;
- M_AXI_UFC_RX_TLAST : out std_logic;
- -- GTX Serial I/O
-
-RXP : in std_logic;
-RXN : in std_logic;
-TXP : out std_logic;
-TXN : out std_logic;
-
- --GTX Reference Clock Interface
-
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
-
- HARD_ERR : out std_logic;
- SOFT_ERR : out std_logic;
- FRAME_ERR : out std_logic;
-
-
- -- Status
-
- CHANNEL_UP : out std_logic;
-LANE_UP : out std_logic;
-
- -- System Interface
-
- user_clk : in std_logic;
- sync_clk : in std_logic;
- RESET : in std_logic;
- POWER_DOWN : in std_logic;
- LOOPBACK : in std_logic_vector(2 downto 0);
- GT_RESET : in std_logic;
- init_clk_in : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- TX_RESETDONE_OUT : out std_logic;
- RX_RESETDONE_OUT : out std_logic;
- LINK_RESET_OUT : out std_logic;
-drpclk_in : in std_logic;
-DRPADDR_IN : in std_logic_vector(8 downto 0);
-DRPDI_IN : in std_logic_vector(15 downto 0);
-DRPDO_OUT : out std_logic_vector(15 downto 0);
-DRPEN_IN : in std_logic;
-DRPRDY_OUT : out std_logic;
-DRPWE_IN : in std_logic;
-
- TX_OUT_CLK : out std_logic;
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
-
- sys_reset_out : out std_logic;
- tx_lock : out std_logic
-
- );
-
-end north_channel_core;
-
-
-architecture MAPPED of north_channel_core is
- attribute core_generation_info : string;
-attribute core_generation_info of MAPPED : architecture is "north_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- -- Parameter Declarations --
- constant DLY : time := 1 ns;
-
--- Component Declarations --
- component north_channel_cdc_sync is
- generic (
- C_CDC_TYPE : integer range 0 to 2 := 1 ;
- -- 0 is pulse synch
- -- 1 is level synch
- -- 2 is ack based level sync
- C_RESET_STATE : integer range 0 to 1 := 0 ;
- -- 0 is reset not needed
- -- 1 is reset needed
- C_SINGLE_BIT : integer range 0 to 1 := 1 ;
- -- 0 is bus input
- -- 1 is single bit input
- C_FLOP_INPUT : integer range 0 to 1 := 0 ;
- C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
- C_MTBF_STAGES : integer range 0 to 6 := 2
- -- Vector Data witdth
- );
-
- port (
- prmry_aclk : in std_logic ; --
- prmry_resetn : in std_logic ; --
- prmry_in : in std_logic ; --
- prmry_vect_in : in std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) ; --
- prmry_ack : out std_logic ;
- --
- scndry_aclk : in std_logic ; --
- scndry_resetn : in std_logic ; --
- --
- -- Primary to Secondary Clock Crossing --
- scndry_out : out std_logic ; --
- --
- scndry_vect_out : out std_logic_vector --
- (C_VECTOR_WIDTH - 1 downto 0) --
-
- );
- end component;
-
- component north_channel_RESET_LOGIC
- port (
- RESET : in std_logic;
- USER_CLK : in std_logic;
- INIT_CLK_IN : in std_logic;
- TX_LOCK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- LINK_RESET_IN : in std_logic;
- TX_RESETDONE_IN : in std_logic;
- RX_RESETDONE_IN : in std_logic;
- SYSTEM_RESET : out std_logic
- );
- end component;
-
-
- -- AXI Shim modules
- component north_channel_LL_TO_AXI is
- generic
- (
- DATA_WIDTH : integer := 16; -- DATA bus width
- USE_UFC_REM : integer := 0; -- UFC REM bus width identifier
- STRB_WIDTH : integer := 2; -- STROBE bus width
- REM_WIDTH : integer := 1 -- REM bus width
- );
-
- port
- (
-
- ---------------------- AXI4-S Interface -------------------------------
- AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_OP_TVALID : out std_logic;
- AXI4_S_OP_TLAST : out std_logic;
- AXI4_S_IP_TREADY : in std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1);
- LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1);
- LL_IP_SRC_RDY_N : in std_logic;
- LL_IP_SOF_N : in std_logic;
- LL_IP_EOF_N : in std_logic;
- LL_OP_DST_RDY_N : out std_logic
-
- );
- end component;
-
- component north_channel_AXI_TO_LL is
- generic
- (
- DATA_WIDTH : integer := 16; -- DATA bus width
- STRB_WIDTH : integer := 2; -- STROBE bus width
- REM_WIDTH : integer := 1; -- REM bus width
- USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC
- USE_UFC_REM : integer := 0 -- UFC REM bus width identifier
- );
-
- port
- (
-
- ---------------------- AXI4-S Interface -------------------------------
- AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1);
- AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1);
- AXI4_S_IP_TX_TVALID : in std_logic;
- AXI4_S_IP_TX_TLAST : in std_logic;
- AXI4_S_OP_TX_TREADY : out std_logic;
-
- ---------------------- LocalLink Interface ----------------------------
- LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1);
- LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1);
- LL_OP_SRC_RDY_N : out std_logic;
- LL_OP_SOF_N : out std_logic;
- LL_OP_EOF_N : out std_logic;
- LL_IP_DST_RDY_N : in std_logic;
-
- ---------------------- System Interface ----------------------------
- USER_CLK : in std_logic;
- RESET : in std_logic;
- CHANNEL_UP : in std_logic
-
- );
- end component;
-
- component FD
-
- generic (
- INIT : bit := '0'
- );
-
- port (
- Q : out std_ulogic;
- C : in std_ulogic;
- D : in std_ulogic
- );
-
- end component;
-
-
- component north_channel_AURORA_LANE_4BYTE
- generic (
- EXAMPLE_SIMULATION : integer := 0
-
- );
- port (
-
- -- GTX Interface
-
- RX_DATA : in std_logic_vector(31 downto 0); -- 4-byte data bus from the GTX.
- RX_NOT_IN_TABLE : in std_logic_vector(3 downto 0); -- Invalid 10-bit code was recieved.
- RX_DISP_ERR : in std_logic_vector(3 downto 0); -- Disparity error detected on RX interface.
- RX_CHAR_IS_K : in std_logic_vector(3 downto 0); -- Indicates which bytes of RX_DATA are control.
- RX_CHAR_IS_COMMA : in std_logic_vector(3 downto 0); -- Comma received on given byte.
- RX_BUF_ERR : in std_logic; -- Overflow/Underflow of RX buffer detected.
- RX_STATUS : in std_logic_vector(5 downto 0); -- Part of GT_11 status and error bus
- TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
- RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
- RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
- RX_RESET : out std_logic; -- Reset RX side of GTX logic.
- TX_CHAR_IS_K : out std_logic_vector(3 downto 0); -- TX_DATA byte is a control character.
- TX_DATA : out std_logic_vector(31 downto 0); -- 4-byte data bus to the GTX.
- TX_RESET : out std_logic; -- Reset TX side of GTX logic.
- LINK_RESET_OUT : out std_logic; -- Link reset for hotplug scenerio.
- HPCNT_RESET : in std_logic; -- Hotplug count reset input.
- INIT_CLK : in std_logic;
-
- -- Comma Detect Phase Align Interface
-
- ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
-
- -- TX_LL Interface
-
- GEN_SCP : in std_logic_vector(0 to 1); -- SCP generation request from TX_LL.
- GEN_ECP : in std_logic_vector(0 to 1); -- ECP generation request from TX_LL.
- GEN_SUF : in std_logic_vector(0 to 1); -- SUF generation request from TX_LL
- GEN_PAD : in std_logic_vector(0 to 1); -- PAD generation request from TX_LL
- FC_NB : in std_logic_vector(0 to 7); -- Size code for SUF and SNF messages
- TX_PE_DATA : in std_logic_vector(0 to 31); -- Data from TX_LL to send over lane.
- TX_PE_DATA_V : in std_logic_vector(0 to 1); -- Indicates TX_PE_DATA is Valid.
- GEN_CC : in std_logic; -- CC generation request from TX_LL.
-
- -- RX_LL Interface
-
- RX_PAD : out std_logic_vector(0 to 1); -- Indicates lane received PAD.
- RX_PE_DATA : out std_logic_vector(0 to 31); -- RX data from lane to RX_LL.
- RX_PE_DATA_V : out std_logic_vector(0 to 1); -- RX_PE_DATA is data, not control symbol.
- RX_SCP : out std_logic_vector(0 to 1); -- Indicates lane received SCP.
- RX_ECP : out std_logic_vector(0 to 1); -- Indicates lane received ECP
- RX_SUF : out std_logic_vector(0 to 1); -- Indicates lane received SUF
- RX_FC_NB : out std_logic_vector(0 to 7); -- Size code for SNF or SUF
-
- -- Global Logic Interface
-
- GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
- GEN_K : in std_logic_vector(0 to 3); -- 'K character' generation request from Global Logic.
- GEN_R : in std_logic_vector(0 to 3); -- 'R character' generation request from Global Logic.
- GEN_V : in std_logic_vector(0 to 3); -- Verification data generation request.
- LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
- SOFT_ERR : out std_logic_vector(0 to 1); -- Soft error detected.
- HARD_ERR : out std_logic; -- Hard error detected.
- CHANNEL_BOND_LOAD : out std_logic; -- Channel Bongding done code recieved.
- GOT_A : out std_logic_vector(0 to 3); -- Indicates lane recieved 'A character' bytes.
- GOT_V : out std_logic; -- Verification symbols received.
- CHANNEL_UP : in std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic; -- System clock for all non-GTX Aurora Logic.
- RESET_SYMGEN : in std_logic; -- Reset the SYM_GEN module.
- RESET : in std_logic -- Reset the lane.
-
- );
-
- end component;
-
-
- component north_channel_GT_WRAPPER
- generic(
- SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
- EXAMPLE_SIMULATION : integer := 0
- );
- port (
-RXFSM_DATA_VALID : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- gt0_txresetdone_out : out std_logic;
- gt0_rxresetdone_out : out std_logic;
- gt0_rxpmaresetdone_out : out std_logic;
- gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
- gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
-
-
- -- DRP I/F
-DRPADDR_IN : in std_logic_vector(8 downto 0);
-DRPCLK_IN : in std_logic;
-DRPDI_IN : in std_logic_vector(15 downto 0);
-DRPDO_OUT : out std_logic_vector(15 downto 0);
-DRPEN_IN : in std_logic;
-DRPRDY_OUT : out std_logic;
-DRPWE_IN : in std_logic;
-
- INIT_CLK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- TX_RESETDONE_OUT : out std_logic;
- RX_RESETDONE_OUT : out std_logic;
-ENCHANSYNC_IN : in std_logic;
-ENMCOMMAALIGN_IN : in std_logic;
-ENPCOMMAALIGN_IN : in std_logic;
- REFCLK : in std_logic;
- LOOPBACK_IN : in std_logic_vector (2 downto 0);
-RXPOLARITY_IN : in std_logic;
-RXRESET_IN : in std_logic;
- RXUSRCLK_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
-RX1N_IN : in std_logic;
-RX1P_IN : in std_logic;
-TXCHARISK_IN : in std_logic_vector (3 downto 0);
-TXDATA_IN : in std_logic_vector (31 downto 0);
- GTRESET_IN : in std_logic;
-TXRESET_IN : in std_logic;
- TXUSRCLK_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
-RXBUFERR_OUT : out std_logic;
-RXCHARISCOMMA_OUT : out std_logic_vector (3 downto 0);
-RXCHARISK_OUT : out std_logic_vector (3 downto 0);
-RXDATA_OUT : out std_logic_vector (31 downto 0);
-RXDISPERR_OUT : out std_logic_vector (3 downto 0);
-RXNOTINTABLE_OUT : out std_logic_vector (3 downto 0);
-RXREALIGN_OUT : out std_logic;
-CHBONDDONE_OUT : out std_logic;
-TXBUFERR_OUT : out std_logic;
-
- GTRXRESET_IN : in std_logic;
-
- LINK_RESET_IN : in std_logic; -- Link reset for hotplug scenerio.
-PLLLKDET_OUT : out std_logic;
-TXOUTCLK1_OUT : out std_logic;
-TX1N_OUT : out std_logic;
-TX1P_OUT : out std_logic;
- POWERDOWN_IN : in std_logic
-
- );
-
- end component;
-
- component BUFG
-
- port (
- O : out STD_ULOGIC;
- I : in STD_ULOGIC
- );
-
- end component;
-
-
- component north_channel_GLOBAL_LOGIC
-
- port (
-
- -- GTX Interface
-
-CH_BOND_DONE : in std_logic;
- EN_CHAN_SYNC : out std_logic;
-
- -- Aurora Lane Interface
-
-LANE_UP : in std_logic;
-SOFT_ERR : in std_logic_vector(0 to 1);
-HARD_ERR : in std_logic;
-CHANNEL_BOND_LOAD : in std_logic;
-GOT_A : in std_logic_vector(0 to 3);
-GOT_V : in std_logic;
-GEN_A : out std_logic;
-GEN_K : out std_logic_vector(0 to 3);
-GEN_R : out std_logic_vector(0 to 3);
-GEN_V : out std_logic_vector(0 to 3);
-RESET_LANES : out std_logic;
- GTRXRESET_OUT : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic;
- RESET : in std_logic;
- POWER_DOWN : in std_logic;
- CHANNEL_UP : out std_logic;
- START_RX : out std_logic;
- CHANNEL_SOFT_ERR : out std_logic;
- CHANNEL_HARD_ERR : out std_logic
-
- );
-
- end component;
-
-
- component north_channel_TX_LL
-
- port (
-
- -- LocalLink PDU Interface
-
-TX_D : in std_logic_vector(0 to 31);
-TX_REM : in std_logic_vector(0 to 1);
- TX_SRC_RDY_N : in std_logic;
- TX_SOF_N : in std_logic;
- TX_EOF_N : in std_logic;
- TX_DST_RDY_N : out std_logic;
-
- -- UFC Interface
-
- UFC_TX_REQ_N : in std_logic;
- UFC_TX_MS : in std_logic_vector(0 to 3);
- UFC_TX_ACK_N : out std_logic;
-
- -- Clock Compensation Interface
- WARN_CC : in std_logic;
- DO_CC : in std_logic;
- -- Global Logic Interface
-
- CHANNEL_UP : in std_logic;
-
- -- Aurora Lane Interface
-
- GEN_SCP : out std_logic;
- GEN_ECP : out std_logic;
- GEN_SUF : out std_logic;
- FC_NB : out std_logic_vector(0 to 3);
-TX_PE_DATA_V : out std_logic_vector(0 to 1);
-GEN_PAD : out std_logic_vector(0 to 1);
-TX_PE_DATA : out std_logic_vector(0 to 31);
-GEN_CC : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
- );
-
- end component;
-
-
- component north_channel_RX_LL
-
- port (
-
- -- LocalLink PDU Interface
-RX_D : out std_logic_vector(0 to 31);
-RX_REM : out std_logic_vector(0 to 1);
- RX_SRC_RDY_N : out std_logic;
- RX_SOF_N : out std_logic;
- RX_EOF_N : out std_logic;
-
- -- UFC Interface
-
-UFC_RX_DATA : out std_logic_vector(0 to 31);
-UFC_RX_REM : out std_logic_vector(0 to 1);
- UFC_RX_SRC_RDY_N : out std_logic;
- UFC_RX_SOF_N : out std_logic;
- UFC_RX_EOF_N : out std_logic;
-
- -- Global Logic Interface
-
- START_RX : in std_logic;
-
- -- Aurora Lane Interface
-
-RX_PAD : in std_logic_vector(0 to 1);
-RX_PE_DATA : in std_logic_vector(0 to 31);
-RX_PE_DATA_V : in std_logic_vector(0 to 1);
-RX_SCP : in std_logic_vector(0 to 1);
-RX_ECP : in std_logic_vector(0 to 1);
-RX_SUF : in std_logic_vector(0 to 1);
-RX_FC_NB : in std_logic_vector(0 to 7);
-
- -- Error Interface
-
- FRAME_ERR : out std_logic;
-
- -- System Interface
-
- USER_CLK : in std_logic
-
- );
-
- end component;
-
-component north_channel_STANDARD_CC_MODULE
- generic
- (
- CC_FREQ_FACTOR : integer := 24
- );
- port (
- -- Clock Compensation Control Interface
- WARN_CC : out std_logic;
- DO_CC : out std_logic;
- -- System Interface
- PLL_NOT_LOCKED : in std_logic;
- USER_CLK : in std_logic;
- RESET : in std_logic
- );
- end component;
--- Signal Declarations --
-
-signal TX1N_OUT_unused : std_logic;
-signal TX1P_OUT_unused : std_logic;
-signal RX1N_IN_unused : std_logic;
-signal RX1P_IN_unused : std_logic;
-signal rx_char_is_comma_i_unused : std_logic_vector(3 downto 0);
-signal rx_char_is_k_i_unused : std_logic_vector(3 downto 0);
-signal rx_data_i_unused : std_logic_vector(31 downto 0);
-signal rx_disp_err_i_unused : std_logic_vector(3 downto 0);
-signal rx_not_in_table_i_unused : std_logic_vector(3 downto 0);
-signal rx_realign_i_unused : std_logic;
-signal ch_bond_done_i_unused : std_logic;
-
-signal ch_bond_done_i : std_logic;
-signal ch_bond_done_r1 : std_logic;
-signal ch_bond_done_r2 : std_logic;
-signal ch_bond_load_not_used_i : std_logic;
-signal channel_up_i : std_logic;
-signal chbondi_not_used_i : std_logic_vector(4 downto 0);
-signal chbondo_not_used_i : std_logic_vector(4 downto 0);
-signal combus_in_not_used_i : std_logic_vector(15 downto 0);
-signal combusout_out_not_used_i: std_logic_vector(15 downto 0);
-signal en_chan_sync_i : std_logic;
-signal ena_comma_align_i : std_logic;
-signal fc_nb_i : std_logic_vector(0 to 3);
-
-signal fc_nb_striped_i : std_logic_vector(0 to 7);
-signal gen_a_i : std_logic;
-signal gen_cc_i : std_logic;
-signal gen_ecp_i : std_logic;
-signal gen_ecp_striped_i : std_logic_vector(0 to 1);
-signal gen_k_i : std_logic_vector(0 to 3);
-signal gen_pad_i : std_logic_vector(0 to 1);
-signal gen_pad_striped_i : std_logic_vector(0 to 1);
-signal gen_r_i : std_logic_vector(0 to 3);
-signal gen_scp_i : std_logic;
-signal gen_scp_striped_i : std_logic_vector(0 to 1);
-signal gen_suf_i : std_logic;
-signal gen_suf_striped_i : std_logic_vector(0 to 1);
-signal gen_v_i : std_logic_vector(0 to 3);
-signal got_a_i : std_logic_vector(0 to 3);
-signal got_v_i : std_logic;
-signal hard_err_i : std_logic;
-signal lane_up_i : std_logic;
-signal open_rx_char_is_comma_i : std_logic_vector(3 downto 0);
-signal open_rx_char_is_k_i : std_logic_vector(3 downto 0);
-signal open_rx_comma_det_i : std_logic;
-signal open_rx_data_i : std_logic_vector(31 downto 0);
-signal open_rx_disp_err_i : std_logic_vector(3 downto 0);
-signal open_rx_loss_of_sync_i : std_logic_vector(1 downto 0);
-signal open_rx_not_in_table_i : std_logic_vector(3 downto 0);
-signal open_rx_rec1_clk_i : std_logic;
-signal open_rx_rec2_clk_i : std_logic;
-signal open_rx_run_disp_i : std_logic_vector(7 downto 0);
-signal open_tx_k_err_i : std_logic_vector(7 downto 0);
-signal open_tx_run_disp_i : std_logic_vector(7 downto 0);
-signal pma_rx_lock_i : std_logic;
- signal link_reset_lane0_i : std_logic;
-signal link_reset_i : std_logic;
-signal raw_tx_out_clk_i : std_logic;
-signal reset_lanes_i : std_logic;
-signal rx_buf_err_i : std_logic;
-signal rx_char_is_comma_i : std_logic_vector(3 downto 0);
-signal rx_char_is_comma_gtx_i : std_logic_vector(7 downto 0);
-signal rx_char_is_k_i : std_logic_vector(3 downto 0);
-signal rx_char_is_k_gtx_i : std_logic_vector(7 downto 0);
-signal rx_data_i : std_logic_vector(31 downto 0);
-signal rx_data_gtx_i : std_logic_vector(63 downto 0);
-signal rx_disp_err_i : std_logic_vector(3 downto 0);
-signal rx_disp_err_gtx_i : std_logic_vector(7 downto 0);
-signal rx_ecp_i : std_logic_vector(0 to 1);
-signal rx_ecp_striped_i : std_logic_vector(0 to 1);
-signal rx_fc_nb_i : std_logic_vector(0 to 7);
-signal rx_fc_nb_striped_i : std_logic_vector(0 to 7);
-signal rx_not_in_table_i : std_logic_vector(3 downto 0);
-signal rx_not_in_table_gtx_i : std_logic_vector(7 downto 0);
-signal rx_pad_i : std_logic_vector(0 to 1);
-signal rx_pad_striped_i : std_logic_vector(0 to 1);
-signal rx_pe_data_i : std_logic_vector(0 to 31);
-signal rx_pe_data_striped_i : std_logic_vector(0 to 31);
-signal rx_pe_data_v_i : std_logic_vector(0 to 1);
-signal rx_pe_data_v_striped_i : std_logic_vector(0 to 1);
-signal rx_polarity_i : std_logic;
-signal rx_realign_i : std_logic;
-signal rx_reset_i : std_logic;
-signal rx_scp_i : std_logic_vector(0 to 1);
-signal rx_scp_striped_i : std_logic_vector(0 to 1);
-signal rx_status_float_i : std_logic_vector(4 downto 0);
-signal rx_suf_i : std_logic_vector(0 to 1);
-signal rx_suf_striped_i : std_logic_vector(0 to 1);
-signal soft_err_i : std_logic_vector(0 to 1);
-signal all_soft_err_i : std_logic;
-signal start_rx_i : std_logic;
-signal tied_to_ground_i : std_logic;
-signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
-signal tied_to_vcc_i : std_logic;
-signal tx_buf_err_i : std_logic;
-signal tx_char_is_k_i : std_logic_vector(3 downto 0);
-signal tx_data_i : std_logic_vector(31 downto 0);
-signal tx_lock_i : std_logic;
-signal tx_out_clk_i : std_logic;
-signal tx_pe_data_i : std_logic_vector(0 to 31);
-signal tx_pe_data_striped_i : std_logic_vector(0 to 31);
-signal tx_pe_data_v_i : std_logic_vector(0 to 1);
-signal tx_pe_data_v_striped_i : std_logic_vector(0 to 1);
-signal tx_reset_i : std_logic;
-signal ufc_tx_ms_i : std_logic_vector(0 to 3);
-
-signal tied_to_gnd_vec_i : std_logic_vector(0 to 31);
-signal rx_nfc_data : std_logic_vector(0 to 7);
- -- TX AXI PDU I/F signals
-signal tx_data : std_logic_vector(0 to 31);
-signal tx_rem : std_logic_vector(0 to 1);
-signal tx_src_rdy : std_logic;
-signal tx_sof : std_logic;
-signal tx_eof : std_logic;
-signal tx_dst_rdy : std_logic;
-
- -- RX AXI PDU I/F signals
-signal rx_data : std_logic_vector(0 to 31);
-signal rx_rem : std_logic_vector(0 to 1);
-signal rx_src_rdy : std_logic;
-signal rx_sof : std_logic;
-signal rx_eof : std_logic;
-
- -- TX AXI UFC I/F signals
-signal tx_ufc_data : std_logic_vector(0 to 3);
-signal tx_ufc_src_rdy : std_logic;
-signal tx_ufc_dst_rdy : std_logic;
-
- -- RX AXI UFC I/F signals
-signal rx_ufc_data : std_logic_vector(0 to 31);
-signal rx_ufc_rem : std_logic_vector(0 to 1);
-signal rx_ufc_src_rdy : std_logic;
-signal rx_ufc_sof : std_logic;
-signal rx_ufc_eof : std_logic;
-
-signal gtrxreset_i : std_logic;
-signal system_reset_i : std_logic;
-signal tx_lock_comb_i : std_logic;
-signal tx_resetdone_i : std_logic;
-signal rx_resetdone_i : std_logic;
-signal rxfsm_data_valid_r : std_logic;
-signal rst_cc_module_i : std_logic;
-signal hpcnt_reset_i : std_logic;
-signal reset_sync_init_clk : std_logic;
-signal reset_sync_user_clk : std_logic;
-signal gt_reset_sync_init_clk : std_logic;
-signal DO_CC_I : std_logic;
-signal WARN_CC : std_logic;
-begin
--- Main Body of Code --
-
- -- Tie off top level constants.
- tied_to_gnd_vec_i <= (others => '0');
- tied_to_ground_vec_i <= (others => '0');
- tied_to_ground_i <= '0';
- tied_to_vcc_i <= '1';
-
- link_reset_i <= link_reset_lane0_i ;
-
-
- process (user_clk)
- begin
- if(user_clk'event and user_clk='1') then
- rxfsm_data_valid_r <= lane_up_i after DLY;
- end if;
- end process;
-
- LINK_RESET_OUT <= link_reset_i;
-
- all_soft_err_i <= soft_err_i(0) or soft_err_i(1);
- chbondi_not_used_i <= (others => '0');
-
- -- Connect top level logic.
-
- CHANNEL_UP <= channel_up_i;
- tx_lock <= tx_lock_comb_i;
- tx_resetdone_out <= tx_resetdone_i;
- rx_resetdone_out <= rx_resetdone_i;
- sys_reset_out <= system_reset_i;
-
-
-
- --Connect the TXOUTCLK of lane 0 to TX_OUT_CLK
-TX_OUT_CLK <= raw_tx_out_clk_i;
-
- -- Connect tx_lock To tx_lock_i from lane 0
- tx_lock_comb_i <= tx_lock_i;
-
-
- reset_sync_user_clk_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1,
- c_flop_input => 0,
- c_reset_state => 0,
- c_single_bit => 1,
- c_vector_width => 2,
- c_mtbf_stages => 5
- )
- port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => RESET ,
- prmry_vect_in => "00" ,
- scndry_aclk => user_clk ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => reset_sync_user_clk,
- scndry_vect_out => open
- );
-
- gt_reset_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1,
- c_flop_input => 0,
- c_reset_state => 0,
- c_single_bit => 1,
- c_vector_width => 2,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => '0' ,
- prmry_resetn => '1' ,
- prmry_in => GT_RESET ,
- prmry_vect_in => "00" ,
- scndry_aclk => init_clk_in ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => gt_reset_sync_init_clk,
- scndry_vect_out => open
- );
-
- -- RESET_LOGIC instance
- core_reset_logic_i : north_channel_RESET_LOGIC
- port map
- (
- RESET => reset_sync_user_clk,
- USER_CLK => user_clk ,
- INIT_CLK_IN => init_clk_in ,
- TX_LOCK_IN => tx_lock_comb_i ,
- PLL_NOT_LOCKED => pll_not_locked ,
- TX_RESETDONE_IN => tx_resetdone_i ,
- RX_RESETDONE_IN => rx_resetdone_i ,
- LINK_RESET_IN => link_reset_i ,
- SYSTEM_RESET => system_reset_i
- );
-
- hpcnt_reset_cdc_sync : north_channel_cdc_sync
- generic map
- (
- c_cdc_type => 1,
- c_flop_input => 0,
- c_reset_state => 0,
- c_single_bit => 1,
- c_vector_width => 2,
- c_mtbf_stages => 6
- )
- port map
- (
- prmry_aclk => user_clk ,
- prmry_resetn => '1' ,
- prmry_in => RESET ,
- prmry_vect_in => "00" ,
- scndry_aclk => init_clk_in ,
- scndry_resetn => '1' ,
- prmry_ack => open ,
- scndry_out => reset_sync_init_clk,
- scndry_vect_out => open
- );
-
-hpcnt_reset_i <= gt_reset_sync_init_clk or reset_sync_init_clk;
-
- -- Instantiate Lane 0 --
-
-LANE_UP <= lane_up_i;
-
- -- Aurora lane striping rules require each 4-byte lane to carry 2 bytes
- -- from the first half of the overall word, and 2 bytes from the second
- -- half. This ensures that the data will be ordered correctly if it is
- -- sent to a 2-byte lane. Here we perform the required concatenation.
-
- gen_scp_striped_i <= gen_scp_i & '0';
- gen_suf_striped_i <= gen_suf_i & '0';
- fc_nb_striped_i <= fc_nb_i & "0000";
- gen_ecp_striped_i <= '0' & gen_ecp_i;
- gen_pad_striped_i(0 to 1) <= gen_pad_i(0) & gen_pad_i(1);
- tx_pe_data_striped_i(0 to 31) <= tx_pe_data_i(0 to 15) & tx_pe_data_i(16 to 31);
- tx_pe_data_v_striped_i(0 to 1) <= tx_pe_data_v_i(0) & tx_pe_data_v_i(1);
- rx_pad_i(0) <= rx_pad_striped_i(0);
- rx_pad_i(1) <= rx_pad_striped_i(1);
- rx_pe_data_i(0 to 15) <= rx_pe_data_striped_i(0 to 15);
- rx_pe_data_i(16 to 31) <= rx_pe_data_striped_i(16 to 31);
- rx_pe_data_v_i(0) <= rx_pe_data_v_striped_i(0);
- rx_pe_data_v_i(1) <= rx_pe_data_v_striped_i(1);
- rx_scp_i(0) <= rx_scp_striped_i(0);
- rx_scp_i(1) <= rx_scp_striped_i(1);
- rx_ecp_i(0) <= rx_ecp_striped_i(0);
- rx_ecp_i(1) <= rx_ecp_striped_i(1);
- rx_suf_i(0) <= rx_suf_striped_i(0);
- rx_suf_i(1) <= rx_suf_striped_i(1);
- rx_fc_nb_i(0 to 3) <= rx_fc_nb_striped_i(0 to 3);
- rx_fc_nb_i(4 to 7) <= rx_fc_nb_striped_i(4 to 7);
-
- north_channel_aurora_lane_4byte_0_i : north_channel_AURORA_LANE_4BYTE
- generic map
- (
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION
- )
- port map (
-
- -- GTX Interface
-
- RX_DATA => rx_data_i(31 downto 0),
- RX_NOT_IN_TABLE => rx_not_in_table_i(3 downto 0),
- RX_DISP_ERR => rx_disp_err_i(3 downto 0),
- RX_CHAR_IS_K => rx_char_is_k_i(3 downto 0),
- RX_CHAR_IS_COMMA => rx_char_is_comma_i(3 downto 0),
- RX_STATUS => tied_to_ground_vec_i(5 downto 0),
- TX_BUF_ERR => tx_buf_err_i,
- RX_BUF_ERR => rx_buf_err_i,
- RX_REALIGN => rx_realign_i,
- RX_POLARITY => rx_polarity_i,
- RX_RESET => rx_reset_i,
- TX_CHAR_IS_K => tx_char_is_k_i(3 downto 0),
- TX_DATA => tx_data_i(31 downto 0),
- TX_RESET => tx_reset_i,
- INIT_CLK => init_clk_in,
- LINK_RESET_OUT => link_reset_lane0_i,
- HPCNT_RESET => hpcnt_reset_i,
-
- -- Comma Detect Phase Align Interface
-
-ENA_COMMA_ALIGN => ena_comma_align_i,
-
- -- TX_LL Interface
- GEN_SCP => gen_scp_striped_i,
- GEN_SUF => gen_suf_striped_i,
- FC_NB => fc_nb_striped_i,
- GEN_ECP => gen_ecp_striped_i,
- GEN_PAD => gen_pad_striped_i(0 to 1),
- TX_PE_DATA => tx_pe_data_striped_i(0 to 31),
- TX_PE_DATA_V => tx_pe_data_v_striped_i(0 to 1),
-GEN_CC => gen_cc_i,
-
- -- RX_LL Interface
-
- RX_PAD => rx_pad_striped_i(0 to 1),
- RX_PE_DATA => rx_pe_data_striped_i(0 to 31),
- RX_PE_DATA_V => rx_pe_data_v_striped_i(0 to 1),
- RX_SCP => rx_scp_striped_i(0 to 1),
- RX_ECP => rx_ecp_striped_i(0 to 1),
- RX_SUF => rx_suf_striped_i(0 to 1),
- RX_FC_NB => rx_fc_nb_striped_i(0 to 7),
-
- -- Global Logic Interface
-
-GEN_A => gen_a_i,
- GEN_K => gen_k_i(0 to 3),
- GEN_R => gen_r_i(0 to 3),
- GEN_V => gen_v_i(0 to 3),
-LANE_UP => lane_up_i,
- SOFT_ERR => soft_err_i(0 to 1),
-HARD_ERR => hard_err_i,
-CHANNEL_BOND_LOAD => ch_bond_load_not_used_i,
- GOT_A => got_a_i(0 to 3),
-GOT_V => got_v_i,
- CHANNEL_UP => channel_up_i,
-
- -- System Interface
-
- USER_CLK => user_clk,
- RESET_SYMGEN => system_reset_i,
-RESET => reset_lanes_i
-
- );
-
-
-
-
- -- Instantiate GT Wrapper --
- gt_wrapper_i : north_channel_GT_WRAPPER
- generic map
- (
- SIM_GTRESET_SPEEDUP => SIM_GTRESET_SPEEDUP,
- EXAMPLE_SIMULATION => EXAMPLE_SIMULATION
- )
- port map
- (
-RXFSM_DATA_VALID => rxfsm_data_valid_r,
-
- gt_common_reset_out => gt_common_reset_out,
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in => gt0_pll0refclklost_in,
- quad1_common_lock_in => quad1_common_lock_in,
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
---____________________________COMMON PORTS_______________________________}
-
- gt0_txresetdone_out => open,
- gt0_rxresetdone_out => open,
- gt0_rxpmaresetdone_out => open,
- gt0_txbufstatus_out => open,
- gt0_rxbufstatus_out => open,
-
- -- DRP I/F
-DRPCLK_IN => drpclk_in,
-DRPADDR_IN => DRPADDR_IN,
-DRPDI_IN => DRPDI_IN,
-DRPDO_OUT => DRPDO_OUT,
-DRPEN_IN => DRPEN_IN,
-DRPRDY_OUT => DRPRDY_OUT,
-DRPWE_IN => DRPWE_IN,
-
- INIT_CLK_IN => init_clk_in,
- PLL_NOT_LOCKED => PLL_NOT_LOCKED,
- TX_RESETDONE_OUT => tx_resetdone_i,
- RX_RESETDONE_OUT => rx_resetdone_i,
- -- Aurora Lane Interface
-
-RXPOLARITY_IN => rx_polarity_i,
-RXRESET_IN => rx_reset_i,
-TXCHARISK_IN => tx_char_is_k_i(3 downto 0),
-TXDATA_IN => tx_data_i(31 downto 0),
-TXRESET_IN => tx_reset_i,
-RXDATA_OUT => rx_data_i(31 downto 0),
-RXNOTINTABLE_OUT => rx_not_in_table_i(3 downto 0),
-RXDISPERR_OUT => rx_disp_err_i(3 downto 0),
-RXCHARISK_OUT => rx_char_is_k_i(3 downto 0),
-RXCHARISCOMMA_OUT => rx_char_is_comma_i(3 downto 0),
-TXBUFERR_OUT => tx_buf_err_i,
-RXBUFERR_OUT => rx_buf_err_i,
-RXREALIGN_OUT => rx_realign_i,
- -- Reset due to channel initialization watchdog timer expiry
- GTRXRESET_IN => gtrxreset_i,
-
- -- reset for hot plug
- LINK_RESET_IN => link_reset_i,
-
- -- Phase Align Interface
-
-ENMCOMMAALIGN_IN => ena_comma_align_i,
-ENPCOMMAALIGN_IN => ena_comma_align_i,
- -- Global Logic Interface
-
-ENCHANSYNC_IN => en_chan_sync_i,
-CHBONDDONE_OUT => ch_bond_done_i,
-
- -- Serial IO
-RX1N_IN => RXN,
-RX1P_IN => RXP,
-TX1N_OUT => TXN,
-TX1P_OUT => TXP,
-
-
- -- Reference Clocks and User Clock
-
- RXUSRCLK_IN => sync_clk,
- RXUSRCLK2_IN => user_clk,
- TXUSRCLK_IN => sync_clk,
- TXUSRCLK2_IN => user_clk,
- REFCLK => gt_refclk1,
-
-TXOUTCLK1_OUT => raw_tx_out_clk_i,
-PLLLKDET_OUT => tx_lock_i,
-
- -- System Interface
-
- GTRESET_IN => gt_reset_sync_init_clk,
- LOOPBACK_IN => LOOPBACK,
-
- POWERDOWN_IN => POWER_DOWN
- );
-
- -- Instantiate Global Logic to combine Lanes into a Channel --
-
- north_channel_global_logic_i : north_channel_GLOBAL_LOGIC
- port map (
- -- GTX Interface
-
- CH_BOND_DONE => ch_bond_done_i,
- EN_CHAN_SYNC => en_chan_sync_i,
-
- -- Aurora Lane Interface
-
- LANE_UP => lane_up_i,
- SOFT_ERR => soft_err_i,
- HARD_ERR => hard_err_i,
- CHANNEL_BOND_LOAD => ch_bond_done_i,
- GOT_A => got_a_i,
- GOT_V => got_v_i,
- GEN_A => gen_a_i,
- GEN_K => gen_k_i,
- GEN_R => gen_r_i,
- GEN_V => gen_v_i,
- RESET_LANES => reset_lanes_i,
- GTRXRESET_OUT => gtrxreset_i,
-
-
- -- System Interface
-
- USER_CLK => user_clk,
- RESET => system_reset_i,
- POWER_DOWN => POWER_DOWN,
- CHANNEL_UP => channel_up_i,
- START_RX => start_rx_i,
- CHANNEL_SOFT_ERR => SOFT_ERR,
- CHANNEL_HARD_ERR => HARD_ERR
- );
-
-
- --_____________________________ TX AXI SHIM _______________________________
- axi_to_ll_pdu_i : north_channel_AXI_TO_LL
- generic map
- (
- DATA_WIDTH => 32,
- STRB_WIDTH => 4,
- REM_WIDTH => 2,
- USE_4_NFC => 0,
- USE_UFC_REM => 0
- )
-
- port map
- (
- AXI4_S_IP_TX_TVALID => S_AXI_TX_TVALID,
- AXI4_S_IP_TX_TDATA => S_AXI_TX_TDATA,
- AXI4_S_IP_TX_TKEEP => S_AXI_TX_TKEEP,
- AXI4_S_IP_TX_TLAST => S_AXI_TX_TLAST,
- AXI4_S_OP_TX_TREADY => S_AXI_TX_TREADY,
-
- LL_OP_DATA => tx_data,
- LL_OP_SOF_N => tx_sof,
- LL_OP_EOF_N => tx_eof,
- LL_OP_REM => tx_rem,
- LL_OP_SRC_RDY_N => tx_src_rdy,
- LL_IP_DST_RDY_N => tx_dst_rdy,
-
- -- System Interface
- USER_CLK => user_clk,
- RESET => system_reset_i,
- CHANNEL_UP => channel_up_i
- );
-
-
- axi_to_ll_ufc_i : north_channel_AXI_TO_LL
- generic map
- (
- DATA_WIDTH => 4,
- STRB_WIDTH => 4,
- REM_WIDTH => 2,
- USE_4_NFC => 2,
- USE_UFC_REM => 1
- )
-
- port map
- (
- AXI4_S_IP_TX_TVALID => S_AXI_UFC_TX_REQ,
- AXI4_S_OP_TX_TREADY => S_AXI_UFC_TX_ACK,
- AXI4_S_IP_TX_TDATA => ufc_tx_ms_i,
-AXI4_S_IP_TX_TKEEP => "0000",
- AXI4_S_IP_TX_TLAST => tied_to_ground_i,
-
- LL_OP_DATA => tx_ufc_data,
- LL_OP_SOF_N => OPEN,
- LL_OP_EOF_N => OPEN,
- LL_OP_REM => OPEN,
- LL_OP_SRC_RDY_N => tx_ufc_src_rdy,
- LL_IP_DST_RDY_N => tx_ufc_dst_rdy,
-
- -- System Interface
- USER_CLK => user_clk,
- RESET => system_reset_i,
- CHANNEL_UP => channel_up_i
- );
-
-
- -- Instantiate TX_LL --
-
- -- The TX_LL module takes 4 bits. We append a 1 to the end so all
- -- ufc message sizes are odd. This sizing is a holdover from the
- -- original Aurora protocol.
-
- ufc_tx_ms_i <= S_AXI_UFC_TX_MS & '1';
-
- rst_cc_module_i <= system_reset_i;
- standard_cc_module_i : north_channel_STANDARD_CC_MODULE
- generic map
- (
- CC_FREQ_FACTOR => CC_FREQ_FACTOR
- )
- port map (
- -- Clock Compensation Control Interface
- WARN_CC => WARN_CC,
- DO_CC => DO_CC_I,
- -- System Interface
- PLL_NOT_LOCKED => pll_not_locked,
- USER_CLK => user_clk,
- RESET => rst_cc_module_i
- );
-
- north_channel_tx_ll_i : north_channel_TX_LL
- port map (
- -- AXI PDU Interface
- TX_D => tx_data,
- TX_REM => tx_rem,
- TX_SRC_RDY_N => tx_src_rdy,
- TX_SOF_N => tx_sof,
- TX_EOF_N => tx_eof,
- TX_DST_RDY_N => tx_dst_rdy,
-
-
- -- UFC Interface
- UFC_TX_REQ_N => tx_ufc_src_rdy,
- UFC_TX_MS => tx_ufc_data,
- UFC_TX_ACK_N => tx_ufc_dst_rdy,
-
- -- Clock Compenstaion Interface
- WARN_CC => WARN_CC,
- DO_CC => DO_CC_I,
-
- -- Global Logic Interface
-
- CHANNEL_UP => channel_up_i,
-
- -- Aurora Lane Interface
-
- GEN_SCP => gen_scp_i,
- GEN_ECP => gen_ecp_i,
- GEN_SUF => gen_suf_i,
- FC_NB => fc_nb_i,
- TX_PE_DATA_V => tx_pe_data_v_i,
- GEN_PAD => gen_pad_i,
- TX_PE_DATA => tx_pe_data_i,
- GEN_CC => gen_cc_i,
-
- -- System Interface
-
- USER_CLK => user_clk
- );
-
-
- --_____________________________ RX AXI SHIM _______________________________
- ll_to_axi_pdu_i : north_channel_LL_TO_AXI
- generic map
- (
- DATA_WIDTH => 32,
- STRB_WIDTH => 4,
- REM_WIDTH => 2
- )
-
- port map
- (
- LL_IP_DATA => rx_data,
- LL_IP_SOF_N => rx_sof,
- LL_IP_EOF_N => rx_eof,
- LL_IP_REM => rx_rem,
- LL_IP_SRC_RDY_N => rx_src_rdy,
- LL_OP_DST_RDY_N => OPEN,
-
- AXI4_S_OP_TVALID => M_AXI_RX_TVALID,
- AXI4_S_OP_TDATA => M_AXI_RX_TDATA,
- AXI4_S_OP_TKEEP => M_AXI_RX_TKEEP,
- AXI4_S_OP_TLAST => M_AXI_RX_TLAST,
- AXI4_S_IP_TREADY => tied_to_ground_i
-
- );
-
- ll_to_axi_ufc_i : north_channel_LL_TO_AXI
- generic map
- (
- DATA_WIDTH => 32,
- USE_UFC_REM => 1,
- STRB_WIDTH => 4,
- REM_WIDTH => 2
- )
-
- port map
- (
- LL_IP_DATA => rx_ufc_data,
- LL_IP_SOF_N => rx_ufc_sof,
- LL_IP_EOF_N => rx_ufc_eof,
- LL_IP_REM => rx_ufc_rem,
- LL_IP_SRC_RDY_N => rx_ufc_src_rdy,
- LL_OP_DST_RDY_N => OPEN,
-
- AXI4_S_OP_TVALID => M_AXI_UFC_RX_TVALID,
- AXI4_S_OP_TDATA => M_AXI_UFC_RX_TDATA,
- AXI4_S_OP_TKEEP => M_AXI_UFC_RX_TKEEP,
- AXI4_S_OP_TLAST => M_AXI_UFC_RX_TLAST,
- AXI4_S_IP_TREADY => tied_to_ground_i
-
- );
-
-
- -- Instantiate RX_LL --
-
- north_channel_rx_ll_i : north_channel_RX_LL
- port map (
- -- AXI PDU Interface
- RX_D => rx_data,
- RX_REM => rx_rem,
- RX_SRC_RDY_N => rx_src_rdy,
- RX_SOF_N => rx_sof,
- RX_EOF_N => rx_eof,
-
- -- UFC Interface
-
- UFC_RX_DATA => rx_ufc_data,
- UFC_RX_REM => rx_ufc_rem,
- UFC_RX_SRC_RDY_N => rx_ufc_src_rdy,
- UFC_RX_SOF_N => rx_ufc_sof,
- UFC_RX_EOF_N => rx_ufc_eof,
-
- -- Global Logic Interface
-
- START_RX => start_rx_i,
-
- -- Aurora Lane Interface
-
- RX_PAD => rx_pad_i,
- RX_PE_DATA => rx_pe_data_i,
- RX_PE_DATA_V => rx_pe_data_v_i,
- RX_SCP => rx_scp_i,
- RX_ECP => rx_ecp_i,
- RX_SUF => rx_suf_i,
- RX_FC_NB => rx_fc_nb_i,
-
- -- Error Interface
-
- FRAME_ERR => FRAME_ERR,
-
- -- System Interface
-
- USER_CLK => user_clk
- );
-end MAPPED;
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_ooc.xdc b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_ooc.xdc
deleted file mode 100644
index 270142da6e9e4cf7650c95a73f9b6a4614ec05bb..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_ooc.xdc
+++ /dev/null
@@ -1,70 +0,0 @@
-
-################################################################################
-##
-## (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-## north_channel_ooc.xdc generated for xc7z015-clg485-2 device
-################################################################################
-# This constraints file contains default clock frequencies to be used during out-of-context flows such as
-# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
-# to match the target frequencies.
-# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
-################################################################################
-# 125.0MHz GT Reference clock constraint
-create_clock -period 8.0 [get_ports gt_refclk1]
-
-
-## USER_CLOCK & SYNC_CLOCK constraint
-create_clock -period 4.0 [get_ports user_clk]
-create_clock -period 4.0 [get_ports sync_clk]
-
-## 8.0 ns period INIT_CLK constraint
-create_clock -period 8.0 [get_ports init_clk_in]
-# 8.000 ns DRP Clock Constraint
-create_clock -period 8.000 [get_ports drpclk_in]
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_sim_netlist.v b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_sim_netlist.v
deleted file mode 100644
index 7dfa404691feb80dffc726ee157bf9c7449c2e6a..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_sim_netlist.v
+++ /dev/null
@@ -1,28578 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 28 10:16:16 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_sim_netlist.v
-// Design : north_channel
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* NotValidForBitStream *)
-module north_channel
- (s_axi_tx_tdata,
- s_axi_tx_tvalid,
- s_axi_tx_tready,
- s_axi_tx_tkeep,
- s_axi_tx_tlast,
- m_axi_rx_tdata,
- m_axi_rx_tvalid,
- m_axi_rx_tkeep,
- m_axi_rx_tlast,
- s_axi_ufc_tx_tvalid,
- s_axi_ufc_tx_tdata,
- s_axi_ufc_tx_tready,
- m_axi_ufc_rx_tdata,
- m_axi_ufc_rx_tkeep,
- m_axi_ufc_rx_tvalid,
- m_axi_ufc_rx_tlast,
- rxp,
- rxn,
- txp,
- txn,
- gt_refclk1,
- frame_err,
- hard_err,
- soft_err,
- channel_up,
- lane_up,
- user_clk,
- sync_clk,
- reset,
- power_down,
- loopback,
- gt_reset,
- tx_lock,
- sys_reset_out,
- init_clk_in,
- tx_resetdone_out,
- rx_resetdone_out,
- link_reset_out,
- drpclk_in,
- drpaddr_in,
- drpdi_in,
- drpdo_out,
- drpen_in,
- drprdy_out,
- drpwe_in,
- gt_common_reset_out,
- gt0_pll0refclklost_in,
- quad1_common_lock_in,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- tx_out_clk,
- pll_not_locked);
- input [0:31]s_axi_tx_tdata;
- input s_axi_tx_tvalid;
- output s_axi_tx_tready;
- input [0:3]s_axi_tx_tkeep;
- input s_axi_tx_tlast;
- output [0:31]m_axi_rx_tdata;
- output m_axi_rx_tvalid;
- output [0:3]m_axi_rx_tkeep;
- output m_axi_rx_tlast;
- input s_axi_ufc_tx_tvalid;
- input [0:2]s_axi_ufc_tx_tdata;
- output s_axi_ufc_tx_tready;
- output [0:31]m_axi_ufc_rx_tdata;
- output [0:3]m_axi_ufc_rx_tkeep;
- output m_axi_ufc_rx_tvalid;
- output m_axi_ufc_rx_tlast;
- input [0:0]rxp;
- input [0:0]rxn;
- output [0:0]txp;
- output [0:0]txn;
- input gt_refclk1;
- output frame_err;
- output hard_err;
- output soft_err;
- output channel_up;
- output [0:0]lane_up;
- input user_clk;
- input sync_clk;
- input reset;
- input power_down;
- input [2:0]loopback;
- input gt_reset;
- output tx_lock;
- output sys_reset_out;
- input init_clk_in;
- output tx_resetdone_out;
- output rx_resetdone_out;
- output link_reset_out;
- input drpclk_in;
- input [8:0]drpaddr_in;
- input [15:0]drpdi_in;
- output [15:0]drpdo_out;
- input drpen_in;
- output drprdy_out;
- input drpwe_in;
- output gt_common_reset_out;
- input gt0_pll0refclklost_in;
- input quad1_common_lock_in;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- output tx_out_clk;
- input pll_not_locked;
-
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire channel_up;
- wire [8:0]drpaddr_in;
- wire drpclk_in;
- wire [15:0]drpdi_in;
- wire [15:0]drpdo_out;
- wire drpen_in;
- wire drprdy_out;
- wire drpwe_in;
- wire frame_err;
- wire gt0_pll0refclklost_in;
- wire gt_common_reset_out;
- wire gt_refclk1;
- wire gt_reset;
- wire hard_err;
- wire init_clk_in;
- wire [0:0]lane_up;
- wire link_reset_out;
- wire [2:0]loopback;
- wire [0:31]m_axi_rx_tdata;
- wire [0:3]m_axi_rx_tkeep;
- wire m_axi_rx_tlast;
- wire m_axi_rx_tvalid;
- wire [0:31]m_axi_ufc_rx_tdata;
- wire [0:3]m_axi_ufc_rx_tkeep;
- wire m_axi_ufc_rx_tlast;
- wire m_axi_ufc_rx_tvalid;
- wire pll_not_locked;
- wire power_down;
- wire quad1_common_lock_in;
- wire reset;
- wire rx_resetdone_out;
- wire [0:0]rxn;
- wire [0:0]rxp;
- wire [0:31]s_axi_tx_tdata;
- wire [0:3]s_axi_tx_tkeep;
- wire s_axi_tx_tlast;
- wire s_axi_tx_tready;
- wire s_axi_tx_tvalid;
- wire [0:2]s_axi_ufc_tx_tdata;
- wire s_axi_ufc_tx_tready;
- wire s_axi_ufc_tx_tvalid;
- wire soft_err;
- wire sync_clk;
- wire sys_reset_out;
- wire tx_lock;
- wire tx_out_clk;
- wire tx_resetdone_out;
- wire [0:0]txn;
- wire [0:0]txp;
- wire user_clk;
-
- (* CC_FREQ_FACTOR = "12" *)
- (* EXAMPLE_SIMULATION = "0" *)
- (* SIM_GTRESET_SPEEDUP = "FALSE" *)
- north_channel_north_channel_core U0
- (.CHANNEL_UP(channel_up),
- .DRPADDR_IN(drpaddr_in),
- .DRPDI_IN(drpdi_in),
- .DRPDO_OUT(drpdo_out),
- .DRPEN_IN(drpen_in),
- .DRPRDY_OUT(drprdy_out),
- .DRPWE_IN(drpwe_in),
- .FRAME_ERR(frame_err),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .GT_RESET(gt_reset),
- .HARD_ERR(hard_err),
- .LANE_UP(lane_up),
- .LINK_RESET_OUT(link_reset_out),
- .LOOPBACK(loopback),
- .M_AXI_RX_TDATA(m_axi_rx_tdata),
- .M_AXI_RX_TKEEP(m_axi_rx_tkeep),
- .M_AXI_RX_TLAST(m_axi_rx_tlast),
- .M_AXI_RX_TVALID(m_axi_rx_tvalid),
- .M_AXI_UFC_RX_TDATA(m_axi_ufc_rx_tdata),
- .M_AXI_UFC_RX_TKEEP(m_axi_ufc_rx_tkeep),
- .M_AXI_UFC_RX_TLAST(m_axi_ufc_rx_tlast),
- .M_AXI_UFC_RX_TVALID(m_axi_ufc_rx_tvalid),
- .PLL_NOT_LOCKED(pll_not_locked),
- .POWER_DOWN(power_down),
- .RESET(reset),
- .RXN(rxn),
- .RXP(rxp),
- .RX_RESETDONE_OUT(rx_resetdone_out),
- .SOFT_ERR(soft_err),
- .S_AXI_TX_TDATA(s_axi_tx_tdata),
- .S_AXI_TX_TKEEP(s_axi_tx_tkeep),
- .S_AXI_TX_TLAST(s_axi_tx_tlast),
- .S_AXI_TX_TREADY(s_axi_tx_tready),
- .S_AXI_TX_TVALID(s_axi_tx_tvalid),
- .S_AXI_UFC_TX_ACK(s_axi_ufc_tx_tready),
- .S_AXI_UFC_TX_MS(s_axi_ufc_tx_tdata),
- .S_AXI_UFC_TX_REQ(s_axi_ufc_tx_tvalid),
- .TXN(txn),
- .TXP(txp),
- .TX_OUT_CLK(tx_out_clk),
- .TX_RESETDONE_OUT(tx_resetdone_out),
- .drpclk_in(drpclk_in),
- .gt0_pll0refclklost_in(gt0_pll0refclklost_in),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_refclk1(gt_refclk1),
- .init_clk_in(init_clk_in),
- .quad1_common_lock_in(quad1_common_lock_in),
- .sync_clk(sync_clk),
- .sys_reset_out(sys_reset_out),
- .tx_lock(tx_lock),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_AURORA_LANE_4BYTE" *)
-module north_channel_north_channel_AURORA_LANE_4BYTE
- (LANE_UP,
- ena_comma_align_i,
- tx_reset_i,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- D,
- LINK_RESET_OUT,
- got_v_i,
- rx_polarity_i,
- hard_err_i,
- Q,
- ready_r_reg,
- \previous_cycle_data_r_reg[7] ,
- \previous_cycle_control_r_reg[0] ,
- neqOp,
- \RX_SUF_Buffer_reg[0] ,
- rx_pe_data_striped_i,
- \data_nxt2_reg[26] ,
- \data_nxt2_reg[26]_0 ,
- \data_nxt2_reg[25] ,
- \RX_SUF_Buffer_reg[1] ,
- \SOFT_ERR_Buffer_reg[0] ,
- TXDATA,
- \CHAR_IS_K_OUT_reg[3] ,
- \RX_PE_DATA_V_reg[0] ,
- p_9_out,
- p_8_out,
- reset_lanes_i,
- user_clk,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[1]_0 ,
- \word_aligned_control_bits_r_reg[3] ,
- \word_aligned_control_bits_r_reg[2] ,
- hard_err_gt0,
- init_clk_in,
- gen_cc_i,
- HPCNT_RESET,
- \fc_nb_r_reg[0] ,
- \fc_nb_r_reg[1] ,
- \fc_nb_r_reg[2] ,
- rx_realign_i,
- \bypass_r_reg[0] ,
- RXNOTINTABLE,
- RXDISPERR,
- reset_count_r_reg,
- RXDATA,
- RXCHARISK,
- \RX_CHAR_IS_COMMA_R_reg[3] ,
- \word_aligned_data_r_reg[24] ,
- \word_aligned_data_r_reg[16] ,
- \soft_err_r_reg[0] ,
- \soft_err_r_reg[1] ,
- \soft_err_r_reg[2] ,
- \soft_err_r_reg[3] ,
- SS,
- \gen_v_r_reg[1] ,
- \gen_pad_r_reg[0] ,
- \tx_pe_data_v_r_reg[0] ,
- GEN_SUF,
- GEN_ECP,
- GEN_SCP,
- \gen_r_r_reg[0] ,
- \gen_k_r_reg[0] ,
- \tx_pe_data_r_reg[0] ,
- GEN_A);
- output LANE_UP;
- output ena_comma_align_i;
- output tx_reset_i;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output [0:0]D;
- output LINK_RESET_OUT;
- output got_v_i;
- output rx_polarity_i;
- output hard_err_i;
- output [1:0]Q;
- output ready_r_reg;
- output [7:0]\previous_cycle_data_r_reg[7] ;
- output [0:0]\previous_cycle_control_r_reg[0] ;
- output neqOp;
- output [1:0]\RX_SUF_Buffer_reg[0] ;
- output [0:31]rx_pe_data_striped_i;
- output \data_nxt2_reg[26] ;
- output \data_nxt2_reg[26]_0 ;
- output \data_nxt2_reg[25] ;
- output \RX_SUF_Buffer_reg[1] ;
- output [1:0]\SOFT_ERR_Buffer_reg[0] ;
- output [31:0]TXDATA;
- output [3:0]\CHAR_IS_K_OUT_reg[3] ;
- output [1:0]\RX_PE_DATA_V_reg[0] ;
- output [1:0]p_9_out;
- output [1:0]p_8_out;
- input reset_lanes_i;
- input user_clk;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[1]_0 ;
- input \word_aligned_control_bits_r_reg[3] ;
- input \word_aligned_control_bits_r_reg[2] ;
- input hard_err_gt0;
- input init_clk_in;
- input gen_cc_i;
- input HPCNT_RESET;
- input \fc_nb_r_reg[0] ;
- input \fc_nb_r_reg[1] ;
- input \fc_nb_r_reg[2] ;
- input rx_realign_i;
- input \bypass_r_reg[0] ;
- input [1:0]RXNOTINTABLE;
- input [1:0]RXDISPERR;
- input reset_count_r_reg;
- input [31:0]RXDATA;
- input [3:0]RXCHARISK;
- input [3:0]\RX_CHAR_IS_COMMA_R_reg[3] ;
- input [7:0]\word_aligned_data_r_reg[24] ;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input \soft_err_r_reg[0] ;
- input \soft_err_r_reg[1] ;
- input \soft_err_r_reg[2] ;
- input \soft_err_r_reg[3] ;
- input [0:0]SS;
- input [2:0]\gen_v_r_reg[1] ;
- input [1:0]\gen_pad_r_reg[0] ;
- input [1:0]\tx_pe_data_v_r_reg[0] ;
- input [0:0]GEN_SUF;
- input [0:0]GEN_ECP;
- input [0:0]GEN_SCP;
- input [3:0]\gen_r_r_reg[0] ;
- input [3:0]\gen_k_r_reg[0] ;
- input [31:0]\tx_pe_data_r_reg[0] ;
- input GEN_A;
-
- wire BYPASS;
- wire BYPASS_2;
- wire [3:0]\CHAR_IS_K_OUT_reg[3] ;
- wire [0:0]D;
- wire D_0;
- wire EN;
- wire EN_3;
- wire GEN_A;
- wire [0:0]GEN_ECP;
- wire [0:0]GEN_SCP;
- wire [0:0]GEN_SUF;
- wire HPCNT_RESET;
- wire LANE_UP;
- wire LINK_RESET_OUT;
- wire [1:0]Q;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire [1:0]RXNOTINTABLE;
- wire [3:0]\RX_CHAR_IS_COMMA_R_reg[3] ;
- wire [1:0]\RX_PE_DATA_V_reg[0] ;
- wire [1:0]\RX_SUF_Buffer_reg[0] ;
- wire \RX_SUF_Buffer_reg[1] ;
- wire [1:0]\SOFT_ERR_Buffer_reg[0] ;
- wire [0:0]SS;
- wire [31:0]TXDATA;
- wire begin_r0;
- wire \bypass_r_reg[0] ;
- wire bypass_w_reg;
- wire counter4_r0;
- wire \data_nxt2_reg[25] ;
- wire \data_nxt2_reg[26] ;
- wire \data_nxt2_reg[26]_0 ;
- wire [15:0]dout_temp;
- wire [15:0]dout_temp_1;
- wire ena_comma_align_i;
- wire enable_err_detect_i;
- wire \fc_nb_r_reg[0] ;
- wire \fc_nb_r_reg[1] ;
- wire \fc_nb_r_reg[2] ;
- wire first_v_received_r;
- wire gen_cc_i;
- wire gen_cc_r;
- wire [3:0]\gen_k_r_reg[0] ;
- wire [1:0]\gen_pad_r_reg[0] ;
- wire [3:0]\gen_r_r_reg[0] ;
- wire gen_sp_i;
- wire gen_spa_i;
- wire gen_spa_r;
- wire gen_v_r;
- wire gen_v_r2;
- wire [2:0]\gen_v_r_reg[1] ;
- wire good_cnt_r3;
- wire got_v_descram_in;
- wire got_v_i;
- wire hard_err_gt0;
- wire hard_err_i;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[1] ;
- wire \left_align_select_r_reg[1]_0 ;
- wire neqOp;
- wire \north_channel_descrambler0_i/p_0_in ;
- wire \north_channel_descrambler0_i/p_0_in3_in ;
- wire \north_channel_descrambler0_i/p_11_in ;
- wire \north_channel_descrambler0_i/p_12_in ;
- wire \north_channel_descrambler0_i/p_13_in28_in ;
- wire \north_channel_descrambler0_i/p_14_in ;
- wire \north_channel_descrambler0_i/p_15_in25_in ;
- wire \north_channel_descrambler0_i/p_1_in ;
- wire \north_channel_descrambler0_i/p_2_in ;
- wire \north_channel_descrambler0_i/p_3_in ;
- wire \north_channel_descrambler0_i/p_5_in ;
- wire \north_channel_descrambler0_i/p_6_in ;
- wire \north_channel_descrambler0_i/p_7_in ;
- wire \north_channel_descrambler0_i/p_8_in ;
- wire \north_channel_descrambler0_i/p_9_in ;
- wire \north_channel_descrambler1_i/p_0_in ;
- wire \north_channel_descrambler1_i/p_0_in3_in ;
- wire \north_channel_descrambler1_i/p_11_in ;
- wire \north_channel_descrambler1_i/p_12_in ;
- wire \north_channel_descrambler1_i/p_13_in28_in ;
- wire \north_channel_descrambler1_i/p_14_in ;
- wire \north_channel_descrambler1_i/p_15_in25_in ;
- wire \north_channel_descrambler1_i/p_1_in ;
- wire \north_channel_descrambler1_i/p_2_in ;
- wire \north_channel_descrambler1_i/p_3_in ;
- wire \north_channel_descrambler1_i/p_5_in ;
- wire \north_channel_descrambler1_i/p_6_in ;
- wire \north_channel_descrambler1_i/p_7_in ;
- wire \north_channel_descrambler1_i/p_8_in ;
- wire \north_channel_descrambler1_i/p_9_in ;
- wire north_channel_descrambler_top_i_n_18;
- wire north_channel_descrambler_top_i_n_34;
- wire north_channel_descrambler_top_i_n_74;
- wire \north_channel_scrambler0_i/p_0_in ;
- wire \north_channel_scrambler0_i/p_0_in3_in ;
- wire \north_channel_scrambler0_i/p_11_in ;
- wire \north_channel_scrambler0_i/p_12_in ;
- wire \north_channel_scrambler0_i/p_13_in28_in ;
- wire \north_channel_scrambler0_i/p_14_in ;
- wire \north_channel_scrambler0_i/p_15_in25_in ;
- wire \north_channel_scrambler0_i/p_1_in ;
- wire \north_channel_scrambler0_i/p_2_in ;
- wire \north_channel_scrambler0_i/p_3_in ;
- wire \north_channel_scrambler0_i/p_5_in ;
- wire \north_channel_scrambler0_i/p_6_in ;
- wire \north_channel_scrambler0_i/p_7_in ;
- wire \north_channel_scrambler0_i/p_8_in ;
- wire \north_channel_scrambler0_i/p_9_in ;
- wire \north_channel_scrambler1_i/p_0_in ;
- wire \north_channel_scrambler1_i/p_0_in3_in ;
- wire \north_channel_scrambler1_i/p_11_in ;
- wire \north_channel_scrambler1_i/p_12_in ;
- wire \north_channel_scrambler1_i/p_13_in28_in ;
- wire \north_channel_scrambler1_i/p_14_in ;
- wire \north_channel_scrambler1_i/p_15_in25_in ;
- wire \north_channel_scrambler1_i/p_1_in ;
- wire \north_channel_scrambler1_i/p_2_in ;
- wire \north_channel_scrambler1_i/p_3_in ;
- wire \north_channel_scrambler1_i/p_5_in ;
- wire \north_channel_scrambler1_i/p_6_in ;
- wire \north_channel_scrambler1_i/p_7_in ;
- wire \north_channel_scrambler1_i/p_8_in ;
- wire \north_channel_scrambler1_i/p_9_in ;
- wire north_channel_scrambler_top_i_n_15;
- wire north_channel_scrambler_top_i_n_31;
- wire north_channel_sym_dec_4byte_i_n_40;
- wire north_channel_sym_dec_4byte_i_n_45;
- wire north_channel_sym_dec_4byte_i_n_46;
- wire north_channel_sym_dec_4byte_i_n_47;
- wire north_channel_sym_dec_4byte_i_n_48;
- wire north_channel_sym_dec_4byte_i_n_49;
- wire north_channel_sym_dec_4byte_i_n_50;
- wire north_channel_sym_dec_4byte_i_n_51;
- wire north_channel_sym_dec_4byte_i_n_52;
- wire north_channel_sym_dec_4byte_i_n_53;
- wire north_channel_sym_dec_4byte_i_n_54;
- wire north_channel_sym_dec_4byte_i_n_55;
- wire north_channel_sym_dec_4byte_i_n_56;
- wire north_channel_sym_dec_4byte_i_n_57;
- wire north_channel_sym_dec_4byte_i_n_58;
- wire north_channel_sym_dec_4byte_i_n_59;
- wire north_channel_sym_dec_4byte_i_n_60;
- wire north_channel_sym_gen_4byte_i_n_10;
- wire north_channel_sym_gen_4byte_i_n_11;
- wire north_channel_sym_gen_4byte_i_n_12;
- wire north_channel_sym_gen_4byte_i_n_13;
- wire north_channel_sym_gen_4byte_i_n_14;
- wire north_channel_sym_gen_4byte_i_n_15;
- wire north_channel_sym_gen_4byte_i_n_16;
- wire north_channel_sym_gen_4byte_i_n_17;
- wire north_channel_sym_gen_4byte_i_n_18;
- wire north_channel_sym_gen_4byte_i_n_19;
- wire north_channel_sym_gen_4byte_i_n_20;
- wire north_channel_sym_gen_4byte_i_n_21;
- wire north_channel_sym_gen_4byte_i_n_22;
- wire north_channel_sym_gen_4byte_i_n_56;
- wire north_channel_sym_gen_4byte_i_n_7;
- wire north_channel_sym_gen_4byte_i_n_73;
- wire north_channel_sym_gen_4byte_i_n_8;
- wire north_channel_sym_gen_4byte_i_n_9;
- wire p_0_in_0;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [0:0]\previous_cycle_control_r_reg[0] ;
- wire [7:0]\previous_cycle_data_r_reg[7] ;
- wire ready_r_reg;
- wire reset_count_r_reg;
- wire reset_lanes_i;
- wire rx_neg_descram_in;
- wire rx_neg_i;
- wire [0:31]rx_pe_data_descram_in;
- wire [0:31]rx_pe_data_striped_i;
- wire [0:1]rx_pe_data_v_descram_in;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire rx_sp_descram_in;
- wire rx_spa_descram_in;
- wire [0:1]rx_suf_descram_in;
- wire \soft_err_r_reg[0] ;
- wire \soft_err_r_reg[1] ;
- wire \soft_err_r_reg[2] ;
- wire \soft_err_r_reg[3] ;
- wire [3:0]tx_char_is_k_i;
- wire [31:0]tx_data_i;
- wire [31:0]\tx_pe_data_r_reg[0] ;
- wire [1:0]\tx_pe_data_v_r_reg[0] ;
- wire tx_reset_i;
- wire user_clk;
- wire \word_aligned_control_bits_r_reg[2] ;
- wire \word_aligned_control_bits_r_reg[3] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
- wire [7:0]\word_aligned_data_r_reg[24] ;
-
- LUT3 #(
- .INIT(8'hFE))
- gen_v_r0
- (.I0(\gen_v_r_reg[1] [1]),
- .I1(\gen_v_r_reg[1] [0]),
- .I2(\gen_v_r_reg[1] [2]),
- .O(p_0_in_0));
- FDRE gen_v_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_v_r),
- .Q(gen_v_r2),
- .R(1'b0));
- FDRE gen_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in_0),
- .Q(gen_v_r),
- .R(1'b0));
- north_channel_north_channel_DESCRAMBLER_TOP north_channel_descrambler_top_i
- (.BYPASS(BYPASS),
- .D({north_channel_sym_dec_4byte_i_n_45,north_channel_sym_dec_4byte_i_n_46,north_channel_sym_dec_4byte_i_n_47,north_channel_sym_dec_4byte_i_n_48,north_channel_sym_dec_4byte_i_n_49,north_channel_sym_dec_4byte_i_n_50,north_channel_sym_dec_4byte_i_n_51,north_channel_sym_dec_4byte_i_n_52,north_channel_sym_dec_4byte_i_n_53,north_channel_sym_dec_4byte_i_n_54,north_channel_sym_dec_4byte_i_n_55,north_channel_sym_dec_4byte_i_n_56,north_channel_sym_dec_4byte_i_n_57,north_channel_sym_dec_4byte_i_n_58,north_channel_sym_dec_4byte_i_n_59,north_channel_sym_dec_4byte_i_n_60}),
- .\DOUT_reg[0] (north_channel_sym_dec_4byte_i_n_40),
- .\DOUT_reg[15] (dout_temp),
- .D_0(D_0),
- .E(EN),
- .Q({\north_channel_descrambler0_i/p_11_in ,\north_channel_descrambler0_i/p_8_in ,\north_channel_descrambler0_i/p_6_in ,\north_channel_descrambler0_i/p_3_in ,\north_channel_descrambler0_i/p_2_in ,\north_channel_descrambler0_i/p_0_in3_in ,\north_channel_descrambler0_i/p_0_in ,\north_channel_descrambler0_i/p_1_in ,\north_channel_descrambler0_i/p_15_in25_in ,\north_channel_descrambler0_i/p_14_in ,\north_channel_descrambler0_i/p_13_in28_in ,\north_channel_descrambler0_i/p_12_in ,\north_channel_descrambler0_i/p_9_in ,\north_channel_descrambler0_i/p_7_in ,\north_channel_descrambler0_i/p_5_in ,north_channel_descrambler_top_i_n_18}),
- .\RX_PE_DATA_V_reg[0]_0 (\RX_PE_DATA_V_reg[0] ),
- .\RX_PE_DATA_V_reg[0]_1 ({rx_pe_data_v_descram_in[0],rx_pe_data_v_descram_in[1]}),
- .RX_SPA_reg_0(north_channel_descrambler_top_i_n_74),
- .\RX_SUF_Buffer_reg[0]_0 (\RX_SUF_Buffer_reg[0] ),
- .\RX_SUF_Buffer_reg[0]_1 ({rx_suf_descram_in[0],rx_suf_descram_in[1]}),
- .\RX_SUF_Buffer_reg[1]_0 (\RX_SUF_Buffer_reg[1] ),
- .SS(SS),
- .bypass_w_reg(bypass_w_reg),
- .counter4_r0(counter4_r0),
- .\data_nxt2_reg[25]_0 (\data_nxt2_reg[25] ),
- .\data_nxt2_reg[26]_0 (\data_nxt2_reg[26] ),
- .\data_nxt2_reg[26]_1 (\data_nxt2_reg[26]_0 ),
- .gen_spa_i(gen_spa_i),
- .got_v_descram_in(got_v_descram_in),
- .got_v_i(got_v_i),
- .\lfsr_reg[15] ({\north_channel_descrambler1_i/p_11_in ,\north_channel_descrambler1_i/p_8_in ,\north_channel_descrambler1_i/p_6_in ,\north_channel_descrambler1_i/p_3_in ,\north_channel_descrambler1_i/p_2_in ,\north_channel_descrambler1_i/p_0_in3_in ,\north_channel_descrambler1_i/p_0_in ,\north_channel_descrambler1_i/p_1_in ,\north_channel_descrambler1_i/p_15_in25_in ,\north_channel_descrambler1_i/p_14_in ,\north_channel_descrambler1_i/p_13_in28_in ,\north_channel_descrambler1_i/p_12_in ,\north_channel_descrambler1_i/p_9_in ,\north_channel_descrambler1_i/p_7_in ,\north_channel_descrambler1_i/p_5_in ,north_channel_descrambler_top_i_n_34}),
- .neqOp(neqOp),
- .rx_neg_descram_in(rx_neg_descram_in),
- .rx_neg_i(rx_neg_i),
- .rx_pe_data_descram_in(rx_pe_data_descram_in),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .rx_sp_descram_in(rx_sp_descram_in),
- .rx_spa_descram_in(rx_spa_descram_in),
- .user_clk(user_clk));
- north_channel_north_channel_ERR_DETECT_4BYTE north_channel_err_detect_4byte_i
- (.\SOFT_ERR_Buffer_reg[0]_0 (\SOFT_ERR_Buffer_reg[0] ),
- .begin_r0(begin_r0),
- .enable_err_detect_i(enable_err_detect_i),
- .good_cnt_r3(good_cnt_r3),
- .hard_err_gt0(hard_err_gt0),
- .hard_err_i(hard_err_i),
- .reset_lanes_i(reset_lanes_i),
- .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
- .\soft_err_r_reg[1]_0 (\soft_err_r_reg[1] ),
- .\soft_err_r_reg[2]_0 (\soft_err_r_reg[2] ),
- .\soft_err_r_reg[3]_0 (\soft_err_r_reg[3] ),
- .user_clk(user_clk));
- north_channel_north_channel_HOTPLUG north_channel_hotplug_i
- (.D(D),
- .HPCNT_RESET(HPCNT_RESET),
- .LINK_RESET_OUT(LINK_RESET_OUT),
- .init_clk_in(init_clk_in),
- .reset_lanes_i(reset_lanes_i),
- .user_clk(user_clk));
- north_channel_north_channel_LANE_INIT_SM_4BYTE north_channel_lane_init_sm_4byte_i
- (.D(D_0),
- .GEN_SP(gen_sp_i),
- .LANE_UP(LANE_UP),
- .RXDISPERR(RXDISPERR),
- .RXNOTINTABLE(RXNOTINTABLE),
- .\RX_CHAR_IS_COMMA_R_reg[3]_0 (\RX_CHAR_IS_COMMA_R_reg[3] ),
- .align_r_reg_0(ena_comma_align_i),
- .begin_r0(begin_r0),
- .\counter3_r_reg[3]_0 (north_channel_descrambler_top_i_n_74),
- .counter4_r0(counter4_r0),
- .enable_err_detect_i(enable_err_detect_i),
- .first_v_received_r(first_v_received_r),
- .gen_spa_i(gen_spa_i),
- .gen_spa_r(gen_spa_r),
- .good_cnt_r3(good_cnt_r3),
- .ready_r_reg_0(ready_r_reg),
- .reset_count_r_reg_0(reset_count_r_reg),
- .reset_lanes_i(reset_lanes_i),
- .rst_r_reg_0(tx_reset_i),
- .rx_neg_i(rx_neg_i),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .user_clk(user_clk));
- north_channel_north_channel_SCRAMBLER_TOP north_channel_scrambler_top_i
- (.BYPASS(BYPASS_2),
- .\CHAR_IS_K_OUT_reg[3]_0 (\CHAR_IS_K_OUT_reg[3] ),
- .\CHAR_IS_K_OUT_reg[3]_1 (tx_char_is_k_i),
- .D(dout_temp_1),
- .\DOUT_reg[0] (EN_3),
- .\DOUT_reg[15] ({north_channel_sym_gen_4byte_i_n_7,north_channel_sym_gen_4byte_i_n_8,north_channel_sym_gen_4byte_i_n_9,north_channel_sym_gen_4byte_i_n_10,north_channel_sym_gen_4byte_i_n_11,north_channel_sym_gen_4byte_i_n_12,north_channel_sym_gen_4byte_i_n_13,north_channel_sym_gen_4byte_i_n_14,north_channel_sym_gen_4byte_i_n_15,north_channel_sym_gen_4byte_i_n_16,north_channel_sym_gen_4byte_i_n_17,north_channel_sym_gen_4byte_i_n_18,north_channel_sym_gen_4byte_i_n_19,north_channel_sym_gen_4byte_i_n_20,north_channel_sym_gen_4byte_i_n_21,north_channel_sym_gen_4byte_i_n_22}),
- .E(north_channel_sym_gen_4byte_i_n_56),
- .Q({\north_channel_scrambler0_i/p_11_in ,\north_channel_scrambler0_i/p_8_in ,\north_channel_scrambler0_i/p_6_in ,\north_channel_scrambler0_i/p_3_in ,\north_channel_scrambler0_i/p_2_in ,\north_channel_scrambler0_i/p_0_in3_in ,\north_channel_scrambler0_i/p_0_in ,\north_channel_scrambler0_i/p_1_in ,\north_channel_scrambler0_i/p_15_in25_in ,\north_channel_scrambler0_i/p_14_in ,\north_channel_scrambler0_i/p_13_in28_in ,\north_channel_scrambler0_i/p_12_in ,\north_channel_scrambler0_i/p_9_in ,\north_channel_scrambler0_i/p_7_in ,\north_channel_scrambler0_i/p_5_in ,north_channel_scrambler_top_i_n_15}),
- .TXDATA(TXDATA),
- .\bypass_r_reg[0]_0 (north_channel_sym_gen_4byte_i_n_73),
- .\data_nxt_reg[31]_0 (tx_data_i),
- .gen_cc_r(gen_cc_r),
- .gen_v_r2(gen_v_r2),
- .\lfsr_reg[15] ({\north_channel_scrambler1_i/p_11_in ,\north_channel_scrambler1_i/p_8_in ,\north_channel_scrambler1_i/p_6_in ,\north_channel_scrambler1_i/p_3_in ,\north_channel_scrambler1_i/p_2_in ,\north_channel_scrambler1_i/p_0_in3_in ,\north_channel_scrambler1_i/p_0_in ,\north_channel_scrambler1_i/p_1_in ,\north_channel_scrambler1_i/p_15_in25_in ,\north_channel_scrambler1_i/p_14_in ,\north_channel_scrambler1_i/p_13_in28_in ,\north_channel_scrambler1_i/p_12_in ,\north_channel_scrambler1_i/p_9_in ,\north_channel_scrambler1_i/p_7_in ,\north_channel_scrambler1_i/p_5_in ,north_channel_scrambler_top_i_n_31}),
- .\lfsr_reg[15]_0 (\bypass_r_reg[0] ),
- .reset_lanes_i(reset_lanes_i),
- .user_clk(user_clk));
- north_channel_north_channel_SYM_DEC_4BYTE north_channel_sym_dec_4byte_i
- (.BYPASS(BYPASS),
- .CHANNEL_UP_Buffer_reg(north_channel_sym_dec_4byte_i_n_40),
- .D(D),
- .\DOUT_reg[0] ({\north_channel_descrambler1_i/p_11_in ,\north_channel_descrambler1_i/p_8_in ,\north_channel_descrambler1_i/p_6_in ,\north_channel_descrambler1_i/p_3_in ,\north_channel_descrambler1_i/p_2_in ,\north_channel_descrambler1_i/p_0_in3_in ,\north_channel_descrambler1_i/p_0_in ,\north_channel_descrambler1_i/p_1_in ,\north_channel_descrambler1_i/p_15_in25_in ,\north_channel_descrambler1_i/p_14_in ,\north_channel_descrambler1_i/p_13_in28_in ,\north_channel_descrambler1_i/p_12_in ,\north_channel_descrambler1_i/p_9_in ,\north_channel_descrambler1_i/p_7_in ,\north_channel_descrambler1_i/p_5_in ,north_channel_descrambler_top_i_n_34}),
- .\DOUT_reg[0]_0 ({\north_channel_descrambler0_i/p_11_in ,\north_channel_descrambler0_i/p_8_in ,\north_channel_descrambler0_i/p_6_in ,\north_channel_descrambler0_i/p_3_in ,\north_channel_descrambler0_i/p_2_in ,\north_channel_descrambler0_i/p_0_in3_in ,\north_channel_descrambler0_i/p_0_in ,\north_channel_descrambler0_i/p_1_in ,\north_channel_descrambler0_i/p_15_in25_in ,\north_channel_descrambler0_i/p_14_in ,\north_channel_descrambler0_i/p_13_in28_in ,\north_channel_descrambler0_i/p_12_in ,\north_channel_descrambler0_i/p_9_in ,\north_channel_descrambler0_i/p_7_in ,\north_channel_descrambler0_i/p_5_in ,north_channel_descrambler_top_i_n_18}),
- .E(EN),
- .LANE_UP(LANE_UP),
- .Q(Q),
- .RXCHARISK(RXCHARISK),
- .RXDATA(RXDATA),
- .\RX_PE_DATA_Buffer_reg[0]_0 (dout_temp),
- .\RX_PE_DATA_Buffer_reg[16]_0 ({north_channel_sym_dec_4byte_i_n_45,north_channel_sym_dec_4byte_i_n_46,north_channel_sym_dec_4byte_i_n_47,north_channel_sym_dec_4byte_i_n_48,north_channel_sym_dec_4byte_i_n_49,north_channel_sym_dec_4byte_i_n_50,north_channel_sym_dec_4byte_i_n_51,north_channel_sym_dec_4byte_i_n_52,north_channel_sym_dec_4byte_i_n_53,north_channel_sym_dec_4byte_i_n_54,north_channel_sym_dec_4byte_i_n_55,north_channel_sym_dec_4byte_i_n_56,north_channel_sym_dec_4byte_i_n_57,north_channel_sym_dec_4byte_i_n_58,north_channel_sym_dec_4byte_i_n_59,north_channel_sym_dec_4byte_i_n_60}),
- .\RX_PE_DATA_V_Buffer_reg[0]_0 ({rx_pe_data_v_descram_in[0],rx_pe_data_v_descram_in[1]}),
- .\RX_SUF_Buffer_reg[0]_0 ({rx_suf_descram_in[0],rx_suf_descram_in[1]}),
- .\bypass_r_reg[0] (\bypass_r_reg[0] ),
- .bypass_w_reg(bypass_w_reg),
- .first_v_received_r(first_v_received_r),
- .got_v_descram_in(got_v_descram_in),
- .\left_align_select_r_reg[0]_0 (\left_align_select_r_reg[0] ),
- .\left_align_select_r_reg[0]_1 (\left_align_select_r_reg[0]_0 ),
- .\left_align_select_r_reg[1]_0 (\left_align_select_r_reg[1] ),
- .\left_align_select_r_reg[1]_1 (\left_align_select_r_reg[1]_0 ),
- .p_8_out(p_8_out),
- .p_9_out(p_9_out),
- .\previous_cycle_control_r_reg[0]_0 (\previous_cycle_control_r_reg[0] ),
- .\previous_cycle_data_r_reg[7]_0 (\previous_cycle_data_r_reg[7] ),
- .reset_lanes_i(reset_lanes_i),
- .rx_neg_descram_in(rx_neg_descram_in),
- .rx_pe_data_descram_in(rx_pe_data_descram_in),
- .rx_sp_descram_in(rx_sp_descram_in),
- .rx_spa_descram_in(rx_spa_descram_in),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2]_0 (\word_aligned_control_bits_r_reg[2] ),
- .\word_aligned_control_bits_r_reg[3]_0 (\word_aligned_control_bits_r_reg[3] ),
- .\word_aligned_data_r_reg[16]_0 (\word_aligned_data_r_reg[16] ),
- .\word_aligned_data_r_reg[24]_0 (\word_aligned_data_r_reg[24] ));
- north_channel_north_channel_SYM_GEN_4BYTE north_channel_sym_gen_4byte_i
- (.BYPASS(BYPASS_2),
- .CHANNEL_UP_Buffer_reg(EN_3),
- .D(dout_temp_1),
- .\DOUT_reg[0] ({\north_channel_scrambler1_i/p_11_in ,\north_channel_scrambler1_i/p_8_in ,\north_channel_scrambler1_i/p_6_in ,\north_channel_scrambler1_i/p_3_in ,\north_channel_scrambler1_i/p_2_in ,\north_channel_scrambler1_i/p_0_in3_in ,\north_channel_scrambler1_i/p_0_in ,\north_channel_scrambler1_i/p_1_in ,\north_channel_scrambler1_i/p_15_in25_in ,\north_channel_scrambler1_i/p_14_in ,\north_channel_scrambler1_i/p_13_in28_in ,\north_channel_scrambler1_i/p_12_in ,\north_channel_scrambler1_i/p_9_in ,\north_channel_scrambler1_i/p_7_in ,\north_channel_scrambler1_i/p_5_in ,north_channel_scrambler_top_i_n_31}),
- .E(north_channel_sym_gen_4byte_i_n_56),
- .GEN_A(GEN_A),
- .GEN_ECP(GEN_ECP),
- .GEN_SCP(GEN_SCP),
- .GEN_SP(gen_sp_i),
- .GEN_SUF(GEN_SUF),
- .Q({\north_channel_scrambler0_i/p_11_in ,\north_channel_scrambler0_i/p_8_in ,\north_channel_scrambler0_i/p_6_in ,\north_channel_scrambler0_i/p_3_in ,\north_channel_scrambler0_i/p_2_in ,\north_channel_scrambler0_i/p_0_in3_in ,\north_channel_scrambler0_i/p_0_in ,\north_channel_scrambler0_i/p_1_in ,\north_channel_scrambler0_i/p_15_in25_in ,\north_channel_scrambler0_i/p_14_in ,\north_channel_scrambler0_i/p_13_in28_in ,\north_channel_scrambler0_i/p_12_in ,\north_channel_scrambler0_i/p_9_in ,\north_channel_scrambler0_i/p_7_in ,\north_channel_scrambler0_i/p_5_in ,north_channel_scrambler_top_i_n_15}),
- .\TX_CHAR_IS_K_Buffer_reg[1]_0 (north_channel_sym_gen_4byte_i_n_73),
- .\TX_CHAR_IS_K_Buffer_reg[3]_0 (tx_char_is_k_i),
- .\TX_DATA_Buffer_reg[31]_0 ({north_channel_sym_gen_4byte_i_n_7,north_channel_sym_gen_4byte_i_n_8,north_channel_sym_gen_4byte_i_n_9,north_channel_sym_gen_4byte_i_n_10,north_channel_sym_gen_4byte_i_n_11,north_channel_sym_gen_4byte_i_n_12,north_channel_sym_gen_4byte_i_n_13,north_channel_sym_gen_4byte_i_n_14,north_channel_sym_gen_4byte_i_n_15,north_channel_sym_gen_4byte_i_n_16,north_channel_sym_gen_4byte_i_n_17,north_channel_sym_gen_4byte_i_n_18,north_channel_sym_gen_4byte_i_n_19,north_channel_sym_gen_4byte_i_n_20,north_channel_sym_gen_4byte_i_n_21,north_channel_sym_gen_4byte_i_n_22}),
- .\TX_DATA_Buffer_reg[31]_1 (tx_data_i),
- .\bypass_r_reg[0] (\bypass_r_reg[0] ),
- .\fc_nb_r_reg[0]_0 (\fc_nb_r_reg[0] ),
- .\fc_nb_r_reg[1]_0 (\fc_nb_r_reg[1] ),
- .\fc_nb_r_reg[2]_0 (\fc_nb_r_reg[2] ),
- .gen_cc_i(gen_cc_i),
- .gen_cc_r(gen_cc_r),
- .\gen_k_r_reg[0]_0 (\gen_k_r_reg[0] ),
- .\gen_pad_r_reg[0]_0 (\gen_pad_r_reg[0] ),
- .\gen_r_r_reg[0]_0 (\gen_r_r_reg[0] ),
- .gen_spa_i(gen_spa_i),
- .gen_spa_r(gen_spa_r),
- .gen_v_r2(gen_v_r2),
- .\gen_v_r_reg[1]_0 (\gen_v_r_reg[1] ),
- .reset_lanes_i(reset_lanes_i),
- .\tx_pe_data_r_reg[0]_0 (\tx_pe_data_r_reg[0] ),
- .\tx_pe_data_v_r_reg[0]_0 (\tx_pe_data_v_r_reg[0] ),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_AXI_TO_LL" *)
-module north_channel_north_channel_AXI_TO_LL
- (new_pkt_r_reg_0,
- new_pkt_r,
- user_clk);
- output new_pkt_r_reg_0;
- input new_pkt_r;
- input user_clk;
-
- wire new_pkt_r;
- wire new_pkt_r_reg_0;
- wire user_clk;
-
- FDRE new_pkt_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(new_pkt_r),
- .Q(new_pkt_r_reg_0),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_CHANNEL_ERR_DETECT" *)
-module north_channel_north_channel_CHANNEL_ERR_DETECT
- (SOFT_ERR,
- HARD_ERR,
- reset_channel_i,
- user_clk,
- hard_err_i,
- LANE_UP,
- POWER_DOWN,
- \soft_err_r_reg[0]_0 );
- output SOFT_ERR;
- output HARD_ERR;
- output reset_channel_i;
- input user_clk;
- input hard_err_i;
- input LANE_UP;
- input POWER_DOWN;
- input [1:0]\soft_err_r_reg[0]_0 ;
-
- wire HARD_ERR;
- wire LANE_UP;
- wire POWER_DOWN;
- wire RESET_CHANNEL_Buffer0;
- wire SOFT_ERR;
- wire channel_soft_err_c;
- wire hard_err_i;
- wire hard_err_r;
- wire lane_up_r;
- wire reset_channel_i;
- wire [1:0]soft_err_r;
- wire [1:0]\soft_err_r_reg[0]_0 ;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b1))
- CHANNEL_HARD_ERR_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(hard_err_r),
- .Q(HARD_ERR),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- CHANNEL_SOFT_ERR_Buffer_i_1
- (.I0(soft_err_r[1]),
- .I1(soft_err_r[0]),
- .O(channel_soft_err_c));
- FDRE #(
- .INIT(1'b1))
- CHANNEL_SOFT_ERR_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(channel_soft_err_c),
- .Q(SOFT_ERR),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- RESET_CHANNEL_Buffer_i_1
- (.I0(POWER_DOWN),
- .I1(lane_up_r),
- .O(RESET_CHANNEL_Buffer0));
- FDRE #(
- .INIT(1'b1))
- RESET_CHANNEL_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(RESET_CHANNEL_Buffer0),
- .Q(reset_channel_i),
- .R(1'b0));
- FDRE hard_err_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(hard_err_i),
- .Q(hard_err_r),
- .R(1'b0));
- FDRE lane_up_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(LANE_UP),
- .Q(lane_up_r),
- .R(1'b0));
- FDRE \soft_err_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[0]_0 [1]),
- .Q(soft_err_r[1]),
- .R(1'b0));
- FDRE \soft_err_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[0]_0 [0]),
- .Q(soft_err_r[0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_CHANNEL_INIT_SM" *)
-module north_channel_north_channel_CHANNEL_INIT_SM
- (reset_lanes_i,
- GTRXRESET_OUT,
- gen_ver_i,
- CHANNEL_UP_Buffer_reg_0,
- START_RX,
- SS,
- CHANNEL_UP_Buffer_reg_1,
- RESET,
- user_clk,
- got_v_i,
- wait_for_lane_up_r0,
- START_RX_Buffer_reg_0,
- \txver_count_r_reg[7]_0 ,
- D,
- reset_channel_i);
- output reset_lanes_i;
- output GTRXRESET_OUT;
- output gen_ver_i;
- output CHANNEL_UP_Buffer_reg_0;
- output START_RX;
- output [0:0]SS;
- output CHANNEL_UP_Buffer_reg_1;
- output RESET;
- input user_clk;
- input got_v_i;
- input wait_for_lane_up_r0;
- input START_RX_Buffer_reg_0;
- input \txver_count_r_reg[7]_0 ;
- input [0:0]D;
- input reset_channel_i;
-
- wire CHANNEL_UP_Buffer_reg_0;
- wire CHANNEL_UP_Buffer_reg_1;
- wire [0:0]D;
- wire D_0;
- wire GTRXRESET_OUT;
- wire GTRXRESET_OUT_i_1_n_0;
- wire GTRXRESET_OUT_i_2_n_0;
- wire Q;
- wire RESET;
- wire [0:0]SS;
- wire START_RX;
- wire START_RX_Buffer0;
- wire START_RX_Buffer_reg_0;
- wire all_lanes_v_r;
- wire bad_v_r;
- wire bad_v_r0;
- wire \free_count_r[13]_i_2_n_0 ;
- wire \free_count_r[13]_i_3_n_0 ;
- wire \free_count_r[13]_i_4_n_0 ;
- wire \free_count_r[13]_i_5_n_0 ;
- wire \free_count_r[1]_i_2_n_0 ;
- wire \free_count_r[1]_i_3_n_0 ;
- wire \free_count_r[5]_i_2_n_0 ;
- wire \free_count_r[5]_i_3_n_0 ;
- wire \free_count_r[5]_i_4_n_0 ;
- wire \free_count_r[5]_i_5_n_0 ;
- wire \free_count_r[9]_i_2_n_0 ;
- wire \free_count_r[9]_i_3_n_0 ;
- wire \free_count_r[9]_i_4_n_0 ;
- wire \free_count_r[9]_i_5_n_0 ;
- wire [0:13]free_count_r_reg;
- wire \free_count_r_reg[13]_i_1_n_0 ;
- wire \free_count_r_reg[13]_i_1_n_1 ;
- wire \free_count_r_reg[13]_i_1_n_2 ;
- wire \free_count_r_reg[13]_i_1_n_3 ;
- wire \free_count_r_reg[13]_i_1_n_4 ;
- wire \free_count_r_reg[13]_i_1_n_5 ;
- wire \free_count_r_reg[13]_i_1_n_6 ;
- wire \free_count_r_reg[13]_i_1_n_7 ;
- wire \free_count_r_reg[1]_i_1_n_3 ;
- wire \free_count_r_reg[1]_i_1_n_6 ;
- wire \free_count_r_reg[1]_i_1_n_7 ;
- wire \free_count_r_reg[5]_i_1_n_0 ;
- wire \free_count_r_reg[5]_i_1_n_1 ;
- wire \free_count_r_reg[5]_i_1_n_2 ;
- wire \free_count_r_reg[5]_i_1_n_3 ;
- wire \free_count_r_reg[5]_i_1_n_4 ;
- wire \free_count_r_reg[5]_i_1_n_5 ;
- wire \free_count_r_reg[5]_i_1_n_6 ;
- wire \free_count_r_reg[5]_i_1_n_7 ;
- wire \free_count_r_reg[9]_i_1_n_0 ;
- wire \free_count_r_reg[9]_i_1_n_1 ;
- wire \free_count_r_reg[9]_i_1_n_2 ;
- wire \free_count_r_reg[9]_i_1_n_3 ;
- wire \free_count_r_reg[9]_i_1_n_4 ;
- wire \free_count_r_reg[9]_i_1_n_5 ;
- wire \free_count_r_reg[9]_i_1_n_6 ;
- wire \free_count_r_reg[9]_i_1_n_7 ;
- wire gen_ver_i;
- wire got_first_v_r;
- wire got_first_v_r_i_1_n_0;
- wire got_v_i;
- wire [7:0]gtrxreset_extend_r;
- wire next_ready_c;
- wire next_verify_c;
- wire [15:15]p_2_out;
- wire p_3_in;
- wire ready_r;
- wire ready_r2;
- wire reset_channel_i;
- wire reset_lanes_i;
- wire rxver_count_r0;
- wire \rxver_count_r_reg[1]_srl2_n_0 ;
- wire \rxver_count_r_reg_n_0_[2] ;
- wire \txver_count_r_reg[6]_srl7_n_0 ;
- wire \txver_count_r_reg[7]_0 ;
- wire \txver_count_r_reg_n_0_[7] ;
- wire user_clk;
- wire \v_count_r_reg[14]_srl15_n_0 ;
- wire \v_count_r_reg_n_0_[15] ;
- wire verify_watchdog_r0;
- wire \verify_watchdog_r_reg[14]_srl15_i_2_n_0 ;
- wire \verify_watchdog_r_reg[14]_srl15_i_3_n_0 ;
- wire \verify_watchdog_r_reg[14]_srl15_n_0 ;
- wire \verify_watchdog_r_reg_n_0_[15] ;
- wire wait_for_lane_up_r;
- wire wait_for_lane_up_r0;
- wire [3:1]\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED ;
- wire [3:2]\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED ;
-
- FDRE CHANNEL_UP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ready_r2),
- .Q(CHANNEL_UP_Buffer_reg_0),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- FRAME_ERR_Buffer_i_1
- (.I0(START_RX),
- .O(RESET));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- GTRXRESET_OUT_i_1
- (.I0(gtrxreset_extend_r[2]),
- .I1(gtrxreset_extend_r[3]),
- .I2(gtrxreset_extend_r[0]),
- .I3(gtrxreset_extend_r[1]),
- .I4(GTRXRESET_OUT_i_2_n_0),
- .O(GTRXRESET_OUT_i_1_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- GTRXRESET_OUT_i_2
- (.I0(gtrxreset_extend_r[5]),
- .I1(gtrxreset_extend_r[4]),
- .I2(gtrxreset_extend_r[7]),
- .I3(gtrxreset_extend_r[6]),
- .O(GTRXRESET_OUT_i_2_n_0));
- FDRE GTRXRESET_OUT_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GTRXRESET_OUT_i_1_n_0),
- .Q(GTRXRESET_OUT),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- START_RX_Buffer_i_1
- (.I0(wait_for_lane_up_r),
- .O(START_RX_Buffer0));
- FDRE START_RX_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(START_RX_Buffer0),
- .Q(START_RX),
- .R(START_RX_Buffer_reg_0));
- FDRE all_lanes_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(got_v_i),
- .Q(all_lanes_v_r),
- .R(1'b0));
- LUT3 #(
- .INIT(8'h48))
- bad_v_r_i_1
- (.I0(all_lanes_v_r),
- .I1(got_first_v_r),
- .I2(\v_count_r_reg_n_0_[15] ),
- .O(bad_v_r0));
- FDRE bad_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(bad_v_r0),
- .Q(bad_v_r),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_2
- (.I0(free_count_r_reg[10]),
- .O(\free_count_r[13]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_3
- (.I0(free_count_r_reg[11]),
- .O(\free_count_r[13]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_4
- (.I0(free_count_r_reg[12]),
- .O(\free_count_r[13]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[13]_i_5
- (.I0(free_count_r_reg[13]),
- .O(\free_count_r[13]_i_5_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[1]_i_2
- (.I0(free_count_r_reg[0]),
- .O(\free_count_r[1]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[1]_i_3
- (.I0(free_count_r_reg[1]),
- .O(\free_count_r[1]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_2
- (.I0(free_count_r_reg[2]),
- .O(\free_count_r[5]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_3
- (.I0(free_count_r_reg[3]),
- .O(\free_count_r[5]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_4
- (.I0(free_count_r_reg[4]),
- .O(\free_count_r[5]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[5]_i_5
- (.I0(free_count_r_reg[5]),
- .O(\free_count_r[5]_i_5_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_2
- (.I0(free_count_r_reg[6]),
- .O(\free_count_r[9]_i_2_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_3
- (.I0(free_count_r_reg[7]),
- .O(\free_count_r[9]_i_3_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_4
- (.I0(free_count_r_reg[8]),
- .O(\free_count_r[9]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \free_count_r[9]_i_5
- (.I0(free_count_r_reg[9]),
- .O(\free_count_r[9]_i_5_n_0 ));
- FDSE \free_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[1]_i_1_n_6 ),
- .Q(free_count_r_reg[0]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_4 ),
- .Q(free_count_r_reg[10]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_5 ),
- .Q(free_count_r_reg[11]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_6 ),
- .Q(free_count_r_reg[12]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[13]_i_1_n_7 ),
- .Q(free_count_r_reg[13]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[13]_i_1
- (.CI(1'b0),
- .CO({\free_count_r_reg[13]_i_1_n_0 ,\free_count_r_reg[13]_i_1_n_1 ,\free_count_r_reg[13]_i_1_n_2 ,\free_count_r_reg[13]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O({\free_count_r_reg[13]_i_1_n_4 ,\free_count_r_reg[13]_i_1_n_5 ,\free_count_r_reg[13]_i_1_n_6 ,\free_count_r_reg[13]_i_1_n_7 }),
- .S({\free_count_r[13]_i_2_n_0 ,\free_count_r[13]_i_3_n_0 ,\free_count_r[13]_i_4_n_0 ,\free_count_r[13]_i_5_n_0 }));
- FDSE \free_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[1]_i_1_n_7 ),
- .Q(free_count_r_reg[1]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[1]_i_1
- (.CI(\free_count_r_reg[5]_i_1_n_0 ),
- .CO({\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED [3:1],\free_count_r_reg[1]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED [3:2],\free_count_r_reg[1]_i_1_n_6 ,\free_count_r_reg[1]_i_1_n_7 }),
- .S({1'b0,1'b0,\free_count_r[1]_i_2_n_0 ,\free_count_r[1]_i_3_n_0 }));
- FDSE \free_count_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_4 ),
- .Q(free_count_r_reg[2]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_5 ),
- .Q(free_count_r_reg[3]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_6 ),
- .Q(free_count_r_reg[4]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[5]_i_1_n_7 ),
- .Q(free_count_r_reg[5]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[5]_i_1
- (.CI(\free_count_r_reg[9]_i_1_n_0 ),
- .CO({\free_count_r_reg[5]_i_1_n_0 ,\free_count_r_reg[5]_i_1_n_1 ,\free_count_r_reg[5]_i_1_n_2 ,\free_count_r_reg[5]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O({\free_count_r_reg[5]_i_1_n_4 ,\free_count_r_reg[5]_i_1_n_5 ,\free_count_r_reg[5]_i_1_n_6 ,\free_count_r_reg[5]_i_1_n_7 }),
- .S({\free_count_r[5]_i_2_n_0 ,\free_count_r[5]_i_3_n_0 ,\free_count_r[5]_i_4_n_0 ,\free_count_r[5]_i_5_n_0 }));
- FDSE \free_count_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_4 ),
- .Q(free_count_r_reg[6]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_5 ),
- .Q(free_count_r_reg[7]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_6 ),
- .Q(free_count_r_reg[8]),
- .S(wait_for_lane_up_r0));
- FDSE \free_count_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\free_count_r_reg[9]_i_1_n_7 ),
- .Q(free_count_r_reg[9]),
- .S(wait_for_lane_up_r0));
- CARRY4 \free_count_r_reg[9]_i_1
- (.CI(\free_count_r_reg[13]_i_1_n_0 ),
- .CO({\free_count_r_reg[9]_i_1_n_0 ,\free_count_r_reg[9]_i_1_n_1 ,\free_count_r_reg[9]_i_1_n_2 ,\free_count_r_reg[9]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O({\free_count_r_reg[9]_i_1_n_4 ,\free_count_r_reg[9]_i_1_n_5 ,\free_count_r_reg[9]_i_1_n_6 ,\free_count_r_reg[9]_i_1_n_7 }),
- .S({\free_count_r[9]_i_2_n_0 ,\free_count_r[9]_i_3_n_0 ,\free_count_r[9]_i_4_n_0 ,\free_count_r[9]_i_5_n_0 }));
- (* SOFT_HLUTNM = "soft_lutpair179" *)
- LUT3 #(
- .INIT(8'hA8))
- got_first_v_r_i_1
- (.I0(gen_ver_i),
- .I1(got_first_v_r),
- .I2(all_lanes_v_r),
- .O(got_first_v_r_i_1_n_0));
- FDRE got_first_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(got_first_v_r_i_1_n_0),
- .Q(got_first_v_r),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gtreset_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_in),
- .Q(Q),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hAE00))
- gtreset_flop_0_i_i_1
- (.I0(\verify_watchdog_r_reg_n_0_[15] ),
- .I1(bad_v_r),
- .I2(\rxver_count_r_reg_n_0_[2] ),
- .I3(gen_ver_i),
- .O(p_3_in));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[1]),
- .Q(gtrxreset_extend_r[0]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[2]),
- .Q(gtrxreset_extend_r[1]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[3]),
- .Q(gtrxreset_extend_r[2]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[4]),
- .Q(gtrxreset_extend_r[3]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[5]),
- .Q(gtrxreset_extend_r[4]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[6]),
- .Q(gtrxreset_extend_r[5]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(gtrxreset_extend_r[7]),
- .Q(gtrxreset_extend_r[6]),
- .R(START_RX_Buffer_reg_0));
- FDRE #(
- .INIT(1'b0))
- \gtrxreset_extend_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q),
- .Q(gtrxreset_extend_r[7]),
- .R(START_RX_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair181" *)
- LUT3 #(
- .INIT(8'hFD))
- \lfsr[15]_i_1__0
- (.I0(CHANNEL_UP_Buffer_reg_0),
- .I1(reset_lanes_i),
- .I2(D),
- .O(SS));
- FDRE ready_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ready_r),
- .Q(ready_r2),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair180" *)
- LUT4 #(
- .INIT(16'hFF80))
- ready_r_i_1__0
- (.I0(\txver_count_r_reg_n_0_[7] ),
- .I1(\rxver_count_r_reg_n_0_[2] ),
- .I2(gen_ver_i),
- .I3(ready_r),
- .O(next_ready_c));
- FDRE ready_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ready_c),
- .Q(ready_r),
- .R(wait_for_lane_up_r0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- reset_lanes_flop_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D_0),
- .Q(reset_lanes_i),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hFFAE))
- reset_lanes_flop_i_i_1
- (.I0(START_RX_Buffer_reg_0),
- .I1(reset_channel_i),
- .I2(wait_for_lane_up_r),
- .I3(p_3_in),
- .O(D_0));
- (* srl_bus_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/rxver_count_r_reg " *)
- (* srl_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/rxver_count_r_reg[1]_srl2 " *)
- SRL16E \rxver_count_r_reg[1]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(rxver_count_r0),
- .CLK(user_clk),
- .D(gen_ver_i),
- .Q(\rxver_count_r_reg[1]_srl2_n_0 ));
- LUT3 #(
- .INIT(8'h8F))
- \rxver_count_r_reg[1]_srl2_i_1
- (.I0(\v_count_r_reg_n_0_[15] ),
- .I1(all_lanes_v_r),
- .I2(gen_ver_i),
- .O(rxver_count_r0));
- FDRE \rxver_count_r_reg[2]
- (.C(user_clk),
- .CE(rxver_count_r0),
- .D(\rxver_count_r_reg[1]_srl2_n_0 ),
- .Q(\rxver_count_r_reg_n_0_[2] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/txver_count_r_reg " *)
- (* srl_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/txver_count_r_reg[6]_srl7 " *)
- SRL16E \txver_count_r_reg[6]_srl7
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b0),
- .CE(\txver_count_r_reg[7]_0 ),
- .CLK(user_clk),
- .D(gen_ver_i),
- .Q(\txver_count_r_reg[6]_srl7_n_0 ));
- FDRE \txver_count_r_reg[7]
- (.C(user_clk),
- .CE(\txver_count_r_reg[7]_0 ),
- .D(\txver_count_r_reg[6]_srl7_n_0 ),
- .Q(\txver_count_r_reg_n_0_[7] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair181" *)
- LUT1 #(
- .INIT(2'h1))
- ufc_header_r_i_1
- (.I0(CHANNEL_UP_Buffer_reg_0),
- .O(CHANNEL_UP_Buffer_reg_1));
- (* srl_bus_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/v_count_r_reg " *)
- (* srl_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/v_count_r_reg[14]_srl15 " *)
- SRL16E \v_count_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_2_out),
- .Q(\v_count_r_reg[14]_srl15_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair179" *)
- LUT4 #(
- .INIT(16'hF444))
- \v_count_r_reg[14]_srl15_i_1
- (.I0(got_first_v_r),
- .I1(all_lanes_v_r),
- .I2(gen_ver_i),
- .I3(\v_count_r_reg_n_0_[15] ),
- .O(p_2_out));
- FDRE \v_count_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\v_count_r_reg[14]_srl15_n_0 ),
- .Q(\v_count_r_reg_n_0_[15] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair180" *)
- LUT4 #(
- .INIT(16'hFF2A))
- verify_r_i_2
- (.I0(gen_ver_i),
- .I1(\txver_count_r_reg_n_0_[7] ),
- .I2(\rxver_count_r_reg_n_0_[2] ),
- .I3(wait_for_lane_up_r),
- .O(next_verify_c));
- FDRE verify_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_verify_c),
- .Q(gen_ver_i),
- .R(wait_for_lane_up_r0));
- (* srl_bus_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/verify_watchdog_r_reg " *)
- (* srl_name = "U0/\north_channel_global_logic_i/channel_init_sm_i/verify_watchdog_r_reg[14]_srl15 " *)
- SRL16E \verify_watchdog_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(verify_watchdog_r0),
- .CLK(user_clk),
- .D(gen_ver_i),
- .Q(\verify_watchdog_r_reg[14]_srl15_n_0 ));
- LUT5 #(
- .INIT(32'h0200FFFF))
- \verify_watchdog_r_reg[14]_srl15_i_1
- (.I0(\verify_watchdog_r_reg[14]_srl15_i_2_n_0 ),
- .I1(free_count_r_reg[12]),
- .I2(free_count_r_reg[13]),
- .I3(\verify_watchdog_r_reg[14]_srl15_i_3_n_0 ),
- .I4(gen_ver_i),
- .O(verify_watchdog_r0));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \verify_watchdog_r_reg[14]_srl15_i_2
- (.I0(free_count_r_reg[9]),
- .I1(free_count_r_reg[8]),
- .I2(free_count_r_reg[11]),
- .I3(free_count_r_reg[10]),
- .I4(free_count_r_reg[6]),
- .I5(free_count_r_reg[7]),
- .O(\verify_watchdog_r_reg[14]_srl15_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \verify_watchdog_r_reg[14]_srl15_i_3
- (.I0(free_count_r_reg[3]),
- .I1(free_count_r_reg[2]),
- .I2(free_count_r_reg[5]),
- .I3(free_count_r_reg[4]),
- .I4(free_count_r_reg[0]),
- .I5(free_count_r_reg[1]),
- .O(\verify_watchdog_r_reg[14]_srl15_i_3_n_0 ));
- FDRE \verify_watchdog_r_reg[15]
- (.C(user_clk),
- .CE(verify_watchdog_r0),
- .D(\verify_watchdog_r_reg[14]_srl15_n_0 ),
- .Q(\verify_watchdog_r_reg_n_0_[15] ),
- .R(1'b0));
- FDRE wait_for_lane_up_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(wait_for_lane_up_r0),
- .Q(wait_for_lane_up_r),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_DESCRAMBLER_TOP" *)
-module north_channel_north_channel_DESCRAMBLER_TOP
- (rx_neg_i,
- got_v_i,
- counter4_r0,
- Q,
- \lfsr_reg[15] ,
- neqOp,
- \RX_SUF_Buffer_reg[0]_0 ,
- rx_pe_data_striped_i,
- \data_nxt2_reg[26]_0 ,
- \data_nxt2_reg[26]_1 ,
- \data_nxt2_reg[25]_0 ,
- \RX_SUF_Buffer_reg[1]_0 ,
- RX_SPA_reg_0,
- \RX_PE_DATA_V_reg[0]_0 ,
- rx_sp_descram_in,
- user_clk,
- rx_spa_descram_in,
- rx_neg_descram_in,
- got_v_descram_in,
- rx_pe_data_descram_in,
- D_0,
- gen_spa_i,
- SS,
- E,
- \DOUT_reg[0] ,
- BYPASS,
- bypass_w_reg,
- D,
- \DOUT_reg[15] ,
- \RX_PE_DATA_V_reg[0]_1 ,
- \RX_SUF_Buffer_reg[0]_1 );
- output rx_neg_i;
- output got_v_i;
- output counter4_r0;
- output [15:0]Q;
- output [15:0]\lfsr_reg[15] ;
- output neqOp;
- output [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- output [0:31]rx_pe_data_striped_i;
- output \data_nxt2_reg[26]_0 ;
- output \data_nxt2_reg[26]_1 ;
- output \data_nxt2_reg[25]_0 ;
- output \RX_SUF_Buffer_reg[1]_0 ;
- output RX_SPA_reg_0;
- output [1:0]\RX_PE_DATA_V_reg[0]_0 ;
- input rx_sp_descram_in;
- input user_clk;
- input rx_spa_descram_in;
- input rx_neg_descram_in;
- input got_v_descram_in;
- input [0:31]rx_pe_data_descram_in;
- input D_0;
- input gen_spa_i;
- input [0:0]SS;
- input [0:0]E;
- input [0:0]\DOUT_reg[0] ;
- input BYPASS;
- input bypass_w_reg;
- input [15:0]D;
- input [15:0]\DOUT_reg[15] ;
- input [1:0]\RX_PE_DATA_V_reg[0]_1 ;
- input [1:0]\RX_SUF_Buffer_reg[0]_1 ;
-
- wire BYPASS;
- wire [15:0]D;
- wire [0:0]\DOUT_reg[0] ;
- wire [15:0]\DOUT_reg[15] ;
- wire D_0;
- wire [0:0]E;
- wire [15:0]Q;
- wire [1:0]\RX_PE_DATA_V_reg[0]_0 ;
- wire [1:0]\RX_PE_DATA_V_reg[0]_1 ;
- wire RX_SPA_reg_0;
- wire [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- wire [1:0]\RX_SUF_Buffer_reg[0]_1 ;
- wire \RX_SUF_Buffer_reg[1]_0 ;
- wire [0:0]SS;
- wire \bypass_r_reg_n_0_[0] ;
- wire \bypass_r_reg_n_0_[1] ;
- wire bypass_w_reg;
- wire counter4_r0;
- wire \data_nxt2_reg[25]_0 ;
- wire \data_nxt2_reg[26]_0 ;
- wire \data_nxt2_reg[26]_1 ;
- wire \data_nxt2_reg_n_0_[0] ;
- wire \data_nxt2_reg_n_0_[10] ;
- wire \data_nxt2_reg_n_0_[11] ;
- wire \data_nxt2_reg_n_0_[12] ;
- wire \data_nxt2_reg_n_0_[13] ;
- wire \data_nxt2_reg_n_0_[14] ;
- wire \data_nxt2_reg_n_0_[15] ;
- wire \data_nxt2_reg_n_0_[16] ;
- wire \data_nxt2_reg_n_0_[17] ;
- wire \data_nxt2_reg_n_0_[18] ;
- wire \data_nxt2_reg_n_0_[19] ;
- wire \data_nxt2_reg_n_0_[1] ;
- wire \data_nxt2_reg_n_0_[20] ;
- wire \data_nxt2_reg_n_0_[21] ;
- wire \data_nxt2_reg_n_0_[22] ;
- wire \data_nxt2_reg_n_0_[23] ;
- wire \data_nxt2_reg_n_0_[24] ;
- wire \data_nxt2_reg_n_0_[25] ;
- wire \data_nxt2_reg_n_0_[26] ;
- wire \data_nxt2_reg_n_0_[27] ;
- wire \data_nxt2_reg_n_0_[28] ;
- wire \data_nxt2_reg_n_0_[29] ;
- wire \data_nxt2_reg_n_0_[2] ;
- wire \data_nxt2_reg_n_0_[30] ;
- wire \data_nxt2_reg_n_0_[31] ;
- wire \data_nxt2_reg_n_0_[3] ;
- wire \data_nxt2_reg_n_0_[4] ;
- wire \data_nxt2_reg_n_0_[5] ;
- wire \data_nxt2_reg_n_0_[6] ;
- wire \data_nxt2_reg_n_0_[7] ;
- wire \data_nxt2_reg_n_0_[8] ;
- wire \data_nxt2_reg_n_0_[9] ;
- wire gen_spa_i;
- wire got_v_descram_in;
- wire got_v_i;
- wire [15:0]\lfsr_reg[15] ;
- wire neqOp;
- wire rx_neg_descram_in;
- wire rx_neg_i;
- wire [0:31]rx_pe_data_descram_in;
- wire [0:31]rx_pe_data_striped_i;
- wire rx_sp_descram_in;
- wire rx_sp_i;
- wire rx_spa_descram_in;
- wire rx_spa_i;
- wire user_clk;
-
- FDRE GOT_V_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(got_v_descram_in),
- .Q(got_v_i),
- .R(1'b0));
- FDRE RX_NEG_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_neg_descram_in),
- .Q(rx_neg_i),
- .R(1'b0));
- FDRE \RX_PE_DATA_V_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_reg[0]_1 [1]),
- .Q(\RX_PE_DATA_V_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_PE_DATA_V_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_reg[0]_1 [0]),
- .Q(\RX_PE_DATA_V_reg[0]_0 [0]),
- .R(1'b0));
- FDRE RX_SPA_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_spa_descram_in),
- .Q(rx_spa_i),
- .R(1'b0));
- FDRE RX_SP_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_sp_descram_in),
- .Q(rx_sp_i),
- .R(1'b0));
- FDRE \RX_SUF_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_SUF_Buffer_reg[0]_1 [1]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_SUF_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_SUF_Buffer_reg[0]_1 [0]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \bypass_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(bypass_w_reg),
- .Q(\bypass_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \bypass_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(BYPASS),
- .Q(\bypass_r_reg_n_0_[1] ),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- \counter3_r_reg[2]_srl3_i_1
- (.I0(rx_spa_i),
- .I1(gen_spa_i),
- .O(RX_SPA_reg_0));
- LUT2 #(
- .INIT(4'hB))
- \counter4_r_reg[14]_srl15_i_1
- (.I0(rx_sp_i),
- .I1(D_0),
- .O(counter4_r0));
- FDRE \data_nxt2_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[0]),
- .Q(\data_nxt2_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[10]),
- .Q(\data_nxt2_reg_n_0_[10] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[11]),
- .Q(\data_nxt2_reg_n_0_[11] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[12]),
- .Q(\data_nxt2_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[13]),
- .Q(\data_nxt2_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[14]),
- .Q(\data_nxt2_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[15]),
- .Q(\data_nxt2_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[16]),
- .Q(\data_nxt2_reg_n_0_[16] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[17]),
- .Q(\data_nxt2_reg_n_0_[17] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[18]),
- .Q(\data_nxt2_reg_n_0_[18] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[19]),
- .Q(\data_nxt2_reg_n_0_[19] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[1]),
- .Q(\data_nxt2_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[20]),
- .Q(\data_nxt2_reg_n_0_[20] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[21]),
- .Q(\data_nxt2_reg_n_0_[21] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[22]),
- .Q(\data_nxt2_reg_n_0_[22] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[23]),
- .Q(\data_nxt2_reg_n_0_[23] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[24]),
- .Q(\data_nxt2_reg_n_0_[24] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[25]),
- .Q(\data_nxt2_reg_n_0_[25] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[26]),
- .Q(\data_nxt2_reg_n_0_[26] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[27]),
- .Q(\data_nxt2_reg_n_0_[27] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[28]),
- .Q(\data_nxt2_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[29]),
- .Q(\data_nxt2_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[2]),
- .Q(\data_nxt2_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[30]),
- .Q(\data_nxt2_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[31]),
- .Q(\data_nxt2_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[3]),
- .Q(\data_nxt2_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[4]),
- .Q(\data_nxt2_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[5]),
- .Q(\data_nxt2_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[6]),
- .Q(\data_nxt2_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[7]),
- .Q(\data_nxt2_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[8]),
- .Q(\data_nxt2_reg_n_0_[8] ),
- .R(1'b0));
- FDRE \data_nxt2_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_descram_in[9]),
- .Q(\data_nxt2_reg_n_0_[9] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair74" *)
- LUT2 #(
- .INIT(4'hE))
- load_ufc_control_code_r_i_1
- (.I0(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I1(\RX_SUF_Buffer_reg[0]_0 [0]),
- .O(neqOp));
- north_channel_north_channel_SCRAMBLER_3 north_channel_descrambler0_i
- (.\DOUT_reg[15]_0 (\DOUT_reg[15] ),
- .E(E),
- .Q(Q),
- .SS(SS),
- .rx_pe_data_striped_i({rx_pe_data_striped_i[0],rx_pe_data_striped_i[1],rx_pe_data_striped_i[2],rx_pe_data_striped_i[3],rx_pe_data_striped_i[4],rx_pe_data_striped_i[5],rx_pe_data_striped_i[6],rx_pe_data_striped_i[7],rx_pe_data_striped_i[8],rx_pe_data_striped_i[9],rx_pe_data_striped_i[10],rx_pe_data_striped_i[11],rx_pe_data_striped_i[12],rx_pe_data_striped_i[13],rx_pe_data_striped_i[14],rx_pe_data_striped_i[15]}),
- .\stage_1_data_r_reg[0] ({\data_nxt2_reg_n_0_[0] ,\data_nxt2_reg_n_0_[1] ,\data_nxt2_reg_n_0_[2] ,\data_nxt2_reg_n_0_[3] ,\data_nxt2_reg_n_0_[4] ,\data_nxt2_reg_n_0_[5] ,\data_nxt2_reg_n_0_[6] ,\data_nxt2_reg_n_0_[7] ,\data_nxt2_reg_n_0_[12] ,\data_nxt2_reg_n_0_[13] ,\data_nxt2_reg_n_0_[14] ,\data_nxt2_reg_n_0_[15] }),
- .\stage_1_data_r_reg[10] (\data_nxt2_reg_n_0_[10] ),
- .\stage_1_data_r_reg[11] (\data_nxt2_reg_n_0_[11] ),
- .\stage_1_data_r_reg[15] (\bypass_r_reg_n_0_[0] ),
- .\stage_1_data_r_reg[8] (\data_nxt2_reg_n_0_[8] ),
- .\stage_1_data_r_reg[9] (\data_nxt2_reg_n_0_[9] ),
- .user_clk(user_clk));
- north_channel_north_channel_SCRAMBLER_4 north_channel_descrambler1_i
- (.D(D),
- .\DOUT_reg[0]_0 (\DOUT_reg[0] ),
- .Q(\lfsr_reg[15] ),
- .SS(SS),
- .rx_pe_data_striped_i({rx_pe_data_striped_i[16],rx_pe_data_striped_i[17],rx_pe_data_striped_i[18],rx_pe_data_striped_i[19],rx_pe_data_striped_i[20],rx_pe_data_striped_i[21],rx_pe_data_striped_i[22],rx_pe_data_striped_i[23],rx_pe_data_striped_i[24],rx_pe_data_striped_i[25],rx_pe_data_striped_i[26],rx_pe_data_striped_i[27],rx_pe_data_striped_i[28],rx_pe_data_striped_i[29],rx_pe_data_striped_i[30],rx_pe_data_striped_i[31]}),
- .\stage_1_data_r_reg[16] ({\data_nxt2_reg_n_0_[16] ,\data_nxt2_reg_n_0_[17] ,\data_nxt2_reg_n_0_[18] ,\data_nxt2_reg_n_0_[19] ,\data_nxt2_reg_n_0_[20] ,\data_nxt2_reg_n_0_[21] ,\data_nxt2_reg_n_0_[22] ,\data_nxt2_reg_n_0_[23] ,\data_nxt2_reg_n_0_[28] ,\data_nxt2_reg_n_0_[29] ,\data_nxt2_reg_n_0_[30] ,\data_nxt2_reg_n_0_[31] }),
- .\stage_1_data_r_reg[24] (\data_nxt2_reg_n_0_[24] ),
- .\stage_1_data_r_reg[25] (\data_nxt2_reg_n_0_[25] ),
- .\stage_1_data_r_reg[26] (\data_nxt2_reg_n_0_[26] ),
- .\stage_1_data_r_reg[27] (\data_nxt2_reg_n_0_[27] ),
- .\stage_1_data_r_reg[31] (\bypass_r_reg_n_0_[1] ),
- .user_clk(user_clk));
- LUT4 #(
- .INIT(16'h8000))
- \stage_1_count_value_r[0]_i_1
- (.I0(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I1(\data_nxt2_reg_n_0_[24] ),
- .I2(\data_nxt2_reg_n_0_[26] ),
- .I3(\data_nxt2_reg_n_0_[25] ),
- .O(\RX_SUF_Buffer_reg[1]_0 ));
- LUT6 #(
- .INIT(64'h78FF780078007800))
- \stage_1_count_value_r[1]_i_1
- (.I0(\data_nxt2_reg_n_0_[25] ),
- .I1(\data_nxt2_reg_n_0_[26] ),
- .I2(\data_nxt2_reg_n_0_[24] ),
- .I3(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I4(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I5(\data_nxt2_reg_n_0_[8] ),
- .O(\data_nxt2_reg[25]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair74" *)
- LUT5 #(
- .INIT(32'h6F606060))
- \stage_1_count_value_r[2]_i_1
- (.I0(\data_nxt2_reg_n_0_[26] ),
- .I1(\data_nxt2_reg_n_0_[25] ),
- .I2(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I3(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I4(\data_nxt2_reg_n_0_[9] ),
- .O(\data_nxt2_reg[26]_1 ));
- LUT4 #(
- .INIT(16'h7444))
- \stage_1_count_value_r[3]_i_1
- (.I0(\data_nxt2_reg_n_0_[26] ),
- .I1(\RX_SUF_Buffer_reg[0]_0 [0]),
- .I2(\RX_SUF_Buffer_reg[0]_0 [1]),
- .I3(\data_nxt2_reg_n_0_[10] ),
- .O(\data_nxt2_reg[26]_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_ERR_DETECT_4BYTE" *)
-module north_channel_north_channel_ERR_DETECT_4BYTE
- (begin_r0,
- hard_err_i,
- \SOFT_ERR_Buffer_reg[0]_0 ,
- good_cnt_r3,
- user_clk,
- hard_err_gt0,
- reset_lanes_i,
- enable_err_detect_i,
- \soft_err_r_reg[0]_0 ,
- \soft_err_r_reg[1]_0 ,
- \soft_err_r_reg[2]_0 ,
- \soft_err_r_reg[3]_0 );
- output begin_r0;
- output hard_err_i;
- output [1:0]\SOFT_ERR_Buffer_reg[0]_0 ;
- input good_cnt_r3;
- input user_clk;
- input hard_err_gt0;
- input reset_lanes_i;
- input enable_err_detect_i;
- input \soft_err_r_reg[0]_0 ;
- input \soft_err_r_reg[1]_0 ;
- input \soft_err_r_reg[2]_0 ;
- input \soft_err_r_reg[3]_0 ;
-
- wire [1:0]\SOFT_ERR_Buffer_reg[0]_0 ;
- wire begin_r0;
- wire cnt_good_code_r;
- wire cnt_good_code_r_i_2_n_0;
- wire cnt_good_code_r_i_3_n_0;
- wire cnt_soft_err_r;
- wire enable_err_detect_i;
- wire \err_cnt_r[0]_i_1_n_0 ;
- wire \err_cnt_r[1]_i_1_n_0 ;
- wire \err_cnt_r[2]_i_1_n_0 ;
- wire \err_cnt_r[2]_i_2_n_0 ;
- wire \err_cnt_r_reg_n_0_[0] ;
- wire \err_cnt_r_reg_n_0_[1] ;
- wire good_cnt_r3;
- wire \good_cnt_r[3]_i_1_n_0 ;
- wire [3:0]good_cnt_r_reg;
- wire hard_err_frm_soft_err;
- wire hard_err_gt;
- wire hard_err_gt0;
- wire hard_err_i;
- wire next_good_code_c;
- wire next_soft_err_c;
- wire next_start_c;
- wire p_0_in;
- wire p_1_in;
- wire p_2_in;
- wire [1:0]p_3_out;
- wire [3:0]plusOp;
- wire reset_lanes_i;
- wire \soft_err_r_reg[0]_0 ;
- wire \soft_err_r_reg[1]_0 ;
- wire \soft_err_r_reg[2]_0 ;
- wire \soft_err_r_reg[3]_0 ;
- wire \soft_err_r_reg_n_0_[0] ;
- wire \soft_err_r_reg_n_0_[3] ;
- wire start_r;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'hE))
- \SOFT_ERR_Buffer[0]_i_1
- (.I0(p_2_in),
- .I1(\soft_err_r_reg_n_0_[0] ),
- .O(p_3_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair78" *)
- LUT2 #(
- .INIT(4'hE))
- \SOFT_ERR_Buffer[1]_i_1
- (.I0(\soft_err_r_reg_n_0_[3] ),
- .I1(p_1_in),
- .O(p_3_out[0]));
- FDRE \SOFT_ERR_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[1]),
- .Q(\SOFT_ERR_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \SOFT_ERR_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[0]),
- .Q(\SOFT_ERR_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair79" *)
- LUT4 #(
- .INIT(16'hFFAE))
- align_r_i_1
- (.I0(hard_err_gt),
- .I1(p_0_in),
- .I2(hard_err_frm_soft_err),
- .I3(reset_lanes_i),
- .O(begin_r0));
- (* SOFT_HLUTNM = "soft_lutpair76" *)
- LUT4 #(
- .INIT(16'h00EA))
- cnt_good_code_r_i_1
- (.I0(cnt_soft_err_r),
- .I1(cnt_good_code_r_i_2_n_0),
- .I2(cnt_good_code_r),
- .I3(cnt_good_code_r_i_3_n_0),
- .O(next_good_code_c));
- (* SOFT_HLUTNM = "soft_lutpair77" *)
- LUT4 #(
- .INIT(16'h7FFF))
- cnt_good_code_r_i_2
- (.I0(good_cnt_r_reg[2]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[1]),
- .I3(good_cnt_r_reg[3]),
- .O(cnt_good_code_r_i_2_n_0));
- (* SOFT_HLUTNM = "soft_lutpair78" *)
- LUT4 #(
- .INIT(16'hFFFE))
- cnt_good_code_r_i_3
- (.I0(p_1_in),
- .I1(\soft_err_r_reg_n_0_[3] ),
- .I2(\soft_err_r_reg_n_0_[0] ),
- .I3(p_2_in),
- .O(cnt_good_code_r_i_3_n_0));
- FDRE cnt_good_code_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_good_code_c),
- .Q(cnt_good_code_r),
- .R(good_cnt_r3));
- (* SOFT_HLUTNM = "soft_lutpair76" *)
- LUT4 #(
- .INIT(16'hFE00))
- cnt_soft_err_r_i_1
- (.I0(start_r),
- .I1(cnt_soft_err_r),
- .I2(cnt_good_code_r),
- .I3(cnt_good_code_r_i_3_n_0),
- .O(next_soft_err_c));
- FDRE cnt_soft_err_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_soft_err_c),
- .Q(cnt_soft_err_r),
- .R(good_cnt_r3));
- LUT5 #(
- .INIT(32'hBEBE4140))
- \err_cnt_r[0]_i_1
- (.I0(p_0_in),
- .I1(cnt_soft_err_r),
- .I2(\err_cnt_r[2]_i_2_n_0 ),
- .I3(\err_cnt_r_reg_n_0_[1] ),
- .I4(\err_cnt_r_reg_n_0_[0] ),
- .O(\err_cnt_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair75" *)
- LUT5 #(
- .INIT(32'hAAAA6AA8))
- \err_cnt_r[1]_i_1
- (.I0(\err_cnt_r_reg_n_0_[1] ),
- .I1(\err_cnt_r_reg_n_0_[0] ),
- .I2(\err_cnt_r[2]_i_2_n_0 ),
- .I3(cnt_soft_err_r),
- .I4(p_0_in),
- .O(\err_cnt_r[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair75" *)
- LUT5 #(
- .INIT(32'hFFFF8000))
- \err_cnt_r[2]_i_1
- (.I0(\err_cnt_r_reg_n_0_[1] ),
- .I1(\err_cnt_r_reg_n_0_[0] ),
- .I2(\err_cnt_r[2]_i_2_n_0 ),
- .I3(cnt_soft_err_r),
- .I4(p_0_in),
- .O(\err_cnt_r[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair77" *)
- LUT4 #(
- .INIT(16'hEEEF))
- \err_cnt_r[2]_i_2
- (.I0(good_cnt_r_reg[1]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[3]),
- .I3(good_cnt_r_reg[2]),
- .O(\err_cnt_r[2]_i_2_n_0 ));
- FDRE \err_cnt_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\err_cnt_r[0]_i_1_n_0 ),
- .Q(\err_cnt_r_reg_n_0_[0] ),
- .R(good_cnt_r3));
- FDRE \err_cnt_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\err_cnt_r[1]_i_1_n_0 ),
- .Q(\err_cnt_r_reg_n_0_[1] ),
- .R(good_cnt_r3));
- FDRE \err_cnt_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\err_cnt_r[2]_i_1_n_0 ),
- .Q(p_0_in),
- .R(good_cnt_r3));
- (* SOFT_HLUTNM = "soft_lutpair81" *)
- LUT1 #(
- .INIT(2'h1))
- \good_cnt_r[0]_i_1
- (.I0(good_cnt_r_reg[0]),
- .O(plusOp[0]));
- (* SOFT_HLUTNM = "soft_lutpair81" *)
- LUT2 #(
- .INIT(4'h6))
- \good_cnt_r[1]_i_1
- (.I0(good_cnt_r_reg[0]),
- .I1(good_cnt_r_reg[1]),
- .O(plusOp[1]));
- (* SOFT_HLUTNM = "soft_lutpair80" *)
- LUT3 #(
- .INIT(8'h78))
- \good_cnt_r[2]_i_1
- (.I0(good_cnt_r_reg[1]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[2]),
- .O(plusOp[2]));
- LUT4 #(
- .INIT(16'hFFF7))
- \good_cnt_r[3]_i_1
- (.I0(cnt_good_code_r),
- .I1(enable_err_detect_i),
- .I2(cnt_soft_err_r),
- .I3(start_r),
- .O(\good_cnt_r[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair80" *)
- LUT4 #(
- .INIT(16'h7F80))
- \good_cnt_r[3]_i_2
- (.I0(good_cnt_r_reg[2]),
- .I1(good_cnt_r_reg[0]),
- .I2(good_cnt_r_reg[1]),
- .I3(good_cnt_r_reg[3]),
- .O(plusOp[3]));
- FDRE \good_cnt_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[0]),
- .Q(good_cnt_r_reg[0]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE \good_cnt_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[1]),
- .Q(good_cnt_r_reg[1]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE \good_cnt_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[2]),
- .Q(good_cnt_r_reg[2]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE \good_cnt_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(plusOp[3]),
- .Q(good_cnt_r_reg[3]),
- .R(\good_cnt_r[3]_i_1_n_0 ));
- FDRE hard_err_frm_soft_err_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in),
- .Q(hard_err_frm_soft_err),
- .R(good_cnt_r3));
- FDRE hard_err_gt_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(hard_err_gt0),
- .Q(hard_err_gt),
- .R(good_cnt_r3));
- (* SOFT_HLUTNM = "soft_lutpair79" *)
- LUT3 #(
- .INIT(8'hF4))
- hard_err_r_i_1
- (.I0(hard_err_frm_soft_err),
- .I1(p_0_in),
- .I2(hard_err_gt),
- .O(hard_err_i));
- FDRE \soft_err_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[0]_0 ),
- .Q(\soft_err_r_reg_n_0_[0] ),
- .R(good_cnt_r3));
- FDRE \soft_err_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[1]_0 ),
- .Q(p_2_in),
- .R(good_cnt_r3));
- FDRE \soft_err_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[2]_0 ),
- .Q(p_1_in),
- .R(good_cnt_r3));
- FDRE \soft_err_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\soft_err_r_reg[3]_0 ),
- .Q(\soft_err_r_reg_n_0_[3] ),
- .R(good_cnt_r3));
- LUT4 #(
- .INIT(16'h00BA))
- start_r_i_1
- (.I0(start_r),
- .I1(cnt_good_code_r_i_2_n_0),
- .I2(cnt_good_code_r),
- .I3(cnt_good_code_r_i_3_n_0),
- .O(next_start_c));
- FDSE start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_start_c),
- .Q(start_r),
- .S(good_cnt_r3));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_GLOBAL_LOGIC" *)
-module north_channel_north_channel_GLOBAL_LOGIC
- (reset_lanes_i,
- gen_v_flop_1_i,
- GEN_A,
- gen_k_flop_0_i,
- gen_r_flop_0_i,
- GTRXRESET_OUT,
- CHANNEL_UP_Buffer_reg,
- SOFT_ERR,
- HARD_ERR,
- reset_channel_i,
- START_RX,
- SS,
- CHANNEL_UP_Buffer_reg_0,
- RESET,
- user_clk,
- got_v_i,
- wait_for_lane_up_r0,
- hard_err_i,
- LANE_UP,
- \downcounter_r_reg[2] ,
- D,
- POWER_DOWN,
- \soft_err_r_reg[0] );
- output reset_lanes_i;
- output [2:0]gen_v_flop_1_i;
- output GEN_A;
- output [3:0]gen_k_flop_0_i;
- output [3:0]gen_r_flop_0_i;
- output GTRXRESET_OUT;
- output CHANNEL_UP_Buffer_reg;
- output SOFT_ERR;
- output HARD_ERR;
- output reset_channel_i;
- output START_RX;
- output [0:0]SS;
- output CHANNEL_UP_Buffer_reg_0;
- output RESET;
- input user_clk;
- input got_v_i;
- input wait_for_lane_up_r0;
- input hard_err_i;
- input LANE_UP;
- input \downcounter_r_reg[2] ;
- input [0:0]D;
- input POWER_DOWN;
- input [1:0]\soft_err_r_reg[0] ;
-
- wire CHANNEL_UP_Buffer_reg;
- wire CHANNEL_UP_Buffer_reg_0;
- wire [0:0]D;
- wire GEN_A;
- wire GTRXRESET_OUT;
- wire HARD_ERR;
- wire LANE_UP;
- wire POWER_DOWN;
- wire RESET;
- wire SOFT_ERR;
- wire [0:0]SS;
- wire START_RX;
- wire \downcounter_r_reg[2] ;
- wire [3:0]gen_k_flop_0_i;
- wire [3:0]gen_r_flop_0_i;
- wire [2:0]gen_v_flop_1_i;
- wire gen_ver_i;
- wire got_v_i;
- wire hard_err_i;
- wire idle_and_ver_gen_i_n_12;
- wire reset_channel_i;
- wire reset_lanes_i;
- wire [1:0]\soft_err_r_reg[0] ;
- wire user_clk;
- wire wait_for_lane_up_r0;
-
- north_channel_north_channel_CHANNEL_ERR_DETECT channel_err_detect_i
- (.HARD_ERR(HARD_ERR),
- .LANE_UP(LANE_UP),
- .POWER_DOWN(POWER_DOWN),
- .SOFT_ERR(SOFT_ERR),
- .hard_err_i(hard_err_i),
- .reset_channel_i(reset_channel_i),
- .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
- .user_clk(user_clk));
- north_channel_north_channel_CHANNEL_INIT_SM channel_init_sm_i
- (.CHANNEL_UP_Buffer_reg_0(CHANNEL_UP_Buffer_reg),
- .CHANNEL_UP_Buffer_reg_1(CHANNEL_UP_Buffer_reg_0),
- .D(D),
- .GTRXRESET_OUT(GTRXRESET_OUT),
- .RESET(RESET),
- .SS(SS),
- .START_RX(START_RX),
- .START_RX_Buffer_reg_0(\downcounter_r_reg[2] ),
- .gen_ver_i(gen_ver_i),
- .got_v_i(got_v_i),
- .reset_channel_i(reset_channel_i),
- .reset_lanes_i(reset_lanes_i),
- .\txver_count_r_reg[7]_0 (idle_and_ver_gen_i_n_12),
- .user_clk(user_clk),
- .wait_for_lane_up_r0(wait_for_lane_up_r0));
- north_channel_north_channel_IDLE_AND_VER_GEN idle_and_ver_gen_i
- (.DID_VER_Buffer_reg_0(idle_and_ver_gen_i_n_12),
- .GEN_A(GEN_A),
- .\downcounter_r_reg[2]_0 (\downcounter_r_reg[2] ),
- .gen_k_flop_0_i_0(gen_k_flop_0_i),
- .gen_r_flop_0_i_0(gen_r_flop_0_i),
- .gen_v_flop_1_i_0(gen_v_flop_1_i),
- .gen_ver_i(gen_ver_i),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_GT_WRAPPER" *)
-module north_channel_north_channel_GT_WRAPPER
- (TX_RESETDONE_OUT,
- drpclk_in_0,
- TXN,
- TXP,
- rx_realign_i,
- TX_OUT_CLK,
- DRPDO_OUT,
- RXDATA,
- D,
- RXCHARISK,
- RXDISPERR,
- RXNOTINTABLE,
- RX_RESETDONE_OUT,
- gt_common_reset_out,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- rst_r_reg,
- drpclk_in_1,
- drpclk_in_2,
- drpclk_in_3,
- drpclk_in_4,
- \left_align_select_r_reg[1]_0 ,
- \left_align_select_r_reg[1]_1 ,
- \left_align_select_r_reg[1]_2 ,
- \left_align_select_r_reg[1]_3 ,
- hard_err_gt0,
- tx_lock,
- rxfsm_rxresetdone_r3_reg_0,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ,
- quad1_common_lock_in,
- drpclk_in,
- RXN,
- RXP,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- ena_comma_align_i,
- rx_polarity_i,
- sync_clk,
- user_clk,
- POWER_DOWN,
- LOOPBACK,
- TXDATA,
- Q,
- GTRXRESET_OUT,
- init_clk_in,
- link_reset_r,
- AR,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[0]_1 ,
- \left_align_select_r_reg[1]_4 ,
- tx_reset_i,
- \word_aligned_data_r_reg[16] ,
- \word_aligned_control_bits_r_reg[2] ,
- PLL_NOT_LOCKED,
- DRPADDR_IN,
- DRPDI_IN,
- DRPWE_IN,
- DRPEN_IN);
- output TX_RESETDONE_OUT;
- output drpclk_in_0;
- output TXN;
- output TXP;
- output rx_realign_i;
- output TX_OUT_CLK;
- output [15:0]DRPDO_OUT;
- output [31:0]RXDATA;
- output [3:0]D;
- output [3:0]RXCHARISK;
- output [1:0]RXDISPERR;
- output [1:0]RXNOTINTABLE;
- output RX_RESETDONE_OUT;
- output gt_common_reset_out;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output rst_r_reg;
- output drpclk_in_1;
- output drpclk_in_2;
- output drpclk_in_3;
- output drpclk_in_4;
- output [7:0]\left_align_select_r_reg[1]_0 ;
- output [7:0]\left_align_select_r_reg[1]_1 ;
- output \left_align_select_r_reg[1]_2 ;
- output \left_align_select_r_reg[1]_3 ;
- output hard_err_gt0;
- output tx_lock;
- output rxfsm_rxresetdone_r3_reg_0;
- output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- input quad1_common_lock_in;
- input drpclk_in;
- input RXN;
- input RXP;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- input ena_comma_align_i;
- input rx_polarity_i;
- input sync_clk;
- input user_clk;
- input POWER_DOWN;
- input [2:0]LOOPBACK;
- input [31:0]TXDATA;
- input [3:0]Q;
- input GTRXRESET_OUT;
- input init_clk_in;
- input link_reset_r;
- input [0:0]AR;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[0]_1 ;
- input \left_align_select_r_reg[1]_4 ;
- input tx_reset_i;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input [0:0]\word_aligned_control_bits_r_reg[2] ;
- input PLL_NOT_LOCKED;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- input DRPWE_IN;
- input DRPEN_IN;
-
- wire [0:0]AR;
- wire [3:0]D;
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN_IN;
- wire DRPWE_IN;
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire GTRXRESET_OUT;
- wire [2:0]LOOPBACK;
- wire PLL_NOT_LOCKED;
- wire POWER_DOWN;
- wire [3:0]Q;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire RXN;
- wire [1:0]RXNOTINTABLE;
- wire RXP;
- wire RX_RESETDONE_OUT;
- wire [31:0]TXDATA;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire TX_RESETDONE_OUT;
- wire drpclk_in;
- wire drpclk_in_0;
- wire drpclk_in_1;
- wire drpclk_in_2;
- wire drpclk_in_3;
- wire drpclk_in_4;
- wire ena_comma_align_i;
- wire gt0_rxresetdone_r3_reg_srl3_n_0;
- wire gt0_txresetdone_r3_reg_srl3_n_0;
- wire gt_common_reset_out;
- wire gt_rx_reset_i;
- wire gt_rxuserrdy_i;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire gtrxreset_i;
- wire gtrxreset_pulse;
- wire gtrxreset_pulse0;
- wire gtrxreset_r1;
- wire gtrxreset_r2;
- wire gtrxreset_r3;
- wire gtrxreset_sync;
- wire hard_err_gt0;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1] ;
- wire [7:0]\left_align_select_r_reg[1]_0 ;
- wire [7:0]\left_align_select_r_reg[1]_1 ;
- wire \left_align_select_r_reg[1]_2 ;
- wire \left_align_select_r_reg[1]_3 ;
- wire \left_align_select_r_reg[1]_4 ;
- wire link_reset_r;
- wire link_reset_r2;
- wire north_channel_multi_gt_i_n_4;
- wire north_channel_multi_gt_i_n_6;
- wire [10:0]p_0_in__2;
- wire quad1_common_lock_in;
- wire rst_r_reg;
- wire rx_cdrlock_counter;
- wire \rx_cdrlock_counter[10]_i_4_n_0 ;
- wire \rx_cdrlock_counter[10]_i_5_n_0 ;
- wire \rx_cdrlock_counter[10]_i_6_n_0 ;
- wire [10:0]rx_cdrlock_counter_reg;
- wire rx_cdrlocked;
- wire rx_cdrlocked_i_1_n_0;
- wire rx_cdrlocked_reg_n_0;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire rxfsm_rxresetdone_r;
- wire rxfsm_rxresetdone_r2;
- wire rxfsm_rxresetdone_r3_reg_0;
- wire rxfsm_soft_reset_r;
- wire rxfsm_soft_reset_r_i_1_n_0;
- wire sync_clk;
- wire tx_lock;
- wire tx_reset_i;
- wire txfsm_txresetdone_r;
- wire user_clk;
- wire [0:0]\word_aligned_control_bits_r_reg[2] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
-
- (* srl_name = "U0/\gt_wrapper_i/gt0_rxresetdone_r3_reg_srl3 " *)
- SRL16E gt0_rxresetdone_r3_reg_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(north_channel_multi_gt_i_n_4),
- .Q(gt0_rxresetdone_r3_reg_srl3_n_0));
- (* srl_name = "U0/\gt_wrapper_i/gt0_txresetdone_r3_reg_srl3 " *)
- SRL16E gt0_txresetdone_r3_reg_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(north_channel_multi_gt_i_n_6),
- .Q(gt0_txresetdone_r3_reg_srl3_n_0));
- (* equivalent_register_removal = "no" *)
- FDRE gt_rx_reset_i_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_i),
- .Q(gt_rx_reset_i),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gt_rxresetdone_r_i_1
- (.I0(RX_RESETDONE_OUT),
- .O(rxfsm_rxresetdone_r3_reg_0));
- north_channel_north_channel_rx_startup_fsm gt_rxresetfsm_i
- (.AR(rxfsm_soft_reset_r),
- .\FSM_sequential_rx_state_reg[0]_0 (rx_cdrlocked_reg_n_0),
- .gt_rxuserrdy_i(gt_rxuserrdy_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .gtrxreset_i(gtrxreset_i),
- .init_clk_in(init_clk_in),
- .quad1_common_lock_in(quad1_common_lock_in),
- .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
- .user_clk(user_clk));
- north_channel_north_channel_tx_startup_fsm gt_txresetfsm_i
- (.AR(AR),
- .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ),
- .PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_tx_reset_i(gt_tx_reset_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .init_clk_in(init_clk_in),
- .out(TX_RESETDONE_OUT),
- .quad1_common_lock_in(quad1_common_lock_in),
- .tx_lock(tx_lock),
- .txfsm_txresetdone_r(txfsm_txresetdone_r),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized6_5 gtrxreset_cdc_sync
- (.GTRXRESET_OUT(GTRXRESET_OUT),
- .init_clk_in(init_clk_in),
- .out(gtrxreset_sync),
- .user_clk(user_clk));
- LUT2 #(
- .INIT(4'h2))
- gtrxreset_pulse_i_1
- (.I0(gtrxreset_r2),
- .I1(gtrxreset_r3),
- .O(gtrxreset_pulse0));
- FDRE gtrxreset_pulse_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_pulse0),
- .Q(gtrxreset_pulse),
- .R(1'b0));
- FDRE gtrxreset_r1_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_sync),
- .Q(gtrxreset_r1),
- .R(1'b0));
- FDRE gtrxreset_r2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_r1),
- .Q(gtrxreset_r2),
- .R(1'b0));
- FDRE gtrxreset_r3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_r2),
- .Q(gtrxreset_r3),
- .R(1'b0));
- (* equivalent_register_removal = "no" *)
- FDRE link_reset_r2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_r),
- .Q(link_reset_r2),
- .R(1'b0));
- north_channel_north_channel_multi_gt north_channel_multi_gt_i
- (.D(D),
- .DRPADDR_IN(DRPADDR_IN),
- .DRPDI_IN(DRPDI_IN),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE_IN(DRPWE_IN),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .LOOPBACK(LOOPBACK),
- .POWER_DOWN(POWER_DOWN),
- .Q(Q),
- .RXCHARISK(RXCHARISK),
- .RXDATA(RXDATA),
- .RXDISPERR(RXDISPERR),
- .RXN(RXN),
- .RXNOTINTABLE(RXNOTINTABLE),
- .RXP(RXP),
- .SR(gt_rx_reset_i),
- .TXDATA(TXDATA),
- .TXN(TXN),
- .TXP(TXP),
- .TX_OUT_CLK(TX_OUT_CLK),
- .drpclk_in(drpclk_in),
- .drpclk_in_0(drpclk_in_0),
- .drpclk_in_1(north_channel_multi_gt_i_n_4),
- .drpclk_in_2(north_channel_multi_gt_i_n_6),
- .drpclk_in_3(drpclk_in_1),
- .drpclk_in_4(drpclk_in_2),
- .drpclk_in_5(drpclk_in_3),
- .drpclk_in_6(drpclk_in_4),
- .ena_comma_align_i(ena_comma_align_i),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_rxuserrdy_i(gt_rxuserrdy_i),
- .gt_tx_reset_i(gt_tx_reset_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .hard_err_gt0(hard_err_gt0),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (\left_align_select_r_reg[0] ),
- .\left_align_select_r_reg[0]_0 (\left_align_select_r_reg[0]_0 ),
- .\left_align_select_r_reg[0]_1 (\left_align_select_r_reg[0]_1 ),
- .\left_align_select_r_reg[1] (\left_align_select_r_reg[1] ),
- .\left_align_select_r_reg[1]_0 (\left_align_select_r_reg[1]_0 ),
- .\left_align_select_r_reg[1]_1 (\left_align_select_r_reg[1]_1 ),
- .\left_align_select_r_reg[1]_2 (\left_align_select_r_reg[1]_2 ),
- .\left_align_select_r_reg[1]_3 (\left_align_select_r_reg[1]_3 ),
- .\left_align_select_r_reg[1]_4 (\left_align_select_r_reg[1]_4 ),
- .rst_r_reg(rst_r_reg),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .sync_clk(sync_clk),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (\word_aligned_control_bits_r_reg[2] ),
- .\word_aligned_data_r_reg[16] (\word_aligned_data_r_reg[16] ));
- LUT1 #(
- .INIT(2'h1))
- \rx_cdrlock_counter[0]_i_1
- (.I0(rx_cdrlock_counter_reg[0]),
- .O(p_0_in__2[0]));
- LUT1 #(
- .INIT(2'h1))
- \rx_cdrlock_counter[10]_i_1
- (.I0(rx_cdrlocked),
- .O(rx_cdrlock_counter));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \rx_cdrlock_counter[10]_i_2
- (.I0(rx_cdrlock_counter_reg[10]),
- .I1(rx_cdrlock_counter_reg[6]),
- .I2(rx_cdrlock_counter_reg[7]),
- .I3(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .I4(rx_cdrlock_counter_reg[8]),
- .I5(rx_cdrlock_counter_reg[9]),
- .O(p_0_in__2[10]));
- LUT5 #(
- .INIT(32'h00000004))
- \rx_cdrlock_counter[10]_i_3
- (.I0(rx_cdrlock_counter_reg[2]),
- .I1(rx_cdrlock_counter_reg[10]),
- .I2(rx_cdrlock_counter_reg[8]),
- .I3(\rx_cdrlock_counter[10]_i_5_n_0 ),
- .I4(\rx_cdrlock_counter[10]_i_6_n_0 ),
- .O(rx_cdrlocked));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_cdrlock_counter[10]_i_4
- (.I0(rx_cdrlock_counter_reg[5]),
- .I1(rx_cdrlock_counter_reg[2]),
- .I2(rx_cdrlock_counter_reg[0]),
- .I3(rx_cdrlock_counter_reg[1]),
- .I4(rx_cdrlock_counter_reg[3]),
- .I5(rx_cdrlock_counter_reg[4]),
- .O(\rx_cdrlock_counter[10]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT4 #(
- .INIT(16'hFF7F))
- \rx_cdrlock_counter[10]_i_5
- (.I0(rx_cdrlock_counter_reg[7]),
- .I1(rx_cdrlock_counter_reg[6]),
- .I2(rx_cdrlock_counter_reg[1]),
- .I3(rx_cdrlock_counter_reg[0]),
- .O(\rx_cdrlock_counter[10]_i_5_n_0 ));
- LUT4 #(
- .INIT(16'hFFFD))
- \rx_cdrlock_counter[10]_i_6
- (.I0(rx_cdrlock_counter_reg[5]),
- .I1(rx_cdrlock_counter_reg[4]),
- .I2(rx_cdrlock_counter_reg[9]),
- .I3(rx_cdrlock_counter_reg[3]),
- .O(\rx_cdrlock_counter[10]_i_6_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT2 #(
- .INIT(4'h6))
- \rx_cdrlock_counter[1]_i_1
- (.I0(rx_cdrlock_counter_reg[0]),
- .I1(rx_cdrlock_counter_reg[1]),
- .O(p_0_in__2[1]));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT3 #(
- .INIT(8'h6A))
- \rx_cdrlock_counter[2]_i_1
- (.I0(rx_cdrlock_counter_reg[2]),
- .I1(rx_cdrlock_counter_reg[0]),
- .I2(rx_cdrlock_counter_reg[1]),
- .O(p_0_in__2[2]));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \rx_cdrlock_counter[3]_i_1
- (.I0(rx_cdrlock_counter_reg[3]),
- .I1(rx_cdrlock_counter_reg[1]),
- .I2(rx_cdrlock_counter_reg[0]),
- .I3(rx_cdrlock_counter_reg[2]),
- .O(p_0_in__2[3]));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \rx_cdrlock_counter[4]_i_1
- (.I0(rx_cdrlock_counter_reg[2]),
- .I1(rx_cdrlock_counter_reg[0]),
- .I2(rx_cdrlock_counter_reg[1]),
- .I3(rx_cdrlock_counter_reg[3]),
- .I4(rx_cdrlock_counter_reg[4]),
- .O(p_0_in__2[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \rx_cdrlock_counter[5]_i_1
- (.I0(rx_cdrlock_counter_reg[5]),
- .I1(rx_cdrlock_counter_reg[2]),
- .I2(rx_cdrlock_counter_reg[0]),
- .I3(rx_cdrlock_counter_reg[1]),
- .I4(rx_cdrlock_counter_reg[3]),
- .I5(rx_cdrlock_counter_reg[4]),
- .O(p_0_in__2[5]));
- LUT2 #(
- .INIT(4'h6))
- \rx_cdrlock_counter[6]_i_1
- (.I0(rx_cdrlock_counter_reg[6]),
- .I1(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .O(p_0_in__2[6]));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT3 #(
- .INIT(8'h6A))
- \rx_cdrlock_counter[7]_i_1
- (.I0(rx_cdrlock_counter_reg[7]),
- .I1(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .I2(rx_cdrlock_counter_reg[6]),
- .O(p_0_in__2[7]));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \rx_cdrlock_counter[8]_i_1
- (.I0(rx_cdrlock_counter_reg[8]),
- .I1(rx_cdrlock_counter_reg[6]),
- .I2(rx_cdrlock_counter_reg[7]),
- .I3(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .O(p_0_in__2[8]));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \rx_cdrlock_counter[9]_i_1
- (.I0(rx_cdrlock_counter_reg[9]),
- .I1(rx_cdrlock_counter_reg[8]),
- .I2(\rx_cdrlock_counter[10]_i_4_n_0 ),
- .I3(rx_cdrlock_counter_reg[7]),
- .I4(rx_cdrlock_counter_reg[6]),
- .O(p_0_in__2[9]));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[0]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[0]),
- .Q(rx_cdrlock_counter_reg[0]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[10]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[10]),
- .Q(rx_cdrlock_counter_reg[10]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[1]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[1]),
- .Q(rx_cdrlock_counter_reg[1]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[2]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[2]),
- .Q(rx_cdrlock_counter_reg[2]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[3]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[3]),
- .Q(rx_cdrlock_counter_reg[3]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[4]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[4]),
- .Q(rx_cdrlock_counter_reg[4]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[5]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[5]),
- .Q(rx_cdrlock_counter_reg[5]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[6]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[6]),
- .Q(rx_cdrlock_counter_reg[6]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[7]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[7]),
- .Q(rx_cdrlock_counter_reg[7]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[8]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[8]),
- .Q(rx_cdrlock_counter_reg[8]),
- .R(gt_rx_reset_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cdrlock_counter_reg[9]
- (.C(init_clk_in),
- .CE(rx_cdrlock_counter),
- .D(p_0_in__2[9]),
- .Q(rx_cdrlock_counter_reg[9]),
- .R(gt_rx_reset_i));
- LUT3 #(
- .INIT(8'h0E))
- rx_cdrlocked_i_1
- (.I0(rx_cdrlocked_reg_n_0),
- .I1(rx_cdrlocked),
- .I2(gt_rx_reset_i),
- .O(rx_cdrlocked_i_1_n_0));
- FDRE rx_cdrlocked_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rx_cdrlocked_i_1_n_0),
- .Q(rx_cdrlocked_reg_n_0),
- .R(1'b0));
- (* equivalent_register_removal = "no" *)
- FDRE rxfsm_rxresetdone_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxfsm_rxresetdone_r),
- .Q(rxfsm_rxresetdone_r2),
- .R(1'b0));
- FDRE rxfsm_rxresetdone_r3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxfsm_rxresetdone_r2),
- .Q(RX_RESETDONE_OUT),
- .R(1'b0));
- FDRE rxfsm_rxresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt0_rxresetdone_r3_reg_srl3_n_0),
- .Q(rxfsm_rxresetdone_r),
- .R(1'b0));
- LUT3 #(
- .INIT(8'hFE))
- rxfsm_soft_reset_r_i_1
- (.I0(link_reset_r2),
- .I1(gtrxreset_pulse),
- .I2(AR),
- .O(rxfsm_soft_reset_r_i_1_n_0));
- FDRE rxfsm_soft_reset_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rxfsm_soft_reset_r_i_1_n_0),
- .Q(rxfsm_soft_reset_r),
- .R(1'b0));
- FDRE txfsm_txresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt0_txresetdone_r3_reg_srl3_n_0),
- .Q(txfsm_txresetdone_r),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_HOTPLUG" *)
-module north_channel_north_channel_HOTPLUG
- (LINK_RESET_OUT,
- user_clk,
- init_clk_in,
- HPCNT_RESET,
- reset_lanes_i,
- D);
- output LINK_RESET_OUT;
- input user_clk;
- input init_clk_in;
- input HPCNT_RESET;
- input reset_lanes_i;
- input [0:0]D;
-
- wire [0:0]D;
- wire HPCNT_RESET;
- wire LINK_RESET_OUT;
- wire [21:0]\hotplug_count_synth.count_for_reset_r_reg ;
- wire init_clk_in;
- wire link_reset_0;
- wire link_reset_r;
- wire link_reset_r_i_2_n_0;
- wire link_reset_r_i_3_n_0;
- wire link_reset_r_i_4_n_0;
- wire link_reset_r_i_5_n_0;
- wire link_reset_r_i_6_n_0;
- wire p_0_in;
- wire reset_lanes_i;
- wire rx_cc_cdc_sync_n_0;
- wire rx_cc_cdc_sync_n_1;
- wire rx_cc_cdc_sync_n_10;
- wire rx_cc_cdc_sync_n_11;
- wire rx_cc_cdc_sync_n_12;
- wire rx_cc_cdc_sync_n_13;
- wire rx_cc_cdc_sync_n_14;
- wire rx_cc_cdc_sync_n_15;
- wire rx_cc_cdc_sync_n_16;
- wire rx_cc_cdc_sync_n_17;
- wire rx_cc_cdc_sync_n_18;
- wire rx_cc_cdc_sync_n_19;
- wire rx_cc_cdc_sync_n_2;
- wire rx_cc_cdc_sync_n_20;
- wire rx_cc_cdc_sync_n_21;
- wire rx_cc_cdc_sync_n_3;
- wire rx_cc_cdc_sync_n_4;
- wire rx_cc_cdc_sync_n_5;
- wire rx_cc_cdc_sync_n_6;
- wire rx_cc_cdc_sync_n_7;
- wire rx_cc_cdc_sync_n_8;
- wire rx_cc_cdc_sync_n_9;
- wire [7:0]rx_cc_extend_r;
- wire rx_cc_extend_r2;
- wire rx_cc_extend_r2_i_2_n_0;
- wire user_clk;
-
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[0]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_3),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [0]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[10]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_9),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [10]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[11]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_8),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [11]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[12]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_15),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [12]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[13]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_14),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [13]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[14]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_13),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [14]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[15]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_12),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [15]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[16]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_19),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [16]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[17]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_18),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [17]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[18]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_17),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [18]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[19]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_16),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [19]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[1]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_2),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [1]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[20]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_21),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [20]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[21]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_20),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [21]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[2]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_1),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [2]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[3]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_0),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [3]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[4]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_7),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [4]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[5]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_6),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [5]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[6]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_5),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [6]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[7]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_4),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [7]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[8]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_11),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [8]));
- FDCE #(
- .INIT(1'b0))
- \hotplug_count_synth.count_for_reset_r_reg[9]
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(HPCNT_RESET),
- .D(rx_cc_cdc_sync_n_10),
- .Q(\hotplug_count_synth.count_for_reset_r_reg [9]));
- FDRE #(
- .INIT(1'b0))
- \hotplug_enable.LINK_RESET_OUT_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_r),
- .Q(LINK_RESET_OUT),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0222222222222222))
- link_reset_r_i_1
- (.I0(link_reset_r_i_2_n_0),
- .I1(link_reset_r_i_3_n_0),
- .I2(link_reset_r_i_4_n_0),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [4]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [1]),
- .I5(\hotplug_count_synth.count_for_reset_r_reg [0]),
- .O(link_reset_0));
- LUT6 #(
- .INIT(64'h0000000040000000))
- link_reset_r_i_2
- (.I0(link_reset_r_i_5_n_0),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [12]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [19]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [9]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [16]),
- .I5(link_reset_r_i_6_n_0),
- .O(link_reset_r_i_2_n_0));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- link_reset_r_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [15]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [13]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [10]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [11]),
- .I5(\hotplug_count_synth.count_for_reset_r_reg [7]),
- .O(link_reset_r_i_3_n_0));
- LUT2 #(
- .INIT(4'h8))
- link_reset_r_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [2]),
- .O(link_reset_r_i_4_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- link_reset_r_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [14]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [18]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [21]),
- .O(link_reset_r_i_5_n_0));
- LUT6 #(
- .INIT(64'h07FFFFFFFFFFFFFF))
- link_reset_r_i_6
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
- .I1(\hotplug_count_synth.count_for_reset_r_reg [2]),
- .I2(\hotplug_count_synth.count_for_reset_r_reg [4]),
- .I3(\hotplug_count_synth.count_for_reset_r_reg [20]),
- .I4(\hotplug_count_synth.count_for_reset_r_reg [5]),
- .I5(\hotplug_count_synth.count_for_reset_r_reg [17]),
- .O(link_reset_r_i_6_n_0));
- FDRE link_reset_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_0),
- .Q(link_reset_r),
- .R(1'b0));
- north_channel_north_channel_cdc_sync__parameterized6 rx_cc_cdc_sync
- (.O({rx_cc_cdc_sync_n_0,rx_cc_cdc_sync_n_1,rx_cc_cdc_sync_n_2,rx_cc_cdc_sync_n_3}),
- .\hotplug_count_synth.count_for_reset_r_reg (\hotplug_count_synth.count_for_reset_r_reg ),
- .\hotplug_count_synth.count_for_reset_r_reg[11] ({rx_cc_cdc_sync_n_8,rx_cc_cdc_sync_n_9,rx_cc_cdc_sync_n_10,rx_cc_cdc_sync_n_11}),
- .\hotplug_count_synth.count_for_reset_r_reg[15] ({rx_cc_cdc_sync_n_12,rx_cc_cdc_sync_n_13,rx_cc_cdc_sync_n_14,rx_cc_cdc_sync_n_15}),
- .\hotplug_count_synth.count_for_reset_r_reg[19] ({rx_cc_cdc_sync_n_16,rx_cc_cdc_sync_n_17,rx_cc_cdc_sync_n_18,rx_cc_cdc_sync_n_19}),
- .\hotplug_count_synth.count_for_reset_r_reg[21] ({rx_cc_cdc_sync_n_20,rx_cc_cdc_sync_n_21}),
- .\hotplug_count_synth.count_for_reset_r_reg[7] ({rx_cc_cdc_sync_n_4,rx_cc_cdc_sync_n_5,rx_cc_cdc_sync_n_6,rx_cc_cdc_sync_n_7}),
- .init_clk_in(init_clk_in),
- .rx_cc_extend_r2(rx_cc_extend_r2),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- rx_cc_extend_r2_i_1
- (.I0(rx_cc_extend_r[2]),
- .I1(rx_cc_extend_r[3]),
- .I2(rx_cc_extend_r[0]),
- .I3(rx_cc_extend_r[1]),
- .I4(rx_cc_extend_r2_i_2_n_0),
- .O(p_0_in));
- LUT4 #(
- .INIT(16'hFFFE))
- rx_cc_extend_r2_i_2
- (.I0(rx_cc_extend_r[5]),
- .I1(rx_cc_extend_r[4]),
- .I2(rx_cc_extend_r[7]),
- .I3(rx_cc_extend_r[6]),
- .O(rx_cc_extend_r2_i_2_n_0));
- FDRE rx_cc_extend_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in),
- .Q(rx_cc_extend_r2),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[1]),
- .Q(rx_cc_extend_r[0]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[2]),
- .Q(rx_cc_extend_r[1]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[3]),
- .Q(rx_cc_extend_r[2]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[4]),
- .Q(rx_cc_extend_r[3]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[5]),
- .Q(rx_cc_extend_r[4]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[6]),
- .Q(rx_cc_extend_r[5]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r[7]),
- .Q(rx_cc_extend_r[6]),
- .R(reset_lanes_i));
- FDRE #(
- .INIT(1'b0))
- \rx_cc_extend_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(rx_cc_extend_r[7]),
- .R(reset_lanes_i));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_IDLE_AND_VER_GEN" *)
-module north_channel_north_channel_IDLE_AND_VER_GEN
- (gen_v_flop_1_i_0,
- GEN_A,
- gen_k_flop_0_i_0,
- gen_r_flop_0_i_0,
- DID_VER_Buffer_reg_0,
- user_clk,
- gen_ver_i,
- \downcounter_r_reg[2]_0 );
- output [2:0]gen_v_flop_1_i_0;
- output GEN_A;
- output [3:0]gen_k_flop_0_i_0;
- output [3:0]gen_r_flop_0_i_0;
- output DID_VER_Buffer_reg_0;
- input user_clk;
- input gen_ver_i;
- input \downcounter_r_reg[2]_0 ;
-
- wire D;
- wire D0_in;
- wire D0_out;
- wire D1_in;
- wire D1_out;
- wire D2_out;
- wire DID_VER_Buffer_reg_0;
- wire GEN_A;
- wire did_ver_i;
- wire [0:2]down_count_r;
- wire \down_count_r[0]_i_1_n_0 ;
- wire \down_count_r[1]_i_1_n_0 ;
- wire \downcounter_r[0]_i_1_n_0 ;
- wire \downcounter_r[1]_i_1_n_0 ;
- wire \downcounter_r[2]_i_1_n_0 ;
- wire \downcounter_r_reg[2]_0 ;
- wire \downcounter_r_reg_n_0_[0] ;
- wire \downcounter_r_reg_n_0_[1] ;
- wire \downcounter_r_reg_n_0_[2] ;
- wire [3:0]gen_k_flop_0_i_0;
- wire gen_k_flop_1_i_i_1_n_0;
- wire gen_k_flop_2_i_i_1_n_0;
- wire gen_k_flop_3_i_i_1_n_0;
- wire [3:0]gen_r_flop_0_i_0;
- wire gen_r_flop_0_i_i_1_n_0;
- wire [2:0]gen_v_flop_1_i_0;
- wire gen_ver_i;
- wire \lfsr_reg_reg_n_0_[3] ;
- wire p_1_in;
- wire [0:0]p_4_out;
- wire prev_cycle_gen_ver_r;
- wire user_clk;
- wire ver_counter_c;
-
- FDRE DID_VER_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ver_counter_c),
- .Q(did_ver_i),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair184" *)
- LUT2 #(
- .INIT(4'hE))
- \down_count_r[0]_i_1
- (.I0(\lfsr_reg_reg_n_0_[3] ),
- .I1(D0_in),
- .O(\down_count_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair186" *)
- LUT2 #(
- .INIT(4'h9))
- \down_count_r[1]_i_1
- (.I0(\lfsr_reg_reg_n_0_[3] ),
- .I1(D0_in),
- .O(\down_count_r[1]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \down_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\down_count_r[0]_i_1_n_0 ),
- .Q(down_count_r[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \down_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\down_count_r[1]_i_1_n_0 ),
- .Q(down_count_r[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \down_count_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_3_i_i_1_n_0),
- .Q(down_count_r[2]),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hE1E0))
- \downcounter_r[0]_i_1
- (.I0(\downcounter_r_reg_n_0_[1] ),
- .I1(\downcounter_r_reg_n_0_[2] ),
- .I2(\downcounter_r_reg_n_0_[0] ),
- .I3(down_count_r[0]),
- .O(\downcounter_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair183" *)
- LUT4 #(
- .INIT(16'hF00E))
- \downcounter_r[1]_i_1
- (.I0(down_count_r[1]),
- .I1(\downcounter_r_reg_n_0_[0] ),
- .I2(\downcounter_r_reg_n_0_[1] ),
- .I3(\downcounter_r_reg_n_0_[2] ),
- .O(\downcounter_r[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair183" *)
- LUT4 #(
- .INIT(16'h0F0E))
- \downcounter_r[2]_i_1
- (.I0(down_count_r[2]),
- .I1(\downcounter_r_reg_n_0_[0] ),
- .I2(\downcounter_r_reg_n_0_[2] ),
- .I3(\downcounter_r_reg_n_0_[1] ),
- .O(\downcounter_r[2]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \downcounter_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\downcounter_r[0]_i_1_n_0 ),
- .Q(\downcounter_r_reg_n_0_[0] ),
- .R(\downcounter_r_reg[2]_0 ));
- FDRE #(
- .INIT(1'b0))
- \downcounter_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\downcounter_r[1]_i_1_n_0 ),
- .Q(\downcounter_r_reg_n_0_[1] ),
- .R(\downcounter_r_reg[2]_0 ));
- FDRE #(
- .INIT(1'b0))
- \downcounter_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\downcounter_r[2]_i_1_n_0 ),
- .Q(\downcounter_r_reg_n_0_[2] ),
- .R(\downcounter_r_reg[2]_0 ));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_a_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D1_out),
- .Q(GEN_A),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair182" *)
- LUT5 #(
- .INIT(32'h00000007))
- gen_a_flop_0_i_i_1
- (.I0(did_ver_i),
- .I1(gen_ver_i),
- .I2(\downcounter_r_reg_n_0_[0] ),
- .I3(\downcounter_r_reg_n_0_[2] ),
- .I4(\downcounter_r_reg_n_0_[1] ),
- .O(D1_out));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D2_out),
- .Q(gen_k_flop_0_i_0[3]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hFFFF555455545554))
- gen_k_flop_0_i_i_1
- (.I0(p_1_in),
- .I1(\downcounter_r_reg_n_0_[1] ),
- .I2(\downcounter_r_reg_n_0_[2] ),
- .I3(\downcounter_r_reg_n_0_[0] ),
- .I4(did_ver_i),
- .I5(gen_ver_i),
- .O(D2_out));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_1_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_1_i_i_1_n_0),
- .Q(gen_k_flop_0_i_0[2]),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gen_k_flop_1_i_i_1
- (.I0(D1_in),
- .O(gen_k_flop_1_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_2_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_2_i_i_1_n_0),
- .Q(gen_k_flop_0_i_0[1]),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gen_k_flop_2_i_i_1
- (.I0(D0_in),
- .O(gen_k_flop_2_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_k_flop_3_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_k_flop_3_i_i_1_n_0),
- .Q(gen_k_flop_0_i_0[0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair186" *)
- LUT1 #(
- .INIT(2'h1))
- gen_k_flop_3_i_i_1
- (.I0(\lfsr_reg_reg_n_0_[3] ),
- .O(gen_k_flop_3_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_r_flop_0_i_i_1_n_0),
- .Q(gen_r_flop_0_i_0[3]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h2A2A2A2A2A2A2A00))
- gen_r_flop_0_i_i_1
- (.I0(p_1_in),
- .I1(gen_ver_i),
- .I2(did_ver_i),
- .I3(\downcounter_r_reg_n_0_[0] ),
- .I4(\downcounter_r_reg_n_0_[2] ),
- .I5(\downcounter_r_reg_n_0_[1] ),
- .O(gen_r_flop_0_i_i_1_n_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_1_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D1_in),
- .Q(gen_r_flop_0_i_0[2]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_2_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_in),
- .Q(gen_r_flop_0_i_0[1]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_r_flop_3_i
- (.C(user_clk),
- .CE(1'b1),
- .D(\lfsr_reg_reg_n_0_[3] ),
- .Q(gen_r_flop_0_i_0[0]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_v_flop_1_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_out),
- .Q(gen_v_flop_1_i_0[2]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair185" *)
- LUT2 #(
- .INIT(4'h8))
- gen_v_flop_1_i_i_1
- (.I0(did_ver_i),
- .I1(gen_ver_i),
- .O(D0_out));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_v_flop_2_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_out),
- .Q(gen_v_flop_1_i_0[1]),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FD" *)
- FDRE #(
- .INIT(1'b0))
- gen_v_flop_3_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_out),
- .Q(gen_v_flop_1_i_0[0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair184" *)
- LUT4 #(
- .INIT(16'h0EF1))
- \lfsr_reg[3]_i_1
- (.I0(D0_in),
- .I1(D1_in),
- .I2(\lfsr_reg_reg_n_0_[3] ),
- .I3(p_1_in),
- .O(p_4_out));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D1_in),
- .Q(p_1_in),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D0_in),
- .Q(D1_in),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\lfsr_reg_reg_n_0_[3] ),
- .Q(D0_in),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \lfsr_reg_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_4_out),
- .Q(\lfsr_reg_reg_n_0_[3] ),
- .R(1'b0));
- FDRE prev_cycle_gen_ver_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_ver_i),
- .Q(prev_cycle_gen_ver_r),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair182" *)
- LUT2 #(
- .INIT(4'hB))
- \txver_count_r_reg[6]_srl7_i_1
- (.I0(did_ver_i),
- .I1(gen_ver_i),
- .O(DID_VER_Buffer_reg_0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "SRL16" *)
- (* srl_name = "U0/\north_channel_global_logic_i/idle_and_ver_gen_i/ver_counter_i " *)
- SRL16E #(
- .INIT(16'h0000))
- ver_counter_i
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(D),
- .Q(ver_counter_c));
- (* SOFT_HLUTNM = "soft_lutpair185" *)
- LUT3 #(
- .INIT(8'hD0))
- ver_counter_i_i_1
- (.I0(prev_cycle_gen_ver_r),
- .I1(did_ver_i),
- .I2(gen_ver_i),
- .O(D));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_LANE_INIT_SM_4BYTE" *)
-module north_channel_north_channel_LANE_INIT_SM_4BYTE
- (LANE_UP,
- D,
- align_r_reg_0,
- gen_spa_i,
- rst_r_reg_0,
- enable_err_detect_i,
- rx_polarity_i,
- GEN_SP,
- good_cnt_r3,
- ready_r_reg_0,
- reset_lanes_i,
- user_clk,
- begin_r0,
- counter4_r0,
- gen_spa_r,
- \counter3_r_reg[3]_0 ,
- rx_realign_i,
- rx_neg_i,
- RXNOTINTABLE,
- RXDISPERR,
- reset_count_r_reg_0,
- first_v_received_r,
- \RX_CHAR_IS_COMMA_R_reg[3]_0 );
- output LANE_UP;
- output D;
- output align_r_reg_0;
- output gen_spa_i;
- output rst_r_reg_0;
- output enable_err_detect_i;
- output rx_polarity_i;
- output GEN_SP;
- output good_cnt_r3;
- output ready_r_reg_0;
- input reset_lanes_i;
- input user_clk;
- input begin_r0;
- input counter4_r0;
- input gen_spa_r;
- input \counter3_r_reg[3]_0 ;
- input rx_realign_i;
- input rx_neg_i;
- input [1:0]RXNOTINTABLE;
- input [1:0]RXDISPERR;
- input reset_count_r_reg_0;
- input first_v_received_r;
- input [3:0]\RX_CHAR_IS_COMMA_R_reg[3]_0 ;
-
- wire D;
- wire ENABLE_ERR_DETECT_Buffer0;
- wire GEN_SP;
- wire LANE_UP;
- wire [1:0]RXDISPERR;
- wire [1:0]RXNOTINTABLE;
- wire [3:0]\RX_CHAR_IS_COMMA_R_reg[3]_0 ;
- wire \RX_CHAR_IS_COMMA_R_reg_n_0_[0] ;
- wire \RX_CHAR_IS_COMMA_R_reg_n_0_[3] ;
- wire align_r_reg_0;
- wire begin_r;
- wire begin_r0;
- wire begin_r_i_2_n_0;
- wire consecutive_commas_r;
- wire consecutive_commas_r0;
- wire count_128d_done_r;
- wire count_32d_done_r;
- wire count_8d_done_r;
- wire counter1_r0;
- wire \counter1_r[0]_i_3_n_0 ;
- wire \counter1_r_reg_n_0_[1] ;
- wire \counter1_r_reg_n_0_[3] ;
- wire \counter1_r_reg_n_0_[5] ;
- wire \counter1_r_reg_n_0_[6] ;
- wire \counter1_r_reg_n_0_[7] ;
- wire \counter2_r_reg[14]_srl14_n_0 ;
- wire \counter2_r_reg_n_0_[15] ;
- wire \counter3_r_reg[2]_srl3_n_0 ;
- wire \counter3_r_reg[3]_0 ;
- wire \counter3_r_reg_n_0_[3] ;
- wire counter4_r0;
- wire \counter4_r_reg[14]_srl15_n_0 ;
- wire \counter4_r_reg_n_0_[15] ;
- wire \counter5_r_reg[14]_srl15_i_1_n_0 ;
- wire \counter5_r_reg[14]_srl15_n_0 ;
- wire \counter5_r_reg_n_0_[15] ;
- wire do_watchdog_count_r;
- wire do_watchdog_count_r0;
- wire enable_err_detect_i;
- wire first_v_received_r;
- wire gen_spa_i;
- wire gen_spa_r;
- wire good_cnt_r3;
- wire next_ack_c;
- wire next_align_c;
- wire next_begin_c;
- wire next_polarity_c;
- wire next_ready_c;
- wire next_realign_c;
- wire next_rst_c;
- wire [7:0]p_0_in;
- wire p_0_in2_in;
- wire p_1_in;
- wire polarity_r;
- wire prev_count_128d_done_r;
- wire ready_r_reg_0;
- wire realign_r;
- wire reset_count_r;
- wire reset_count_r0;
- wire reset_count_r_i_2_n_0;
- wire reset_count_r_reg_0;
- wire reset_lanes_i;
- wire rst_r_reg_0;
- wire rx_neg_i;
- wire rx_polarity_i;
- wire rx_polarity_r_i_1_n_0;
- wire rx_realign_i;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'hE))
- ENABLE_ERR_DETECT_Buffer_i_1
- (.I0(gen_spa_i),
- .I1(D),
- .O(ENABLE_ERR_DETECT_Buffer0));
- FDRE ENABLE_ERR_DETECT_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ENABLE_ERR_DETECT_Buffer0),
- .Q(enable_err_detect_i),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [0]),
- .Q(\RX_CHAR_IS_COMMA_R_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [1]),
- .Q(p_1_in),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [2]),
- .Q(p_0_in2_in),
- .R(1'b0));
- FDRE \RX_CHAR_IS_COMMA_R_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_CHAR_IS_COMMA_R_reg[3]_0 [3]),
- .Q(\RX_CHAR_IS_COMMA_R_reg_n_0_[3] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h444444444FFF4444))
- ack_r_i_1
- (.I0(rx_neg_i),
- .I1(polarity_r),
- .I2(\counter2_r_reg_n_0_[15] ),
- .I3(\counter3_r_reg_n_0_[3] ),
- .I4(gen_spa_i),
- .I5(\counter5_r_reg_n_0_[15] ),
- .O(next_ack_c));
- FDRE ack_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ack_c),
- .Q(gen_spa_i),
- .R(begin_r0));
- (* SOFT_HLUTNM = "soft_lutpair84" *)
- LUT4 #(
- .INIT(16'h8F88))
- align_r_i_2
- (.I0(count_8d_done_r),
- .I1(rst_r_reg_0),
- .I2(count_128d_done_r),
- .I3(align_r_reg_0),
- .O(next_align_c));
- FDRE align_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_align_c),
- .Q(align_r_reg_0),
- .R(begin_r0));
- LUT3 #(
- .INIT(8'hF8))
- begin_r_i_1
- (.I0(polarity_r),
- .I1(rx_neg_i),
- .I2(begin_r_i_2_n_0),
- .O(next_begin_c));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- begin_r_i_2
- (.I0(\counter4_r_reg_n_0_[15] ),
- .I1(D),
- .I2(gen_spa_i),
- .I3(\counter5_r_reg_n_0_[15] ),
- .I4(rx_realign_i),
- .I5(realign_r),
- .O(begin_r_i_2_n_0));
- FDSE begin_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_begin_c),
- .Q(begin_r),
- .S(begin_r0));
- LUT5 #(
- .INIT(32'hFFFFFFEF))
- consecutive_commas_r_i_1
- (.I0(\RX_CHAR_IS_COMMA_R_reg_n_0_[0] ),
- .I1(\RX_CHAR_IS_COMMA_R_reg_n_0_[3] ),
- .I2(align_r_reg_0),
- .I3(p_0_in2_in),
- .I4(p_1_in),
- .O(consecutive_commas_r0));
- FDRE consecutive_commas_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(consecutive_commas_r0),
- .Q(consecutive_commas_r),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- \counter1_r[0]_i_1
- (.I0(reset_count_r),
- .I1(D),
- .O(counter1_r0));
- (* SOFT_HLUTNM = "soft_lutpair87" *)
- LUT3 #(
- .INIT(8'hD2))
- \counter1_r[0]_i_2
- (.I0(\counter1_r_reg_n_0_[1] ),
- .I1(\counter1_r[0]_i_3_n_0 ),
- .I2(count_128d_done_r),
- .O(p_0_in[7]));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- \counter1_r[0]_i_3
- (.I0(\counter1_r_reg_n_0_[3] ),
- .I1(\counter1_r_reg_n_0_[5] ),
- .I2(\counter1_r_reg_n_0_[7] ),
- .I3(\counter1_r_reg_n_0_[6] ),
- .I4(count_8d_done_r),
- .I5(count_32d_done_r),
- .O(\counter1_r[0]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair87" *)
- LUT2 #(
- .INIT(4'h9))
- \counter1_r[1]_i_1
- (.I0(\counter1_r[0]_i_3_n_0 ),
- .I1(\counter1_r_reg_n_0_[1] ),
- .O(p_0_in[6]));
- LUT6 #(
- .INIT(64'h7FFFFFFF80000000))
- \counter1_r[2]_i_1
- (.I0(\counter1_r_reg_n_0_[3] ),
- .I1(\counter1_r_reg_n_0_[5] ),
- .I2(\counter1_r_reg_n_0_[7] ),
- .I3(\counter1_r_reg_n_0_[6] ),
- .I4(count_8d_done_r),
- .I5(count_32d_done_r),
- .O(p_0_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair82" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \counter1_r[3]_i_1
- (.I0(count_8d_done_r),
- .I1(\counter1_r_reg_n_0_[6] ),
- .I2(\counter1_r_reg_n_0_[7] ),
- .I3(\counter1_r_reg_n_0_[5] ),
- .I4(\counter1_r_reg_n_0_[3] ),
- .O(p_0_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair82" *)
- LUT4 #(
- .INIT(16'h7F80))
- \counter1_r[4]_i_1
- (.I0(\counter1_r_reg_n_0_[5] ),
- .I1(\counter1_r_reg_n_0_[7] ),
- .I2(\counter1_r_reg_n_0_[6] ),
- .I3(count_8d_done_r),
- .O(p_0_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair86" *)
- LUT3 #(
- .INIT(8'h78))
- \counter1_r[5]_i_1
- (.I0(\counter1_r_reg_n_0_[6] ),
- .I1(\counter1_r_reg_n_0_[7] ),
- .I2(\counter1_r_reg_n_0_[5] ),
- .O(p_0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair86" *)
- LUT2 #(
- .INIT(4'h6))
- \counter1_r[6]_i_1
- (.I0(\counter1_r_reg_n_0_[7] ),
- .I1(\counter1_r_reg_n_0_[6] ),
- .O(p_0_in[1]));
- LUT1 #(
- .INIT(2'h1))
- \counter1_r[7]_i_1
- (.I0(\counter1_r_reg_n_0_[7] ),
- .O(p_0_in[0]));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[0]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[7]),
- .Q(count_128d_done_r),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[1]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[6]),
- .Q(\counter1_r_reg_n_0_[1] ),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[2]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[5]),
- .Q(count_32d_done_r),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[3]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[4]),
- .Q(\counter1_r_reg_n_0_[3] ),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[4]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[3]),
- .Q(count_8d_done_r),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[5]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[2]),
- .Q(\counter1_r_reg_n_0_[5] ),
- .R(counter1_r0));
- FDRE #(
- .INIT(1'b0))
- \counter1_r_reg[6]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[1]),
- .Q(\counter1_r_reg_n_0_[6] ),
- .R(counter1_r0));
- FDSE #(
- .INIT(1'b1))
- \counter1_r_reg[7]
- (.C(user_clk),
- .CE(consecutive_commas_r0),
- .D(p_0_in[0]),
- .Q(\counter1_r_reg_n_0_[7] ),
- .S(counter1_r0));
- (* srl_bus_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter2_r_reg " *)
- (* srl_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter2_r_reg[14]_srl14 " *)
- SRL16E \counter2_r_reg[14]_srl14
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b1),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(gen_spa_r),
- .Q(\counter2_r_reg[14]_srl14_n_0 ));
- FDRE \counter2_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\counter2_r_reg[14]_srl14_n_0 ),
- .Q(\counter2_r_reg_n_0_[15] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter3_r_reg " *)
- (* srl_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter3_r_reg[2]_srl3 " *)
- SRL16E \counter3_r_reg[2]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(\counter3_r_reg[3]_0 ),
- .CLK(user_clk),
- .D(gen_spa_i),
- .Q(\counter3_r_reg[2]_srl3_n_0 ));
- FDRE \counter3_r_reg[3]
- (.C(user_clk),
- .CE(\counter3_r_reg[3]_0 ),
- .D(\counter3_r_reg[2]_srl3_n_0 ),
- .Q(\counter3_r_reg_n_0_[3] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter4_r_reg " *)
- (* srl_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter4_r_reg[14]_srl15 " *)
- SRL16E \counter4_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(counter4_r0),
- .CLK(user_clk),
- .D(D),
- .Q(\counter4_r_reg[14]_srl15_n_0 ));
- FDRE \counter4_r_reg[15]
- (.C(user_clk),
- .CE(counter4_r0),
- .D(\counter4_r_reg[14]_srl15_n_0 ),
- .Q(\counter4_r_reg_n_0_[15] ),
- .R(1'b0));
- (* srl_bus_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter5_r_reg " *)
- (* srl_name = "U0/\north_channel_aurora_lane_4byte_0_i/north_channel_lane_init_sm_4byte_i/counter5_r_reg[14]_srl15 " *)
- SRL16E \counter5_r_reg[14]_srl15
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b1),
- .A3(1'b1),
- .CE(\counter5_r_reg[14]_srl15_i_1_n_0 ),
- .CLK(user_clk),
- .D(gen_spa_i),
- .Q(\counter5_r_reg[14]_srl15_n_0 ));
- LUT2 #(
- .INIT(4'hB))
- \counter5_r_reg[14]_srl15_i_1
- (.I0(do_watchdog_count_r),
- .I1(gen_spa_i),
- .O(\counter5_r_reg[14]_srl15_i_1_n_0 ));
- FDRE \counter5_r_reg[15]
- (.C(user_clk),
- .CE(\counter5_r_reg[14]_srl15_i_1_n_0 ),
- .D(\counter5_r_reg[14]_srl15_n_0 ),
- .Q(\counter5_r_reg_n_0_[15] ),
- .R(1'b0));
- LUT2 #(
- .INIT(4'h2))
- do_watchdog_count_r_i_1
- (.I0(count_128d_done_r),
- .I1(prev_count_128d_done_r),
- .O(do_watchdog_count_r0));
- FDRE do_watchdog_count_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(do_watchdog_count_r0),
- .Q(do_watchdog_count_r),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair85" *)
- LUT2 #(
- .INIT(4'h1))
- gen_sp_r_i_1
- (.I0(D),
- .I1(gen_spa_i),
- .O(GEN_SP));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FDR" *)
- FDRE #(
- .INIT(1'b0))
- lane_up_flop_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(LANE_UP),
- .R(reset_lanes_i));
- (* SOFT_HLUTNM = "soft_lutpair85" *)
- LUT3 #(
- .INIT(8'h0E))
- \left_align_select_r[0]_i_2
- (.I0(D),
- .I1(align_r_reg_0),
- .I2(first_v_received_r),
- .O(ready_r_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair83" *)
- LUT3 #(
- .INIT(8'h40))
- polarity_r_i_1
- (.I0(rx_realign_i),
- .I1(count_32d_done_r),
- .I2(realign_r),
- .O(next_polarity_c));
- FDRE polarity_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_polarity_c),
- .Q(polarity_r),
- .R(begin_r0));
- FDRE prev_count_128d_done_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(count_128d_done_r),
- .Q(prev_count_128d_done_r),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0080FFFF00800080))
- ready_r_i_1
- (.I0(\counter2_r_reg_n_0_[15] ),
- .I1(\counter3_r_reg_n_0_[3] ),
- .I2(gen_spa_i),
- .I3(\counter5_r_reg_n_0_[15] ),
- .I4(\counter4_r_reg_n_0_[15] ),
- .I5(D),
- .O(next_ready_c));
- FDRE ready_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ready_c),
- .Q(D),
- .R(begin_r0));
- (* SOFT_HLUTNM = "soft_lutpair83" *)
- LUT5 #(
- .INIT(32'hFF020202))
- realign_r_i_1
- (.I0(realign_r),
- .I1(rx_realign_i),
- .I2(count_32d_done_r),
- .I3(count_128d_done_r),
- .I4(align_r_reg_0),
- .O(next_realign_c));
- FDRE realign_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_realign_c),
- .Q(realign_r),
- .R(begin_r0));
- LUT6 #(
- .INIT(64'hFFAAFFAAFFFEFFFF))
- reset_count_r_i_1
- (.I0(reset_count_r_i_2_n_0),
- .I1(RXNOTINTABLE[1]),
- .I2(RXDISPERR[1]),
- .I3(reset_lanes_i),
- .I4(consecutive_commas_r),
- .I5(rst_r_reg_0),
- .O(reset_count_r0));
- LUT6 #(
- .INIT(64'hFFFFFFFF77763332))
- reset_count_r_i_2
- (.I0(begin_r),
- .I1(rst_r_reg_0),
- .I2(RXDISPERR[0]),
- .I3(RXNOTINTABLE[0]),
- .I4(count_8d_done_r),
- .I5(reset_count_r_reg_0),
- .O(reset_count_r_i_2_n_0));
- FDRE reset_count_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(reset_count_r0),
- .Q(reset_count_r),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair84" *)
- LUT3 #(
- .INIT(8'hF4))
- rst_r_i_1
- (.I0(count_8d_done_r),
- .I1(rst_r_reg_0),
- .I2(begin_r),
- .O(next_rst_c));
- FDRE rst_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_rst_c),
- .Q(rst_r_reg_0),
- .R(begin_r0));
- LUT3 #(
- .INIT(8'h78))
- rx_polarity_r_i_1
- (.I0(polarity_r),
- .I1(rx_neg_i),
- .I2(rx_polarity_i),
- .O(rx_polarity_r_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- rx_polarity_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_polarity_r_i_1_n_0),
- .Q(rx_polarity_i),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- \soft_err_r[0]_i_1
- (.I0(enable_err_detect_i),
- .O(good_cnt_r3));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_LEFT_ALIGN_CONTROL" *)
-module north_channel_north_channel_LEFT_ALIGN_CONTROL
- (MUX_SELECT,
- mux_select_c,
- user_clk);
- output [0:0]MUX_SELECT;
- input [0:0]mux_select_c;
- input user_clk;
-
- wire [0:0]MUX_SELECT;
- wire [0:0]mux_select_c;
- wire user_clk;
-
- FDRE \MUX_SELECT_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(mux_select_c),
- .Q(MUX_SELECT),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_LEFT_ALIGN_MUX" *)
-module north_channel_north_channel_LEFT_ALIGN_MUX
- (\MUXED_DATA_Buffer_reg[0]_0 ,
- D,
- Q,
- MUX_SELECT,
- user_clk,
- STORAGE_SELECT_Buffer);
- output [15:0]\MUXED_DATA_Buffer_reg[0]_0 ;
- output [31:0]D;
- input [31:0]Q;
- input [0:0]MUX_SELECT;
- input user_clk;
- input [1:0]STORAGE_SELECT_Buffer;
-
- wire [31:0]D;
- wire [16:31]MUXED_DATA_Buffer;
- wire [15:0]\MUXED_DATA_Buffer_reg[0]_0 ;
- wire [0:0]MUX_SELECT;
- wire [31:0]Q;
- wire [1:0]STORAGE_SELECT_Buffer;
- wire [0:15]muxed_data_c;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair207" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[0]_i_1
- (.I0(Q[15]),
- .I1(MUX_SELECT),
- .I2(Q[31]),
- .O(muxed_data_c[0]));
- (* SOFT_HLUTNM = "soft_lutpair202" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[10]_i_1
- (.I0(Q[5]),
- .I1(MUX_SELECT),
- .I2(Q[21]),
- .O(muxed_data_c[10]));
- (* SOFT_HLUTNM = "soft_lutpair202" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[11]_i_1
- (.I0(Q[4]),
- .I1(MUX_SELECT),
- .I2(Q[20]),
- .O(muxed_data_c[11]));
- (* SOFT_HLUTNM = "soft_lutpair201" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[12]_i_1
- (.I0(Q[3]),
- .I1(MUX_SELECT),
- .I2(Q[19]),
- .O(muxed_data_c[12]));
- (* SOFT_HLUTNM = "soft_lutpair201" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[13]_i_1
- (.I0(Q[2]),
- .I1(MUX_SELECT),
- .I2(Q[18]),
- .O(muxed_data_c[13]));
- (* SOFT_HLUTNM = "soft_lutpair200" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[14]_i_1
- (.I0(Q[1]),
- .I1(MUX_SELECT),
- .I2(Q[17]),
- .O(muxed_data_c[14]));
- (* SOFT_HLUTNM = "soft_lutpair200" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[15]_i_1
- (.I0(Q[0]),
- .I1(MUX_SELECT),
- .I2(Q[16]),
- .O(muxed_data_c[15]));
- (* SOFT_HLUTNM = "soft_lutpair207" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[1]_i_1
- (.I0(Q[14]),
- .I1(MUX_SELECT),
- .I2(Q[30]),
- .O(muxed_data_c[1]));
- (* SOFT_HLUTNM = "soft_lutpair206" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[2]_i_1
- (.I0(Q[13]),
- .I1(MUX_SELECT),
- .I2(Q[29]),
- .O(muxed_data_c[2]));
- (* SOFT_HLUTNM = "soft_lutpair206" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[3]_i_1
- (.I0(Q[12]),
- .I1(MUX_SELECT),
- .I2(Q[28]),
- .O(muxed_data_c[3]));
- (* SOFT_HLUTNM = "soft_lutpair205" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[4]_i_1
- (.I0(Q[11]),
- .I1(MUX_SELECT),
- .I2(Q[27]),
- .O(muxed_data_c[4]));
- (* SOFT_HLUTNM = "soft_lutpair205" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[5]_i_1
- (.I0(Q[10]),
- .I1(MUX_SELECT),
- .I2(Q[26]),
- .O(muxed_data_c[5]));
- (* SOFT_HLUTNM = "soft_lutpair204" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[6]_i_1
- (.I0(Q[9]),
- .I1(MUX_SELECT),
- .I2(Q[25]),
- .O(muxed_data_c[6]));
- (* SOFT_HLUTNM = "soft_lutpair204" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[7]_i_1
- (.I0(Q[8]),
- .I1(MUX_SELECT),
- .I2(Q[24]),
- .O(muxed_data_c[7]));
- (* SOFT_HLUTNM = "soft_lutpair203" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[8]_i_1
- (.I0(Q[7]),
- .I1(MUX_SELECT),
- .I2(Q[23]),
- .O(muxed_data_c[8]));
- (* SOFT_HLUTNM = "soft_lutpair203" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[9]_i_1
- (.I0(Q[6]),
- .I1(MUX_SELECT),
- .I2(Q[22]),
- .O(muxed_data_c[9]));
- FDRE \MUXED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[0]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [15]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[10]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [5]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[11]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [4]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[12]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [3]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[13]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [2]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[14]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[15]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[15]),
- .Q(MUXED_DATA_Buffer[16]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[14]),
- .Q(MUXED_DATA_Buffer[17]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[13]),
- .Q(MUXED_DATA_Buffer[18]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[12]),
- .Q(MUXED_DATA_Buffer[19]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[1]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [14]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[11]),
- .Q(MUXED_DATA_Buffer[20]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[10]),
- .Q(MUXED_DATA_Buffer[21]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[9]),
- .Q(MUXED_DATA_Buffer[22]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[8]),
- .Q(MUXED_DATA_Buffer[23]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[7]),
- .Q(MUXED_DATA_Buffer[24]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[6]),
- .Q(MUXED_DATA_Buffer[25]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[5]),
- .Q(MUXED_DATA_Buffer[26]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[4]),
- .Q(MUXED_DATA_Buffer[27]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[3]),
- .Q(MUXED_DATA_Buffer[28]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[2]),
- .Q(MUXED_DATA_Buffer[29]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[2]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [13]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[1]),
- .Q(MUXED_DATA_Buffer[30]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[0]),
- .Q(MUXED_DATA_Buffer[31]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[3]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [12]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[4]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [11]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[5]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [10]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[6]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [9]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[7]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [8]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[8]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [7]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(muxed_data_c[9]),
- .Q(\MUXED_DATA_Buffer_reg[0]_0 [6]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair223" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[0]_i_1
- (.I0(MUXED_DATA_Buffer[16]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [15]),
- .O(D[31]));
- (* SOFT_HLUTNM = "soft_lutpair213" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[10]_i_1
- (.I0(MUXED_DATA_Buffer[26]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [5]),
- .O(D[21]));
- (* SOFT_HLUTNM = "soft_lutpair212" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[11]_i_1
- (.I0(MUXED_DATA_Buffer[27]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [4]),
- .O(D[20]));
- (* SOFT_HLUTNM = "soft_lutpair211" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[12]_i_1
- (.I0(MUXED_DATA_Buffer[28]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [3]),
- .O(D[19]));
- (* SOFT_HLUTNM = "soft_lutpair210" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[13]_i_1
- (.I0(MUXED_DATA_Buffer[29]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [2]),
- .O(D[18]));
- (* SOFT_HLUTNM = "soft_lutpair209" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[14]_i_1
- (.I0(MUXED_DATA_Buffer[30]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [1]),
- .O(D[17]));
- (* SOFT_HLUTNM = "soft_lutpair208" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[15]_i_1
- (.I0(MUXED_DATA_Buffer[31]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [0]),
- .O(D[16]));
- (* SOFT_HLUTNM = "soft_lutpair223" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[16]_i_1
- (.I0(MUXED_DATA_Buffer[16]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [15]),
- .O(D[15]));
- (* SOFT_HLUTNM = "soft_lutpair222" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[17]_i_1
- (.I0(MUXED_DATA_Buffer[17]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [14]),
- .O(D[14]));
- (* SOFT_HLUTNM = "soft_lutpair221" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[18]_i_1
- (.I0(MUXED_DATA_Buffer[18]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [13]),
- .O(D[13]));
- (* SOFT_HLUTNM = "soft_lutpair220" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[19]_i_1
- (.I0(MUXED_DATA_Buffer[19]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [12]),
- .O(D[12]));
- (* SOFT_HLUTNM = "soft_lutpair222" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[1]_i_1
- (.I0(MUXED_DATA_Buffer[17]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [14]),
- .O(D[30]));
- (* SOFT_HLUTNM = "soft_lutpair219" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[20]_i_1
- (.I0(MUXED_DATA_Buffer[20]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [11]),
- .O(D[11]));
- (* SOFT_HLUTNM = "soft_lutpair218" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[21]_i_1
- (.I0(MUXED_DATA_Buffer[21]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [10]),
- .O(D[10]));
- (* SOFT_HLUTNM = "soft_lutpair217" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[22]_i_1
- (.I0(MUXED_DATA_Buffer[22]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [9]),
- .O(D[9]));
- (* SOFT_HLUTNM = "soft_lutpair216" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[23]_i_1
- (.I0(MUXED_DATA_Buffer[23]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [8]),
- .O(D[8]));
- (* SOFT_HLUTNM = "soft_lutpair215" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[24]_i_1
- (.I0(MUXED_DATA_Buffer[24]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [7]),
- .O(D[7]));
- (* SOFT_HLUTNM = "soft_lutpair214" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[25]_i_1
- (.I0(MUXED_DATA_Buffer[25]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [6]),
- .O(D[6]));
- (* SOFT_HLUTNM = "soft_lutpair213" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[26]_i_1
- (.I0(MUXED_DATA_Buffer[26]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [5]),
- .O(D[5]));
- (* SOFT_HLUTNM = "soft_lutpair212" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[27]_i_1
- (.I0(MUXED_DATA_Buffer[27]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [4]),
- .O(D[4]));
- (* SOFT_HLUTNM = "soft_lutpair211" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[28]_i_1
- (.I0(MUXED_DATA_Buffer[28]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [3]),
- .O(D[3]));
- (* SOFT_HLUTNM = "soft_lutpair210" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[29]_i_1
- (.I0(MUXED_DATA_Buffer[29]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [2]),
- .O(D[2]));
- (* SOFT_HLUTNM = "soft_lutpair221" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[2]_i_1
- (.I0(MUXED_DATA_Buffer[18]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [13]),
- .O(D[29]));
- (* SOFT_HLUTNM = "soft_lutpair209" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[30]_i_1
- (.I0(MUXED_DATA_Buffer[30]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [1]),
- .O(D[1]));
- (* SOFT_HLUTNM = "soft_lutpair208" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[31]_i_1
- (.I0(MUXED_DATA_Buffer[31]),
- .I1(STORAGE_SELECT_Buffer[0]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [0]),
- .O(D[0]));
- (* SOFT_HLUTNM = "soft_lutpair220" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[3]_i_1
- (.I0(MUXED_DATA_Buffer[19]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [12]),
- .O(D[28]));
- (* SOFT_HLUTNM = "soft_lutpair219" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[4]_i_1
- (.I0(MUXED_DATA_Buffer[20]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [11]),
- .O(D[27]));
- (* SOFT_HLUTNM = "soft_lutpair218" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[5]_i_1
- (.I0(MUXED_DATA_Buffer[21]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [10]),
- .O(D[26]));
- (* SOFT_HLUTNM = "soft_lutpair217" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[6]_i_1
- (.I0(MUXED_DATA_Buffer[22]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [9]),
- .O(D[25]));
- (* SOFT_HLUTNM = "soft_lutpair216" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[7]_i_1
- (.I0(MUXED_DATA_Buffer[23]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [8]),
- .O(D[24]));
- (* SOFT_HLUTNM = "soft_lutpair215" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[8]_i_1
- (.I0(MUXED_DATA_Buffer[24]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [7]),
- .O(D[23]));
- (* SOFT_HLUTNM = "soft_lutpair214" *)
- LUT3 #(
- .INIT(8'hB8))
- \STORAGE_DATA_Buffer[9]_i_1
- (.I0(MUXED_DATA_Buffer[25]),
- .I1(STORAGE_SELECT_Buffer[1]),
- .I2(\MUXED_DATA_Buffer_reg[0]_0 [6]),
- .O(D[22]));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_LL_TO_AXI" *)
-module north_channel_north_channel_LL_TO_AXI
- (M_AXI_RX_TKEEP,
- rx_eof,
- Q);
- output [2:0]M_AXI_RX_TKEEP;
- input rx_eof;
- input [1:0]Q;
-
- wire [2:0]M_AXI_RX_TKEEP;
- wire [1:0]Q;
- wire rx_eof;
-
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT3 #(
- .INIT(8'hFE))
- \M_AXI_RX_TKEEP[1]_INST_0
- (.I0(rx_eof),
- .I1(Q[0]),
- .I2(Q[1]),
- .O(M_AXI_RX_TKEEP[2]));
- LUT2 #(
- .INIT(4'hE))
- \M_AXI_RX_TKEEP[2]_INST_0
- (.I0(rx_eof),
- .I1(Q[1]),
- .O(M_AXI_RX_TKEEP[1]));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT3 #(
- .INIT(8'hEA))
- \M_AXI_RX_TKEEP[3]_INST_0
- (.I0(rx_eof),
- .I1(Q[1]),
- .I2(Q[0]),
- .O(M_AXI_RX_TKEEP[0]));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_OUTPUT_MUX" *)
-module north_channel_north_channel_OUTPUT_MUX
- (M_AXI_RX_TDATA,
- Q,
- user_clk,
- \OUTPUT_DATA_Buffer_reg[16]_0 ,
- OUTPUT_SELECT_Buffer);
- output [0:31]M_AXI_RX_TDATA;
- input [31:0]Q;
- input user_clk;
- input [15:0]\OUTPUT_DATA_Buffer_reg[16]_0 ;
- input OUTPUT_SELECT_Buffer;
-
- wire [0:31]M_AXI_RX_TDATA;
- wire [15:0]\OUTPUT_DATA_Buffer_reg[16]_0 ;
- wire OUTPUT_SELECT_Buffer;
- wire [31:0]Q;
- wire [16:31]output_data_c;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair194" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[16]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [15]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[15]),
- .O(output_data_c[16]));
- (* SOFT_HLUTNM = "soft_lutpair194" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[17]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [14]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[14]),
- .O(output_data_c[17]));
- (* SOFT_HLUTNM = "soft_lutpair193" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[18]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [13]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[13]),
- .O(output_data_c[18]));
- (* SOFT_HLUTNM = "soft_lutpair193" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[19]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [12]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[12]),
- .O(output_data_c[19]));
- (* SOFT_HLUTNM = "soft_lutpair192" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[20]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [11]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[11]),
- .O(output_data_c[20]));
- (* SOFT_HLUTNM = "soft_lutpair192" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[21]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [10]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[10]),
- .O(output_data_c[21]));
- (* SOFT_HLUTNM = "soft_lutpair191" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[22]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [9]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[9]),
- .O(output_data_c[22]));
- (* SOFT_HLUTNM = "soft_lutpair191" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[23]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [8]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[8]),
- .O(output_data_c[23]));
- (* SOFT_HLUTNM = "soft_lutpair190" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[24]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [7]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[7]),
- .O(output_data_c[24]));
- (* SOFT_HLUTNM = "soft_lutpair190" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[25]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [6]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[6]),
- .O(output_data_c[25]));
- (* SOFT_HLUTNM = "soft_lutpair189" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[26]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [5]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[5]),
- .O(output_data_c[26]));
- (* SOFT_HLUTNM = "soft_lutpair189" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[27]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [4]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[4]),
- .O(output_data_c[27]));
- (* SOFT_HLUTNM = "soft_lutpair188" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[28]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [3]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[3]),
- .O(output_data_c[28]));
- (* SOFT_HLUTNM = "soft_lutpair188" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[29]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [2]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[2]),
- .O(output_data_c[29]));
- (* SOFT_HLUTNM = "soft_lutpair187" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[30]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [1]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[1]),
- .O(output_data_c[30]));
- (* SOFT_HLUTNM = "soft_lutpair187" *)
- LUT3 #(
- .INIT(8'hB8))
- \OUTPUT_DATA_Buffer[31]_i_1
- (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [0]),
- .I1(OUTPUT_SELECT_Buffer),
- .I2(Q[0]),
- .O(output_data_c[31]));
- FDRE \OUTPUT_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[31]),
- .Q(M_AXI_RX_TDATA[0]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[21]),
- .Q(M_AXI_RX_TDATA[10]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[20]),
- .Q(M_AXI_RX_TDATA[11]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[19]),
- .Q(M_AXI_RX_TDATA[12]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[18]),
- .Q(M_AXI_RX_TDATA[13]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[17]),
- .Q(M_AXI_RX_TDATA[14]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[16]),
- .Q(M_AXI_RX_TDATA[15]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[16]),
- .Q(M_AXI_RX_TDATA[16]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[17]),
- .Q(M_AXI_RX_TDATA[17]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[18]),
- .Q(M_AXI_RX_TDATA[18]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[19]),
- .Q(M_AXI_RX_TDATA[19]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[30]),
- .Q(M_AXI_RX_TDATA[1]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[20]),
- .Q(M_AXI_RX_TDATA[20]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[21]),
- .Q(M_AXI_RX_TDATA[21]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[22]),
- .Q(M_AXI_RX_TDATA[22]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[23]),
- .Q(M_AXI_RX_TDATA[23]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[24]),
- .Q(M_AXI_RX_TDATA[24]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[25]),
- .Q(M_AXI_RX_TDATA[25]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[26]),
- .Q(M_AXI_RX_TDATA[26]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[27]),
- .Q(M_AXI_RX_TDATA[27]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[28]),
- .Q(M_AXI_RX_TDATA[28]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[29]),
- .Q(M_AXI_RX_TDATA[29]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[29]),
- .Q(M_AXI_RX_TDATA[2]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[30]),
- .Q(M_AXI_RX_TDATA[30]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_data_c[31]),
- .Q(M_AXI_RX_TDATA[31]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[28]),
- .Q(M_AXI_RX_TDATA[3]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[27]),
- .Q(M_AXI_RX_TDATA[4]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[26]),
- .Q(M_AXI_RX_TDATA[5]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[25]),
- .Q(M_AXI_RX_TDATA[6]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[24]),
- .Q(M_AXI_RX_TDATA[7]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[23]),
- .Q(M_AXI_RX_TDATA[8]),
- .R(1'b0));
- FDRE \OUTPUT_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[22]),
- .Q(M_AXI_RX_TDATA[9]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_OUTPUT_SWITCH_CONTROL" *)
-module north_channel_north_channel_OUTPUT_SWITCH_CONTROL
- (OUTPUT_SELECT_Buffer,
- output_select_c,
- user_clk);
- output OUTPUT_SELECT_Buffer;
- input [0:0]output_select_c;
- input user_clk;
-
- wire OUTPUT_SELECT_Buffer;
- wire [0:0]output_select_c;
- wire user_clk;
-
- FDRE \OUTPUT_SELECT_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(output_select_c),
- .Q(OUTPUT_SELECT_Buffer),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_RESET_LOGIC" *)
-module north_channel_north_channel_RESET_LOGIC
- (link_reset_r,
- SYSTEM_RESET_reg_0,
- wait_for_lane_up_r0,
- new_pkt_r,
- PLL_NOT_LOCKED,
- out,
- LINK_RESET_OUT,
- init_clk_in,
- user_clk,
- tx_lock,
- gt_rxresetdone_r2_reg_0,
- gt_txresetdone_r2_reg_0,
- reset_channel_i,
- new_pkt_r_reg,
- S_AXI_TX_TLAST,
- S_AXI_TX_TVALID,
- tx_dst_rdy,
- new_pkt_r_reg_0);
- output link_reset_r;
- output SYSTEM_RESET_reg_0;
- output wait_for_lane_up_r0;
- output new_pkt_r;
- input PLL_NOT_LOCKED;
- input out;
- input LINK_RESET_OUT;
- input init_clk_in;
- input user_clk;
- input tx_lock;
- input gt_rxresetdone_r2_reg_0;
- input gt_txresetdone_r2_reg_0;
- input reset_channel_i;
- input new_pkt_r_reg;
- input S_AXI_TX_TLAST;
- input S_AXI_TX_TVALID;
- input tx_dst_rdy;
- input new_pkt_r_reg_0;
-
- wire LINK_RESET_OUT;
- wire PLL_NOT_LOCKED;
- wire SYSTEM_RESET0_n_0;
- wire SYSTEM_RESET_reg_0;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TVALID;
- wire gt_rxresetdone_r;
- wire gt_rxresetdone_r2;
- wire gt_rxresetdone_r2_reg_0;
- wire gt_rxresetdone_r3;
- wire gt_txresetdone_r;
- wire gt_txresetdone_r2;
- wire gt_txresetdone_r2_reg_0;
- wire gt_txresetdone_r3;
- wire init_clk_in;
- wire link_reset_r;
- wire new_pkt_r;
- wire new_pkt_r_reg;
- wire new_pkt_r_reg_0;
- wire out;
- wire pll_not_locked_sync;
- wire reset_channel_i;
- wire scndry_out;
- wire tx_dst_rdy;
- wire tx_lock;
- wire tx_lock_comb_r;
- wire tx_lock_sync;
- wire user_clk;
- wire wait_for_lane_up_r0;
-
- LUT6 #(
- .INIT(64'hFFFFEFFFFFFFFFFF))
- SYSTEM_RESET0
- (.I0(pll_not_locked_sync),
- .I1(out),
- .I2(gt_txresetdone_r3),
- .I3(gt_rxresetdone_r3),
- .I4(scndry_out),
- .I5(tx_lock_sync),
- .O(SYSTEM_RESET0_n_0));
- FDRE SYSTEM_RESET_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(SYSTEM_RESET0_n_0),
- .Q(SYSTEM_RESET_reg_0),
- .R(1'b0));
- FDCE gt_rxresetdone_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_rxresetdone_r2_reg_0),
- .D(gt_rxresetdone_r),
- .Q(gt_rxresetdone_r2));
- FDRE gt_rxresetdone_r3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt_rxresetdone_r2),
- .Q(gt_rxresetdone_r3),
- .R(1'b0));
- FDCE gt_rxresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_rxresetdone_r2_reg_0),
- .D(1'b1),
- .Q(gt_rxresetdone_r));
- FDCE gt_txresetdone_r2_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_txresetdone_r2_reg_0),
- .D(gt_txresetdone_r),
- .Q(gt_txresetdone_r2));
- FDRE gt_txresetdone_r3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gt_txresetdone_r2),
- .Q(gt_txresetdone_r3),
- .R(1'b0));
- FDCE gt_txresetdone_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(gt_txresetdone_r2_reg_0),
- .D(1'b1),
- .Q(gt_txresetdone_r));
- north_channel_north_channel_cdc_sync__parameterized3_27 link_reset_cdc_sync
- (.init_clk_in(init_clk_in),
- .link_reset_r(link_reset_r),
- .out(scndry_out),
- .user_clk(user_clk));
- FDRE link_reset_comb_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(LINK_RESET_OUT),
- .Q(link_reset_r),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h4444044400000400))
- new_pkt_r_i_1
- (.I0(SYSTEM_RESET_reg_0),
- .I1(new_pkt_r_reg),
- .I2(S_AXI_TX_TLAST),
- .I3(S_AXI_TX_TVALID),
- .I4(tx_dst_rdy),
- .I5(new_pkt_r_reg_0),
- .O(new_pkt_r));
- north_channel_north_channel_cdc_sync_28 pll_not_locked_cdc_sync
- (.PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .out(pll_not_locked_sync),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized3_29 tx_lock_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(tx_lock_sync),
- .tx_lock_comb_r(tx_lock_comb_r),
- .user_clk(user_clk));
- FDRE tx_lock_comb_r_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_lock),
- .Q(tx_lock_comb_r),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- verify_r_i_1
- (.I0(SYSTEM_RESET_reg_0),
- .I1(reset_channel_i),
- .O(wait_for_lane_up_r0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_RX_LL" *)
-module north_channel_north_channel_RX_LL
- (rx_eof,
- FRAME_ERR,
- M_AXI_RX_TLAST,
- M_AXI_RX_TVALID,
- M_AXI_UFC_RX_TVALID,
- \RX_REM_Buffer_reg[0] ,
- M_AXI_RX_TDATA,
- M_AXI_UFC_RX_TDATA,
- M_AXI_UFC_RX_TKEEP,
- M_AXI_UFC_RX_TLAST,
- user_clk,
- RESET,
- neqOp,
- \rx_suf_r_reg[0] ,
- p_8_out,
- p_9_out,
- Q,
- rx_pe_data_striped_i,
- START_RX,
- \stage_1_count_value_r_reg[0] ,
- \stage_1_count_value_r_reg[1] ,
- \stage_1_count_value_r_reg[2] ,
- \stage_1_count_value_r_reg[3] ,
- D);
- output rx_eof;
- output FRAME_ERR;
- output M_AXI_RX_TLAST;
- output M_AXI_RX_TVALID;
- output M_AXI_UFC_RX_TVALID;
- output [1:0]\RX_REM_Buffer_reg[0] ;
- output [0:31]M_AXI_RX_TDATA;
- output [0:31]M_AXI_UFC_RX_TDATA;
- output [0:0]M_AXI_UFC_RX_TKEEP;
- output M_AXI_UFC_RX_TLAST;
- input user_clk;
- input RESET;
- input neqOp;
- input [1:0]\rx_suf_r_reg[0] ;
- input [1:0]p_8_out;
- input [1:0]p_9_out;
- input [1:0]Q;
- input [0:31]rx_pe_data_striped_i;
- input START_RX;
- input \stage_1_count_value_r_reg[0] ;
- input \stage_1_count_value_r_reg[1] ;
- input \stage_1_count_value_r_reg[2] ;
- input \stage_1_count_value_r_reg[3] ;
- input [1:0]D;
-
- wire [1:0]D;
- wire FRAME_ERR;
- wire [0:31]M_AXI_RX_TDATA;
- wire M_AXI_RX_TLAST;
- wire M_AXI_RX_TVALID;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [0:0]M_AXI_UFC_RX_TKEEP;
- wire M_AXI_UFC_RX_TLAST;
- wire M_AXI_UFC_RX_TVALID;
- wire [1:0]Q;
- wire RESET;
- wire [1:0]\RX_REM_Buffer_reg[0] ;
- wire START_RX;
- wire UFC_START;
- wire barrel_shifter_control_i;
- wire neqOp;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [0:1]pdu_data_v_i;
- wire [0:1]pdu_ecp_i;
- wire [0:1]pdu_scp_i;
- wire plusOp;
- wire rx_eof;
- wire [0:31]rx_pe_data_striped_i;
- wire [1:0]\rx_suf_r_reg[0] ;
- wire \stage_1_count_value_r_reg[0] ;
- wire \stage_1_count_value_r_reg[1] ;
- wire \stage_1_count_value_r_reg[2] ;
- wire \stage_1_count_value_r_reg[3] ;
- wire [0:31]stage_1_data_r;
- wire \stage_1_rx_ll_deframer_i/S1_in ;
- wire ufc_filter_i_n_10;
- wire ufc_filter_i_n_11;
- wire ufc_filter_i_n_12;
- wire ufc_filter_i_n_13;
- wire ufc_filter_i_n_14;
- wire ufc_filter_i_n_15;
- wire ufc_filter_i_n_16;
- wire ufc_filter_i_n_17;
- wire ufc_filter_i_n_18;
- wire ufc_filter_i_n_19;
- wire ufc_filter_i_n_20;
- wire ufc_filter_i_n_21;
- wire ufc_filter_i_n_22;
- wire ufc_filter_i_n_23;
- wire ufc_filter_i_n_24;
- wire ufc_filter_i_n_25;
- wire ufc_filter_i_n_26;
- wire ufc_filter_i_n_27;
- wire ufc_filter_i_n_28;
- wire ufc_filter_i_n_29;
- wire ufc_filter_i_n_30;
- wire ufc_filter_i_n_31;
- wire ufc_filter_i_n_32;
- wire ufc_filter_i_n_33;
- wire ufc_filter_i_n_34;
- wire ufc_filter_i_n_35;
- wire ufc_filter_i_n_36;
- wire ufc_filter_i_n_37;
- wire ufc_filter_i_n_38;
- wire ufc_filter_i_n_39;
- wire ufc_filter_i_n_40;
- wire ufc_filter_i_n_44;
- wire ufc_filter_i_n_45;
- wire ufc_filter_i_n_6;
- wire ufc_filter_i_n_7;
- wire ufc_filter_i_n_8;
- wire ufc_filter_i_n_9;
- wire user_clk;
-
- north_channel_north_channel_RX_LL_PDU_DATAPATH rx_ll_pdu_datapath_i
- (.\AFTER_SCP_Buffer_reg[1] (ufc_filter_i_n_45),
- .D({pdu_scp_i[0],pdu_scp_i[1]}),
- .FRAME_ERR(FRAME_ERR),
- .\IN_FRAME_Buffer_reg[1] (ufc_filter_i_n_40),
- .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
- .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
- .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
- .Q({pdu_data_v_i[0],pdu_data_v_i[1]}),
- .RESET(RESET),
- .\RX_REM_Buffer_reg[0]_0 (\RX_REM_Buffer_reg[0] ),
- .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
- .START_RX(START_RX),
- .in_frame_r_reg(ufc_filter_i_n_39),
- .rx_eof(rx_eof),
- .\stage_1_ecp_r_reg[0]_0 ({pdu_ecp_i[0],pdu_ecp_i[1]}),
- .stage_1_pad_r_reg_0(ufc_filter_i_n_38),
- .\stage_2_data_r_reg[0]_0 ({stage_1_data_r[0],stage_1_data_r[1],stage_1_data_r[2],stage_1_data_r[3],stage_1_data_r[4],stage_1_data_r[5],stage_1_data_r[6],stage_1_data_r[7],stage_1_data_r[8],stage_1_data_r[9],stage_1_data_r[10],stage_1_data_r[11],stage_1_data_r[12],stage_1_data_r[13],stage_1_data_r[14],stage_1_data_r[15],stage_1_data_r[16],stage_1_data_r[17],stage_1_data_r[18],stage_1_data_r[19],stage_1_data_r[20],stage_1_data_r[21],stage_1_data_r[22],stage_1_data_r[23],stage_1_data_r[24],stage_1_data_r[25],stage_1_data_r[26],stage_1_data_r[27],stage_1_data_r[28],stage_1_data_r[29],stage_1_data_r[30],stage_1_data_r[31]}),
- .user_clk(user_clk));
- north_channel_north_channel_RX_LL_UFC_DATAPATH rx_ll_ufc_datapath_i
- (.M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
- .M_AXI_UFC_RX_TKEEP(M_AXI_UFC_RX_TKEEP),
- .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
- .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
- .Q({plusOp,ufc_filter_i_n_44}),
- .RESET(RESET),
- .UFC_START(UFC_START),
- .barrel_shifter_control_i(barrel_shifter_control_i),
- .\stage_1_data_r_reg[0]_0 ({stage_1_data_r[0],stage_1_data_r[1],stage_1_data_r[2],stage_1_data_r[3],stage_1_data_r[4],stage_1_data_r[5],stage_1_data_r[6],stage_1_data_r[7],stage_1_data_r[8],stage_1_data_r[9],stage_1_data_r[10],stage_1_data_r[11],stage_1_data_r[12],stage_1_data_r[13],stage_1_data_r[14],stage_1_data_r[15],stage_1_data_r[16],stage_1_data_r[17],stage_1_data_r[18],stage_1_data_r[19],stage_1_data_r[20],stage_1_data_r[21],stage_1_data_r[22],stage_1_data_r[23],stage_1_data_r[24],stage_1_data_r[25],stage_1_data_r[26],stage_1_data_r[27],stage_1_data_r[28],stage_1_data_r[29],stage_1_data_r[30],stage_1_data_r[31]}),
- .\stage_1_data_r_reg[0]_1 (ufc_filter_i_n_6),
- .\stage_1_data_r_reg[10]_0 (ufc_filter_i_n_16),
- .\stage_1_data_r_reg[11]_0 (ufc_filter_i_n_17),
- .\stage_1_data_r_reg[12]_0 (ufc_filter_i_n_18),
- .\stage_1_data_r_reg[13]_0 (ufc_filter_i_n_19),
- .\stage_1_data_r_reg[14]_0 (ufc_filter_i_n_20),
- .\stage_1_data_r_reg[15]_0 (ufc_filter_i_n_21),
- .\stage_1_data_r_reg[16]_0 (ufc_filter_i_n_22),
- .\stage_1_data_r_reg[17]_0 (ufc_filter_i_n_23),
- .\stage_1_data_r_reg[18]_0 (ufc_filter_i_n_24),
- .\stage_1_data_r_reg[19]_0 (ufc_filter_i_n_25),
- .\stage_1_data_r_reg[1]_0 (ufc_filter_i_n_7),
- .\stage_1_data_r_reg[20]_0 (ufc_filter_i_n_26),
- .\stage_1_data_r_reg[21]_0 (ufc_filter_i_n_27),
- .\stage_1_data_r_reg[22]_0 (ufc_filter_i_n_28),
- .\stage_1_data_r_reg[23]_0 (ufc_filter_i_n_29),
- .\stage_1_data_r_reg[24]_0 (ufc_filter_i_n_30),
- .\stage_1_data_r_reg[25]_0 (ufc_filter_i_n_31),
- .\stage_1_data_r_reg[26]_0 (ufc_filter_i_n_32),
- .\stage_1_data_r_reg[27]_0 (ufc_filter_i_n_33),
- .\stage_1_data_r_reg[28]_0 (ufc_filter_i_n_34),
- .\stage_1_data_r_reg[29]_0 (ufc_filter_i_n_35),
- .\stage_1_data_r_reg[2]_0 (ufc_filter_i_n_8),
- .\stage_1_data_r_reg[30]_0 (ufc_filter_i_n_36),
- .\stage_1_data_r_reg[31]_0 (ufc_filter_i_n_37),
- .\stage_1_data_r_reg[3]_0 (ufc_filter_i_n_9),
- .\stage_1_data_r_reg[4]_0 (ufc_filter_i_n_10),
- .\stage_1_data_r_reg[5]_0 (ufc_filter_i_n_11),
- .\stage_1_data_r_reg[6]_0 (ufc_filter_i_n_12),
- .\stage_1_data_r_reg[7]_0 (ufc_filter_i_n_13),
- .\stage_1_data_r_reg[8]_0 (ufc_filter_i_n_14),
- .\stage_1_data_r_reg[9]_0 (ufc_filter_i_n_15),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_FILTER ufc_filter_i
- (.D({pdu_scp_i[0],pdu_scp_i[1]}),
- .\PDU_DATA_V_Buffer_reg[0]_0 ({pdu_data_v_i[0],pdu_data_v_i[1]}),
- .\PDU_ECP_Buffer_reg[0]_0 ({pdu_ecp_i[0],pdu_ecp_i[1]}),
- .\PDU_ECP_Buffer_reg[0]_1 (ufc_filter_i_n_40),
- .\PDU_ECP_Buffer_reg[1]_0 (ufc_filter_i_n_39),
- .\PDU_PAD_Buffer_reg[0]_0 (ufc_filter_i_n_38),
- .\PDU_SCP_Buffer_reg[1]_0 (ufc_filter_i_n_45),
- .Q(Q),
- .RESET(RESET),
- .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
- .\UFC_DATA_V_Buffer_reg[0]_0 ({plusOp,ufc_filter_i_n_44}),
- .UFC_START(UFC_START),
- .barrel_shifter_control_i(barrel_shifter_control_i),
- .neqOp(neqOp),
- .p_8_out(p_8_out),
- .p_9_out(p_9_out),
- .\rx_data_v_r_reg[0]_0 (D),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .\rx_suf_r_reg[0]_0 (\rx_suf_r_reg[0] ),
- .\stage_1_count_value_r_reg[0]_0 (\stage_1_count_value_r_reg[0] ),
- .\stage_1_count_value_r_reg[1]_0 (\stage_1_count_value_r_reg[1] ),
- .\stage_1_count_value_r_reg[2]_0 (\stage_1_count_value_r_reg[2] ),
- .\stage_1_count_value_r_reg[3]_0 (\stage_1_count_value_r_reg[3] ),
- .user_clk(user_clk),
- .user_clk_0(ufc_filter_i_n_6),
- .user_clk_1(ufc_filter_i_n_7),
- .user_clk_10(ufc_filter_i_n_16),
- .user_clk_11(ufc_filter_i_n_17),
- .user_clk_12(ufc_filter_i_n_18),
- .user_clk_13(ufc_filter_i_n_19),
- .user_clk_14(ufc_filter_i_n_20),
- .user_clk_15(ufc_filter_i_n_21),
- .user_clk_16(ufc_filter_i_n_22),
- .user_clk_17(ufc_filter_i_n_23),
- .user_clk_18(ufc_filter_i_n_24),
- .user_clk_19(ufc_filter_i_n_25),
- .user_clk_2(ufc_filter_i_n_8),
- .user_clk_20(ufc_filter_i_n_26),
- .user_clk_21(ufc_filter_i_n_27),
- .user_clk_22(ufc_filter_i_n_28),
- .user_clk_23(ufc_filter_i_n_29),
- .user_clk_24(ufc_filter_i_n_30),
- .user_clk_25(ufc_filter_i_n_31),
- .user_clk_26(ufc_filter_i_n_32),
- .user_clk_27(ufc_filter_i_n_33),
- .user_clk_28(ufc_filter_i_n_34),
- .user_clk_29(ufc_filter_i_n_35),
- .user_clk_3(ufc_filter_i_n_9),
- .user_clk_30(ufc_filter_i_n_36),
- .user_clk_31(ufc_filter_i_n_37),
- .user_clk_4(ufc_filter_i_n_10),
- .user_clk_5(ufc_filter_i_n_11),
- .user_clk_6(ufc_filter_i_n_12),
- .user_clk_7(ufc_filter_i_n_13),
- .user_clk_8(ufc_filter_i_n_14),
- .user_clk_9(ufc_filter_i_n_15));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_RX_LL_DEFRAMER" *)
-module north_channel_north_channel_RX_LL_DEFRAMER
- (mux_select_c,
- \AFTER_SCP_Buffer_reg[0]_0 ,
- \AFTER_SCP_Buffer_reg[0]_1 ,
- \AFTER_SCP_Buffer_reg[0]_2 ,
- \DEFRAMED_DATA_V_Buffer_reg[1]_0 ,
- \stage_1_ecp_r_reg[0] ,
- \IN_FRAME_Buffer_reg[1]_0 ,
- D,
- in_frame_r_reg_0,
- S1_in,
- \AFTER_SCP_Buffer_reg[1]_0 ,
- RESET,
- user_clk,
- Q,
- stage_2_frame_err_r_reg,
- \DEFRAMED_DATA_V_Buffer_reg[0]_0 );
- output [0:0]mux_select_c;
- output \AFTER_SCP_Buffer_reg[0]_0 ;
- output \AFTER_SCP_Buffer_reg[0]_1 ;
- output \AFTER_SCP_Buffer_reg[0]_2 ;
- output [1:0]\DEFRAMED_DATA_V_Buffer_reg[1]_0 ;
- output \stage_1_ecp_r_reg[0] ;
- input \IN_FRAME_Buffer_reg[1]_0 ;
- input [1:0]D;
- input in_frame_r_reg_0;
- input S1_in;
- input \AFTER_SCP_Buffer_reg[1]_0 ;
- input RESET;
- input user_clk;
- input [1:0]Q;
- input [1:0]stage_2_frame_err_r_reg;
- input [1:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;
-
- wire \AFTER_SCP_Buffer_reg[0]_0 ;
- wire \AFTER_SCP_Buffer_reg[0]_1 ;
- wire \AFTER_SCP_Buffer_reg[0]_2 ;
- wire \AFTER_SCP_Buffer_reg[1]_0 ;
- wire CI;
- wire [1:0]D;
- wire \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ;
- wire \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;
- wire [1:0]\DEFRAMED_DATA_V_Buffer_reg[1]_0 ;
- wire \IN_FRAME_Buffer_reg[1]_0 ;
- wire [1:0]Q;
- wire RESET;
- wire S1_in;
- wire after_scp_c_1;
- wire data_after_start_muxcy_1_n_0;
- wire in_frame_c_0;
- wire in_frame_c_1;
- wire in_frame_r_reg_0;
- wire [0:0]mux_select_c;
- wire [0:1]stage_1_after_scp_r;
- wire [0:1]stage_1_data_v_r;
- wire \stage_1_ecp_r_reg[0] ;
- wire [0:1]stage_1_in_frame_r;
- wire [1:0]stage_2_frame_err_r_reg;
- wire user_clk;
- wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED;
- wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED;
- wire [3:0]NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED;
- wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED;
- wire [3:2]NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED;
- wire [3:2]NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED;
- wire [3:0]NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED;
- wire [3:2]NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED;
-
- FDRE \AFTER_SCP_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(after_scp_c_1),
- .Q(stage_1_after_scp_r[0]),
- .R(RESET));
- FDRE \AFTER_SCP_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(data_after_start_muxcy_1_n_0),
- .Q(stage_1_after_scp_r[1]),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair198" *)
- LUT2 #(
- .INIT(4'h8))
- \COUNT_Buffer[0]_i_1
- (.I0(stage_1_data_v_r[1]),
- .I1(stage_1_data_v_r[0]),
- .O(\DEFRAMED_DATA_V_Buffer_reg[1]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair198" *)
- LUT2 #(
- .INIT(4'h6))
- \COUNT_Buffer[1]_i_1
- (.I0(stage_1_data_v_r[0]),
- .I1(stage_1_data_v_r[1]),
- .O(\DEFRAMED_DATA_V_Buffer_reg[1]_0 [0]));
- LUT2 #(
- .INIT(4'h8))
- \DEFRAMED_DATA_V_Buffer[0]_i_1
- (.I0(in_frame_c_1),
- .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [1]),
- .O(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \DEFRAMED_DATA_V_Buffer[1]_i_1
- (.I0(in_frame_c_0),
- .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [0]),
- .O(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \DEFRAMED_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ),
- .Q(stage_1_data_v_r[0]),
- .R(RESET));
- FDRE \DEFRAMED_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(stage_1_data_v_r[1]),
- .R(RESET));
- FDRE \IN_FRAME_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(CI),
- .Q(stage_1_in_frame_r[0]),
- .R(RESET));
- FDRE \IN_FRAME_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(in_frame_c_1),
- .Q(stage_1_in_frame_r[1]),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair197" *)
- LUT2 #(
- .INIT(4'h2))
- \MUX_SELECT_Buffer[2]_i_1
- (.I0(stage_1_data_v_r[1]),
- .I1(stage_1_data_v_r[0]),
- .O(mux_select_c));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* OPT_MODIFIED = "MLO" *)
- (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
- CARRY4 data_after_start_muxcy_0_CARRY4
- (.CI(1'b0),
- .CO({NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED[3:2],data_after_start_muxcy_1_n_0,after_scp_c_1}),
- .CYINIT(1'b0),
- .DI({NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED[3:2],1'b1,1'b1}),
- .O(NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
- .S({NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED[3:2],\AFTER_SCP_Buffer_reg[1]_0 ,S1_in}));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* OPT_MODIFIED = "MLO" *)
- (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
- CARRY4 in_frame_muxcy_0_CARRY4
- (.CI(1'b0),
- .CO({NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED[3:2],in_frame_c_0,in_frame_c_1}),
- .CYINIT(CI),
- .DI({NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED[3:2],D[0],D[1]}),
- .O(NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
- .S({NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED[3:2],in_frame_r_reg_0,\IN_FRAME_Buffer_reg[1]_0 }));
- FDRE in_frame_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(in_frame_c_0),
- .Q(CI),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair196" *)
- LUT4 #(
- .INIT(16'hF888))
- stage_2_end_after_start_r_i_1
- (.I0(stage_1_after_scp_r[0]),
- .I1(Q[1]),
- .I2(stage_1_after_scp_r[1]),
- .I3(Q[0]),
- .O(\AFTER_SCP_Buffer_reg[0]_2 ));
- (* SOFT_HLUTNM = "soft_lutpair196" *)
- LUT4 #(
- .INIT(16'h4F44))
- stage_2_end_before_start_r_i_1
- (.I0(stage_1_after_scp_r[0]),
- .I1(Q[1]),
- .I2(stage_1_after_scp_r[1]),
- .I3(Q[0]),
- .O(\AFTER_SCP_Buffer_reg[0]_1 ));
- LUT6 #(
- .INIT(64'hFFFFF0AAFCEEFCEE))
- stage_2_frame_err_r_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .I2(stage_2_frame_err_r_reg[1]),
- .I3(stage_1_in_frame_r[0]),
- .I4(stage_2_frame_err_r_reg[0]),
- .I5(stage_1_in_frame_r[1]),
- .O(\stage_1_ecp_r_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair197" *)
- LUT4 #(
- .INIT(16'hF888))
- stage_2_start_with_data_r_i_1
- (.I0(stage_1_after_scp_r[0]),
- .I1(stage_1_data_v_r[0]),
- .I2(stage_1_after_scp_r[1]),
- .I3(stage_1_data_v_r[1]),
- .O(\AFTER_SCP_Buffer_reg[0]_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_RX_LL_PDU_DATAPATH" *)
-module north_channel_north_channel_RX_LL_PDU_DATAPATH
- (rx_eof,
- FRAME_ERR,
- M_AXI_RX_TLAST,
- M_AXI_RX_TVALID,
- \RX_REM_Buffer_reg[0]_0 ,
- M_AXI_RX_TDATA,
- \IN_FRAME_Buffer_reg[1] ,
- D,
- in_frame_r_reg,
- S1_in,
- \AFTER_SCP_Buffer_reg[1] ,
- user_clk,
- RESET,
- stage_1_pad_r_reg_0,
- START_RX,
- Q,
- \stage_1_ecp_r_reg[0]_0 ,
- \stage_2_data_r_reg[0]_0 );
- output rx_eof;
- output FRAME_ERR;
- output M_AXI_RX_TLAST;
- output M_AXI_RX_TVALID;
- output [1:0]\RX_REM_Buffer_reg[0]_0 ;
- output [0:31]M_AXI_RX_TDATA;
- input \IN_FRAME_Buffer_reg[1] ;
- input [1:0]D;
- input in_frame_r_reg;
- input S1_in;
- input \AFTER_SCP_Buffer_reg[1] ;
- input user_clk;
- input RESET;
- input stage_1_pad_r_reg_0;
- input START_RX;
- input [1:0]Q;
- input [1:0]\stage_1_ecp_r_reg[0]_0 ;
- input [31:0]\stage_2_data_r_reg[0]_0 ;
-
- wire \AFTER_SCP_Buffer_reg[1] ;
- wire [1:0]D;
- wire EOF_N_Buffer;
- wire FRAME_ERR;
- wire FRAME_ERR_RESULT_Buffer;
- wire FRAME_ERR_RESULT_Buffer0;
- wire \IN_FRAME_Buffer_reg[1] ;
- wire [0:15]MUXED_DATA_Buffer;
- wire [2:2]MUX_SELECT;
- wire [0:31]M_AXI_RX_TDATA;
- wire M_AXI_RX_TLAST;
- wire M_AXI_RX_TVALID;
- wire OUTPUT_SELECT_Buffer;
- wire [1:0]Q;
- wire RESET;
- wire [0:1]RX_REM_Buffer;
- wire [1:0]\RX_REM_Buffer_reg[0]_0 ;
- wire RX_SRC_RDY_N_Buffer;
- wire S1_in;
- wire SRC_RDY_N_Buffer;
- wire START_RX;
- wire [0:31]STORAGE_DATA;
- wire [4:9]STORAGE_SELECT_Buffer;
- wire [0:1]ce_command_c;
- wire end_storage_r0;
- wire in_frame_r_reg;
- wire [2:2]mux_select_c;
- wire [9:9]output_select_c;
- wire p_0_in0;
- wire rx_eof;
- wire sideband_output_i_n_1;
- wire sideband_output_i_n_5;
- wire [0:1]stage_1_ecp_r;
- wire [1:0]\stage_1_ecp_r_reg[0]_0 ;
- wire stage_1_pad_r;
- wire stage_1_pad_r_reg_0;
- wire stage_1_rx_ll_deframer_i_n_1;
- wire stage_1_rx_ll_deframer_i_n_2;
- wire stage_1_rx_ll_deframer_i_n_3;
- wire stage_1_rx_ll_deframer_i_n_4;
- wire stage_1_rx_ll_deframer_i_n_5;
- wire stage_1_rx_ll_deframer_i_n_6;
- wire [0:1]stage_1_scp_r;
- wire [0:31]stage_2_data_r;
- wire [31:0]\stage_2_data_r_reg[0]_0 ;
- wire [1:1]stage_2_data_v_count_r;
- wire stage_2_end_after_start_r;
- wire stage_2_end_before_start_r;
- wire stage_2_frame_err_r;
- wire stage_2_pad_r;
- wire stage_2_start_with_data_r;
- wire stage_2_valid_data_counter_i_n_3;
- wire stage_3_end_storage_r;
- wire stage_3_left_align_datapath_mux_i_n_16;
- wire stage_3_left_align_datapath_mux_i_n_17;
- wire stage_3_left_align_datapath_mux_i_n_18;
- wire stage_3_left_align_datapath_mux_i_n_19;
- wire stage_3_left_align_datapath_mux_i_n_20;
- wire stage_3_left_align_datapath_mux_i_n_21;
- wire stage_3_left_align_datapath_mux_i_n_22;
- wire stage_3_left_align_datapath_mux_i_n_23;
- wire stage_3_left_align_datapath_mux_i_n_24;
- wire stage_3_left_align_datapath_mux_i_n_25;
- wire stage_3_left_align_datapath_mux_i_n_26;
- wire stage_3_left_align_datapath_mux_i_n_27;
- wire stage_3_left_align_datapath_mux_i_n_28;
- wire stage_3_left_align_datapath_mux_i_n_29;
- wire stage_3_left_align_datapath_mux_i_n_30;
- wire stage_3_left_align_datapath_mux_i_n_31;
- wire stage_3_left_align_datapath_mux_i_n_32;
- wire stage_3_left_align_datapath_mux_i_n_33;
- wire stage_3_left_align_datapath_mux_i_n_34;
- wire stage_3_left_align_datapath_mux_i_n_35;
- wire stage_3_left_align_datapath_mux_i_n_36;
- wire stage_3_left_align_datapath_mux_i_n_37;
- wire stage_3_left_align_datapath_mux_i_n_38;
- wire stage_3_left_align_datapath_mux_i_n_39;
- wire stage_3_left_align_datapath_mux_i_n_40;
- wire stage_3_left_align_datapath_mux_i_n_41;
- wire stage_3_left_align_datapath_mux_i_n_42;
- wire stage_3_left_align_datapath_mux_i_n_43;
- wire stage_3_left_align_datapath_mux_i_n_44;
- wire stage_3_left_align_datapath_mux_i_n_45;
- wire stage_3_left_align_datapath_mux_i_n_46;
- wire stage_3_left_align_datapath_mux_i_n_47;
- wire stage_3_storage_ce_control_i_n_1;
- wire stage_3_storage_count_control_i_n_4;
- wire [0:1]stage_3_storage_count_r;
- wire std_bool2_in;
- wire std_bool6_in;
- wire user_clk;
-
- FDRE FRAME_ERR_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(FRAME_ERR_RESULT_Buffer),
- .Q(FRAME_ERR),
- .R(RESET));
- LUT1 #(
- .INIT(2'h1))
- M_AXI_RX_TLAST_INST_0
- (.I0(rx_eof),
- .O(M_AXI_RX_TLAST));
- LUT1 #(
- .INIT(2'h1))
- M_AXI_RX_TVALID_INST_0
- (.I0(RX_SRC_RDY_N_Buffer),
- .O(M_AXI_RX_TVALID));
- FDRE RX_EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(EOF_N_Buffer),
- .Q(rx_eof),
- .R(1'b0));
- FDRE \RX_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_REM_Buffer[0]),
- .Q(\RX_REM_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_REM_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_REM_Buffer[1]),
- .Q(\RX_REM_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDSE RX_SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(SRC_RDY_N_Buffer),
- .Q(RX_SRC_RDY_N_Buffer),
- .S(RESET));
- north_channel_north_channel_OUTPUT_MUX output_mux_i
- (.M_AXI_RX_TDATA(M_AXI_RX_TDATA),
- .\OUTPUT_DATA_Buffer_reg[16]_0 ({MUXED_DATA_Buffer[0],MUXED_DATA_Buffer[1],MUXED_DATA_Buffer[2],MUXED_DATA_Buffer[3],MUXED_DATA_Buffer[4],MUXED_DATA_Buffer[5],MUXED_DATA_Buffer[6],MUXED_DATA_Buffer[7],MUXED_DATA_Buffer[8],MUXED_DATA_Buffer[9],MUXED_DATA_Buffer[10],MUXED_DATA_Buffer[11],MUXED_DATA_Buffer[12],MUXED_DATA_Buffer[13],MUXED_DATA_Buffer[14],MUXED_DATA_Buffer[15]}),
- .OUTPUT_SELECT_Buffer(OUTPUT_SELECT_Buffer),
- .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31]}),
- .user_clk(user_clk));
- north_channel_north_channel_SIDEBAND_OUTPUT sideband_output_i
- (.D(sideband_output_i_n_5),
- .EOF_N_Buffer(EOF_N_Buffer),
- .EOF_N_Buffer_reg_0(stage_3_storage_count_control_i_n_4),
- .FRAME_ERR_RESULT_Buffer(FRAME_ERR_RESULT_Buffer),
- .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
- .Q(stage_3_storage_count_r[1]),
- .\RX_REM_Buffer_reg[0]_0 ({RX_REM_Buffer[0],RX_REM_Buffer[1]}),
- .\RX_REM_Buffer_reg[0]_1 (stage_2_data_v_count_r),
- .SR(sideband_output_i_n_1),
- .SRC_RDY_N_Buffer(SRC_RDY_N_Buffer),
- .START_RX(START_RX),
- .end_storage_r0(end_storage_r0),
- .stage_2_end_before_start_r(stage_2_end_before_start_r),
- .stage_2_frame_err_r(stage_2_frame_err_r),
- .stage_2_pad_r(stage_2_pad_r),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .std_bool6_in(std_bool6_in),
- .user_clk(user_clk));
- FDRE \stage_1_ecp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_ecp_r_reg[0]_0 [1]),
- .Q(stage_1_ecp_r[0]),
- .R(1'b0));
- FDRE \stage_1_ecp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_ecp_r_reg[0]_0 [0]),
- .Q(stage_1_ecp_r[1]),
- .R(1'b0));
- FDRE stage_1_pad_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_pad_r_reg_0),
- .Q(stage_1_pad_r),
- .R(1'b0));
- north_channel_north_channel_RX_LL_DEFRAMER stage_1_rx_ll_deframer_i
- (.\AFTER_SCP_Buffer_reg[0]_0 (stage_1_rx_ll_deframer_i_n_1),
- .\AFTER_SCP_Buffer_reg[0]_1 (stage_1_rx_ll_deframer_i_n_2),
- .\AFTER_SCP_Buffer_reg[0]_2 (stage_1_rx_ll_deframer_i_n_3),
- .\AFTER_SCP_Buffer_reg[1]_0 (\AFTER_SCP_Buffer_reg[1] ),
- .D(D),
- .\DEFRAMED_DATA_V_Buffer_reg[0]_0 (Q),
- .\DEFRAMED_DATA_V_Buffer_reg[1]_0 ({stage_1_rx_ll_deframer_i_n_4,stage_1_rx_ll_deframer_i_n_5}),
- .\IN_FRAME_Buffer_reg[1]_0 (\IN_FRAME_Buffer_reg[1] ),
- .Q({stage_1_ecp_r[0],stage_1_ecp_r[1]}),
- .RESET(RESET),
- .S1_in(S1_in),
- .in_frame_r_reg_0(in_frame_r_reg),
- .mux_select_c(mux_select_c),
- .\stage_1_ecp_r_reg[0] (stage_1_rx_ll_deframer_i_n_6),
- .stage_2_frame_err_r_reg({stage_1_scp_r[0],stage_1_scp_r[1]}),
- .user_clk(user_clk));
- FDRE \stage_1_scp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(stage_1_scp_r[0]),
- .R(1'b0));
- FDRE \stage_1_scp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(stage_1_scp_r[1]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [31]),
- .Q(stage_2_data_r[0]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [21]),
- .Q(stage_2_data_r[10]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [20]),
- .Q(stage_2_data_r[11]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [19]),
- .Q(stage_2_data_r[12]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [18]),
- .Q(stage_2_data_r[13]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [17]),
- .Q(stage_2_data_r[14]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [16]),
- .Q(stage_2_data_r[15]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [15]),
- .Q(stage_2_data_r[16]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [14]),
- .Q(stage_2_data_r[17]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [13]),
- .Q(stage_2_data_r[18]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [12]),
- .Q(stage_2_data_r[19]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [30]),
- .Q(stage_2_data_r[1]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [11]),
- .Q(stage_2_data_r[20]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [10]),
- .Q(stage_2_data_r[21]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [9]),
- .Q(stage_2_data_r[22]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [8]),
- .Q(stage_2_data_r[23]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [7]),
- .Q(stage_2_data_r[24]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [6]),
- .Q(stage_2_data_r[25]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [5]),
- .Q(stage_2_data_r[26]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [4]),
- .Q(stage_2_data_r[27]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [3]),
- .Q(stage_2_data_r[28]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [2]),
- .Q(stage_2_data_r[29]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [29]),
- .Q(stage_2_data_r[2]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [1]),
- .Q(stage_2_data_r[30]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [0]),
- .Q(stage_2_data_r[31]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [28]),
- .Q(stage_2_data_r[3]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [27]),
- .Q(stage_2_data_r[4]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [26]),
- .Q(stage_2_data_r[5]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [25]),
- .Q(stage_2_data_r[6]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [24]),
- .Q(stage_2_data_r[7]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [23]),
- .Q(stage_2_data_r[8]),
- .R(1'b0));
- FDRE \stage_2_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_data_r_reg[0]_0 [22]),
- .Q(stage_2_data_r[9]),
- .R(1'b0));
- FDRE stage_2_end_after_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_3),
- .Q(stage_2_end_after_start_r),
- .R(RESET));
- FDRE stage_2_end_before_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_2),
- .Q(stage_2_end_before_start_r),
- .R(RESET));
- FDRE stage_2_frame_err_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_6),
- .Q(stage_2_frame_err_r),
- .R(RESET));
- north_channel_north_channel_LEFT_ALIGN_CONTROL stage_2_left_align_control_i
- (.MUX_SELECT(MUX_SELECT),
- .mux_select_c(mux_select_c),
- .user_clk(user_clk));
- FDRE stage_2_pad_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_pad_r),
- .Q(stage_2_pad_r),
- .R(1'b0));
- FDRE stage_2_start_with_data_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_1_rx_ll_deframer_i_n_1),
- .Q(stage_2_start_with_data_r),
- .R(RESET));
- north_channel_north_channel_VALID_DATA_COUNTER_1 stage_2_valid_data_counter_i
- (.\COUNT_Buffer_reg[0]_0 ({stage_1_rx_ll_deframer_i_n_4,stage_1_rx_ll_deframer_i_n_5}),
- .D({ce_command_c[0],ce_command_c[1]}),
- .Q(stage_2_data_v_count_r),
- .RESET(RESET),
- .\STORAGE_CE_Buffer_reg[0] ({stage_3_storage_count_r[0],stage_3_storage_count_r[1]}),
- .end_storage_r0(end_storage_r0),
- .end_storage_r_reg(stage_2_valid_data_counter_i_n_3),
- .stage_2_end_after_start_r(stage_2_end_after_start_r),
- .stage_2_end_before_start_r(stage_2_end_before_start_r),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .std_bool2_in(std_bool2_in),
- .std_bool6_in(std_bool6_in),
- .user_clk(user_clk));
- north_channel_north_channel_LEFT_ALIGN_MUX stage_3_left_align_datapath_mux_i
- (.D({stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,stage_3_left_align_datapath_mux_i_n_32,stage_3_left_align_datapath_mux_i_n_33,stage_3_left_align_datapath_mux_i_n_34,stage_3_left_align_datapath_mux_i_n_35,stage_3_left_align_datapath_mux_i_n_36,stage_3_left_align_datapath_mux_i_n_37,stage_3_left_align_datapath_mux_i_n_38,stage_3_left_align_datapath_mux_i_n_39,stage_3_left_align_datapath_mux_i_n_40,stage_3_left_align_datapath_mux_i_n_41,stage_3_left_align_datapath_mux_i_n_42,stage_3_left_align_datapath_mux_i_n_43,stage_3_left_align_datapath_mux_i_n_44,stage_3_left_align_datapath_mux_i_n_45,stage_3_left_align_datapath_mux_i_n_46,stage_3_left_align_datapath_mux_i_n_47}),
- .\MUXED_DATA_Buffer_reg[0]_0 ({MUXED_DATA_Buffer[0],MUXED_DATA_Buffer[1],MUXED_DATA_Buffer[2],MUXED_DATA_Buffer[3],MUXED_DATA_Buffer[4],MUXED_DATA_Buffer[5],MUXED_DATA_Buffer[6],MUXED_DATA_Buffer[7],MUXED_DATA_Buffer[8],MUXED_DATA_Buffer[9],MUXED_DATA_Buffer[10],MUXED_DATA_Buffer[11],MUXED_DATA_Buffer[12],MUXED_DATA_Buffer[13],MUXED_DATA_Buffer[14],MUXED_DATA_Buffer[15]}),
- .MUX_SELECT(MUX_SELECT),
- .Q({stage_2_data_r[0],stage_2_data_r[1],stage_2_data_r[2],stage_2_data_r[3],stage_2_data_r[4],stage_2_data_r[5],stage_2_data_r[6],stage_2_data_r[7],stage_2_data_r[8],stage_2_data_r[9],stage_2_data_r[10],stage_2_data_r[11],stage_2_data_r[12],stage_2_data_r[13],stage_2_data_r[14],stage_2_data_r[15],stage_2_data_r[16],stage_2_data_r[17],stage_2_data_r[18],stage_2_data_r[19],stage_2_data_r[20],stage_2_data_r[21],stage_2_data_r[22],stage_2_data_r[23],stage_2_data_r[24],stage_2_data_r[25],stage_2_data_r[26],stage_2_data_r[27],stage_2_data_r[28],stage_2_data_r[29],stage_2_data_r[30],stage_2_data_r[31]}),
- .STORAGE_SELECT_Buffer({STORAGE_SELECT_Buffer[4],STORAGE_SELECT_Buffer[9]}),
- .user_clk(user_clk));
- north_channel_north_channel_OUTPUT_SWITCH_CONTROL stage_3_output_switch_control_i
- (.OUTPUT_SELECT_Buffer(OUTPUT_SELECT_Buffer),
- .output_select_c(output_select_c),
- .user_clk(user_clk));
- north_channel_north_channel_STORAGE_CE_CONTROL stage_3_storage_ce_control_i
- (.D({ce_command_c[0],ce_command_c[1]}),
- .Q({p_0_in0,stage_3_storage_ce_control_i_n_1}),
- .RESET(RESET),
- .user_clk(user_clk));
- north_channel_north_channel_STORAGE_COUNT_CONTROL stage_3_storage_count_control_i
- (.D({stage_2_valid_data_counter_i_n_3,sideband_output_i_n_5}),
- .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
- .Q({stage_3_storage_count_r[0],stage_3_storage_count_r[1]}),
- .SR(sideband_output_i_n_1),
- .end_storage_r_reg(stage_3_storage_count_control_i_n_4),
- .output_select_c(output_select_c),
- .stage_2_end_after_start_r(stage_2_end_after_start_r),
- .stage_2_end_before_start_r(stage_2_end_before_start_r),
- .stage_2_frame_err_r(stage_2_frame_err_r),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .std_bool2_in(std_bool2_in),
- .user_clk(user_clk));
- north_channel_north_channel_STORAGE_SWITCH_CONTROL stage_3_storage_switch_control_i
- (.Q(stage_3_storage_count_r[1]),
- .STORAGE_SELECT_Buffer({STORAGE_SELECT_Buffer[4],STORAGE_SELECT_Buffer[9]}),
- .stage_2_start_with_data_r(stage_2_start_with_data_r),
- .stage_3_end_storage_r(stage_3_end_storage_r),
- .user_clk(user_clk));
- north_channel_north_channel_STORAGE_MUX stage_4_storage_mux_i
- (.D({stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,stage_3_left_align_datapath_mux_i_n_32,stage_3_left_align_datapath_mux_i_n_33,stage_3_left_align_datapath_mux_i_n_34,stage_3_left_align_datapath_mux_i_n_35,stage_3_left_align_datapath_mux_i_n_36,stage_3_left_align_datapath_mux_i_n_37,stage_3_left_align_datapath_mux_i_n_38,stage_3_left_align_datapath_mux_i_n_39,stage_3_left_align_datapath_mux_i_n_40,stage_3_left_align_datapath_mux_i_n_41,stage_3_left_align_datapath_mux_i_n_42,stage_3_left_align_datapath_mux_i_n_43,stage_3_left_align_datapath_mux_i_n_44,stage_3_left_align_datapath_mux_i_n_45,stage_3_left_align_datapath_mux_i_n_46,stage_3_left_align_datapath_mux_i_n_47}),
- .E({p_0_in0,stage_3_storage_ce_control_i_n_1}),
- .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31]}),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_RX_LL_UFC_DATAPATH" *)
-module north_channel_north_channel_RX_LL_UFC_DATAPATH
- (\stage_1_data_r_reg[0]_0 ,
- M_AXI_UFC_RX_TVALID,
- M_AXI_UFC_RX_TDATA,
- M_AXI_UFC_RX_TKEEP,
- M_AXI_UFC_RX_TLAST,
- user_clk,
- RESET,
- UFC_START,
- barrel_shifter_control_i,
- \stage_1_data_r_reg[0]_1 ,
- \stage_1_data_r_reg[1]_0 ,
- \stage_1_data_r_reg[2]_0 ,
- \stage_1_data_r_reg[3]_0 ,
- \stage_1_data_r_reg[4]_0 ,
- \stage_1_data_r_reg[5]_0 ,
- \stage_1_data_r_reg[6]_0 ,
- \stage_1_data_r_reg[7]_0 ,
- \stage_1_data_r_reg[8]_0 ,
- \stage_1_data_r_reg[9]_0 ,
- \stage_1_data_r_reg[10]_0 ,
- \stage_1_data_r_reg[11]_0 ,
- \stage_1_data_r_reg[12]_0 ,
- \stage_1_data_r_reg[13]_0 ,
- \stage_1_data_r_reg[14]_0 ,
- \stage_1_data_r_reg[15]_0 ,
- \stage_1_data_r_reg[16]_0 ,
- \stage_1_data_r_reg[17]_0 ,
- \stage_1_data_r_reg[18]_0 ,
- \stage_1_data_r_reg[19]_0 ,
- \stage_1_data_r_reg[20]_0 ,
- \stage_1_data_r_reg[21]_0 ,
- \stage_1_data_r_reg[22]_0 ,
- \stage_1_data_r_reg[23]_0 ,
- \stage_1_data_r_reg[24]_0 ,
- \stage_1_data_r_reg[25]_0 ,
- \stage_1_data_r_reg[26]_0 ,
- \stage_1_data_r_reg[27]_0 ,
- \stage_1_data_r_reg[28]_0 ,
- \stage_1_data_r_reg[29]_0 ,
- \stage_1_data_r_reg[30]_0 ,
- \stage_1_data_r_reg[31]_0 ,
- Q);
- output [31:0]\stage_1_data_r_reg[0]_0 ;
- output M_AXI_UFC_RX_TVALID;
- output [0:31]M_AXI_UFC_RX_TDATA;
- output [0:0]M_AXI_UFC_RX_TKEEP;
- output M_AXI_UFC_RX_TLAST;
- input user_clk;
- input RESET;
- input UFC_START;
- input barrel_shifter_control_i;
- input \stage_1_data_r_reg[0]_1 ;
- input \stage_1_data_r_reg[1]_0 ;
- input \stage_1_data_r_reg[2]_0 ;
- input \stage_1_data_r_reg[3]_0 ;
- input \stage_1_data_r_reg[4]_0 ;
- input \stage_1_data_r_reg[5]_0 ;
- input \stage_1_data_r_reg[6]_0 ;
- input \stage_1_data_r_reg[7]_0 ;
- input \stage_1_data_r_reg[8]_0 ;
- input \stage_1_data_r_reg[9]_0 ;
- input \stage_1_data_r_reg[10]_0 ;
- input \stage_1_data_r_reg[11]_0 ;
- input \stage_1_data_r_reg[12]_0 ;
- input \stage_1_data_r_reg[13]_0 ;
- input \stage_1_data_r_reg[14]_0 ;
- input \stage_1_data_r_reg[15]_0 ;
- input \stage_1_data_r_reg[16]_0 ;
- input \stage_1_data_r_reg[17]_0 ;
- input \stage_1_data_r_reg[18]_0 ;
- input \stage_1_data_r_reg[19]_0 ;
- input \stage_1_data_r_reg[20]_0 ;
- input \stage_1_data_r_reg[21]_0 ;
- input \stage_1_data_r_reg[22]_0 ;
- input \stage_1_data_r_reg[23]_0 ;
- input \stage_1_data_r_reg[24]_0 ;
- input \stage_1_data_r_reg[25]_0 ;
- input \stage_1_data_r_reg[26]_0 ;
- input \stage_1_data_r_reg[27]_0 ;
- input \stage_1_data_r_reg[28]_0 ;
- input \stage_1_data_r_reg[29]_0 ;
- input \stage_1_data_r_reg[30]_0 ;
- input \stage_1_data_r_reg[31]_0 ;
- input [1:0]Q;
-
- wire BARREL_SHIFTER_CONTROL_Buffer;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [0:0]M_AXI_UFC_RX_TKEEP;
- wire M_AXI_UFC_RX_TLAST;
- wire M_AXI_UFC_RX_TVALID;
- wire [1:0]Q;
- wire RESET;
- wire [0:31]SHIFTED_DATA_Buffer;
- wire UFC_EOF_N_Buffer;
- wire [1:0]UFC_OUTPUT_SELECT_Buffer;
- wire [0:0]UFC_RX_REM_Buffer;
- wire UFC_RX_SRC_RDY_N_Buffer;
- wire UFC_SRC_RDY_N_Buffer;
- wire UFC_START;
- wire [2:5]UFC_STORAGE_SELECT_Buffer;
- wire [0:1]barrel_shifted_count_r;
- wire barrel_shifter_control_i;
- wire rx_ufc_eof;
- wire [31:0]\stage_1_data_r_reg[0]_0 ;
- wire \stage_1_data_r_reg[0]_1 ;
- wire \stage_1_data_r_reg[10]_0 ;
- wire \stage_1_data_r_reg[11]_0 ;
- wire \stage_1_data_r_reg[12]_0 ;
- wire \stage_1_data_r_reg[13]_0 ;
- wire \stage_1_data_r_reg[14]_0 ;
- wire \stage_1_data_r_reg[15]_0 ;
- wire \stage_1_data_r_reg[16]_0 ;
- wire \stage_1_data_r_reg[17]_0 ;
- wire \stage_1_data_r_reg[18]_0 ;
- wire \stage_1_data_r_reg[19]_0 ;
- wire \stage_1_data_r_reg[1]_0 ;
- wire \stage_1_data_r_reg[20]_0 ;
- wire \stage_1_data_r_reg[21]_0 ;
- wire \stage_1_data_r_reg[22]_0 ;
- wire \stage_1_data_r_reg[23]_0 ;
- wire \stage_1_data_r_reg[24]_0 ;
- wire \stage_1_data_r_reg[25]_0 ;
- wire \stage_1_data_r_reg[26]_0 ;
- wire \stage_1_data_r_reg[27]_0 ;
- wire \stage_1_data_r_reg[28]_0 ;
- wire \stage_1_data_r_reg[29]_0 ;
- wire \stage_1_data_r_reg[2]_0 ;
- wire \stage_1_data_r_reg[30]_0 ;
- wire \stage_1_data_r_reg[31]_0 ;
- wire \stage_1_data_r_reg[3]_0 ;
- wire \stage_1_data_r_reg[4]_0 ;
- wire \stage_1_data_r_reg[5]_0 ;
- wire \stage_1_data_r_reg[6]_0 ;
- wire \stage_1_data_r_reg[7]_0 ;
- wire \stage_1_data_r_reg[8]_0 ;
- wire \stage_1_data_r_reg[9]_0 ;
- wire stage_1_ufc_start_r;
- wire [1:1]storage_count_2x_c;
- wire ufc_barrel_shifter_i_n_32;
- wire ufc_barrel_shifter_i_n_33;
- wire ufc_barrel_shifter_i_n_34;
- wire ufc_barrel_shifter_i_n_35;
- wire ufc_barrel_shifter_i_n_36;
- wire ufc_barrel_shifter_i_n_37;
- wire ufc_barrel_shifter_i_n_38;
- wire ufc_barrel_shifter_i_n_39;
- wire ufc_barrel_shifter_i_n_40;
- wire ufc_barrel_shifter_i_n_41;
- wire ufc_barrel_shifter_i_n_42;
- wire ufc_barrel_shifter_i_n_43;
- wire ufc_barrel_shifter_i_n_44;
- wire ufc_barrel_shifter_i_n_45;
- wire ufc_barrel_shifter_i_n_46;
- wire ufc_barrel_shifter_i_n_47;
- wire ufc_sideband_output_i_n_0;
- wire ufc_storage_count_control_i_n_0;
- wire ufc_storage_count_control_i_n_1;
- wire ufc_storage_count_control_i_n_3;
- wire ufc_storage_count_control_i_n_4;
- wire ufc_storage_count_control_i_n_5;
- wire ufc_storage_count_control_i_n_6;
- wire ufc_storage_count_control_i_n_7;
- wire ufc_storage_mux_i_n_0;
- wire ufc_storage_mux_i_n_1;
- wire ufc_storage_mux_i_n_10;
- wire ufc_storage_mux_i_n_11;
- wire ufc_storage_mux_i_n_12;
- wire ufc_storage_mux_i_n_13;
- wire ufc_storage_mux_i_n_14;
- wire ufc_storage_mux_i_n_15;
- wire ufc_storage_mux_i_n_16;
- wire ufc_storage_mux_i_n_17;
- wire ufc_storage_mux_i_n_18;
- wire ufc_storage_mux_i_n_19;
- wire ufc_storage_mux_i_n_2;
- wire ufc_storage_mux_i_n_20;
- wire ufc_storage_mux_i_n_21;
- wire ufc_storage_mux_i_n_22;
- wire ufc_storage_mux_i_n_23;
- wire ufc_storage_mux_i_n_24;
- wire ufc_storage_mux_i_n_25;
- wire ufc_storage_mux_i_n_26;
- wire ufc_storage_mux_i_n_27;
- wire ufc_storage_mux_i_n_28;
- wire ufc_storage_mux_i_n_29;
- wire ufc_storage_mux_i_n_3;
- wire ufc_storage_mux_i_n_30;
- wire ufc_storage_mux_i_n_31;
- wire ufc_storage_mux_i_n_4;
- wire ufc_storage_mux_i_n_5;
- wire ufc_storage_mux_i_n_6;
- wire ufc_storage_mux_i_n_7;
- wire ufc_storage_mux_i_n_8;
- wire ufc_storage_mux_i_n_9;
- wire \ufc_storage_switch_control_i/_n_0 ;
- wire ufc_storage_switch_control_i_n_0;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair263" *)
- LUT2 #(
- .INIT(4'hE))
- \M_AXI_UFC_RX_TKEEP[3]_INST_0
- (.I0(rx_ufc_eof),
- .I1(UFC_RX_REM_Buffer),
- .O(M_AXI_UFC_RX_TKEEP));
- (* SOFT_HLUTNM = "soft_lutpair263" *)
- LUT1 #(
- .INIT(2'h1))
- M_AXI_UFC_RX_TLAST_INST_0
- (.I0(rx_ufc_eof),
- .O(M_AXI_UFC_RX_TLAST));
- LUT1 #(
- .INIT(2'h1))
- M_AXI_UFC_RX_TVALID_INST_0
- (.I0(UFC_RX_SRC_RDY_N_Buffer),
- .O(M_AXI_UFC_RX_TVALID));
- FDRE UFC_RX_EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_EOF_N_Buffer),
- .Q(rx_ufc_eof),
- .R(1'b0));
- FDRE \UFC_RX_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(ufc_sideband_output_i_n_0),
- .Q(UFC_RX_REM_Buffer),
- .R(1'b0));
- FDSE UFC_RX_SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_SRC_RDY_N_Buffer),
- .Q(UFC_RX_SRC_RDY_N_Buffer),
- .S(RESET));
- FDRE \stage_1_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[0]_1 ),
- .Q(\stage_1_data_r_reg[0]_0 [31]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[10]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [21]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[11]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [20]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[12]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [19]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[13]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [18]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[14]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [17]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[15]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [16]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[16]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [15]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[17]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [14]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[18]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [13]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[19]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [12]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[1]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [30]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[20]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [11]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[21]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [10]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[22]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [9]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[23]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [8]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[24]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [7]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[25]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [6]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[26]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [5]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[27]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [4]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[28]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [3]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[29]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [2]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[2]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [29]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[30]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[31]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[3]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [28]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[4]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [27]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[5]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [26]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[6]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [25]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[7]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [24]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[8]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [23]),
- .R(1'b0));
- FDRE \stage_1_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_data_r_reg[9]_0 ),
- .Q(\stage_1_data_r_reg[0]_0 [22]),
- .R(1'b0));
- FDRE stage_1_ufc_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_START),
- .Q(stage_1_ufc_start_r),
- .R(RESET));
- north_channel_north_channel_UFC_BARREL_SHIFTER_CONTROL ufc_barrel_shifter_control_i
- (.BARREL_SHIFTER_CONTROL_Buffer(BARREL_SHIFTER_CONTROL_Buffer),
- .barrel_shifter_control_i(barrel_shifter_control_i),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_BARREL_SHIFTER ufc_barrel_shifter_i
- (.BARREL_SHIFTER_CONTROL_Buffer(BARREL_SHIFTER_CONTROL_Buffer),
- .\MUXED_DATA_Buffer_reg[16] (ufc_storage_mux_i_n_16),
- .\MUXED_DATA_Buffer_reg[17] (ufc_storage_mux_i_n_17),
- .\MUXED_DATA_Buffer_reg[18] (ufc_storage_mux_i_n_18),
- .\MUXED_DATA_Buffer_reg[19] (ufc_storage_mux_i_n_19),
- .\MUXED_DATA_Buffer_reg[20] (ufc_storage_mux_i_n_20),
- .\MUXED_DATA_Buffer_reg[21] (ufc_storage_mux_i_n_21),
- .\MUXED_DATA_Buffer_reg[22] (ufc_storage_mux_i_n_22),
- .\MUXED_DATA_Buffer_reg[23] (ufc_storage_mux_i_n_23),
- .\MUXED_DATA_Buffer_reg[24] (ufc_storage_mux_i_n_24),
- .\MUXED_DATA_Buffer_reg[25] (ufc_storage_mux_i_n_25),
- .\MUXED_DATA_Buffer_reg[26] (ufc_storage_mux_i_n_26),
- .\MUXED_DATA_Buffer_reg[27] (ufc_storage_mux_i_n_27),
- .\MUXED_DATA_Buffer_reg[28] (ufc_storage_mux_i_n_28),
- .\MUXED_DATA_Buffer_reg[29] (ufc_storage_mux_i_n_29),
- .\MUXED_DATA_Buffer_reg[30] (ufc_storage_mux_i_n_30),
- .\MUXED_DATA_Buffer_reg[31] (ufc_storage_mux_i_n_31),
- .SHIFTED_DATA_Buffer(SHIFTED_DATA_Buffer),
- .\SHIFTED_DATA_Buffer_reg[0]_0 (ufc_barrel_shifter_i_n_47),
- .\SHIFTED_DATA_Buffer_reg[0]_1 (\stage_1_data_r_reg[0]_0 ),
- .\SHIFTED_DATA_Buffer_reg[10]_0 (ufc_barrel_shifter_i_n_37),
- .\SHIFTED_DATA_Buffer_reg[11]_0 (ufc_barrel_shifter_i_n_36),
- .\SHIFTED_DATA_Buffer_reg[12]_0 (ufc_barrel_shifter_i_n_35),
- .\SHIFTED_DATA_Buffer_reg[13]_0 (ufc_barrel_shifter_i_n_34),
- .\SHIFTED_DATA_Buffer_reg[14]_0 (ufc_barrel_shifter_i_n_33),
- .\SHIFTED_DATA_Buffer_reg[15]_0 (ufc_barrel_shifter_i_n_32),
- .\SHIFTED_DATA_Buffer_reg[1]_0 (ufc_barrel_shifter_i_n_46),
- .\SHIFTED_DATA_Buffer_reg[2]_0 (ufc_barrel_shifter_i_n_45),
- .\SHIFTED_DATA_Buffer_reg[3]_0 (ufc_barrel_shifter_i_n_44),
- .\SHIFTED_DATA_Buffer_reg[4]_0 (ufc_barrel_shifter_i_n_43),
- .\SHIFTED_DATA_Buffer_reg[5]_0 (ufc_barrel_shifter_i_n_42),
- .\SHIFTED_DATA_Buffer_reg[6]_0 (ufc_barrel_shifter_i_n_41),
- .\SHIFTED_DATA_Buffer_reg[7]_0 (ufc_barrel_shifter_i_n_40),
- .\SHIFTED_DATA_Buffer_reg[8]_0 (ufc_barrel_shifter_i_n_39),
- .\SHIFTED_DATA_Buffer_reg[9]_0 (ufc_barrel_shifter_i_n_38),
- .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer[0]),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_OUTPUT_MUX ufc_output_mux_i
- (.D({ufc_storage_mux_i_n_0,ufc_storage_mux_i_n_1,ufc_storage_mux_i_n_2,ufc_storage_mux_i_n_3,ufc_storage_mux_i_n_4,ufc_storage_mux_i_n_5,ufc_storage_mux_i_n_6,ufc_storage_mux_i_n_7,ufc_storage_mux_i_n_8,ufc_storage_mux_i_n_9,ufc_storage_mux_i_n_10,ufc_storage_mux_i_n_11,ufc_storage_mux_i_n_12,ufc_storage_mux_i_n_13,ufc_storage_mux_i_n_14,ufc_storage_mux_i_n_15}),
- .\MUXED_DATA_Buffer_reg[16]_0 (ufc_barrel_shifter_i_n_47),
- .\MUXED_DATA_Buffer_reg[17]_0 (ufc_barrel_shifter_i_n_46),
- .\MUXED_DATA_Buffer_reg[18]_0 (ufc_barrel_shifter_i_n_45),
- .\MUXED_DATA_Buffer_reg[19]_0 (ufc_barrel_shifter_i_n_44),
- .\MUXED_DATA_Buffer_reg[20]_0 (ufc_barrel_shifter_i_n_43),
- .\MUXED_DATA_Buffer_reg[21]_0 (ufc_barrel_shifter_i_n_42),
- .\MUXED_DATA_Buffer_reg[22]_0 (ufc_barrel_shifter_i_n_41),
- .\MUXED_DATA_Buffer_reg[23]_0 (ufc_barrel_shifter_i_n_40),
- .\MUXED_DATA_Buffer_reg[24]_0 (ufc_barrel_shifter_i_n_39),
- .\MUXED_DATA_Buffer_reg[25]_0 (ufc_barrel_shifter_i_n_38),
- .\MUXED_DATA_Buffer_reg[26]_0 (ufc_barrel_shifter_i_n_37),
- .\MUXED_DATA_Buffer_reg[27]_0 (ufc_barrel_shifter_i_n_36),
- .\MUXED_DATA_Buffer_reg[28]_0 (ufc_barrel_shifter_i_n_35),
- .\MUXED_DATA_Buffer_reg[29]_0 (ufc_barrel_shifter_i_n_34),
- .\MUXED_DATA_Buffer_reg[30]_0 (ufc_barrel_shifter_i_n_33),
- .\MUXED_DATA_Buffer_reg[31]_0 (ufc_barrel_shifter_i_n_32),
- .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
- .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer[1]),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_OUTPUT_SWITCH_CONTROL ufc_output_switch_control_i
- (.Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
- .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer),
- .\UFC_OUTPUT_SELECT_Buffer_reg[4]_0 (ufc_storage_count_control_i_n_6),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_SIDEBAND_OUTPUT ufc_sideband_output_i
- (.RESET(RESET),
- .UFC_EOF_N_Buffer(UFC_EOF_N_Buffer),
- .UFC_EOF_N_Buffer_reg_0(ufc_storage_count_control_i_n_0),
- .\UFC_REM_Buffer_reg[0]_0 (ufc_sideband_output_i_n_0),
- .\UFC_REM_Buffer_reg[0]_1 (ufc_storage_count_control_i_n_7),
- .UFC_SRC_RDY_N_Buffer(UFC_SRC_RDY_N_Buffer),
- .UFC_SRC_RDY_N_Buffer_reg_0(ufc_storage_count_control_i_n_6),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_STORAGE_COUNT_CONTROL ufc_storage_count_control_i
- (.D(ufc_storage_count_control_i_n_5),
- .Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
- .RESET(RESET),
- .UFC_EOF_N_Buffer_reg({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
- .stage_1_ufc_start_r(stage_1_ufc_start_r),
- .stage_1_ufc_start_r_reg(ufc_storage_count_control_i_n_0),
- .stage_1_ufc_start_r_reg_0(ufc_storage_count_control_i_n_7),
- .\storage_count_r_reg[0]_0 (ufc_storage_count_control_i_n_6),
- .\storage_count_r_reg[1]_0 (ufc_storage_count_control_i_n_3),
- .\storage_count_r_reg[1]_1 (ufc_storage_count_control_i_n_4),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_STORAGE_MUX ufc_storage_mux_i
- (.D({ufc_storage_mux_i_n_0,ufc_storage_mux_i_n_1,ufc_storage_mux_i_n_2,ufc_storage_mux_i_n_3,ufc_storage_mux_i_n_4,ufc_storage_mux_i_n_5,ufc_storage_mux_i_n_6,ufc_storage_mux_i_n_7,ufc_storage_mux_i_n_8,ufc_storage_mux_i_n_9,ufc_storage_mux_i_n_10,ufc_storage_mux_i_n_11,ufc_storage_mux_i_n_12,ufc_storage_mux_i_n_13,ufc_storage_mux_i_n_14,ufc_storage_mux_i_n_15}),
- .\MUXED_DATA_Buffer_reg[0]_0 (ufc_storage_switch_control_i_n_0),
- .\MUXED_DATA_Buffer_reg[16]_0 (ufc_storage_mux_i_n_16),
- .\MUXED_DATA_Buffer_reg[17]_0 (ufc_storage_mux_i_n_17),
- .\MUXED_DATA_Buffer_reg[18]_0 (ufc_storage_mux_i_n_18),
- .\MUXED_DATA_Buffer_reg[19]_0 (ufc_storage_mux_i_n_19),
- .\MUXED_DATA_Buffer_reg[20]_0 (ufc_storage_mux_i_n_20),
- .\MUXED_DATA_Buffer_reg[21]_0 (ufc_storage_mux_i_n_21),
- .\MUXED_DATA_Buffer_reg[22]_0 (ufc_storage_mux_i_n_22),
- .\MUXED_DATA_Buffer_reg[23]_0 (ufc_storage_mux_i_n_23),
- .\MUXED_DATA_Buffer_reg[24]_0 (ufc_storage_mux_i_n_24),
- .\MUXED_DATA_Buffer_reg[25]_0 (ufc_storage_mux_i_n_25),
- .\MUXED_DATA_Buffer_reg[26]_0 (ufc_storage_mux_i_n_26),
- .\MUXED_DATA_Buffer_reg[27]_0 (ufc_storage_mux_i_n_27),
- .\MUXED_DATA_Buffer_reg[28]_0 (ufc_storage_mux_i_n_28),
- .\MUXED_DATA_Buffer_reg[29]_0 (ufc_storage_mux_i_n_29),
- .\MUXED_DATA_Buffer_reg[30]_0 (ufc_storage_mux_i_n_30),
- .\MUXED_DATA_Buffer_reg[31]_0 (ufc_storage_mux_i_n_31),
- .SHIFTED_DATA_Buffer(SHIFTED_DATA_Buffer),
- .UFC_STORAGE_SELECT_Buffer({UFC_STORAGE_SELECT_Buffer[2],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[5]}),
- .user_clk(user_clk));
- north_channel_north_channel_UFC_STORAGE_SWITCH_CONTROL ufc_storage_switch_control_i
- (.D(ufc_storage_count_control_i_n_5),
- .Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
- .\UFC_STORAGE_SELECT_Buffer_reg[0]_0 (ufc_storage_switch_control_i_n_0),
- .\UFC_STORAGE_SELECT_Buffer_reg[0]_1 (ufc_storage_count_control_i_n_3),
- .\UFC_STORAGE_SELECT_Buffer_reg[1]_0 (ufc_storage_count_control_i_n_4),
- .\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ({UFC_STORAGE_SELECT_Buffer[2],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[5]}),
- .\UFC_STORAGE_SELECT_Buffer_reg[4]_0 (\ufc_storage_switch_control_i/_n_0 ),
- .\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
- .stage_1_ufc_start_r(stage_1_ufc_start_r),
- .user_clk(user_clk));
- LUT1 #(
- .INIT(2'h1))
- \ufc_storage_switch_control_i/
- (.I0(ufc_storage_count_control_i_n_1),
- .O(\ufc_storage_switch_control_i/_n_0 ));
- north_channel_north_channel_VALID_DATA_COUNTER ufc_valid_data_counter
- (.\COUNT_Buffer_reg[0]_0 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
- .Q(Q),
- .RESET(RESET),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SCRAMBLER" *)
-module north_channel_north_channel_SCRAMBLER
- (SS,
- Q,
- \DOUT_reg[15]_0 ,
- gen_v_r2,
- reset_lanes_i,
- \lfsr_reg[15]_0 ,
- clear_nxt2,
- E,
- user_clk,
- D);
- output [0:0]SS;
- output [15:0]Q;
- output [15:0]\DOUT_reg[15]_0 ;
- input gen_v_r2;
- input reset_lanes_i;
- input \lfsr_reg[15]_0 ;
- input clear_nxt2;
- input [0:0]E;
- input user_clk;
- input [15:0]D;
-
- wire [15:0]D;
- wire [15:0]\DOUT_reg[15]_0 ;
- wire [0:0]E;
- wire [15:0]Q;
- wire [0:0]SS;
- wire clear_nxt2;
- wire gen_v_r2;
- wire [12:3]lfsrNext;
- wire \lfsr_reg[15]_0 ;
- wire reset_lanes_i;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(D[0]),
- .Q(\DOUT_reg[15]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(D[10]),
- .Q(\DOUT_reg[15]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(D[11]),
- .Q(\DOUT_reg[15]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(D[12]),
- .Q(\DOUT_reg[15]_0 [12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(D[13]),
- .Q(\DOUT_reg[15]_0 [13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(D[14]),
- .Q(\DOUT_reg[15]_0 [14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(D[15]),
- .Q(\DOUT_reg[15]_0 [15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(D[1]),
- .Q(\DOUT_reg[15]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(D[2]),
- .Q(\DOUT_reg[15]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(D[3]),
- .Q(\DOUT_reg[15]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(D[4]),
- .Q(\DOUT_reg[15]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(D[5]),
- .Q(\DOUT_reg[15]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(D[6]),
- .Q(\DOUT_reg[15]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(D[7]),
- .Q(\DOUT_reg[15]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(D[8]),
- .Q(\DOUT_reg[15]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(D[9]),
- .Q(\DOUT_reg[15]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair90" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair90" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair89" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- LUT4 #(
- .INIT(16'hFFEF))
- \lfsr[15]_i_1__2
- (.I0(gen_v_r2),
- .I1(reset_lanes_i),
- .I2(\lfsr_reg[15]_0 ),
- .I3(clear_nxt2),
- .O(SS));
- (* SOFT_HLUTNM = "soft_lutpair88" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair91" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair91" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair89" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair88" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SCRAMBLER" *)
-module north_channel_north_channel_SCRAMBLER_2
- (Q,
- \DOUT_reg[15]_0 ,
- SS,
- \DOUT_reg[0]_0 ,
- user_clk,
- \DOUT_reg[15]_1 );
- output [15:0]Q;
- output [15:0]\DOUT_reg[15]_0 ;
- input [0:0]SS;
- input [0:0]\DOUT_reg[0]_0 ;
- input user_clk;
- input [15:0]\DOUT_reg[15]_1 ;
-
- wire [0:0]\DOUT_reg[0]_0 ;
- wire [15:0]\DOUT_reg[15]_0 ;
- wire [15:0]\DOUT_reg[15]_1 ;
- wire [15:0]Q;
- wire [0:0]SS;
- wire [12:3]lfsrNext;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [0]),
- .Q(\DOUT_reg[15]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [10]),
- .Q(\DOUT_reg[15]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [11]),
- .Q(\DOUT_reg[15]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [12]),
- .Q(\DOUT_reg[15]_0 [12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [13]),
- .Q(\DOUT_reg[15]_0 [13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [14]),
- .Q(\DOUT_reg[15]_0 [14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [15]),
- .Q(\DOUT_reg[15]_0 [15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [1]),
- .Q(\DOUT_reg[15]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [2]),
- .Q(\DOUT_reg[15]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [3]),
- .Q(\DOUT_reg[15]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [4]),
- .Q(\DOUT_reg[15]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [5]),
- .Q(\DOUT_reg[15]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [6]),
- .Q(\DOUT_reg[15]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [7]),
- .Q(\DOUT_reg[15]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [8]),
- .Q(\DOUT_reg[15]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(\DOUT_reg[15]_1 [9]),
- .Q(\DOUT_reg[15]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair94" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1__0
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair94" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1__0
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair93" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1__0
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- (* SOFT_HLUTNM = "soft_lutpair92" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1__0
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair95" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1__0
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair95" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1__0
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1__0
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair93" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1__0
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair92" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1__0
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1__0
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SCRAMBLER" *)
-module north_channel_north_channel_SCRAMBLER_3
- (Q,
- rx_pe_data_striped_i,
- \stage_1_data_r_reg[0] ,
- \stage_1_data_r_reg[15] ,
- \stage_1_data_r_reg[11] ,
- \stage_1_data_r_reg[10] ,
- \stage_1_data_r_reg[9] ,
- \stage_1_data_r_reg[8] ,
- SS,
- E,
- user_clk,
- \DOUT_reg[15]_0 );
- output [15:0]Q;
- output [15:0]rx_pe_data_striped_i;
- input [11:0]\stage_1_data_r_reg[0] ;
- input [0:0]\stage_1_data_r_reg[15] ;
- input \stage_1_data_r_reg[11] ;
- input \stage_1_data_r_reg[10] ;
- input \stage_1_data_r_reg[9] ;
- input \stage_1_data_r_reg[8] ;
- input [0:0]SS;
- input [0:0]E;
- input user_clk;
- input [15:0]\DOUT_reg[15]_0 ;
-
- wire [15:0]DOUT;
- wire [15:0]\DOUT_reg[15]_0 ;
- wire [0:0]E;
- wire [15:0]Q;
- wire [0:0]SS;
- wire [12:3]lfsrNext;
- wire [15:0]rx_pe_data_striped_i;
- wire [11:0]\stage_1_data_r_reg[0] ;
- wire \stage_1_data_r_reg[10] ;
- wire \stage_1_data_r_reg[11] ;
- wire [0:0]\stage_1_data_r_reg[15] ;
- wire \stage_1_data_r_reg[8] ;
- wire \stage_1_data_r_reg[9] ;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [0]),
- .Q(DOUT[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [10]),
- .Q(DOUT[10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [11]),
- .Q(DOUT[11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [12]),
- .Q(DOUT[12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [13]),
- .Q(DOUT[13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [14]),
- .Q(DOUT[14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [15]),
- .Q(DOUT[15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [1]),
- .Q(DOUT[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [2]),
- .Q(DOUT[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [3]),
- .Q(DOUT[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [4]),
- .Q(DOUT[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [5]),
- .Q(DOUT[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [6]),
- .Q(DOUT[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [7]),
- .Q(DOUT[7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [8]),
- .Q(DOUT[8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(\DOUT_reg[15]_0 [9]),
- .Q(DOUT[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[0]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [11]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[15]),
- .O(rx_pe_data_striped_i[15]));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[10]_srl2_i_1
- (.I0(\stage_1_data_r_reg[10] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[5]),
- .O(rx_pe_data_striped_i[5]));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[11]_srl2_i_1
- (.I0(\stage_1_data_r_reg[11] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[4]),
- .O(rx_pe_data_striped_i[4]));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[12]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [3]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[3]),
- .O(rx_pe_data_striped_i[3]));
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[13]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [2]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[2]),
- .O(rx_pe_data_striped_i[2]));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[14]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [1]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[1]),
- .O(rx_pe_data_striped_i[1]));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[15]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [0]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[0]),
- .O(rx_pe_data_striped_i[0]));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[1]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [10]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[14]),
- .O(rx_pe_data_striped_i[14]));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[2]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [9]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[13]),
- .O(rx_pe_data_striped_i[13]));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[3]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [8]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[12]),
- .O(rx_pe_data_striped_i[12]));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[4]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [7]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[11]),
- .O(rx_pe_data_striped_i[11]));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[5]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [6]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[10]),
- .O(rx_pe_data_striped_i[10]));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[6]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [5]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[9]),
- .O(rx_pe_data_striped_i[9]));
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[7]_srl2_i_1
- (.I0(\stage_1_data_r_reg[0] [4]),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[8]),
- .O(rx_pe_data_striped_i[8]));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[8]_srl2_i_1
- (.I0(\stage_1_data_r_reg[8] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[7]),
- .O(rx_pe_data_striped_i[7]));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[9]_srl2_i_1
- (.I0(\stage_1_data_r_reg[9] ),
- .I1(\stage_1_data_r_reg[15] ),
- .I2(DOUT[6]),
- .O(rx_pe_data_striped_i[6]));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1__1
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1__1
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1__1
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1__1
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1__1
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1__1
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1__1
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1__1
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1__1
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1__1
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SCRAMBLER" *)
-module north_channel_north_channel_SCRAMBLER_4
- (Q,
- rx_pe_data_striped_i,
- \stage_1_data_r_reg[16] ,
- \stage_1_data_r_reg[31] ,
- \stage_1_data_r_reg[27] ,
- \stage_1_data_r_reg[26] ,
- \stage_1_data_r_reg[25] ,
- \stage_1_data_r_reg[24] ,
- SS,
- \DOUT_reg[0]_0 ,
- user_clk,
- D);
- output [15:0]Q;
- output [15:0]rx_pe_data_striped_i;
- input [11:0]\stage_1_data_r_reg[16] ;
- input [0:0]\stage_1_data_r_reg[31] ;
- input \stage_1_data_r_reg[27] ;
- input \stage_1_data_r_reg[26] ;
- input \stage_1_data_r_reg[25] ;
- input \stage_1_data_r_reg[24] ;
- input [0:0]SS;
- input [0:0]\DOUT_reg[0]_0 ;
- input user_clk;
- input [15:0]D;
-
- wire [15:0]D;
- wire [0:0]\DOUT_reg[0]_0 ;
- wire \DOUT_reg_n_0_[0] ;
- wire \DOUT_reg_n_0_[10] ;
- wire \DOUT_reg_n_0_[11] ;
- wire \DOUT_reg_n_0_[12] ;
- wire \DOUT_reg_n_0_[13] ;
- wire \DOUT_reg_n_0_[14] ;
- wire \DOUT_reg_n_0_[15] ;
- wire \DOUT_reg_n_0_[1] ;
- wire \DOUT_reg_n_0_[2] ;
- wire \DOUT_reg_n_0_[3] ;
- wire \DOUT_reg_n_0_[4] ;
- wire \DOUT_reg_n_0_[5] ;
- wire \DOUT_reg_n_0_[6] ;
- wire \DOUT_reg_n_0_[7] ;
- wire \DOUT_reg_n_0_[8] ;
- wire \DOUT_reg_n_0_[9] ;
- wire [15:0]Q;
- wire [0:0]SS;
- wire [12:3]lfsrNext;
- wire [15:0]rx_pe_data_striped_i;
- wire [11:0]\stage_1_data_r_reg[16] ;
- wire \stage_1_data_r_reg[24] ;
- wire \stage_1_data_r_reg[25] ;
- wire \stage_1_data_r_reg[26] ;
- wire \stage_1_data_r_reg[27] ;
- wire [0:0]\stage_1_data_r_reg[31] ;
- wire user_clk;
-
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[0]),
- .Q(\DOUT_reg_n_0_[0] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[10]),
- .Q(\DOUT_reg_n_0_[10] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[11]),
- .Q(\DOUT_reg_n_0_[11] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[12]),
- .Q(\DOUT_reg_n_0_[12] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[13]),
- .Q(\DOUT_reg_n_0_[13] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[14]),
- .Q(\DOUT_reg_n_0_[14] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[15]),
- .Q(\DOUT_reg_n_0_[15] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[1]),
- .Q(\DOUT_reg_n_0_[1] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[2]),
- .Q(\DOUT_reg_n_0_[2] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[3]),
- .Q(\DOUT_reg_n_0_[3] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[4]),
- .Q(\DOUT_reg_n_0_[4] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[5]),
- .Q(\DOUT_reg_n_0_[5] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[6]),
- .Q(\DOUT_reg_n_0_[6] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[7]),
- .Q(\DOUT_reg_n_0_[7] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[8]),
- .Q(\DOUT_reg_n_0_[8] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \DOUT_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(D[9]),
- .Q(\DOUT_reg_n_0_[9] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair73" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[16]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [11]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[15] ),
- .O(rx_pe_data_striped_i[15]));
- (* SOFT_HLUTNM = "soft_lutpair72" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[17]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [10]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[14] ),
- .O(rx_pe_data_striped_i[14]));
- (* SOFT_HLUTNM = "soft_lutpair73" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[18]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [9]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[13] ),
- .O(rx_pe_data_striped_i[13]));
- (* SOFT_HLUTNM = "soft_lutpair71" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[19]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [8]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[12] ),
- .O(rx_pe_data_striped_i[12]));
- (* SOFT_HLUTNM = "soft_lutpair72" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[20]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [7]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[11] ),
- .O(rx_pe_data_striped_i[11]));
- (* SOFT_HLUTNM = "soft_lutpair71" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[21]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [6]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[10] ),
- .O(rx_pe_data_striped_i[10]));
- (* SOFT_HLUTNM = "soft_lutpair70" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[22]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [5]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[9] ),
- .O(rx_pe_data_striped_i[9]));
- (* SOFT_HLUTNM = "soft_lutpair68" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[23]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [4]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[8] ),
- .O(rx_pe_data_striped_i[8]));
- (* SOFT_HLUTNM = "soft_lutpair70" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[24]_srl2_i_1
- (.I0(\stage_1_data_r_reg[24] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[7] ),
- .O(rx_pe_data_striped_i[7]));
- (* SOFT_HLUTNM = "soft_lutpair66" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[25]_srl2_i_1
- (.I0(\stage_1_data_r_reg[25] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[6] ),
- .O(rx_pe_data_striped_i[6]));
- (* SOFT_HLUTNM = "soft_lutpair67" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[26]_srl2_i_1
- (.I0(\stage_1_data_r_reg[26] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[5] ),
- .O(rx_pe_data_striped_i[5]));
- (* SOFT_HLUTNM = "soft_lutpair69" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[27]_srl2_i_1
- (.I0(\stage_1_data_r_reg[27] ),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[4] ),
- .O(rx_pe_data_striped_i[4]));
- (* SOFT_HLUTNM = "soft_lutpair69" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[28]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [3]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[3] ),
- .O(rx_pe_data_striped_i[3]));
- (* SOFT_HLUTNM = "soft_lutpair68" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[29]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [2]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[2] ),
- .O(rx_pe_data_striped_i[2]));
- (* SOFT_HLUTNM = "soft_lutpair67" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[30]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [1]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[1] ),
- .O(rx_pe_data_striped_i[1]));
- (* SOFT_HLUTNM = "soft_lutpair66" *)
- LUT3 #(
- .INIT(8'hB8))
- \PDU_DATA_Buffer_reg[31]_srl2_i_1
- (.I0(\stage_1_data_r_reg[16] [0]),
- .I1(\stage_1_data_r_reg[31] ),
- .I2(\DOUT_reg_n_0_[0] ),
- .O(rx_pe_data_striped_i[0]));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[10]_i_1__2
- (.I0(Q[15]),
- .I1(Q[2]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[10]));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[11]_i_1__2
- (.I0(Q[15]),
- .I1(Q[14]),
- .I2(Q[3]),
- .O(lfsrNext[11]));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[12]_i_1__2
- (.I0(Q[15]),
- .I1(Q[4]),
- .O(lfsrNext[12]));
- (* SOFT_HLUTNM = "soft_lutpair64" *)
- LUT2 #(
- .INIT(4'h6))
- \lfsr[3]_i_1__2
- (.I0(Q[8]),
- .I1(Q[11]),
- .O(lfsrNext[3]));
- (* SOFT_HLUTNM = "soft_lutpair65" *)
- LUT3 #(
- .INIT(8'h96))
- \lfsr[4]_i_1__2
- (.I0(Q[12]),
- .I1(Q[9]),
- .I2(Q[8]),
- .O(lfsrNext[4]));
- (* SOFT_HLUTNM = "soft_lutpair65" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[5]_i_1__2
- (.I0(Q[13]),
- .I1(Q[8]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[5]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[6]_i_1__2
- (.I0(Q[14]),
- .I1(Q[11]),
- .I2(Q[10]),
- .I3(Q[9]),
- .O(lfsrNext[6]));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[7]_i_1__2
- (.I0(Q[15]),
- .I1(Q[10]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[7]));
- (* SOFT_HLUTNM = "soft_lutpair64" *)
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[8]_i_1__2
- (.I0(Q[13]),
- .I1(Q[0]),
- .I2(Q[12]),
- .I3(Q[11]),
- .O(lfsrNext[8]));
- LUT4 #(
- .INIT(16'h6996))
- \lfsr[9]_i_1__2
- (.I0(Q[12]),
- .I1(Q[1]),
- .I2(Q[14]),
- .I3(Q[13]),
- .O(lfsrNext[9]));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[0]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[8]),
- .Q(Q[0]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[10]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[10]),
- .Q(Q[10]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[11]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[11]),
- .Q(Q[11]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[12]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[12]),
- .Q(Q[12]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[13]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[5]),
- .Q(Q[13]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[14]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[6]),
- .Q(Q[14]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[15]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[7]),
- .Q(Q[15]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[1]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[9]),
- .Q(Q[1]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[2]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(Q[10]),
- .Q(Q[2]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[3]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[3]),
- .Q(Q[3]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[4]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[4]),
- .Q(Q[4]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[5]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[5]),
- .Q(Q[5]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[6]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[6]),
- .Q(Q[6]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[7]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[7]),
- .Q(Q[7]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[8]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[8]),
- .Q(Q[8]),
- .S(SS));
- FDSE #(
- .INIT(1'b0))
- \lfsr_reg[9]
- (.C(user_clk),
- .CE(\DOUT_reg[0]_0 ),
- .D(lfsrNext[9]),
- .Q(Q[9]),
- .S(SS));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SCRAMBLER_TOP" *)
-module north_channel_north_channel_SCRAMBLER_TOP
- (Q,
- \lfsr_reg[15] ,
- TXDATA,
- \CHAR_IS_K_OUT_reg[3]_0 ,
- gen_cc_r,
- user_clk,
- gen_v_r2,
- reset_lanes_i,
- \lfsr_reg[15]_0 ,
- E,
- \DOUT_reg[0] ,
- BYPASS,
- \bypass_r_reg[0]_0 ,
- D,
- \data_nxt_reg[31]_0 ,
- \DOUT_reg[15] ,
- \CHAR_IS_K_OUT_reg[3]_1 );
- output [15:0]Q;
- output [15:0]\lfsr_reg[15] ;
- output [31:0]TXDATA;
- output [3:0]\CHAR_IS_K_OUT_reg[3]_0 ;
- input gen_cc_r;
- input user_clk;
- input gen_v_r2;
- input reset_lanes_i;
- input \lfsr_reg[15]_0 ;
- input [0:0]E;
- input [0:0]\DOUT_reg[0] ;
- input BYPASS;
- input \bypass_r_reg[0]_0 ;
- input [15:0]D;
- input [31:0]\data_nxt_reg[31]_0 ;
- input [15:0]\DOUT_reg[15] ;
- input [3:0]\CHAR_IS_K_OUT_reg[3]_1 ;
-
- wire BYPASS;
- wire [3:0]\CHAR_IS_K_OUT_reg[3]_0 ;
- wire [3:0]\CHAR_IS_K_OUT_reg[3]_1 ;
- wire [15:0]D;
- wire [15:0]DOUT;
- wire [0:0]\DOUT_reg[0] ;
- wire [15:0]\DOUT_reg[15] ;
- wire [0:0]E;
- wire [15:0]Q;
- wire [31:0]TXDATA;
- wire [1:0]bypass_r;
- wire \bypass_r_reg[0]_0 ;
- wire clear_nxt2;
- wire [31:0]data_nxt;
- wire [31:0]\data_nxt_reg[31]_0 ;
- wire gen_cc_r;
- wire gen_v_r2;
- wire [15:0]\lfsr_reg[15] ;
- wire \lfsr_reg[15]_0 ;
- wire north_channel_scrambler0_i_n_0;
- wire north_channel_scrambler1_i_n_16;
- wire north_channel_scrambler1_i_n_17;
- wire north_channel_scrambler1_i_n_18;
- wire north_channel_scrambler1_i_n_19;
- wire north_channel_scrambler1_i_n_20;
- wire north_channel_scrambler1_i_n_21;
- wire north_channel_scrambler1_i_n_22;
- wire north_channel_scrambler1_i_n_23;
- wire north_channel_scrambler1_i_n_24;
- wire north_channel_scrambler1_i_n_25;
- wire north_channel_scrambler1_i_n_26;
- wire north_channel_scrambler1_i_n_27;
- wire north_channel_scrambler1_i_n_28;
- wire north_channel_scrambler1_i_n_29;
- wire north_channel_scrambler1_i_n_30;
- wire north_channel_scrambler1_i_n_31;
- wire reset_lanes_i;
- wire user_clk;
-
- FDRE \CHAR_IS_K_OUT_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [0]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [0]),
- .R(1'b0));
- FDRE \CHAR_IS_K_OUT_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [1]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [1]),
- .R(1'b0));
- FDRE \CHAR_IS_K_OUT_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [2]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [2]),
- .R(1'b0));
- FDRE \CHAR_IS_K_OUT_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\CHAR_IS_K_OUT_reg[3]_1 [3]),
- .Q(\CHAR_IS_K_OUT_reg[3]_0 [3]),
- .R(1'b0));
- FDRE \bypass_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\bypass_r_reg[0]_0 ),
- .Q(bypass_r[0]),
- .R(1'b0));
- FDRE \bypass_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(BYPASS),
- .Q(bypass_r[1]),
- .R(1'b0));
- FDRE clear_nxt2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_cc_r),
- .Q(clear_nxt2),
- .R(1'b0));
- FDRE \data_nxt_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [0]),
- .Q(data_nxt[0]),
- .R(1'b0));
- FDRE \data_nxt_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [10]),
- .Q(data_nxt[10]),
- .R(1'b0));
- FDRE \data_nxt_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [11]),
- .Q(data_nxt[11]),
- .R(1'b0));
- FDRE \data_nxt_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [12]),
- .Q(data_nxt[12]),
- .R(1'b0));
- FDRE \data_nxt_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [13]),
- .Q(data_nxt[13]),
- .R(1'b0));
- FDRE \data_nxt_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [14]),
- .Q(data_nxt[14]),
- .R(1'b0));
- FDRE \data_nxt_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [15]),
- .Q(data_nxt[15]),
- .R(1'b0));
- FDRE \data_nxt_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [16]),
- .Q(data_nxt[16]),
- .R(1'b0));
- FDRE \data_nxt_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [17]),
- .Q(data_nxt[17]),
- .R(1'b0));
- FDRE \data_nxt_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [18]),
- .Q(data_nxt[18]),
- .R(1'b0));
- FDRE \data_nxt_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [19]),
- .Q(data_nxt[19]),
- .R(1'b0));
- FDRE \data_nxt_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [1]),
- .Q(data_nxt[1]),
- .R(1'b0));
- FDRE \data_nxt_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [20]),
- .Q(data_nxt[20]),
- .R(1'b0));
- FDRE \data_nxt_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [21]),
- .Q(data_nxt[21]),
- .R(1'b0));
- FDRE \data_nxt_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [22]),
- .Q(data_nxt[22]),
- .R(1'b0));
- FDRE \data_nxt_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [23]),
- .Q(data_nxt[23]),
- .R(1'b0));
- FDRE \data_nxt_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [24]),
- .Q(data_nxt[24]),
- .R(1'b0));
- FDRE \data_nxt_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [25]),
- .Q(data_nxt[25]),
- .R(1'b0));
- FDRE \data_nxt_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [26]),
- .Q(data_nxt[26]),
- .R(1'b0));
- FDRE \data_nxt_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [27]),
- .Q(data_nxt[27]),
- .R(1'b0));
- FDRE \data_nxt_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [28]),
- .Q(data_nxt[28]),
- .R(1'b0));
- FDRE \data_nxt_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [29]),
- .Q(data_nxt[29]),
- .R(1'b0));
- FDRE \data_nxt_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [2]),
- .Q(data_nxt[2]),
- .R(1'b0));
- FDRE \data_nxt_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [30]),
- .Q(data_nxt[30]),
- .R(1'b0));
- FDRE \data_nxt_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [31]),
- .Q(data_nxt[31]),
- .R(1'b0));
- FDRE \data_nxt_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [3]),
- .Q(data_nxt[3]),
- .R(1'b0));
- FDRE \data_nxt_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [4]),
- .Q(data_nxt[4]),
- .R(1'b0));
- FDRE \data_nxt_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [5]),
- .Q(data_nxt[5]),
- .R(1'b0));
- FDRE \data_nxt_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [6]),
- .Q(data_nxt[6]),
- .R(1'b0));
- FDRE \data_nxt_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [7]),
- .Q(data_nxt[7]),
- .R(1'b0));
- FDRE \data_nxt_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [8]),
- .Q(data_nxt[8]),
- .R(1'b0));
- FDRE \data_nxt_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\data_nxt_reg[31]_0 [9]),
- .Q(data_nxt[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair99" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_19
- (.I0(data_nxt[7]),
- .I1(bypass_r[0]),
- .I2(DOUT[7]),
- .O(TXDATA[31]));
- (* SOFT_HLUTNM = "soft_lutpair99" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_20
- (.I0(data_nxt[6]),
- .I1(bypass_r[0]),
- .I2(DOUT[6]),
- .O(TXDATA[30]));
- (* SOFT_HLUTNM = "soft_lutpair98" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_21
- (.I0(data_nxt[5]),
- .I1(bypass_r[0]),
- .I2(DOUT[5]),
- .O(TXDATA[29]));
- (* SOFT_HLUTNM = "soft_lutpair98" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_22
- (.I0(data_nxt[4]),
- .I1(bypass_r[0]),
- .I2(DOUT[4]),
- .O(TXDATA[28]));
- (* SOFT_HLUTNM = "soft_lutpair97" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_23
- (.I0(data_nxt[3]),
- .I1(bypass_r[0]),
- .I2(DOUT[3]),
- .O(TXDATA[27]));
- (* SOFT_HLUTNM = "soft_lutpair97" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_24
- (.I0(data_nxt[2]),
- .I1(bypass_r[0]),
- .I2(DOUT[2]),
- .O(TXDATA[26]));
- (* SOFT_HLUTNM = "soft_lutpair96" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_25
- (.I0(data_nxt[1]),
- .I1(bypass_r[0]),
- .I2(DOUT[1]),
- .O(TXDATA[25]));
- (* SOFT_HLUTNM = "soft_lutpair96" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_26
- (.I0(data_nxt[0]),
- .I1(bypass_r[0]),
- .I2(DOUT[0]),
- .O(TXDATA[24]));
- (* SOFT_HLUTNM = "soft_lutpair103" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_27
- (.I0(data_nxt[15]),
- .I1(bypass_r[0]),
- .I2(DOUT[15]),
- .O(TXDATA[23]));
- (* SOFT_HLUTNM = "soft_lutpair103" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_28
- (.I0(data_nxt[14]),
- .I1(bypass_r[0]),
- .I2(DOUT[14]),
- .O(TXDATA[22]));
- (* SOFT_HLUTNM = "soft_lutpair102" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_29
- (.I0(data_nxt[13]),
- .I1(bypass_r[0]),
- .I2(DOUT[13]),
- .O(TXDATA[21]));
- (* SOFT_HLUTNM = "soft_lutpair102" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_30
- (.I0(data_nxt[12]),
- .I1(bypass_r[0]),
- .I2(DOUT[12]),
- .O(TXDATA[20]));
- (* SOFT_HLUTNM = "soft_lutpair101" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_31
- (.I0(data_nxt[11]),
- .I1(bypass_r[0]),
- .I2(DOUT[11]),
- .O(TXDATA[19]));
- (* SOFT_HLUTNM = "soft_lutpair101" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_32
- (.I0(data_nxt[10]),
- .I1(bypass_r[0]),
- .I2(DOUT[10]),
- .O(TXDATA[18]));
- (* SOFT_HLUTNM = "soft_lutpair100" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_33
- (.I0(data_nxt[9]),
- .I1(bypass_r[0]),
- .I2(DOUT[9]),
- .O(TXDATA[17]));
- (* SOFT_HLUTNM = "soft_lutpair100" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_34
- (.I0(data_nxt[8]),
- .I1(bypass_r[0]),
- .I2(DOUT[8]),
- .O(TXDATA[16]));
- (* SOFT_HLUTNM = "soft_lutpair107" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_35
- (.I0(data_nxt[23]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_24),
- .O(TXDATA[15]));
- (* SOFT_HLUTNM = "soft_lutpair107" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_36
- (.I0(data_nxt[22]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_25),
- .O(TXDATA[14]));
- (* SOFT_HLUTNM = "soft_lutpair106" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_37
- (.I0(data_nxt[21]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_26),
- .O(TXDATA[13]));
- (* SOFT_HLUTNM = "soft_lutpair106" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_38
- (.I0(data_nxt[20]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_27),
- .O(TXDATA[12]));
- (* SOFT_HLUTNM = "soft_lutpair105" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_39
- (.I0(data_nxt[19]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_28),
- .O(TXDATA[11]));
- (* SOFT_HLUTNM = "soft_lutpair105" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_40
- (.I0(data_nxt[18]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_29),
- .O(TXDATA[10]));
- (* SOFT_HLUTNM = "soft_lutpair104" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_41
- (.I0(data_nxt[17]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_30),
- .O(TXDATA[9]));
- (* SOFT_HLUTNM = "soft_lutpair104" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_42
- (.I0(data_nxt[16]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_31),
- .O(TXDATA[8]));
- (* SOFT_HLUTNM = "soft_lutpair111" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_43
- (.I0(data_nxt[31]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_16),
- .O(TXDATA[7]));
- (* SOFT_HLUTNM = "soft_lutpair111" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_44
- (.I0(data_nxt[30]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_17),
- .O(TXDATA[6]));
- (* SOFT_HLUTNM = "soft_lutpair110" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_45
- (.I0(data_nxt[29]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_18),
- .O(TXDATA[5]));
- (* SOFT_HLUTNM = "soft_lutpair110" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_46
- (.I0(data_nxt[28]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_19),
- .O(TXDATA[4]));
- (* SOFT_HLUTNM = "soft_lutpair109" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_47
- (.I0(data_nxt[27]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_20),
- .O(TXDATA[3]));
- (* SOFT_HLUTNM = "soft_lutpair109" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_48
- (.I0(data_nxt[26]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_21),
- .O(TXDATA[2]));
- (* SOFT_HLUTNM = "soft_lutpair108" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_49
- (.I0(data_nxt[25]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_22),
- .O(TXDATA[1]));
- (* SOFT_HLUTNM = "soft_lutpair108" *)
- LUT3 #(
- .INIT(8'hB8))
- gtpe2_i_i_50
- (.I0(data_nxt[24]),
- .I1(bypass_r[1]),
- .I2(north_channel_scrambler1_i_n_23),
- .O(TXDATA[0]));
- north_channel_north_channel_SCRAMBLER north_channel_scrambler0_i
- (.D(D),
- .\DOUT_reg[15]_0 (DOUT),
- .E(E),
- .Q(Q),
- .SS(north_channel_scrambler0_i_n_0),
- .clear_nxt2(clear_nxt2),
- .gen_v_r2(gen_v_r2),
- .\lfsr_reg[15]_0 (\lfsr_reg[15]_0 ),
- .reset_lanes_i(reset_lanes_i),
- .user_clk(user_clk));
- north_channel_north_channel_SCRAMBLER_2 north_channel_scrambler1_i
- (.\DOUT_reg[0]_0 (\DOUT_reg[0] ),
- .\DOUT_reg[15]_0 ({north_channel_scrambler1_i_n_16,north_channel_scrambler1_i_n_17,north_channel_scrambler1_i_n_18,north_channel_scrambler1_i_n_19,north_channel_scrambler1_i_n_20,north_channel_scrambler1_i_n_21,north_channel_scrambler1_i_n_22,north_channel_scrambler1_i_n_23,north_channel_scrambler1_i_n_24,north_channel_scrambler1_i_n_25,north_channel_scrambler1_i_n_26,north_channel_scrambler1_i_n_27,north_channel_scrambler1_i_n_28,north_channel_scrambler1_i_n_29,north_channel_scrambler1_i_n_30,north_channel_scrambler1_i_n_31}),
- .\DOUT_reg[15]_1 (\DOUT_reg[15] ),
- .Q(\lfsr_reg[15] ),
- .SS(north_channel_scrambler0_i_n_0),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SIDEBAND_OUTPUT" *)
-module north_channel_north_channel_SIDEBAND_OUTPUT
- (SRC_RDY_N_Buffer,
- SR,
- EOF_N_Buffer,
- stage_3_end_storage_r,
- FRAME_ERR_RESULT_Buffer,
- D,
- \RX_REM_Buffer_reg[0]_0 ,
- user_clk,
- EOF_N_Buffer_reg_0,
- end_storage_r0,
- FRAME_ERR_RESULT_Buffer0,
- stage_2_start_with_data_r,
- stage_2_pad_r,
- Q,
- \RX_REM_Buffer_reg[0]_1 ,
- std_bool6_in,
- stage_2_end_before_start_r,
- stage_2_frame_err_r,
- START_RX);
- output SRC_RDY_N_Buffer;
- output [0:0]SR;
- output EOF_N_Buffer;
- output stage_3_end_storage_r;
- output FRAME_ERR_RESULT_Buffer;
- output [0:0]D;
- output [1:0]\RX_REM_Buffer_reg[0]_0 ;
- input user_clk;
- input EOF_N_Buffer_reg_0;
- input end_storage_r0;
- input FRAME_ERR_RESULT_Buffer0;
- input stage_2_start_with_data_r;
- input stage_2_pad_r;
- input [0:0]Q;
- input [0:0]\RX_REM_Buffer_reg[0]_1 ;
- input std_bool6_in;
- input stage_2_end_before_start_r;
- input stage_2_frame_err_r;
- input START_RX;
-
- wire [0:0]D;
- wire EOF_N_Buffer;
- wire EOF_N_Buffer_reg_0;
- wire FRAME_ERR_RESULT_Buffer;
- wire FRAME_ERR_RESULT_Buffer0;
- wire [0:0]Q;
- wire [1:0]\RX_REM_Buffer_reg[0]_0 ;
- wire [0:0]\RX_REM_Buffer_reg[0]_1 ;
- wire [0:0]SR;
- wire SRC_RDY_N_Buffer;
- wire SRC_RDY_N_Buffer_i_2_n_0;
- wire START_RX;
- wire end_storage_r0;
- wire pad_storage_r;
- wire pad_storage_r_i_1_n_0;
- wire [1:0]rx_rem_c;
- wire stage_2_end_before_start_r;
- wire stage_2_frame_err_r;
- wire stage_2_pad_r;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire std_bool6_in;
- wire user_clk;
-
- FDRE EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(EOF_N_Buffer_reg_0),
- .Q(EOF_N_Buffer),
- .R(1'b0));
- FDRE FRAME_ERR_RESULT_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(FRAME_ERR_RESULT_Buffer0),
- .Q(FRAME_ERR_RESULT_Buffer),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair195" *)
- LUT4 #(
- .INIT(16'h1E0F))
- \RX_REM_Buffer[0]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(Q),
- .I3(\RX_REM_Buffer_reg[0]_1 ),
- .O(rx_rem_c[1]));
- LUT4 #(
- .INIT(16'h00EF))
- \RX_REM_Buffer[1]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(stage_2_pad_r),
- .I3(pad_storage_r),
- .O(rx_rem_c[0]));
- FDRE \RX_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_rem_c[1]),
- .Q(\RX_REM_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_REM_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_rem_c[0]),
- .Q(\RX_REM_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- SRC_RDY_N_Buffer_i_1
- (.I0(stage_2_frame_err_r),
- .I1(START_RX),
- .O(SR));
- LUT4 #(
- .INIT(16'h0145))
- SRC_RDY_N_Buffer_i_2
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(std_bool6_in),
- .I3(stage_2_end_before_start_r),
- .O(SRC_RDY_N_Buffer_i_2_n_0));
- FDSE SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(SRC_RDY_N_Buffer_i_2_n_0),
- .Q(SRC_RDY_N_Buffer),
- .S(SR));
- FDRE end_storage_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(end_storage_r0),
- .Q(stage_3_end_storage_r),
- .R(SR));
- LUT6 #(
- .INIT(64'hAAABBABBAAAAAAAA))
- pad_storage_r_i_1
- (.I0(stage_2_pad_r),
- .I1(stage_3_end_storage_r),
- .I2(stage_2_start_with_data_r),
- .I3(std_bool6_in),
- .I4(stage_2_end_before_start_r),
- .I5(pad_storage_r),
- .O(pad_storage_r_i_1_n_0));
- FDRE pad_storage_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(pad_storage_r_i_1_n_0),
- .Q(pad_storage_r),
- .R(SR));
- (* SOFT_HLUTNM = "soft_lutpair195" *)
- LUT4 #(
- .INIT(16'hE1F0))
- \storage_count_r[1]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(\RX_REM_Buffer_reg[0]_1 ),
- .I3(Q),
- .O(D));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_STANDARD_CC_MODULE" *)
-module north_channel_north_channel_STANDARD_CC_MODULE
- (WARN_CC,
- DO_CC_I,
- next_ufc_idle_c,
- DO_CC_reg_0,
- user_clk,
- ufc_idle_r_reg,
- S_AXI_UFC_TX_REQ);
- output WARN_CC;
- output DO_CC_I;
- output next_ufc_idle_c;
- input DO_CC_reg_0;
- input user_clk;
- input ufc_idle_r_reg;
- input S_AXI_UFC_TX_REQ;
-
- wire DO_CC_I;
- wire DO_CC_i_1_n_0;
- wire DO_CC_reg_0;
- wire S_AXI_UFC_TX_REQ;
- wire WARN_CC;
- wire WARN_CC_i_1_n_0;
- wire [5:5]cc_count_r;
- wire cc_idle_count_done_c;
- wire count_13d_flop_r_reg_r_n_0;
- wire \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ;
- wire \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ;
- wire \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ;
- wire count_13d_srl_r_reg_gate_n_0;
- wire count_13d_srl_r_reg_r_0_n_0;
- wire count_13d_srl_r_reg_r_1_n_0;
- wire count_13d_srl_r_reg_r_2_n_0;
- wire count_13d_srl_r_reg_r_3_n_0;
- wire count_13d_srl_r_reg_r_4_n_0;
- wire count_13d_srl_r_reg_r_5_n_0;
- wire count_13d_srl_r_reg_r_6_n_0;
- wire count_13d_srl_r_reg_r_7_n_0;
- wire count_13d_srl_r_reg_r_8_n_0;
- wire count_13d_srl_r_reg_r_9_n_0;
- wire count_13d_srl_r_reg_r_n_0;
- wire count_16d_flop_r;
- wire count_16d_flop_r_i_1_n_0;
- wire count_16d_srl_r0;
- wire \count_16d_srl_r_reg_n_0_[0] ;
- wire \count_16d_srl_r_reg_n_0_[10] ;
- wire \count_16d_srl_r_reg_n_0_[11] ;
- wire \count_16d_srl_r_reg_n_0_[12] ;
- wire \count_16d_srl_r_reg_n_0_[13] ;
- wire \count_16d_srl_r_reg_n_0_[14] ;
- wire \count_16d_srl_r_reg_n_0_[1] ;
- wire \count_16d_srl_r_reg_n_0_[2] ;
- wire \count_16d_srl_r_reg_n_0_[3] ;
- wire \count_16d_srl_r_reg_n_0_[4] ;
- wire \count_16d_srl_r_reg_n_0_[5] ;
- wire \count_16d_srl_r_reg_n_0_[6] ;
- wire \count_16d_srl_r_reg_n_0_[7] ;
- wire \count_16d_srl_r_reg_n_0_[8] ;
- wire \count_16d_srl_r_reg_n_0_[9] ;
- wire count_24d_flop_r;
- wire count_24d_flop_r_i_1_n_0;
- wire count_24d_srl_r0;
- wire \count_24d_srl_r_reg_n_0_[0] ;
- wire \count_24d_srl_r_reg_n_0_[10] ;
- wire \count_24d_srl_r_reg_n_0_[1] ;
- wire \count_24d_srl_r_reg_n_0_[2] ;
- wire \count_24d_srl_r_reg_n_0_[3] ;
- wire \count_24d_srl_r_reg_n_0_[4] ;
- wire \count_24d_srl_r_reg_n_0_[5] ;
- wire \count_24d_srl_r_reg_n_0_[6] ;
- wire \count_24d_srl_r_reg_n_0_[7] ;
- wire \count_24d_srl_r_reg_n_0_[8] ;
- wire \count_24d_srl_r_reg_n_0_[9] ;
- wire next_ufc_idle_c;
- wire [1:0]p_2_in;
- wire [2:2]p_3_out;
- wire \prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_n_0 ;
- wire \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2_n_0 ;
- wire prepare_count_r_reg_gate_n_0;
- wire reset_r;
- wire ufc_idle_r_reg;
- wire user_clk;
-
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- DO_CC_i_1
- (.I0(reset_r),
- .I1(p_2_in[1]),
- .I2(p_3_out),
- .I3(p_2_in[0]),
- .I4(cc_count_r),
- .O(DO_CC_i_1_n_0));
- FDRE DO_CC_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(DO_CC_i_1_n_0),
- .Q(DO_CC_I),
- .R(DO_CC_reg_0));
- LUT5 #(
- .INIT(32'h80FF8080))
- WARN_CC_i_1
- (.I0(\count_24d_srl_r_reg_n_0_[10] ),
- .I1(\count_16d_srl_r_reg_n_0_[14] ),
- .I2(count_16d_srl_r0),
- .I3(p_3_out),
- .I4(WARN_CC),
- .O(WARN_CC_i_1_n_0));
- FDRE WARN_CC_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(WARN_CC_i_1_n_0),
- .Q(WARN_CC),
- .R(DO_CC_reg_0));
- FDRE #(
- .INIT(1'b0))
- \cc_count_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out),
- .Q(p_2_in[1]),
- .R(DO_CC_reg_0));
- FDRE #(
- .INIT(1'b0))
- \cc_count_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_in[1]),
- .Q(p_2_in[0]),
- .R(DO_CC_reg_0));
- FDRE #(
- .INIT(1'b0))
- \cc_count_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_in[0]),
- .Q(cc_count_r),
- .R(DO_CC_reg_0));
- FDRE count_13d_flop_r_reg_r
- (.C(user_clk),
- .CE(1'b1),
- .D(1'b1),
- .Q(count_13d_flop_r_reg_r_n_0),
- .R(DO_CC_reg_0));
- FDRE \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9
- (.C(user_clk),
- .CE(1'b1),
- .D(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ),
- .Q(\count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ),
- .R(1'b0));
- FDRE \count_13d_srl_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_gate_n_0),
- .Q(count_16d_srl_r0),
- .R(DO_CC_reg_0));
- (* srl_bus_name = "U0/\standard_cc_module_i/count_13d_srl_r_reg " *)
- (* srl_name = "U0/\standard_cc_module_i/count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8 " *)
- SRL16E \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b1),
- .CE(1'b1),
- .CLK(user_clk),
- .D(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ),
- .Q(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair281" *)
- LUT2 #(
- .INIT(4'hE))
- \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1
- (.I0(count_16d_srl_r0),
- .I1(reset_r),
- .O(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- count_13d_srl_r_reg_gate
- (.I0(\count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ),
- .I1(count_13d_srl_r_reg_r_9_n_0),
- .O(count_13d_srl_r_reg_gate_n_0));
- FDRE count_13d_srl_r_reg_r
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_flop_r_reg_r_n_0),
- .Q(count_13d_srl_r_reg_r_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_0
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_n_0),
- .Q(count_13d_srl_r_reg_r_0_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_1
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_0_n_0),
- .Q(count_13d_srl_r_reg_r_1_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_2
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_1_n_0),
- .Q(count_13d_srl_r_reg_r_2_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_3
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_2_n_0),
- .Q(count_13d_srl_r_reg_r_3_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_4
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_3_n_0),
- .Q(count_13d_srl_r_reg_r_4_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_5
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_4_n_0),
- .Q(count_13d_srl_r_reg_r_5_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_6
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_5_n_0),
- .Q(count_13d_srl_r_reg_r_6_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_7
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_6_n_0),
- .Q(count_13d_srl_r_reg_r_7_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_8
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_7_n_0),
- .Q(count_13d_srl_r_reg_r_8_n_0),
- .R(DO_CC_reg_0));
- FDRE count_13d_srl_r_reg_r_9
- (.C(user_clk),
- .CE(1'b1),
- .D(count_13d_srl_r_reg_r_8_n_0),
- .Q(count_13d_srl_r_reg_r_9_n_0),
- .R(DO_CC_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair281" *)
- LUT4 #(
- .INIT(16'hFBF8))
- count_16d_flop_r_i_1
- (.I0(\count_16d_srl_r_reg_n_0_[14] ),
- .I1(count_16d_srl_r0),
- .I2(reset_r),
- .I3(count_16d_flop_r),
- .O(count_16d_flop_r_i_1_n_0));
- FDRE count_16d_flop_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(count_16d_flop_r_i_1_n_0),
- .Q(count_16d_flop_r),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[0]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(count_16d_flop_r),
- .Q(\count_16d_srl_r_reg_n_0_[0] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[10]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[9] ),
- .Q(\count_16d_srl_r_reg_n_0_[10] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[11]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[10] ),
- .Q(\count_16d_srl_r_reg_n_0_[11] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[12]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[11] ),
- .Q(\count_16d_srl_r_reg_n_0_[12] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[13]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[12] ),
- .Q(\count_16d_srl_r_reg_n_0_[13] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[14]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[13] ),
- .Q(\count_16d_srl_r_reg_n_0_[14] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[1]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[0] ),
- .Q(\count_16d_srl_r_reg_n_0_[1] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[2]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[1] ),
- .Q(\count_16d_srl_r_reg_n_0_[2] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[3]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[2] ),
- .Q(\count_16d_srl_r_reg_n_0_[3] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[4]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[3] ),
- .Q(\count_16d_srl_r_reg_n_0_[4] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[5]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[4] ),
- .Q(\count_16d_srl_r_reg_n_0_[5] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[6]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[5] ),
- .Q(\count_16d_srl_r_reg_n_0_[6] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[7]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[6] ),
- .Q(\count_16d_srl_r_reg_n_0_[7] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[8]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[7] ),
- .Q(\count_16d_srl_r_reg_n_0_[8] ),
- .R(DO_CC_reg_0));
- FDRE \count_16d_srl_r_reg[9]
- (.C(user_clk),
- .CE(count_16d_srl_r0),
- .D(\count_16d_srl_r_reg_n_0_[8] ),
- .Q(\count_16d_srl_r_reg_n_0_[9] ),
- .R(DO_CC_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair280" *)
- LUT5 #(
- .INIT(32'hFFBFFF80))
- count_24d_flop_r_i_1
- (.I0(\count_24d_srl_r_reg_n_0_[10] ),
- .I1(count_16d_srl_r0),
- .I2(\count_16d_srl_r_reg_n_0_[14] ),
- .I3(reset_r),
- .I4(count_24d_flop_r),
- .O(count_24d_flop_r_i_1_n_0));
- FDRE count_24d_flop_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(count_24d_flop_r_i_1_n_0),
- .Q(count_24d_flop_r),
- .R(DO_CC_reg_0));
- LUT2 #(
- .INIT(4'h8))
- \count_24d_srl_r[0]_i_1
- (.I0(count_16d_srl_r0),
- .I1(\count_16d_srl_r_reg_n_0_[14] ),
- .O(count_24d_srl_r0));
- FDRE \count_24d_srl_r_reg[0]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(count_24d_flop_r),
- .Q(\count_24d_srl_r_reg_n_0_[0] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[10]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[9] ),
- .Q(\count_24d_srl_r_reg_n_0_[10] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[1]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[0] ),
- .Q(\count_24d_srl_r_reg_n_0_[1] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[2]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[1] ),
- .Q(\count_24d_srl_r_reg_n_0_[2] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[3]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[2] ),
- .Q(\count_24d_srl_r_reg_n_0_[3] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[4]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[3] ),
- .Q(\count_24d_srl_r_reg_n_0_[4] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[5]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[4] ),
- .Q(\count_24d_srl_r_reg_n_0_[5] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[6]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[5] ),
- .Q(\count_24d_srl_r_reg_n_0_[6] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[7]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[6] ),
- .Q(\count_24d_srl_r_reg_n_0_[7] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[8]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[7] ),
- .Q(\count_24d_srl_r_reg_n_0_[8] ),
- .R(DO_CC_reg_0));
- FDRE \count_24d_srl_r_reg[9]
- (.C(user_clk),
- .CE(count_24d_srl_r0),
- .D(\count_24d_srl_r_reg_n_0_[8] ),
- .Q(\count_24d_srl_r_reg_n_0_[9] ),
- .R(DO_CC_reg_0));
- (* srl_bus_name = "U0/\standard_cc_module_i/prepare_count_r_reg " *)
- (* srl_name = "U0/\standard_cc_module_i/prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1 " *)
- SRL16E #(
- .INIT(16'h0000))
- \prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1
- (.A0(1'b1),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(cc_idle_count_done_c),
- .Q(\prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair280" *)
- LUT3 #(
- .INIT(8'h80))
- \prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_i_1
- (.I0(count_16d_srl_r0),
- .I1(\count_16d_srl_r_reg_n_0_[14] ),
- .I2(\count_24d_srl_r_reg_n_0_[10] ),
- .O(cc_idle_count_done_c));
- FDRE \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2
- (.C(user_clk),
- .CE(1'b1),
- .D(\prepare_count_r_reg[7]_srl4___standard_cc_module_i_count_13d_srl_r_reg_r_1_n_0 ),
- .Q(\prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2_n_0 ),
- .R(1'b0));
- FDRE \prepare_count_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(prepare_count_r_reg_gate_n_0),
- .Q(p_3_out),
- .R(DO_CC_reg_0));
- LUT2 #(
- .INIT(4'h8))
- prepare_count_r_reg_gate
- (.I0(\prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_2_n_0 ),
- .I1(count_13d_srl_r_reg_r_2_n_0),
- .O(prepare_count_r_reg_gate_n_0));
- FDRE reset_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(DO_CC_reg_0),
- .Q(reset_r),
- .R(1'b0));
- LUT4 #(
- .INIT(16'hA8AA))
- ufc_idle_r_i_1
- (.I0(ufc_idle_r_reg),
- .I1(DO_CC_I),
- .I2(WARN_CC),
- .I3(S_AXI_UFC_TX_REQ),
- .O(next_ufc_idle_c));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_STORAGE_CE_CONTROL" *)
-module north_channel_north_channel_STORAGE_CE_CONTROL
- (Q,
- RESET,
- D,
- user_clk);
- output [1:0]Q;
- input RESET;
- input [1:0]D;
- input user_clk;
-
- wire [1:0]D;
- wire [1:0]Q;
- wire RESET;
- wire user_clk;
-
- FDRE \STORAGE_CE_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(Q[1]),
- .R(RESET));
- FDRE \STORAGE_CE_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(Q[0]),
- .R(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_STORAGE_COUNT_CONTROL" *)
-module north_channel_north_channel_STORAGE_COUNT_CONTROL
- (output_select_c,
- Q,
- FRAME_ERR_RESULT_Buffer0,
- end_storage_r_reg,
- stage_2_start_with_data_r,
- stage_3_end_storage_r,
- stage_2_frame_err_r,
- stage_2_end_after_start_r,
- stage_2_end_before_start_r,
- std_bool2_in,
- SR,
- D,
- user_clk);
- output [0:0]output_select_c;
- output [1:0]Q;
- output FRAME_ERR_RESULT_Buffer0;
- output end_storage_r_reg;
- input stage_2_start_with_data_r;
- input stage_3_end_storage_r;
- input stage_2_frame_err_r;
- input stage_2_end_after_start_r;
- input stage_2_end_before_start_r;
- input std_bool2_in;
- input [0:0]SR;
- input [1:0]D;
- input user_clk;
-
- wire [1:0]D;
- wire FRAME_ERR_RESULT_Buffer0;
- wire [1:0]Q;
- wire [0:0]SR;
- wire end_storage_r_reg;
- wire [0:0]output_select_c;
- wire \sideband_output_i/std_bool ;
- wire stage_2_end_after_start_r;
- wire stage_2_end_before_start_r;
- wire stage_2_frame_err_r;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire std_bool2_in;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair224" *)
- LUT5 #(
- .INIT(32'h15151555))
- EOF_N_Buffer_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_end_before_start_r),
- .I2(stage_2_start_with_data_r),
- .I3(Q[1]),
- .I4(Q[0]),
- .O(end_storage_r_reg));
- LUT6 #(
- .INIT(64'hDDFFCCFCDDFCCCFC))
- FRAME_ERR_RESULT_Buffer_i_1
- (.I0(\sideband_output_i/std_bool ),
- .I1(stage_2_frame_err_r),
- .I2(stage_2_end_after_start_r),
- .I3(stage_2_start_with_data_r),
- .I4(stage_2_end_before_start_r),
- .I5(std_bool2_in),
- .O(FRAME_ERR_RESULT_Buffer0));
- LUT2 #(
- .INIT(4'hE))
- FRAME_ERR_RESULT_Buffer_i_2
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\sideband_output_i/std_bool ));
- (* SOFT_HLUTNM = "soft_lutpair224" *)
- LUT3 #(
- .INIT(8'h01))
- \OUTPUT_SELECT_Buffer[9]_i_1
- (.I0(Q[1]),
- .I1(stage_2_start_with_data_r),
- .I2(stage_3_end_storage_r),
- .O(output_select_c));
- FDRE \storage_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(Q[1]),
- .R(SR));
- FDRE \storage_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(Q[0]),
- .R(SR));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_STORAGE_MUX" *)
-module north_channel_north_channel_STORAGE_MUX
- (Q,
- E,
- D,
- user_clk);
- output [31:0]Q;
- input [1:0]E;
- input [31:0]D;
- input user_clk;
-
- wire [31:0]D;
- wire [1:0]E;
- wire [31:0]Q;
- wire user_clk;
-
- FDRE \STORAGE_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[31]),
- .Q(Q[31]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[21]),
- .Q(Q[21]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[20]),
- .Q(Q[20]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[19]),
- .Q(Q[19]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[18]),
- .Q(Q[18]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[17]),
- .Q(Q[17]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[16]),
- .Q(Q[16]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[15]),
- .Q(Q[15]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[14]),
- .Q(Q[14]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[13]),
- .Q(Q[13]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[12]),
- .Q(Q[12]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[30]),
- .Q(Q[30]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[11]),
- .Q(Q[11]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[10]),
- .Q(Q[10]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[9]),
- .Q(Q[9]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[8]),
- .Q(Q[8]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[7]),
- .Q(Q[7]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[6]),
- .Q(Q[6]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[5]),
- .Q(Q[5]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[4]),
- .Q(Q[4]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[3]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[2]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[29]),
- .Q(Q[29]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(E[0]),
- .D(D[0]),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[28]),
- .Q(Q[28]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[27]),
- .Q(Q[27]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[26]),
- .Q(Q[26]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[25]),
- .Q(Q[25]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[24]),
- .Q(Q[24]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[23]),
- .Q(Q[23]),
- .R(1'b0));
- FDRE \STORAGE_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(E[1]),
- .D(D[22]),
- .Q(Q[22]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_STORAGE_SWITCH_CONTROL" *)
-module north_channel_north_channel_STORAGE_SWITCH_CONTROL
- (STORAGE_SELECT_Buffer,
- Q,
- stage_2_start_with_data_r,
- stage_3_end_storage_r,
- user_clk);
- output [1:0]STORAGE_SELECT_Buffer;
- input [0:0]Q;
- input stage_2_start_with_data_r;
- input stage_3_end_storage_r;
- input user_clk;
-
- wire [0:0]Q;
- wire [1:0]STORAGE_SELECT_Buffer;
- wire \STORAGE_SELECT_Buffer[4]_i_1_n_0 ;
- wire \STORAGE_SELECT_Buffer[9]_i_1_n_0 ;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair225" *)
- LUT3 #(
- .INIT(8'h02))
- \STORAGE_SELECT_Buffer[4]_i_1
- (.I0(Q),
- .I1(stage_2_start_with_data_r),
- .I2(stage_3_end_storage_r),
- .O(\STORAGE_SELECT_Buffer[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair225" *)
- LUT3 #(
- .INIT(8'hFD))
- \STORAGE_SELECT_Buffer[9]_i_1
- (.I0(Q),
- .I1(stage_2_start_with_data_r),
- .I2(stage_3_end_storage_r),
- .O(\STORAGE_SELECT_Buffer[9]_i_1_n_0 ));
- FDRE \STORAGE_SELECT_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\STORAGE_SELECT_Buffer[4]_i_1_n_0 ),
- .Q(STORAGE_SELECT_Buffer[1]),
- .R(1'b0));
- FDRE \STORAGE_SELECT_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\STORAGE_SELECT_Buffer[9]_i_1_n_0 ),
- .Q(STORAGE_SELECT_Buffer[0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SYM_DEC_4BYTE" *)
-module north_channel_north_channel_SYM_DEC_4BYTE
- (\left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[1]_0 ,
- rx_sp_descram_in,
- rx_spa_descram_in,
- rx_neg_descram_in,
- got_v_descram_in,
- D,
- rx_pe_data_descram_in,
- first_v_received_r,
- CHANNEL_UP_Buffer_reg,
- Q,
- \RX_PE_DATA_V_Buffer_reg[0]_0 ,
- \RX_PE_DATA_Buffer_reg[16]_0 ,
- BYPASS,
- E,
- \RX_PE_DATA_Buffer_reg[0]_0 ,
- bypass_w_reg,
- \previous_cycle_data_r_reg[7]_0 ,
- \previous_cycle_control_r_reg[0]_0 ,
- \RX_SUF_Buffer_reg[0]_0 ,
- p_9_out,
- p_8_out,
- \left_align_select_r_reg[0]_1 ,
- user_clk,
- \left_align_select_r_reg[1]_1 ,
- \word_aligned_control_bits_r_reg[3]_0 ,
- \word_aligned_control_bits_r_reg[2]_0 ,
- \bypass_r_reg[0] ,
- reset_lanes_i,
- \DOUT_reg[0] ,
- \DOUT_reg[0]_0 ,
- RXDATA,
- RXCHARISK,
- LANE_UP,
- \word_aligned_data_r_reg[24]_0 ,
- \word_aligned_data_r_reg[16]_0 );
- output \left_align_select_r_reg[0]_0 ;
- output \left_align_select_r_reg[1]_0 ;
- output rx_sp_descram_in;
- output rx_spa_descram_in;
- output rx_neg_descram_in;
- output got_v_descram_in;
- output [0:0]D;
- output [0:31]rx_pe_data_descram_in;
- output first_v_received_r;
- output [0:0]CHANNEL_UP_Buffer_reg;
- output [1:0]Q;
- output [1:0]\RX_PE_DATA_V_Buffer_reg[0]_0 ;
- output [15:0]\RX_PE_DATA_Buffer_reg[16]_0 ;
- output BYPASS;
- output [0:0]E;
- output [15:0]\RX_PE_DATA_Buffer_reg[0]_0 ;
- output bypass_w_reg;
- output [7:0]\previous_cycle_data_r_reg[7]_0 ;
- output [0:0]\previous_cycle_control_r_reg[0]_0 ;
- output [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- output [1:0]p_9_out;
- output [1:0]p_8_out;
- input \left_align_select_r_reg[0]_1 ;
- input user_clk;
- input \left_align_select_r_reg[1]_1 ;
- input \word_aligned_control_bits_r_reg[3]_0 ;
- input \word_aligned_control_bits_r_reg[2]_0 ;
- input \bypass_r_reg[0] ;
- input reset_lanes_i;
- input [15:0]\DOUT_reg[0] ;
- input [15:0]\DOUT_reg[0]_0 ;
- input [31:0]RXDATA;
- input [3:0]RXCHARISK;
- input LANE_UP;
- input [7:0]\word_aligned_data_r_reg[24]_0 ;
- input [7:0]\word_aligned_data_r_reg[16]_0 ;
-
- wire BYPASS;
- wire [0:0]CHANNEL_UP_Buffer_reg;
- wire [0:0]D;
- wire [15:0]\DOUT_reg[0] ;
- wire [15:0]\DOUT_reg[0]_0 ;
- wire [0:0]E;
- wire \EXP_IN_inferred__0/i__n_0 ;
- wire \EXP_IN_inferred__1/i__n_0 ;
- wire \EXP_IN_inferred__10/i__n_0 ;
- wire \EXP_IN_inferred__11/i__n_0 ;
- wire \EXP_IN_inferred__12/i__n_0 ;
- wire \EXP_IN_inferred__13/i__n_0 ;
- wire \EXP_IN_inferred__14/i__n_0 ;
- wire \EXP_IN_inferred__15/i__n_0 ;
- wire \EXP_IN_inferred__16/i__n_0 ;
- wire \EXP_IN_inferred__17/i__n_0 ;
- wire \EXP_IN_inferred__18/i__n_0 ;
- wire \EXP_IN_inferred__19/i__n_0 ;
- wire \EXP_IN_inferred__2/i__n_0 ;
- wire \EXP_IN_inferred__20/i__n_0 ;
- wire \EXP_IN_inferred__21/i__n_0 ;
- wire \EXP_IN_inferred__22/i__n_0 ;
- wire \EXP_IN_inferred__23/i__n_0 ;
- wire \EXP_IN_inferred__24/i__n_0 ;
- wire \EXP_IN_inferred__25/i__n_0 ;
- wire \EXP_IN_inferred__26/i__n_0 ;
- wire \EXP_IN_inferred__3/i__n_0 ;
- wire \EXP_IN_inferred__30/i__n_0 ;
- wire \EXP_IN_inferred__31/i__n_0 ;
- wire \EXP_IN_inferred__32/i__n_0 ;
- wire \EXP_IN_inferred__34/i__n_0 ;
- wire \EXP_IN_inferred__35/i__n_0 ;
- wire \EXP_IN_inferred__4/i__n_0 ;
- wire \EXP_IN_inferred__44/i__n_0 ;
- wire \EXP_IN_inferred__45/i__n_0 ;
- wire \EXP_IN_inferred__46/i__n_0 ;
- wire \EXP_IN_inferred__47/i__n_0 ;
- wire \EXP_IN_inferred__5/i__n_0 ;
- wire \EXP_IN_inferred__8/i__n_0 ;
- wire \EXP_IN_inferred__9/i__n_0 ;
- wire EXP_IN_n_0;
- wire GOT_V_Buffer_i_2_n_0;
- wire LANE_UP;
- wire [1:0]Q;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire RX_CC_Buffer_i_1_n_0;
- wire RX_CC_Buffer_i_2_n_0;
- wire RX_CC_Buffer_i_3_n_0;
- wire RX_NEG_Buffer0;
- wire [15:0]\RX_PE_DATA_Buffer_reg[0]_0 ;
- wire [15:0]\RX_PE_DATA_Buffer_reg[16]_0 ;
- wire \RX_PE_DATA_V_Buffer[0]_i_1_n_0 ;
- wire \RX_PE_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\RX_PE_DATA_V_Buffer_reg[0]_0 ;
- wire RX_SPA_Buffer_i_2_n_0;
- wire RX_SP_Buffer_i_2_n_0;
- wire RX_SP_Buffer_i_3_n_0;
- wire [1:0]\RX_SUF_Buffer_reg[0]_0 ;
- wire \bypass_r_reg[0] ;
- wire bypass_w_reg;
- wire first_v_received_r;
- wire first_v_received_r_i_1_n_0;
- wire got_v_descram_in;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1]_0 ;
- wire \left_align_select_r_reg[1]_1 ;
- wire [3:0]p_0_in;
- wire p_0_in14_in;
- wire p_0_in18_in;
- wire p_0_in26_in;
- wire p_0_in28_in;
- wire p_15_in;
- wire p_1_in;
- wire p_21_in;
- wire [7:0]p_2_in;
- wire p_2_in30_in;
- wire [1:0]p_2_out;
- wire p_32_in;
- wire p_3_in;
- wire [1:0]p_5_out;
- wire p_6_in22_in;
- wire p_6_in34_in;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [2:1]previous_cycle_control_r;
- wire [0:0]\previous_cycle_control_r_reg[0]_0 ;
- wire [7:0]\previous_cycle_data_r_reg[7]_0 ;
- wire \previous_cycle_data_r_reg_n_0_[16] ;
- wire \previous_cycle_data_r_reg_n_0_[17] ;
- wire \previous_cycle_data_r_reg_n_0_[18] ;
- wire \previous_cycle_data_r_reg_n_0_[19] ;
- wire \previous_cycle_data_r_reg_n_0_[20] ;
- wire \previous_cycle_data_r_reg_n_0_[21] ;
- wire \previous_cycle_data_r_reg_n_0_[22] ;
- wire \previous_cycle_data_r_reg_n_0_[23] ;
- wire reset_lanes_i;
- wire [1:7]rx_cc_r;
- wire \rx_ecp_d_r_reg_n_0_[3] ;
- wire \rx_ecp_d_r_reg_n_0_[5] ;
- wire \rx_ecp_d_r_reg_n_0_[7] ;
- wire rx_neg_descram_in;
- wire [0:2]rx_pad_d_r;
- wire \rx_pe_control_r_reg_n_0_[3] ;
- wire [0:31]rx_pe_data_descram_in;
- wire [0:31]rx_pe_data_r;
- wire \rx_scp_d_r_reg_n_0_[3] ;
- wire \rx_scp_d_r_reg_n_0_[7] ;
- wire rx_sp_descram_in;
- wire [0:1]rx_sp_neg_d_r;
- wire [0:7]rx_sp_r;
- wire \rx_sp_r[2]_i_1_n_0 ;
- wire \rx_sp_r[3]_i_1_n_0 ;
- wire \rx_sp_r[4]_i_1_n_0 ;
- wire \rx_sp_r[5]_i_1_n_0 ;
- wire \rx_sp_r[6]_i_1_n_0 ;
- wire \rx_sp_r[7]_i_1_n_0 ;
- wire rx_spa_descram_in;
- wire [0:1]rx_spa_neg_d_r;
- wire [2:7]rx_spa_r;
- wire [2:7]rx_v_d_r;
- wire std_bool;
- wire std_bool11_out;
- wire std_bool13_in;
- wire std_bool13_out;
- wire std_bool16_in;
- wire std_bool1_out;
- wire user_clk;
- wire [0:3]word_aligned_control_bits_r;
- wire \word_aligned_control_bits_r[0]_i_1_n_0 ;
- wire \word_aligned_control_bits_r[1]_i_1_n_0 ;
- wire \word_aligned_control_bits_r_reg[2]_0 ;
- wire \word_aligned_control_bits_r_reg[3]_0 ;
- wire \word_aligned_data_r[0]_i_1_n_0 ;
- wire \word_aligned_data_r[10]_i_1_n_0 ;
- wire \word_aligned_data_r[11]_i_1_n_0 ;
- wire \word_aligned_data_r[12]_i_1_n_0 ;
- wire \word_aligned_data_r[13]_i_1_n_0 ;
- wire \word_aligned_data_r[14]_i_1_n_0 ;
- wire \word_aligned_data_r[15]_i_1_n_0 ;
- wire \word_aligned_data_r[1]_i_1_n_0 ;
- wire \word_aligned_data_r[2]_i_1_n_0 ;
- wire \word_aligned_data_r[3]_i_1_n_0 ;
- wire \word_aligned_data_r[4]_i_1_n_0 ;
- wire \word_aligned_data_r[5]_i_1_n_0 ;
- wire \word_aligned_data_r[6]_i_1_n_0 ;
- wire \word_aligned_data_r[7]_i_1_n_0 ;
- wire \word_aligned_data_r[8]_i_1_n_0 ;
- wire \word_aligned_data_r[9]_i_1_n_0 ;
- wire [7:0]\word_aligned_data_r_reg[16]_0 ;
- wire [7:0]\word_aligned_data_r_reg[24]_0 ;
- wire \word_aligned_data_r_reg_n_0_[0] ;
- wire \word_aligned_data_r_reg_n_0_[12] ;
- wire \word_aligned_data_r_reg_n_0_[13] ;
- wire \word_aligned_data_r_reg_n_0_[14] ;
- wire \word_aligned_data_r_reg_n_0_[15] ;
- wire \word_aligned_data_r_reg_n_0_[16] ;
- wire \word_aligned_data_r_reg_n_0_[17] ;
- wire \word_aligned_data_r_reg_n_0_[18] ;
- wire \word_aligned_data_r_reg_n_0_[19] ;
- wire \word_aligned_data_r_reg_n_0_[1] ;
- wire \word_aligned_data_r_reg_n_0_[20] ;
- wire \word_aligned_data_r_reg_n_0_[21] ;
- wire \word_aligned_data_r_reg_n_0_[22] ;
- wire \word_aligned_data_r_reg_n_0_[23] ;
- wire \word_aligned_data_r_reg_n_0_[24] ;
- wire \word_aligned_data_r_reg_n_0_[25] ;
- wire \word_aligned_data_r_reg_n_0_[26] ;
- wire \word_aligned_data_r_reg_n_0_[27] ;
- wire \word_aligned_data_r_reg_n_0_[28] ;
- wire \word_aligned_data_r_reg_n_0_[29] ;
- wire \word_aligned_data_r_reg_n_0_[2] ;
- wire \word_aligned_data_r_reg_n_0_[30] ;
- wire \word_aligned_data_r_reg_n_0_[31] ;
- wire \word_aligned_data_r_reg_n_0_[3] ;
- wire \word_aligned_data_r_reg_n_0_[4] ;
- wire \word_aligned_data_r_reg_n_0_[5] ;
- wire \word_aligned_data_r_reg_n_0_[6] ;
- wire \word_aligned_data_r_reg_n_0_[7] ;
-
- (* SOFT_HLUTNM = "soft_lutpair149" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[31]),
- .I2(\DOUT_reg[0] [15]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [0]));
- (* SOFT_HLUTNM = "soft_lutpair140" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[15]),
- .I2(\DOUT_reg[0]_0 [15]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [0]));
- (* SOFT_HLUTNM = "soft_lutpair137" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[21]),
- .I2(\DOUT_reg[0] [5]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [10]));
- (* SOFT_HLUTNM = "soft_lutpair145" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[5]),
- .I2(\DOUT_reg[0]_0 [5]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [10]));
- (* SOFT_HLUTNM = "soft_lutpair139" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[20]),
- .I2(\DOUT_reg[0] [4]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [11]));
- (* SOFT_HLUTNM = "soft_lutpair144" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[4]),
- .I2(\DOUT_reg[0]_0 [4]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [11]));
- (* SOFT_HLUTNM = "soft_lutpair138" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[19]),
- .I2(\DOUT_reg[0] [3]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [12]));
- (* SOFT_HLUTNM = "soft_lutpair143" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[3]),
- .I2(\DOUT_reg[0]_0 [3]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [12]));
- (* SOFT_HLUTNM = "soft_lutpair138" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[18]),
- .I2(\DOUT_reg[0] [2]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [13]));
- (* SOFT_HLUTNM = "soft_lutpair142" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[2]),
- .I2(\DOUT_reg[0]_0 [2]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [13]));
- (* SOFT_HLUTNM = "soft_lutpair137" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[17]),
- .I2(\DOUT_reg[0] [1]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [14]));
- (* SOFT_HLUTNM = "soft_lutpair141" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[1]),
- .I2(\DOUT_reg[0]_0 [1]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [14]));
- (* SOFT_HLUTNM = "soft_lutpair136" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[16]),
- .I2(\DOUT_reg[0] [0]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [15]));
- (* SOFT_HLUTNM = "soft_lutpair140" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[0]),
- .I2(\DOUT_reg[0]_0 [0]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [15]));
- (* SOFT_HLUTNM = "soft_lutpair150" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[30]),
- .I2(\DOUT_reg[0] [14]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair141" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[14]),
- .I2(\DOUT_reg[0]_0 [14]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair151" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[29]),
- .I2(\DOUT_reg[0] [13]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [2]));
- (* SOFT_HLUTNM = "soft_lutpair142" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[13]),
- .I2(\DOUT_reg[0]_0 [13]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [2]));
- (* SOFT_HLUTNM = "soft_lutpair151" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[28]),
- .I2(\DOUT_reg[0] [12]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [3]));
- (* SOFT_HLUTNM = "soft_lutpair143" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[12]),
- .I2(\DOUT_reg[0]_0 [12]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [3]));
- (* SOFT_HLUTNM = "soft_lutpair150" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[27]),
- .I2(\DOUT_reg[0] [11]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [4]));
- (* SOFT_HLUTNM = "soft_lutpair144" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[11]),
- .I2(\DOUT_reg[0]_0 [11]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [4]));
- (* SOFT_HLUTNM = "soft_lutpair136" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[26]),
- .I2(\DOUT_reg[0] [10]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [5]));
- (* SOFT_HLUTNM = "soft_lutpair145" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[10]),
- .I2(\DOUT_reg[0]_0 [10]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [5]));
- (* SOFT_HLUTNM = "soft_lutpair149" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[25]),
- .I2(\DOUT_reg[0] [9]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [6]));
- (* SOFT_HLUTNM = "soft_lutpair146" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[9]),
- .I2(\DOUT_reg[0]_0 [9]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [6]));
- (* SOFT_HLUTNM = "soft_lutpair148" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[24]),
- .I2(\DOUT_reg[0] [8]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [7]));
- (* SOFT_HLUTNM = "soft_lutpair147" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[8]),
- .I2(\DOUT_reg[0]_0 [8]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [7]));
- (* SOFT_HLUTNM = "soft_lutpair148" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[23]),
- .I2(\DOUT_reg[0] [7]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [8]));
- (* SOFT_HLUTNM = "soft_lutpair147" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[7]),
- .I2(\DOUT_reg[0]_0 [7]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [8]));
- (* SOFT_HLUTNM = "soft_lutpair139" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1
- (.I0(BYPASS),
- .I1(rx_pe_data_descram_in[22]),
- .I2(\DOUT_reg[0] [6]),
- .O(\RX_PE_DATA_Buffer_reg[16]_0 [9]));
- (* SOFT_HLUTNM = "soft_lutpair146" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1__0
- (.I0(bypass_w_reg),
- .I1(rx_pe_data_descram_in[6]),
- .I2(\DOUT_reg[0]_0 [6]),
- .O(\RX_PE_DATA_Buffer_reg[0]_0 [9]));
- (* SOFT_HLUTNM = "soft_lutpair121" *)
- LUT4 #(
- .INIT(16'h1000))
- EXP_IN
- (.I0(\word_aligned_data_r_reg_n_0_[6] ),
- .I1(\word_aligned_data_r_reg_n_0_[7] ),
- .I2(\word_aligned_data_r_reg_n_0_[5] ),
- .I3(\word_aligned_data_r_reg_n_0_[4] ),
- .O(EXP_IN_n_0));
- (* SOFT_HLUTNM = "soft_lutpair119" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__0/i_
- (.I0(\word_aligned_data_r_reg_n_0_[1] ),
- .I1(\word_aligned_data_r_reg_n_0_[0] ),
- .I2(\word_aligned_data_r_reg_n_0_[2] ),
- .I3(\word_aligned_data_r_reg_n_0_[3] ),
- .O(\EXP_IN_inferred__0/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair134" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__1/i_
- (.I0(\word_aligned_data_r_reg_n_0_[29] ),
- .I1(\word_aligned_data_r_reg_n_0_[30] ),
- .I2(\word_aligned_data_r_reg_n_0_[28] ),
- .I3(\word_aligned_data_r_reg_n_0_[31] ),
- .O(\EXP_IN_inferred__1/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair122" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__10/i_
- (.I0(\word_aligned_data_r_reg_n_0_[14] ),
- .I1(\word_aligned_data_r_reg_n_0_[15] ),
- .I2(\word_aligned_data_r_reg_n_0_[13] ),
- .I3(\word_aligned_data_r_reg_n_0_[12] ),
- .O(\EXP_IN_inferred__10/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair130" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__11/i_
- (.I0(p_0_in[2]),
- .I1(p_0_in[1]),
- .I2(p_0_in[3]),
- .I3(p_0_in[0]),
- .O(\EXP_IN_inferred__11/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair135" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__12/i_
- (.I0(\word_aligned_data_r_reg_n_0_[29] ),
- .I1(\word_aligned_data_r_reg_n_0_[28] ),
- .I2(\word_aligned_data_r_reg_n_0_[30] ),
- .I3(\word_aligned_data_r_reg_n_0_[31] ),
- .O(\EXP_IN_inferred__12/i__n_0 ));
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__13/i_
- (.I0(\word_aligned_data_r_reg_n_0_[26] ),
- .I1(\word_aligned_data_r_reg_n_0_[27] ),
- .I2(\word_aligned_data_r_reg_n_0_[25] ),
- .I3(\word_aligned_data_r_reg_n_0_[24] ),
- .O(\EXP_IN_inferred__13/i__n_0 ));
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__14/i_
- (.I0(\word_aligned_data_r_reg_n_0_[22] ),
- .I1(\word_aligned_data_r_reg_n_0_[23] ),
- .I2(\word_aligned_data_r_reg_n_0_[21] ),
- .I3(\word_aligned_data_r_reg_n_0_[20] ),
- .O(\EXP_IN_inferred__14/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair128" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__15/i_
- (.I0(\word_aligned_data_r_reg_n_0_[16] ),
- .I1(\word_aligned_data_r_reg_n_0_[18] ),
- .I2(\word_aligned_data_r_reg_n_0_[17] ),
- .I3(\word_aligned_data_r_reg_n_0_[19] ),
- .O(\EXP_IN_inferred__15/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair126" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__16/i_
- (.I0(\word_aligned_data_r_reg_n_0_[13] ),
- .I1(\word_aligned_data_r_reg_n_0_[12] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__16/i__n_0 ));
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__17/i_
- (.I0(p_0_in[1]),
- .I1(p_0_in[0]),
- .I2(p_0_in[2]),
- .I3(p_0_in[3]),
- .O(\EXP_IN_inferred__17/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair120" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__18/i_
- (.I0(\word_aligned_data_r_reg_n_0_[0] ),
- .I1(\word_aligned_data_r_reg_n_0_[2] ),
- .I2(\word_aligned_data_r_reg_n_0_[1] ),
- .I3(\word_aligned_data_r_reg_n_0_[3] ),
- .O(\EXP_IN_inferred__18/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair134" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__19/i_
- (.I0(\word_aligned_data_r_reg_n_0_[31] ),
- .I1(\word_aligned_data_r_reg_n_0_[29] ),
- .I2(\word_aligned_data_r_reg_n_0_[28] ),
- .I3(\word_aligned_data_r_reg_n_0_[30] ),
- .O(\EXP_IN_inferred__19/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair115" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__2/i_
- (.I0(\word_aligned_data_r_reg_n_0_[27] ),
- .I1(\word_aligned_data_r_reg_n_0_[25] ),
- .I2(\word_aligned_data_r_reg_n_0_[24] ),
- .I3(\word_aligned_data_r_reg_n_0_[26] ),
- .O(\EXP_IN_inferred__2/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair133" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__20/i_
- (.I0(\word_aligned_data_r_reg_n_0_[22] ),
- .I1(\word_aligned_data_r_reg_n_0_[21] ),
- .I2(\word_aligned_data_r_reg_n_0_[20] ),
- .I3(\word_aligned_data_r_reg_n_0_[23] ),
- .O(\EXP_IN_inferred__20/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair132" *)
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__21/i_
- (.I0(\word_aligned_data_r_reg_n_0_[18] ),
- .I1(\word_aligned_data_r_reg_n_0_[19] ),
- .I2(\word_aligned_data_r_reg_n_0_[17] ),
- .I3(\word_aligned_data_r_reg_n_0_[16] ),
- .O(\EXP_IN_inferred__21/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair131" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__22/i_
- (.I0(\word_aligned_data_r_reg_n_0_[15] ),
- .I1(\word_aligned_data_r_reg_n_0_[13] ),
- .I2(\word_aligned_data_r_reg_n_0_[12] ),
- .I3(\word_aligned_data_r_reg_n_0_[14] ),
- .O(\EXP_IN_inferred__22/i__n_0 ));
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__23/i_
- (.I0(\word_aligned_data_r_reg_n_0_[6] ),
- .I1(\word_aligned_data_r_reg_n_0_[5] ),
- .I2(\word_aligned_data_r_reg_n_0_[4] ),
- .I3(\word_aligned_data_r_reg_n_0_[7] ),
- .O(\EXP_IN_inferred__23/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair120" *)
- LUT4 #(
- .INIT(16'h8000))
- \EXP_IN_inferred__24/i_
- (.I0(\word_aligned_data_r_reg_n_0_[2] ),
- .I1(\word_aligned_data_r_reg_n_0_[3] ),
- .I2(\word_aligned_data_r_reg_n_0_[1] ),
- .I3(\word_aligned_data_r_reg_n_0_[0] ),
- .O(\EXP_IN_inferred__24/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair132" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__25/i_
- (.I0(\word_aligned_data_r_reg_n_0_[17] ),
- .I1(\word_aligned_data_r_reg_n_0_[18] ),
- .I2(\word_aligned_data_r_reg_n_0_[16] ),
- .I3(\word_aligned_data_r_reg_n_0_[19] ),
- .O(\EXP_IN_inferred__25/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair119" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__26/i_
- (.I0(\word_aligned_data_r_reg_n_0_[1] ),
- .I1(\word_aligned_data_r_reg_n_0_[2] ),
- .I2(\word_aligned_data_r_reg_n_0_[0] ),
- .I3(\word_aligned_data_r_reg_n_0_[3] ),
- .O(\EXP_IN_inferred__26/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair131" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__27/i_
- (.I0(\word_aligned_data_r_reg_n_0_[12] ),
- .I1(\word_aligned_data_r_reg_n_0_[14] ),
- .I2(\word_aligned_data_r_reg_n_0_[13] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(std_bool13_in));
- (* SOFT_HLUTNM = "soft_lutpair130" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__28/i_
- (.I0(p_0_in[2]),
- .I1(p_0_in[3]),
- .I2(p_0_in[1]),
- .I3(p_0_in[0]),
- .O(std_bool16_in));
- (* SOFT_HLUTNM = "soft_lutpair133" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__3/i_
- (.I0(\word_aligned_data_r_reg_n_0_[21] ),
- .I1(\word_aligned_data_r_reg_n_0_[22] ),
- .I2(\word_aligned_data_r_reg_n_0_[20] ),
- .I3(\word_aligned_data_r_reg_n_0_[23] ),
- .O(\EXP_IN_inferred__3/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair129" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__30/i_
- (.I0(\word_aligned_data_r_reg_n_0_[25] ),
- .I1(\word_aligned_data_r_reg_n_0_[24] ),
- .I2(\word_aligned_data_r_reg_n_0_[26] ),
- .I3(\word_aligned_data_r_reg_n_0_[27] ),
- .O(\EXP_IN_inferred__30/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair128" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__31/i_
- (.I0(\word_aligned_data_r_reg_n_0_[17] ),
- .I1(\word_aligned_data_r_reg_n_0_[16] ),
- .I2(\word_aligned_data_r_reg_n_0_[18] ),
- .I3(\word_aligned_data_r_reg_n_0_[19] ),
- .O(\EXP_IN_inferred__31/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair127" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__32/i_
- (.I0(p_0_in[2]),
- .I1(p_0_in[3]),
- .I2(p_0_in[1]),
- .I3(p_0_in[0]),
- .O(\EXP_IN_inferred__32/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair126" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__34/i_
- (.I0(\word_aligned_data_r_reg_n_0_[13] ),
- .I1(\word_aligned_data_r_reg_n_0_[12] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__34/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair125" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__35/i_
- (.I0(p_0_in[1]),
- .I1(p_0_in[2]),
- .I2(p_0_in[3]),
- .I3(p_0_in[0]),
- .O(\EXP_IN_inferred__35/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair116" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__4/i_
- (.I0(\word_aligned_data_r_reg_n_0_[19] ),
- .I1(\word_aligned_data_r_reg_n_0_[17] ),
- .I2(\word_aligned_data_r_reg_n_0_[16] ),
- .I3(\word_aligned_data_r_reg_n_0_[18] ),
- .O(\EXP_IN_inferred__4/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair124" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__44/i_
- (.I0(\word_aligned_data_r_reg_n_0_[28] ),
- .I1(\word_aligned_data_r_reg_n_0_[29] ),
- .I2(\word_aligned_data_r_reg_n_0_[30] ),
- .I3(\word_aligned_data_r_reg_n_0_[31] ),
- .O(\EXP_IN_inferred__44/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair123" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__45/i_
- (.I0(\word_aligned_data_r_reg_n_0_[20] ),
- .I1(\word_aligned_data_r_reg_n_0_[21] ),
- .I2(\word_aligned_data_r_reg_n_0_[22] ),
- .I3(\word_aligned_data_r_reg_n_0_[23] ),
- .O(\EXP_IN_inferred__45/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair122" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__46/i_
- (.I0(\word_aligned_data_r_reg_n_0_[12] ),
- .I1(\word_aligned_data_r_reg_n_0_[13] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__46/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair121" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__47/i_
- (.I0(\word_aligned_data_r_reg_n_0_[4] ),
- .I1(\word_aligned_data_r_reg_n_0_[5] ),
- .I2(\word_aligned_data_r_reg_n_0_[6] ),
- .I3(\word_aligned_data_r_reg_n_0_[7] ),
- .O(\EXP_IN_inferred__47/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair114" *)
- LUT4 #(
- .INIT(16'h0010))
- \EXP_IN_inferred__5/i_
- (.I0(\word_aligned_data_r_reg_n_0_[13] ),
- .I1(\word_aligned_data_r_reg_n_0_[14] ),
- .I2(\word_aligned_data_r_reg_n_0_[12] ),
- .I3(\word_aligned_data_r_reg_n_0_[15] ),
- .O(\EXP_IN_inferred__5/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair127" *)
- LUT4 #(
- .INIT(16'h4000))
- \EXP_IN_inferred__6/i_
- (.I0(p_0_in[0]),
- .I1(p_0_in[2]),
- .I2(p_0_in[3]),
- .I3(p_0_in[1]),
- .O(std_bool));
- (* SOFT_HLUTNM = "soft_lutpair135" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__8/i_
- (.I0(\word_aligned_data_r_reg_n_0_[30] ),
- .I1(\word_aligned_data_r_reg_n_0_[31] ),
- .I2(\word_aligned_data_r_reg_n_0_[29] ),
- .I3(\word_aligned_data_r_reg_n_0_[28] ),
- .O(\EXP_IN_inferred__8/i__n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair129" *)
- LUT4 #(
- .INIT(16'h1000))
- \EXP_IN_inferred__9/i_
- (.I0(\word_aligned_data_r_reg_n_0_[25] ),
- .I1(\word_aligned_data_r_reg_n_0_[26] ),
- .I2(\word_aligned_data_r_reg_n_0_[24] ),
- .I3(\word_aligned_data_r_reg_n_0_[27] ),
- .O(\EXP_IN_inferred__9/i__n_0 ));
- LUT6 #(
- .INIT(64'h2000000000000000))
- GOT_V_Buffer_i_1
- (.I0(RX_SP_Buffer_i_2_n_0),
- .I1(GOT_V_Buffer_i_2_n_0),
- .I2(rx_sp_r[0]),
- .I3(rx_sp_r[1]),
- .I4(rx_v_d_r[3]),
- .I5(rx_v_d_r[2]),
- .O(std_bool1_out));
- LUT4 #(
- .INIT(16'h7FFF))
- GOT_V_Buffer_i_2
- (.I0(rx_v_d_r[5]),
- .I1(rx_v_d_r[4]),
- .I2(rx_v_d_r[7]),
- .I3(rx_v_d_r[6]),
- .O(GOT_V_Buffer_i_2_n_0));
- FDRE GOT_V_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool1_out),
- .Q(got_v_descram_in),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0000000000008000))
- RX_CC_Buffer_i_1
- (.I0(p_1_in),
- .I1(\rx_pe_control_r_reg_n_0_[3] ),
- .I2(p_3_in),
- .I3(p_0_in26_in),
- .I4(RX_CC_Buffer_i_2_n_0),
- .I5(RX_CC_Buffer_i_3_n_0),
- .O(RX_CC_Buffer_i_1_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_CC_Buffer_i_2
- (.I0(rx_cc_r[5]),
- .I1(p_0_in18_in),
- .I2(rx_cc_r[7]),
- .I3(p_2_in30_in),
- .O(RX_CC_Buffer_i_2_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_CC_Buffer_i_3
- (.I0(p_21_in),
- .I1(rx_cc_r[1]),
- .I2(rx_cc_r[3]),
- .I3(p_6_in34_in),
- .O(RX_CC_Buffer_i_3_n_0));
- FDRE RX_CC_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_CC_Buffer_i_1_n_0),
- .Q(D),
- .R(1'b0));
- LUT5 #(
- .INIT(32'h0000F888))
- RX_NEG_Buffer_i_1
- (.I0(rx_spa_neg_d_r[1]),
- .I1(rx_spa_neg_d_r[0]),
- .I2(rx_sp_neg_d_r[1]),
- .I3(rx_sp_neg_d_r[0]),
- .I4(p_0_in26_in),
- .O(RX_NEG_Buffer0));
- FDRE RX_NEG_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(RX_NEG_Buffer0),
- .Q(rx_neg_descram_in),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair118" *)
- LUT4 #(
- .INIT(16'h0800))
- \RX_PAD_Buffer[0]_i_1
- (.I0(rx_pad_d_r[0]),
- .I1(rx_spa_r[3]),
- .I2(p_3_in),
- .I3(p_0_in26_in),
- .O(p_2_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair117" *)
- LUT4 #(
- .INIT(16'h0800))
- \RX_PAD_Buffer[1]_i_1
- (.I0(rx_pad_d_r[2]),
- .I1(rx_spa_r[7]),
- .I2(p_1_in),
- .I3(\rx_pe_control_r_reg_n_0_[3] ),
- .O(p_2_out[0]));
- FDRE \RX_PAD_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_out[1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \RX_PAD_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_2_out[0]),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[0]),
- .Q(rx_pe_data_descram_in[0]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[10]),
- .Q(rx_pe_data_descram_in[10]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[11]),
- .Q(rx_pe_data_descram_in[11]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[12]),
- .Q(rx_pe_data_descram_in[12]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[13]),
- .Q(rx_pe_data_descram_in[13]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[14]),
- .Q(rx_pe_data_descram_in[14]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[15]),
- .Q(rx_pe_data_descram_in[15]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[16]),
- .Q(rx_pe_data_descram_in[16]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[17]),
- .Q(rx_pe_data_descram_in[17]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[18]),
- .Q(rx_pe_data_descram_in[18]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[19]),
- .Q(rx_pe_data_descram_in[19]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[1]),
- .Q(rx_pe_data_descram_in[1]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[20]),
- .Q(rx_pe_data_descram_in[20]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[21]),
- .Q(rx_pe_data_descram_in[21]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[22]),
- .Q(rx_pe_data_descram_in[22]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[23]),
- .Q(rx_pe_data_descram_in[23]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[24]),
- .Q(rx_pe_data_descram_in[24]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[25]),
- .Q(rx_pe_data_descram_in[25]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[26]),
- .Q(rx_pe_data_descram_in[26]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[27]),
- .Q(rx_pe_data_descram_in[27]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[28]),
- .Q(rx_pe_data_descram_in[28]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[29]),
- .Q(rx_pe_data_descram_in[29]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[2]),
- .Q(rx_pe_data_descram_in[2]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[30]),
- .Q(rx_pe_data_descram_in[30]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[31]),
- .Q(rx_pe_data_descram_in[31]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[3]),
- .Q(rx_pe_data_descram_in[3]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[4]),
- .Q(rx_pe_data_descram_in[4]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[5]),
- .Q(rx_pe_data_descram_in[5]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[6]),
- .Q(rx_pe_data_descram_in[6]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[7]),
- .Q(rx_pe_data_descram_in[7]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[8]),
- .Q(rx_pe_data_descram_in[8]),
- .R(1'b0));
- FDRE \RX_PE_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_pe_data_r[9]),
- .Q(rx_pe_data_descram_in[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair118" *)
- LUT1 #(
- .INIT(2'h1))
- \RX_PE_DATA_V_Buffer[0]_i_1
- (.I0(p_3_in),
- .O(\RX_PE_DATA_V_Buffer[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair117" *)
- LUT1 #(
- .INIT(2'h1))
- \RX_PE_DATA_V_Buffer[1]_i_1
- (.I0(p_1_in),
- .O(\RX_PE_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \RX_PE_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_Buffer[0]_i_1_n_0 ),
- .Q(\RX_PE_DATA_V_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_PE_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\RX_PE_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(\RX_PE_DATA_V_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h2000000000000000))
- RX_SPA_Buffer_i_1
- (.I0(RX_SP_Buffer_i_2_n_0),
- .I1(RX_SPA_Buffer_i_2_n_0),
- .I2(rx_sp_r[0]),
- .I3(rx_sp_r[1]),
- .I4(rx_spa_r[3]),
- .I5(rx_spa_r[2]),
- .O(std_bool11_out));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_SPA_Buffer_i_2
- (.I0(rx_spa_r[5]),
- .I1(rx_spa_r[4]),
- .I2(rx_spa_r[7]),
- .I3(rx_spa_r[6]),
- .O(RX_SPA_Buffer_i_2_n_0));
- FDRE RX_SPA_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool11_out),
- .Q(rx_spa_descram_in),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h2000000000000000))
- RX_SP_Buffer_i_1
- (.I0(RX_SP_Buffer_i_2_n_0),
- .I1(RX_SP_Buffer_i_3_n_0),
- .I2(rx_sp_r[0]),
- .I3(rx_sp_r[1]),
- .I4(rx_sp_r[3]),
- .I5(rx_sp_r[2]),
- .O(std_bool13_out));
- LUT4 #(
- .INIT(16'h0010))
- RX_SP_Buffer_i_2
- (.I0(\rx_pe_control_r_reg_n_0_[3] ),
- .I1(p_0_in26_in),
- .I2(p_3_in),
- .I3(p_1_in),
- .O(RX_SP_Buffer_i_2_n_0));
- LUT4 #(
- .INIT(16'h7FFF))
- RX_SP_Buffer_i_3
- (.I0(rx_sp_r[5]),
- .I1(rx_sp_r[4]),
- .I2(rx_sp_r[7]),
- .I3(rx_sp_r[6]),
- .O(RX_SP_Buffer_i_3_n_0));
- FDRE RX_SP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool13_out),
- .Q(rx_sp_descram_in),
- .R(1'b0));
- LUT3 #(
- .INIT(8'h80))
- \RX_SUF_Buffer[0]_i_1
- (.I0(p_3_in),
- .I1(p_15_in),
- .I2(rx_sp_r[1]),
- .O(p_5_out[1]));
- LUT3 #(
- .INIT(8'h80))
- \RX_SUF_Buffer[1]_i_1
- (.I0(p_1_in),
- .I1(p_0_in14_in),
- .I2(rx_spa_r[5]),
- .O(p_5_out[0]));
- FDRE \RX_SUF_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_5_out[1]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \RX_SUF_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_5_out[0]),
- .Q(\RX_SUF_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair112" *)
- LUT5 #(
- .INIT(32'hFFFDFFFF))
- \bypass_r[0]_i_1
- (.I0(\RX_PE_DATA_V_Buffer_reg[0]_0 [1]),
- .I1(Q[1]),
- .I2(got_v_descram_in),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(bypass_w_reg));
- (* SOFT_HLUTNM = "soft_lutpair113" *)
- LUT5 #(
- .INIT(32'hFFFDFFFF))
- \bypass_r[1]_i_1
- (.I0(\RX_PE_DATA_V_Buffer_reg[0]_0 [0]),
- .I1(Q[0]),
- .I2(got_v_descram_in),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(BYPASS));
- LUT3 #(
- .INIT(8'hA8))
- first_v_received_r_i_1
- (.I0(LANE_UP),
- .I1(first_v_received_r),
- .I2(std_bool1_out),
- .O(first_v_received_r_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- first_v_received_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(first_v_received_r_i_1_n_0),
- .Q(first_v_received_r),
- .R(1'b0));
- FDRE \left_align_select_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\left_align_select_r_reg[0]_1 ),
- .Q(\left_align_select_r_reg[0]_0 ),
- .R(1'b0));
- FDRE \left_align_select_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\left_align_select_r_reg[1]_1 ),
- .Q(\left_align_select_r_reg[1]_0 ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair113" *)
- LUT5 #(
- .INIT(32'h00020000))
- \lfsr[15]_i_1
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(got_v_descram_in),
- .I3(Q[0]),
- .I4(\RX_PE_DATA_V_Buffer_reg[0]_0 [0]),
- .O(CHANNEL_UP_Buffer_reg));
- (* SOFT_HLUTNM = "soft_lutpair112" *)
- LUT5 #(
- .INIT(32'h00020000))
- \lfsr[15]_i_2
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(got_v_descram_in),
- .I3(Q[1]),
- .I4(\RX_PE_DATA_V_Buffer_reg[0]_0 [1]),
- .O(E));
- FDRE \previous_cycle_control_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXCHARISK[3]),
- .Q(\previous_cycle_control_r_reg[0]_0 ),
- .R(1'b0));
- FDRE \previous_cycle_control_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXCHARISK[2]),
- .Q(previous_cycle_control_r[1]),
- .R(1'b0));
- FDRE \previous_cycle_control_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXCHARISK[1]),
- .Q(previous_cycle_control_r[2]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[24]),
- .Q(\previous_cycle_data_r_reg[7]_0 [0]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[18]),
- .Q(p_2_in[2]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[19]),
- .Q(p_2_in[3]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[20]),
- .Q(p_2_in[4]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[21]),
- .Q(p_2_in[5]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[22]),
- .Q(p_2_in[6]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[23]),
- .Q(p_2_in[7]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[8]),
- .Q(\previous_cycle_data_r_reg_n_0_[16] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[9]),
- .Q(\previous_cycle_data_r_reg_n_0_[17] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[10]),
- .Q(\previous_cycle_data_r_reg_n_0_[18] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[11]),
- .Q(\previous_cycle_data_r_reg_n_0_[19] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[25]),
- .Q(\previous_cycle_data_r_reg[7]_0 [1]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[12]),
- .Q(\previous_cycle_data_r_reg_n_0_[20] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[13]),
- .Q(\previous_cycle_data_r_reg_n_0_[21] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[14]),
- .Q(\previous_cycle_data_r_reg_n_0_[22] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[15]),
- .Q(\previous_cycle_data_r_reg_n_0_[23] ),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[26]),
- .Q(\previous_cycle_data_r_reg[7]_0 [2]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[27]),
- .Q(\previous_cycle_data_r_reg[7]_0 [3]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[28]),
- .Q(\previous_cycle_data_r_reg[7]_0 [4]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[29]),
- .Q(\previous_cycle_data_r_reg[7]_0 [5]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[30]),
- .Q(\previous_cycle_data_r_reg[7]_0 [6]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[31]),
- .Q(\previous_cycle_data_r_reg[7]_0 [7]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[16]),
- .Q(p_2_in[0]),
- .R(1'b0));
- FDRE \previous_cycle_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(RXDATA[17]),
- .Q(p_2_in[1]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__47/i__n_0 ),
- .Q(rx_cc_r[1]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__46/i__n_0 ),
- .Q(rx_cc_r[3]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__45/i__n_0 ),
- .Q(rx_cc_r[5]),
- .R(1'b0));
- FDRE \rx_cc_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__44/i__n_0 ),
- .Q(rx_cc_r[7]),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__24/i__n_0 ),
- .Q(p_21_in),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__23/i__n_0 ),
- .Q(p_6_in22_in),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__22/i__n_0 ),
- .Q(\rx_ecp_d_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__21/i__n_0 ),
- .Q(p_0_in18_in),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__20/i__n_0 ),
- .Q(\rx_ecp_d_r_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \rx_ecp_d_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__19/i__n_0 ),
- .Q(\rx_ecp_d_r_reg_n_0_[7] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_ecp_r_reg[0]_srl3_i_1
- (.I0(p_0_in26_in),
- .I1(p_3_in),
- .I2(p_6_in22_in),
- .I3(p_21_in),
- .I4(\rx_ecp_d_r_reg_n_0_[3] ),
- .I5(p_6_in34_in),
- .O(p_9_out[1]));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_ecp_r_reg[1]_srl3_i_1
- (.I0(\rx_pe_control_r_reg_n_0_[3] ),
- .I1(p_1_in),
- .I2(\rx_ecp_d_r_reg_n_0_[5] ),
- .I3(p_0_in18_in),
- .I4(\rx_ecp_d_r_reg_n_0_[7] ),
- .I5(p_2_in30_in),
- .O(p_9_out[0]));
- FDRE \rx_pad_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__11/i__n_0 ),
- .Q(rx_pad_d_r[0]),
- .R(1'b0));
- FDRE \rx_pad_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__9/i__n_0 ),
- .Q(rx_pad_d_r[2]),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[0]),
- .Q(p_3_in),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[1]),
- .Q(p_0_in26_in),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[2]),
- .Q(p_1_in),
- .R(1'b0));
- FDRE \rx_pe_control_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(word_aligned_control_bits_r[3]),
- .Q(\rx_pe_control_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[0] ),
- .Q(rx_pe_data_r[0]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[1]),
- .Q(rx_pe_data_r[10]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[0]),
- .Q(rx_pe_data_r[11]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[12] ),
- .Q(rx_pe_data_r[12]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[13] ),
- .Q(rx_pe_data_r[13]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[14] ),
- .Q(rx_pe_data_r[14]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[15] ),
- .Q(rx_pe_data_r[15]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[16] ),
- .Q(rx_pe_data_r[16]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[17] ),
- .Q(rx_pe_data_r[17]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[18] ),
- .Q(rx_pe_data_r[18]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[19] ),
- .Q(rx_pe_data_r[19]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[1] ),
- .Q(rx_pe_data_r[1]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[20] ),
- .Q(rx_pe_data_r[20]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[21] ),
- .Q(rx_pe_data_r[21]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[22] ),
- .Q(rx_pe_data_r[22]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[23] ),
- .Q(rx_pe_data_r[23]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[24] ),
- .Q(rx_pe_data_r[24]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[25] ),
- .Q(rx_pe_data_r[25]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[26] ),
- .Q(rx_pe_data_r[26]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[27] ),
- .Q(rx_pe_data_r[27]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[28] ),
- .Q(rx_pe_data_r[28]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[29] ),
- .Q(rx_pe_data_r[29]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[2] ),
- .Q(rx_pe_data_r[2]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[30] ),
- .Q(rx_pe_data_r[30]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[31] ),
- .Q(rx_pe_data_r[31]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[3] ),
- .Q(rx_pe_data_r[3]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[4] ),
- .Q(rx_pe_data_r[4]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[5] ),
- .Q(rx_pe_data_r[5]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[6] ),
- .Q(rx_pe_data_r[6]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg_n_0_[7] ),
- .Q(rx_pe_data_r[7]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[3]),
- .Q(rx_pe_data_r[8]),
- .R(1'b0));
- FDRE \rx_pe_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_0_in[2]),
- .Q(rx_pe_data_r[9]),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__18/i__n_0 ),
- .Q(p_32_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__17/i__n_0 ),
- .Q(p_6_in34_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__16/i__n_0 ),
- .Q(\rx_scp_d_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__15/i__n_0 ),
- .Q(p_0_in28_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__13/i__n_0 ),
- .Q(p_2_in30_in),
- .R(1'b0));
- FDRE \rx_scp_d_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__12/i__n_0 ),
- .Q(\rx_scp_d_r_reg_n_0_[7] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_scp_r_reg[0]_srl3_i_1
- (.I0(p_0_in26_in),
- .I1(p_3_in),
- .I2(rx_sp_r[1]),
- .I3(p_32_in),
- .I4(\rx_scp_d_r_reg_n_0_[3] ),
- .I5(p_6_in34_in),
- .O(p_8_out[1]));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \rx_scp_r_reg[1]_srl3_i_1
- (.I0(\rx_pe_control_r_reg_n_0_[3] ),
- .I1(p_1_in),
- .I2(rx_spa_r[5]),
- .I3(p_0_in28_in),
- .I4(\rx_scp_d_r_reg_n_0_[7] ),
- .I5(p_2_in30_in),
- .O(p_8_out[0]));
- FDRE \rx_sp_neg_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool16_in),
- .Q(rx_sp_neg_d_r[0]),
- .R(1'b0));
- FDRE \rx_sp_neg_d_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool13_in),
- .Q(rx_sp_neg_d_r[1]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair125" *)
- LUT4 #(
- .INIT(16'h0180))
- \rx_sp_r[2]_i_1
- (.I0(p_0_in[0]),
- .I1(p_0_in[1]),
- .I2(p_0_in[3]),
- .I3(p_0_in[2]),
- .O(\rx_sp_r[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair114" *)
- LUT4 #(
- .INIT(16'h1008))
- \rx_sp_r[3]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[15] ),
- .I1(\word_aligned_data_r_reg_n_0_[13] ),
- .I2(\word_aligned_data_r_reg_n_0_[14] ),
- .I3(\word_aligned_data_r_reg_n_0_[12] ),
- .O(\rx_sp_r[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair116" *)
- LUT4 #(
- .INIT(16'h0810))
- \rx_sp_r[4]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[18] ),
- .I1(\word_aligned_data_r_reg_n_0_[19] ),
- .I2(\word_aligned_data_r_reg_n_0_[17] ),
- .I3(\word_aligned_data_r_reg_n_0_[16] ),
- .O(\rx_sp_r[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair123" *)
- LUT4 #(
- .INIT(16'h1008))
- \rx_sp_r[5]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[21] ),
- .I1(\word_aligned_data_r_reg_n_0_[23] ),
- .I2(\word_aligned_data_r_reg_n_0_[22] ),
- .I3(\word_aligned_data_r_reg_n_0_[20] ),
- .O(\rx_sp_r[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair115" *)
- LUT4 #(
- .INIT(16'h0810))
- \rx_sp_r[6]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[26] ),
- .I1(\word_aligned_data_r_reg_n_0_[27] ),
- .I2(\word_aligned_data_r_reg_n_0_[25] ),
- .I3(\word_aligned_data_r_reg_n_0_[24] ),
- .O(\rx_sp_r[6]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair124" *)
- LUT4 #(
- .INIT(16'h1008))
- \rx_sp_r[7]_i_1
- (.I0(\word_aligned_data_r_reg_n_0_[29] ),
- .I1(\word_aligned_data_r_reg_n_0_[31] ),
- .I2(\word_aligned_data_r_reg_n_0_[30] ),
- .I3(\word_aligned_data_r_reg_n_0_[28] ),
- .O(\rx_sp_r[7]_i_1_n_0 ));
- FDRE \rx_sp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__0/i__n_0 ),
- .Q(rx_sp_r[0]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(EXP_IN_n_0),
- .Q(rx_sp_r[1]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[2]_i_1_n_0 ),
- .Q(rx_sp_r[2]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[3]_i_1_n_0 ),
- .Q(rx_sp_r[3]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[4]_i_1_n_0 ),
- .Q(rx_sp_r[4]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[5]_i_1_n_0 ),
- .Q(rx_sp_r[5]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[6]_i_1_n_0 ),
- .Q(rx_sp_r[6]),
- .R(1'b0));
- FDRE \rx_sp_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_sp_r[7]_i_1_n_0 ),
- .Q(rx_sp_r[7]),
- .R(1'b0));
- FDRE \rx_spa_neg_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__35/i__n_0 ),
- .Q(rx_spa_neg_d_r[0]),
- .R(1'b0));
- FDRE \rx_spa_neg_d_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__34/i__n_0 ),
- .Q(rx_spa_neg_d_r[1]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__32/i__n_0 ),
- .Q(rx_spa_r[2]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__10/i__n_0 ),
- .Q(rx_spa_r[3]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__31/i__n_0 ),
- .Q(rx_spa_r[4]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__14/i__n_0 ),
- .Q(rx_spa_r[5]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__30/i__n_0 ),
- .Q(rx_spa_r[6]),
- .R(1'b0));
- FDRE \rx_spa_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__8/i__n_0 ),
- .Q(rx_spa_r[7]),
- .R(1'b0));
- FDRE \rx_suf_d_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__26/i__n_0 ),
- .Q(p_15_in),
- .R(1'b0));
- FDRE \rx_suf_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__25/i__n_0 ),
- .Q(p_0_in14_in),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(std_bool),
- .Q(rx_v_d_r[2]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__5/i__n_0 ),
- .Q(rx_v_d_r[3]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__4/i__n_0 ),
- .Q(rx_v_d_r[4]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__3/i__n_0 ),
- .Q(rx_v_d_r[5]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__2/i__n_0 ),
- .Q(rx_v_d_r[6]),
- .R(1'b0));
- FDRE \rx_v_d_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\EXP_IN_inferred__1/i__n_0 ),
- .Q(rx_v_d_r[7]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[0]_i_1
- (.I0(\previous_cycle_control_r_reg[0]_0 ),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(previous_cycle_control_r[1]),
- .I4(previous_cycle_control_r[2]),
- .I5(RXCHARISK[0]),
- .O(\word_aligned_control_bits_r[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[1]_i_1
- (.I0(RXCHARISK[0]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_control_r_reg[0]_0 ),
- .I4(previous_cycle_control_r[1]),
- .I5(RXCHARISK[1]),
- .O(\word_aligned_control_bits_r[1]_i_1_n_0 ));
- FDRE \word_aligned_control_bits_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r[0]_i_1_n_0 ),
- .Q(word_aligned_control_bits_r[0]),
- .R(1'b0));
- FDRE \word_aligned_control_bits_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r[1]_i_1_n_0 ),
- .Q(word_aligned_control_bits_r[1]),
- .R(1'b0));
- FDRE \word_aligned_control_bits_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r_reg[2]_0 ),
- .Q(word_aligned_control_bits_r[2]),
- .R(1'b0));
- FDRE \word_aligned_control_bits_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_control_bits_r_reg[3]_0 ),
- .Q(word_aligned_control_bits_r[3]),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[0]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [7]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[7]),
- .I4(\previous_cycle_data_r_reg_n_0_[23] ),
- .I5(RXDATA[7]),
- .O(\word_aligned_data_r[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[10]_i_1
- (.I0(RXDATA[5]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [5]),
- .I4(p_2_in[5]),
- .I5(RXDATA[13]),
- .O(\word_aligned_data_r[10]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[11]_i_1
- (.I0(RXDATA[4]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [4]),
- .I4(p_2_in[4]),
- .I5(RXDATA[12]),
- .O(\word_aligned_data_r[11]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[12]_i_1
- (.I0(RXDATA[3]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [3]),
- .I4(p_2_in[3]),
- .I5(RXDATA[11]),
- .O(\word_aligned_data_r[12]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[13]_i_1
- (.I0(RXDATA[2]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [2]),
- .I4(p_2_in[2]),
- .I5(RXDATA[10]),
- .O(\word_aligned_data_r[13]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[14]_i_1
- (.I0(RXDATA[1]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [1]),
- .I4(p_2_in[1]),
- .I5(RXDATA[9]),
- .O(\word_aligned_data_r[14]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[15]_i_1
- (.I0(RXDATA[0]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [0]),
- .I4(p_2_in[0]),
- .I5(RXDATA[8]),
- .O(\word_aligned_data_r[15]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[1]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [6]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[6]),
- .I4(\previous_cycle_data_r_reg_n_0_[22] ),
- .I5(RXDATA[6]),
- .O(\word_aligned_data_r[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[2]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [5]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[5]),
- .I4(\previous_cycle_data_r_reg_n_0_[21] ),
- .I5(RXDATA[5]),
- .O(\word_aligned_data_r[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[3]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [4]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[4]),
- .I4(\previous_cycle_data_r_reg_n_0_[20] ),
- .I5(RXDATA[4]),
- .O(\word_aligned_data_r[3]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[4]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [3]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[3]),
- .I4(\previous_cycle_data_r_reg_n_0_[19] ),
- .I5(RXDATA[3]),
- .O(\word_aligned_data_r[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[5]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [2]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[2]),
- .I4(\previous_cycle_data_r_reg_n_0_[18] ),
- .I5(RXDATA[2]),
- .O(\word_aligned_data_r[5]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[6]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [1]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[1]),
- .I4(\previous_cycle_data_r_reg_n_0_[17] ),
- .I5(RXDATA[1]),
- .O(\word_aligned_data_r[6]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[7]_i_1
- (.I0(\previous_cycle_data_r_reg[7]_0 [0]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(p_2_in[0]),
- .I4(\previous_cycle_data_r_reg_n_0_[16] ),
- .I5(RXDATA[0]),
- .O(\word_aligned_data_r[7]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[8]_i_1
- (.I0(RXDATA[7]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [7]),
- .I4(p_2_in[7]),
- .I5(RXDATA[15]),
- .O(\word_aligned_data_r[8]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[9]_i_1
- (.I0(RXDATA[6]),
- .I1(\left_align_select_r_reg[1]_0 ),
- .I2(\left_align_select_r_reg[0]_0 ),
- .I3(\previous_cycle_data_r_reg[7]_0 [6]),
- .I4(p_2_in[6]),
- .I5(RXDATA[14]),
- .O(\word_aligned_data_r[9]_i_1_n_0 ));
- FDRE \word_aligned_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[0]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[10]_i_1_n_0 ),
- .Q(p_0_in[1]),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[11]_i_1_n_0 ),
- .Q(p_0_in[0]),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[12]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[13]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[14]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[15]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [7]),
- .Q(\word_aligned_data_r_reg_n_0_[16] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [6]),
- .Q(\word_aligned_data_r_reg_n_0_[17] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [5]),
- .Q(\word_aligned_data_r_reg_n_0_[18] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [4]),
- .Q(\word_aligned_data_r_reg_n_0_[19] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[1]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [3]),
- .Q(\word_aligned_data_r_reg_n_0_[20] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [2]),
- .Q(\word_aligned_data_r_reg_n_0_[21] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [1]),
- .Q(\word_aligned_data_r_reg_n_0_[22] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[16]_0 [0]),
- .Q(\word_aligned_data_r_reg_n_0_[23] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [7]),
- .Q(\word_aligned_data_r_reg_n_0_[24] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [6]),
- .Q(\word_aligned_data_r_reg_n_0_[25] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [5]),
- .Q(\word_aligned_data_r_reg_n_0_[26] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [4]),
- .Q(\word_aligned_data_r_reg_n_0_[27] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [3]),
- .Q(\word_aligned_data_r_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [2]),
- .Q(\word_aligned_data_r_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[2]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [1]),
- .Q(\word_aligned_data_r_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r_reg[24]_0 [0]),
- .Q(\word_aligned_data_r_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[3]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[4]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[5]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[6]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[7]_i_1_n_0 ),
- .Q(\word_aligned_data_r_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[8]_i_1_n_0 ),
- .Q(p_0_in[3]),
- .R(1'b0));
- FDRE \word_aligned_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\word_aligned_data_r[9]_i_1_n_0 ),
- .Q(p_0_in[2]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_SYM_GEN_4BYTE" *)
-module north_channel_north_channel_SYM_GEN_4BYTE
- (gen_spa_r,
- gen_cc_r,
- CHANNEL_UP_Buffer_reg,
- \TX_CHAR_IS_K_Buffer_reg[3]_0 ,
- \TX_DATA_Buffer_reg[31]_0 ,
- BYPASS,
- \TX_DATA_Buffer_reg[31]_1 ,
- E,
- D,
- \TX_CHAR_IS_K_Buffer_reg[1]_0 ,
- gen_spa_i,
- user_clk,
- gen_cc_i,
- \fc_nb_r_reg[0]_0 ,
- \fc_nb_r_reg[1]_0 ,
- \fc_nb_r_reg[2]_0 ,
- \bypass_r_reg[0] ,
- reset_lanes_i,
- gen_v_r2,
- \DOUT_reg[0] ,
- Q,
- \gen_v_r_reg[1]_0 ,
- \gen_pad_r_reg[0]_0 ,
- GEN_SP,
- \tx_pe_data_v_r_reg[0]_0 ,
- GEN_SUF,
- GEN_ECP,
- GEN_SCP,
- \gen_r_r_reg[0]_0 ,
- \gen_k_r_reg[0]_0 ,
- \tx_pe_data_r_reg[0]_0 ,
- GEN_A);
- output gen_spa_r;
- output gen_cc_r;
- output [0:0]CHANNEL_UP_Buffer_reg;
- output [3:0]\TX_CHAR_IS_K_Buffer_reg[3]_0 ;
- output [15:0]\TX_DATA_Buffer_reg[31]_0 ;
- output BYPASS;
- output [31:0]\TX_DATA_Buffer_reg[31]_1 ;
- output [0:0]E;
- output [15:0]D;
- output \TX_CHAR_IS_K_Buffer_reg[1]_0 ;
- input gen_spa_i;
- input user_clk;
- input gen_cc_i;
- input \fc_nb_r_reg[0]_0 ;
- input \fc_nb_r_reg[1]_0 ;
- input \fc_nb_r_reg[2]_0 ;
- input \bypass_r_reg[0] ;
- input reset_lanes_i;
- input gen_v_r2;
- input [15:0]\DOUT_reg[0] ;
- input [15:0]Q;
- input [2:0]\gen_v_r_reg[1]_0 ;
- input [1:0]\gen_pad_r_reg[0]_0 ;
- input GEN_SP;
- input [1:0]\tx_pe_data_v_r_reg[0]_0 ;
- input [0:0]GEN_SUF;
- input [0:0]GEN_ECP;
- input [0:0]GEN_SCP;
- input [3:0]\gen_r_r_reg[0]_0 ;
- input [3:0]\gen_k_r_reg[0]_0 ;
- input [31:0]\tx_pe_data_r_reg[0]_0 ;
- input GEN_A;
-
- wire BYPASS;
- wire [0:0]CHANNEL_UP_Buffer_reg;
- wire [15:0]D;
- wire [15:0]\DOUT_reg[0] ;
- wire [0:0]E;
- wire GEN_A;
- wire [0:0]GEN_ECP;
- wire [0:0]GEN_SCP;
- wire GEN_SP;
- wire [0:0]GEN_SUF;
- wire [15:0]Q;
- wire \TX_CHAR_IS_K_Buffer[2]_i_2_n_0 ;
- wire \TX_CHAR_IS_K_Buffer[3]_i_1_n_0 ;
- wire TX_CHAR_IS_K_Buffer_reg0;
- wire TX_CHAR_IS_K_Buffer_reg03_out;
- wire TX_CHAR_IS_K_Buffer_reg08_out;
- wire \TX_CHAR_IS_K_Buffer_reg[1]_0 ;
- wire [3:0]\TX_CHAR_IS_K_Buffer_reg[3]_0 ;
- wire \TX_DATA_Buffer[0]_i_1_n_0 ;
- wire \TX_DATA_Buffer[0]_i_2_n_0 ;
- wire \TX_DATA_Buffer[10]_i_1_n_0 ;
- wire \TX_DATA_Buffer[10]_i_2_n_0 ;
- wire \TX_DATA_Buffer[10]_i_3_n_0 ;
- wire \TX_DATA_Buffer[11]_i_1_n_0 ;
- wire \TX_DATA_Buffer[12]_i_1_n_0 ;
- wire \TX_DATA_Buffer[12]_i_2_n_0 ;
- wire \TX_DATA_Buffer[13]_i_1_n_0 ;
- wire \TX_DATA_Buffer[13]_i_2_n_0 ;
- wire \TX_DATA_Buffer[14]_i_1_n_0 ;
- wire \TX_DATA_Buffer[14]_i_2_n_0 ;
- wire \TX_DATA_Buffer[14]_i_3_n_0 ;
- wire \TX_DATA_Buffer[14]_i_4_n_0 ;
- wire \TX_DATA_Buffer[15]_i_1_n_0 ;
- wire \TX_DATA_Buffer[15]_i_2_n_0 ;
- wire \TX_DATA_Buffer[15]_i_3_n_0 ;
- wire \TX_DATA_Buffer[16]_i_1_n_0 ;
- wire \TX_DATA_Buffer[17]_i_1_n_0 ;
- wire \TX_DATA_Buffer[18]_i_1_n_0 ;
- wire \TX_DATA_Buffer[18]_i_2_n_0 ;
- wire \TX_DATA_Buffer[18]_i_3_n_0 ;
- wire \TX_DATA_Buffer[19]_i_1_n_0 ;
- wire \TX_DATA_Buffer[1]_i_1_n_0 ;
- wire \TX_DATA_Buffer[20]_i_1_n_0 ;
- wire \TX_DATA_Buffer[20]_i_2_n_0 ;
- wire \TX_DATA_Buffer[21]_i_1_n_0 ;
- wire \TX_DATA_Buffer[21]_i_2_n_0 ;
- wire \TX_DATA_Buffer[22]_i_1_n_0 ;
- wire \TX_DATA_Buffer[22]_i_2_n_0 ;
- wire \TX_DATA_Buffer[23]_i_1_n_0 ;
- wire \TX_DATA_Buffer[23]_i_2_n_0 ;
- wire \TX_DATA_Buffer[23]_i_3_n_0 ;
- wire \TX_DATA_Buffer[23]_i_4_n_0 ;
- wire \TX_DATA_Buffer[24]_i_1_n_0 ;
- wire \TX_DATA_Buffer[25]_i_1_n_0 ;
- wire \TX_DATA_Buffer[26]_i_1_n_0 ;
- wire \TX_DATA_Buffer[27]_i_1_n_0 ;
- wire \TX_DATA_Buffer[28]_i_1_n_0 ;
- wire \TX_DATA_Buffer[29]_i_1_n_0 ;
- wire \TX_DATA_Buffer[29]_i_2_n_0 ;
- wire \TX_DATA_Buffer[2]_i_1_n_0 ;
- wire \TX_DATA_Buffer[2]_i_2_n_0 ;
- wire \TX_DATA_Buffer[30]_i_1_n_0 ;
- wire \TX_DATA_Buffer[30]_i_2_n_0 ;
- wire \TX_DATA_Buffer[31]_i_1_n_0 ;
- wire \TX_DATA_Buffer[31]_i_2_n_0 ;
- wire \TX_DATA_Buffer[31]_i_3_n_0 ;
- wire \TX_DATA_Buffer[31]_i_4_n_0 ;
- wire \TX_DATA_Buffer[3]_i_1_n_0 ;
- wire \TX_DATA_Buffer[4]_i_1_n_0 ;
- wire \TX_DATA_Buffer[4]_i_2_n_0 ;
- wire \TX_DATA_Buffer[5]_i_1_n_0 ;
- wire \TX_DATA_Buffer[5]_i_2_n_0 ;
- wire \TX_DATA_Buffer[6]_i_1_n_0 ;
- wire \TX_DATA_Buffer[6]_i_2_n_0 ;
- wire \TX_DATA_Buffer[7]_i_2_n_0 ;
- wire \TX_DATA_Buffer[7]_i_3_n_0 ;
- wire \TX_DATA_Buffer[7]_i_4_n_0 ;
- wire \TX_DATA_Buffer[8]_i_1_n_0 ;
- wire \TX_DATA_Buffer[9]_i_1_n_0 ;
- wire \TX_DATA_Buffer[9]_i_2_n_0 ;
- wire TX_DATA_Buffer_reg0;
- wire [15:0]\TX_DATA_Buffer_reg[31]_0 ;
- wire [31:0]\TX_DATA_Buffer_reg[31]_1 ;
- wire \bypass_r_reg[0] ;
- wire [7:0]data0;
- wire [7:0]data1;
- wire [0:2]fc_nb_r;
- wire \fc_nb_r_reg[0]_0 ;
- wire \fc_nb_r_reg[1]_0 ;
- wire \fc_nb_r_reg[2]_0 ;
- wire gen_a_r;
- wire gen_cc_i;
- wire gen_cc_r;
- wire \gen_ecp_r_reg_n_0_[1] ;
- wire [3:0]\gen_k_r_reg[0]_0 ;
- wire \gen_k_r_reg_n_0_[3] ;
- wire [1:0]\gen_pad_r_reg[0]_0 ;
- wire \gen_pad_r_reg_n_0_[1] ;
- wire [3:0]\gen_r_r_reg[0]_0 ;
- wire \gen_r_r_reg_n_0_[3] ;
- wire gen_sp_r;
- wire gen_spa_i;
- wire gen_spa_r;
- wire gen_v_r2;
- wire [2:0]\gen_v_r_reg[1]_0 ;
- wire \gen_v_r_reg_n_0_[3] ;
- wire p_0_in;
- wire p_0_in12_in;
- wire p_0_in14_in;
- wire p_0_in16_in;
- wire p_0_in4_in;
- wire p_0_in5_in;
- wire p_0_in6_in;
- wire p_0_in8_in;
- wire p_1_in;
- wire p_1_in11_in;
- wire p_1_in16_in;
- wire p_2_in;
- wire reset_lanes_i;
- wire [31:0]\tx_pe_data_r_reg[0]_0 ;
- wire \tx_pe_data_r_reg_n_0_[0] ;
- wire \tx_pe_data_r_reg_n_0_[1] ;
- wire \tx_pe_data_r_reg_n_0_[24] ;
- wire \tx_pe_data_r_reg_n_0_[25] ;
- wire \tx_pe_data_r_reg_n_0_[26] ;
- wire \tx_pe_data_r_reg_n_0_[27] ;
- wire \tx_pe_data_r_reg_n_0_[28] ;
- wire \tx_pe_data_r_reg_n_0_[29] ;
- wire \tx_pe_data_r_reg_n_0_[2] ;
- wire \tx_pe_data_r_reg_n_0_[30] ;
- wire \tx_pe_data_r_reg_n_0_[31] ;
- wire \tx_pe_data_r_reg_n_0_[3] ;
- wire \tx_pe_data_r_reg_n_0_[4] ;
- wire \tx_pe_data_r_reg_n_0_[5] ;
- wire \tx_pe_data_r_reg_n_0_[6] ;
- wire \tx_pe_data_r_reg_n_0_[7] ;
- wire [1:0]\tx_pe_data_v_r_reg[0]_0 ;
- wire \tx_pe_data_v_r_reg_n_0_[1] ;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair177" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [16]),
- .I2(\DOUT_reg[0] [15]),
- .O(\TX_DATA_Buffer_reg[31]_0 [0]));
- (* SOFT_HLUTNM = "soft_lutpair174" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[0]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [0]),
- .I2(Q[15]),
- .O(D[0]));
- (* SOFT_HLUTNM = "soft_lutpair175" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [26]),
- .I2(\DOUT_reg[0] [5]),
- .O(\TX_DATA_Buffer_reg[31]_0 [10]));
- (* SOFT_HLUTNM = "soft_lutpair163" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[10]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [10]),
- .I2(Q[5]),
- .O(D[10]));
- (* SOFT_HLUTNM = "soft_lutpair173" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [27]),
- .I2(\DOUT_reg[0] [4]),
- .O(\TX_DATA_Buffer_reg[31]_0 [11]));
- (* SOFT_HLUTNM = "soft_lutpair165" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[11]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [11]),
- .I2(Q[4]),
- .O(D[11]));
- (* SOFT_HLUTNM = "soft_lutpair172" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [28]),
- .I2(\DOUT_reg[0] [3]),
- .O(\TX_DATA_Buffer_reg[31]_0 [12]));
- (* SOFT_HLUTNM = "soft_lutpair164" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[12]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [12]),
- .I2(Q[3]),
- .O(D[12]));
- (* SOFT_HLUTNM = "soft_lutpair171" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [29]),
- .I2(\DOUT_reg[0] [2]),
- .O(\TX_DATA_Buffer_reg[31]_0 [13]));
- (* SOFT_HLUTNM = "soft_lutpair163" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[13]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [13]),
- .I2(Q[2]),
- .O(D[13]));
- (* SOFT_HLUTNM = "soft_lutpair170" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [30]),
- .I2(\DOUT_reg[0] [1]),
- .O(\TX_DATA_Buffer_reg[31]_0 [14]));
- (* SOFT_HLUTNM = "soft_lutpair162" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[14]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [14]),
- .I2(Q[1]),
- .O(D[14]));
- (* SOFT_HLUTNM = "soft_lutpair169" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [31]),
- .I2(\DOUT_reg[0] [0]),
- .O(\TX_DATA_Buffer_reg[31]_0 [15]));
- (* SOFT_HLUTNM = "soft_lutpair161" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[15]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [15]),
- .I2(Q[0]),
- .O(D[15]));
- (* SOFT_HLUTNM = "soft_lutpair169" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [17]),
- .I2(\DOUT_reg[0] [14]),
- .O(\TX_DATA_Buffer_reg[31]_0 [1]));
- (* SOFT_HLUTNM = "soft_lutpair174" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[1]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [1]),
- .I2(Q[14]),
- .O(D[1]));
- (* SOFT_HLUTNM = "soft_lutpair170" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [18]),
- .I2(\DOUT_reg[0] [13]),
- .O(\TX_DATA_Buffer_reg[31]_0 [2]));
- (* SOFT_HLUTNM = "soft_lutpair162" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[2]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [2]),
- .I2(Q[13]),
- .O(D[2]));
- (* SOFT_HLUTNM = "soft_lutpair171" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [19]),
- .I2(\DOUT_reg[0] [12]),
- .O(\TX_DATA_Buffer_reg[31]_0 [3]));
- (* SOFT_HLUTNM = "soft_lutpair165" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[3]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [3]),
- .I2(Q[12]),
- .O(D[3]));
- (* SOFT_HLUTNM = "soft_lutpair172" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [20]),
- .I2(\DOUT_reg[0] [11]),
- .O(\TX_DATA_Buffer_reg[31]_0 [4]));
- (* SOFT_HLUTNM = "soft_lutpair167" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[4]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [4]),
- .I2(Q[11]),
- .O(D[4]));
- (* SOFT_HLUTNM = "soft_lutpair173" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [21]),
- .I2(\DOUT_reg[0] [10]),
- .O(\TX_DATA_Buffer_reg[31]_0 [5]));
- (* SOFT_HLUTNM = "soft_lutpair167" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[5]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [5]),
- .I2(Q[10]),
- .O(D[5]));
- (* SOFT_HLUTNM = "soft_lutpair175" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [22]),
- .I2(\DOUT_reg[0] [9]),
- .O(\TX_DATA_Buffer_reg[31]_0 [6]));
- (* SOFT_HLUTNM = "soft_lutpair166" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[6]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [6]),
- .I2(Q[9]),
- .O(D[6]));
- (* SOFT_HLUTNM = "soft_lutpair176" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [23]),
- .I2(\DOUT_reg[0] [8]),
- .O(\TX_DATA_Buffer_reg[31]_0 [7]));
- (* SOFT_HLUTNM = "soft_lutpair166" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[7]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [7]),
- .I2(Q[8]),
- .O(D[7]));
- (* SOFT_HLUTNM = "soft_lutpair177" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [24]),
- .I2(\DOUT_reg[0] [7]),
- .O(\TX_DATA_Buffer_reg[31]_0 [8]));
- (* SOFT_HLUTNM = "soft_lutpair164" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[8]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [8]),
- .I2(Q[7]),
- .O(D[8]));
- (* SOFT_HLUTNM = "soft_lutpair176" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1__1
- (.I0(BYPASS),
- .I1(\TX_DATA_Buffer_reg[31]_1 [25]),
- .I2(\DOUT_reg[0] [6]),
- .O(\TX_DATA_Buffer_reg[31]_0 [9]));
- (* SOFT_HLUTNM = "soft_lutpair161" *)
- LUT3 #(
- .INIT(8'h14))
- \DOUT[9]_i_1__2
- (.I0(\TX_CHAR_IS_K_Buffer_reg[1]_0 ),
- .I1(\TX_DATA_Buffer_reg[31]_1 [9]),
- .I2(Q[6]),
- .O(D[9]));
- LUT6 #(
- .INIT(64'hFFFFFFFF0000000B))
- \TX_CHAR_IS_K_Buffer[0]_i_1
- (.I0(\gen_pad_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(\gen_v_r_reg_n_0_[3] ),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(TX_CHAR_IS_K_Buffer_reg0));
- (* SOFT_HLUTNM = "soft_lutpair153" *)
- LUT5 #(
- .INIT(32'hFFFF0001))
- \TX_CHAR_IS_K_Buffer[1]_i_1
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(p_1_in),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(gen_cc_r),
- .O(TX_CHAR_IS_K_Buffer_reg03_out));
- LUT6 #(
- .INIT(64'hFF00FF45FF00BA00))
- \TX_CHAR_IS_K_Buffer[2]_i_1
- (.I0(p_0_in5_in),
- .I1(p_0_in12_in),
- .I2(p_1_in11_in),
- .I3(gen_cc_r),
- .I4(p_2_in),
- .I5(\TX_CHAR_IS_K_Buffer[2]_i_2_n_0 ),
- .O(TX_CHAR_IS_K_Buffer_reg08_out));
- (* SOFT_HLUTNM = "soft_lutpair168" *)
- LUT3 #(
- .INIT(8'hF1))
- \TX_CHAR_IS_K_Buffer[2]_i_2
- (.I0(gen_sp_r),
- .I1(gen_spa_r),
- .I2(gen_cc_r),
- .O(\TX_CHAR_IS_K_Buffer[2]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair178" *)
- LUT2 #(
- .INIT(4'hB))
- \TX_CHAR_IS_K_Buffer[3]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .O(\TX_CHAR_IS_K_Buffer[3]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(TX_CHAR_IS_K_Buffer_reg0),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(TX_CHAR_IS_K_Buffer_reg03_out),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(TX_CHAR_IS_K_Buffer_reg08_out),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \TX_CHAR_IS_K_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_CHAR_IS_K_Buffer[3]_i_1_n_0 ),
- .Q(\TX_CHAR_IS_K_Buffer_reg[3]_0 [3]),
- .R(1'b0));
- LUT3 #(
- .INIT(8'hB8))
- \TX_DATA_Buffer[0]_i_1
- (.I0(\TX_DATA_Buffer[0]_i_2_n_0 ),
- .I1(TX_DATA_Buffer_reg0),
- .I2(\TX_DATA_Buffer_reg[31]_1 [0]),
- .O(\TX_DATA_Buffer[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h000044E4))
- \TX_DATA_Buffer[0]_i_2
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(gen_cc_r),
- .I2(\tx_pe_data_r_reg_n_0_[31] ),
- .I3(\gen_pad_r_reg_n_0_[1] ),
- .I4(\gen_ecp_r_reg_n_0_[1] ),
- .O(\TX_DATA_Buffer[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hBB88BB8BBB88B888))
- \TX_DATA_Buffer[10]_i_1
- (.I0(data0[2]),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(p_0_in4_in),
- .I3(\TX_DATA_Buffer[10]_i_2_n_0 ),
- .I4(p_0_in),
- .I5(\TX_DATA_Buffer[10]_i_3_n_0 ),
- .O(\TX_DATA_Buffer[10]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair156" *)
- LUT4 #(
- .INIT(16'hF0FB))
- \TX_DATA_Buffer[10]_i_2
- (.I0(gen_spa_r),
- .I1(p_1_in),
- .I2(gen_cc_r),
- .I3(gen_sp_r),
- .O(\TX_DATA_Buffer[10]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair178" *)
- LUT3 #(
- .INIT(8'hF4))
- \TX_DATA_Buffer[10]_i_3
- (.I0(gen_sp_r),
- .I1(gen_spa_r),
- .I2(gen_cc_r),
- .O(\TX_DATA_Buffer[10]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair159" *)
- LUT4 #(
- .INIT(16'hEAEF))
- \TX_DATA_Buffer[11]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[3]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[11]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBB88BB8BBB88B888))
- \TX_DATA_Buffer[12]_i_1
- (.I0(data0[4]),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(p_0_in4_in),
- .I3(\TX_DATA_Buffer[12]_i_2_n_0 ),
- .I4(p_0_in),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair153" *)
- LUT4 #(
- .INIT(16'hFF01))
- \TX_DATA_Buffer[12]_i_2
- (.I0(p_1_in),
- .I1(gen_sp_r),
- .I2(gen_spa_r),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[12]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hEFEA))
- \TX_DATA_Buffer[13]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[5]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(\TX_DATA_Buffer[13]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[13]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0000FFFFFEFF))
- \TX_DATA_Buffer[13]_i_2
- (.I0(p_0_in4_in),
- .I1(p_1_in),
- .I2(gen_spa_r),
- .I3(p_0_in),
- .I4(gen_cc_r),
- .I5(gen_sp_r),
- .O(\TX_DATA_Buffer[13]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \TX_DATA_Buffer[14]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .O(\TX_DATA_Buffer[14]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBB88BB8BBB88B888))
- \TX_DATA_Buffer[14]_i_2
- (.I0(data0[6]),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(p_0_in4_in),
- .I3(\TX_DATA_Buffer[14]_i_3_n_0 ),
- .I4(p_0_in),
- .I5(\TX_DATA_Buffer[14]_i_4_n_0 ),
- .O(\TX_DATA_Buffer[14]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair156" *)
- LUT4 #(
- .INIT(16'hFFF4))
- \TX_DATA_Buffer[14]_i_3
- (.I0(gen_spa_r),
- .I1(p_1_in),
- .I2(gen_sp_r),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[14]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair168" *)
- LUT3 #(
- .INIT(8'hFD))
- \TX_DATA_Buffer[14]_i_4
- (.I0(gen_spa_r),
- .I1(gen_sp_r),
- .I2(gen_cc_r),
- .O(\TX_DATA_Buffer[14]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[15]_i_1
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(p_0_in),
- .I2(\TX_DATA_Buffer[7]_i_3_n_0 ),
- .I3(p_1_in),
- .I4(p_0_in4_in),
- .I5(\gen_ecp_r_reg_n_0_[1] ),
- .O(\TX_DATA_Buffer[15]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hEFEA))
- \TX_DATA_Buffer[15]_i_2
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[7]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(\TX_DATA_Buffer[15]_i_3_n_0 ),
- .O(\TX_DATA_Buffer[15]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000EF))
- \TX_DATA_Buffer[15]_i_3
- (.I0(p_0_in4_in),
- .I1(p_1_in),
- .I2(p_0_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[15]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h000044E4))
- \TX_DATA_Buffer[16]_i_1
- (.I0(p_1_in11_in),
- .I1(gen_cc_r),
- .I2(data1[0]),
- .I3(p_0_in12_in),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[16]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000000EFE0E0E))
- \TX_DATA_Buffer[17]_i_1
- (.I0(gen_cc_r),
- .I1(gen_sp_r),
- .I2(p_1_in11_in),
- .I3(p_0_in12_in),
- .I4(data1[1]),
- .I5(p_0_in5_in),
- .O(\TX_DATA_Buffer[17]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0001FFFE0000))
- \TX_DATA_Buffer[18]_i_1
- (.I0(p_0_in5_in),
- .I1(\TX_DATA_Buffer[23]_i_3_n_0 ),
- .I2(p_1_in11_in),
- .I3(p_1_in16_in),
- .I4(\TX_DATA_Buffer[18]_i_2_n_0 ),
- .I5(\TX_DATA_Buffer_reg[31]_1 [18]),
- .O(\TX_DATA_Buffer[18]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000054555400))
- \TX_DATA_Buffer[18]_i_2
- (.I0(p_0_in5_in),
- .I1(data1[2]),
- .I2(p_0_in12_in),
- .I3(p_1_in11_in),
- .I4(\TX_DATA_Buffer[18]_i_3_n_0 ),
- .I5(p_1_in16_in),
- .O(\TX_DATA_Buffer[18]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00FF0032))
- \TX_DATA_Buffer[18]_i_3
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(p_0_in6_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[18]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h0000DDD1))
- \TX_DATA_Buffer[19]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(p_0_in12_in),
- .I3(data1[3]),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[19]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAEFFAEFFAEFFAEAA))
- \TX_DATA_Buffer[1]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[30] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(gen_sp_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[1]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFEEE2))
- \TX_DATA_Buffer[20]_i_1
- (.I0(\TX_DATA_Buffer[20]_i_2_n_0 ),
- .I1(p_1_in11_in),
- .I2(p_0_in12_in),
- .I3(data1[4]),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[20]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00030002))
- \TX_DATA_Buffer[20]_i_2
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(p_0_in6_in),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[20]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h88B8BBBB88B88888))
- \TX_DATA_Buffer[21]_i_1
- (.I0(fc_nb_r[2]),
- .I1(p_0_in5_in),
- .I2(data1[5]),
- .I3(p_0_in12_in),
- .I4(p_1_in11_in),
- .I5(\TX_DATA_Buffer[21]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[21]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0000FFFFFEFF))
- \TX_DATA_Buffer[21]_i_2
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(gen_spa_r),
- .I3(p_0_in6_in),
- .I4(gen_cc_r),
- .I5(gen_sp_r),
- .O(\TX_DATA_Buffer[21]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h88B8BBBB88B88888))
- \TX_DATA_Buffer[22]_i_1
- (.I0(fc_nb_r[1]),
- .I1(p_0_in5_in),
- .I2(data1[6]),
- .I3(p_0_in12_in),
- .I4(p_1_in11_in),
- .I5(\TX_DATA_Buffer[22]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[22]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF00CD))
- \TX_DATA_Buffer[22]_i_2
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(p_0_in6_in),
- .I3(gen_spa_r),
- .I4(gen_sp_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[22]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \TX_DATA_Buffer[23]_i_1
- (.I0(p_0_in5_in),
- .I1(\TX_DATA_Buffer[23]_i_3_n_0 ),
- .I2(p_1_in11_in),
- .I3(p_1_in16_in),
- .O(\TX_DATA_Buffer[23]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBBB8BBBBBBB88888))
- \TX_DATA_Buffer[23]_i_2
- (.I0(fc_nb_r[0]),
- .I1(p_0_in5_in),
- .I2(data1[7]),
- .I3(p_0_in12_in),
- .I4(p_1_in11_in),
- .I5(\TX_DATA_Buffer[23]_i_4_n_0 ),
- .O(\TX_DATA_Buffer[23]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[23]_i_3
- (.I0(p_0_in6_in),
- .I1(gen_cc_r),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(p_2_in),
- .I5(p_0_in8_in),
- .O(\TX_DATA_Buffer[23]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000EF))
- \TX_DATA_Buffer[23]_i_4
- (.I0(p_0_in8_in),
- .I1(p_2_in),
- .I2(p_0_in6_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[23]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair158" *)
- LUT4 #(
- .INIT(16'h00E2))
- \TX_DATA_Buffer[24]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[7] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[24]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair158" *)
- LUT4 #(
- .INIT(16'h00E2))
- \TX_DATA_Buffer[25]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[6] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[25]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair157" *)
- LUT4 #(
- .INIT(16'hFFE2))
- \TX_DATA_Buffer[26]_i_1
- (.I0(\TX_DATA_Buffer[31]_i_3_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[5] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[26]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair160" *)
- LUT4 #(
- .INIT(16'hFFD1))
- \TX_DATA_Buffer[27]_i_1
- (.I0(gen_cc_r),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[4] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[27]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair157" *)
- LUT4 #(
- .INIT(16'hFFE2))
- \TX_DATA_Buffer[28]_i_1
- (.I0(\TX_DATA_Buffer[31]_i_3_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[3] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[28]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h0000FD0D))
- \TX_DATA_Buffer[29]_i_1
- (.I0(p_0_in14_in),
- .I1(\TX_DATA_Buffer[29]_i_2_n_0 ),
- .I2(p_1_in11_in),
- .I3(\tx_pe_data_r_reg_n_0_[2] ),
- .I4(p_0_in5_in),
- .O(\TX_DATA_Buffer[29]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair155" *)
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \TX_DATA_Buffer[29]_i_2
- (.I0(gen_a_r),
- .I1(gen_spa_r),
- .I2(gen_sp_r),
- .I3(gen_cc_r),
- .I4(p_0_in16_in),
- .O(\TX_DATA_Buffer[29]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFEFFFEAA))
- \TX_DATA_Buffer[2]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[29] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[2]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00FF0032))
- \TX_DATA_Buffer[2]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(\gen_r_r_reg_n_0_[3] ),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[2]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h00E2))
- \TX_DATA_Buffer[30]_i_1
- (.I0(\TX_DATA_Buffer[30]_i_2_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[1] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[30]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000CD))
- \TX_DATA_Buffer[30]_i_2
- (.I0(p_0_in14_in),
- .I1(gen_a_r),
- .I2(p_0_in16_in),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[30]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \TX_DATA_Buffer[31]_i_1
- (.I0(p_0_in5_in),
- .I1(\TX_DATA_Buffer[31]_i_3_n_0 ),
- .I2(p_1_in11_in),
- .I3(p_1_in16_in),
- .O(\TX_DATA_Buffer[31]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFE2))
- \TX_DATA_Buffer[31]_i_2
- (.I0(\TX_DATA_Buffer[31]_i_4_n_0 ),
- .I1(p_1_in11_in),
- .I2(\tx_pe_data_r_reg_n_0_[0] ),
- .I3(p_0_in5_in),
- .O(\TX_DATA_Buffer[31]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[31]_i_3
- (.I0(p_0_in16_in),
- .I1(gen_cc_r),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(gen_a_r),
- .I5(p_0_in14_in),
- .O(\TX_DATA_Buffer[31]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFF0FFFFFFFB))
- \TX_DATA_Buffer[31]_i_4
- (.I0(p_0_in16_in),
- .I1(p_0_in14_in),
- .I2(gen_cc_r),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_a_r),
- .O(\TX_DATA_Buffer[31]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFEAAFEFF))
- \TX_DATA_Buffer[3]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[28] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(gen_cc_r),
- .O(\TX_DATA_Buffer[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFEFFFEAA))
- \TX_DATA_Buffer[4]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[27] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[4]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00030002))
- \TX_DATA_Buffer[4]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(gen_sp_r),
- .I3(gen_spa_r),
- .I4(\gen_r_r_reg_n_0_[3] ),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[4]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hAEFFAEAA))
- \TX_DATA_Buffer[5]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[26] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[5]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[5]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFF0000FFFFFEFF))
- \TX_DATA_Buffer[5]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(gen_spa_r),
- .I3(\gen_r_r_reg_n_0_[3] ),
- .I4(gen_cc_r),
- .I5(gen_sp_r),
- .O(\TX_DATA_Buffer[5]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hAEFFAEAA))
- \TX_DATA_Buffer[6]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[25] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[6]_i_2_n_0 ),
- .O(\TX_DATA_Buffer[6]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF00CD))
- \TX_DATA_Buffer[6]_i_2
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(\gen_r_r_reg_n_0_[3] ),
- .I3(gen_spa_r),
- .I4(gen_sp_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \TX_DATA_Buffer[7]_i_1
- (.I0(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I1(\gen_r_r_reg_n_0_[3] ),
- .I2(\TX_DATA_Buffer[7]_i_3_n_0 ),
- .I3(\gen_v_r_reg_n_0_[3] ),
- .I4(\gen_k_r_reg_n_0_[3] ),
- .I5(\gen_ecp_r_reg_n_0_[1] ),
- .O(TX_DATA_Buffer_reg0));
- LUT5 #(
- .INIT(32'hFEFFFEAA))
- \TX_DATA_Buffer[7]_i_2
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(\tx_pe_data_r_reg_n_0_[24] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .I3(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[7]_i_4_n_0 ),
- .O(\TX_DATA_Buffer[7]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair155" *)
- LUT3 #(
- .INIT(8'hFE))
- \TX_DATA_Buffer[7]_i_3
- (.I0(gen_spa_r),
- .I1(gen_sp_r),
- .I2(gen_cc_r),
- .O(\TX_DATA_Buffer[7]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF000000EF))
- \TX_DATA_Buffer[7]_i_4
- (.I0(\gen_k_r_reg_n_0_[3] ),
- .I1(\gen_v_r_reg_n_0_[3] ),
- .I2(\gen_r_r_reg_n_0_[3] ),
- .I3(gen_sp_r),
- .I4(gen_spa_r),
- .I5(gen_cc_r),
- .O(\TX_DATA_Buffer[7]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair159" *)
- LUT4 #(
- .INIT(16'hEFEA))
- \TX_DATA_Buffer[8]_i_1
- (.I0(\gen_ecp_r_reg_n_0_[1] ),
- .I1(data0[0]),
- .I2(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I3(gen_cc_r),
- .O(\TX_DATA_Buffer[8]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00E2FFFF00E20000))
- \TX_DATA_Buffer[9]_i_1
- (.I0(\TX_DATA_Buffer[9]_i_2_n_0 ),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(data0[1]),
- .I3(\gen_ecp_r_reg_n_0_[1] ),
- .I4(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .I5(\TX_DATA_Buffer_reg[31]_1 [9]),
- .O(\TX_DATA_Buffer[9]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair160" *)
- LUT2 #(
- .INIT(4'hE))
- \TX_DATA_Buffer[9]_i_2
- (.I0(gen_sp_r),
- .I1(gen_cc_r),
- .O(\TX_DATA_Buffer[9]_i_2_n_0 ));
- FDRE \TX_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_DATA_Buffer[0]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [0]),
- .R(1'b0));
- FDSE \TX_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[10]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [10]),
- .S(\TX_DATA_Buffer[14]_i_1_n_0 ));
- FDSE \TX_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[11]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [11]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[12]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [12]),
- .S(\TX_DATA_Buffer[14]_i_1_n_0 ));
- FDSE \TX_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[13]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [13]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[14]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [14]),
- .S(\TX_DATA_Buffer[14]_i_1_n_0 ));
- FDSE \TX_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[15]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [15]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[16]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [16]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[17]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [17]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_DATA_Buffer[18]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [18]),
- .R(1'b0));
- FDSE \TX_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[19]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [19]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[1]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [1]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[20]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [20]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[21]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [21]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[22]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [22]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[23]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[23]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [23]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[24]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [24]),
- .R(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[25]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [25]),
- .R(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[26]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [26]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[27]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [27]),
- .S(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[28]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [28]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[29]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [29]),
- .R(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[2]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [2]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[30]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [30]),
- .S(p_1_in16_in));
- FDRE \TX_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[31]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[31]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [31]),
- .R(p_1_in16_in));
- FDSE \TX_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[3]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [3]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[4]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [4]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[5]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [5]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[6]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [6]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(TX_DATA_Buffer_reg0),
- .D(\TX_DATA_Buffer[7]_i_2_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [7]),
- .S(1'b0));
- FDSE \TX_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(\TX_DATA_Buffer[15]_i_1_n_0 ),
- .D(\TX_DATA_Buffer[8]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [8]),
- .S(1'b0));
- FDRE \TX_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\TX_DATA_Buffer[9]_i_1_n_0 ),
- .Q(\TX_DATA_Buffer_reg[31]_1 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair154" *)
- LUT5 #(
- .INIT(32'hFFFEFFFF))
- \bypass_r[0]_i_1__0
- (.I0(\TX_CHAR_IS_K_Buffer_reg[3]_0 [1]),
- .I1(\TX_CHAR_IS_K_Buffer_reg[3]_0 [0]),
- .I2(gen_v_r2),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(\TX_CHAR_IS_K_Buffer_reg[1]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair152" *)
- LUT5 #(
- .INIT(32'hFFFEFFFF))
- \bypass_r[1]_i_1__0
- (.I0(\TX_CHAR_IS_K_Buffer_reg[3]_0 [3]),
- .I1(\TX_CHAR_IS_K_Buffer_reg[3]_0 [2]),
- .I2(gen_v_r2),
- .I3(reset_lanes_i),
- .I4(\bypass_r_reg[0] ),
- .O(BYPASS));
- FDRE \fc_nb_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\fc_nb_r_reg[0]_0 ),
- .Q(fc_nb_r[0]),
- .R(1'b0));
- FDRE \fc_nb_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\fc_nb_r_reg[1]_0 ),
- .Q(fc_nb_r[1]),
- .R(1'b0));
- FDRE \fc_nb_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\fc_nb_r_reg[2]_0 ),
- .Q(fc_nb_r[2]),
- .R(1'b0));
- FDRE gen_a_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_A),
- .Q(gen_a_r),
- .R(1'b0));
- FDRE gen_cc_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_cc_i),
- .Q(gen_cc_r),
- .R(1'b0));
- FDRE \gen_ecp_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_ECP),
- .Q(\gen_ecp_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \gen_k_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [3]),
- .Q(p_0_in16_in),
- .R(1'b0));
- FDRE \gen_k_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [2]),
- .Q(p_0_in8_in),
- .R(1'b0));
- FDRE \gen_k_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [1]),
- .Q(p_0_in4_in),
- .R(1'b0));
- FDRE \gen_k_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_k_r_reg[0]_0 [0]),
- .Q(\gen_k_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \gen_pad_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_pad_r_reg[0]_0 [1]),
- .Q(p_0_in12_in),
- .R(1'b0));
- FDRE \gen_pad_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_pad_r_reg[0]_0 [0]),
- .Q(\gen_pad_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \gen_r_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [3]),
- .Q(p_0_in14_in),
- .R(1'b0));
- FDRE \gen_r_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [2]),
- .Q(p_0_in6_in),
- .R(1'b0));
- FDRE \gen_r_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [1]),
- .Q(p_0_in),
- .R(1'b0));
- FDRE \gen_r_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_r_r_reg[0]_0 [0]),
- .Q(\gen_r_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \gen_scp_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SCP),
- .Q(p_1_in16_in),
- .R(1'b0));
- FDRE gen_sp_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SP),
- .Q(gen_sp_r),
- .R(1'b0));
- FDRE gen_spa_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(gen_spa_i),
- .Q(gen_spa_r),
- .R(1'b0));
- FDRE \gen_suf_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SUF),
- .Q(p_0_in5_in),
- .R(1'b0));
- FDRE \gen_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_v_r_reg[1]_0 [2]),
- .Q(p_2_in),
- .R(1'b0));
- FDRE \gen_v_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_v_r_reg[1]_0 [1]),
- .Q(p_1_in),
- .R(1'b0));
- FDRE \gen_v_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\gen_v_r_reg[1]_0 [0]),
- .Q(\gen_v_r_reg_n_0_[3] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair152" *)
- LUT5 #(
- .INIT(32'h00000002))
- \lfsr[15]_i_1__1
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(gen_v_r2),
- .I3(\TX_CHAR_IS_K_Buffer_reg[3]_0 [2]),
- .I4(\TX_CHAR_IS_K_Buffer_reg[3]_0 [3]),
- .O(CHANNEL_UP_Buffer_reg));
- (* SOFT_HLUTNM = "soft_lutpair154" *)
- LUT5 #(
- .INIT(32'h00000002))
- \lfsr[15]_i_2__0
- (.I0(\bypass_r_reg[0] ),
- .I1(reset_lanes_i),
- .I2(gen_v_r2),
- .I3(\TX_CHAR_IS_K_Buffer_reg[3]_0 [0]),
- .I4(\TX_CHAR_IS_K_Buffer_reg[3]_0 [1]),
- .O(E));
- FDRE \tx_pe_data_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [31]),
- .Q(\tx_pe_data_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [21]),
- .Q(data1[5]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [20]),
- .Q(data1[4]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [19]),
- .Q(data1[3]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [18]),
- .Q(data1[2]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [17]),
- .Q(data1[1]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [16]),
- .Q(data1[0]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [15]),
- .Q(data0[7]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [14]),
- .Q(data0[6]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [13]),
- .Q(data0[5]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [12]),
- .Q(data0[4]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [30]),
- .Q(\tx_pe_data_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [11]),
- .Q(data0[3]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [10]),
- .Q(data0[2]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [9]),
- .Q(data0[1]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [8]),
- .Q(data0[0]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [7]),
- .Q(\tx_pe_data_r_reg_n_0_[24] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [6]),
- .Q(\tx_pe_data_r_reg_n_0_[25] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [5]),
- .Q(\tx_pe_data_r_reg_n_0_[26] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [4]),
- .Q(\tx_pe_data_r_reg_n_0_[27] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [3]),
- .Q(\tx_pe_data_r_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [2]),
- .Q(\tx_pe_data_r_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [29]),
- .Q(\tx_pe_data_r_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [1]),
- .Q(\tx_pe_data_r_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [0]),
- .Q(\tx_pe_data_r_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [28]),
- .Q(\tx_pe_data_r_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [27]),
- .Q(\tx_pe_data_r_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [26]),
- .Q(\tx_pe_data_r_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [25]),
- .Q(\tx_pe_data_r_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [24]),
- .Q(\tx_pe_data_r_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [23]),
- .Q(data1[7]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_r_reg[0]_0 [22]),
- .Q(data1[6]),
- .R(1'b0));
- FDRE \tx_pe_data_v_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_v_r_reg[0]_0 [1]),
- .Q(p_1_in11_in),
- .R(1'b0));
- FDRE \tx_pe_data_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\tx_pe_data_v_r_reg[0]_0 [0]),
- .Q(\tx_pe_data_v_r_reg_n_0_[1] ),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_TX_LL" *)
-module north_channel_north_channel_TX_LL
- (gen_cc_i,
- tx_dst_rdy,
- ufc_header_r_reg,
- GEN_SCP,
- GEN_ECP,
- GEN_SUF,
- \s_axi_ufc_tx_tdata[0] ,
- \s_axi_ufc_tx_tdata[1] ,
- \s_axi_ufc_tx_tdata[2] ,
- S_AXI_TX_TREADY,
- \ufc_message_count_r_reg[2] ,
- Q,
- \GEN_PAD_Buffer_reg[0] ,
- \TX_PE_DATA_Buffer_reg[0] ,
- user_clk,
- in_frame_r_reg,
- DO_CC_I,
- next_ufc_idle_c,
- S_AXI_UFC_TX_MS,
- S_AXI_TX_TLAST,
- S_AXI_TX_TKEEP,
- \tx_pe_data_v_r_reg[1] ,
- S_AXI_TX_TVALID,
- WARN_CC,
- S_AXI_UFC_TX_REQ,
- S_AXI_TX_TDATA);
- output gen_cc_i;
- output tx_dst_rdy;
- output ufc_header_r_reg;
- output [0:0]GEN_SCP;
- output [0:0]GEN_ECP;
- output [0:0]GEN_SUF;
- output \s_axi_ufc_tx_tdata[0] ;
- output \s_axi_ufc_tx_tdata[1] ;
- output \s_axi_ufc_tx_tdata[2] ;
- output S_AXI_TX_TREADY;
- output \ufc_message_count_r_reg[2] ;
- output [1:0]Q;
- output [1:0]\GEN_PAD_Buffer_reg[0] ;
- output [31:0]\TX_PE_DATA_Buffer_reg[0] ;
- input user_clk;
- input in_frame_r_reg;
- input DO_CC_I;
- input next_ufc_idle_c;
- input [0:2]S_AXI_UFC_TX_MS;
- input S_AXI_TX_TLAST;
- input [0:3]S_AXI_TX_TKEEP;
- input \tx_pe_data_v_r_reg[1] ;
- input S_AXI_TX_TVALID;
- input WARN_CC;
- input S_AXI_UFC_TX_REQ;
- input [0:31]S_AXI_TX_TDATA;
-
- wire D;
- wire DO_CC_I;
- wire [0:0]GEN_ECP;
- wire [1:0]\GEN_PAD_Buffer_reg[0] ;
- wire [0:0]GEN_SCP;
- wire [0:0]GEN_SUF;
- wire [1:0]Q;
- wire [0:31]S_AXI_TX_TDATA;
- wire [0:3]S_AXI_TX_TKEEP;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TREADY;
- wire S_AXI_TX_TVALID;
- wire [0:2]S_AXI_UFC_TX_MS;
- wire S_AXI_UFC_TX_REQ;
- wire [31:0]\TX_PE_DATA_Buffer_reg[0] ;
- wire WARN_CC;
- wire create_gap_for_scp_c043_out;
- wire gen_cc_i;
- wire in_frame_r_reg;
- wire next_ufc_idle_c;
- wire pdu_ok_c;
- wire \s_axi_ufc_tx_tdata[0] ;
- wire \s_axi_ufc_tx_tdata[1] ;
- wire \s_axi_ufc_tx_tdata[2] ;
- wire tx_dst_rdy;
- wire tx_ll_control_i_n_15;
- wire tx_ll_datapath_i_n_0;
- wire \tx_pe_data_v_r_reg[1] ;
- wire ufc_header_r_reg;
- wire \ufc_message_count_r_reg[2] ;
- wire [1:1]ufc_message_i;
- wire user_clk;
-
- north_channel_north_channel_TX_LL_CONTROL tx_ll_control_i
- (.D(create_gap_for_scp_c043_out),
- .DO_CC_I(DO_CC_I),
- .D_0(D),
- .GEN_ECP(GEN_ECP),
- .GEN_SCP(GEN_SCP),
- .GEN_SUF(GEN_SUF),
- .GEN_SUF_Buffer_reg_0(in_frame_r_reg),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TREADY(S_AXI_TX_TREADY),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .S_AXI_UFC_TX_MS(S_AXI_UFC_TX_MS),
- .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
- .TX_DST_RDY_N_Buffer_reg_0(tx_dst_rdy),
- .WARN_CC(WARN_CC),
- .gen_cc_i(gen_cc_i),
- .in_frame_r_reg(tx_ll_datapath_i_n_0),
- .new_pkt_r_reg(tx_ll_control_i_n_15),
- .next_ufc_idle_c(next_ufc_idle_c),
- .pdu_ok_c(pdu_ok_c),
- .\s_axi_ufc_tx_tdata[0] (\s_axi_ufc_tx_tdata[0] ),
- .\s_axi_ufc_tx_tdata[1] (\s_axi_ufc_tx_tdata[1] ),
- .\s_axi_ufc_tx_tdata[2] (\s_axi_ufc_tx_tdata[2] ),
- .sof_to_eof_1_r_reg_0(\tx_pe_data_v_r_reg[1] ),
- .ufc_header_r_reg_0(ufc_header_r_reg),
- .\ufc_message_count_r_reg[2]_0 (\ufc_message_count_r_reg[2] ),
- .ufc_message_i(ufc_message_i),
- .user_clk(user_clk));
- north_channel_north_channel_TX_LL_DATAPATH tx_ll_datapath_i
- (.D(create_gap_for_scp_c043_out),
- .D_0(D),
- .E(pdu_ok_c),
- .\GEN_PAD_Buffer_reg[0]_0 (\GEN_PAD_Buffer_reg[0] ),
- .Q(Q),
- .S_AXI_TX_TDATA(S_AXI_TX_TDATA),
- .S_AXI_TX_TKEEP(S_AXI_TX_TKEEP),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .\TX_PE_DATA_Buffer_reg[0]_0 (\TX_PE_DATA_Buffer_reg[0] ),
- .in_frame_r_reg_0(tx_ll_datapath_i_n_0),
- .in_frame_r_reg_1(in_frame_r_reg),
- .in_frame_r_reg_2(tx_ll_control_i_n_15),
- .tx_dst_rdy(tx_dst_rdy),
- .\tx_pe_data_v_r_reg[1]_0 (\tx_pe_data_v_r_reg[1] ),
- .ufc_message_i(ufc_message_i),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_TX_LL_CONTROL" *)
-module north_channel_north_channel_TX_LL_CONTROL
- (gen_cc_i,
- D_0,
- TX_DST_RDY_N_Buffer_reg_0,
- ufc_header_r_reg_0,
- pdu_ok_c,
- GEN_SCP,
- GEN_ECP,
- GEN_SUF,
- \s_axi_ufc_tx_tdata[0] ,
- \s_axi_ufc_tx_tdata[1] ,
- \s_axi_ufc_tx_tdata[2] ,
- S_AXI_TX_TREADY,
- \ufc_message_count_r_reg[2]_0 ,
- D,
- ufc_message_i,
- new_pkt_r_reg,
- user_clk,
- GEN_SUF_Buffer_reg_0,
- DO_CC_I,
- next_ufc_idle_c,
- S_AXI_UFC_TX_MS,
- S_AXI_TX_TLAST,
- S_AXI_TX_TVALID,
- sof_to_eof_1_r_reg_0,
- WARN_CC,
- S_AXI_UFC_TX_REQ,
- in_frame_r_reg);
- output gen_cc_i;
- output D_0;
- output TX_DST_RDY_N_Buffer_reg_0;
- output ufc_header_r_reg_0;
- output pdu_ok_c;
- output [0:0]GEN_SCP;
- output [0:0]GEN_ECP;
- output [0:0]GEN_SUF;
- output \s_axi_ufc_tx_tdata[0] ;
- output \s_axi_ufc_tx_tdata[1] ;
- output \s_axi_ufc_tx_tdata[2] ;
- output S_AXI_TX_TREADY;
- output \ufc_message_count_r_reg[2]_0 ;
- output [0:0]D;
- output [0:0]ufc_message_i;
- output new_pkt_r_reg;
- input user_clk;
- input GEN_SUF_Buffer_reg_0;
- input DO_CC_I;
- input next_ufc_idle_c;
- input [0:2]S_AXI_UFC_TX_MS;
- input S_AXI_TX_TLAST;
- input S_AXI_TX_TVALID;
- input sof_to_eof_1_r_reg_0;
- input WARN_CC;
- input S_AXI_UFC_TX_REQ;
- input in_frame_r_reg;
-
- wire [0:0]D;
- wire DO_CC_I;
- wire D_0;
- wire [0:0]GEN_ECP;
- wire GEN_ECP_Buffer0;
- wire [0:0]GEN_SCP;
- wire GEN_SCP_Buffer0;
- wire [0:0]GEN_SUF;
- wire GEN_SUF_Buffer_reg_0;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TREADY;
- wire S_AXI_TX_TVALID;
- wire [0:2]S_AXI_UFC_TX_MS;
- wire S_AXI_UFC_TX_REQ;
- wire TX_DST_RDY_N_Buffer_i_2_n_0;
- wire TX_DST_RDY_N_Buffer_i_3_n_0;
- wire TX_DST_RDY_N_Buffer_i_4_n_0;
- wire TX_DST_RDY_N_Buffer_i_6_n_0;
- wire TX_DST_RDY_N_Buffer_reg_0;
- wire WARN_CC;
- wire data_r;
- wire data_to_eof_1_r;
- wire data_to_eof_2_r;
- wire gen_cc_i;
- wire idle_r;
- wire in_frame_r_reg;
- wire new_pkt_r_reg;
- wire next_data_c;
- wire next_data_to_eof_1_c;
- wire next_idle_c;
- wire next_sof_to_data_c;
- wire next_sof_to_eof_1_c;
- wire next_ufc_header_c;
- wire next_ufc_idle_c;
- wire next_ufc_message1_c;
- wire next_ufc_message2_c;
- wire next_ufc_message3_c;
- wire next_ufc_message4_c;
- wire next_ufc_message5_c;
- wire next_ufc_message6_c;
- wire next_ufc_message7_c;
- wire next_ufc_message8_c;
- wire pdu_ok_c;
- wire \s_axi_ufc_tx_tdata[0] ;
- wire \s_axi_ufc_tx_tdata[1] ;
- wire \s_axi_ufc_tx_tdata[2] ;
- wire sof_to_data_r;
- wire sof_to_data_r_i_2_n_0;
- wire sof_to_eof_1_r;
- wire sof_to_eof_1_r_reg_0;
- wire sof_to_eof_2_r;
- wire suf_delay_1_r;
- wire suf_delay_2_r;
- wire tx_dst_rdy_n_c;
- wire ufc_header_r_i_3_n_0;
- wire ufc_header_r_i_4_n_0;
- wire ufc_header_r_reg_0;
- wire ufc_idle_r;
- wire ufc_message1_r;
- wire ufc_message2_r;
- wire ufc_message3_r;
- wire ufc_message4_r;
- wire ufc_message5_r;
- wire ufc_message6_r;
- wire ufc_message7_r;
- wire ufc_message8_r;
- wire [0:2]ufc_message_count_r;
- wire \ufc_message_count_r[0]_i_1_n_0 ;
- wire \ufc_message_count_r[1]_i_1_n_0 ;
- wire \ufc_message_count_r[2]_i_1_n_0 ;
- wire \ufc_message_count_r_reg[2]_0 ;
- wire [0:0]ufc_message_i;
- wire user_clk;
-
- (* srl_bus_name = "U0/\north_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[0]_srl3 " *)
- SRL16E \FC_NB_Buffer_reg[0]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(S_AXI_UFC_TX_MS[0]),
- .Q(\s_axi_ufc_tx_tdata[0] ));
- (* srl_bus_name = "U0/\north_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[1]_srl3 " *)
- SRL16E \FC_NB_Buffer_reg[1]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(S_AXI_UFC_TX_MS[1]),
- .Q(\s_axi_ufc_tx_tdata[1] ));
- (* srl_bus_name = "U0/\north_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[2]_srl3 " *)
- SRL16E \FC_NB_Buffer_reg[2]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(S_AXI_UFC_TX_MS[2]),
- .Q(\s_axi_ufc_tx_tdata[2] ));
- (* SOFT_HLUTNM = "soft_lutpair274" *)
- LUT3 #(
- .INIT(8'h0E))
- GEN_ECP_Buffer_i_1
- (.I0(data_to_eof_2_r),
- .I1(sof_to_eof_2_r),
- .I2(D_0),
- .O(GEN_ECP_Buffer0));
- FDRE GEN_ECP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_ECP_Buffer0),
- .Q(GEN_ECP),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair274" *)
- LUT3 #(
- .INIT(8'h32))
- GEN_SCP_Buffer_i_1
- (.I0(sof_to_data_r),
- .I1(D_0),
- .I2(sof_to_eof_1_r),
- .O(GEN_SCP_Buffer0));
- FDRE GEN_SCP_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GEN_SCP_Buffer0),
- .Q(GEN_SCP),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE GEN_SUF_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(suf_delay_2_r),
- .Q(GEN_SUF),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair268" *)
- LUT1 #(
- .INIT(2'h1))
- S_AXI_TX_TREADY_INST_0
- (.I0(TX_DST_RDY_N_Buffer_reg_0),
- .O(S_AXI_TX_TREADY));
- LUT6 #(
- .INIT(64'hFFFFFFFFABAAFFFF))
- TX_DST_RDY_N_Buffer_i_1
- (.I0(TX_DST_RDY_N_Buffer_i_2_n_0),
- .I1(D_0),
- .I2(TX_DST_RDY_N_Buffer_i_3_n_0),
- .I3(TX_DST_RDY_N_Buffer_i_4_n_0),
- .I4(\ufc_message_count_r_reg[2]_0 ),
- .I5(DO_CC_I),
- .O(tx_dst_rdy_n_c));
- LUT6 #(
- .INIT(64'hFFFFFFFFF4F4F444))
- TX_DST_RDY_N_Buffer_i_2
- (.I0(WARN_CC),
- .I1(S_AXI_UFC_TX_REQ),
- .I2(D_0),
- .I3(sof_to_eof_1_r),
- .I4(data_to_eof_1_r),
- .I5(TX_DST_RDY_N_Buffer_i_6_n_0),
- .O(TX_DST_RDY_N_Buffer_i_2_n_0));
- (* SOFT_HLUTNM = "soft_lutpair267" *)
- LUT3 #(
- .INIT(8'hDF))
- TX_DST_RDY_N_Buffer_i_3
- (.I0(S_AXI_TX_TVALID),
- .I1(TX_DST_RDY_N_Buffer_reg_0),
- .I2(S_AXI_TX_TLAST),
- .O(TX_DST_RDY_N_Buffer_i_3_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF5554))
- TX_DST_RDY_N_Buffer_i_4
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(data_to_eof_2_r),
- .I2(sof_to_eof_2_r),
- .I3(idle_r),
- .I4(sof_to_data_r),
- .I5(data_r),
- .O(TX_DST_RDY_N_Buffer_i_4_n_0));
- (* SOFT_HLUTNM = "soft_lutpair275" *)
- LUT3 #(
- .INIT(8'hAE))
- TX_DST_RDY_N_Buffer_i_5
- (.I0(ufc_header_r_i_3_n_0),
- .I1(ufc_message_count_r[2]),
- .I2(ufc_header_r_i_4_n_0),
- .O(\ufc_message_count_r_reg[2]_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- TX_DST_RDY_N_Buffer_i_6
- (.I0(data_r),
- .I1(sof_to_data_r),
- .I2(ufc_idle_r),
- .I3(ufc_header_r_reg_0),
- .I4(sof_to_eof_1_r),
- .I5(data_to_eof_1_r),
- .O(TX_DST_RDY_N_Buffer_i_6_n_0));
- FDSE TX_DST_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_dst_rdy_n_c),
- .Q(TX_DST_RDY_N_Buffer_reg_0),
- .S(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair265" *)
- LUT5 #(
- .INIT(32'hEE0EEEEE))
- data_r_i_1
- (.I0(sof_to_data_r),
- .I1(data_r),
- .I2(S_AXI_TX_TLAST),
- .I3(TX_DST_RDY_N_Buffer_reg_0),
- .I4(S_AXI_TX_TVALID),
- .O(next_data_c));
- FDRE data_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_data_c),
- .Q(data_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair265" *)
- LUT5 #(
- .INIT(32'h00E00000))
- data_to_eof_1_r_i_1
- (.I0(sof_to_data_r),
- .I1(data_r),
- .I2(S_AXI_TX_TLAST),
- .I3(TX_DST_RDY_N_Buffer_reg_0),
- .I4(S_AXI_TX_TVALID),
- .O(next_data_to_eof_1_c));
- FDRE data_to_eof_1_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_data_to_eof_1_c),
- .Q(data_to_eof_1_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE data_to_eof_2_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(data_to_eof_1_r),
- .Q(data_to_eof_2_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE do_cc_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(DO_CC_I),
- .Q(D_0),
- .R(1'b0));
- (* BOX_TYPE = "PRIMITIVE" *)
- (* XILINX_LEGACY_PRIM = "FDR" *)
- FDRE #(
- .INIT(1'b0))
- gen_cc_flop_0_i
- (.C(user_clk),
- .CE(1'b1),
- .D(D_0),
- .Q(gen_cc_i),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hEFEFEFEFEFEFEF00))
- idle_r_i_1
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(TX_DST_RDY_N_Buffer_reg_0),
- .I2(S_AXI_TX_TVALID),
- .I3(idle_r),
- .I4(sof_to_eof_2_r),
- .I5(data_to_eof_2_r),
- .O(next_idle_c));
- FDSE idle_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_idle_c),
- .Q(idle_r),
- .S(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair268" *)
- LUT5 #(
- .INIT(32'hF3FF0100))
- in_frame_r_i_1
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(S_AXI_TX_TLAST),
- .I2(TX_DST_RDY_N_Buffer_reg_0),
- .I3(S_AXI_TX_TVALID),
- .I4(in_frame_r_reg),
- .O(new_pkt_r_reg));
- (* SOFT_HLUTNM = "soft_lutpair267" *)
- LUT5 #(
- .INIT(32'h00040000))
- sof_to_data_r_i_1
- (.I0(S_AXI_TX_TLAST),
- .I1(S_AXI_TX_TVALID),
- .I2(TX_DST_RDY_N_Buffer_reg_0),
- .I3(sof_to_eof_1_r_reg_0),
- .I4(sof_to_data_r_i_2_n_0),
- .O(next_sof_to_data_c));
- (* SOFT_HLUTNM = "soft_lutpair266" *)
- LUT3 #(
- .INIT(8'hFE))
- sof_to_data_r_i_2
- (.I0(data_to_eof_2_r),
- .I1(sof_to_eof_2_r),
- .I2(idle_r),
- .O(sof_to_data_r_i_2_n_0));
- FDRE sof_to_data_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_sof_to_data_c),
- .Q(sof_to_data_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair266" *)
- LUT5 #(
- .INIT(32'h11111110))
- sof_to_eof_1_r_i_1
- (.I0(sof_to_eof_1_r_reg_0),
- .I1(TX_DST_RDY_N_Buffer_i_3_n_0),
- .I2(idle_r),
- .I3(sof_to_eof_2_r),
- .I4(data_to_eof_2_r),
- .O(next_sof_to_eof_1_c));
- FDRE sof_to_eof_1_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(next_sof_to_eof_1_c),
- .Q(sof_to_eof_1_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE sof_to_eof_2_r_reg
- (.C(user_clk),
- .CE(pdu_ok_c),
- .D(sof_to_eof_1_r),
- .Q(sof_to_eof_2_r),
- .R(GEN_SUF_Buffer_reg_0));
- LUT4 #(
- .INIT(16'hFFFE))
- storage_ufc_v_r_i_1
- (.I0(ufc_message2_r),
- .I1(ufc_message8_r),
- .I2(ufc_message6_r),
- .I3(ufc_message4_r),
- .O(ufc_message_i));
- LUT1 #(
- .INIT(2'h1))
- storage_v_r_i_1
- (.I0(D_0),
- .O(pdu_ok_c));
- FDRE suf_delay_1_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ufc_header_r_reg_0),
- .Q(suf_delay_1_r),
- .R(GEN_SUF_Buffer_reg_0));
- FDRE suf_delay_2_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(suf_delay_1_r),
- .Q(suf_delay_2_r),
- .R(GEN_SUF_Buffer_reg_0));
- LUT2 #(
- .INIT(4'h1))
- \tx_pe_ufc_v_r[1]_i_1
- (.I0(ufc_idle_r),
- .I1(ufc_header_r_reg_0),
- .O(D));
- LUT6 #(
- .INIT(64'h0008000C00080008))
- ufc_header_r_i_2
- (.I0(ufc_header_r_i_3_n_0),
- .I1(S_AXI_UFC_TX_REQ),
- .I2(WARN_CC),
- .I3(DO_CC_I),
- .I4(ufc_header_r_i_4_n_0),
- .I5(ufc_message_count_r[2]),
- .O(next_ufc_header_c));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- ufc_header_r_i_3
- (.I0(ufc_message1_r),
- .I1(ufc_message7_r),
- .I2(ufc_idle_r),
- .I3(ufc_message5_r),
- .I4(ufc_message3_r),
- .O(ufc_header_r_i_3_n_0));
- LUT6 #(
- .INIT(64'h3030505F3F3F505F))
- ufc_header_r_i_4
- (.I0(ufc_message4_r),
- .I1(ufc_message8_r),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_message2_r),
- .I4(ufc_message_count_r[0]),
- .I5(ufc_message6_r),
- .O(ufc_header_r_i_4_n_0));
- FDRE ufc_header_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_header_c),
- .Q(ufc_header_r_reg_0),
- .R(GEN_SUF_Buffer_reg_0));
- FDSE ufc_idle_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_idle_c),
- .Q(ufc_idle_r),
- .S(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair271" *)
- LUT4 #(
- .INIT(16'h0002))
- ufc_message1_r_i_1
- (.I0(ufc_header_r_reg_0),
- .I1(ufc_message_count_r[0]),
- .I2(ufc_message_count_r[2]),
- .I3(ufc_message_count_r[1]),
- .O(next_ufc_message1_c));
- FDRE ufc_message1_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message1_c),
- .Q(ufc_message1_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair271" *)
- LUT4 #(
- .INIT(16'hFE00))
- ufc_message2_r_i_1
- (.I0(ufc_message_count_r[0]),
- .I1(ufc_message_count_r[2]),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_header_r_reg_0),
- .O(next_ufc_message2_c));
- FDRE ufc_message2_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message2_c),
- .Q(ufc_message2_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair272" *)
- LUT4 #(
- .INIT(16'h0400))
- ufc_message3_r_i_1
- (.I0(ufc_message_count_r[2]),
- .I1(ufc_message_count_r[1]),
- .I2(ufc_message_count_r[0]),
- .I3(ufc_message2_r),
- .O(next_ufc_message3_c));
- FDRE ufc_message3_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message3_c),
- .Q(ufc_message3_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair272" *)
- LUT4 #(
- .INIT(16'hF080))
- ufc_message4_r_i_1
- (.I0(ufc_message_count_r[2]),
- .I1(ufc_message_count_r[1]),
- .I2(ufc_message2_r),
- .I3(ufc_message_count_r[0]),
- .O(next_ufc_message4_c));
- FDRE ufc_message4_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message4_c),
- .Q(ufc_message4_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair269" *)
- LUT4 #(
- .INIT(16'h0008))
- ufc_message5_r_i_1
- (.I0(ufc_message4_r),
- .I1(ufc_message_count_r[0]),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_message_count_r[2]),
- .O(next_ufc_message5_c));
- FDRE ufc_message5_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message5_c),
- .Q(ufc_message5_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair269" *)
- LUT4 #(
- .INIT(16'h8880))
- ufc_message6_r_i_1
- (.I0(ufc_message4_r),
- .I1(ufc_message_count_r[0]),
- .I2(ufc_message_count_r[1]),
- .I3(ufc_message_count_r[2]),
- .O(next_ufc_message6_c));
- FDRE ufc_message6_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message6_c),
- .Q(ufc_message6_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair270" *)
- LUT4 #(
- .INIT(16'h4000))
- ufc_message7_r_i_1
- (.I0(ufc_message_count_r[2]),
- .I1(ufc_message_count_r[1]),
- .I2(ufc_message6_r),
- .I3(ufc_message_count_r[0]),
- .O(next_ufc_message7_c));
- FDRE ufc_message7_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message7_c),
- .Q(ufc_message7_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair270" *)
- LUT4 #(
- .INIT(16'h8000))
- ufc_message8_r_i_1
- (.I0(ufc_message_count_r[1]),
- .I1(ufc_message_count_r[2]),
- .I2(ufc_message6_r),
- .I3(ufc_message_count_r[0]),
- .O(next_ufc_message8_c));
- FDRE ufc_message8_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(next_ufc_message8_c),
- .Q(ufc_message8_r),
- .R(GEN_SUF_Buffer_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair273" *)
- LUT3 #(
- .INIT(8'hB8))
- \ufc_message_count_r[0]_i_1
- (.I0(S_AXI_UFC_TX_MS[0]),
- .I1(next_ufc_header_c),
- .I2(ufc_message_count_r[0]),
- .O(\ufc_message_count_r[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair273" *)
- LUT3 #(
- .INIT(8'hB8))
- \ufc_message_count_r[1]_i_1
- (.I0(S_AXI_UFC_TX_MS[1]),
- .I1(next_ufc_header_c),
- .I2(ufc_message_count_r[1]),
- .O(\ufc_message_count_r[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair275" *)
- LUT3 #(
- .INIT(8'hB8))
- \ufc_message_count_r[2]_i_1
- (.I0(S_AXI_UFC_TX_MS[2]),
- .I1(next_ufc_header_c),
- .I2(ufc_message_count_r[2]),
- .O(\ufc_message_count_r[2]_i_1_n_0 ));
- FDRE \ufc_message_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\ufc_message_count_r[0]_i_1_n_0 ),
- .Q(ufc_message_count_r[0]),
- .R(1'b0));
- FDRE \ufc_message_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\ufc_message_count_r[1]_i_1_n_0 ),
- .Q(ufc_message_count_r[1]),
- .R(1'b0));
- FDRE \ufc_message_count_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\ufc_message_count_r[2]_i_1_n_0 ),
- .Q(ufc_message_count_r[2]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_TX_LL_DATAPATH" *)
-module north_channel_north_channel_TX_LL_DATAPATH
- (in_frame_r_reg_0,
- Q,
- \GEN_PAD_Buffer_reg[0]_0 ,
- \TX_PE_DATA_Buffer_reg[0]_0 ,
- E,
- user_clk,
- ufc_message_i,
- in_frame_r_reg_1,
- in_frame_r_reg_2,
- S_AXI_TX_TLAST,
- S_AXI_TX_TKEEP,
- \tx_pe_data_v_r_reg[1]_0 ,
- S_AXI_TX_TVALID,
- tx_dst_rdy,
- D_0,
- D,
- S_AXI_TX_TDATA);
- output in_frame_r_reg_0;
- output [1:0]Q;
- output [1:0]\GEN_PAD_Buffer_reg[0]_0 ;
- output [31:0]\TX_PE_DATA_Buffer_reg[0]_0 ;
- input [0:0]E;
- input user_clk;
- input [0:0]ufc_message_i;
- input in_frame_r_reg_1;
- input in_frame_r_reg_2;
- input S_AXI_TX_TLAST;
- input [0:3]S_AXI_TX_TKEEP;
- input \tx_pe_data_v_r_reg[1]_0 ;
- input S_AXI_TX_TVALID;
- input tx_dst_rdy;
- input D_0;
- input [0:0]D;
- input [0:31]S_AXI_TX_TDATA;
-
- wire [0:0]D;
- wire D_0;
- wire [0:0]E;
- wire [1:0]\GEN_PAD_Buffer_reg[0]_0 ;
- wire [1:0]Q;
- wire [0:31]S_AXI_TX_TDATA;
- wire [0:3]S_AXI_TX_TKEEP;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TVALID;
- wire [31:0]\TX_PE_DATA_Buffer_reg[0]_0 ;
- wire \gen_pad_r[1]_i_1_n_0 ;
- wire \gen_pad_r_reg_n_0_[0] ;
- wire \gen_pad_r_reg_n_0_[1] ;
- wire in_frame_r_reg_0;
- wire in_frame_r_reg_1;
- wire in_frame_r_reg_2;
- wire p_13_in;
- wire p_3_in;
- wire [1:0]p_3_out;
- wire [1:0]p_4_out;
- wire storage_pad_r;
- wire storage_pad_r0;
- wire storage_pad_r_i_2_n_0;
- wire [0:15]storage_r;
- wire storage_ufc_v_r;
- wire storage_v_r;
- wire storage_v_r0;
- wire tx_dst_rdy;
- wire [0:31]tx_pe_data_r;
- wire \tx_pe_data_v_r_reg[1]_0 ;
- wire \tx_pe_data_v_r_reg_n_0_[0] ;
- wire \tx_pe_data_v_r_reg_n_0_[1] ;
- wire \tx_pe_ufc_v_r_reg_n_0_[1] ;
- wire [0:0]ufc_message_i;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair278" *)
- LUT3 #(
- .INIT(8'h10))
- \GEN_PAD_Buffer[0]_i_1
- (.I0(D_0),
- .I1(p_3_in),
- .I2(\gen_pad_r_reg_n_0_[0] ),
- .O(p_4_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair279" *)
- LUT3 #(
- .INIT(8'h10))
- \GEN_PAD_Buffer[1]_i_1
- (.I0(D_0),
- .I1(\tx_pe_ufc_v_r_reg_n_0_[1] ),
- .I2(\gen_pad_r_reg_n_0_[1] ),
- .O(p_4_out[0]));
- FDRE \GEN_PAD_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_4_out[1]),
- .Q(\GEN_PAD_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \GEN_PAD_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_4_out[0]),
- .Q(\GEN_PAD_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[0]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [31]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[10]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [21]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[11]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [20]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[12]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [19]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[13]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [18]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[14]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [17]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[15]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [16]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[16]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [15]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[17]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [14]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[18]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [13]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[19]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [12]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[1]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [30]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[20]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [11]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[21]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [10]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[22]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [9]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[23]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [8]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[24]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [7]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[25]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [6]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[26]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [5]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[27]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [4]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[28]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [3]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[29]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [2]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[2]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [29]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[30]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[31]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[3]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [28]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[4]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [27]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[5]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [26]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[6]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [25]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[7]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [24]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[8]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [23]),
- .R(1'b0));
- FDRE \TX_PE_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(tx_pe_data_r[9]),
- .Q(\TX_PE_DATA_Buffer_reg[0]_0 [22]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair278" *)
- LUT3 #(
- .INIT(8'hF4))
- \TX_PE_DATA_V_Buffer[0]_i_1
- (.I0(D_0),
- .I1(\tx_pe_data_v_r_reg_n_0_[0] ),
- .I2(p_3_in),
- .O(p_3_out[1]));
- (* SOFT_HLUTNM = "soft_lutpair279" *)
- LUT3 #(
- .INIT(8'hF4))
- \TX_PE_DATA_V_Buffer[1]_i_1
- (.I0(D_0),
- .I1(\tx_pe_data_v_r_reg_n_0_[1] ),
- .I2(\tx_pe_ufc_v_r_reg_n_0_[1] ),
- .O(p_3_out[0]));
- FDRE \TX_PE_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \TX_PE_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(p_3_out[0]),
- .Q(Q[0]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair277" *)
- LUT5 #(
- .INIT(32'h00020228))
- \gen_pad_r[1]_i_1
- (.I0(storage_pad_r_i_2_n_0),
- .I1(S_AXI_TX_TKEEP[2]),
- .I2(S_AXI_TX_TKEEP[3]),
- .I3(S_AXI_TX_TKEEP[0]),
- .I4(S_AXI_TX_TKEEP[1]),
- .O(\gen_pad_r[1]_i_1_n_0 ));
- FDRE \gen_pad_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(storage_pad_r),
- .Q(\gen_pad_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \gen_pad_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(\gen_pad_r[1]_i_1_n_0 ),
- .Q(\gen_pad_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE in_frame_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(in_frame_r_reg_2),
- .Q(in_frame_r_reg_0),
- .R(in_frame_r_reg_1));
- (* SOFT_HLUTNM = "soft_lutpair277" *)
- LUT5 #(
- .INIT(32'h28808000))
- storage_pad_r_i_1
- (.I0(storage_pad_r_i_2_n_0),
- .I1(S_AXI_TX_TKEEP[2]),
- .I2(S_AXI_TX_TKEEP[3]),
- .I3(S_AXI_TX_TKEEP[0]),
- .I4(S_AXI_TX_TKEEP[1]),
- .O(storage_pad_r0));
- (* SOFT_HLUTNM = "soft_lutpair276" *)
- LUT5 #(
- .INIT(32'h00D00000))
- storage_pad_r_i_2
- (.I0(\tx_pe_data_v_r_reg[1]_0 ),
- .I1(in_frame_r_reg_0),
- .I2(S_AXI_TX_TLAST),
- .I3(tx_dst_rdy),
- .I4(S_AXI_TX_TVALID),
- .O(storage_pad_r_i_2_n_0));
- FDRE storage_pad_r_reg
- (.C(user_clk),
- .CE(E),
- .D(storage_pad_r0),
- .Q(storage_pad_r),
- .R(1'b0));
- FDRE \storage_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[16]),
- .Q(storage_r[0]),
- .R(1'b0));
- FDRE \storage_r_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[26]),
- .Q(storage_r[10]),
- .R(1'b0));
- FDRE \storage_r_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[27]),
- .Q(storage_r[11]),
- .R(1'b0));
- FDRE \storage_r_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[28]),
- .Q(storage_r[12]),
- .R(1'b0));
- FDRE \storage_r_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[29]),
- .Q(storage_r[13]),
- .R(1'b0));
- FDRE \storage_r_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[30]),
- .Q(storage_r[14]),
- .R(1'b0));
- FDRE \storage_r_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[31]),
- .Q(storage_r[15]),
- .R(1'b0));
- FDRE \storage_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[17]),
- .Q(storage_r[1]),
- .R(1'b0));
- FDRE \storage_r_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[18]),
- .Q(storage_r[2]),
- .R(1'b0));
- FDRE \storage_r_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[19]),
- .Q(storage_r[3]),
- .R(1'b0));
- FDRE \storage_r_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[20]),
- .Q(storage_r[4]),
- .R(1'b0));
- FDRE \storage_r_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[21]),
- .Q(storage_r[5]),
- .R(1'b0));
- FDRE \storage_r_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[22]),
- .Q(storage_r[6]),
- .R(1'b0));
- FDRE \storage_r_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[23]),
- .Q(storage_r[7]),
- .R(1'b0));
- FDRE \storage_r_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[24]),
- .Q(storage_r[8]),
- .R(1'b0));
- FDRE \storage_r_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[25]),
- .Q(storage_r[9]),
- .R(1'b0));
- FDRE storage_ufc_v_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(ufc_message_i),
- .Q(storage_ufc_v_r),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hAAA2A222A222222A))
- storage_v_r_i_2
- (.I0(p_13_in),
- .I1(S_AXI_TX_TLAST),
- .I2(S_AXI_TX_TKEEP[0]),
- .I3(S_AXI_TX_TKEEP[1]),
- .I4(S_AXI_TX_TKEEP[2]),
- .I5(S_AXI_TX_TKEEP[3]),
- .O(storage_v_r0));
- FDRE storage_v_r_reg
- (.C(user_clk),
- .CE(E),
- .D(storage_v_r0),
- .Q(storage_v_r),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[0]),
- .Q(tx_pe_data_r[0]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[10]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[10]),
- .Q(tx_pe_data_r[10]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[11]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[11]),
- .Q(tx_pe_data_r[11]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[12]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[12]),
- .Q(tx_pe_data_r[12]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[13]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[13]),
- .Q(tx_pe_data_r[13]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[14]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[14]),
- .Q(tx_pe_data_r[14]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[15]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[15]),
- .Q(tx_pe_data_r[15]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[16]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[0]),
- .Q(tx_pe_data_r[16]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[17]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[1]),
- .Q(tx_pe_data_r[17]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[18]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[2]),
- .Q(tx_pe_data_r[18]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[19]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[3]),
- .Q(tx_pe_data_r[19]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[1]),
- .Q(tx_pe_data_r[1]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[20]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[4]),
- .Q(tx_pe_data_r[20]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[21]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[5]),
- .Q(tx_pe_data_r[21]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[22]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[6]),
- .Q(tx_pe_data_r[22]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[23]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[7]),
- .Q(tx_pe_data_r[23]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[24]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[8]),
- .Q(tx_pe_data_r[24]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[25]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[9]),
- .Q(tx_pe_data_r[25]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[26]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[10]),
- .Q(tx_pe_data_r[26]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[27]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[11]),
- .Q(tx_pe_data_r[27]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[28]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[12]),
- .Q(tx_pe_data_r[28]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[29]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[13]),
- .Q(tx_pe_data_r[29]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[2]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[2]),
- .Q(tx_pe_data_r[2]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[30]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[14]),
- .Q(tx_pe_data_r[30]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[31]
- (.C(user_clk),
- .CE(E),
- .D(S_AXI_TX_TDATA[15]),
- .Q(tx_pe_data_r[31]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[3]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[3]),
- .Q(tx_pe_data_r[3]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[4]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[4]),
- .Q(tx_pe_data_r[4]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[5]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[5]),
- .Q(tx_pe_data_r[5]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[6]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[6]),
- .Q(tx_pe_data_r[6]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[7]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[7]),
- .Q(tx_pe_data_r[7]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[8]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[8]),
- .Q(tx_pe_data_r[8]),
- .R(1'b0));
- FDRE \tx_pe_data_r_reg[9]
- (.C(user_clk),
- .CE(E),
- .D(storage_r[9]),
- .Q(tx_pe_data_r[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair276" *)
- LUT4 #(
- .INIT(16'h00D0))
- \tx_pe_data_v_r[1]_i_1
- (.I0(\tx_pe_data_v_r_reg[1]_0 ),
- .I1(in_frame_r_reg_0),
- .I2(S_AXI_TX_TVALID),
- .I3(tx_dst_rdy),
- .O(p_13_in));
- FDRE \tx_pe_data_v_r_reg[0]
- (.C(user_clk),
- .CE(E),
- .D(storage_v_r),
- .Q(\tx_pe_data_v_r_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \tx_pe_data_v_r_reg[1]
- (.C(user_clk),
- .CE(E),
- .D(p_13_in),
- .Q(\tx_pe_data_v_r_reg_n_0_[1] ),
- .R(1'b0));
- FDRE \tx_pe_ufc_v_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(storage_ufc_v_r),
- .Q(p_3_in),
- .R(1'b0));
- FDRE \tx_pe_ufc_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(\tx_pe_ufc_v_r_reg_n_0_[1] ),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_BARREL_SHIFTER" *)
-module north_channel_north_channel_UFC_BARREL_SHIFTER
- (SHIFTED_DATA_Buffer,
- \SHIFTED_DATA_Buffer_reg[15]_0 ,
- \SHIFTED_DATA_Buffer_reg[14]_0 ,
- \SHIFTED_DATA_Buffer_reg[13]_0 ,
- \SHIFTED_DATA_Buffer_reg[12]_0 ,
- \SHIFTED_DATA_Buffer_reg[11]_0 ,
- \SHIFTED_DATA_Buffer_reg[10]_0 ,
- \SHIFTED_DATA_Buffer_reg[9]_0 ,
- \SHIFTED_DATA_Buffer_reg[8]_0 ,
- \SHIFTED_DATA_Buffer_reg[7]_0 ,
- \SHIFTED_DATA_Buffer_reg[6]_0 ,
- \SHIFTED_DATA_Buffer_reg[5]_0 ,
- \SHIFTED_DATA_Buffer_reg[4]_0 ,
- \SHIFTED_DATA_Buffer_reg[3]_0 ,
- \SHIFTED_DATA_Buffer_reg[2]_0 ,
- \SHIFTED_DATA_Buffer_reg[1]_0 ,
- \SHIFTED_DATA_Buffer_reg[0]_0 ,
- \SHIFTED_DATA_Buffer_reg[0]_1 ,
- BARREL_SHIFTER_CONTROL_Buffer,
- user_clk,
- UFC_OUTPUT_SELECT_Buffer,
- \MUXED_DATA_Buffer_reg[31] ,
- \MUXED_DATA_Buffer_reg[30] ,
- \MUXED_DATA_Buffer_reg[29] ,
- \MUXED_DATA_Buffer_reg[28] ,
- \MUXED_DATA_Buffer_reg[27] ,
- \MUXED_DATA_Buffer_reg[26] ,
- \MUXED_DATA_Buffer_reg[25] ,
- \MUXED_DATA_Buffer_reg[24] ,
- \MUXED_DATA_Buffer_reg[23] ,
- \MUXED_DATA_Buffer_reg[22] ,
- \MUXED_DATA_Buffer_reg[21] ,
- \MUXED_DATA_Buffer_reg[20] ,
- \MUXED_DATA_Buffer_reg[19] ,
- \MUXED_DATA_Buffer_reg[18] ,
- \MUXED_DATA_Buffer_reg[17] ,
- \MUXED_DATA_Buffer_reg[16] );
- output [0:31]SHIFTED_DATA_Buffer;
- output \SHIFTED_DATA_Buffer_reg[15]_0 ;
- output \SHIFTED_DATA_Buffer_reg[14]_0 ;
- output \SHIFTED_DATA_Buffer_reg[13]_0 ;
- output \SHIFTED_DATA_Buffer_reg[12]_0 ;
- output \SHIFTED_DATA_Buffer_reg[11]_0 ;
- output \SHIFTED_DATA_Buffer_reg[10]_0 ;
- output \SHIFTED_DATA_Buffer_reg[9]_0 ;
- output \SHIFTED_DATA_Buffer_reg[8]_0 ;
- output \SHIFTED_DATA_Buffer_reg[7]_0 ;
- output \SHIFTED_DATA_Buffer_reg[6]_0 ;
- output \SHIFTED_DATA_Buffer_reg[5]_0 ;
- output \SHIFTED_DATA_Buffer_reg[4]_0 ;
- output \SHIFTED_DATA_Buffer_reg[3]_0 ;
- output \SHIFTED_DATA_Buffer_reg[2]_0 ;
- output \SHIFTED_DATA_Buffer_reg[1]_0 ;
- output \SHIFTED_DATA_Buffer_reg[0]_0 ;
- input [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
- input BARREL_SHIFTER_CONTROL_Buffer;
- input user_clk;
- input [0:0]UFC_OUTPUT_SELECT_Buffer;
- input \MUXED_DATA_Buffer_reg[31] ;
- input \MUXED_DATA_Buffer_reg[30] ;
- input \MUXED_DATA_Buffer_reg[29] ;
- input \MUXED_DATA_Buffer_reg[28] ;
- input \MUXED_DATA_Buffer_reg[27] ;
- input \MUXED_DATA_Buffer_reg[26] ;
- input \MUXED_DATA_Buffer_reg[25] ;
- input \MUXED_DATA_Buffer_reg[24] ;
- input \MUXED_DATA_Buffer_reg[23] ;
- input \MUXED_DATA_Buffer_reg[22] ;
- input \MUXED_DATA_Buffer_reg[21] ;
- input \MUXED_DATA_Buffer_reg[20] ;
- input \MUXED_DATA_Buffer_reg[19] ;
- input \MUXED_DATA_Buffer_reg[18] ;
- input \MUXED_DATA_Buffer_reg[17] ;
- input \MUXED_DATA_Buffer_reg[16] ;
-
- wire BARREL_SHIFTER_CONTROL_Buffer;
- wire \MUXED_DATA_Buffer_reg[16] ;
- wire \MUXED_DATA_Buffer_reg[17] ;
- wire \MUXED_DATA_Buffer_reg[18] ;
- wire \MUXED_DATA_Buffer_reg[19] ;
- wire \MUXED_DATA_Buffer_reg[20] ;
- wire \MUXED_DATA_Buffer_reg[21] ;
- wire \MUXED_DATA_Buffer_reg[22] ;
- wire \MUXED_DATA_Buffer_reg[23] ;
- wire \MUXED_DATA_Buffer_reg[24] ;
- wire \MUXED_DATA_Buffer_reg[25] ;
- wire \MUXED_DATA_Buffer_reg[26] ;
- wire \MUXED_DATA_Buffer_reg[27] ;
- wire \MUXED_DATA_Buffer_reg[28] ;
- wire \MUXED_DATA_Buffer_reg[29] ;
- wire \MUXED_DATA_Buffer_reg[30] ;
- wire \MUXED_DATA_Buffer_reg[31] ;
- wire [0:31]SHIFTED_DATA_Buffer;
- wire \SHIFTED_DATA_Buffer_reg[0]_0 ;
- wire [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
- wire \SHIFTED_DATA_Buffer_reg[10]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[11]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[12]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[13]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[14]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[15]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[1]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[2]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[3]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[4]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[5]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[6]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[7]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[8]_0 ;
- wire \SHIFTED_DATA_Buffer_reg[9]_0 ;
- wire [0:0]UFC_OUTPUT_SELECT_Buffer;
- wire [0:15]shifted_data_c;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair241" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[16]_i_1
- (.I0(SHIFTED_DATA_Buffer[0]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[16] ),
- .O(\SHIFTED_DATA_Buffer_reg[0]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair241" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[17]_i_1
- (.I0(SHIFTED_DATA_Buffer[1]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[17] ),
- .O(\SHIFTED_DATA_Buffer_reg[1]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair240" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[18]_i_1
- (.I0(SHIFTED_DATA_Buffer[2]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[18] ),
- .O(\SHIFTED_DATA_Buffer_reg[2]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair240" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[19]_i_1
- (.I0(SHIFTED_DATA_Buffer[3]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[19] ),
- .O(\SHIFTED_DATA_Buffer_reg[3]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair239" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[20]_i_1
- (.I0(SHIFTED_DATA_Buffer[4]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[20] ),
- .O(\SHIFTED_DATA_Buffer_reg[4]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair239" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[21]_i_1
- (.I0(SHIFTED_DATA_Buffer[5]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[21] ),
- .O(\SHIFTED_DATA_Buffer_reg[5]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair238" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[22]_i_1
- (.I0(SHIFTED_DATA_Buffer[6]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[22] ),
- .O(\SHIFTED_DATA_Buffer_reg[6]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair238" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[23]_i_1
- (.I0(SHIFTED_DATA_Buffer[7]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[23] ),
- .O(\SHIFTED_DATA_Buffer_reg[7]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair237" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[24]_i_1
- (.I0(SHIFTED_DATA_Buffer[8]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[24] ),
- .O(\SHIFTED_DATA_Buffer_reg[8]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair237" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[25]_i_1
- (.I0(SHIFTED_DATA_Buffer[9]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[25] ),
- .O(\SHIFTED_DATA_Buffer_reg[9]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair236" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[26]_i_1
- (.I0(SHIFTED_DATA_Buffer[10]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[26] ),
- .O(\SHIFTED_DATA_Buffer_reg[10]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair236" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[27]_i_1
- (.I0(SHIFTED_DATA_Buffer[11]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[27] ),
- .O(\SHIFTED_DATA_Buffer_reg[11]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair235" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[28]_i_1
- (.I0(SHIFTED_DATA_Buffer[12]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[28] ),
- .O(\SHIFTED_DATA_Buffer_reg[12]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair235" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[29]_i_1
- (.I0(SHIFTED_DATA_Buffer[13]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[29] ),
- .O(\SHIFTED_DATA_Buffer_reg[13]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair234" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[30]_i_1
- (.I0(SHIFTED_DATA_Buffer[14]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[30] ),
- .O(\SHIFTED_DATA_Buffer_reg[14]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair234" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[31]_i_1
- (.I0(SHIFTED_DATA_Buffer[15]),
- .I1(UFC_OUTPUT_SELECT_Buffer),
- .I2(\MUXED_DATA_Buffer_reg[31] ),
- .O(\SHIFTED_DATA_Buffer_reg[15]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair233" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[0]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [31]),
- .O(shifted_data_c[0]));
- (* SOFT_HLUTNM = "soft_lutpair228" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[10]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [21]),
- .O(shifted_data_c[10]));
- (* SOFT_HLUTNM = "soft_lutpair228" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[11]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [20]),
- .O(shifted_data_c[11]));
- (* SOFT_HLUTNM = "soft_lutpair227" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[12]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [19]),
- .O(shifted_data_c[12]));
- (* SOFT_HLUTNM = "soft_lutpair227" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[13]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [18]),
- .O(shifted_data_c[13]));
- (* SOFT_HLUTNM = "soft_lutpair226" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[14]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [17]),
- .O(shifted_data_c[14]));
- (* SOFT_HLUTNM = "soft_lutpair226" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[15]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [16]),
- .O(shifted_data_c[15]));
- (* SOFT_HLUTNM = "soft_lutpair233" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[1]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [30]),
- .O(shifted_data_c[1]));
- (* SOFT_HLUTNM = "soft_lutpair232" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[2]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [29]),
- .O(shifted_data_c[2]));
- (* SOFT_HLUTNM = "soft_lutpair232" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[3]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [28]),
- .O(shifted_data_c[3]));
- (* SOFT_HLUTNM = "soft_lutpair231" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[4]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [27]),
- .O(shifted_data_c[4]));
- (* SOFT_HLUTNM = "soft_lutpair231" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[5]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [26]),
- .O(shifted_data_c[5]));
- (* SOFT_HLUTNM = "soft_lutpair230" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[6]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [25]),
- .O(shifted_data_c[6]));
- (* SOFT_HLUTNM = "soft_lutpair230" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[7]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [24]),
- .O(shifted_data_c[7]));
- (* SOFT_HLUTNM = "soft_lutpair229" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[8]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [23]),
- .O(shifted_data_c[8]));
- (* SOFT_HLUTNM = "soft_lutpair229" *)
- LUT3 #(
- .INIT(8'hB8))
- \SHIFTED_DATA_Buffer[9]_i_1
- (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
- .I1(BARREL_SHIFTER_CONTROL_Buffer),
- .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [22]),
- .O(shifted_data_c[9]));
- FDRE \SHIFTED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[0]),
- .Q(SHIFTED_DATA_Buffer[0]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[10]),
- .Q(SHIFTED_DATA_Buffer[10]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[11]),
- .Q(SHIFTED_DATA_Buffer[11]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[12]),
- .Q(SHIFTED_DATA_Buffer[12]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[13]),
- .Q(SHIFTED_DATA_Buffer[13]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[14]),
- .Q(SHIFTED_DATA_Buffer[14]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[15]),
- .Q(SHIFTED_DATA_Buffer[15]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
- .Q(SHIFTED_DATA_Buffer[16]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
- .Q(SHIFTED_DATA_Buffer[17]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
- .Q(SHIFTED_DATA_Buffer[18]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
- .Q(SHIFTED_DATA_Buffer[19]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[1]),
- .Q(SHIFTED_DATA_Buffer[1]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
- .Q(SHIFTED_DATA_Buffer[20]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
- .Q(SHIFTED_DATA_Buffer[21]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
- .Q(SHIFTED_DATA_Buffer[22]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
- .Q(SHIFTED_DATA_Buffer[23]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
- .Q(SHIFTED_DATA_Buffer[24]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
- .Q(SHIFTED_DATA_Buffer[25]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
- .Q(SHIFTED_DATA_Buffer[26]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
- .Q(SHIFTED_DATA_Buffer[27]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
- .Q(SHIFTED_DATA_Buffer[28]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
- .Q(SHIFTED_DATA_Buffer[29]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[2]),
- .Q(SHIFTED_DATA_Buffer[2]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
- .Q(SHIFTED_DATA_Buffer[30]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
- .Q(SHIFTED_DATA_Buffer[31]),
- .R(BARREL_SHIFTER_CONTROL_Buffer));
- FDRE \SHIFTED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[3]),
- .Q(SHIFTED_DATA_Buffer[3]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[4]),
- .Q(SHIFTED_DATA_Buffer[4]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[5]),
- .Q(SHIFTED_DATA_Buffer[5]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[6]),
- .Q(SHIFTED_DATA_Buffer[6]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[7]),
- .Q(SHIFTED_DATA_Buffer[7]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[8]),
- .Q(SHIFTED_DATA_Buffer[8]),
- .R(1'b0));
- FDRE \SHIFTED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(shifted_data_c[9]),
- .Q(SHIFTED_DATA_Buffer[9]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_BARREL_SHIFTER_CONTROL" *)
-module north_channel_north_channel_UFC_BARREL_SHIFTER_CONTROL
- (BARREL_SHIFTER_CONTROL_Buffer,
- barrel_shifter_control_i,
- user_clk);
- output BARREL_SHIFTER_CONTROL_Buffer;
- input barrel_shifter_control_i;
- input user_clk;
-
- wire BARREL_SHIFTER_CONTROL_Buffer;
- wire barrel_shifter_control_i;
- wire user_clk;
-
- FDRE \BARREL_SHIFTER_CONTROL_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(barrel_shifter_control_i),
- .Q(BARREL_SHIFTER_CONTROL_Buffer),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_FILTER" *)
-module north_channel_north_channel_UFC_FILTER
- (UFC_START,
- barrel_shifter_control_i,
- D,
- \PDU_ECP_Buffer_reg[0]_0 ,
- user_clk_0,
- user_clk_1,
- user_clk_2,
- user_clk_3,
- user_clk_4,
- user_clk_5,
- user_clk_6,
- user_clk_7,
- user_clk_8,
- user_clk_9,
- user_clk_10,
- user_clk_11,
- user_clk_12,
- user_clk_13,
- user_clk_14,
- user_clk_15,
- user_clk_16,
- user_clk_17,
- user_clk_18,
- user_clk_19,
- user_clk_20,
- user_clk_21,
- user_clk_22,
- user_clk_23,
- user_clk_24,
- user_clk_25,
- user_clk_26,
- user_clk_27,
- user_clk_28,
- user_clk_29,
- user_clk_30,
- user_clk_31,
- \PDU_PAD_Buffer_reg[0]_0 ,
- \PDU_ECP_Buffer_reg[1]_0 ,
- \PDU_ECP_Buffer_reg[0]_1 ,
- \PDU_DATA_V_Buffer_reg[0]_0 ,
- \UFC_DATA_V_Buffer_reg[0]_0 ,
- \PDU_SCP_Buffer_reg[1]_0 ,
- S1_in,
- RESET,
- neqOp,
- user_clk,
- \rx_suf_r_reg[0]_0 ,
- p_8_out,
- p_9_out,
- Q,
- rx_pe_data_striped_i,
- \stage_1_count_value_r_reg[0]_0 ,
- \stage_1_count_value_r_reg[1]_0 ,
- \stage_1_count_value_r_reg[2]_0 ,
- \stage_1_count_value_r_reg[3]_0 ,
- \rx_data_v_r_reg[0]_0 );
- output UFC_START;
- output barrel_shifter_control_i;
- output [1:0]D;
- output [1:0]\PDU_ECP_Buffer_reg[0]_0 ;
- output user_clk_0;
- output user_clk_1;
- output user_clk_2;
- output user_clk_3;
- output user_clk_4;
- output user_clk_5;
- output user_clk_6;
- output user_clk_7;
- output user_clk_8;
- output user_clk_9;
- output user_clk_10;
- output user_clk_11;
- output user_clk_12;
- output user_clk_13;
- output user_clk_14;
- output user_clk_15;
- output user_clk_16;
- output user_clk_17;
- output user_clk_18;
- output user_clk_19;
- output user_clk_20;
- output user_clk_21;
- output user_clk_22;
- output user_clk_23;
- output user_clk_24;
- output user_clk_25;
- output user_clk_26;
- output user_clk_27;
- output user_clk_28;
- output user_clk_29;
- output user_clk_30;
- output user_clk_31;
- output \PDU_PAD_Buffer_reg[0]_0 ;
- output \PDU_ECP_Buffer_reg[1]_0 ;
- output \PDU_ECP_Buffer_reg[0]_1 ;
- output [1:0]\PDU_DATA_V_Buffer_reg[0]_0 ;
- output [1:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
- output \PDU_SCP_Buffer_reg[1]_0 ;
- output S1_in;
- input RESET;
- input neqOp;
- input user_clk;
- input [1:0]\rx_suf_r_reg[0]_0 ;
- input [1:0]p_8_out;
- input [1:0]p_9_out;
- input [1:0]Q;
- input [0:31]rx_pe_data_striped_i;
- input \stage_1_count_value_r_reg[0]_0 ;
- input \stage_1_count_value_r_reg[1]_0 ;
- input \stage_1_count_value_r_reg[2]_0 ;
- input \stage_1_count_value_r_reg[3]_0 ;
- input [1:0]\rx_data_v_r_reg[0]_0 ;
-
- wire [1:0]D;
- wire [0:1]L;
- wire \PDU_DATA_V_Buffer[0]_i_1_n_0 ;
- wire \PDU_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\PDU_DATA_V_Buffer_reg[0]_0 ;
- wire [1:0]\PDU_ECP_Buffer_reg[0]_0 ;
- wire \PDU_ECP_Buffer_reg[0]_1 ;
- wire \PDU_ECP_Buffer_reg[1]_0 ;
- wire [0:1]PDU_PAD;
- wire \PDU_PAD_Buffer_reg[0]_0 ;
- wire \PDU_SCP_Buffer_reg[1]_0 ;
- wire [1:0]Q;
- wire RESET;
- wire S1_in;
- wire \UFC_DATA_V_Buffer[1]_i_1_n_0 ;
- wire [1:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
- wire UFC_START;
- wire UFC_START_Buffer_i_1_n_0;
- wire barrel_shifter_control_i;
- wire load_ufc_control_code_r;
- wire neqOp;
- wire [1:0]p_8_out;
- wire [1:0]p_9_out;
- wire [0:1]rx_data_v_r;
- wire [1:0]\rx_data_v_r_reg[0]_0 ;
- wire \rx_ecp_r_reg[0]_srl3_n_0 ;
- wire \rx_ecp_r_reg[1]_srl3_n_0 ;
- wire \rx_pad_r_reg[0]_srl2_n_0 ;
- wire \rx_pad_r_reg[1]_srl2_n_0 ;
- wire [0:31]rx_pe_data_striped_i;
- wire \rx_scp_r_reg[0]_srl3_n_0 ;
- wire \rx_scp_r_reg[1]_srl3_n_0 ;
- wire [1:0]\rx_suf_r_reg[0]_0 ;
- wire \rx_suf_r_reg_n_0_[1] ;
- wire [0:3]stage_1_count_value_r;
- wire \stage_1_count_value_r_reg[0]_0 ;
- wire \stage_1_count_value_r_reg[1]_0 ;
- wire \stage_1_count_value_r_reg[2]_0 ;
- wire \stage_1_count_value_r_reg[3]_0 ;
- wire [0:3]stage_2_count_value_r;
- wire \stage_2_count_value_r[0]_i_1_n_0 ;
- wire \stage_2_count_value_r[1]_i_1_n_0 ;
- wire \stage_2_count_value_r[2]_i_1_n_0 ;
- wire \stage_2_count_value_r[3]_i_1_n_0 ;
- wire [0:0]stage_2_lane_mask_c__0;
- wire user_clk;
- wire user_clk_0;
- wire user_clk_1;
- wire user_clk_10;
- wire user_clk_11;
- wire user_clk_12;
- wire user_clk_13;
- wire user_clk_14;
- wire user_clk_15;
- wire user_clk_16;
- wire user_clk_17;
- wire user_clk_18;
- wire user_clk_19;
- wire user_clk_2;
- wire user_clk_20;
- wire user_clk_21;
- wire user_clk_22;
- wire user_clk_23;
- wire user_clk_24;
- wire user_clk_25;
- wire user_clk_26;
- wire user_clk_27;
- wire user_clk_28;
- wire user_clk_29;
- wire user_clk_3;
- wire user_clk_30;
- wire user_clk_31;
- wire user_clk_4;
- wire user_clk_5;
- wire user_clk_6;
- wire user_clk_7;
- wire user_clk_8;
- wire user_clk_9;
-
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[0]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[0]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[0]),
- .Q(user_clk_0));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[10]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[10]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[10]),
- .Q(user_clk_10));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[11]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[11]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[11]),
- .Q(user_clk_11));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[12]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[12]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[12]),
- .Q(user_clk_12));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[13]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[13]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[13]),
- .Q(user_clk_13));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[14]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[14]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[14]),
- .Q(user_clk_14));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[15]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[15]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[15]),
- .Q(user_clk_15));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[16]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[16]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[16]),
- .Q(user_clk_16));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[17]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[17]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[17]),
- .Q(user_clk_17));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[18]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[18]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[18]),
- .Q(user_clk_18));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[19]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[19]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[19]),
- .Q(user_clk_19));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[1]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[1]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[1]),
- .Q(user_clk_1));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[20]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[20]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[20]),
- .Q(user_clk_20));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[21]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[21]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[21]),
- .Q(user_clk_21));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[22]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[22]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[22]),
- .Q(user_clk_22));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[23]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[23]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[23]),
- .Q(user_clk_23));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[24]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[24]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[24]),
- .Q(user_clk_24));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[25]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[25]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[25]),
- .Q(user_clk_25));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[26]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[26]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[26]),
- .Q(user_clk_26));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[27]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[27]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[27]),
- .Q(user_clk_27));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[28]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[28]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[28]),
- .Q(user_clk_28));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[29]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[29]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[29]),
- .Q(user_clk_29));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[2]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[2]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[2]),
- .Q(user_clk_2));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[30]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[30]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[30]),
- .Q(user_clk_30));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[31]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[31]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[31]),
- .Q(user_clk_31));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[3]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[3]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[3]),
- .Q(user_clk_3));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[4]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[4]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[4]),
- .Q(user_clk_4));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[5]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[5]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[5]),
- .Q(user_clk_5));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[6]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[6]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[6]),
- .Q(user_clk_6));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[7]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[7]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[7]),
- .Q(user_clk_7));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[8]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[8]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[8]),
- .Q(user_clk_8));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[9]_srl2 " *)
- SRL16E \PDU_DATA_Buffer_reg[9]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(rx_pe_data_striped_i[9]),
- .Q(user_clk_9));
- (* SOFT_HLUTNM = "soft_lutpair264" *)
- LUT5 #(
- .INIT(32'h88888882))
- \PDU_DATA_V_Buffer[0]_i_1
- (.I0(rx_data_v_r[0]),
- .I1(stage_2_count_value_r[0]),
- .I2(stage_2_count_value_r[1]),
- .I3(stage_2_count_value_r[2]),
- .I4(stage_2_count_value_r[3]),
- .O(\PDU_DATA_V_Buffer[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00000000AA02A802))
- \PDU_DATA_V_Buffer[1]_i_1
- (.I0(rx_data_v_r[1]),
- .I1(stage_2_count_value_r[2]),
- .I2(stage_2_count_value_r[1]),
- .I3(stage_2_count_value_r[0]),
- .I4(stage_2_count_value_r[3]),
- .I5(L[0]),
- .O(\PDU_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \PDU_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\PDU_DATA_V_Buffer[0]_i_1_n_0 ),
- .Q(\PDU_DATA_V_Buffer_reg[0]_0 [1]),
- .R(RESET));
- FDRE \PDU_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\PDU_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(\PDU_DATA_V_Buffer_reg[0]_0 [0]),
- .R(RESET));
- FDRE \PDU_ECP_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_ecp_r_reg[0]_srl3_n_0 ),
- .Q(\PDU_ECP_Buffer_reg[0]_0 [1]),
- .R(1'b0));
- FDRE \PDU_ECP_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_ecp_r_reg[1]_srl3_n_0 ),
- .Q(\PDU_ECP_Buffer_reg[0]_0 [0]),
- .R(1'b0));
- FDRE \PDU_PAD_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_pad_r_reg[0]_srl2_n_0 ),
- .Q(PDU_PAD[0]),
- .R(1'b0));
- FDRE \PDU_PAD_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_pad_r_reg[1]_srl2_n_0 ),
- .Q(PDU_PAD[1]),
- .R(1'b0));
- FDRE \PDU_SCP_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_scp_r_reg[0]_srl3_n_0 ),
- .Q(D[1]),
- .R(1'b0));
- FDRE \PDU_SCP_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_scp_r_reg[1]_srl3_n_0 ),
- .Q(D[0]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hAFAFAFBA))
- \UFC_DATA_V_Buffer[1]_i_1
- (.I0(L[0]),
- .I1(stage_2_count_value_r[3]),
- .I2(stage_2_count_value_r[0]),
- .I3(stage_2_count_value_r[1]),
- .I4(stage_2_count_value_r[2]),
- .O(\UFC_DATA_V_Buffer[1]_i_1_n_0 ));
- FDRE \UFC_DATA_V_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(stage_2_lane_mask_c__0),
- .Q(\UFC_DATA_V_Buffer_reg[0]_0 [1]),
- .R(RESET));
- FDRE \UFC_DATA_V_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_DATA_V_Buffer[1]_i_1_n_0 ),
- .Q(\UFC_DATA_V_Buffer_reg[0]_0 [0]),
- .R(RESET));
- FDRE \UFC_MESSAGE_START_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(L[0]),
- .Q(barrel_shifter_control_i),
- .R(RESET));
- LUT2 #(
- .INIT(4'hE))
- UFC_START_Buffer_i_1
- (.I0(L[0]),
- .I1(L[1]),
- .O(UFC_START_Buffer_i_1_n_0));
- FDRE UFC_START_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_START_Buffer_i_1_n_0),
- .Q(UFC_START),
- .R(RESET));
- LUT1 #(
- .INIT(2'h1))
- data_after_start_muxcy_0_i_1
- (.I0(D[1]),
- .O(S1_in));
- LUT1 #(
- .INIT(2'h1))
- data_after_start_muxcy_1_i_1
- (.I0(D[0]),
- .O(\PDU_SCP_Buffer_reg[1]_0 ));
- LUT2 #(
- .INIT(4'h1))
- in_frame_muxcy_0_i_1
- (.I0(\PDU_ECP_Buffer_reg[0]_0 [1]),
- .I1(D[1]),
- .O(\PDU_ECP_Buffer_reg[0]_1 ));
- LUT2 #(
- .INIT(4'h1))
- in_frame_muxcy_1_i_1
- (.I0(\PDU_ECP_Buffer_reg[0]_0 [0]),
- .I1(D[0]),
- .O(\PDU_ECP_Buffer_reg[1]_0 ));
- FDRE load_ufc_control_code_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(neqOp),
- .Q(load_ufc_control_code_r),
- .R(RESET));
- FDRE \rx_data_v_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_data_v_r_reg[0]_0 [1]),
- .Q(rx_data_v_r[0]),
- .R(RESET));
- FDRE \rx_data_v_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_data_v_r_reg[0]_0 [0]),
- .Q(rx_data_v_r[1]),
- .R(RESET));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[0]_srl3 " *)
- SRL16E \rx_ecp_r_reg[0]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_9_out[1]),
- .Q(\rx_ecp_r_reg[0]_srl3_n_0 ));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[1]_srl3 " *)
- SRL16E \rx_ecp_r_reg[1]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_9_out[0]),
- .Q(\rx_ecp_r_reg[1]_srl3_n_0 ));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg[0]_srl2 " *)
- SRL16E \rx_pad_r_reg[0]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(Q[1]),
- .Q(\rx_pad_r_reg[0]_srl2_n_0 ));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_pad_r_reg[1]_srl2 " *)
- SRL16E \rx_pad_r_reg[1]_srl2
- (.A0(1'b1),
- .A1(1'b0),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(Q[0]),
- .Q(\rx_pad_r_reg[1]_srl2_n_0 ));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg[0]_srl3 " *)
- SRL16E \rx_scp_r_reg[0]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_8_out[1]),
- .Q(\rx_scp_r_reg[0]_srl3_n_0 ));
- (* srl_bus_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg " *)
- (* srl_name = "U0/\north_channel_rx_ll_i/ufc_filter_i/rx_scp_r_reg[1]_srl3 " *)
- SRL16E \rx_scp_r_reg[1]_srl3
- (.A0(1'b0),
- .A1(1'b1),
- .A2(1'b0),
- .A3(1'b0),
- .CE(1'b1),
- .CLK(user_clk),
- .D(p_8_out[0]),
- .Q(\rx_scp_r_reg[1]_srl3_n_0 ));
- FDRE \rx_suf_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_suf_r_reg[0]_0 [1]),
- .Q(L[0]),
- .R(RESET));
- FDRE \rx_suf_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_suf_r_reg[0]_0 [0]),
- .Q(\rx_suf_r_reg_n_0_[1] ),
- .R(RESET));
- FDRE save_start_r_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(\rx_suf_r_reg_n_0_[1] ),
- .Q(L[1]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[0]_0 ),
- .Q(stage_1_count_value_r[0]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[1]_0 ),
- .Q(stage_1_count_value_r[1]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[2]_0 ),
- .Q(stage_1_count_value_r[2]),
- .R(RESET));
- FDRE \stage_1_count_value_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_1_count_value_r_reg[3]_0 ),
- .Q(stage_1_count_value_r[3]),
- .R(RESET));
- LUT2 #(
- .INIT(4'hE))
- stage_1_pad_r_i_1
- (.I0(PDU_PAD[0]),
- .I1(PDU_PAD[1]),
- .O(\PDU_PAD_Buffer_reg[0]_0 ));
- LUT2 #(
- .INIT(4'h8))
- \stage_2_count_value_r[0]_i_1
- (.I0(load_ufc_control_code_r),
- .I1(stage_1_count_value_r[0]),
- .O(\stage_2_count_value_r[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8B888B88888888B8))
- \stage_2_count_value_r[1]_i_1
- (.I0(stage_1_count_value_r[1]),
- .I1(load_ufc_control_code_r),
- .I2(stage_2_count_value_r[0]),
- .I3(stage_2_count_value_r[1]),
- .I4(stage_2_count_value_r[3]),
- .I5(stage_2_count_value_r[2]),
- .O(\stage_2_count_value_r[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h888B888B88888B88))
- \stage_2_count_value_r[2]_i_1
- (.I0(stage_1_count_value_r[2]),
- .I1(load_ufc_control_code_r),
- .I2(stage_2_count_value_r[2]),
- .I3(stage_2_count_value_r[0]),
- .I4(stage_2_count_value_r[3]),
- .I5(stage_2_count_value_r[1]),
- .O(\stage_2_count_value_r[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8B8B8B8888888888))
- \stage_2_count_value_r[3]_i_1
- (.I0(stage_1_count_value_r[3]),
- .I1(load_ufc_control_code_r),
- .I2(stage_2_count_value_r[0]),
- .I3(stage_2_count_value_r[2]),
- .I4(stage_2_count_value_r[1]),
- .I5(stage_2_count_value_r[3]),
- .O(\stage_2_count_value_r[3]_i_1_n_0 ));
- FDRE \stage_2_count_value_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[0]_i_1_n_0 ),
- .Q(stage_2_count_value_r[0]),
- .R(RESET));
- FDRE \stage_2_count_value_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[1]_i_1_n_0 ),
- .Q(stage_2_count_value_r[1]),
- .R(RESET));
- FDRE \stage_2_count_value_r_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[2]_i_1_n_0 ),
- .Q(stage_2_count_value_r[2]),
- .R(RESET));
- FDRE \stage_2_count_value_r_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\stage_2_count_value_r[3]_i_1_n_0 ),
- .Q(stage_2_count_value_r[3]),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair264" *)
- LUT4 #(
- .INIT(16'h01FE))
- stage_2_lane_mask_c
- (.I0(stage_2_count_value_r[3]),
- .I1(stage_2_count_value_r[2]),
- .I2(stage_2_count_value_r[1]),
- .I3(stage_2_count_value_r[0]),
- .O(stage_2_lane_mask_c__0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_OUTPUT_MUX" *)
-module north_channel_north_channel_UFC_OUTPUT_MUX
- (M_AXI_UFC_RX_TDATA,
- D,
- user_clk,
- UFC_OUTPUT_SELECT_Buffer,
- \MUXED_DATA_Buffer_reg[16]_0 ,
- \MUXED_DATA_Buffer_reg[17]_0 ,
- \MUXED_DATA_Buffer_reg[18]_0 ,
- \MUXED_DATA_Buffer_reg[19]_0 ,
- \MUXED_DATA_Buffer_reg[20]_0 ,
- \MUXED_DATA_Buffer_reg[21]_0 ,
- \MUXED_DATA_Buffer_reg[22]_0 ,
- \MUXED_DATA_Buffer_reg[23]_0 ,
- \MUXED_DATA_Buffer_reg[24]_0 ,
- \MUXED_DATA_Buffer_reg[25]_0 ,
- \MUXED_DATA_Buffer_reg[26]_0 ,
- \MUXED_DATA_Buffer_reg[27]_0 ,
- \MUXED_DATA_Buffer_reg[28]_0 ,
- \MUXED_DATA_Buffer_reg[29]_0 ,
- \MUXED_DATA_Buffer_reg[30]_0 ,
- \MUXED_DATA_Buffer_reg[31]_0 );
- output [0:31]M_AXI_UFC_RX_TDATA;
- input [15:0]D;
- input user_clk;
- input [0:0]UFC_OUTPUT_SELECT_Buffer;
- input \MUXED_DATA_Buffer_reg[16]_0 ;
- input \MUXED_DATA_Buffer_reg[17]_0 ;
- input \MUXED_DATA_Buffer_reg[18]_0 ;
- input \MUXED_DATA_Buffer_reg[19]_0 ;
- input \MUXED_DATA_Buffer_reg[20]_0 ;
- input \MUXED_DATA_Buffer_reg[21]_0 ;
- input \MUXED_DATA_Buffer_reg[22]_0 ;
- input \MUXED_DATA_Buffer_reg[23]_0 ;
- input \MUXED_DATA_Buffer_reg[24]_0 ;
- input \MUXED_DATA_Buffer_reg[25]_0 ;
- input \MUXED_DATA_Buffer_reg[26]_0 ;
- input \MUXED_DATA_Buffer_reg[27]_0 ;
- input \MUXED_DATA_Buffer_reg[28]_0 ;
- input \MUXED_DATA_Buffer_reg[29]_0 ;
- input \MUXED_DATA_Buffer_reg[30]_0 ;
- input \MUXED_DATA_Buffer_reg[31]_0 ;
-
- wire [15:0]D;
- wire \MUXED_DATA_Buffer_reg[16]_0 ;
- wire \MUXED_DATA_Buffer_reg[17]_0 ;
- wire \MUXED_DATA_Buffer_reg[18]_0 ;
- wire \MUXED_DATA_Buffer_reg[19]_0 ;
- wire \MUXED_DATA_Buffer_reg[20]_0 ;
- wire \MUXED_DATA_Buffer_reg[21]_0 ;
- wire \MUXED_DATA_Buffer_reg[22]_0 ;
- wire \MUXED_DATA_Buffer_reg[23]_0 ;
- wire \MUXED_DATA_Buffer_reg[24]_0 ;
- wire \MUXED_DATA_Buffer_reg[25]_0 ;
- wire \MUXED_DATA_Buffer_reg[26]_0 ;
- wire \MUXED_DATA_Buffer_reg[27]_0 ;
- wire \MUXED_DATA_Buffer_reg[28]_0 ;
- wire \MUXED_DATA_Buffer_reg[29]_0 ;
- wire \MUXED_DATA_Buffer_reg[30]_0 ;
- wire \MUXED_DATA_Buffer_reg[31]_0 ;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [0:0]UFC_OUTPUT_SELECT_Buffer;
- wire user_clk;
-
- FDRE \MUXED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[15]),
- .Q(M_AXI_UFC_RX_TDATA[0]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[5]),
- .Q(M_AXI_UFC_RX_TDATA[10]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[4]),
- .Q(M_AXI_UFC_RX_TDATA[11]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[3]),
- .Q(M_AXI_UFC_RX_TDATA[12]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[2]),
- .Q(M_AXI_UFC_RX_TDATA[13]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[1]),
- .Q(M_AXI_UFC_RX_TDATA[14]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[0]),
- .Q(M_AXI_UFC_RX_TDATA[15]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[16]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[16]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[17]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[17]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[18]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[18]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[19]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[19]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[14]),
- .Q(M_AXI_UFC_RX_TDATA[1]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[20]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[20]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[21]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[21]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[22]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[22]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[23]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[23]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[24]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[24]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[25]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[25]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[26]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[26]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[27]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[27]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[28]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[28]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[29]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[29]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[13]),
- .Q(M_AXI_UFC_RX_TDATA[2]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[30]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[30]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer_reg[31]_0 ),
- .Q(M_AXI_UFC_RX_TDATA[31]),
- .R(UFC_OUTPUT_SELECT_Buffer));
- FDRE \MUXED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[12]),
- .Q(M_AXI_UFC_RX_TDATA[3]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[11]),
- .Q(M_AXI_UFC_RX_TDATA[4]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[10]),
- .Q(M_AXI_UFC_RX_TDATA[5]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[9]),
- .Q(M_AXI_UFC_RX_TDATA[6]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[8]),
- .Q(M_AXI_UFC_RX_TDATA[7]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[7]),
- .Q(M_AXI_UFC_RX_TDATA[8]),
- .R(1'b0));
- FDRE \MUXED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(D[6]),
- .Q(M_AXI_UFC_RX_TDATA[9]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_OUTPUT_SWITCH_CONTROL" *)
-module north_channel_north_channel_UFC_OUTPUT_SWITCH_CONTROL
- (UFC_OUTPUT_SELECT_Buffer,
- Q,
- \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ,
- user_clk);
- output [1:0]UFC_OUTPUT_SELECT_Buffer;
- input [1:0]Q;
- input \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ;
- input user_clk;
-
- wire [1:0]Q;
- wire [1:0]UFC_OUTPUT_SELECT_Buffer;
- wire \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ;
- wire \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'h4))
- \UFC_OUTPUT_SELECT_Buffer[5]_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ));
- FDRE \UFC_OUTPUT_SELECT_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ),
- .Q(UFC_OUTPUT_SELECT_Buffer[1]),
- .R(1'b0));
- FDRE \UFC_OUTPUT_SELECT_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ),
- .Q(UFC_OUTPUT_SELECT_Buffer[0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_SIDEBAND_OUTPUT" *)
-module north_channel_north_channel_UFC_SIDEBAND_OUTPUT
- (\UFC_REM_Buffer_reg[0]_0 ,
- UFC_SRC_RDY_N_Buffer,
- UFC_EOF_N_Buffer,
- \UFC_REM_Buffer_reg[0]_1 ,
- user_clk,
- RESET,
- UFC_SRC_RDY_N_Buffer_reg_0,
- UFC_EOF_N_Buffer_reg_0);
- output \UFC_REM_Buffer_reg[0]_0 ;
- output UFC_SRC_RDY_N_Buffer;
- output UFC_EOF_N_Buffer;
- input \UFC_REM_Buffer_reg[0]_1 ;
- input user_clk;
- input RESET;
- input UFC_SRC_RDY_N_Buffer_reg_0;
- input UFC_EOF_N_Buffer_reg_0;
-
- wire RESET;
- wire UFC_EOF_N_Buffer;
- wire UFC_EOF_N_Buffer_reg_0;
- wire \UFC_REM_Buffer_reg[0]_0 ;
- wire \UFC_REM_Buffer_reg[0]_1 ;
- wire UFC_SRC_RDY_N_Buffer;
- wire UFC_SRC_RDY_N_Buffer_reg_0;
- wire user_clk;
-
- FDRE UFC_EOF_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_EOF_N_Buffer_reg_0),
- .Q(UFC_EOF_N_Buffer),
- .R(1'b0));
- FDRE \UFC_REM_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_REM_Buffer_reg[0]_1 ),
- .Q(\UFC_REM_Buffer_reg[0]_0 ),
- .R(1'b0));
- FDSE UFC_SRC_RDY_N_Buffer_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(UFC_SRC_RDY_N_Buffer_reg_0),
- .Q(UFC_SRC_RDY_N_Buffer),
- .S(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_STORAGE_COUNT_CONTROL" *)
-module north_channel_north_channel_UFC_STORAGE_COUNT_CONTROL
- (stage_1_ufc_start_r_reg,
- Q,
- \storage_count_r_reg[1]_0 ,
- \storage_count_r_reg[1]_1 ,
- D,
- \storage_count_r_reg[0]_0 ,
- stage_1_ufc_start_r_reg_0,
- stage_1_ufc_start_r,
- UFC_EOF_N_Buffer_reg,
- RESET,
- user_clk);
- output stage_1_ufc_start_r_reg;
- output [1:0]Q;
- output \storage_count_r_reg[1]_0 ;
- output \storage_count_r_reg[1]_1 ;
- output [0:0]D;
- output \storage_count_r_reg[0]_0 ;
- output stage_1_ufc_start_r_reg_0;
- input stage_1_ufc_start_r;
- input [1:0]UFC_EOF_N_Buffer_reg;
- input RESET;
- input user_clk;
-
- wire [0:0]D;
- wire [1:0]Q;
- wire RESET;
- wire [1:0]UFC_EOF_N_Buffer_reg;
- wire stage_1_ufc_start_r;
- wire stage_1_ufc_start_r_reg;
- wire stage_1_ufc_start_r_reg_0;
- wire [0:1]storage_count_c;
- wire \storage_count_r_reg[0]_0 ;
- wire \storage_count_r_reg[1]_0 ;
- wire \storage_count_r_reg[1]_1 ;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair242" *)
- LUT5 #(
- .INIT(32'h55547733))
- UFC_EOF_N_Buffer_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[0]),
- .I2(UFC_EOF_N_Buffer_reg[0]),
- .I3(UFC_EOF_N_Buffer_reg[1]),
- .I4(Q[1]),
- .O(stage_1_ufc_start_r_reg));
- (* SOFT_HLUTNM = "soft_lutpair244" *)
- LUT4 #(
- .INIT(16'h6433))
- \UFC_REM_Buffer[0]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[0]),
- .I2(Q[1]),
- .I3(UFC_EOF_N_Buffer_reg[0]),
- .O(stage_1_ufc_start_r_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair245" *)
- LUT2 #(
- .INIT(4'h1))
- UFC_SRC_RDY_N_Buffer_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\storage_count_r_reg[0]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair244" *)
- LUT2 #(
- .INIT(4'h8))
- \UFC_STORAGE_SELECT_Buffer[0]_i_2
- (.I0(Q[0]),
- .I1(Q[1]),
- .O(\storage_count_r_reg[1]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair245" *)
- LUT2 #(
- .INIT(4'h9))
- \UFC_STORAGE_SELECT_Buffer[1]_i_1
- (.I0(Q[0]),
- .I1(Q[1]),
- .O(\storage_count_r_reg[1]_1 ));
- (* SOFT_HLUTNM = "soft_lutpair243" *)
- LUT4 #(
- .INIT(16'hABFF))
- \UFC_STORAGE_SELECT_Buffer[5]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[1]),
- .I2(UFC_EOF_N_Buffer_reg[1]),
- .I3(Q[0]),
- .O(D));
- (* SOFT_HLUTNM = "soft_lutpair243" *)
- LUT5 #(
- .INIT(32'h9CC8C8C8))
- \storage_count_r[0]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(UFC_EOF_N_Buffer_reg[1]),
- .I2(Q[1]),
- .I3(Q[0]),
- .I4(UFC_EOF_N_Buffer_reg[0]),
- .O(storage_count_c[0]));
- (* SOFT_HLUTNM = "soft_lutpair242" *)
- LUT5 #(
- .INIT(32'hAAFE5400))
- \storage_count_r[1]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(UFC_EOF_N_Buffer_reg[1]),
- .I2(Q[1]),
- .I3(Q[0]),
- .I4(UFC_EOF_N_Buffer_reg[0]),
- .O(storage_count_c[1]));
- FDRE \storage_count_r_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(storage_count_c[0]),
- .Q(Q[1]),
- .R(RESET));
- FDRE \storage_count_r_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(storage_count_c[1]),
- .Q(Q[0]),
- .R(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_STORAGE_MUX" *)
-module north_channel_north_channel_UFC_STORAGE_MUX
- (D,
- \MUXED_DATA_Buffer_reg[16]_0 ,
- \MUXED_DATA_Buffer_reg[17]_0 ,
- \MUXED_DATA_Buffer_reg[18]_0 ,
- \MUXED_DATA_Buffer_reg[19]_0 ,
- \MUXED_DATA_Buffer_reg[20]_0 ,
- \MUXED_DATA_Buffer_reg[21]_0 ,
- \MUXED_DATA_Buffer_reg[22]_0 ,
- \MUXED_DATA_Buffer_reg[23]_0 ,
- \MUXED_DATA_Buffer_reg[24]_0 ,
- \MUXED_DATA_Buffer_reg[25]_0 ,
- \MUXED_DATA_Buffer_reg[26]_0 ,
- \MUXED_DATA_Buffer_reg[27]_0 ,
- \MUXED_DATA_Buffer_reg[28]_0 ,
- \MUXED_DATA_Buffer_reg[29]_0 ,
- \MUXED_DATA_Buffer_reg[30]_0 ,
- \MUXED_DATA_Buffer_reg[31]_0 ,
- \MUXED_DATA_Buffer_reg[0]_0 ,
- user_clk,
- UFC_STORAGE_SELECT_Buffer,
- SHIFTED_DATA_Buffer);
- output [15:0]D;
- output \MUXED_DATA_Buffer_reg[16]_0 ;
- output \MUXED_DATA_Buffer_reg[17]_0 ;
- output \MUXED_DATA_Buffer_reg[18]_0 ;
- output \MUXED_DATA_Buffer_reg[19]_0 ;
- output \MUXED_DATA_Buffer_reg[20]_0 ;
- output \MUXED_DATA_Buffer_reg[21]_0 ;
- output \MUXED_DATA_Buffer_reg[22]_0 ;
- output \MUXED_DATA_Buffer_reg[23]_0 ;
- output \MUXED_DATA_Buffer_reg[24]_0 ;
- output \MUXED_DATA_Buffer_reg[25]_0 ;
- output \MUXED_DATA_Buffer_reg[26]_0 ;
- output \MUXED_DATA_Buffer_reg[27]_0 ;
- output \MUXED_DATA_Buffer_reg[28]_0 ;
- output \MUXED_DATA_Buffer_reg[29]_0 ;
- output \MUXED_DATA_Buffer_reg[30]_0 ;
- output \MUXED_DATA_Buffer_reg[31]_0 ;
- input \MUXED_DATA_Buffer_reg[0]_0 ;
- input user_clk;
- input [2:0]UFC_STORAGE_SELECT_Buffer;
- input [0:31]SHIFTED_DATA_Buffer;
-
- wire [15:0]D;
- wire \MUXED_DATA_Buffer[0]_i_2_n_0 ;
- wire \MUXED_DATA_Buffer[10]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[11]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[12]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[13]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[14]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[15]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[16]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[17]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[18]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[19]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[1]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[20]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[21]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[22]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[23]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[24]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[25]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[26]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[27]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[28]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[29]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[2]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[30]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[31]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[3]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[4]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[5]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[6]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[7]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[8]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer[9]_i_1_n_0 ;
- wire \MUXED_DATA_Buffer_reg[0]_0 ;
- wire \MUXED_DATA_Buffer_reg[16]_0 ;
- wire \MUXED_DATA_Buffer_reg[17]_0 ;
- wire \MUXED_DATA_Buffer_reg[18]_0 ;
- wire \MUXED_DATA_Buffer_reg[19]_0 ;
- wire \MUXED_DATA_Buffer_reg[20]_0 ;
- wire \MUXED_DATA_Buffer_reg[21]_0 ;
- wire \MUXED_DATA_Buffer_reg[22]_0 ;
- wire \MUXED_DATA_Buffer_reg[23]_0 ;
- wire \MUXED_DATA_Buffer_reg[24]_0 ;
- wire \MUXED_DATA_Buffer_reg[25]_0 ;
- wire \MUXED_DATA_Buffer_reg[26]_0 ;
- wire \MUXED_DATA_Buffer_reg[27]_0 ;
- wire \MUXED_DATA_Buffer_reg[28]_0 ;
- wire \MUXED_DATA_Buffer_reg[29]_0 ;
- wire \MUXED_DATA_Buffer_reg[30]_0 ;
- wire \MUXED_DATA_Buffer_reg[31]_0 ;
- wire [0:31]SHIFTED_DATA_Buffer;
- wire [2:0]UFC_STORAGE_SELECT_Buffer;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair261" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[0]_i_2
- (.I0(SHIFTED_DATA_Buffer[16]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[0]),
- .O(\MUXED_DATA_Buffer[0]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair256" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[10]_i_1
- (.I0(SHIFTED_DATA_Buffer[26]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[10]),
- .O(\MUXED_DATA_Buffer[10]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair256" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[11]_i_1
- (.I0(SHIFTED_DATA_Buffer[27]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[11]),
- .O(\MUXED_DATA_Buffer[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair255" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[12]_i_1
- (.I0(SHIFTED_DATA_Buffer[28]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[12]),
- .O(\MUXED_DATA_Buffer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair255" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[13]_i_1
- (.I0(SHIFTED_DATA_Buffer[29]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[13]),
- .O(\MUXED_DATA_Buffer[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair254" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[14]_i_1
- (.I0(SHIFTED_DATA_Buffer[30]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[14]),
- .O(\MUXED_DATA_Buffer[14]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair254" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[15]_i_1
- (.I0(SHIFTED_DATA_Buffer[31]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[15]),
- .O(\MUXED_DATA_Buffer[15]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair253" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[16]_i_1
- (.I0(SHIFTED_DATA_Buffer[16]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[0]),
- .O(\MUXED_DATA_Buffer[16]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair253" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[17]_i_1
- (.I0(SHIFTED_DATA_Buffer[17]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[1]),
- .O(\MUXED_DATA_Buffer[17]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair252" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[18]_i_1
- (.I0(SHIFTED_DATA_Buffer[18]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[2]),
- .O(\MUXED_DATA_Buffer[18]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair252" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[19]_i_1
- (.I0(SHIFTED_DATA_Buffer[19]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[3]),
- .O(\MUXED_DATA_Buffer[19]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair261" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[1]_i_1
- (.I0(SHIFTED_DATA_Buffer[17]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[1]),
- .O(\MUXED_DATA_Buffer[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair251" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[20]_i_1
- (.I0(SHIFTED_DATA_Buffer[20]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[4]),
- .O(\MUXED_DATA_Buffer[20]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair251" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[21]_i_1
- (.I0(SHIFTED_DATA_Buffer[21]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[5]),
- .O(\MUXED_DATA_Buffer[21]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair250" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[22]_i_1
- (.I0(SHIFTED_DATA_Buffer[22]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[6]),
- .O(\MUXED_DATA_Buffer[22]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair250" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[23]_i_1
- (.I0(SHIFTED_DATA_Buffer[23]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[7]),
- .O(\MUXED_DATA_Buffer[23]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair249" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[24]_i_1
- (.I0(SHIFTED_DATA_Buffer[24]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[8]),
- .O(\MUXED_DATA_Buffer[24]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair249" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[25]_i_1
- (.I0(SHIFTED_DATA_Buffer[25]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[9]),
- .O(\MUXED_DATA_Buffer[25]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair248" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[26]_i_1
- (.I0(SHIFTED_DATA_Buffer[26]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[10]),
- .O(\MUXED_DATA_Buffer[26]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair248" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[27]_i_1
- (.I0(SHIFTED_DATA_Buffer[27]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[11]),
- .O(\MUXED_DATA_Buffer[27]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair247" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[28]_i_1
- (.I0(SHIFTED_DATA_Buffer[28]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[12]),
- .O(\MUXED_DATA_Buffer[28]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair247" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[29]_i_1
- (.I0(SHIFTED_DATA_Buffer[29]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[13]),
- .O(\MUXED_DATA_Buffer[29]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair260" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[2]_i_1
- (.I0(SHIFTED_DATA_Buffer[18]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[2]),
- .O(\MUXED_DATA_Buffer[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair246" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[30]_i_1
- (.I0(SHIFTED_DATA_Buffer[30]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[14]),
- .O(\MUXED_DATA_Buffer[30]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair246" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[31]_i_1
- (.I0(SHIFTED_DATA_Buffer[31]),
- .I1(UFC_STORAGE_SELECT_Buffer[0]),
- .I2(SHIFTED_DATA_Buffer[15]),
- .O(\MUXED_DATA_Buffer[31]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair260" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[3]_i_1
- (.I0(SHIFTED_DATA_Buffer[19]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[3]),
- .O(\MUXED_DATA_Buffer[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair259" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[4]_i_1
- (.I0(SHIFTED_DATA_Buffer[20]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[4]),
- .O(\MUXED_DATA_Buffer[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair259" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[5]_i_1
- (.I0(SHIFTED_DATA_Buffer[21]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[5]),
- .O(\MUXED_DATA_Buffer[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair258" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[6]_i_1
- (.I0(SHIFTED_DATA_Buffer[22]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[6]),
- .O(\MUXED_DATA_Buffer[6]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair258" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[7]_i_1
- (.I0(SHIFTED_DATA_Buffer[23]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[7]),
- .O(\MUXED_DATA_Buffer[7]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair257" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[8]_i_1
- (.I0(SHIFTED_DATA_Buffer[24]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[8]),
- .O(\MUXED_DATA_Buffer[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair257" *)
- LUT3 #(
- .INIT(8'hB8))
- \MUXED_DATA_Buffer[9]_i_1
- (.I0(SHIFTED_DATA_Buffer[25]),
- .I1(UFC_STORAGE_SELECT_Buffer[2]),
- .I2(SHIFTED_DATA_Buffer[9]),
- .O(\MUXED_DATA_Buffer[9]_i_1_n_0 ));
- FDRE \MUXED_DATA_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[0]_i_2_n_0 ),
- .Q(D[15]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[10]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[10]_i_1_n_0 ),
- .Q(D[5]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[11]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[11]_i_1_n_0 ),
- .Q(D[4]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[12]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[12]_i_1_n_0 ),
- .Q(D[3]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[13]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[13]_i_1_n_0 ),
- .Q(D[2]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[14]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[14]_i_1_n_0 ),
- .Q(D[1]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[15]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[15]_i_1_n_0 ),
- .Q(D[0]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[16]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[16]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[16]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[17]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[17]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[17]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[18]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[18]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[18]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[19]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[19]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[19]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[1]_i_1_n_0 ),
- .Q(D[14]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[20]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[20]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[20]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[21]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[21]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[21]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[22]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[22]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[22]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[23]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[23]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[23]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[24]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[24]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[24]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[25]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[25]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[25]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[26]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[26]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[26]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[27]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[27]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[27]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[28]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[28]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[28]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[29]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[29]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[29]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[2]_i_1_n_0 ),
- .Q(D[13]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[30]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[30]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[30]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[31]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[31]_i_1_n_0 ),
- .Q(\MUXED_DATA_Buffer_reg[31]_0 ),
- .R(UFC_STORAGE_SELECT_Buffer[1]));
- FDRE \MUXED_DATA_Buffer_reg[3]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[3]_i_1_n_0 ),
- .Q(D[12]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[4]_i_1_n_0 ),
- .Q(D[11]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[5]_i_1_n_0 ),
- .Q(D[10]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[6]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[6]_i_1_n_0 ),
- .Q(D[9]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[7]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[7]_i_1_n_0 ),
- .Q(D[8]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[8]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[8]_i_1_n_0 ),
- .Q(D[7]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
- FDRE \MUXED_DATA_Buffer_reg[9]
- (.C(user_clk),
- .CE(1'b1),
- .D(\MUXED_DATA_Buffer[9]_i_1_n_0 ),
- .Q(D[6]),
- .R(\MUXED_DATA_Buffer_reg[0]_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_UFC_STORAGE_SWITCH_CONTROL" *)
-module north_channel_north_channel_UFC_STORAGE_SWITCH_CONTROL
- (\UFC_STORAGE_SELECT_Buffer_reg[0]_0 ,
- \UFC_STORAGE_SELECT_Buffer_reg[2]_0 ,
- D,
- user_clk,
- \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ,
- \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ,
- Q,
- \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ,
- stage_1_ufc_start_r,
- \UFC_STORAGE_SELECT_Buffer_reg[4]_1 );
- output \UFC_STORAGE_SELECT_Buffer_reg[0]_0 ;
- output [2:0]\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ;
- input [0:0]D;
- input user_clk;
- input \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ;
- input \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
- input [1:0]Q;
- input \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ;
- input stage_1_ufc_start_r;
- input [1:0]\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ;
-
- wire [0:0]D;
- wire [1:0]Q;
- wire [0:1]UFC_STORAGE_SELECT_Buffer;
- wire \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[0]_0 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
- wire [2:0]\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ;
- wire \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ;
- wire [1:0]\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ;
- wire stage_1_ufc_start_r;
- wire user_clk;
-
- LUT2 #(
- .INIT(4'hE))
- \MUXED_DATA_Buffer[0]_i_1
- (.I0(UFC_STORAGE_SELECT_Buffer[0]),
- .I1(UFC_STORAGE_SELECT_Buffer[1]),
- .O(\UFC_STORAGE_SELECT_Buffer_reg[0]_0 ));
- LUT5 #(
- .INIT(32'hABABABBF))
- \UFC_STORAGE_SELECT_Buffer[0]_i_1
- (.I0(stage_1_ufc_start_r),
- .I1(Q[1]),
- .I2(\UFC_STORAGE_SELECT_Buffer_reg[4]_1 [1]),
- .I3(\UFC_STORAGE_SELECT_Buffer_reg[4]_1 [0]),
- .I4(Q[0]),
- .O(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_STORAGE_SELECT_Buffer_reg[0]_1 ),
- .Q(UFC_STORAGE_SELECT_Buffer[0]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_STORAGE_SELECT_Buffer_reg[1]_0 ),
- .Q(UFC_STORAGE_SELECT_Buffer[1]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[2]
- (.C(user_clk),
- .CE(1'b1),
- .D(Q[0]),
- .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [2]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[4]
- (.C(user_clk),
- .CE(1'b1),
- .D(\UFC_STORAGE_SELECT_Buffer_reg[4]_0 ),
- .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [1]),
- .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
- FDRE \UFC_STORAGE_SELECT_Buffer_reg[5]
- (.C(user_clk),
- .CE(1'b1),
- .D(D),
- .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [0]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_VALID_DATA_COUNTER" *)
-module north_channel_north_channel_VALID_DATA_COUNTER
- (\COUNT_Buffer_reg[0]_0 ,
- Q,
- RESET,
- user_clk);
- output [1:0]\COUNT_Buffer_reg[0]_0 ;
- input [1:0]Q;
- input RESET;
- input user_clk;
-
- wire \COUNT_Buffer[0]_i_1_n_0 ;
- wire \COUNT_Buffer[1]_i_1_n_0 ;
- wire [1:0]\COUNT_Buffer_reg[0]_0 ;
- wire [1:0]Q;
- wire RESET;
- wire user_clk;
-
- (* SOFT_HLUTNM = "soft_lutpair262" *)
- LUT2 #(
- .INIT(4'h8))
- \COUNT_Buffer[0]_i_1
- (.I0(Q[0]),
- .I1(Q[1]),
- .O(\COUNT_Buffer[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair262" *)
- LUT2 #(
- .INIT(4'h6))
- \COUNT_Buffer[1]_i_1
- (.I0(Q[1]),
- .I1(Q[0]),
- .O(\COUNT_Buffer[1]_i_1_n_0 ));
- FDRE \COUNT_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer[0]_i_1_n_0 ),
- .Q(\COUNT_Buffer_reg[0]_0 [1]),
- .R(RESET));
- FDRE \COUNT_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer[1]_i_1_n_0 ),
- .Q(\COUNT_Buffer_reg[0]_0 [0]),
- .R(RESET));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_VALID_DATA_COUNTER" *)
-module north_channel_north_channel_VALID_DATA_COUNTER_1
- (D,
- Q,
- end_storage_r_reg,
- end_storage_r0,
- std_bool2_in,
- std_bool6_in,
- \STORAGE_CE_Buffer_reg[0] ,
- stage_3_end_storage_r,
- stage_2_start_with_data_r,
- stage_2_end_before_start_r,
- stage_2_end_after_start_r,
- RESET,
- \COUNT_Buffer_reg[0]_0 ,
- user_clk);
- output [1:0]D;
- output [0:0]Q;
- output [0:0]end_storage_r_reg;
- output end_storage_r0;
- output std_bool2_in;
- output std_bool6_in;
- input [1:0]\STORAGE_CE_Buffer_reg[0] ;
- input stage_3_end_storage_r;
- input stage_2_start_with_data_r;
- input stage_2_end_before_start_r;
- input stage_2_end_after_start_r;
- input RESET;
- input [1:0]\COUNT_Buffer_reg[0]_0 ;
- input user_clk;
-
- wire [1:0]\COUNT_Buffer_reg[0]_0 ;
- wire [1:0]D;
- wire [0:0]Q;
- wire RESET;
- wire [1:0]\STORAGE_CE_Buffer_reg[0] ;
- wire end_storage_r0;
- wire [0:0]end_storage_r_reg;
- wire [0:0]stage_2_data_v_count_r;
- wire stage_2_end_after_start_r;
- wire stage_2_end_before_start_r;
- wire stage_2_start_with_data_r;
- wire stage_3_end_storage_r;
- wire std_bool2_in;
- wire std_bool6_in;
- wire user_clk;
-
- FDRE \COUNT_Buffer_reg[0]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer_reg[0]_0 [1]),
- .Q(stage_2_data_v_count_r),
- .R(RESET));
- FDRE \COUNT_Buffer_reg[1]
- (.C(user_clk),
- .CE(1'b1),
- .D(\COUNT_Buffer_reg[0]_0 [0]),
- .Q(Q),
- .R(RESET));
- (* SOFT_HLUTNM = "soft_lutpair199" *)
- LUT4 #(
- .INIT(16'hFEE0))
- SRC_RDY_N_Buffer_i_3
- (.I0(Q),
- .I1(\STORAGE_CE_Buffer_reg[0] [0]),
- .I2(\STORAGE_CE_Buffer_reg[0] [1]),
- .I3(stage_2_data_v_count_r),
- .O(std_bool6_in));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFAEF))
- \STORAGE_CE_Buffer[0]_i_1
- (.I0(stage_2_data_v_count_r),
- .I1(Q),
- .I2(\STORAGE_CE_Buffer_reg[0] [1]),
- .I3(\STORAGE_CE_Buffer_reg[0] [0]),
- .I4(stage_3_end_storage_r),
- .I5(stage_2_start_with_data_r),
- .O(D[1]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFEFF))
- \STORAGE_CE_Buffer[1]_i_1
- (.I0(stage_2_data_v_count_r),
- .I1(\STORAGE_CE_Buffer_reg[0] [0]),
- .I2(Q),
- .I3(\STORAGE_CE_Buffer_reg[0] [1]),
- .I4(stage_3_end_storage_r),
- .I5(stage_2_start_with_data_r),
- .O(D[0]));
- LUT4 #(
- .INIT(16'hF404))
- end_storage_r_i_1
- (.I0(std_bool2_in),
- .I1(stage_2_end_before_start_r),
- .I2(stage_2_start_with_data_r),
- .I3(stage_2_end_after_start_r),
- .O(end_storage_r0));
- (* SOFT_HLUTNM = "soft_lutpair199" *)
- LUT4 #(
- .INIT(16'h0001))
- end_storage_r_i_2
- (.I0(Q),
- .I1(\STORAGE_CE_Buffer_reg[0] [0]),
- .I2(\STORAGE_CE_Buffer_reg[0] [1]),
- .I3(stage_2_data_v_count_r),
- .O(std_bool2_in));
- LUT6 #(
- .INIT(64'hEFFFFEEF10011000))
- \storage_count_r[0]_i_1
- (.I0(stage_3_end_storage_r),
- .I1(stage_2_start_with_data_r),
- .I2(Q),
- .I3(\STORAGE_CE_Buffer_reg[0] [0]),
- .I4(\STORAGE_CE_Buffer_reg[0] [1]),
- .I5(stage_2_data_v_count_r),
- .O(end_storage_r_reg));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync
- (out,
- RESET,
- user_clk);
- output out;
- input RESET;
- input user_clk;
-
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- assign p_level_in_int = RESET;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync_24
- (out,
- user_clk);
- output out;
- input user_clk;
-
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync_28
- (out,
- PLL_NOT_LOCKED,
- user_clk);
- output out;
- input PLL_NOT_LOCKED;
- input user_clk;
-
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- assign p_level_in_int = PLL_NOT_LOCKED;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1
- (AR,
- GT_RESET,
- init_clk_in);
- output [0:0]AR;
- input GT_RESET;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign AR[0] = s_level_out_d6;
- assign p_level_in_int = GT_RESET;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_0
- (HPCNT_RESET,
- RESET,
- init_clk_in,
- AR);
- output HPCNT_RESET;
- input RESET;
- input init_clk_in;
- input [0:0]AR;
-
- wire [0:0]AR;
- wire HPCNT_RESET;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign p_level_in_int = RESET;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- \hotplug_count_synth.count_for_reset_r[0]_i_2
- (.I0(s_level_out_d6),
- .I1(AR),
- .O(HPCNT_RESET));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_10
- (init_clk_in);
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b1),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_12
- (SR,
- mmcm_lock_reclocked_reg,
- init_clk_in,
- PLL_NOT_LOCKED,
- mmcm_lock_reclocked,
- mmcm_lock_reclocked_reg_0);
- output [0:0]SR;
- output mmcm_lock_reclocked_reg;
- input init_clk_in;
- input PLL_NOT_LOCKED;
- input mmcm_lock_reclocked;
- input mmcm_lock_reclocked_reg_0;
-
- wire PLL_NOT_LOCKED;
- wire [0:0]SR;
- wire init_clk_in;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_reg;
- wire mmcm_lock_reclocked_reg_0;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[9]_i_1
- (.I0(s_level_out_d6),
- .O(SR));
- LUT3 #(
- .INIT(8'hE0))
- mmcm_lock_reclocked_i_1
- (.I0(mmcm_lock_reclocked),
- .I1(mmcm_lock_reclocked_reg_0),
- .I2(s_level_out_d6),
- .O(mmcm_lock_reclocked_reg));
- LUT1 #(
- .INIT(2'h1))
- p_level_in_int_inferred_i_1
- (.I0(PLL_NOT_LOCKED),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_16
- (E,
- reset_time_out_reg,
- quad1_common_lock_in,
- init_clk_in,
- Q,
- reset_time_out_reg_0,
- \FSM_sequential_rx_state_reg[0] ,
- \FSM_sequential_rx_state_reg[0]_0 ,
- \FSM_sequential_rx_state_reg[0]_1 ,
- \FSM_sequential_rx_state_reg[0]_2 ,
- \FSM_sequential_rx_state_reg[0]_3 ,
- reset_time_out_reg_1,
- check_tlock_max,
- reset_time_out_reg_2,
- reset_time_out_reg_3,
- reset_time_out_reg_4);
- output [0:0]E;
- output reset_time_out_reg;
- input quad1_common_lock_in;
- input init_clk_in;
- input [3:0]Q;
- input reset_time_out_reg_0;
- input \FSM_sequential_rx_state_reg[0] ;
- input \FSM_sequential_rx_state_reg[0]_0 ;
- input [0:0]\FSM_sequential_rx_state_reg[0]_1 ;
- input \FSM_sequential_rx_state_reg[0]_2 ;
- input \FSM_sequential_rx_state_reg[0]_3 ;
- input reset_time_out_reg_1;
- input check_tlock_max;
- input reset_time_out_reg_2;
- input reset_time_out_reg_3;
- input reset_time_out_reg_4;
-
- wire [0:0]E;
- wire \FSM_sequential_rx_state[3]_i_5_n_0 ;
- wire \FSM_sequential_rx_state_reg[0] ;
- wire \FSM_sequential_rx_state_reg[0]_0 ;
- wire [0:0]\FSM_sequential_rx_state_reg[0]_1 ;
- wire \FSM_sequential_rx_state_reg[0]_2 ;
- wire \FSM_sequential_rx_state_reg[0]_3 ;
- wire [3:0]Q;
- wire check_tlock_max;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire reset_time_out_i_5_n_0;
- wire reset_time_out_reg;
- wire reset_time_out_reg_0;
- wire reset_time_out_reg_1;
- wire reset_time_out_reg_2;
- wire reset_time_out_reg_3;
- wire reset_time_out_reg_4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign p_level_in_int = quad1_common_lock_in;
- LUT6 #(
- .INIT(64'hAAABBBBBAAABAAAB))
- \FSM_sequential_rx_state[3]_i_1
- (.I0(\FSM_sequential_rx_state_reg[0] ),
- .I1(\FSM_sequential_rx_state_reg[0]_0 ),
- .I2(\FSM_sequential_rx_state_reg[0]_1 ),
- .I3(Q[0]),
- .I4(\FSM_sequential_rx_state[3]_i_5_n_0 ),
- .I5(\FSM_sequential_rx_state_reg[0]_2 ),
- .O(E));
- LUT6 #(
- .INIT(64'h5500550055005700))
- \FSM_sequential_rx_state[3]_i_5
- (.I0(Q[0]),
- .I1(\FSM_sequential_rx_state_reg[0]_3 ),
- .I2(s_level_out_d6),
- .I3(Q[1]),
- .I4(Q[3]),
- .I5(Q[2]),
- .O(\FSM_sequential_rx_state[3]_i_5_n_0 ));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT6 #(
- .INIT(64'hFF40FFFFFF400000))
- reset_time_out_i_1__0
- (.I0(reset_time_out_reg_1),
- .I1(check_tlock_max),
- .I2(reset_time_out_reg_2),
- .I3(reset_time_out_i_5_n_0),
- .I4(reset_time_out_reg_3),
- .I5(reset_time_out_reg_4),
- .O(reset_time_out_reg));
- LUT6 #(
- .INIT(64'h10DD10DDDC11DCDD))
- reset_time_out_i_5
- (.I0(Q[2]),
- .I1(Q[3]),
- .I2(s_level_out_d6),
- .I3(Q[1]),
- .I4(Q[0]),
- .I5(reset_time_out_reg_0),
- .O(reset_time_out_i_5_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_17
- (init_clk_in);
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b1),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_19
- (SR,
- mmcm_lock_reclocked_reg,
- init_clk_in,
- mmcm_lock_reclocked,
- mmcm_lock_reclocked_reg_0);
- output [0:0]SR;
- output mmcm_lock_reclocked_reg;
- input init_clk_in;
- input mmcm_lock_reclocked;
- input mmcm_lock_reclocked_reg_0;
-
- wire [0:0]SR;
- wire init_clk_in;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_reg;
- wire mmcm_lock_reclocked_reg_0;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b1),
- .O(p_level_in_int));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[9]_i_1__0
- (.I0(s_level_out_d6),
- .O(SR));
- LUT3 #(
- .INIT(8'hE0))
- mmcm_lock_reclocked_i_1__0
- (.I0(mmcm_lock_reclocked),
- .I1(mmcm_lock_reclocked_reg_0),
- .I2(s_level_out_d6),
- .O(mmcm_lock_reclocked_reg));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_8
- (out,
- in0,
- drpclk_in);
- output out;
- input in0;
- input drpclk_in;
-
- wire drpclk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign out = s_level_out_d6;
- assign p_level_in_int = in0;
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized1_9
- (E,
- \FSM_sequential_tx_state_reg[0] ,
- quad1_common_lock_in,
- init_clk_in,
- \FSM_sequential_tx_state_reg[0]_0 ,
- reset_time_out_reg,
- \FSM_sequential_tx_state_reg[0]_1 ,
- Q,
- \FSM_sequential_tx_state_reg[3]_i_5_0 ,
- reset_time_out,
- mmcm_lock_reclocked,
- \FSM_sequential_tx_state_reg[3]_i_5_1 ,
- txresetdone_s3,
- \FSM_sequential_tx_state_reg[3]_i_5_2 ,
- \FSM_sequential_tx_state_reg[3]_i_5_3 ,
- reset_time_out_reg_0);
- output [0:0]E;
- output \FSM_sequential_tx_state_reg[0] ;
- input quad1_common_lock_in;
- input init_clk_in;
- input \FSM_sequential_tx_state_reg[0]_0 ;
- input reset_time_out_reg;
- input \FSM_sequential_tx_state_reg[0]_1 ;
- input [3:0]Q;
- input \FSM_sequential_tx_state_reg[3]_i_5_0 ;
- input reset_time_out;
- input mmcm_lock_reclocked;
- input \FSM_sequential_tx_state_reg[3]_i_5_1 ;
- input txresetdone_s3;
- input \FSM_sequential_tx_state_reg[3]_i_5_2 ;
- input \FSM_sequential_tx_state_reg[3]_i_5_3 ;
- input reset_time_out_reg_0;
-
- wire [0:0]E;
- wire \FSM_sequential_tx_state[3]_i_7_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_8_n_0 ;
- wire \FSM_sequential_tx_state_reg[0] ;
- wire \FSM_sequential_tx_state_reg[0]_0 ;
- wire \FSM_sequential_tx_state_reg[0]_1 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_0 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_1 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_2 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_3 ;
- wire \FSM_sequential_tx_state_reg[3]_i_5_n_0 ;
- wire [3:0]Q;
- wire init_clk_in;
- wire mmcm_lock_reclocked;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire reset_time_out;
- wire reset_time_out_i_2_n_0;
- wire reset_time_out_i_3_n_0;
- wire reset_time_out_reg;
- wire reset_time_out_reg_0;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire txresetdone_s3;
-
- assign p_level_in_int = quad1_common_lock_in;
- LUT6 #(
- .INIT(64'h000000FFCCCCB8B8))
- \FSM_sequential_tx_state[3]_i_1
- (.I0(\FSM_sequential_tx_state_reg[0]_0 ),
- .I1(reset_time_out_reg),
- .I2(\FSM_sequential_tx_state_reg[0]_1 ),
- .I3(\FSM_sequential_tx_state_reg[3]_i_5_n_0 ),
- .I4(Q[3]),
- .I5(Q[0]),
- .O(E));
- LUT6 #(
- .INIT(64'h0DFF0D000DFF0DFF))
- \FSM_sequential_tx_state[3]_i_7
- (.I0(\FSM_sequential_tx_state_reg[3]_i_5_0 ),
- .I1(reset_time_out),
- .I2(mmcm_lock_reclocked),
- .I3(Q[2]),
- .I4(s_level_out_d6),
- .I5(\FSM_sequential_tx_state_reg[3]_i_5_1 ),
- .O(\FSM_sequential_tx_state[3]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h45004500450045FF))
- \FSM_sequential_tx_state[3]_i_8
- (.I0(txresetdone_s3),
- .I1(reset_time_out),
- .I2(\FSM_sequential_tx_state_reg[3]_i_5_2 ),
- .I3(Q[2]),
- .I4(s_level_out_d6),
- .I5(\FSM_sequential_tx_state_reg[3]_i_5_3 ),
- .O(\FSM_sequential_tx_state[3]_i_8_n_0 ));
- MUXF7 \FSM_sequential_tx_state_reg[3]_i_5
- (.I0(\FSM_sequential_tx_state[3]_i_7_n_0 ),
- .I1(\FSM_sequential_tx_state[3]_i_8_n_0 ),
- .O(\FSM_sequential_tx_state_reg[3]_i_5_n_0 ),
- .S(Q[1]));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(p_level_in_d1_cdc_from));
- LUT6 #(
- .INIT(64'h8F80FFFF8F800000))
- reset_time_out_i_1
- (.I0(reset_time_out_reg),
- .I1(Q[0]),
- .I2(Q[3]),
- .I3(reset_time_out_i_2_n_0),
- .I4(reset_time_out_i_3_n_0),
- .I5(reset_time_out),
- .O(\FSM_sequential_tx_state_reg[0] ));
- LUT5 #(
- .INIT(32'hFFFF8A80))
- reset_time_out_i_2
- (.I0(Q[1]),
- .I1(txresetdone_s3),
- .I2(Q[2]),
- .I3(s_level_out_d6),
- .I4(reset_time_out_reg_0),
- .O(reset_time_out_i_2_n_0));
- LUT6 #(
- .INIT(64'h22202F2F22202E2E))
- reset_time_out_i_3
- (.I0(Q[0]),
- .I1(Q[3]),
- .I2(Q[2]),
- .I3(s_level_out_d6),
- .I4(Q[1]),
- .I5(\FSM_sequential_tx_state_reg[0]_0 ),
- .O(reset_time_out_i_3_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3
- (out,
- run_phase_alignment_int,
- init_clk_in,
- user_clk);
- output out;
- input run_phase_alignment_int;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire run_phase_alignment_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(run_phase_alignment_int),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3_14
- (out,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ,
- tx_fsm_reset_done_int,
- init_clk_in,
- user_clk);
- output out;
- output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ;
- input tx_fsm_reset_done_int;
- input init_clk_in;
- input user_clk;
-
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire tx_fsm_reset_done_int;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_fsm_reset_done_int),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- gt_txresetdone_r_i_1
- (.I0(s_level_out_d5),
- .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 ));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3_15
- (out,
- gtrxreset_i,
- init_clk_in,
- user_clk);
- output out;
- input gtrxreset_i;
- input init_clk_in;
- input user_clk;
-
- wire gtrxreset_i;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_i),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3_20
- (init_clk_in,
- user_clk);
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(1'b0),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3_21
- (out,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ,
- init_clk_in,
- user_clk);
- output out;
- input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- input init_clk_in;
- input user_clk;
-
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3_22
- (out,
- rx_fsm_reset_done_int,
- init_clk_in,
- user_clk);
- output out;
- input rx_fsm_reset_done_int;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rx_fsm_reset_done_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rx_fsm_reset_done_int),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3_27
- (out,
- link_reset_r,
- init_clk_in,
- user_clk);
- output out;
- input link_reset_r;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- wire link_reset_r;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(link_reset_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized3_29
- (out,
- tx_lock_comb_r,
- init_clk_in,
- user_clk);
- output out;
- input tx_lock_comb_r;
- input init_clk_in;
- input user_clk;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire tx_lock_comb_r;
- wire user_clk;
-
- assign out = s_level_out_d5;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_lock_comb_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6
- (O,
- \hotplug_count_synth.count_for_reset_r_reg[7] ,
- \hotplug_count_synth.count_for_reset_r_reg[11] ,
- \hotplug_count_synth.count_for_reset_r_reg[15] ,
- \hotplug_count_synth.count_for_reset_r_reg[19] ,
- \hotplug_count_synth.count_for_reset_r_reg[21] ,
- rx_cc_extend_r2,
- user_clk,
- init_clk_in,
- \hotplug_count_synth.count_for_reset_r_reg );
- output [3:0]O;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
- output [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
- output [1:0]\hotplug_count_synth.count_for_reset_r_reg[21] ;
- input rx_cc_extend_r2;
- input user_clk;
- input init_clk_in;
- input [21:0]\hotplug_count_synth.count_for_reset_r_reg ;
-
- wire [3:0]O;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ;
- wire [21:0]\hotplug_count_synth.count_for_reset_r_reg ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 ;
- wire [1:0]\hotplug_count_synth.count_for_reset_r_reg[21] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 ;
- wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ;
- wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rx_cc_extend_r2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
- wire [3:1]\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_CO_UNCONNECTED ;
- wire [3:2]\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_O_UNCONNECTED ;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rx_cc_extend_r2),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[0]_i_6
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [1]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h1))
- \hotplug_count_synth.count_for_reset_r[0]_i_7
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [15]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [14]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [13]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[12]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [12]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [19]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [18]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [17]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[16]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[20]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [21]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[20]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [20]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [5]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[4]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [4]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_2
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [11]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_3
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_4
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [9]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \hotplug_count_synth.count_for_reset_r[8]_i_5
- (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
- .I1(s_level_out_d6),
- .O(\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[0]_i_1
- (.CI(1'b0),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 }),
- .O(O),
- .S({\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[12]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[15] ),
- .S({\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[16]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[19] ),
- .S({\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[20]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ),
- .CO({\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_CO_UNCONNECTED [3:1],\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_hotplug_count_synth.count_for_reset_r_reg[20]_i_1_O_UNCONNECTED [3:2],\hotplug_count_synth.count_for_reset_r_reg[21] }),
- .S({1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[4]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[7] ),
- .S({\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 }));
- CARRY4 \hotplug_count_synth.count_for_reset_r_reg[8]_i_1
- (.CI(\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ),
- .CO({\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(\hotplug_count_synth.count_for_reset_r_reg[11] ),
- .S({\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 }));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_11
- (out,
- txfsm_txresetdone_r,
- user_clk,
- init_clk_in);
- output out;
- input txfsm_txresetdone_r;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire txfsm_txresetdone_r;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(txfsm_txresetdone_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_13
- (out,
- time_out_wait_bypass,
- user_clk,
- init_clk_in);
- output out;
- input time_out_wait_bypass;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire time_out_wait_bypass;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(time_out_wait_bypass),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_18
- (out,
- rxfsm_rxresetdone_r,
- user_clk,
- init_clk_in);
- output out;
- input rxfsm_rxresetdone_r;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rxfsm_rxresetdone_r;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxfsm_rxresetdone_r),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_23
- (rxpmaresetdone_i,
- user_clk,
- init_clk_in);
- input rxpmaresetdone_i;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- wire rxpmaresetdone_i;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(rxpmaresetdone_i),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_25
- (out,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ,
- user_clk,
- init_clk_in);
- output out;
- input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- input user_clk;
- input init_clk_in;
-
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 ),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_26
- (txpmaresetdone_i,
- user_clk,
- init_clk_in);
- input txpmaresetdone_i;
- input user_clk;
- input init_clk_in;
-
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire txpmaresetdone_i;
- wire user_clk;
-
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(txpmaresetdone_i),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_5
- (out,
- GTRXRESET_OUT,
- user_clk,
- init_clk_in);
- output out;
- input GTRXRESET_OUT;
- input user_clk;
- input init_clk_in;
-
- wire GTRXRESET_OUT;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
- wire user_clk;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(GTRXRESET_OUT),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_6
- (out,
- SR,
- init_clk_in,
- drpclk_in);
- output out;
- input [0:0]SR;
- input init_clk_in;
- input drpclk_in;
-
- wire [0:0]SR;
- wire drpclk_in;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign out = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(SR),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_cdc_sync" *)
-module north_channel_north_channel_cdc_sync__parameterized6_7
- (AR,
- gt_common_reset_out,
- init_clk_in,
- drpclk_in);
- output [0:0]AR;
- input gt_common_reset_out;
- input init_clk_in;
- input drpclk_in;
-
- wire drpclk_in;
- wire gt_common_reset_out;
- wire init_clk_in;
- (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
- wire p_level_in_int;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_north_channel_cdc_to;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
- (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
-
- assign AR[0] = s_level_out_d6;
- (* KEEP = "yes" *)
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gt_common_reset_out),
- .Q(p_level_in_d1_cdc_from),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_north_channel_cdc_to_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(p_level_in_int),
- .Q(s_level_out_d1_north_channel_cdc_to),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d1_north_channel_cdc_to),
- .Q(s_level_out_d2),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d2),
- .Q(s_level_out_d3),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d3),
- .Q(s_level_out_d4),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d4),
- .Q(s_level_out_d5),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- (* shift_extract = "no" *)
- FDRE #(
- .INIT(1'b0))
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(s_level_out_d5),
- .Q(s_level_out_d6),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h2))
- p_level_in_d1_cdc_from_inst
- (.I0(p_level_in_d1_cdc_from),
- .O(p_level_in_int));
-endmodule
-
-(* CC_FREQ_FACTOR = "12" *) (* EXAMPLE_SIMULATION = "0" *) (* ORIG_REF_NAME = "north_channel_core" *)
-(* SIM_GTRESET_SPEEDUP = "FALSE" *)
-module north_channel_north_channel_core
- (S_AXI_TX_TDATA,
- S_AXI_TX_TKEEP,
- S_AXI_TX_TVALID,
- S_AXI_TX_TREADY,
- S_AXI_TX_TLAST,
- M_AXI_RX_TDATA,
- M_AXI_RX_TKEEP,
- M_AXI_RX_TVALID,
- M_AXI_RX_TLAST,
- S_AXI_UFC_TX_REQ,
- S_AXI_UFC_TX_MS,
- S_AXI_UFC_TX_ACK,
- M_AXI_UFC_RX_TDATA,
- M_AXI_UFC_RX_TKEEP,
- M_AXI_UFC_RX_TVALID,
- M_AXI_UFC_RX_TLAST,
- RXP,
- RXN,
- TXP,
- TXN,
- gt_refclk1,
- HARD_ERR,
- SOFT_ERR,
- FRAME_ERR,
- CHANNEL_UP,
- LANE_UP,
- user_clk,
- sync_clk,
- RESET,
- POWER_DOWN,
- LOOPBACK,
- GT_RESET,
- init_clk_in,
- PLL_NOT_LOCKED,
- TX_RESETDONE_OUT,
- RX_RESETDONE_OUT,
- LINK_RESET_OUT,
- drpclk_in,
- DRPADDR_IN,
- DRPDI_IN,
- DRPDO_OUT,
- DRPEN_IN,
- DRPRDY_OUT,
- DRPWE_IN,
- TX_OUT_CLK,
- gt_common_reset_out,
- gt0_pll0refclklost_in,
- quad1_common_lock_in,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- sys_reset_out,
- tx_lock);
- input [0:31]S_AXI_TX_TDATA;
- input [0:3]S_AXI_TX_TKEEP;
- input S_AXI_TX_TVALID;
- output S_AXI_TX_TREADY;
- input S_AXI_TX_TLAST;
- output [0:31]M_AXI_RX_TDATA;
- output [0:3]M_AXI_RX_TKEEP;
- output M_AXI_RX_TVALID;
- output M_AXI_RX_TLAST;
- input S_AXI_UFC_TX_REQ;
- input [0:2]S_AXI_UFC_TX_MS;
- output S_AXI_UFC_TX_ACK;
- output [0:31]M_AXI_UFC_RX_TDATA;
- output [0:3]M_AXI_UFC_RX_TKEEP;
- output M_AXI_UFC_RX_TVALID;
- output M_AXI_UFC_RX_TLAST;
- input RXP;
- input RXN;
- output TXP;
- output TXN;
- input gt_refclk1;
- output HARD_ERR;
- output SOFT_ERR;
- output FRAME_ERR;
- output CHANNEL_UP;
- output LANE_UP;
- input user_clk;
- input sync_clk;
- input RESET;
- input POWER_DOWN;
- input [2:0]LOOPBACK;
- input GT_RESET;
- input init_clk_in;
- input PLL_NOT_LOCKED;
- output TX_RESETDONE_OUT;
- output RX_RESETDONE_OUT;
- output LINK_RESET_OUT;
- input drpclk_in;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- output [15:0]DRPDO_OUT;
- input DRPEN_IN;
- output DRPRDY_OUT;
- input DRPWE_IN;
- output TX_OUT_CLK;
- output gt_common_reset_out;
- input gt0_pll0refclklost_in;
- input quad1_common_lock_in;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- output sys_reset_out;
- output tx_lock;
-
- wire \<const1> ;
- wire CHANNEL_UP;
- wire DO_CC_I;
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN_IN;
- wire DRPRDY_OUT;
- wire DRPWE_IN;
- wire FRAME_ERR;
- wire GEN_SCP;
- wire GEN_SUF;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire GTRXRESET_OUT;
- wire GT_RESET;
- wire HARD_ERR;
- wire HPCNT_RESET;
- wire LANE_UP;
- wire LINK_RESET_OUT;
- wire [2:0]LOOPBACK;
- wire [0:31]M_AXI_RX_TDATA;
- wire [1:3]\^M_AXI_RX_TKEEP ;
- wire M_AXI_RX_TLAST;
- wire M_AXI_RX_TVALID;
- wire [0:31]M_AXI_UFC_RX_TDATA;
- wire [2:2]\^M_AXI_UFC_RX_TKEEP ;
- wire M_AXI_UFC_RX_TLAST;
- wire M_AXI_UFC_RX_TVALID;
- wire PLL_NOT_LOCKED;
- wire POWER_DOWN;
- wire RESET;
- wire RESET_0;
- wire RXN;
- wire RXP;
- wire RX_RESETDONE_OUT;
- wire SOFT_ERR;
- wire START_RX;
- wire [0:31]S_AXI_TX_TDATA;
- wire [0:3]S_AXI_TX_TKEEP;
- wire S_AXI_TX_TLAST;
- wire S_AXI_TX_TREADY;
- wire S_AXI_TX_TVALID;
- wire S_AXI_UFC_TX_ACK;
- wire [0:2]S_AXI_UFC_TX_MS;
- wire S_AXI_UFC_TX_REQ;
- wire [3:0]TXCHARISK_IN;
- wire [31:0]TXDATA_IN;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire TX_RESETDONE_OUT;
- wire WARN_CC;
- wire axi_to_ll_pdu_i_n_0;
- wire \channel_init_sm_i/wait_for_lane_up_r0 ;
- wire drpclk_in;
- wire ena_comma_align_i;
- wire gen_a_i;
- wire gen_cc_i;
- wire gen_ecp_i;
- wire [0:3]gen_k_i;
- wire [0:1]gen_pad_i;
- wire [0:3]gen_r_i;
- wire [1:3]gen_v_i;
- wire got_v_i;
- wire gt_common_reset_out;
- wire gt_reset_sync_init_clk;
- wire gt_wrapper_i_n_68;
- wire gt_wrapper_i_n_69;
- wire gt_wrapper_i_n_70;
- wire gt_wrapper_i_n_71;
- wire gt_wrapper_i_n_72;
- wire gt_wrapper_i_n_73;
- wire gt_wrapper_i_n_74;
- wire gt_wrapper_i_n_75;
- wire gt_wrapper_i_n_76;
- wire gt_wrapper_i_n_77;
- wire gt_wrapper_i_n_78;
- wire gt_wrapper_i_n_79;
- wire gt_wrapper_i_n_80;
- wire gt_wrapper_i_n_81;
- wire gt_wrapper_i_n_82;
- wire gt_wrapper_i_n_83;
- wire gt_wrapper_i_n_84;
- wire gt_wrapper_i_n_85;
- wire gt_wrapper_i_n_86;
- wire gt_wrapper_i_n_87;
- wire gt_wrapper_i_n_88;
- wire gt_wrapper_i_n_89;
- wire gt_wrapper_i_n_90;
- wire gt_wrapper_i_n_91;
- wire gt_wrapper_i_n_92;
- wire gt_wrapper_i_n_95;
- wire gt_wrapper_i_n_96;
- wire hard_err_i;
- wire init_clk_in;
- wire link_reset_r;
- wire neqOp;
- wire new_pkt_r;
- wire north_channel_aurora_lane_4byte_0_i_n_12;
- wire north_channel_aurora_lane_4byte_0_i_n_13;
- wire north_channel_aurora_lane_4byte_0_i_n_14;
- wire north_channel_aurora_lane_4byte_0_i_n_15;
- wire north_channel_aurora_lane_4byte_0_i_n_16;
- wire north_channel_aurora_lane_4byte_0_i_n_17;
- wire north_channel_aurora_lane_4byte_0_i_n_18;
- wire north_channel_aurora_lane_4byte_0_i_n_19;
- wire north_channel_aurora_lane_4byte_0_i_n_20;
- wire north_channel_aurora_lane_4byte_0_i_n_3;
- wire north_channel_aurora_lane_4byte_0_i_n_4;
- wire north_channel_aurora_lane_4byte_0_i_n_57;
- wire north_channel_aurora_lane_4byte_0_i_n_58;
- wire north_channel_aurora_lane_4byte_0_i_n_59;
- wire north_channel_aurora_lane_4byte_0_i_n_60;
- wire \north_channel_err_detect_4byte_i/hard_err_gt0 ;
- wire north_channel_global_logic_i_n_19;
- wire north_channel_global_logic_i_n_20;
- wire north_channel_rx_ll_i_n_5;
- wire north_channel_rx_ll_i_n_6;
- wire [1:0]\north_channel_sym_dec_4byte_i/p_8_out ;
- wire [1:0]\north_channel_sym_dec_4byte_i/p_9_out ;
- wire [0:0]\north_channel_sym_dec_4byte_i/previous_cycle_control_r ;
- wire north_channel_tx_ll_i_n_10;
- wire north_channel_tx_ll_i_n_6;
- wire north_channel_tx_ll_i_n_7;
- wire north_channel_tx_ll_i_n_8;
- wire quad1_common_lock_in;
- wire reset_channel_i;
- wire reset_lanes_i;
- wire reset_sync_user_clk;
- wire rx_cc_i;
- wire [3:0]rx_char_is_comma_i;
- wire [3:0]rx_char_is_k_i;
- wire [31:0]rx_data_i;
- wire [3:0]rx_disp_err_i;
- wire rx_eof;
- wire [3:0]rx_not_in_table_i;
- wire [0:1]rx_pad_descram_in;
- wire [0:31]rx_pe_data_striped_i;
- wire [0:1]rx_pe_data_v_striped_i;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire [0:1]rx_suf_striped_i;
- wire [0:1]soft_err_i;
- wire sync_clk;
- wire sys_reset_out;
- wire tx_dst_rdy;
- wire \tx_ll_control_i/next_ufc_idle_c ;
- wire tx_lock;
- wire [0:31]tx_pe_data_i;
- wire [0:1]tx_pe_data_v_i;
- wire tx_reset_i;
- wire user_clk;
-
- assign M_AXI_RX_TKEEP[0] = \<const1> ;
- assign M_AXI_RX_TKEEP[1:3] = \^M_AXI_RX_TKEEP [1:3];
- assign M_AXI_UFC_RX_TKEEP[0] = \<const1> ;
- assign M_AXI_UFC_RX_TKEEP[1] = \<const1> ;
- assign M_AXI_UFC_RX_TKEEP[2] = \^M_AXI_UFC_RX_TKEEP [2];
- assign M_AXI_UFC_RX_TKEEP[3] = \^M_AXI_UFC_RX_TKEEP [2];
- VCC VCC
- (.P(\<const1> ));
- north_channel_north_channel_AXI_TO_LL axi_to_ll_pdu_i
- (.new_pkt_r(new_pkt_r),
- .new_pkt_r_reg_0(axi_to_ll_pdu_i_n_0),
- .user_clk(user_clk));
- north_channel_north_channel_RESET_LOGIC core_reset_logic_i
- (.LINK_RESET_OUT(LINK_RESET_OUT),
- .PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .SYSTEM_RESET_reg_0(sys_reset_out),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .gt_rxresetdone_r2_reg_0(gt_wrapper_i_n_95),
- .gt_txresetdone_r2_reg_0(gt_wrapper_i_n_96),
- .init_clk_in(init_clk_in),
- .link_reset_r(link_reset_r),
- .new_pkt_r(new_pkt_r),
- .new_pkt_r_reg(CHANNEL_UP),
- .new_pkt_r_reg_0(axi_to_ll_pdu_i_n_0),
- .out(reset_sync_user_clk),
- .reset_channel_i(reset_channel_i),
- .tx_dst_rdy(tx_dst_rdy),
- .tx_lock(tx_lock),
- .user_clk(user_clk),
- .wait_for_lane_up_r0(\channel_init_sm_i/wait_for_lane_up_r0 ));
- north_channel_north_channel_cdc_sync__parameterized1 gt_reset_cdc_sync
- (.AR(gt_reset_sync_init_clk),
- .GT_RESET(GT_RESET),
- .init_clk_in(init_clk_in));
- north_channel_north_channel_GT_WRAPPER gt_wrapper_i
- (.AR(gt_reset_sync_init_clk),
- .D(rx_char_is_comma_i),
- .DRPADDR_IN(DRPADDR_IN),
- .DRPDI_IN(DRPDI_IN),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE_IN(DRPWE_IN),
- .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg (gt_wrapper_i_n_96),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .GTRXRESET_OUT(GTRXRESET_OUT),
- .LOOPBACK(LOOPBACK),
- .PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .POWER_DOWN(POWER_DOWN),
- .Q({TXCHARISK_IN[0],TXCHARISK_IN[1],TXCHARISK_IN[2],TXCHARISK_IN[3]}),
- .RXCHARISK(rx_char_is_k_i),
- .RXDATA(rx_data_i),
- .RXDISPERR({rx_disp_err_i[3],rx_disp_err_i[0]}),
- .RXN(RXN),
- .RXNOTINTABLE({rx_not_in_table_i[3],rx_not_in_table_i[0]}),
- .RXP(RXP),
- .RX_RESETDONE_OUT(RX_RESETDONE_OUT),
- .TXDATA(TXDATA_IN),
- .TXN(TXN),
- .TXP(TXP),
- .TX_OUT_CLK(TX_OUT_CLK),
- .TX_RESETDONE_OUT(TX_RESETDONE_OUT),
- .drpclk_in(drpclk_in),
- .drpclk_in_0(DRPRDY_OUT),
- .drpclk_in_1(gt_wrapper_i_n_71),
- .drpclk_in_2(gt_wrapper_i_n_72),
- .drpclk_in_3(gt_wrapper_i_n_73),
- .drpclk_in_4(gt_wrapper_i_n_74),
- .ena_comma_align_i(ena_comma_align_i),
- .gt_common_reset_out(gt_common_reset_out),
- .hard_err_gt0(\north_channel_err_detect_4byte_i/hard_err_gt0 ),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (gt_wrapper_i_n_68),
- .\left_align_select_r_reg[0]_0 (north_channel_aurora_lane_4byte_0_i_n_12),
- .\left_align_select_r_reg[0]_1 (north_channel_aurora_lane_4byte_0_i_n_3),
- .\left_align_select_r_reg[1] (gt_wrapper_i_n_69),
- .\left_align_select_r_reg[1]_0 ({gt_wrapper_i_n_75,gt_wrapper_i_n_76,gt_wrapper_i_n_77,gt_wrapper_i_n_78,gt_wrapper_i_n_79,gt_wrapper_i_n_80,gt_wrapper_i_n_81,gt_wrapper_i_n_82}),
- .\left_align_select_r_reg[1]_1 ({gt_wrapper_i_n_83,gt_wrapper_i_n_84,gt_wrapper_i_n_85,gt_wrapper_i_n_86,gt_wrapper_i_n_87,gt_wrapper_i_n_88,gt_wrapper_i_n_89,gt_wrapper_i_n_90}),
- .\left_align_select_r_reg[1]_2 (gt_wrapper_i_n_91),
- .\left_align_select_r_reg[1]_3 (gt_wrapper_i_n_92),
- .\left_align_select_r_reg[1]_4 (north_channel_aurora_lane_4byte_0_i_n_4),
- .link_reset_r(link_reset_r),
- .quad1_common_lock_in(quad1_common_lock_in),
- .rst_r_reg(gt_wrapper_i_n_70),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .rxfsm_rxresetdone_r3_reg_0(gt_wrapper_i_n_95),
- .sync_clk(sync_clk),
- .tx_lock(tx_lock),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (\north_channel_sym_dec_4byte_i/previous_cycle_control_r ),
- .\word_aligned_data_r_reg[16] ({north_channel_aurora_lane_4byte_0_i_n_13,north_channel_aurora_lane_4byte_0_i_n_14,north_channel_aurora_lane_4byte_0_i_n_15,north_channel_aurora_lane_4byte_0_i_n_16,north_channel_aurora_lane_4byte_0_i_n_17,north_channel_aurora_lane_4byte_0_i_n_18,north_channel_aurora_lane_4byte_0_i_n_19,north_channel_aurora_lane_4byte_0_i_n_20}));
- north_channel_north_channel_cdc_sync__parameterized1_0 hpcnt_reset_cdc_sync
- (.AR(gt_reset_sync_init_clk),
- .HPCNT_RESET(HPCNT_RESET),
- .RESET(RESET),
- .init_clk_in(init_clk_in));
- north_channel_north_channel_LL_TO_AXI ll_to_axi_pdu_i
- (.M_AXI_RX_TKEEP({\^M_AXI_RX_TKEEP [1],\^M_AXI_RX_TKEEP [2],\^M_AXI_RX_TKEEP [3]}),
- .Q({north_channel_rx_ll_i_n_5,north_channel_rx_ll_i_n_6}),
- .rx_eof(rx_eof));
- north_channel_north_channel_AURORA_LANE_4BYTE north_channel_aurora_lane_4byte_0_i
- (.\CHAR_IS_K_OUT_reg[3] ({TXCHARISK_IN[0],TXCHARISK_IN[1],TXCHARISK_IN[2],TXCHARISK_IN[3]}),
- .D(rx_cc_i),
- .GEN_A(gen_a_i),
- .GEN_ECP(gen_ecp_i),
- .GEN_SCP(GEN_SCP),
- .GEN_SUF(GEN_SUF),
- .HPCNT_RESET(HPCNT_RESET),
- .LANE_UP(LANE_UP),
- .LINK_RESET_OUT(LINK_RESET_OUT),
- .Q({rx_pad_descram_in[0],rx_pad_descram_in[1]}),
- .RXCHARISK(rx_char_is_k_i),
- .RXDATA(rx_data_i),
- .RXDISPERR({rx_disp_err_i[3],rx_disp_err_i[0]}),
- .RXNOTINTABLE({rx_not_in_table_i[3],rx_not_in_table_i[0]}),
- .\RX_CHAR_IS_COMMA_R_reg[3] (rx_char_is_comma_i),
- .\RX_PE_DATA_V_reg[0] ({rx_pe_data_v_striped_i[0],rx_pe_data_v_striped_i[1]}),
- .\RX_SUF_Buffer_reg[0] ({rx_suf_striped_i[0],rx_suf_striped_i[1]}),
- .\RX_SUF_Buffer_reg[1] (north_channel_aurora_lane_4byte_0_i_n_60),
- .\SOFT_ERR_Buffer_reg[0] ({soft_err_i[0],soft_err_i[1]}),
- .SS(north_channel_global_logic_i_n_19),
- .TXDATA(TXDATA_IN),
- .\bypass_r_reg[0] (CHANNEL_UP),
- .\data_nxt2_reg[25] (north_channel_aurora_lane_4byte_0_i_n_59),
- .\data_nxt2_reg[26] (north_channel_aurora_lane_4byte_0_i_n_57),
- .\data_nxt2_reg[26]_0 (north_channel_aurora_lane_4byte_0_i_n_58),
- .ena_comma_align_i(ena_comma_align_i),
- .\fc_nb_r_reg[0] (north_channel_tx_ll_i_n_6),
- .\fc_nb_r_reg[1] (north_channel_tx_ll_i_n_7),
- .\fc_nb_r_reg[2] (north_channel_tx_ll_i_n_8),
- .gen_cc_i(gen_cc_i),
- .\gen_k_r_reg[0] ({gen_k_i[0],gen_k_i[1],gen_k_i[2],gen_k_i[3]}),
- .\gen_pad_r_reg[0] ({gen_pad_i[0],gen_pad_i[1]}),
- .\gen_r_r_reg[0] ({gen_r_i[0],gen_r_i[1],gen_r_i[2],gen_r_i[3]}),
- .\gen_v_r_reg[1] ({gen_v_i[1],gen_v_i[2],gen_v_i[3]}),
- .got_v_i(got_v_i),
- .hard_err_gt0(\north_channel_err_detect_4byte_i/hard_err_gt0 ),
- .hard_err_i(hard_err_i),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (north_channel_aurora_lane_4byte_0_i_n_3),
- .\left_align_select_r_reg[0]_0 (gt_wrapper_i_n_68),
- .\left_align_select_r_reg[1] (north_channel_aurora_lane_4byte_0_i_n_4),
- .\left_align_select_r_reg[1]_0 (gt_wrapper_i_n_69),
- .neqOp(neqOp),
- .p_8_out(\north_channel_sym_dec_4byte_i/p_8_out ),
- .p_9_out(\north_channel_sym_dec_4byte_i/p_9_out ),
- .\previous_cycle_control_r_reg[0] (\north_channel_sym_dec_4byte_i/previous_cycle_control_r ),
- .\previous_cycle_data_r_reg[7] ({north_channel_aurora_lane_4byte_0_i_n_13,north_channel_aurora_lane_4byte_0_i_n_14,north_channel_aurora_lane_4byte_0_i_n_15,north_channel_aurora_lane_4byte_0_i_n_16,north_channel_aurora_lane_4byte_0_i_n_17,north_channel_aurora_lane_4byte_0_i_n_18,north_channel_aurora_lane_4byte_0_i_n_19,north_channel_aurora_lane_4byte_0_i_n_20}),
- .ready_r_reg(north_channel_aurora_lane_4byte_0_i_n_12),
- .reset_count_r_reg(gt_wrapper_i_n_70),
- .reset_lanes_i(reset_lanes_i),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .\soft_err_r_reg[0] (gt_wrapper_i_n_73),
- .\soft_err_r_reg[1] (gt_wrapper_i_n_71),
- .\soft_err_r_reg[2] (gt_wrapper_i_n_72),
- .\soft_err_r_reg[3] (gt_wrapper_i_n_74),
- .\tx_pe_data_r_reg[0] ({tx_pe_data_i[0],tx_pe_data_i[1],tx_pe_data_i[2],tx_pe_data_i[3],tx_pe_data_i[4],tx_pe_data_i[5],tx_pe_data_i[6],tx_pe_data_i[7],tx_pe_data_i[8],tx_pe_data_i[9],tx_pe_data_i[10],tx_pe_data_i[11],tx_pe_data_i[12],tx_pe_data_i[13],tx_pe_data_i[14],tx_pe_data_i[15],tx_pe_data_i[16],tx_pe_data_i[17],tx_pe_data_i[18],tx_pe_data_i[19],tx_pe_data_i[20],tx_pe_data_i[21],tx_pe_data_i[22],tx_pe_data_i[23],tx_pe_data_i[24],tx_pe_data_i[25],tx_pe_data_i[26],tx_pe_data_i[27],tx_pe_data_i[28],tx_pe_data_i[29],tx_pe_data_i[30],tx_pe_data_i[31]}),
- .\tx_pe_data_v_r_reg[0] ({tx_pe_data_v_i[0],tx_pe_data_v_i[1]}),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (gt_wrapper_i_n_91),
- .\word_aligned_control_bits_r_reg[3] (gt_wrapper_i_n_92),
- .\word_aligned_data_r_reg[16] ({gt_wrapper_i_n_75,gt_wrapper_i_n_76,gt_wrapper_i_n_77,gt_wrapper_i_n_78,gt_wrapper_i_n_79,gt_wrapper_i_n_80,gt_wrapper_i_n_81,gt_wrapper_i_n_82}),
- .\word_aligned_data_r_reg[24] ({gt_wrapper_i_n_83,gt_wrapper_i_n_84,gt_wrapper_i_n_85,gt_wrapper_i_n_86,gt_wrapper_i_n_87,gt_wrapper_i_n_88,gt_wrapper_i_n_89,gt_wrapper_i_n_90}));
- north_channel_north_channel_GLOBAL_LOGIC north_channel_global_logic_i
- (.CHANNEL_UP_Buffer_reg(CHANNEL_UP),
- .CHANNEL_UP_Buffer_reg_0(north_channel_global_logic_i_n_20),
- .D(rx_cc_i),
- .GEN_A(gen_a_i),
- .GTRXRESET_OUT(GTRXRESET_OUT),
- .HARD_ERR(HARD_ERR),
- .LANE_UP(LANE_UP),
- .POWER_DOWN(POWER_DOWN),
- .RESET(RESET_0),
- .SOFT_ERR(SOFT_ERR),
- .SS(north_channel_global_logic_i_n_19),
- .START_RX(START_RX),
- .\downcounter_r_reg[2] (sys_reset_out),
- .gen_k_flop_0_i({gen_k_i[0],gen_k_i[1],gen_k_i[2],gen_k_i[3]}),
- .gen_r_flop_0_i({gen_r_i[0],gen_r_i[1],gen_r_i[2],gen_r_i[3]}),
- .gen_v_flop_1_i({gen_v_i[1],gen_v_i[2],gen_v_i[3]}),
- .got_v_i(got_v_i),
- .hard_err_i(hard_err_i),
- .reset_channel_i(reset_channel_i),
- .reset_lanes_i(reset_lanes_i),
- .\soft_err_r_reg[0] ({soft_err_i[0],soft_err_i[1]}),
- .user_clk(user_clk),
- .wait_for_lane_up_r0(\channel_init_sm_i/wait_for_lane_up_r0 ));
- north_channel_north_channel_RX_LL north_channel_rx_ll_i
- (.D({rx_pe_data_v_striped_i[0],rx_pe_data_v_striped_i[1]}),
- .FRAME_ERR(FRAME_ERR),
- .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
- .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
- .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
- .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
- .M_AXI_UFC_RX_TKEEP(\^M_AXI_UFC_RX_TKEEP ),
- .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
- .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
- .Q({rx_pad_descram_in[0],rx_pad_descram_in[1]}),
- .RESET(RESET_0),
- .\RX_REM_Buffer_reg[0] ({north_channel_rx_ll_i_n_5,north_channel_rx_ll_i_n_6}),
- .START_RX(START_RX),
- .neqOp(neqOp),
- .p_8_out(\north_channel_sym_dec_4byte_i/p_8_out ),
- .p_9_out(\north_channel_sym_dec_4byte_i/p_9_out ),
- .rx_eof(rx_eof),
- .rx_pe_data_striped_i(rx_pe_data_striped_i),
- .\rx_suf_r_reg[0] ({rx_suf_striped_i[0],rx_suf_striped_i[1]}),
- .\stage_1_count_value_r_reg[0] (north_channel_aurora_lane_4byte_0_i_n_60),
- .\stage_1_count_value_r_reg[1] (north_channel_aurora_lane_4byte_0_i_n_59),
- .\stage_1_count_value_r_reg[2] (north_channel_aurora_lane_4byte_0_i_n_58),
- .\stage_1_count_value_r_reg[3] (north_channel_aurora_lane_4byte_0_i_n_57),
- .user_clk(user_clk));
- north_channel_north_channel_TX_LL north_channel_tx_ll_i
- (.DO_CC_I(DO_CC_I),
- .GEN_ECP(gen_ecp_i),
- .\GEN_PAD_Buffer_reg[0] ({gen_pad_i[0],gen_pad_i[1]}),
- .GEN_SCP(GEN_SCP),
- .GEN_SUF(GEN_SUF),
- .Q({tx_pe_data_v_i[0],tx_pe_data_v_i[1]}),
- .S_AXI_TX_TDATA(S_AXI_TX_TDATA),
- .S_AXI_TX_TKEEP(S_AXI_TX_TKEEP),
- .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
- .S_AXI_TX_TREADY(S_AXI_TX_TREADY),
- .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
- .S_AXI_UFC_TX_MS(S_AXI_UFC_TX_MS),
- .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
- .\TX_PE_DATA_Buffer_reg[0] ({tx_pe_data_i[0],tx_pe_data_i[1],tx_pe_data_i[2],tx_pe_data_i[3],tx_pe_data_i[4],tx_pe_data_i[5],tx_pe_data_i[6],tx_pe_data_i[7],tx_pe_data_i[8],tx_pe_data_i[9],tx_pe_data_i[10],tx_pe_data_i[11],tx_pe_data_i[12],tx_pe_data_i[13],tx_pe_data_i[14],tx_pe_data_i[15],tx_pe_data_i[16],tx_pe_data_i[17],tx_pe_data_i[18],tx_pe_data_i[19],tx_pe_data_i[20],tx_pe_data_i[21],tx_pe_data_i[22],tx_pe_data_i[23],tx_pe_data_i[24],tx_pe_data_i[25],tx_pe_data_i[26],tx_pe_data_i[27],tx_pe_data_i[28],tx_pe_data_i[29],tx_pe_data_i[30],tx_pe_data_i[31]}),
- .WARN_CC(WARN_CC),
- .gen_cc_i(gen_cc_i),
- .in_frame_r_reg(north_channel_global_logic_i_n_20),
- .next_ufc_idle_c(\tx_ll_control_i/next_ufc_idle_c ),
- .\s_axi_ufc_tx_tdata[0] (north_channel_tx_ll_i_n_6),
- .\s_axi_ufc_tx_tdata[1] (north_channel_tx_ll_i_n_7),
- .\s_axi_ufc_tx_tdata[2] (north_channel_tx_ll_i_n_8),
- .tx_dst_rdy(tx_dst_rdy),
- .\tx_pe_data_v_r_reg[1] (axi_to_ll_pdu_i_n_0),
- .ufc_header_r_reg(S_AXI_UFC_TX_ACK),
- .\ufc_message_count_r_reg[2] (north_channel_tx_ll_i_n_10),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync reset_sync_user_clk_cdc_sync
- (.RESET(RESET),
- .out(reset_sync_user_clk),
- .user_clk(user_clk));
- north_channel_north_channel_STANDARD_CC_MODULE standard_cc_module_i
- (.DO_CC_I(DO_CC_I),
- .DO_CC_reg_0(sys_reset_out),
- .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
- .WARN_CC(WARN_CC),
- .next_ufc_idle_c(\tx_ll_control_i/next_ufc_idle_c ),
- .ufc_idle_r_reg(north_channel_tx_ll_i_n_10),
- .user_clk(user_clk));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_gt" *)
-module north_channel_north_channel_gt
- (drpclk_in_0,
- TXN,
- TXP,
- rx_realign_i,
- drpclk_in_1,
- TX_OUT_CLK,
- drpclk_in_2,
- DRPDO_OUT,
- RXDATA,
- D,
- RXCHARISK,
- RXDISPERR,
- RXNOTINTABLE,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- rst_r_reg,
- drpclk_in_3,
- drpclk_in_4,
- drpclk_in_5,
- drpclk_in_6,
- \left_align_select_r_reg[1]_0 ,
- \left_align_select_r_reg[1]_1 ,
- \left_align_select_r_reg[1]_2 ,
- \left_align_select_r_reg[1]_3 ,
- hard_err_gt0,
- drpclk_in,
- RXN,
- RXP,
- gt_tx_reset_i,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- ena_comma_align_i,
- rx_polarity_i,
- gt_rxuserrdy_i,
- sync_clk,
- user_clk,
- POWER_DOWN,
- gt_txuserrdy_i,
- LOOPBACK,
- TXDATA,
- Q,
- gt_common_reset_out,
- init_clk_in,
- SR,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[0]_1 ,
- \left_align_select_r_reg[1]_4 ,
- tx_reset_i,
- \word_aligned_data_r_reg[16] ,
- \word_aligned_control_bits_r_reg[2] ,
- DRPADDR_IN,
- DRPDI_IN,
- DRPWE_IN,
- DRPEN_IN);
- output drpclk_in_0;
- output TXN;
- output TXP;
- output rx_realign_i;
- output drpclk_in_1;
- output TX_OUT_CLK;
- output drpclk_in_2;
- output [15:0]DRPDO_OUT;
- output [31:0]RXDATA;
- output [3:0]D;
- output [3:0]RXCHARISK;
- output [1:0]RXDISPERR;
- output [1:0]RXNOTINTABLE;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output rst_r_reg;
- output drpclk_in_3;
- output drpclk_in_4;
- output drpclk_in_5;
- output drpclk_in_6;
- output [7:0]\left_align_select_r_reg[1]_0 ;
- output [7:0]\left_align_select_r_reg[1]_1 ;
- output \left_align_select_r_reg[1]_2 ;
- output \left_align_select_r_reg[1]_3 ;
- output hard_err_gt0;
- input drpclk_in;
- input RXN;
- input RXP;
- input gt_tx_reset_i;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- input ena_comma_align_i;
- input rx_polarity_i;
- input gt_rxuserrdy_i;
- input sync_clk;
- input user_clk;
- input POWER_DOWN;
- input gt_txuserrdy_i;
- input [2:0]LOOPBACK;
- input [31:0]TXDATA;
- input [3:0]Q;
- input gt_common_reset_out;
- input init_clk_in;
- input [0:0]SR;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[0]_1 ;
- input \left_align_select_r_reg[1]_4 ;
- input tx_reset_i;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input [0:0]\word_aligned_control_bits_r_reg[2] ;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- input DRPWE_IN;
- input DRPEN_IN;
-
- wire [3:0]D;
- wire [4:0]DRPADDR;
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN;
- wire DRPEN_IN;
- wire DRPWE;
- wire DRPWE_IN;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire GTRXRESET;
- wire [2:0]LOOPBACK;
- wire POWER_DOWN;
- wire [3:0]Q;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire RXN;
- wire [1:0]RXNOTINTABLE;
- wire RXP;
- wire [0:0]SR;
- wire [31:0]TXDATA;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire drp_op_done;
- wire drpclk_in;
- wire drpclk_in_0;
- wire drpclk_in_1;
- wire drpclk_in_2;
- wire drpclk_in_3;
- wire drpclk_in_4;
- wire drpclk_in_5;
- wire drpclk_in_6;
- wire ena_comma_align_i;
- wire gt_common_reset_out;
- wire gt_rxuserrdy_i;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire gtpe2_i_n_1;
- wire gtpe2_i_n_102;
- wire gtpe2_i_n_104;
- wire gtpe2_i_n_105;
- wire gtpe2_i_n_14;
- wire gtpe2_i_n_24;
- wire gtpe2_i_n_28;
- wire gtpe2_i_n_29;
- wire gtpe2_i_n_39;
- wire gtpe2_i_n_40;
- wire gtpe2_i_n_48;
- wire gtpe2_i_n_49;
- wire gtpe2_i_n_50;
- wire gtpe2_i_n_51;
- wire gtpe2_i_n_52;
- wire gtpe2_i_n_53;
- wire gtpe2_i_n_54;
- wire gtpe2_i_n_55;
- wire gtpe2_i_n_56;
- wire gtpe2_i_n_57;
- wire gtpe2_i_n_58;
- wire gtpe2_i_n_59;
- wire gtpe2_i_n_60;
- wire gtpe2_i_n_61;
- wire gtpe2_i_n_62;
- wire gtpe2_i_n_7;
- wire gtpe2_i_n_9;
- wire gtpe2_i_n_95;
- wire gtpe2_i_n_96;
- wire gtrxreset_seq_i_n_10;
- wire gtrxreset_seq_i_n_17;
- wire gtrxreset_seq_i_n_2;
- wire gtrxreset_seq_i_n_4;
- wire gtrxreset_seq_i_n_5;
- wire gtrxreset_seq_i_n_6;
- wire gtrxreset_seq_i_n_7;
- wire gtrxreset_seq_i_n_8;
- wire gtrxreset_seq_i_n_9;
- wire hard_err_gt0;
- wire [15:0]in7;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1] ;
- wire [7:0]\left_align_select_r_reg[1]_0 ;
- wire [7:0]\left_align_select_r_reg[1]_1 ;
- wire \left_align_select_r_reg[1]_2 ;
- wire \left_align_select_r_reg[1]_3 ;
- wire \left_align_select_r_reg[1]_4 ;
- wire p_0_in;
- wire rst_r_reg;
- wire rx_buf_err_i;
- wire [2:1]rx_disp_err_i;
- wire [2:1]rx_not_in_table_i;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire sync_clk;
- wire tx_buf_err_i;
- wire tx_reset_i;
- wire user_clk;
- wire [0:0]\word_aligned_control_bits_r_reg[2] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
- wire NLW_gtpe2_i_PHYSTATUS_UNCONNECTED;
- wire NLW_gtpe2_i_PMARSVDOUT0_UNCONNECTED;
- wire NLW_gtpe2_i_PMARSVDOUT1_UNCONNECTED;
- wire NLW_gtpe2_i_RXCHANBONDSEQ_UNCONNECTED;
- wire NLW_gtpe2_i_RXCHANISALIGNED_UNCONNECTED;
- wire NLW_gtpe2_i_RXCHANREALIGN_UNCONNECTED;
- wire NLW_gtpe2_i_RXCOMINITDET_UNCONNECTED;
- wire NLW_gtpe2_i_RXCOMSASDET_UNCONNECTED;
- wire NLW_gtpe2_i_RXCOMWAKEDET_UNCONNECTED;
- wire NLW_gtpe2_i_RXDLYSRESETDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXELECIDLE_UNCONNECTED;
- wire NLW_gtpe2_i_RXHEADERVALID_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTSTARTED_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
- wire NLW_gtpe2_i_RXOUTCLKFABRIC_UNCONNECTED;
- wire NLW_gtpe2_i_RXOUTCLKPCS_UNCONNECTED;
- wire NLW_gtpe2_i_RXPHALIGNDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXRATEDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXSYNCDONE_UNCONNECTED;
- wire NLW_gtpe2_i_RXSYNCOUT_UNCONNECTED;
- wire NLW_gtpe2_i_RXVALID_UNCONNECTED;
- wire NLW_gtpe2_i_TXCOMFINISH_UNCONNECTED;
- wire NLW_gtpe2_i_TXDLYSRESETDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXGEARBOXREADY_UNCONNECTED;
- wire NLW_gtpe2_i_TXPHALIGNDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXPHINITDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXPMARESETDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXRATEDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXSYNCDONE_UNCONNECTED;
- wire NLW_gtpe2_i_TXSYNCOUT_UNCONNECTED;
- wire [15:0]NLW_gtpe2_i_PCSRSVDOUT_UNCONNECTED;
- wire [3:0]NLW_gtpe2_i_RXCHBONDO_UNCONNECTED;
- wire [1:0]NLW_gtpe2_i_RXDATAVALID_UNCONNECTED;
- wire [2:0]NLW_gtpe2_i_RXHEADER_UNCONNECTED;
- wire [4:0]NLW_gtpe2_i_RXPHMONITOR_UNCONNECTED;
- wire [4:0]NLW_gtpe2_i_RXPHSLIPMONITOR_UNCONNECTED;
- wire [1:0]NLW_gtpe2_i_RXSTARTOFSEQ_UNCONNECTED;
- wire [2:0]NLW_gtpe2_i_RXSTATUS_UNCONNECTED;
-
- (* BOX_TYPE = "PRIMITIVE" *)
- GTPE2_CHANNEL #(
- .ACJTAG_DEBUG_MODE(1'b0),
- .ACJTAG_MODE(1'b0),
- .ACJTAG_RESET(1'b0),
- .ADAPT_CFG0(20'b00000000000000000000),
- .ALIGN_COMMA_DOUBLE("FALSE"),
- .ALIGN_COMMA_ENABLE(10'b1111111111),
- .ALIGN_COMMA_WORD(2),
- .ALIGN_MCOMMA_DET("TRUE"),
- .ALIGN_MCOMMA_VALUE(10'b1010000011),
- .ALIGN_PCOMMA_DET("TRUE"),
- .ALIGN_PCOMMA_VALUE(10'b0101111100),
- .CBCC_DATA_SOURCE_SEL("DECODED"),
- .CFOK_CFG(43'b1001001000000000000000001000000111010000000),
- .CFOK_CFG2(7'b0100000),
- .CFOK_CFG3(7'b0100000),
- .CFOK_CFG4(1'b0),
- .CFOK_CFG5(2'b00),
- .CFOK_CFG6(4'b0000),
- .CHAN_BOND_KEEP_ALIGN("FALSE"),
- .CHAN_BOND_MAX_SKEW(7),
- .CHAN_BOND_SEQ_1_1(10'b0101111100),
- .CHAN_BOND_SEQ_1_2(10'b0000000000),
- .CHAN_BOND_SEQ_1_3(10'b0000000000),
- .CHAN_BOND_SEQ_1_4(10'b0000000000),
- .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
- .CHAN_BOND_SEQ_2_1(10'b0000000000),
- .CHAN_BOND_SEQ_2_2(10'b0000000000),
- .CHAN_BOND_SEQ_2_3(10'b0000000000),
- .CHAN_BOND_SEQ_2_4(10'b0000000000),
- .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
- .CHAN_BOND_SEQ_2_USE("FALSE"),
- .CHAN_BOND_SEQ_LEN(1),
- .CLK_COMMON_SWING(1'b0),
- .CLK_CORRECT_USE("TRUE"),
- .CLK_COR_KEEP_IDLE("FALSE"),
- .CLK_COR_MAX_LAT(31),
- .CLK_COR_MIN_LAT(24),
- .CLK_COR_PRECEDENCE("TRUE"),
- .CLK_COR_REPEAT_WAIT(0),
- .CLK_COR_SEQ_1_1(10'b0111110111),
- .CLK_COR_SEQ_1_2(10'b0111110111),
- .CLK_COR_SEQ_1_3(10'b0111110111),
- .CLK_COR_SEQ_1_4(10'b0111110111),
- .CLK_COR_SEQ_1_ENABLE(4'b1111),
- .CLK_COR_SEQ_2_1(10'b0100000000),
- .CLK_COR_SEQ_2_2(10'b0100000000),
- .CLK_COR_SEQ_2_3(10'b0100000000),
- .CLK_COR_SEQ_2_4(10'b0100000000),
- .CLK_COR_SEQ_2_ENABLE(4'b1111),
- .CLK_COR_SEQ_2_USE("FALSE"),
- .CLK_COR_SEQ_LEN(4),
- .DEC_MCOMMA_DETECT("TRUE"),
- .DEC_PCOMMA_DETECT("TRUE"),
- .DEC_VALID_COMMA_ONLY("FALSE"),
- .DMONITOR_CFG(24'h000A00),
- .ES_CLK_PHASE_SEL(1'b0),
- .ES_CONTROL(6'b000000),
- .ES_ERRDET_EN("FALSE"),
- .ES_EYE_SCAN_EN("FALSE"),
- .ES_HORZ_OFFSET(12'h010),
- .ES_PMA_CFG(10'b0000000000),
- .ES_PRESCALE(5'b00000),
- .ES_QUALIFIER(80'h00000000000000000000),
- .ES_QUAL_MASK(80'h00000000000000000000),
- .ES_SDATA_MASK(80'h00000000000000000000),
- .ES_VERT_OFFSET(9'b000000000),
- .FTS_DESKEW_SEQ_ENABLE(4'b1111),
- .FTS_LANE_DESKEW_CFG(4'b1111),
- .FTS_LANE_DESKEW_EN("FALSE"),
- .GEARBOX_MODE(3'b000),
- .IS_CLKRSVD0_INVERTED(1'b0),
- .IS_CLKRSVD1_INVERTED(1'b0),
- .IS_DMONITORCLK_INVERTED(1'b0),
- .IS_DRPCLK_INVERTED(1'b0),
- .IS_RXUSRCLK2_INVERTED(1'b0),
- .IS_RXUSRCLK_INVERTED(1'b0),
- .IS_SIGVALIDCLK_INVERTED(1'b0),
- .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
- .IS_TXUSRCLK2_INVERTED(1'b0),
- .IS_TXUSRCLK_INVERTED(1'b0),
- .LOOPBACK_CFG(1'b0),
- .OUTREFCLK_SEL_INV(2'b11),
- .PCS_PCIE_EN("FALSE"),
- .PCS_RSVD_ATTR(48'h000000000000),
- .PD_TRANS_TIME_FROM_P2(12'h03C),
- .PD_TRANS_TIME_NONE_P2(8'h3C),
- .PD_TRANS_TIME_TO_P2(8'h64),
- .PMA_LOOPBACK_CFG(1'b0),
- .PMA_RSV(32'h00000333),
- .PMA_RSV2(32'h00002040),
- .PMA_RSV3(2'b00),
- .PMA_RSV4(4'b0000),
- .PMA_RSV5(1'b0),
- .PMA_RSV6(1'b0),
- .PMA_RSV7(1'b0),
- .RXBUFRESET_TIME(5'b00001),
- .RXBUF_ADDR_MODE("FULL"),
- .RXBUF_EIDLE_HI_CNT(4'b1000),
- .RXBUF_EIDLE_LO_CNT(4'b0000),
- .RXBUF_EN("TRUE"),
- .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
- .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
- .RXBUF_RESET_ON_EIDLE("FALSE"),
- .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
- .RXBUF_THRESH_OVFLW(61),
- .RXBUF_THRESH_OVRD("FALSE"),
- .RXBUF_THRESH_UNDFLW(4),
- .RXCDRFREQRESET_TIME(5'b00001),
- .RXCDRPHRESET_TIME(5'b00001),
- .RXCDR_CFG(83'h0000107FE406001041010),
- .RXCDR_FR_RESET_ON_EIDLE(1'b0),
- .RXCDR_HOLD_DURING_EIDLE(1'b0),
- .RXCDR_LOCK_CFG(6'b001001),
- .RXCDR_PH_RESET_ON_EIDLE(1'b0),
- .RXDLY_CFG(16'h001F),
- .RXDLY_LCFG(9'h030),
- .RXDLY_TAP_CFG(16'h0000),
- .RXGEARBOX_EN("FALSE"),
- .RXISCANRESET_TIME(5'b00001),
- .RXLPMRESET_TIME(7'b0001111),
- .RXLPM_BIAS_STARTUP_DISABLE(1'b0),
- .RXLPM_CFG(4'b0110),
- .RXLPM_CFG1(1'b0),
- .RXLPM_CM_CFG(1'b0),
- .RXLPM_GC_CFG(9'b111100010),
- .RXLPM_GC_CFG2(3'b001),
- .RXLPM_HF_CFG(14'b00001111110000),
- .RXLPM_HF_CFG2(5'b01010),
- .RXLPM_HF_CFG3(4'b0000),
- .RXLPM_HOLD_DURING_EIDLE(1'b0),
- .RXLPM_INCM_CFG(1'b1),
- .RXLPM_IPCM_CFG(1'b0),
- .RXLPM_LF_CFG(18'b000000001111110000),
- .RXLPM_LF_CFG2(5'b01010),
- .RXLPM_OSINT_CFG(3'b100),
- .RXOOB_CFG(7'b0000110),
- .RXOOB_CLK_CFG("PMA"),
- .RXOSCALRESET_TIME(5'b00011),
- .RXOSCALRESET_TIMEOUT(5'b00000),
- .RXOUT_DIV(1),
- .RXPCSRESET_TIME(5'b00001),
- .RXPHDLY_CFG(24'h084020),
- .RXPH_CFG(24'hC00002),
- .RXPH_MONITOR_SEL(5'b00000),
- .RXPI_CFG0(3'b000),
- .RXPI_CFG1(1'b1),
- .RXPI_CFG2(1'b1),
- .RXPMARESET_TIME(5'b00011),
- .RXPRBS_ERR_LOOPBACK(1'b0),
- .RXSLIDE_AUTO_WAIT(7),
- .RXSLIDE_MODE("OFF"),
- .RXSYNC_MULTILANE(1'b0),
- .RXSYNC_OVRD(1'b0),
- .RXSYNC_SKIP_DA(1'b0),
- .RX_BIAS_CFG(16'b0000111100110011),
- .RX_BUFFER_CFG(6'b000000),
- .RX_CLK25_DIV(5),
- .RX_CLKMUX_EN(1'b1),
- .RX_CM_SEL(2'b11),
- .RX_CM_TRIM(4'b1010),
- .RX_DATA_WIDTH(40),
- .RX_DDI_SEL(6'b000000),
- .RX_DEBUG_CFG(14'b00000000000000),
- .RX_DEFER_RESET_BUF_EN("TRUE"),
- .RX_DISPERR_SEQ_MATCH("TRUE"),
- .RX_OS_CFG(13'b0000010000000),
- .RX_SIG_VALID_DLY(10),
- .RX_XCLK_SEL("RXREC"),
- .SAS_MAX_COM(64),
- .SAS_MIN_COM(36),
- .SATA_BURST_SEQ_LEN(4'b0101),
- .SATA_BURST_VAL(3'b100),
- .SATA_EIDLE_VAL(3'b100),
- .SATA_MAX_BURST(8),
- .SATA_MAX_INIT(21),
- .SATA_MAX_WAKE(7),
- .SATA_MIN_BURST(4),
- .SATA_MIN_INIT(12),
- .SATA_MIN_WAKE(4),
- .SATA_PLL_CFG("VCO_3000MHZ"),
- .SHOW_REALIGN_COMMA("TRUE"),
- .SIM_RECEIVER_DETECT_PASS("TRUE"),
- .SIM_RESET_SPEEDUP("FALSE"),
- .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
- .SIM_VERSION("2.0"),
- .TERM_RCAL_CFG(15'b100001000010000),
- .TERM_RCAL_OVRD(3'b000),
- .TRANS_TIME_RATE(8'h0E),
- .TST_RSV(32'h00000000),
- .TXBUF_EN("TRUE"),
- .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
- .TXDLY_CFG(16'h001F),
- .TXDLY_LCFG(9'h030),
- .TXDLY_TAP_CFG(16'h0000),
- .TXGEARBOX_EN("FALSE"),
- .TXOOB_CFG(1'b0),
- .TXOUT_DIV(1),
- .TXPCSRESET_TIME(5'b00001),
- .TXPHDLY_CFG(24'h084020),
- .TXPH_CFG(16'h0780),
- .TXPH_MONITOR_SEL(5'b00000),
- .TXPI_CFG0(2'b00),
- .TXPI_CFG1(2'b00),
- .TXPI_CFG2(2'b00),
- .TXPI_CFG3(1'b0),
- .TXPI_CFG4(1'b0),
- .TXPI_CFG5(3'b000),
- .TXPI_GREY_SEL(1'b0),
- .TXPI_INVSTROBE_SEL(1'b0),
- .TXPI_PPMCLK_SEL("TXUSRCLK2"),
- .TXPI_PPM_CFG(8'b00000000),
- .TXPI_SYNFREQ_PPM(3'b000),
- .TXPMARESET_TIME(5'b00001),
- .TXSYNC_MULTILANE(1'b0),
- .TXSYNC_OVRD(1'b0),
- .TXSYNC_SKIP_DA(1'b0),
- .TX_CLK25_DIV(5),
- .TX_CLKMUX_EN(1'b1),
- .TX_DATA_WIDTH(40),
- .TX_DEEMPH0(6'b000000),
- .TX_DEEMPH1(6'b000000),
- .TX_DRIVE_MODE("DIRECT"),
- .TX_EIDLE_ASSERT_DELAY(3'b110),
- .TX_EIDLE_DEASSERT_DELAY(3'b100),
- .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
- .TX_MAINCURSOR_SEL(1'b0),
- .TX_MARGIN_FULL_0(7'b1001110),
- .TX_MARGIN_FULL_1(7'b1001001),
- .TX_MARGIN_FULL_2(7'b1000101),
- .TX_MARGIN_FULL_3(7'b1000010),
- .TX_MARGIN_FULL_4(7'b1000000),
- .TX_MARGIN_LOW_0(7'b1000110),
- .TX_MARGIN_LOW_1(7'b1000100),
- .TX_MARGIN_LOW_2(7'b1000010),
- .TX_MARGIN_LOW_3(7'b1000000),
- .TX_MARGIN_LOW_4(7'b1000000),
- .TX_PREDRIVER_MODE(1'b0),
- .TX_RXDETECT_CFG(14'h1832),
- .TX_RXDETECT_REF(3'b100),
- .TX_XCLK_SEL("TXOUT"),
- .UCODEER_CLR(1'b0),
- .USE_PCS_CLK_PHASE_SEL(1'b0))
- gtpe2_i
- (.CFGRESET(1'b0),
- .CLKRSVD0(1'b0),
- .CLKRSVD1(1'b0),
- .DMONFIFORESET(1'b0),
- .DMONITORCLK(1'b0),
- .DMONITOROUT({gtpe2_i_n_48,gtpe2_i_n_49,gtpe2_i_n_50,gtpe2_i_n_51,gtpe2_i_n_52,gtpe2_i_n_53,gtpe2_i_n_54,gtpe2_i_n_55,gtpe2_i_n_56,gtpe2_i_n_57,gtpe2_i_n_58,gtpe2_i_n_59,gtpe2_i_n_60,gtpe2_i_n_61,gtpe2_i_n_62}),
- .DRPADDR({gtrxreset_seq_i_n_4,gtrxreset_seq_i_n_5,gtrxreset_seq_i_n_6,gtrxreset_seq_i_n_7,DRPADDR[4],gtrxreset_seq_i_n_8,gtrxreset_seq_i_n_9,gtrxreset_seq_i_n_10,DRPADDR[0]}),
- .DRPCLK(drpclk_in),
- .DRPDI(DRPDI),
- .DRPDO(DRPDO_OUT),
- .DRPEN(DRPEN),
- .DRPRDY(drpclk_in_0),
- .DRPWE(DRPWE),
- .EYESCANDATAERROR(gtpe2_i_n_1),
- .EYESCANMODE(1'b0),
- .EYESCANRESET(1'b0),
- .EYESCANTRIGGER(1'b0),
- .GTPRXN(RXN),
- .GTPRXP(RXP),
- .GTPTXN(TXN),
- .GTPTXP(TXP),
- .GTRESETSEL(1'b0),
- .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .GTRXRESET(GTRXRESET),
- .GTTXRESET(gt_tx_reset_i),
- .LOOPBACK(LOOPBACK),
- .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCSRSVDOUT(NLW_gtpe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
- .PHYSTATUS(NLW_gtpe2_i_PHYSTATUS_UNCONNECTED),
- .PLL0CLK(GT0_PLL0OUTCLK_IN),
- .PLL0REFCLK(GT0_PLL0OUTREFCLK_IN),
- .PLL1CLK(GT0_PLL1OUTCLK_IN),
- .PLL1REFCLK(GT0_PLL1OUTREFCLK_IN),
- .PMARSVDIN0(1'b0),
- .PMARSVDIN1(1'b0),
- .PMARSVDIN2(1'b0),
- .PMARSVDIN3(1'b0),
- .PMARSVDIN4(1'b0),
- .PMARSVDOUT0(NLW_gtpe2_i_PMARSVDOUT0_UNCONNECTED),
- .PMARSVDOUT1(NLW_gtpe2_i_PMARSVDOUT1_UNCONNECTED),
- .RESETOVRD(1'b0),
- .RX8B10BEN(1'b1),
- .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .RXBUFRESET(1'b0),
- .RXBUFSTATUS({rx_buf_err_i,gtpe2_i_n_104,gtpe2_i_n_105}),
- .RXBYTEISALIGNED(gtpe2_i_n_7),
- .RXBYTEREALIGN(rx_realign_i),
- .RXCDRFREQRESET(1'b0),
- .RXCDRHOLD(1'b0),
- .RXCDRLOCK(gtpe2_i_n_9),
- .RXCDROVRDEN(1'b0),
- .RXCDRRESET(1'b0),
- .RXCDRRESETRSV(1'b0),
- .RXCHANBONDSEQ(NLW_gtpe2_i_RXCHANBONDSEQ_UNCONNECTED),
- .RXCHANISALIGNED(NLW_gtpe2_i_RXCHANISALIGNED_UNCONNECTED),
- .RXCHANREALIGN(NLW_gtpe2_i_RXCHANREALIGN_UNCONNECTED),
- .RXCHARISCOMMA(D),
- .RXCHARISK(RXCHARISK),
- .RXCHBONDEN(1'b0),
- .RXCHBONDI({1'b0,1'b0,1'b0,1'b0}),
- .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
- .RXCHBONDMASTER(1'b0),
- .RXCHBONDO(NLW_gtpe2_i_RXCHBONDO_UNCONNECTED[3:0]),
- .RXCHBONDSLAVE(1'b0),
- .RXCLKCORCNT({gtpe2_i_n_95,gtpe2_i_n_96}),
- .RXCOMINITDET(NLW_gtpe2_i_RXCOMINITDET_UNCONNECTED),
- .RXCOMMADET(gtpe2_i_n_14),
- .RXCOMMADETEN(1'b1),
- .RXCOMSASDET(NLW_gtpe2_i_RXCOMSASDET_UNCONNECTED),
- .RXCOMWAKEDET(NLW_gtpe2_i_RXCOMWAKEDET_UNCONNECTED),
- .RXDATA(RXDATA),
- .RXDATAVALID(NLW_gtpe2_i_RXDATAVALID_UNCONNECTED[1:0]),
- .RXDDIEN(1'b0),
- .RXDFEXYDEN(1'b0),
- .RXDISPERR({RXDISPERR[1],rx_disp_err_i,RXDISPERR[0]}),
- .RXDLYBYPASS(1'b1),
- .RXDLYEN(1'b0),
- .RXDLYOVRDEN(1'b0),
- .RXDLYSRESET(1'b0),
- .RXDLYSRESETDONE(NLW_gtpe2_i_RXDLYSRESETDONE_UNCONNECTED),
- .RXELECIDLE(NLW_gtpe2_i_RXELECIDLE_UNCONNECTED),
- .RXELECIDLEMODE({1'b1,1'b1}),
- .RXGEARBOXSLIP(1'b0),
- .RXHEADER(NLW_gtpe2_i_RXHEADER_UNCONNECTED[2:0]),
- .RXHEADERVALID(NLW_gtpe2_i_RXHEADERVALID_UNCONNECTED),
- .RXLPMHFHOLD(1'b0),
- .RXLPMHFOVRDEN(1'b0),
- .RXLPMLFHOLD(1'b0),
- .RXLPMLFOVRDEN(1'b0),
- .RXLPMOSINTNTRLEN(1'b0),
- .RXLPMRESET(1'b0),
- .RXMCOMMAALIGNEN(ena_comma_align_i),
- .RXNOTINTABLE({RXNOTINTABLE[1],rx_not_in_table_i,RXNOTINTABLE[0]}),
- .RXOOBRESET(1'b0),
- .RXOSCALRESET(1'b0),
- .RXOSHOLD(1'b0),
- .RXOSINTCFG({1'b0,1'b0,1'b1,1'b0}),
- .RXOSINTDONE(NLW_gtpe2_i_RXOSINTDONE_UNCONNECTED),
- .RXOSINTEN(1'b1),
- .RXOSINTHOLD(1'b0),
- .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
- .RXOSINTNTRLEN(1'b0),
- .RXOSINTOVRDEN(1'b0),
- .RXOSINTPD(1'b0),
- .RXOSINTSTARTED(NLW_gtpe2_i_RXOSINTSTARTED_UNCONNECTED),
- .RXOSINTSTROBE(1'b0),
- .RXOSINTSTROBEDONE(NLW_gtpe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
- .RXOSINTSTROBESTARTED(NLW_gtpe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
- .RXOSINTTESTOVRDEN(1'b0),
- .RXOSOVRDEN(1'b0),
- .RXOUTCLK(gtpe2_i_n_24),
- .RXOUTCLKFABRIC(NLW_gtpe2_i_RXOUTCLKFABRIC_UNCONNECTED),
- .RXOUTCLKPCS(NLW_gtpe2_i_RXOUTCLKPCS_UNCONNECTED),
- .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
- .RXPCOMMAALIGNEN(ena_comma_align_i),
- .RXPCSRESET(1'b0),
- .RXPD({POWER_DOWN,POWER_DOWN}),
- .RXPHALIGN(1'b0),
- .RXPHALIGNDONE(NLW_gtpe2_i_RXPHALIGNDONE_UNCONNECTED),
- .RXPHALIGNEN(1'b0),
- .RXPHDLYPD(1'b0),
- .RXPHDLYRESET(1'b0),
- .RXPHMONITOR(NLW_gtpe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
- .RXPHOVRDEN(1'b0),
- .RXPHSLIPMONITOR(NLW_gtpe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
- .RXPMARESET(1'b0),
- .RXPMARESETDONE(gtpe2_i_n_28),
- .RXPOLARITY(rx_polarity_i),
- .RXPRBSCNTRESET(1'b0),
- .RXPRBSERR(gtpe2_i_n_29),
- .RXPRBSSEL({1'b0,1'b0,1'b0}),
- .RXRATE({1'b0,1'b0,1'b0}),
- .RXRATEDONE(NLW_gtpe2_i_RXRATEDONE_UNCONNECTED),
- .RXRATEMODE(1'b0),
- .RXRESETDONE(drpclk_in_1),
- .RXSLIDE(1'b0),
- .RXSTARTOFSEQ(NLW_gtpe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
- .RXSTATUS(NLW_gtpe2_i_RXSTATUS_UNCONNECTED[2:0]),
- .RXSYNCALLIN(1'b0),
- .RXSYNCDONE(NLW_gtpe2_i_RXSYNCDONE_UNCONNECTED),
- .RXSYNCIN(1'b0),
- .RXSYNCMODE(1'b0),
- .RXSYNCOUT(NLW_gtpe2_i_RXSYNCOUT_UNCONNECTED),
- .RXSYSCLKSEL({1'b0,1'b0}),
- .RXUSERRDY(gt_rxuserrdy_i),
- .RXUSRCLK(sync_clk),
- .RXUSRCLK2(user_clk),
- .RXVALID(NLW_gtpe2_i_RXVALID_UNCONNECTED),
- .SETERRSTATUS(1'b0),
- .SIGVALIDCLK(1'b0),
- .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0}),
- .TX8B10BEN(1'b1),
- .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
- .TXBUFSTATUS({tx_buf_err_i,gtpe2_i_n_102}),
- .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0}),
- .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0}),
- .TXCHARISK({Q[0],Q[1],Q[2],Q[3]}),
- .TXCOMFINISH(NLW_gtpe2_i_TXCOMFINISH_UNCONNECTED),
- .TXCOMINIT(1'b0),
- .TXCOMSAS(1'b0),
- .TXCOMWAKE(1'b0),
- .TXDATA(TXDATA),
- .TXDEEMPH(1'b0),
- .TXDETECTRX(1'b0),
- .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}),
- .TXDIFFPD(1'b0),
- .TXDLYBYPASS(1'b1),
- .TXDLYEN(1'b0),
- .TXDLYHOLD(1'b0),
- .TXDLYOVRDEN(1'b0),
- .TXDLYSRESET(1'b0),
- .TXDLYSRESETDONE(NLW_gtpe2_i_TXDLYSRESETDONE_UNCONNECTED),
- .TXDLYUPDOWN(1'b0),
- .TXELECIDLE(POWER_DOWN),
- .TXGEARBOXREADY(NLW_gtpe2_i_TXGEARBOXREADY_UNCONNECTED),
- .TXHEADER({1'b0,1'b0,1'b0}),
- .TXINHIBIT(1'b0),
- .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXMARGIN({1'b0,1'b0,1'b0}),
- .TXOUTCLK(TX_OUT_CLK),
- .TXOUTCLKFABRIC(gtpe2_i_n_39),
- .TXOUTCLKPCS(gtpe2_i_n_40),
- .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
- .TXPCSRESET(1'b0),
- .TXPD({POWER_DOWN,POWER_DOWN}),
- .TXPDELECIDLEMODE(1'b0),
- .TXPHALIGN(1'b0),
- .TXPHALIGNDONE(NLW_gtpe2_i_TXPHALIGNDONE_UNCONNECTED),
- .TXPHALIGNEN(1'b0),
- .TXPHDLYPD(1'b0),
- .TXPHDLYRESET(1'b0),
- .TXPHDLYTSTCLK(1'b0),
- .TXPHINIT(1'b0),
- .TXPHINITDONE(NLW_gtpe2_i_TXPHINITDONE_UNCONNECTED),
- .TXPHOVRDEN(1'b0),
- .TXPIPPMEN(1'b0),
- .TXPIPPMOVRDEN(1'b0),
- .TXPIPPMPD(1'b0),
- .TXPIPPMSEL(1'b1),
- .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXPISOPD(1'b0),
- .TXPMARESET(1'b0),
- .TXPMARESETDONE(NLW_gtpe2_i_TXPMARESETDONE_UNCONNECTED),
- .TXPOLARITY(1'b0),
- .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXPOSTCURSORINV(1'b0),
- .TXPRBSFORCEERR(1'b0),
- .TXPRBSSEL({1'b0,1'b0,1'b0}),
- .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXPRECURSORINV(1'b0),
- .TXRATE({1'b0,1'b0,1'b0}),
- .TXRATEDONE(NLW_gtpe2_i_TXRATEDONE_UNCONNECTED),
- .TXRATEMODE(1'b0),
- .TXRESETDONE(drpclk_in_2),
- .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .TXSTARTSEQ(1'b0),
- .TXSWING(1'b0),
- .TXSYNCALLIN(1'b0),
- .TXSYNCDONE(NLW_gtpe2_i_TXSYNCDONE_UNCONNECTED),
- .TXSYNCIN(1'b0),
- .TXSYNCMODE(1'b0),
- .TXSYNCOUT(NLW_gtpe2_i_TXSYNCOUT_UNCONNECTED),
- .TXSYSCLKSEL({1'b0,1'b0}),
- .TXUSERRDY(gt_txuserrdy_i),
- .TXUSRCLK(sync_clk),
- .TXUSRCLK2(user_clk));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_10
- (.I0(DRPDI_IN[8]),
- .I1(in7[8]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[8]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_11
- (.I0(DRPDI_IN[7]),
- .I1(in7[7]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[7]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_12
- (.I0(DRPDI_IN[6]),
- .I1(in7[6]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[6]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_13
- (.I0(DRPDI_IN[5]),
- .I1(in7[5]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[5]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_14
- (.I0(DRPDI_IN[4]),
- .I1(in7[4]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[4]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_15
- (.I0(DRPDI_IN[3]),
- .I1(in7[3]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[3]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_16
- (.I0(DRPDI_IN[2]),
- .I1(in7[2]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[2]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_17
- (.I0(DRPDI_IN[1]),
- .I1(in7[1]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[1]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_18
- (.I0(DRPDI_IN[0]),
- .I1(in7[0]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[0]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_3
- (.I0(DRPDI_IN[15]),
- .I1(in7[15]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[15]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_4
- (.I0(DRPDI_IN[14]),
- .I1(in7[14]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[14]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_5
- (.I0(DRPDI_IN[13]),
- .I1(in7[13]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[13]));
- LUT2 #(
- .INIT(4'hB))
- gtpe2_i_i_55
- (.I0(DRPADDR_IN[4]),
- .I1(drp_op_done),
- .O(DRPADDR[4]));
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT2 #(
- .INIT(4'hB))
- gtpe2_i_i_59
- (.I0(DRPADDR_IN[0]),
- .I1(drp_op_done),
- .O(DRPADDR[0]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_6
- (.I0(DRPDI_IN[12]),
- .I1(in7[12]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[12]));
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT4 #(
- .INIT(16'hAAC0))
- gtpe2_i_i_7
- (.I0(DRPDI_IN[11]),
- .I1(p_0_in),
- .I2(gtrxreset_seq_i_n_17),
- .I3(drp_op_done),
- .O(DRPDI[11]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_8
- (.I0(DRPDI_IN[10]),
- .I1(in7[10]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[10]));
- LUT5 #(
- .INIT(32'hAAAACCC0))
- gtpe2_i_i_9
- (.I0(DRPDI_IN[9]),
- .I1(in7[9]),
- .I2(gtrxreset_seq_i_n_2),
- .I3(p_0_in),
- .I4(drp_op_done),
- .O(DRPDI[9]));
- north_channel_north_channel_gtrxreset_seq gtrxreset_seq_i
- (.DRPADDR({gtrxreset_seq_i_n_4,gtrxreset_seq_i_n_5,gtrxreset_seq_i_n_6,gtrxreset_seq_i_n_7,gtrxreset_seq_i_n_8,gtrxreset_seq_i_n_9,gtrxreset_seq_i_n_10}),
- .DRPADDR_IN({DRPADDR_IN[8:5],DRPADDR_IN[3:1]}),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN(DRPEN),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE(DRPWE),
- .DRPWE_IN(DRPWE_IN),
- .GTRXRESET(GTRXRESET),
- .Q({gtrxreset_seq_i_n_2,p_0_in}),
- .SR(SR),
- .drp_op_done(drp_op_done),
- .drpclk_in(drpclk_in),
- .gt_common_reset_out(gt_common_reset_out),
- .in0(gtpe2_i_n_28),
- .init_clk_in(init_clk_in),
- .\rd_data_reg[0]_0 (drpclk_in_0),
- .\rd_data_reg[15]_0 ({in7[15:12],gtrxreset_seq_i_n_17,in7[10:0]}));
- LUT3 #(
- .INIT(8'hFE))
- hard_err_gt_i_1
- (.I0(rx_realign_i),
- .I1(tx_buf_err_i),
- .I2(rx_buf_err_i),
- .O(hard_err_gt0));
- LUT6 #(
- .INIT(64'hFFFFFF5700028200))
- \left_align_select_r[0]_i_1
- (.I0(\left_align_select_r_reg[0]_0 ),
- .I1(RXCHARISK[1]),
- .I2(RXCHARISK[0]),
- .I3(RXCHARISK[2]),
- .I4(RXCHARISK[3]),
- .I5(\left_align_select_r_reg[0]_1 ),
- .O(\left_align_select_r_reg[0] ));
- LUT6 #(
- .INIT(64'hFFFF7DDF00020088))
- \left_align_select_r[1]_i_1
- (.I0(\left_align_select_r_reg[0]_0 ),
- .I1(RXCHARISK[1]),
- .I2(RXCHARISK[0]),
- .I3(RXCHARISK[2]),
- .I4(RXCHARISK[3]),
- .I5(\left_align_select_r_reg[1]_4 ),
- .O(\left_align_select_r_reg[1] ));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT5 #(
- .INIT(32'h0F0F0F0E))
- reset_count_r_i_3
- (.I0(rx_disp_err_i[2]),
- .I1(rx_not_in_table_i[2]),
- .I2(tx_reset_i),
- .I3(rx_disp_err_i[1]),
- .I4(rx_not_in_table_i[1]),
- .O(rst_r_reg));
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[0]_i_2
- (.I0(RXDISPERR[0]),
- .I1(RXNOTINTABLE[0]),
- .O(drpclk_in_5));
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[1]_i_1
- (.I0(rx_disp_err_i[1]),
- .I1(rx_not_in_table_i[1]),
- .O(drpclk_in_3));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[2]_i_1
- (.I0(rx_disp_err_i[2]),
- .I1(rx_not_in_table_i[2]),
- .O(drpclk_in_4));
- LUT2 #(
- .INIT(4'hE))
- \soft_err_r[3]_i_1
- (.I0(RXDISPERR[1]),
- .I1(RXNOTINTABLE[1]),
- .O(drpclk_in_6));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[2]_i_1
- (.I0(RXCHARISK[1]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXCHARISK[0]),
- .I4(\word_aligned_control_bits_r_reg[2] ),
- .I5(RXCHARISK[2]),
- .O(\left_align_select_r_reg[1]_2 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_control_bits_r[3]_i_1
- (.I0(RXCHARISK[2]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXCHARISK[1]),
- .I4(RXCHARISK[0]),
- .I5(RXCHARISK[3]),
- .O(\left_align_select_r_reg[1]_3 ));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[16]_i_1
- (.I0(RXDATA[15]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[7]),
- .I4(\word_aligned_data_r_reg[16] [7]),
- .I5(RXDATA[23]),
- .O(\left_align_select_r_reg[1]_0 [7]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[17]_i_1
- (.I0(RXDATA[14]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[6]),
- .I4(\word_aligned_data_r_reg[16] [6]),
- .I5(RXDATA[22]),
- .O(\left_align_select_r_reg[1]_0 [6]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[18]_i_1
- (.I0(RXDATA[13]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[5]),
- .I4(\word_aligned_data_r_reg[16] [5]),
- .I5(RXDATA[21]),
- .O(\left_align_select_r_reg[1]_0 [5]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[19]_i_1
- (.I0(RXDATA[12]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[4]),
- .I4(\word_aligned_data_r_reg[16] [4]),
- .I5(RXDATA[20]),
- .O(\left_align_select_r_reg[1]_0 [4]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[20]_i_1
- (.I0(RXDATA[11]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[3]),
- .I4(\word_aligned_data_r_reg[16] [3]),
- .I5(RXDATA[19]),
- .O(\left_align_select_r_reg[1]_0 [3]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[21]_i_1
- (.I0(RXDATA[10]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[2]),
- .I4(\word_aligned_data_r_reg[16] [2]),
- .I5(RXDATA[18]),
- .O(\left_align_select_r_reg[1]_0 [2]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[22]_i_1
- (.I0(RXDATA[9]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[1]),
- .I4(\word_aligned_data_r_reg[16] [1]),
- .I5(RXDATA[17]),
- .O(\left_align_select_r_reg[1]_0 [1]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[23]_i_1
- (.I0(RXDATA[8]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[0]),
- .I4(\word_aligned_data_r_reg[16] [0]),
- .I5(RXDATA[16]),
- .O(\left_align_select_r_reg[1]_0 [0]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[24]_i_1
- (.I0(RXDATA[23]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[15]),
- .I4(RXDATA[7]),
- .I5(RXDATA[31]),
- .O(\left_align_select_r_reg[1]_1 [7]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[25]_i_1
- (.I0(RXDATA[22]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[14]),
- .I4(RXDATA[6]),
- .I5(RXDATA[30]),
- .O(\left_align_select_r_reg[1]_1 [6]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[26]_i_1
- (.I0(RXDATA[21]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[13]),
- .I4(RXDATA[5]),
- .I5(RXDATA[29]),
- .O(\left_align_select_r_reg[1]_1 [5]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[27]_i_1
- (.I0(RXDATA[20]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[12]),
- .I4(RXDATA[4]),
- .I5(RXDATA[28]),
- .O(\left_align_select_r_reg[1]_1 [4]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[28]_i_1
- (.I0(RXDATA[19]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[11]),
- .I4(RXDATA[3]),
- .I5(RXDATA[27]),
- .O(\left_align_select_r_reg[1]_1 [3]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[29]_i_1
- (.I0(RXDATA[18]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[10]),
- .I4(RXDATA[2]),
- .I5(RXDATA[26]),
- .O(\left_align_select_r_reg[1]_1 [2]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[30]_i_1
- (.I0(RXDATA[17]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[9]),
- .I4(RXDATA[1]),
- .I5(RXDATA[25]),
- .O(\left_align_select_r_reg[1]_1 [1]));
- LUT6 #(
- .INIT(64'hBF8FB383BC8CB080))
- \word_aligned_data_r[31]_i_1
- (.I0(RXDATA[16]),
- .I1(\left_align_select_r_reg[1]_4 ),
- .I2(\left_align_select_r_reg[0]_1 ),
- .I3(RXDATA[8]),
- .I4(RXDATA[0]),
- .I5(RXDATA[24]),
- .O(\left_align_select_r_reg[1]_1 [0]));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_gtrxreset_seq" *)
-module north_channel_north_channel_gtrxreset_seq
- (GTRXRESET,
- drp_op_done,
- Q,
- DRPADDR,
- DRPWE,
- DRPEN,
- \rd_data_reg[15]_0 ,
- in0,
- drpclk_in,
- gt_common_reset_out,
- init_clk_in,
- SR,
- \rd_data_reg[0]_0 ,
- DRPADDR_IN,
- DRPWE_IN,
- DRPEN_IN,
- DRPDO_OUT);
- output GTRXRESET;
- output drp_op_done;
- output [1:0]Q;
- output [6:0]DRPADDR;
- output DRPWE;
- output DRPEN;
- output [15:0]\rd_data_reg[15]_0 ;
- input in0;
- input drpclk_in;
- input gt_common_reset_out;
- input init_clk_in;
- input [0:0]SR;
- input \rd_data_reg[0]_0 ;
- input [6:0]DRPADDR_IN;
- input DRPWE_IN;
- input DRPEN_IN;
- input [15:0]DRPDO_OUT;
-
- wire [6:0]DRPADDR;
- wire [6:0]DRPADDR_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN;
- wire DRPEN_IN;
- wire DRPWE;
- wire DRPWE_IN;
- wire \FSM_onehot_state[0]_i_1_n_0 ;
- wire \FSM_onehot_state[1]_i_1_n_0 ;
- wire \FSM_onehot_state[2]_i_1_n_0 ;
- wire \FSM_onehot_state[3]_i_1_n_0 ;
- wire \FSM_onehot_state[4]_i_1_n_0 ;
- wire \FSM_onehot_state[5]_i_1_n_0 ;
- wire \FSM_onehot_state[6]_i_1_n_0 ;
- wire \FSM_onehot_state[7]_i_1_n_0 ;
- wire \FSM_onehot_state_reg_n_0_[1] ;
- wire \FSM_onehot_state_reg_n_0_[3] ;
- wire \FSM_onehot_state_reg_n_0_[4] ;
- wire \FSM_onehot_state_reg_n_0_[7] ;
- wire GTRXRESET;
- wire [1:0]Q;
- wire [0:0]SR;
- wire drp_op_done;
- wire drp_op_done_o_i_1_n_0;
- wire drpclk_in;
- wire flag;
- wire flag_i_1_n_0;
- wire flag_reg_n_0;
- wire gt_common_reset_out;
- wire gtrxreset_f;
- wire gtrxreset_i__0;
- wire gtrxreset_s;
- wire gtrxreset_ss;
- wire in0;
- wire init_clk_in;
- wire next_rd_data;
- wire [15:0]original_rd_data;
- wire original_rd_data0;
- wire p_0_in0_in;
- wire \rd_data[0]_i_1_n_0 ;
- wire \rd_data[10]_i_1_n_0 ;
- wire \rd_data[11]_i_1_n_0 ;
- wire \rd_data[12]_i_1_n_0 ;
- wire \rd_data[13]_i_1_n_0 ;
- wire \rd_data[14]_i_1_n_0 ;
- wire \rd_data[15]_i_2_n_0 ;
- wire \rd_data[1]_i_1_n_0 ;
- wire \rd_data[2]_i_1_n_0 ;
- wire \rd_data[3]_i_1_n_0 ;
- wire \rd_data[4]_i_1_n_0 ;
- wire \rd_data[5]_i_1_n_0 ;
- wire \rd_data[6]_i_1_n_0 ;
- wire \rd_data[7]_i_1_n_0 ;
- wire \rd_data[8]_i_1_n_0 ;
- wire \rd_data[9]_i_1_n_0 ;
- wire \rd_data_reg[0]_0 ;
- wire [15:0]\rd_data_reg[15]_0 ;
- wire rst_ss;
- wire rxpmaresetdone_ss;
- wire rxpmaresetdone_sss;
-
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT3 #(
- .INIT(8'hBA))
- \FSM_onehot_state[0]_i_1
- (.I0(Q[0]),
- .I1(\rd_data_reg[0]_0 ),
- .I2(flag),
- .O(\FSM_onehot_state[0]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h8F88))
- \FSM_onehot_state[1]_i_1
- (.I0(\rd_data_reg[0]_0 ),
- .I1(flag),
- .I2(gtrxreset_ss),
- .I3(\FSM_onehot_state_reg_n_0_[1] ),
- .O(\FSM_onehot_state[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT3 #(
- .INIT(8'h20))
- \FSM_onehot_state[2]_i_1
- (.I0(\FSM_onehot_state_reg_n_0_[3] ),
- .I1(rxpmaresetdone_ss),
- .I2(rxpmaresetdone_sss),
- .O(\FSM_onehot_state[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT5 #(
- .INIT(32'hFFD0D0D0))
- \FSM_onehot_state[3]_i_1
- (.I0(rxpmaresetdone_sss),
- .I1(rxpmaresetdone_ss),
- .I2(\FSM_onehot_state_reg_n_0_[3] ),
- .I3(\rd_data_reg[0]_0 ),
- .I4(\FSM_onehot_state_reg_n_0_[4] ),
- .O(\FSM_onehot_state[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT3 #(
- .INIT(8'hBA))
- \FSM_onehot_state[4]_i_1
- (.I0(Q[1]),
- .I1(\rd_data_reg[0]_0 ),
- .I2(\FSM_onehot_state_reg_n_0_[4] ),
- .O(\FSM_onehot_state[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT2 #(
- .INIT(4'h8))
- \FSM_onehot_state[5]_i_1
- (.I0(p_0_in0_in),
- .I1(\rd_data_reg[0]_0 ),
- .O(\FSM_onehot_state[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT3 #(
- .INIT(8'hBA))
- \FSM_onehot_state[6]_i_1
- (.I0(\FSM_onehot_state_reg_n_0_[7] ),
- .I1(\rd_data_reg[0]_0 ),
- .I2(p_0_in0_in),
- .O(\FSM_onehot_state[6]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \FSM_onehot_state[7]_i_1
- (.I0(\FSM_onehot_state_reg_n_0_[1] ),
- .I1(gtrxreset_ss),
- .O(\FSM_onehot_state[7]_i_1_n_0 ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[0]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[0]_i_1_n_0 ),
- .Q(flag));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDPE #(
- .INIT(1'b1))
- \FSM_onehot_state_reg[1]
- (.C(drpclk_in),
- .CE(1'b1),
- .D(\FSM_onehot_state[1]_i_1_n_0 ),
- .PRE(rst_ss),
- .Q(\FSM_onehot_state_reg_n_0_[1] ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[2]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[2]_i_1_n_0 ),
- .Q(Q[0]));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[3]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[3]_i_1_n_0 ),
- .Q(\FSM_onehot_state_reg_n_0_[3] ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[4]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[4]_i_1_n_0 ),
- .Q(\FSM_onehot_state_reg_n_0_[4] ));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[5]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[5]_i_1_n_0 ),
- .Q(Q[1]));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[6]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[6]_i_1_n_0 ),
- .Q(p_0_in0_in));
- (* FSM_ENCODED_STATES = "drp_rd:10000000,wait_rd_data:01000000,wr_16:00100000,wait_wr_done1:00010000,wait_pmareset:00001000,wr_20:00000100,wait_wr_done2:00000001,idle:00000010" *)
- FDCE #(
- .INIT(1'b0))
- \FSM_onehot_state_reg[7]
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(\FSM_onehot_state[7]_i_1_n_0 ),
- .Q(\FSM_onehot_state_reg_n_0_[7] ));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT3 #(
- .INIT(8'hF8))
- drp_op_done_o_i_1
- (.I0(\rd_data_reg[0]_0 ),
- .I1(flag),
- .I2(drp_op_done),
- .O(drp_op_done_o_i_1_n_0));
- FDCE drp_op_done_o_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(gtrxreset_f),
- .D(drp_op_done_o_i_1_n_0),
- .Q(drp_op_done));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFF4))
- flag_i_1
- (.I0(flag),
- .I1(flag_reg_n_0),
- .I2(Q[0]),
- .I3(\FSM_onehot_state_reg_n_0_[3] ),
- .I4(Q[1]),
- .I5(\FSM_onehot_state_reg_n_0_[4] ),
- .O(flag_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- flag_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .D(flag_i_1_n_0),
- .Q(flag_reg_n_0),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hBBBBBBB8))
- gtpe2_i_i_1
- (.I0(DRPEN_IN),
- .I1(drp_op_done),
- .I2(Q[1]),
- .I3(Q[0]),
- .I4(\FSM_onehot_state_reg_n_0_[7] ),
- .O(DRPEN));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT4 #(
- .INIT(16'hBBB8))
- gtpe2_i_i_2
- (.I0(DRPWE_IN),
- .I1(drp_op_done),
- .I2(Q[0]),
- .I3(Q[1]),
- .O(DRPWE));
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_51
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[6]),
- .O(DRPADDR[6]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_52
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[5]),
- .O(DRPADDR[5]));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_53
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[4]),
- .O(DRPADDR[4]));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_54
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[3]),
- .O(DRPADDR[3]));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_56
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[2]),
- .O(DRPADDR[2]));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_57
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[1]),
- .O(DRPADDR[1]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT2 #(
- .INIT(4'h8))
- gtpe2_i_i_58
- (.I0(drp_op_done),
- .I1(DRPADDR_IN[0]),
- .O(DRPADDR[0]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFEEE))
- gtrxreset_i
- (.I0(\FSM_onehot_state_reg_n_0_[7] ),
- .I1(\FSM_onehot_state_reg_n_0_[4] ),
- .I2(gtrxreset_ss),
- .I3(\FSM_onehot_state_reg_n_0_[3] ),
- .I4(p_0_in0_in),
- .I5(Q[1]),
- .O(gtrxreset_i__0));
- north_channel_north_channel_cdc_sync__parameterized6_6 gtrxreset_in_cdc_sync
- (.SR(SR),
- .drpclk_in(drpclk_in),
- .init_clk_in(init_clk_in),
- .out(gtrxreset_f));
- FDCE gtrxreset_o_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(gtrxreset_i__0),
- .Q(GTRXRESET));
- FDCE gtrxreset_s_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(gtrxreset_f),
- .Q(gtrxreset_s));
- FDCE gtrxreset_ss_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(gtrxreset_s),
- .Q(gtrxreset_ss));
- LUT3 #(
- .INIT(8'h40))
- \original_rd_data[15]_i_1
- (.I0(flag_reg_n_0),
- .I1(\rd_data_reg[0]_0 ),
- .I2(p_0_in0_in),
- .O(original_rd_data0));
- FDRE \original_rd_data_reg[0]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[0]),
- .Q(original_rd_data[0]),
- .R(1'b0));
- FDRE \original_rd_data_reg[10]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[10]),
- .Q(original_rd_data[10]),
- .R(1'b0));
- FDRE \original_rd_data_reg[11]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[11]),
- .Q(original_rd_data[11]),
- .R(1'b0));
- FDRE \original_rd_data_reg[12]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[12]),
- .Q(original_rd_data[12]),
- .R(1'b0));
- FDRE \original_rd_data_reg[13]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[13]),
- .Q(original_rd_data[13]),
- .R(1'b0));
- FDRE \original_rd_data_reg[14]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[14]),
- .Q(original_rd_data[14]),
- .R(1'b0));
- FDRE \original_rd_data_reg[15]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[15]),
- .Q(original_rd_data[15]),
- .R(1'b0));
- FDRE \original_rd_data_reg[1]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[1]),
- .Q(original_rd_data[1]),
- .R(1'b0));
- FDRE \original_rd_data_reg[2]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[2]),
- .Q(original_rd_data[2]),
- .R(1'b0));
- FDRE \original_rd_data_reg[3]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[3]),
- .Q(original_rd_data[3]),
- .R(1'b0));
- FDRE \original_rd_data_reg[4]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[4]),
- .Q(original_rd_data[4]),
- .R(1'b0));
- FDRE \original_rd_data_reg[5]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[5]),
- .Q(original_rd_data[5]),
- .R(1'b0));
- FDRE \original_rd_data_reg[6]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[6]),
- .Q(original_rd_data[6]),
- .R(1'b0));
- FDRE \original_rd_data_reg[7]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[7]),
- .Q(original_rd_data[7]),
- .R(1'b0));
- FDRE \original_rd_data_reg[8]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[8]),
- .Q(original_rd_data[8]),
- .R(1'b0));
- FDRE \original_rd_data_reg[9]
- (.C(drpclk_in),
- .CE(original_rd_data0),
- .D(DRPDO_OUT[9]),
- .Q(original_rd_data[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[0]_i_1
- (.I0(DRPDO_OUT[0]),
- .I1(original_rd_data[0]),
- .I2(flag_reg_n_0),
- .O(\rd_data[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[10]_i_1
- (.I0(DRPDO_OUT[10]),
- .I1(original_rd_data[10]),
- .I2(flag_reg_n_0),
- .O(\rd_data[10]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[11]_i_1
- (.I0(DRPDO_OUT[11]),
- .I1(original_rd_data[11]),
- .I2(flag_reg_n_0),
- .O(\rd_data[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[12]_i_1
- (.I0(DRPDO_OUT[12]),
- .I1(original_rd_data[12]),
- .I2(flag_reg_n_0),
- .O(\rd_data[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[13]_i_1
- (.I0(DRPDO_OUT[13]),
- .I1(original_rd_data[13]),
- .I2(flag_reg_n_0),
- .O(\rd_data[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[14]_i_1
- (.I0(DRPDO_OUT[14]),
- .I1(original_rd_data[14]),
- .I2(flag_reg_n_0),
- .O(\rd_data[14]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \rd_data[15]_i_1
- (.I0(p_0_in0_in),
- .I1(\rd_data_reg[0]_0 ),
- .O(next_rd_data));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[15]_i_2
- (.I0(DRPDO_OUT[15]),
- .I1(original_rd_data[15]),
- .I2(flag_reg_n_0),
- .O(\rd_data[15]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[1]_i_1
- (.I0(DRPDO_OUT[1]),
- .I1(original_rd_data[1]),
- .I2(flag_reg_n_0),
- .O(\rd_data[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[2]_i_1
- (.I0(DRPDO_OUT[2]),
- .I1(original_rd_data[2]),
- .I2(flag_reg_n_0),
- .O(\rd_data[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[3]_i_1
- (.I0(DRPDO_OUT[3]),
- .I1(original_rd_data[3]),
- .I2(flag_reg_n_0),
- .O(\rd_data[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[4]_i_1
- (.I0(DRPDO_OUT[4]),
- .I1(original_rd_data[4]),
- .I2(flag_reg_n_0),
- .O(\rd_data[4]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[5]_i_1
- (.I0(DRPDO_OUT[5]),
- .I1(original_rd_data[5]),
- .I2(flag_reg_n_0),
- .O(\rd_data[5]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[6]_i_1
- (.I0(DRPDO_OUT[6]),
- .I1(original_rd_data[6]),
- .I2(flag_reg_n_0),
- .O(\rd_data[6]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[7]_i_1
- (.I0(DRPDO_OUT[7]),
- .I1(original_rd_data[7]),
- .I2(flag_reg_n_0),
- .O(\rd_data[7]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[8]_i_1
- (.I0(DRPDO_OUT[8]),
- .I1(original_rd_data[8]),
- .I2(flag_reg_n_0),
- .O(\rd_data[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT3 #(
- .INIT(8'hCA))
- \rd_data[9]_i_1
- (.I0(DRPDO_OUT[9]),
- .I1(original_rd_data[9]),
- .I2(flag_reg_n_0),
- .O(\rd_data[9]_i_1_n_0 ));
- FDCE \rd_data_reg[0]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[0]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [0]));
- FDCE \rd_data_reg[10]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[10]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [10]));
- FDCE \rd_data_reg[11]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[11]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [11]));
- FDCE \rd_data_reg[12]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[12]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [12]));
- FDCE \rd_data_reg[13]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[13]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [13]));
- FDCE \rd_data_reg[14]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[14]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [14]));
- FDCE \rd_data_reg[15]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[15]_i_2_n_0 ),
- .Q(\rd_data_reg[15]_0 [15]));
- FDCE \rd_data_reg[1]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[1]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [1]));
- FDCE \rd_data_reg[2]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[2]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [2]));
- FDCE \rd_data_reg[3]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[3]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [3]));
- FDCE \rd_data_reg[4]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[4]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [4]));
- FDCE \rd_data_reg[5]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[5]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [5]));
- FDCE \rd_data_reg[6]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[6]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [6]));
- FDCE \rd_data_reg[7]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[7]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [7]));
- FDCE \rd_data_reg[8]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[8]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [8]));
- FDCE \rd_data_reg[9]
- (.C(drpclk_in),
- .CE(next_rd_data),
- .CLR(rst_ss),
- .D(\rd_data[9]_i_1_n_0 ),
- .Q(\rd_data_reg[15]_0 [9]));
- north_channel_north_channel_cdc_sync__parameterized6_7 rst_cdc_sync
- (.AR(rst_ss),
- .drpclk_in(drpclk_in),
- .gt_common_reset_out(gt_common_reset_out),
- .init_clk_in(init_clk_in));
- north_channel_north_channel_cdc_sync__parameterized1_8 rxpmaresetdone_cdc_sync
- (.drpclk_in(drpclk_in),
- .in0(in0),
- .out(rxpmaresetdone_ss));
- FDCE rxpmaresetdone_sss_reg
- (.C(drpclk_in),
- .CE(1'b1),
- .CLR(rst_ss),
- .D(rxpmaresetdone_ss),
- .Q(rxpmaresetdone_sss));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_multi_gt" *)
-module north_channel_north_channel_multi_gt
- (drpclk_in_0,
- TXN,
- TXP,
- rx_realign_i,
- drpclk_in_1,
- TX_OUT_CLK,
- drpclk_in_2,
- DRPDO_OUT,
- RXDATA,
- D,
- RXCHARISK,
- RXDISPERR,
- RXNOTINTABLE,
- \left_align_select_r_reg[0] ,
- \left_align_select_r_reg[1] ,
- rst_r_reg,
- drpclk_in_3,
- drpclk_in_4,
- drpclk_in_5,
- drpclk_in_6,
- \left_align_select_r_reg[1]_0 ,
- \left_align_select_r_reg[1]_1 ,
- \left_align_select_r_reg[1]_2 ,
- \left_align_select_r_reg[1]_3 ,
- hard_err_gt0,
- drpclk_in,
- RXN,
- RXP,
- gt_tx_reset_i,
- GT0_PLL0OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTCLK_IN,
- GT0_PLL1OUTREFCLK_IN,
- ena_comma_align_i,
- rx_polarity_i,
- gt_rxuserrdy_i,
- sync_clk,
- user_clk,
- POWER_DOWN,
- gt_txuserrdy_i,
- LOOPBACK,
- TXDATA,
- Q,
- gt_common_reset_out,
- init_clk_in,
- SR,
- \left_align_select_r_reg[0]_0 ,
- \left_align_select_r_reg[0]_1 ,
- \left_align_select_r_reg[1]_4 ,
- tx_reset_i,
- \word_aligned_data_r_reg[16] ,
- \word_aligned_control_bits_r_reg[2] ,
- DRPADDR_IN,
- DRPDI_IN,
- DRPWE_IN,
- DRPEN_IN);
- output drpclk_in_0;
- output TXN;
- output TXP;
- output rx_realign_i;
- output drpclk_in_1;
- output TX_OUT_CLK;
- output drpclk_in_2;
- output [15:0]DRPDO_OUT;
- output [31:0]RXDATA;
- output [3:0]D;
- output [3:0]RXCHARISK;
- output [1:0]RXDISPERR;
- output [1:0]RXNOTINTABLE;
- output \left_align_select_r_reg[0] ;
- output \left_align_select_r_reg[1] ;
- output rst_r_reg;
- output drpclk_in_3;
- output drpclk_in_4;
- output drpclk_in_5;
- output drpclk_in_6;
- output [7:0]\left_align_select_r_reg[1]_0 ;
- output [7:0]\left_align_select_r_reg[1]_1 ;
- output \left_align_select_r_reg[1]_2 ;
- output \left_align_select_r_reg[1]_3 ;
- output hard_err_gt0;
- input drpclk_in;
- input RXN;
- input RXP;
- input gt_tx_reset_i;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- input ena_comma_align_i;
- input rx_polarity_i;
- input gt_rxuserrdy_i;
- input sync_clk;
- input user_clk;
- input POWER_DOWN;
- input gt_txuserrdy_i;
- input [2:0]LOOPBACK;
- input [31:0]TXDATA;
- input [3:0]Q;
- input gt_common_reset_out;
- input init_clk_in;
- input [0:0]SR;
- input \left_align_select_r_reg[0]_0 ;
- input \left_align_select_r_reg[0]_1 ;
- input \left_align_select_r_reg[1]_4 ;
- input tx_reset_i;
- input [7:0]\word_aligned_data_r_reg[16] ;
- input [0:0]\word_aligned_control_bits_r_reg[2] ;
- input [8:0]DRPADDR_IN;
- input [15:0]DRPDI_IN;
- input DRPWE_IN;
- input DRPEN_IN;
-
- wire [3:0]D;
- wire [8:0]DRPADDR_IN;
- wire [15:0]DRPDI_IN;
- wire [15:0]DRPDO_OUT;
- wire DRPEN_IN;
- wire DRPWE_IN;
- wire GT0_PLL0OUTCLK_IN;
- wire GT0_PLL0OUTREFCLK_IN;
- wire GT0_PLL1OUTCLK_IN;
- wire GT0_PLL1OUTREFCLK_IN;
- wire [2:0]LOOPBACK;
- wire POWER_DOWN;
- wire [3:0]Q;
- wire [3:0]RXCHARISK;
- wire [31:0]RXDATA;
- wire [1:0]RXDISPERR;
- wire RXN;
- wire [1:0]RXNOTINTABLE;
- wire RXP;
- wire [0:0]SR;
- wire [31:0]TXDATA;
- wire TXN;
- wire TXP;
- wire TX_OUT_CLK;
- wire drpclk_in;
- wire drpclk_in_0;
- wire drpclk_in_1;
- wire drpclk_in_2;
- wire drpclk_in_3;
- wire drpclk_in_4;
- wire drpclk_in_5;
- wire drpclk_in_6;
- wire ena_comma_align_i;
- wire gt_common_reset_out;
- wire gt_rxuserrdy_i;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire hard_err_gt0;
- wire init_clk_in;
- wire \left_align_select_r_reg[0] ;
- wire \left_align_select_r_reg[0]_0 ;
- wire \left_align_select_r_reg[0]_1 ;
- wire \left_align_select_r_reg[1] ;
- wire [7:0]\left_align_select_r_reg[1]_0 ;
- wire [7:0]\left_align_select_r_reg[1]_1 ;
- wire \left_align_select_r_reg[1]_2 ;
- wire \left_align_select_r_reg[1]_3 ;
- wire \left_align_select_r_reg[1]_4 ;
- wire rst_r_reg;
- wire rx_polarity_i;
- wire rx_realign_i;
- wire sync_clk;
- wire tx_reset_i;
- wire user_clk;
- wire [0:0]\word_aligned_control_bits_r_reg[2] ;
- wire [7:0]\word_aligned_data_r_reg[16] ;
-
- north_channel_north_channel_gt gt0_north_channel_i
- (.D(D),
- .DRPADDR_IN(DRPADDR_IN),
- .DRPDI_IN(DRPDI_IN),
- .DRPDO_OUT(DRPDO_OUT),
- .DRPEN_IN(DRPEN_IN),
- .DRPWE_IN(DRPWE_IN),
- .GT0_PLL0OUTCLK_IN(GT0_PLL0OUTCLK_IN),
- .GT0_PLL0OUTREFCLK_IN(GT0_PLL0OUTREFCLK_IN),
- .GT0_PLL1OUTCLK_IN(GT0_PLL1OUTCLK_IN),
- .GT0_PLL1OUTREFCLK_IN(GT0_PLL1OUTREFCLK_IN),
- .LOOPBACK(LOOPBACK),
- .POWER_DOWN(POWER_DOWN),
- .Q(Q),
- .RXCHARISK(RXCHARISK),
- .RXDATA(RXDATA),
- .RXDISPERR(RXDISPERR),
- .RXN(RXN),
- .RXNOTINTABLE(RXNOTINTABLE),
- .RXP(RXP),
- .SR(SR),
- .TXDATA(TXDATA),
- .TXN(TXN),
- .TXP(TXP),
- .TX_OUT_CLK(TX_OUT_CLK),
- .drpclk_in(drpclk_in),
- .drpclk_in_0(drpclk_in_0),
- .drpclk_in_1(drpclk_in_1),
- .drpclk_in_2(drpclk_in_2),
- .drpclk_in_3(drpclk_in_3),
- .drpclk_in_4(drpclk_in_4),
- .drpclk_in_5(drpclk_in_5),
- .drpclk_in_6(drpclk_in_6),
- .ena_comma_align_i(ena_comma_align_i),
- .gt_common_reset_out(gt_common_reset_out),
- .gt_rxuserrdy_i(gt_rxuserrdy_i),
- .gt_tx_reset_i(gt_tx_reset_i),
- .gt_txuserrdy_i(gt_txuserrdy_i),
- .hard_err_gt0(hard_err_gt0),
- .init_clk_in(init_clk_in),
- .\left_align_select_r_reg[0] (\left_align_select_r_reg[0] ),
- .\left_align_select_r_reg[0]_0 (\left_align_select_r_reg[0]_0 ),
- .\left_align_select_r_reg[0]_1 (\left_align_select_r_reg[0]_1 ),
- .\left_align_select_r_reg[1] (\left_align_select_r_reg[1] ),
- .\left_align_select_r_reg[1]_0 (\left_align_select_r_reg[1]_0 ),
- .\left_align_select_r_reg[1]_1 (\left_align_select_r_reg[1]_1 ),
- .\left_align_select_r_reg[1]_2 (\left_align_select_r_reg[1]_2 ),
- .\left_align_select_r_reg[1]_3 (\left_align_select_r_reg[1]_3 ),
- .\left_align_select_r_reg[1]_4 (\left_align_select_r_reg[1]_4 ),
- .rst_r_reg(rst_r_reg),
- .rx_polarity_i(rx_polarity_i),
- .rx_realign_i(rx_realign_i),
- .sync_clk(sync_clk),
- .tx_reset_i(tx_reset_i),
- .user_clk(user_clk),
- .\word_aligned_control_bits_r_reg[2] (\word_aligned_control_bits_r_reg[2] ),
- .\word_aligned_data_r_reg[16] (\word_aligned_data_r_reg[16] ));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_rx_startup_fsm" *)
-module north_channel_north_channel_rx_startup_fsm
- (gtrxreset_i,
- gt_rxuserrdy_i,
- quad1_common_lock_in,
- init_clk_in,
- user_clk,
- rxfsm_rxresetdone_r,
- AR,
- \FSM_sequential_rx_state_reg[0]_0 ,
- gt_txuserrdy_i);
- output gtrxreset_i;
- output gt_rxuserrdy_i;
- input quad1_common_lock_in;
- input init_clk_in;
- input user_clk;
- input rxfsm_rxresetdone_r;
- input [0:0]AR;
- input \FSM_sequential_rx_state_reg[0]_0 ;
- input gt_txuserrdy_i;
-
- wire [0:0]AR;
- wire \FSM_sequential_rx_state[0]_i_2_n_0 ;
- wire \FSM_sequential_rx_state[1]_i_2_n_0 ;
- wire \FSM_sequential_rx_state[2]_i_1_n_0 ;
- wire \FSM_sequential_rx_state[2]_i_2_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_10_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_11_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_3_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_4_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_6_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_7_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_8_n_0 ;
- wire \FSM_sequential_rx_state[3]_i_9_n_0 ;
- wire \FSM_sequential_rx_state_reg[0]_0 ;
- wire RXUSERRDY_i_1_n_0;
- wire check_tlock_max;
- wire check_tlock_max_i_1_n_0;
- wire check_tlock_max_reg_n_0;
- wire gt_rxuserrdy_i;
- wire gt_txuserrdy_i;
- wire gtrxreset_i;
- wire gtrxreset_i_i_1_n_0;
- wire init_clk_in;
- wire init_wait_count;
- wire \init_wait_count[6]_i_3__0_n_0 ;
- wire \init_wait_count[6]_i_4__0_n_0 ;
- wire [6:0]init_wait_count_reg;
- wire init_wait_done_i_1__0_n_0;
- wire init_wait_done_reg_n_0;
- wire \mmcm_lock_count[9]_i_2__0_n_0 ;
- wire \mmcm_lock_count[9]_i_4__0_n_0 ;
- wire [9:0]mmcm_lock_count_reg;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_i_2__0_n_0;
- wire [6:0]p_0_in__1;
- wire [9:0]p_0_in__3;
- wire quad1_common_lock_in;
- wire reset_time_out_i_2__0_n_0;
- wire reset_time_out_i_4__0_n_0;
- wire reset_time_out_i_6_n_0;
- wire reset_time_out_reg_n_0;
- wire run_phase_alignment_int_i_1__0_n_0;
- wire run_phase_alignment_int_reg_n_0;
- wire run_phase_alignment_int_s2;
- wire run_phase_alignment_int_s3_reg_n_0;
- wire rx_fsm_reset_done_int;
- wire rx_fsm_reset_done_int_0;
- wire rx_fsm_reset_done_int_i_1_n_0;
- wire rx_fsm_reset_done_int_i_3_n_0;
- wire rx_fsm_reset_done_int_s3;
- wire [3:0]rx_state;
- wire [3:0]rx_state__0;
- wire rxfsm_rxresetdone_r;
- wire rxpmaresetdone_i;
- wire rxpmaresetdone_rx_s;
- wire rxresetdone_s2;
- wire rxresetdone_s3;
- wire scndry_out;
- wire sync_PLL0LOCK_cdc_sync_n_0;
- wire sync_PLL0LOCK_cdc_sync_n_1;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_0;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_1;
- wire sync_rx_fsm_reset_done_int_cdc_sync_n_0;
- wire time_out_100us_i_1_n_0;
- wire time_out_100us_i_2_n_0;
- wire time_out_100us_i_3_n_0;
- wire time_out_100us_i_4_n_0;
- wire time_out_100us_i_5_n_0;
- wire time_out_100us_reg_n_0;
- wire time_out_1us_i_1_n_0;
- wire time_out_1us_i_2_n_0;
- wire time_out_1us_reg_n_0;
- wire time_out_2ms_i_1_n_0;
- wire time_out_2ms_i_2_n_0;
- wire time_out_2ms_i_3_n_0;
- wire time_out_2ms_reg_n_0;
- wire time_out_counter;
- wire \time_out_counter[0]_i_3_n_0 ;
- wire \time_out_counter[0]_i_4__0_n_0 ;
- wire \time_out_counter[0]_i_5__0_n_0 ;
- wire \time_out_counter[0]_i_6__0_n_0 ;
- wire \time_out_counter[0]_i_7_n_0 ;
- wire \time_out_counter[0]_i_8_n_0 ;
- wire [19:0]time_out_counter_reg;
- wire \time_out_counter_reg[0]_i_2__0_n_0 ;
- wire \time_out_counter_reg[0]_i_2__0_n_1 ;
- wire \time_out_counter_reg[0]_i_2__0_n_2 ;
- wire \time_out_counter_reg[0]_i_2__0_n_3 ;
- wire \time_out_counter_reg[0]_i_2__0_n_4 ;
- wire \time_out_counter_reg[0]_i_2__0_n_5 ;
- wire \time_out_counter_reg[0]_i_2__0_n_6 ;
- wire \time_out_counter_reg[0]_i_2__0_n_7 ;
- wire \time_out_counter_reg[12]_i_1__0_n_0 ;
- wire \time_out_counter_reg[12]_i_1__0_n_1 ;
- wire \time_out_counter_reg[12]_i_1__0_n_2 ;
- wire \time_out_counter_reg[12]_i_1__0_n_3 ;
- wire \time_out_counter_reg[12]_i_1__0_n_4 ;
- wire \time_out_counter_reg[12]_i_1__0_n_5 ;
- wire \time_out_counter_reg[12]_i_1__0_n_6 ;
- wire \time_out_counter_reg[12]_i_1__0_n_7 ;
- wire \time_out_counter_reg[16]_i_1__0_n_1 ;
- wire \time_out_counter_reg[16]_i_1__0_n_2 ;
- wire \time_out_counter_reg[16]_i_1__0_n_3 ;
- wire \time_out_counter_reg[16]_i_1__0_n_4 ;
- wire \time_out_counter_reg[16]_i_1__0_n_5 ;
- wire \time_out_counter_reg[16]_i_1__0_n_6 ;
- wire \time_out_counter_reg[16]_i_1__0_n_7 ;
- wire \time_out_counter_reg[4]_i_1__0_n_0 ;
- wire \time_out_counter_reg[4]_i_1__0_n_1 ;
- wire \time_out_counter_reg[4]_i_1__0_n_2 ;
- wire \time_out_counter_reg[4]_i_1__0_n_3 ;
- wire \time_out_counter_reg[4]_i_1__0_n_4 ;
- wire \time_out_counter_reg[4]_i_1__0_n_5 ;
- wire \time_out_counter_reg[4]_i_1__0_n_6 ;
- wire \time_out_counter_reg[4]_i_1__0_n_7 ;
- wire \time_out_counter_reg[8]_i_1__0_n_0 ;
- wire \time_out_counter_reg[8]_i_1__0_n_1 ;
- wire \time_out_counter_reg[8]_i_1__0_n_2 ;
- wire \time_out_counter_reg[8]_i_1__0_n_3 ;
- wire \time_out_counter_reg[8]_i_1__0_n_4 ;
- wire \time_out_counter_reg[8]_i_1__0_n_5 ;
- wire \time_out_counter_reg[8]_i_1__0_n_6 ;
- wire \time_out_counter_reg[8]_i_1__0_n_7 ;
- wire time_out_wait_bypass_i_1__0_n_0;
- wire time_out_wait_bypass_reg_n_0;
- wire time_out_wait_bypass_s2;
- wire time_out_wait_bypass_s3;
- wire time_tlock_max;
- wire time_tlock_max1;
- wire time_tlock_max1_carry__0_i_1_n_0;
- wire time_tlock_max1_carry__0_i_2_n_0;
- wire time_tlock_max1_carry__0_i_3_n_0;
- wire time_tlock_max1_carry__0_i_4_n_0;
- wire time_tlock_max1_carry__0_i_5_n_0;
- wire time_tlock_max1_carry__0_i_6_n_0;
- wire time_tlock_max1_carry__0_i_7_n_0;
- wire time_tlock_max1_carry__0_n_0;
- wire time_tlock_max1_carry__0_n_1;
- wire time_tlock_max1_carry__0_n_2;
- wire time_tlock_max1_carry__0_n_3;
- wire time_tlock_max1_carry__1_i_1_n_0;
- wire time_tlock_max1_carry__1_i_2_n_0;
- wire time_tlock_max1_carry__1_i_3_n_0;
- wire time_tlock_max1_carry__1_i_4_n_0;
- wire time_tlock_max1_carry__1_n_3;
- wire time_tlock_max1_carry_i_1_n_0;
- wire time_tlock_max1_carry_i_2_n_0;
- wire time_tlock_max1_carry_i_3_n_0;
- wire time_tlock_max1_carry_i_4_n_0;
- wire time_tlock_max1_carry_i_5_n_0;
- wire time_tlock_max1_carry_n_0;
- wire time_tlock_max1_carry_n_1;
- wire time_tlock_max1_carry_n_2;
- wire time_tlock_max1_carry_n_3;
- wire time_tlock_max_i_1_n_0;
- wire txpmaresetdone_i;
- wire user_clk;
- wire \wait_bypass_count[0]_i_1__0_n_0 ;
- wire \wait_bypass_count[0]_i_2__0_n_0 ;
- wire \wait_bypass_count[0]_i_4__0_n_0 ;
- wire \wait_bypass_count[0]_i_5__0_n_0 ;
- wire \wait_bypass_count[0]_i_6__0_n_0 ;
- wire \wait_bypass_count[0]_i_7__0_n_0 ;
- wire [12:0]wait_bypass_count_reg;
- wire \wait_bypass_count_reg[0]_i_3__0_n_0 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_1 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_2 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_3 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_4 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_5 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_6 ;
- wire \wait_bypass_count_reg[0]_i_3__0_n_7 ;
- wire \wait_bypass_count_reg[12]_i_1__0_n_7 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_0 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_1 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_2 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_3 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_4 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_5 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_6 ;
- wire \wait_bypass_count_reg[4]_i_1__0_n_7 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_0 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_1 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_2 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_3 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_4 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_5 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_6 ;
- wire \wait_bypass_count_reg[8]_i_1__0_n_7 ;
- wire [6:0]wait_time_cnt0__0;
- wire \wait_time_cnt[1]_i_1__0_n_0 ;
- wire \wait_time_cnt[6]_i_1_n_0 ;
- wire \wait_time_cnt[6]_i_2__0_n_0 ;
- wire \wait_time_cnt[6]_i_4__0_n_0 ;
- wire [6:0]wait_time_cnt_reg;
- wire [3:3]\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED ;
- wire [3:0]NLW_time_tlock_max1_carry_O_UNCONNECTED;
- wire [3:0]NLW_time_tlock_max1_carry__0_O_UNCONNECTED;
- wire [3:2]NLW_time_tlock_max1_carry__1_CO_UNCONNECTED;
- wire [3:0]NLW_time_tlock_max1_carry__1_O_UNCONNECTED;
- wire [3:0]\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED ;
- wire [3:1]\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED ;
-
- LUT3 #(
- .INIT(8'h74))
- \FSM_sequential_rx_state[0]_i_1
- (.I0(\FSM_sequential_rx_state[1]_i_2_n_0 ),
- .I1(rx_state[3]),
- .I2(\FSM_sequential_rx_state[0]_i_2_n_0 ),
- .O(rx_state__0[0]));
- LUT6 #(
- .INIT(64'h3F200020FFFFFFFF))
- \FSM_sequential_rx_state[0]_i_2
- (.I0(time_tlock_max),
- .I1(reset_time_out_reg_n_0),
- .I2(\FSM_sequential_rx_state[3]_i_11_n_0 ),
- .I3(rx_state[1]),
- .I4(time_out_2ms_reg_n_0),
- .I5(rx_state[0]),
- .O(\FSM_sequential_rx_state[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h8888BBBBBB8B8888))
- \FSM_sequential_rx_state[1]_i_1
- (.I0(\FSM_sequential_rx_state[1]_i_2_n_0 ),
- .I1(rx_state[3]),
- .I2(rx_state[2]),
- .I3(\FSM_sequential_rx_state[2]_i_2_n_0 ),
- .I4(rx_state[0]),
- .I5(rx_state[1]),
- .O(rx_state__0[1]));
- LUT5 #(
- .INIT(32'h0000FB00))
- \FSM_sequential_rx_state[1]_i_2
- (.I0(reset_time_out_reg_n_0),
- .I1(time_out_100us_reg_n_0),
- .I2(gt_rxuserrdy_i),
- .I3(rx_state[0]),
- .I4(\FSM_sequential_rx_state[3]_i_11_n_0 ),
- .O(\FSM_sequential_rx_state[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h050F020005050200))
- \FSM_sequential_rx_state[2]_i_1
- (.I0(rx_state[0]),
- .I1(time_out_2ms_reg_n_0),
- .I2(rx_state[3]),
- .I3(rx_state[1]),
- .I4(rx_state[2]),
- .I5(\FSM_sequential_rx_state[2]_i_2_n_0 ),
- .O(\FSM_sequential_rx_state[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT2 #(
- .INIT(4'hB))
- \FSM_sequential_rx_state[2]_i_2
- (.I0(reset_time_out_reg_n_0),
- .I1(time_tlock_max),
- .O(\FSM_sequential_rx_state[2]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'hF0F0F0F1))
- \FSM_sequential_rx_state[3]_i_10
- (.I0(rx_state[2]),
- .I1(rx_state[1]),
- .I2(rx_state[3]),
- .I3(init_wait_done_reg_n_0),
- .I4(rx_state[0]),
- .O(\FSM_sequential_rx_state[3]_i_10_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT3 #(
- .INIT(8'hCA))
- \FSM_sequential_rx_state[3]_i_11
- (.I0(rx_state[2]),
- .I1(rx_state[1]),
- .I2(rx_state[3]),
- .O(\FSM_sequential_rx_state[3]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'h33330000DDFD0000))
- \FSM_sequential_rx_state[3]_i_3
- (.I0(rx_state[0]),
- .I1(gt_rxuserrdy_i),
- .I2(time_out_100us_reg_n_0),
- .I3(reset_time_out_reg_n_0),
- .I4(rx_state[3]),
- .I5(rx_state[1]),
- .O(\FSM_sequential_rx_state[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF00011101))
- \FSM_sequential_rx_state[3]_i_4
- (.I0(\FSM_sequential_rx_state[3]_i_9_n_0 ),
- .I1(rx_state[1]),
- .I2(\FSM_sequential_rx_state_reg[0]_0 ),
- .I3(rx_state[0]),
- .I4(mmcm_lock_reclocked),
- .I5(\FSM_sequential_rx_state[3]_i_10_n_0 ),
- .O(\FSM_sequential_rx_state[3]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hF1FFF1FFFFFFF1FF))
- \FSM_sequential_rx_state[3]_i_6
- (.I0(rx_state[3]),
- .I1(rx_state[2]),
- .I2(rxresetdone_s3),
- .I3(rx_state[1]),
- .I4(time_out_2ms_reg_n_0),
- .I5(reset_time_out_reg_n_0),
- .O(\FSM_sequential_rx_state[3]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hE000E0000000E000))
- \FSM_sequential_rx_state[3]_i_7
- (.I0(rx_state[3]),
- .I1(rx_state[2]),
- .I2(rx_state[1]),
- .I3(rx_state[0]),
- .I4(time_out_2ms_reg_n_0),
- .I5(reset_time_out_reg_n_0),
- .O(\FSM_sequential_rx_state[3]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFBFB00FF))
- \FSM_sequential_rx_state[3]_i_8
- (.I0(reset_time_out_reg_n_0),
- .I1(time_out_100us_reg_n_0),
- .I2(gt_rxuserrdy_i),
- .I3(time_out_wait_bypass_s3),
- .I4(rx_state[0]),
- .I5(\FSM_sequential_rx_state[3]_i_11_n_0 ),
- .O(\FSM_sequential_rx_state[3]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'h2727FF2727272727))
- \FSM_sequential_rx_state[3]_i_9
- (.I0(rx_state[3]),
- .I1(rx_state[1]),
- .I2(rx_state[2]),
- .I3(rx_state[0]),
- .I4(reset_time_out_reg_n_0),
- .I5(time_tlock_max),
- .O(\FSM_sequential_rx_state[3]_i_9_n_0 ));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[0]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(rx_state__0[0]),
- .Q(rx_state[0]),
- .R(AR));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[1]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(rx_state__0[1]),
- .Q(rx_state[1]),
- .R(AR));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[2]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(\FSM_sequential_rx_state[2]_i_1_n_0 ),
- .Q(rx_state[2]),
- .R(AR));
- (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_rx_state_reg[3]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(rx_state__0[3]),
- .Q(rx_state[3]),
- .R(AR));
- MUXF7 \FSM_sequential_rx_state_reg[3]_i_2
- (.I0(\FSM_sequential_rx_state[3]_i_7_n_0 ),
- .I1(\FSM_sequential_rx_state[3]_i_8_n_0 ),
- .O(rx_state__0[3]),
- .S(rx_state[3]));
- LUT6 #(
- .INIT(64'hFFFBFFFB40000000))
- RXUSERRDY_i_1
- (.I0(rx_state[3]),
- .I1(rx_state[0]),
- .I2(rx_state[1]),
- .I3(rx_state[2]),
- .I4(gt_txuserrdy_i),
- .I5(gt_rxuserrdy_i),
- .O(RXUSERRDY_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- RXUSERRDY_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(RXUSERRDY_i_1_n_0),
- .Q(gt_rxuserrdy_i),
- .R(AR));
- LUT5 #(
- .INIT(32'hFFEF0020))
- check_tlock_max_i_1
- (.I0(rx_state[2]),
- .I1(rx_state[1]),
- .I2(rx_state[0]),
- .I3(rx_state[3]),
- .I4(check_tlock_max_reg_n_0),
- .O(check_tlock_max_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- check_tlock_max_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(check_tlock_max_i_1_n_0),
- .Q(check_tlock_max_reg_n_0),
- .R(AR));
- north_channel_north_channel_cdc_sync__parameterized3_15 gtrxreset_cdc_sync
- (.gtrxreset_i(gtrxreset_i),
- .init_clk_in(init_clk_in),
- .out(scndry_out),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'hFFFB0002))
- gtrxreset_i_i_1
- (.I0(rx_state[0]),
- .I1(rx_state[2]),
- .I2(rx_state[1]),
- .I3(rx_state[3]),
- .I4(gtrxreset_i),
- .O(gtrxreset_i_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- gtrxreset_i_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gtrxreset_i_i_1_n_0),
- .Q(gtrxreset_i),
- .R(AR));
- LUT1 #(
- .INIT(2'h1))
- \init_wait_count[0]_i_1__0
- (.I0(init_wait_count_reg[0]),
- .O(p_0_in__1[0]));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT2 #(
- .INIT(4'h6))
- \init_wait_count[1]_i_1__0
- (.I0(init_wait_count_reg[0]),
- .I1(init_wait_count_reg[1]),
- .O(p_0_in__1[1]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[2]_i_1__0
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .O(p_0_in__1[2]));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \init_wait_count[3]_i_1__0
- (.I0(init_wait_count_reg[3]),
- .I1(init_wait_count_reg[1]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[2]),
- .O(p_0_in__1[3]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \init_wait_count[4]_i_1__0
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[3]),
- .I4(init_wait_count_reg[4]),
- .O(p_0_in__1[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \init_wait_count[5]_i_1__0
- (.I0(init_wait_count_reg[5]),
- .I1(init_wait_count_reg[2]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[1]),
- .I4(init_wait_count_reg[3]),
- .I5(init_wait_count_reg[4]),
- .O(p_0_in__1[5]));
- LUT4 #(
- .INIT(16'hFFBF))
- \init_wait_count[6]_i_1__0
- (.I0(\init_wait_count[6]_i_3__0_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .O(init_wait_count));
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[6]_i_2__0
- (.I0(init_wait_count_reg[6]),
- .I1(\init_wait_count[6]_i_4__0_n_0 ),
- .I2(init_wait_count_reg[5]),
- .O(p_0_in__1[6]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \init_wait_count[6]_i_3__0
- (.I0(init_wait_count_reg[1]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[4]),
- .I3(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_3__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'h80000000))
- \init_wait_count[6]_i_4__0
- (.I0(init_wait_count_reg[4]),
- .I1(init_wait_count_reg[3]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[0]),
- .I4(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_4__0_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[0]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[0]),
- .Q(init_wait_count_reg[0]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[1]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[1]),
- .Q(init_wait_count_reg[1]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[2]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[2]),
- .Q(init_wait_count_reg[2]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[3]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[3]),
- .Q(init_wait_count_reg[3]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[4]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[4]),
- .Q(init_wait_count_reg[4]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[5]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[5]),
- .Q(init_wait_count_reg[5]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[6]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in__1[6]),
- .Q(init_wait_count_reg[6]));
- LUT5 #(
- .INIT(32'hFFFF0040))
- init_wait_done_i_1__0
- (.I0(\init_wait_count[6]_i_3__0_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .I4(init_wait_done_reg_n_0),
- .O(init_wait_done_i_1__0_n_0));
- FDCE #(
- .INIT(1'b0))
- init_wait_done_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(AR),
- .D(init_wait_done_i_1__0_n_0),
- .Q(init_wait_done_reg_n_0));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[0]_i_1__0
- (.I0(mmcm_lock_count_reg[0]),
- .O(p_0_in__3[0]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT2 #(
- .INIT(4'h6))
- \mmcm_lock_count[1]_i_1__0
- (.I0(mmcm_lock_count_reg[0]),
- .I1(mmcm_lock_count_reg[1]),
- .O(p_0_in__3[1]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[2]_i_1__0
- (.I0(mmcm_lock_count_reg[2]),
- .I1(mmcm_lock_count_reg[0]),
- .I2(mmcm_lock_count_reg[1]),
- .O(p_0_in__3[2]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[3]_i_1__0
- (.I0(mmcm_lock_count_reg[3]),
- .I1(mmcm_lock_count_reg[1]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[2]),
- .O(p_0_in__3[3]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[4]_i_1__0
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .O(p_0_in__3[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[5]_i_1__0
- (.I0(mmcm_lock_count_reg[5]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .I5(mmcm_lock_count_reg[4]),
- .O(p_0_in__3[5]));
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[6]_i_1__0
- (.I0(mmcm_lock_count_reg[6]),
- .I1(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I2(mmcm_lock_count_reg[5]),
- .O(p_0_in__3[6]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[7]_i_1__0
- (.I0(mmcm_lock_count_reg[7]),
- .I1(mmcm_lock_count_reg[5]),
- .I2(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I3(mmcm_lock_count_reg[6]),
- .O(p_0_in__3[7]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[8]_i_1__0
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .O(p_0_in__3[8]));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- \mmcm_lock_count[9]_i_2__0
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .I5(mmcm_lock_count_reg[9]),
- .O(\mmcm_lock_count[9]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[9]_i_3__0
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(p_0_in__3[9]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h80000000))
- \mmcm_lock_count[9]_i_4__0
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[3]),
- .I2(mmcm_lock_count_reg[1]),
- .I3(mmcm_lock_count_reg[0]),
- .I4(mmcm_lock_count_reg[2]),
- .O(\mmcm_lock_count[9]_i_4__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[0]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[0]),
- .Q(mmcm_lock_count_reg[0]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[1]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[1]),
- .Q(mmcm_lock_count_reg[1]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[2]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[2]),
- .Q(mmcm_lock_count_reg[2]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[3]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[3]),
- .Q(mmcm_lock_count_reg[3]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[4]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[4]),
- .Q(mmcm_lock_count_reg[4]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[5]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[5]),
- .Q(mmcm_lock_count_reg[5]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[6]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[6]),
- .Q(mmcm_lock_count_reg[6]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[7]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[7]),
- .Q(mmcm_lock_count_reg[7]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[8]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[8]),
- .Q(mmcm_lock_count_reg[8]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[9]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2__0_n_0 ),
- .D(p_0_in__3[9]),
- .Q(mmcm_lock_count_reg[9]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- mmcm_lock_reclocked_i_2__0
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4__0_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(mmcm_lock_reclocked_i_2__0_n_0));
- FDRE #(
- .INIT(1'b0))
- mmcm_lock_reclocked_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .Q(mmcm_lock_reclocked),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT4 #(
- .INIT(16'h0151))
- reset_time_out_i_2__0
- (.I0(rx_state[1]),
- .I1(\FSM_sequential_rx_state_reg[0]_0 ),
- .I2(rx_state[0]),
- .I3(mmcm_lock_reclocked),
- .O(reset_time_out_i_2__0_n_0));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT2 #(
- .INIT(4'h2))
- reset_time_out_i_3__0
- (.I0(rx_state[2]),
- .I1(rx_state[3]),
- .O(check_tlock_max));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT2 #(
- .INIT(4'hB))
- reset_time_out_i_4__0
- (.I0(rxresetdone_s3),
- .I1(rx_state[1]),
- .O(reset_time_out_i_4__0_n_0));
- LUT5 #(
- .INIT(32'h07DC07CC))
- reset_time_out_i_6
- (.I0(rx_state[1]),
- .I1(rx_state[0]),
- .I2(rx_state[2]),
- .I3(rx_state[3]),
- .I4(\FSM_sequential_rx_state_reg[0]_0 ),
- .O(reset_time_out_i_6_n_0));
- FDSE #(
- .INIT(1'b0))
- reset_time_out_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_PLL0LOCK_cdc_sync_n_1),
- .Q(reset_time_out_reg_n_0),
- .S(AR));
- LUT5 #(
- .INIT(32'hFFFD0004))
- run_phase_alignment_int_i_1__0
- (.I0(rx_state[0]),
- .I1(rx_state[3]),
- .I2(rx_state[1]),
- .I3(rx_state[2]),
- .I4(run_phase_alignment_int_reg_n_0),
- .O(run_phase_alignment_int_i_1__0_n_0));
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(run_phase_alignment_int_i_1__0_n_0),
- .Q(run_phase_alignment_int_reg_n_0),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(run_phase_alignment_int_s2),
- .Q(run_phase_alignment_int_s3_reg_n_0),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'hFFBF0080))
- rx_fsm_reset_done_int_i_1
- (.I0(rx_fsm_reset_done_int_0),
- .I1(rx_fsm_reset_done_int_i_3_n_0),
- .I2(rx_state[3]),
- .I3(rx_state[2]),
- .I4(rx_fsm_reset_done_int),
- .O(rx_fsm_reset_done_int_i_1_n_0));
- LUT5 #(
- .INIT(32'h00100000))
- rx_fsm_reset_done_int_i_2
- (.I0(rx_state[0]),
- .I1(rx_state[2]),
- .I2(time_out_1us_reg_n_0),
- .I3(reset_time_out_reg_n_0),
- .I4(gt_rxuserrdy_i),
- .O(rx_fsm_reset_done_int_0));
- LUT6 #(
- .INIT(64'h00003B3BCFCC0000))
- rx_fsm_reset_done_int_i_3
- (.I0(time_out_1us_reg_n_0),
- .I1(gt_rxuserrdy_i),
- .I2(reset_time_out_reg_n_0),
- .I3(time_out_100us_reg_n_0),
- .I4(rx_state[0]),
- .I5(rx_state[1]),
- .O(rx_fsm_reset_done_int_i_3_n_0));
- FDRE #(
- .INIT(1'b0))
- rx_fsm_reset_done_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rx_fsm_reset_done_int_i_1_n_0),
- .Q(rx_fsm_reset_done_int),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- rx_fsm_reset_done_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
- .Q(rx_fsm_reset_done_int_s3),
- .R(1'b0));
- FDCE #(
- .INIT(1'b0))
- rxpmaresetdone_i_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(scndry_out),
- .D(rxpmaresetdone_rx_s),
- .Q(rxpmaresetdone_i));
- FDRE #(
- .INIT(1'b0))
- rxresetdone_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(rxresetdone_s2),
- .Q(rxresetdone_s3),
- .R(1'b0));
- north_channel_north_channel_cdc_sync__parameterized1_16 sync_PLL0LOCK_cdc_sync
- (.E(sync_PLL0LOCK_cdc_sync_n_0),
- .\FSM_sequential_rx_state_reg[0] (\FSM_sequential_rx_state[3]_i_3_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_0 (\FSM_sequential_rx_state[3]_i_4_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_1 (\wait_time_cnt[6]_i_2__0_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_2 (\FSM_sequential_rx_state[3]_i_6_n_0 ),
- .\FSM_sequential_rx_state_reg[0]_3 (time_out_2ms_reg_n_0),
- .Q(rx_state),
- .check_tlock_max(check_tlock_max),
- .init_clk_in(init_clk_in),
- .quad1_common_lock_in(quad1_common_lock_in),
- .reset_time_out_reg(sync_PLL0LOCK_cdc_sync_n_1),
- .reset_time_out_reg_0(gt_rxuserrdy_i),
- .reset_time_out_reg_1(reset_time_out_i_2__0_n_0),
- .reset_time_out_reg_2(reset_time_out_i_4__0_n_0),
- .reset_time_out_reg_3(reset_time_out_i_6_n_0),
- .reset_time_out_reg_4(reset_time_out_reg_n_0));
- north_channel_north_channel_cdc_sync__parameterized1_17 sync_PLL1LOCK_cdc_sync
- (.init_clk_in(init_clk_in));
- north_channel_north_channel_cdc_sync__parameterized6_18 sync_RXRESETDONE_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(rxresetdone_s2),
- .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized1_19 sync_mmcm_lock_reclocked_cdc_sync
- (.SR(sync_mmcm_lock_reclocked_cdc_sync_n_0),
- .init_clk_in(init_clk_in),
- .mmcm_lock_reclocked(mmcm_lock_reclocked),
- .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .mmcm_lock_reclocked_reg_0(mmcm_lock_reclocked_i_2__0_n_0));
- north_channel_north_channel_cdc_sync__parameterized3_20 sync_pmaresetdone_fallingedge_detect_cdc_sync
- (.init_clk_in(init_clk_in),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized3_21 sync_run_phase_alignment_int_cdc_sync
- (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 (run_phase_alignment_int_reg_n_0),
- .init_clk_in(init_clk_in),
- .out(run_phase_alignment_int_s2),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized3_22 sync_rx_fsm_reset_done_int_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
- .rx_fsm_reset_done_int(rx_fsm_reset_done_int),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized6_23 sync_rxpmaresetdone_cdc_sync
- (.init_clk_in(init_clk_in),
- .rxpmaresetdone_i(rxpmaresetdone_i),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync_24 sync_rxpmaresetdone_rx_s_cdc_sync
- (.out(rxpmaresetdone_rx_s),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized6_25 sync_time_out_wait_bypass_cdc_sync
- (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg_0 (time_out_wait_bypass_reg_n_0),
- .init_clk_in(init_clk_in),
- .out(time_out_wait_bypass_s2),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized6_26 sync_txpmaresetdone_cdc_sync
- (.init_clk_in(init_clk_in),
- .txpmaresetdone_i(txpmaresetdone_i),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'hFFFF0010))
- time_out_100us_i_1
- (.I0(time_out_100us_i_2_n_0),
- .I1(time_out_100us_i_3_n_0),
- .I2(time_out_100us_i_4_n_0),
- .I3(time_out_100us_i_5_n_0),
- .I4(time_out_100us_reg_n_0),
- .O(time_out_100us_i_1_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- time_out_100us_i_2
- (.I0(time_out_counter_reg[18]),
- .I1(time_out_counter_reg[19]),
- .I2(time_out_counter_reg[15]),
- .I3(time_out_counter_reg[17]),
- .I4(time_out_counter_reg[16]),
- .O(time_out_100us_i_2_n_0));
- LUT6 #(
- .INIT(64'hFFFBFFFFFFFFFFFF))
- time_out_100us_i_3
- (.I0(time_out_counter_reg[3]),
- .I1(time_out_counter_reg[2]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[14]),
- .I4(time_out_counter_reg[7]),
- .I5(time_out_counter_reg[6]),
- .O(time_out_100us_i_3_n_0));
- LUT4 #(
- .INIT(16'h0010))
- time_out_100us_i_4
- (.I0(time_out_counter_reg[11]),
- .I1(time_out_counter_reg[10]),
- .I2(time_out_counter_reg[2]),
- .I3(time_out_counter_reg[9]),
- .O(time_out_100us_i_4_n_0));
- LUT6 #(
- .INIT(64'hFFFFEFFFFFFFFFFF))
- time_out_100us_i_5
- (.I0(time_out_counter_reg[1]),
- .I1(time_out_counter_reg[0]),
- .I2(time_out_counter_reg[13]),
- .I3(time_out_counter_reg[12]),
- .I4(time_out_counter_reg[5]),
- .I5(time_out_counter_reg[4]),
- .O(time_out_100us_i_5_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_100us_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_100us_i_1_n_0),
- .Q(time_out_100us_reg_n_0),
- .R(reset_time_out_reg_n_0));
- LUT5 #(
- .INIT(32'hFFFF0010))
- time_out_1us_i_1
- (.I0(\time_out_counter[0]_i_6__0_n_0 ),
- .I1(time_out_100us_i_2_n_0),
- .I2(time_out_100us_i_4_n_0),
- .I3(time_out_1us_i_2_n_0),
- .I4(time_out_1us_reg_n_0),
- .O(time_out_1us_i_1_n_0));
- LUT6 #(
- .INIT(64'hFDFFFFFFFFFFFFFF))
- time_out_1us_i_2
- (.I0(time_out_counter_reg[0]),
- .I1(time_out_counter_reg[1]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[4]),
- .I4(time_out_counter_reg[3]),
- .I5(time_out_counter_reg[5]),
- .O(time_out_1us_i_2_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_1us_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_1us_i_1_n_0),
- .Q(time_out_1us_reg_n_0),
- .R(reset_time_out_reg_n_0));
- LUT4 #(
- .INIT(16'hFF01))
- time_out_2ms_i_1
- (.I0(time_out_2ms_i_2_n_0),
- .I1(\time_out_counter[0]_i_5__0_n_0 ),
- .I2(\time_out_counter[0]_i_6__0_n_0 ),
- .I3(time_out_2ms_reg_n_0),
- .O(time_out_2ms_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFF2FF))
- time_out_2ms_i_2
- (.I0(time_out_counter_reg[9]),
- .I1(time_out_counter_reg[10]),
- .I2(time_out_counter_reg[17]),
- .I3(time_out_counter_reg[16]),
- .I4(time_out_2ms_i_3_n_0),
- .I5(\time_out_counter[0]_i_3_n_0 ),
- .O(time_out_2ms_i_2_n_0));
- LUT2 #(
- .INIT(4'h7))
- time_out_2ms_i_3
- (.I0(time_out_counter_reg[3]),
- .I1(time_out_counter_reg[5]),
- .O(time_out_2ms_i_3_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_2ms_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_2ms_i_1_n_0),
- .Q(time_out_2ms_reg_n_0),
- .R(reset_time_out_reg_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFBF))
- \time_out_counter[0]_i_1
- (.I0(\time_out_counter[0]_i_3_n_0 ),
- .I1(time_out_counter_reg[5]),
- .I2(time_out_counter_reg[3]),
- .I3(\time_out_counter[0]_i_4__0_n_0 ),
- .I4(\time_out_counter[0]_i_5__0_n_0 ),
- .I5(\time_out_counter[0]_i_6__0_n_0 ),
- .O(time_out_counter));
- LUT2 #(
- .INIT(4'hE))
- \time_out_counter[0]_i_3
- (.I0(time_out_counter_reg[0]),
- .I1(time_out_counter_reg[1]),
- .O(\time_out_counter[0]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'hDFDD))
- \time_out_counter[0]_i_4__0
- (.I0(time_out_counter_reg[16]),
- .I1(time_out_counter_reg[17]),
- .I2(time_out_counter_reg[10]),
- .I3(time_out_counter_reg[9]),
- .O(\time_out_counter[0]_i_4__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFEFFF))
- \time_out_counter[0]_i_5__0
- (.I0(time_out_counter_reg[10]),
- .I1(time_out_counter_reg[18]),
- .I2(time_out_counter_reg[15]),
- .I3(time_out_counter_reg[19]),
- .I4(\time_out_counter[0]_i_8_n_0 ),
- .O(\time_out_counter[0]_i_5__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFD))
- \time_out_counter[0]_i_6__0
- (.I0(time_out_counter_reg[6]),
- .I1(time_out_counter_reg[14]),
- .I2(time_out_counter_reg[13]),
- .I3(time_out_counter_reg[12]),
- .I4(time_out_counter_reg[7]),
- .O(\time_out_counter[0]_i_6__0_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \time_out_counter[0]_i_7
- (.I0(time_out_counter_reg[0]),
- .O(\time_out_counter[0]_i_7_n_0 ));
- LUT4 #(
- .INIT(16'hEFFF))
- \time_out_counter[0]_i_8
- (.I0(time_out_counter_reg[4]),
- .I1(time_out_counter_reg[2]),
- .I2(time_out_counter_reg[11]),
- .I3(time_out_counter_reg[8]),
- .O(\time_out_counter[0]_i_8_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[0]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_7 ),
- .Q(time_out_counter_reg[0]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[0]_i_2__0
- (.CI(1'b0),
- .CO({\time_out_counter_reg[0]_i_2__0_n_0 ,\time_out_counter_reg[0]_i_2__0_n_1 ,\time_out_counter_reg[0]_i_2__0_n_2 ,\time_out_counter_reg[0]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\time_out_counter_reg[0]_i_2__0_n_4 ,\time_out_counter_reg[0]_i_2__0_n_5 ,\time_out_counter_reg[0]_i_2__0_n_6 ,\time_out_counter_reg[0]_i_2__0_n_7 }),
- .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_7_n_0 }));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[10]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[10]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[11]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[11]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[12]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[12]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[12]_i_1__0
- (.CI(\time_out_counter_reg[8]_i_1__0_n_0 ),
- .CO({\time_out_counter_reg[12]_i_1__0_n_0 ,\time_out_counter_reg[12]_i_1__0_n_1 ,\time_out_counter_reg[12]_i_1__0_n_2 ,\time_out_counter_reg[12]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[12]_i_1__0_n_4 ,\time_out_counter_reg[12]_i_1__0_n_5 ,\time_out_counter_reg[12]_i_1__0_n_6 ,\time_out_counter_reg[12]_i_1__0_n_7 }),
- .S(time_out_counter_reg[15:12]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[13]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[13]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[14]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[14]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[15]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[15]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[16]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[16]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[16]_i_1__0
- (.CI(\time_out_counter_reg[12]_i_1__0_n_0 ),
- .CO({\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED [3],\time_out_counter_reg[16]_i_1__0_n_1 ,\time_out_counter_reg[16]_i_1__0_n_2 ,\time_out_counter_reg[16]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[16]_i_1__0_n_4 ,\time_out_counter_reg[16]_i_1__0_n_5 ,\time_out_counter_reg[16]_i_1__0_n_6 ,\time_out_counter_reg[16]_i_1__0_n_7 }),
- .S(time_out_counter_reg[19:16]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[17]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[17]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[18]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[18]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[19]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[19]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[1]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_6 ),
- .Q(time_out_counter_reg[1]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[2]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_5 ),
- .Q(time_out_counter_reg[2]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[3]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2__0_n_4 ),
- .Q(time_out_counter_reg[3]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[4]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[4]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[4]_i_1__0
- (.CI(\time_out_counter_reg[0]_i_2__0_n_0 ),
- .CO({\time_out_counter_reg[4]_i_1__0_n_0 ,\time_out_counter_reg[4]_i_1__0_n_1 ,\time_out_counter_reg[4]_i_1__0_n_2 ,\time_out_counter_reg[4]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[4]_i_1__0_n_4 ,\time_out_counter_reg[4]_i_1__0_n_5 ,\time_out_counter_reg[4]_i_1__0_n_6 ,\time_out_counter_reg[4]_i_1__0_n_7 }),
- .S(time_out_counter_reg[7:4]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[5]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[5]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[6]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_5 ),
- .Q(time_out_counter_reg[6]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[7]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1__0_n_4 ),
- .Q(time_out_counter_reg[7]),
- .R(reset_time_out_reg_n_0));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[8]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_7 ),
- .Q(time_out_counter_reg[8]),
- .R(reset_time_out_reg_n_0));
- CARRY4 \time_out_counter_reg[8]_i_1__0
- (.CI(\time_out_counter_reg[4]_i_1__0_n_0 ),
- .CO({\time_out_counter_reg[8]_i_1__0_n_0 ,\time_out_counter_reg[8]_i_1__0_n_1 ,\time_out_counter_reg[8]_i_1__0_n_2 ,\time_out_counter_reg[8]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[8]_i_1__0_n_4 ,\time_out_counter_reg[8]_i_1__0_n_5 ,\time_out_counter_reg[8]_i_1__0_n_6 ,\time_out_counter_reg[8]_i_1__0_n_7 }),
- .S(time_out_counter_reg[11:8]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[9]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1__0_n_6 ),
- .Q(time_out_counter_reg[9]),
- .R(reset_time_out_reg_n_0));
- LUT4 #(
- .INIT(16'hAB00))
- time_out_wait_bypass_i_1__0
- (.I0(time_out_wait_bypass_reg_n_0),
- .I1(\wait_bypass_count[0]_i_4__0_n_0 ),
- .I2(rx_fsm_reset_done_int_s3),
- .I3(run_phase_alignment_int_s3_reg_n_0),
- .O(time_out_wait_bypass_i_1__0_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(time_out_wait_bypass_i_1__0_n_0),
- .Q(time_out_wait_bypass_reg_n_0),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_wait_bypass_s2),
- .Q(time_out_wait_bypass_s3),
- .R(1'b0));
- CARRY4 time_tlock_max1_carry
- (.CI(1'b0),
- .CO({time_tlock_max1_carry_n_0,time_tlock_max1_carry_n_1,time_tlock_max1_carry_n_2,time_tlock_max1_carry_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,time_out_counter_reg[5],time_out_counter_reg[3],time_tlock_max1_carry_i_1_n_0}),
- .O(NLW_time_tlock_max1_carry_O_UNCONNECTED[3:0]),
- .S({time_tlock_max1_carry_i_2_n_0,time_tlock_max1_carry_i_3_n_0,time_tlock_max1_carry_i_4_n_0,time_tlock_max1_carry_i_5_n_0}));
- CARRY4 time_tlock_max1_carry__0
- (.CI(time_tlock_max1_carry_n_0),
- .CO({time_tlock_max1_carry__0_n_0,time_tlock_max1_carry__0_n_1,time_tlock_max1_carry__0_n_2,time_tlock_max1_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI({time_tlock_max1_carry__0_i_1_n_0,1'b0,time_tlock_max1_carry__0_i_2_n_0,time_tlock_max1_carry__0_i_3_n_0}),
- .O(NLW_time_tlock_max1_carry__0_O_UNCONNECTED[3:0]),
- .S({time_tlock_max1_carry__0_i_4_n_0,time_tlock_max1_carry__0_i_5_n_0,time_tlock_max1_carry__0_i_6_n_0,time_tlock_max1_carry__0_i_7_n_0}));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__0_i_1
- (.I0(time_out_counter_reg[15]),
- .I1(time_out_counter_reg[14]),
- .O(time_tlock_max1_carry__0_i_1_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__0_i_2
- (.I0(time_out_counter_reg[11]),
- .I1(time_out_counter_reg[10]),
- .O(time_tlock_max1_carry__0_i_2_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__0_i_3
- (.I0(time_out_counter_reg[9]),
- .I1(time_out_counter_reg[8]),
- .O(time_tlock_max1_carry__0_i_3_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__0_i_4
- (.I0(time_out_counter_reg[14]),
- .I1(time_out_counter_reg[15]),
- .O(time_tlock_max1_carry__0_i_4_n_0));
- LUT2 #(
- .INIT(4'h8))
- time_tlock_max1_carry__0_i_5
- (.I0(time_out_counter_reg[12]),
- .I1(time_out_counter_reg[13]),
- .O(time_tlock_max1_carry__0_i_5_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__0_i_6
- (.I0(time_out_counter_reg[10]),
- .I1(time_out_counter_reg[11]),
- .O(time_tlock_max1_carry__0_i_6_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__0_i_7
- (.I0(time_out_counter_reg[8]),
- .I1(time_out_counter_reg[9]),
- .O(time_tlock_max1_carry__0_i_7_n_0));
- CARRY4 time_tlock_max1_carry__1
- (.CI(time_tlock_max1_carry__0_n_0),
- .CO({NLW_time_tlock_max1_carry__1_CO_UNCONNECTED[3:2],time_tlock_max1,time_tlock_max1_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,time_tlock_max1_carry__1_i_1_n_0,time_tlock_max1_carry__1_i_2_n_0}),
- .O(NLW_time_tlock_max1_carry__1_O_UNCONNECTED[3:0]),
- .S({1'b0,1'b0,time_tlock_max1_carry__1_i_3_n_0,time_tlock_max1_carry__1_i_4_n_0}));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__1_i_1
- (.I0(time_out_counter_reg[18]),
- .I1(time_out_counter_reg[19]),
- .O(time_tlock_max1_carry__1_i_1_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry__1_i_2
- (.I0(time_out_counter_reg[17]),
- .I1(time_out_counter_reg[16]),
- .O(time_tlock_max1_carry__1_i_2_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__1_i_3
- (.I0(time_out_counter_reg[19]),
- .I1(time_out_counter_reg[18]),
- .O(time_tlock_max1_carry__1_i_3_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry__1_i_4
- (.I0(time_out_counter_reg[16]),
- .I1(time_out_counter_reg[17]),
- .O(time_tlock_max1_carry__1_i_4_n_0));
- LUT2 #(
- .INIT(4'hE))
- time_tlock_max1_carry_i_1
- (.I0(time_out_counter_reg[0]),
- .I1(time_out_counter_reg[1]),
- .O(time_tlock_max1_carry_i_1_n_0));
- LUT2 #(
- .INIT(4'h8))
- time_tlock_max1_carry_i_2
- (.I0(time_out_counter_reg[6]),
- .I1(time_out_counter_reg[7]),
- .O(time_tlock_max1_carry_i_2_n_0));
- LUT2 #(
- .INIT(4'h2))
- time_tlock_max1_carry_i_3
- (.I0(time_out_counter_reg[4]),
- .I1(time_out_counter_reg[5]),
- .O(time_tlock_max1_carry_i_3_n_0));
- LUT2 #(
- .INIT(4'h2))
- time_tlock_max1_carry_i_4
- (.I0(time_out_counter_reg[2]),
- .I1(time_out_counter_reg[3]),
- .O(time_tlock_max1_carry_i_4_n_0));
- LUT2 #(
- .INIT(4'h1))
- time_tlock_max1_carry_i_5
- (.I0(time_out_counter_reg[1]),
- .I1(time_out_counter_reg[0]),
- .O(time_tlock_max1_carry_i_5_n_0));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT3 #(
- .INIT(8'hF8))
- time_tlock_max_i_1
- (.I0(time_tlock_max1),
- .I1(check_tlock_max_reg_n_0),
- .I2(time_tlock_max),
- .O(time_tlock_max_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- time_tlock_max_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_tlock_max_i_1_n_0),
- .Q(time_tlock_max),
- .R(reset_time_out_reg_n_0));
- FDCE #(
- .INIT(1'b0))
- txpmaresetdone_i_reg
- (.C(user_clk),
- .CE(1'b1),
- .CLR(scndry_out),
- .D(1'b1),
- .Q(txpmaresetdone_i));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_1__0
- (.I0(run_phase_alignment_int_s3_reg_n_0),
- .O(\wait_bypass_count[0]_i_1__0_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \wait_bypass_count[0]_i_2__0
- (.I0(\wait_bypass_count[0]_i_4__0_n_0 ),
- .I1(rx_fsm_reset_done_int_s3),
- .O(\wait_bypass_count[0]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \wait_bypass_count[0]_i_4__0
- (.I0(\wait_bypass_count[0]_i_6__0_n_0 ),
- .I1(wait_bypass_count_reg[4]),
- .I2(wait_bypass_count_reg[3]),
- .I3(wait_bypass_count_reg[6]),
- .I4(wait_bypass_count_reg[5]),
- .I5(\wait_bypass_count[0]_i_7__0_n_0 ),
- .O(\wait_bypass_count[0]_i_4__0_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_5__0
- (.I0(wait_bypass_count_reg[0]),
- .O(\wait_bypass_count[0]_i_5__0_n_0 ));
- LUT4 #(
- .INIT(16'hFF7F))
- \wait_bypass_count[0]_i_6__0
- (.I0(wait_bypass_count_reg[8]),
- .I1(wait_bypass_count_reg[7]),
- .I2(wait_bypass_count_reg[9]),
- .I3(wait_bypass_count_reg[10]),
- .O(\wait_bypass_count[0]_i_6__0_n_0 ));
- LUT5 #(
- .INIT(32'hDFFFFFFF))
- \wait_bypass_count[0]_i_7__0
- (.I0(wait_bypass_count_reg[0]),
- .I1(wait_bypass_count_reg[11]),
- .I2(wait_bypass_count_reg[12]),
- .I3(wait_bypass_count_reg[2]),
- .I4(wait_bypass_count_reg[1]),
- .O(\wait_bypass_count[0]_i_7__0_n_0 ));
- FDRE \wait_bypass_count_reg[0]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_7 ),
- .Q(wait_bypass_count_reg[0]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[0]_i_3__0
- (.CI(1'b0),
- .CO({\wait_bypass_count_reg[0]_i_3__0_n_0 ,\wait_bypass_count_reg[0]_i_3__0_n_1 ,\wait_bypass_count_reg[0]_i_3__0_n_2 ,\wait_bypass_count_reg[0]_i_3__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\wait_bypass_count_reg[0]_i_3__0_n_4 ,\wait_bypass_count_reg[0]_i_3__0_n_5 ,\wait_bypass_count_reg[0]_i_3__0_n_6 ,\wait_bypass_count_reg[0]_i_3__0_n_7 }),
- .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5__0_n_0 }));
- FDRE \wait_bypass_count_reg[10]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_5 ),
- .Q(wait_bypass_count_reg[10]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[11]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_4 ),
- .Q(wait_bypass_count_reg[11]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[12]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1__0_n_7 ),
- .Q(wait_bypass_count_reg[12]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[12]_i_1__0
- (.CI(\wait_bypass_count_reg[8]_i_1__0_n_0 ),
- .CO(\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED [3:0]),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED [3:1],\wait_bypass_count_reg[12]_i_1__0_n_7 }),
- .S({1'b0,1'b0,1'b0,wait_bypass_count_reg[12]}));
- FDRE \wait_bypass_count_reg[1]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_6 ),
- .Q(wait_bypass_count_reg[1]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[2]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_5 ),
- .Q(wait_bypass_count_reg[2]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[3]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3__0_n_4 ),
- .Q(wait_bypass_count_reg[3]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[4]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_7 ),
- .Q(wait_bypass_count_reg[4]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[4]_i_1__0
- (.CI(\wait_bypass_count_reg[0]_i_3__0_n_0 ),
- .CO({\wait_bypass_count_reg[4]_i_1__0_n_0 ,\wait_bypass_count_reg[4]_i_1__0_n_1 ,\wait_bypass_count_reg[4]_i_1__0_n_2 ,\wait_bypass_count_reg[4]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[4]_i_1__0_n_4 ,\wait_bypass_count_reg[4]_i_1__0_n_5 ,\wait_bypass_count_reg[4]_i_1__0_n_6 ,\wait_bypass_count_reg[4]_i_1__0_n_7 }),
- .S(wait_bypass_count_reg[7:4]));
- FDRE \wait_bypass_count_reg[5]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_6 ),
- .Q(wait_bypass_count_reg[5]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[6]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_5 ),
- .Q(wait_bypass_count_reg[6]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[7]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1__0_n_4 ),
- .Q(wait_bypass_count_reg[7]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- FDRE \wait_bypass_count_reg[8]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_7 ),
- .Q(wait_bypass_count_reg[8]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- CARRY4 \wait_bypass_count_reg[8]_i_1__0
- (.CI(\wait_bypass_count_reg[4]_i_1__0_n_0 ),
- .CO({\wait_bypass_count_reg[8]_i_1__0_n_0 ,\wait_bypass_count_reg[8]_i_1__0_n_1 ,\wait_bypass_count_reg[8]_i_1__0_n_2 ,\wait_bypass_count_reg[8]_i_1__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[8]_i_1__0_n_4 ,\wait_bypass_count_reg[8]_i_1__0_n_5 ,\wait_bypass_count_reg[8]_i_1__0_n_6 ,\wait_bypass_count_reg[8]_i_1__0_n_7 }),
- .S(wait_bypass_count_reg[11:8]));
- FDRE \wait_bypass_count_reg[9]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2__0_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1__0_n_6 ),
- .Q(wait_bypass_count_reg[9]),
- .R(\wait_bypass_count[0]_i_1__0_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \wait_time_cnt[0]_i_1__0
- (.I0(wait_time_cnt_reg[0]),
- .O(wait_time_cnt0__0[0]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT2 #(
- .INIT(4'h9))
- \wait_time_cnt[1]_i_1__0
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .O(\wait_time_cnt[1]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'hE1))
- \wait_time_cnt[2]_i_1__0
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[2]),
- .O(wait_time_cnt0__0[2]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'hFE01))
- \wait_time_cnt[3]_i_1__0
- (.I0(wait_time_cnt_reg[2]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[0]),
- .I3(wait_time_cnt_reg[3]),
- .O(wait_time_cnt0__0[3]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT5 #(
- .INIT(32'hAAAAAAA9))
- \wait_time_cnt[4]_i_1__0
- (.I0(wait_time_cnt_reg[4]),
- .I1(wait_time_cnt_reg[2]),
- .I2(wait_time_cnt_reg[1]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[3]),
- .O(wait_time_cnt0__0[4]));
- LUT6 #(
- .INIT(64'hAAAAAAAAAAAAAAA9))
- \wait_time_cnt[5]_i_1__0
- (.I0(wait_time_cnt_reg[5]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[1]),
- .I5(wait_time_cnt_reg[2]),
- .O(wait_time_cnt0__0[5]));
- LUT3 #(
- .INIT(8'h04))
- \wait_time_cnt[6]_i_1
- (.I0(rx_state[1]),
- .I1(rx_state[0]),
- .I2(rx_state[3]),
- .O(\wait_time_cnt[6]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFEFF))
- \wait_time_cnt[6]_i_2__0
- (.I0(wait_time_cnt_reg[6]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[5]),
- .I3(\wait_time_cnt[6]_i_4__0_n_0 ),
- .O(\wait_time_cnt[6]_i_2__0_n_0 ));
- LUT4 #(
- .INIT(16'hA9AA))
- \wait_time_cnt[6]_i_3__0
- (.I0(wait_time_cnt_reg[6]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[5]),
- .I3(\wait_time_cnt[6]_i_4__0_n_0 ),
- .O(wait_time_cnt0__0[6]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h0001))
- \wait_time_cnt[6]_i_4__0
- (.I0(wait_time_cnt_reg[3]),
- .I1(wait_time_cnt_reg[0]),
- .I2(wait_time_cnt_reg[1]),
- .I3(wait_time_cnt_reg[2]),
- .O(\wait_time_cnt[6]_i_4__0_n_0 ));
- FDRE \wait_time_cnt_reg[0]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[0]),
- .Q(wait_time_cnt_reg[0]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDRE \wait_time_cnt_reg[1]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(\wait_time_cnt[1]_i_1__0_n_0 ),
- .Q(wait_time_cnt_reg[1]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDSE \wait_time_cnt_reg[2]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[2]),
- .Q(wait_time_cnt_reg[2]),
- .S(\wait_time_cnt[6]_i_1_n_0 ));
- FDRE \wait_time_cnt_reg[3]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[3]),
- .Q(wait_time_cnt_reg[3]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDRE \wait_time_cnt_reg[4]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[4]),
- .Q(wait_time_cnt_reg[4]),
- .R(\wait_time_cnt[6]_i_1_n_0 ));
- FDSE \wait_time_cnt_reg[5]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[5]),
- .Q(wait_time_cnt_reg[5]),
- .S(\wait_time_cnt[6]_i_1_n_0 ));
- FDSE \wait_time_cnt_reg[6]
- (.C(init_clk_in),
- .CE(\wait_time_cnt[6]_i_2__0_n_0 ),
- .D(wait_time_cnt0__0[6]),
- .Q(wait_time_cnt_reg[6]),
- .S(\wait_time_cnt[6]_i_1_n_0 ));
-endmodule
-
-(* ORIG_REF_NAME = "north_channel_tx_startup_fsm" *)
-module north_channel_north_channel_tx_startup_fsm
- (out,
- gt_tx_reset_i,
- gt_common_reset_out,
- gt_txuserrdy_i,
- tx_lock,
- \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ,
- quad1_common_lock_in,
- init_clk_in,
- user_clk,
- txfsm_txresetdone_r,
- AR,
- PLL_NOT_LOCKED);
- output out;
- output gt_tx_reset_i;
- output gt_common_reset_out;
- output gt_txuserrdy_i;
- output tx_lock;
- output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- input quad1_common_lock_in;
- input init_clk_in;
- input user_clk;
- input txfsm_txresetdone_r;
- input [0:0]AR;
- input PLL_NOT_LOCKED;
-
- wire [0:0]AR;
- wire \FSM_sequential_tx_state[0]_i_2_n_0 ;
- wire \FSM_sequential_tx_state[0]_i_3_n_0 ;
- wire \FSM_sequential_tx_state[1]_i_1_n_0 ;
- wire \FSM_sequential_tx_state[1]_i_2_n_0 ;
- wire \FSM_sequential_tx_state[2]_i_1_n_0 ;
- wire \FSM_sequential_tx_state[2]_i_2_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_3_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_4_n_0 ;
- wire \FSM_sequential_tx_state[3]_i_6_n_0 ;
- wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ;
- wire MMCM_RESET;
- wire MMCM_RESET_i_1_n_0;
- wire PLL0_RESET_i_1_n_0;
- wire PLL_NOT_LOCKED;
- wire TXUSERRDY_i_1_n_0;
- wire clear;
- wire gt_common_reset_out;
- wire gt_tx_reset_i;
- wire gt_txuserrdy_i;
- wire gttxreset_i_i_1_n_0;
- wire init_clk_in;
- wire init_wait_count;
- wire \init_wait_count[6]_i_3_n_0 ;
- wire \init_wait_count[6]_i_4_n_0 ;
- wire [6:0]init_wait_count_reg;
- wire init_wait_done_i_1_n_0;
- wire init_wait_done_reg_n_0;
- wire \mmcm_lock_count[9]_i_2_n_0 ;
- wire \mmcm_lock_count[9]_i_4_n_0 ;
- wire [9:0]mmcm_lock_count_reg;
- wire mmcm_lock_reclocked;
- wire mmcm_lock_reclocked_i_2_n_0;
- wire out;
- wire [6:0]p_0_in;
- wire [9:0]p_0_in__0;
- wire pll_reset_asserted_i_1_n_0;
- wire pll_reset_asserted_reg_n_0;
- wire quad1_common_lock_in;
- wire reset_time_out;
- wire reset_time_out_i_4_n_0;
- wire run_phase_alignment_int;
- wire run_phase_alignment_int_i_1_n_0;
- wire run_phase_alignment_int_s3;
- wire scndry_out;
- wire sel;
- wire sync_PLL0LOCK_cdc_sync_n_0;
- wire sync_PLL0LOCK_cdc_sync_n_1;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_0;
- wire sync_mmcm_lock_reclocked_cdc_sync_n_1;
- wire time_out_2ms_i_1__0_n_0;
- wire time_out_2ms_i_2__0_n_0;
- wire time_out_2ms_reg_n_0;
- wire time_out_500us_i_1_n_0;
- wire time_out_500us_i_2_n_0;
- wire time_out_500us_i_3_n_0;
- wire time_out_500us_i_4_n_0;
- wire time_out_500us_i_5_n_0;
- wire time_out_500us_reg_n_0;
- wire time_out_counter;
- wire \time_out_counter[0]_i_3__0_n_0 ;
- wire \time_out_counter[0]_i_4_n_0 ;
- wire \time_out_counter[0]_i_5_n_0 ;
- wire \time_out_counter[0]_i_6_n_0 ;
- wire \time_out_counter[0]_i_7__0_n_0 ;
- wire [17:0]time_out_counter_reg;
- wire \time_out_counter_reg[0]_i_2_n_0 ;
- wire \time_out_counter_reg[0]_i_2_n_1 ;
- wire \time_out_counter_reg[0]_i_2_n_2 ;
- wire \time_out_counter_reg[0]_i_2_n_3 ;
- wire \time_out_counter_reg[0]_i_2_n_4 ;
- wire \time_out_counter_reg[0]_i_2_n_5 ;
- wire \time_out_counter_reg[0]_i_2_n_6 ;
- wire \time_out_counter_reg[0]_i_2_n_7 ;
- wire \time_out_counter_reg[12]_i_1_n_0 ;
- wire \time_out_counter_reg[12]_i_1_n_1 ;
- wire \time_out_counter_reg[12]_i_1_n_2 ;
- wire \time_out_counter_reg[12]_i_1_n_3 ;
- wire \time_out_counter_reg[12]_i_1_n_4 ;
- wire \time_out_counter_reg[12]_i_1_n_5 ;
- wire \time_out_counter_reg[12]_i_1_n_6 ;
- wire \time_out_counter_reg[12]_i_1_n_7 ;
- wire \time_out_counter_reg[16]_i_1_n_3 ;
- wire \time_out_counter_reg[16]_i_1_n_6 ;
- wire \time_out_counter_reg[16]_i_1_n_7 ;
- wire \time_out_counter_reg[4]_i_1_n_0 ;
- wire \time_out_counter_reg[4]_i_1_n_1 ;
- wire \time_out_counter_reg[4]_i_1_n_2 ;
- wire \time_out_counter_reg[4]_i_1_n_3 ;
- wire \time_out_counter_reg[4]_i_1_n_4 ;
- wire \time_out_counter_reg[4]_i_1_n_5 ;
- wire \time_out_counter_reg[4]_i_1_n_6 ;
- wire \time_out_counter_reg[4]_i_1_n_7 ;
- wire \time_out_counter_reg[8]_i_1_n_0 ;
- wire \time_out_counter_reg[8]_i_1_n_1 ;
- wire \time_out_counter_reg[8]_i_1_n_2 ;
- wire \time_out_counter_reg[8]_i_1_n_3 ;
- wire \time_out_counter_reg[8]_i_1_n_4 ;
- wire \time_out_counter_reg[8]_i_1_n_5 ;
- wire \time_out_counter_reg[8]_i_1_n_6 ;
- wire \time_out_counter_reg[8]_i_1_n_7 ;
- wire time_out_wait_bypass;
- wire time_out_wait_bypass_i_1_n_0;
- wire time_out_wait_bypass_s2;
- wire time_out_wait_bypass_s3;
- wire time_tlock_max_i_1__0_n_0;
- wire time_tlock_max_i_2_n_0;
- wire time_tlock_max_i_3_n_0;
- wire time_tlock_max_reg_n_0;
- wire tx_fsm_reset_done_int;
- wire tx_fsm_reset_done_int_i_1_n_0;
- wire tx_fsm_reset_done_int_s3;
- wire tx_lock;
- wire [3:0]tx_state;
- wire [3:0]tx_state__0;
- wire txfsm_txresetdone_r;
- wire txresetdone_s2;
- wire txresetdone_s3;
- wire user_clk;
- wire \wait_bypass_count[0]_i_2_n_0 ;
- wire \wait_bypass_count[0]_i_4_n_0 ;
- wire \wait_bypass_count[0]_i_5_n_0 ;
- wire \wait_bypass_count[0]_i_6_n_0 ;
- wire \wait_bypass_count[0]_i_7_n_0 ;
- wire \wait_bypass_count[0]_i_8_n_0 ;
- wire \wait_bypass_count[0]_i_9_n_0 ;
- wire [15:0]wait_bypass_count_reg;
- wire \wait_bypass_count_reg[0]_i_3_n_0 ;
- wire \wait_bypass_count_reg[0]_i_3_n_1 ;
- wire \wait_bypass_count_reg[0]_i_3_n_2 ;
- wire \wait_bypass_count_reg[0]_i_3_n_3 ;
- wire \wait_bypass_count_reg[0]_i_3_n_4 ;
- wire \wait_bypass_count_reg[0]_i_3_n_5 ;
- wire \wait_bypass_count_reg[0]_i_3_n_6 ;
- wire \wait_bypass_count_reg[0]_i_3_n_7 ;
- wire \wait_bypass_count_reg[12]_i_1_n_1 ;
- wire \wait_bypass_count_reg[12]_i_1_n_2 ;
- wire \wait_bypass_count_reg[12]_i_1_n_3 ;
- wire \wait_bypass_count_reg[12]_i_1_n_4 ;
- wire \wait_bypass_count_reg[12]_i_1_n_5 ;
- wire \wait_bypass_count_reg[12]_i_1_n_6 ;
- wire \wait_bypass_count_reg[12]_i_1_n_7 ;
- wire \wait_bypass_count_reg[4]_i_1_n_0 ;
- wire \wait_bypass_count_reg[4]_i_1_n_1 ;
- wire \wait_bypass_count_reg[4]_i_1_n_2 ;
- wire \wait_bypass_count_reg[4]_i_1_n_3 ;
- wire \wait_bypass_count_reg[4]_i_1_n_4 ;
- wire \wait_bypass_count_reg[4]_i_1_n_5 ;
- wire \wait_bypass_count_reg[4]_i_1_n_6 ;
- wire \wait_bypass_count_reg[4]_i_1_n_7 ;
- wire \wait_bypass_count_reg[8]_i_1_n_0 ;
- wire \wait_bypass_count_reg[8]_i_1_n_1 ;
- wire \wait_bypass_count_reg[8]_i_1_n_2 ;
- wire \wait_bypass_count_reg[8]_i_1_n_3 ;
- wire \wait_bypass_count_reg[8]_i_1_n_4 ;
- wire \wait_bypass_count_reg[8]_i_1_n_5 ;
- wire \wait_bypass_count_reg[8]_i_1_n_6 ;
- wire \wait_bypass_count_reg[8]_i_1_n_7 ;
- wire [6:0]wait_time_cnt0;
- wire \wait_time_cnt[1]_i_1_n_0 ;
- wire \wait_time_cnt[6]_i_1__0_n_0 ;
- wire \wait_time_cnt[6]_i_4_n_0 ;
- wire \wait_time_cnt[6]_i_5_n_0 ;
- wire [6:0]wait_time_cnt_reg;
- wire [3:1]\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED ;
- wire [3:2]\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED ;
- wire [3:3]\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED ;
-
- LUT6 #(
- .INIT(64'h00000000DD0D0D0D))
- \FSM_sequential_tx_state[0]_i_1
- (.I0(\FSM_sequential_tx_state[0]_i_2_n_0 ),
- .I1(\FSM_sequential_tx_state[1]_i_2_n_0 ),
- .I2(\FSM_sequential_tx_state[0]_i_3_n_0 ),
- .I3(tx_state[1]),
- .I4(time_out_2ms_reg_n_0),
- .I5(\FSM_sequential_tx_state[3]_i_6_n_0 ),
- .O(tx_state__0[0]));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT2 #(
- .INIT(4'h2))
- \FSM_sequential_tx_state[0]_i_2
- (.I0(tx_state[2]),
- .I1(tx_state[3]),
- .O(\FSM_sequential_tx_state[0]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT3 #(
- .INIT(8'h02))
- \FSM_sequential_tx_state[0]_i_3
- (.I0(tx_state[0]),
- .I1(tx_state[2]),
- .I2(tx_state[3]),
- .O(\FSM_sequential_tx_state[0]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h05105555))
- \FSM_sequential_tx_state[1]_i_1
- (.I0(tx_state[3]),
- .I1(tx_state[2]),
- .I2(tx_state[0]),
- .I3(tx_state[1]),
- .I4(\FSM_sequential_tx_state[1]_i_2_n_0 ),
- .O(\FSM_sequential_tx_state[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT5 #(
- .INIT(32'hDDDDDFDD))
- \FSM_sequential_tx_state[1]_i_2
- (.I0(tx_state[0]),
- .I1(tx_state[1]),
- .I2(reset_time_out),
- .I3(time_tlock_max_reg_n_0),
- .I4(mmcm_lock_reclocked),
- .O(\FSM_sequential_tx_state[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0505100005551000))
- \FSM_sequential_tx_state[2]_i_1
- (.I0(tx_state[3]),
- .I1(time_out_2ms_reg_n_0),
- .I2(tx_state[0]),
- .I3(tx_state[1]),
- .I4(tx_state[2]),
- .I5(\FSM_sequential_tx_state[2]_i_2_n_0 ),
- .O(\FSM_sequential_tx_state[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT3 #(
- .INIT(8'h04))
- \FSM_sequential_tx_state[2]_i_2
- (.I0(mmcm_lock_reclocked),
- .I1(time_tlock_max_reg_n_0),
- .I2(reset_time_out),
- .O(\FSM_sequential_tx_state[2]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hBA))
- \FSM_sequential_tx_state[3]_i_2
- (.I0(\FSM_sequential_tx_state[3]_i_6_n_0 ),
- .I1(time_out_wait_bypass_s3),
- .I2(tx_state[3]),
- .O(tx_state__0[3]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT2 #(
- .INIT(4'h1))
- \FSM_sequential_tx_state[3]_i_3
- (.I0(tx_state[1]),
- .I1(tx_state[2]),
- .O(\FSM_sequential_tx_state[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \FSM_sequential_tx_state[3]_i_4
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[6]),
- .I2(wait_time_cnt_reg[4]),
- .I3(wait_time_cnt_reg[5]),
- .I4(\wait_time_cnt[6]_i_4_n_0 ),
- .I5(wait_time_cnt_reg[1]),
- .O(\FSM_sequential_tx_state[3]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h0000D00000000000))
- \FSM_sequential_tx_state[3]_i_6
- (.I0(time_out_500us_reg_n_0),
- .I1(reset_time_out),
- .I2(tx_state[2]),
- .I3(tx_state[1]),
- .I4(tx_state[3]),
- .I5(tx_state[0]),
- .O(\FSM_sequential_tx_state[3]_i_6_n_0 ));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[0]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(tx_state__0[0]),
- .Q(tx_state[0]),
- .R(AR));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[1]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(\FSM_sequential_tx_state[1]_i_1_n_0 ),
- .Q(tx_state[1]),
- .R(AR));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[2]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(\FSM_sequential_tx_state[2]_i_1_n_0 ),
- .Q(tx_state[2]),
- .R(AR));
- (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *)
- FDRE #(
- .INIT(1'b0))
- \FSM_sequential_tx_state_reg[3]
- (.C(init_clk_in),
- .CE(sync_PLL0LOCK_cdc_sync_n_0),
- .D(tx_state__0[3]),
- .Q(tx_state[3]),
- .R(AR));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT5 #(
- .INIT(32'hFFDF0010))
- MMCM_RESET_i_1
- (.I0(tx_state[2]),
- .I1(tx_state[1]),
- .I2(tx_state[0]),
- .I3(tx_state[3]),
- .I4(MMCM_RESET),
- .O(MMCM_RESET_i_1_n_0));
- FDRE #(
- .INIT(1'b1))
- MMCM_RESET_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(MMCM_RESET_i_1_n_0),
- .Q(MMCM_RESET),
- .R(AR));
- LUT6 #(
- .INIT(64'hFFFFFDFF00000100))
- PLL0_RESET_i_1
- (.I0(pll_reset_asserted_reg_n_0),
- .I1(tx_state[2]),
- .I2(tx_state[1]),
- .I3(tx_state[0]),
- .I4(tx_state[3]),
- .I5(gt_common_reset_out),
- .O(PLL0_RESET_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- PLL0_RESET_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(PLL0_RESET_i_1_n_0),
- .Q(gt_common_reset_out),
- .R(AR));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT5 #(
- .INIT(32'hFEFF0800))
- TXUSERRDY_i_1
- (.I0(tx_state[1]),
- .I1(tx_state[2]),
- .I2(tx_state[3]),
- .I3(tx_state[0]),
- .I4(gt_txuserrdy_i),
- .O(TXUSERRDY_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- TXUSERRDY_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(TXUSERRDY_i_1_n_0),
- .Q(gt_txuserrdy_i),
- .R(AR));
- LUT5 #(
- .INIT(32'hFFEF0100))
- gttxreset_i_i_1
- (.I0(tx_state[3]),
- .I1(tx_state[1]),
- .I2(tx_state[2]),
- .I3(tx_state[0]),
- .I4(gt_tx_reset_i),
- .O(gttxreset_i_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- gttxreset_i_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(gttxreset_i_i_1_n_0),
- .Q(gt_tx_reset_i),
- .R(AR));
- LUT1 #(
- .INIT(2'h1))
- \init_wait_count[0]_i_1
- (.I0(init_wait_count_reg[0]),
- .O(p_0_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT2 #(
- .INIT(4'h6))
- \init_wait_count[1]_i_1
- (.I0(init_wait_count_reg[0]),
- .I1(init_wait_count_reg[1]),
- .O(p_0_in[1]));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[2]_i_1
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .O(p_0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \init_wait_count[3]_i_1
- (.I0(init_wait_count_reg[3]),
- .I1(init_wait_count_reg[1]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[2]),
- .O(p_0_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \init_wait_count[4]_i_1
- (.I0(init_wait_count_reg[2]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[3]),
- .I4(init_wait_count_reg[4]),
- .O(p_0_in[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \init_wait_count[5]_i_1
- (.I0(init_wait_count_reg[5]),
- .I1(init_wait_count_reg[2]),
- .I2(init_wait_count_reg[0]),
- .I3(init_wait_count_reg[1]),
- .I4(init_wait_count_reg[3]),
- .I5(init_wait_count_reg[4]),
- .O(p_0_in[5]));
- LUT4 #(
- .INIT(16'hFFBF))
- \init_wait_count[6]_i_1
- (.I0(\init_wait_count[6]_i_3_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .O(init_wait_count));
- LUT3 #(
- .INIT(8'h6A))
- \init_wait_count[6]_i_2
- (.I0(init_wait_count_reg[6]),
- .I1(\init_wait_count[6]_i_4_n_0 ),
- .I2(init_wait_count_reg[5]),
- .O(p_0_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \init_wait_count[6]_i_3
- (.I0(init_wait_count_reg[1]),
- .I1(init_wait_count_reg[0]),
- .I2(init_wait_count_reg[4]),
- .I3(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT5 #(
- .INIT(32'h80000000))
- \init_wait_count[6]_i_4
- (.I0(init_wait_count_reg[4]),
- .I1(init_wait_count_reg[3]),
- .I2(init_wait_count_reg[1]),
- .I3(init_wait_count_reg[0]),
- .I4(init_wait_count_reg[2]),
- .O(\init_wait_count[6]_i_4_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[0]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[0]),
- .Q(init_wait_count_reg[0]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[1]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[1]),
- .Q(init_wait_count_reg[1]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[2]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[2]),
- .Q(init_wait_count_reg[2]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[3]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[3]),
- .Q(init_wait_count_reg[3]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[4]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[4]),
- .Q(init_wait_count_reg[4]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[5]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[5]),
- .Q(init_wait_count_reg[5]));
- FDCE #(
- .INIT(1'b0))
- \init_wait_count_reg[6]
- (.C(init_clk_in),
- .CE(init_wait_count),
- .CLR(AR),
- .D(p_0_in[6]),
- .Q(init_wait_count_reg[6]));
- LUT5 #(
- .INIT(32'hFFFF0040))
- init_wait_done_i_1
- (.I0(\init_wait_count[6]_i_3_n_0 ),
- .I1(init_wait_count_reg[6]),
- .I2(init_wait_count_reg[3]),
- .I3(init_wait_count_reg[5]),
- .I4(init_wait_done_reg_n_0),
- .O(init_wait_done_i_1_n_0));
- FDCE #(
- .INIT(1'b0))
- init_wait_done_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .CLR(AR),
- .D(init_wait_done_i_1_n_0),
- .Q(init_wait_done_reg_n_0));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT1 #(
- .INIT(2'h1))
- \mmcm_lock_count[0]_i_1
- (.I0(mmcm_lock_count_reg[0]),
- .O(p_0_in__0[0]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'h6))
- \mmcm_lock_count[1]_i_1
- (.I0(mmcm_lock_count_reg[0]),
- .I1(mmcm_lock_count_reg[1]),
- .O(p_0_in__0[1]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[2]_i_1
- (.I0(mmcm_lock_count_reg[2]),
- .I1(mmcm_lock_count_reg[0]),
- .I2(mmcm_lock_count_reg[1]),
- .O(p_0_in__0[2]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[3]_i_1
- (.I0(mmcm_lock_count_reg[3]),
- .I1(mmcm_lock_count_reg[1]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[2]),
- .O(p_0_in__0[3]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[4]_i_1
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .O(p_0_in__0[4]));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[5]_i_1
- (.I0(mmcm_lock_count_reg[5]),
- .I1(mmcm_lock_count_reg[2]),
- .I2(mmcm_lock_count_reg[0]),
- .I3(mmcm_lock_count_reg[1]),
- .I4(mmcm_lock_count_reg[3]),
- .I5(mmcm_lock_count_reg[4]),
- .O(p_0_in__0[5]));
- LUT3 #(
- .INIT(8'h6A))
- \mmcm_lock_count[6]_i_1
- (.I0(mmcm_lock_count_reg[6]),
- .I1(\mmcm_lock_count[9]_i_4_n_0 ),
- .I2(mmcm_lock_count_reg[5]),
- .O(p_0_in__0[6]));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT4 #(
- .INIT(16'h6AAA))
- \mmcm_lock_count[7]_i_1
- (.I0(mmcm_lock_count_reg[7]),
- .I1(mmcm_lock_count_reg[5]),
- .I2(\mmcm_lock_count[9]_i_4_n_0 ),
- .I3(mmcm_lock_count_reg[6]),
- .O(p_0_in__0[7]));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT5 #(
- .INIT(32'h6AAAAAAA))
- \mmcm_lock_count[8]_i_1
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .O(p_0_in__0[8]));
- LUT6 #(
- .INIT(64'h7FFFFFFFFFFFFFFF))
- \mmcm_lock_count[9]_i_2
- (.I0(mmcm_lock_count_reg[8]),
- .I1(mmcm_lock_count_reg[6]),
- .I2(\mmcm_lock_count[9]_i_4_n_0 ),
- .I3(mmcm_lock_count_reg[5]),
- .I4(mmcm_lock_count_reg[7]),
- .I5(mmcm_lock_count_reg[9]),
- .O(\mmcm_lock_count[9]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h6AAAAAAAAAAAAAAA))
- \mmcm_lock_count[9]_i_3
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(p_0_in__0[9]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT5 #(
- .INIT(32'h80000000))
- \mmcm_lock_count[9]_i_4
- (.I0(mmcm_lock_count_reg[4]),
- .I1(mmcm_lock_count_reg[3]),
- .I2(mmcm_lock_count_reg[1]),
- .I3(mmcm_lock_count_reg[0]),
- .I4(mmcm_lock_count_reg[2]),
- .O(\mmcm_lock_count[9]_i_4_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[0]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[0]),
- .Q(mmcm_lock_count_reg[0]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[1]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[1]),
- .Q(mmcm_lock_count_reg[1]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[2]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[2]),
- .Q(mmcm_lock_count_reg[2]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[3]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[3]),
- .Q(mmcm_lock_count_reg[3]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[4]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[4]),
- .Q(mmcm_lock_count_reg[4]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[5]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[5]),
- .Q(mmcm_lock_count_reg[5]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[6]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[6]),
- .Q(mmcm_lock_count_reg[6]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[7]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[7]),
- .Q(mmcm_lock_count_reg[7]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[8]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[8]),
- .Q(mmcm_lock_count_reg[8]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- FDRE #(
- .INIT(1'b0))
- \mmcm_lock_count_reg[9]
- (.C(init_clk_in),
- .CE(\mmcm_lock_count[9]_i_2_n_0 ),
- .D(p_0_in__0[9]),
- .Q(mmcm_lock_count_reg[9]),
- .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- mmcm_lock_reclocked_i_2
- (.I0(mmcm_lock_count_reg[9]),
- .I1(mmcm_lock_count_reg[7]),
- .I2(mmcm_lock_count_reg[5]),
- .I3(\mmcm_lock_count[9]_i_4_n_0 ),
- .I4(mmcm_lock_count_reg[6]),
- .I5(mmcm_lock_count_reg[8]),
- .O(mmcm_lock_reclocked_i_2_n_0));
- FDRE #(
- .INIT(1'b0))
- mmcm_lock_reclocked_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .Q(mmcm_lock_reclocked),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hEFFF0010))
- pll_reset_asserted_i_1
- (.I0(tx_state[3]),
- .I1(tx_state[2]),
- .I2(tx_state[0]),
- .I3(tx_state[1]),
- .I4(pll_reset_asserted_reg_n_0),
- .O(pll_reset_asserted_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- pll_reset_asserted_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(pll_reset_asserted_i_1_n_0),
- .Q(pll_reset_asserted_reg_n_0),
- .R(AR));
- LUT5 #(
- .INIT(32'h40FF4040))
- reset_time_out_i_4
- (.I0(tx_state[1]),
- .I1(tx_state[2]),
- .I2(mmcm_lock_reclocked),
- .I3(tx_state[0]),
- .I4(init_wait_done_reg_n_0),
- .O(reset_time_out_i_4_n_0));
- FDRE #(
- .INIT(1'b0))
- reset_time_out_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(sync_PLL0LOCK_cdc_sync_n_1),
- .Q(reset_time_out),
- .R(AR));
- LUT5 #(
- .INIT(32'hFEFF0010))
- run_phase_alignment_int_i_1
- (.I0(tx_state[2]),
- .I1(tx_state[1]),
- .I2(tx_state[3]),
- .I3(tx_state[0]),
- .I4(run_phase_alignment_int),
- .O(run_phase_alignment_int_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(run_phase_alignment_int_i_1_n_0),
- .Q(run_phase_alignment_int),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- run_phase_alignment_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(scndry_out),
- .Q(run_phase_alignment_int_s3),
- .R(1'b0));
- north_channel_north_channel_cdc_sync__parameterized1_9 sync_PLL0LOCK_cdc_sync
- (.E(sync_PLL0LOCK_cdc_sync_n_0),
- .\FSM_sequential_tx_state_reg[0] (sync_PLL0LOCK_cdc_sync_n_1),
- .\FSM_sequential_tx_state_reg[0]_0 (init_wait_done_reg_n_0),
- .\FSM_sequential_tx_state_reg[0]_1 (\FSM_sequential_tx_state[3]_i_4_n_0 ),
- .\FSM_sequential_tx_state_reg[3]_i_5_0 (time_tlock_max_reg_n_0),
- .\FSM_sequential_tx_state_reg[3]_i_5_1 (pll_reset_asserted_reg_n_0),
- .\FSM_sequential_tx_state_reg[3]_i_5_2 (time_out_500us_reg_n_0),
- .\FSM_sequential_tx_state_reg[3]_i_5_3 (time_out_2ms_reg_n_0),
- .Q(tx_state),
- .init_clk_in(init_clk_in),
- .mmcm_lock_reclocked(mmcm_lock_reclocked),
- .quad1_common_lock_in(quad1_common_lock_in),
- .reset_time_out(reset_time_out),
- .reset_time_out_reg(\FSM_sequential_tx_state[3]_i_3_n_0 ),
- .reset_time_out_reg_0(reset_time_out_i_4_n_0),
- .txresetdone_s3(txresetdone_s3));
- north_channel_north_channel_cdc_sync__parameterized1_10 sync_PLL1LOCK_cdc_sync
- (.init_clk_in(init_clk_in));
- north_channel_north_channel_cdc_sync__parameterized6_11 sync_TXRESETDONE_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(txresetdone_s2),
- .txfsm_txresetdone_r(txfsm_txresetdone_r),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized1_12 sync_mmcm_lock_reclocked_cdc_sync
- (.PLL_NOT_LOCKED(PLL_NOT_LOCKED),
- .SR(sync_mmcm_lock_reclocked_cdc_sync_n_0),
- .init_clk_in(init_clk_in),
- .mmcm_lock_reclocked(mmcm_lock_reclocked),
- .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_cdc_sync_n_1),
- .mmcm_lock_reclocked_reg_0(mmcm_lock_reclocked_i_2_n_0));
- north_channel_north_channel_cdc_sync__parameterized3 sync_run_phase_alignment_int_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(scndry_out),
- .run_phase_alignment_int(run_phase_alignment_int),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized6_13 sync_time_out_wait_bypass_cdc_sync
- (.init_clk_in(init_clk_in),
- .out(time_out_wait_bypass_s2),
- .time_out_wait_bypass(time_out_wait_bypass),
- .user_clk(user_clk));
- north_channel_north_channel_cdc_sync__parameterized3_14 sync_tx_fsm_reset_done_int_cdc_sync
- (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg ),
- .init_clk_in(init_clk_in),
- .out(out),
- .tx_fsm_reset_done_int(tx_fsm_reset_done_int),
- .user_clk(user_clk));
- LUT5 #(
- .INIT(32'h0000AAAB))
- time_out_2ms_i_1__0
- (.I0(time_out_2ms_reg_n_0),
- .I1(\time_out_counter[0]_i_5_n_0 ),
- .I2(time_out_2ms_i_2__0_n_0),
- .I3(\time_out_counter[0]_i_3__0_n_0 ),
- .I4(reset_time_out),
- .O(time_out_2ms_i_1__0_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFF8FFFFFF))
- time_out_2ms_i_2__0
- (.I0(time_out_counter_reg[7]),
- .I1(time_out_counter_reg[6]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[16]),
- .I4(time_out_counter_reg[17]),
- .I5(time_out_counter_reg[2]),
- .O(time_out_2ms_i_2__0_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_2ms_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_2ms_i_1__0_n_0),
- .Q(time_out_2ms_reg_n_0),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h00000000AAAAAAAE))
- time_out_500us_i_1
- (.I0(time_out_500us_reg_n_0),
- .I1(time_out_500us_i_2_n_0),
- .I2(time_out_500us_i_3_n_0),
- .I3(time_out_500us_i_4_n_0),
- .I4(time_out_500us_i_5_n_0),
- .I5(reset_time_out),
- .O(time_out_500us_i_1_n_0));
- LUT6 #(
- .INIT(64'h0000000000000008))
- time_out_500us_i_2
- (.I0(time_out_counter_reg[12]),
- .I1(time_out_counter_reg[13]),
- .I2(time_out_counter_reg[16]),
- .I3(time_out_counter_reg[17]),
- .I4(time_out_counter_reg[9]),
- .I5(time_out_counter_reg[11]),
- .O(time_out_500us_i_2_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF0DFF))
- time_out_500us_i_3
- (.I0(time_out_counter_reg[15]),
- .I1(time_out_counter_reg[16]),
- .I2(time_out_counter_reg[17]),
- .I3(time_out_counter_reg[2]),
- .I4(time_out_counter_reg[0]),
- .I5(time_out_counter_reg[1]),
- .O(time_out_500us_i_3_n_0));
- LUT4 #(
- .INIT(16'hDFFF))
- time_out_500us_i_4
- (.I0(time_out_counter_reg[14]),
- .I1(time_out_counter_reg[6]),
- .I2(time_out_counter_reg[10]),
- .I3(time_out_counter_reg[5]),
- .O(time_out_500us_i_4_n_0));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT4 #(
- .INIT(16'hFFFE))
- time_out_500us_i_5
- (.I0(time_out_counter_reg[7]),
- .I1(time_out_counter_reg[4]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[3]),
- .O(time_out_500us_i_5_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_500us_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_500us_i_1_n_0),
- .Q(time_out_500us_reg_n_0),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFEFFF))
- \time_out_counter[0]_i_1__0
- (.I0(\time_out_counter[0]_i_3__0_n_0 ),
- .I1(time_out_counter_reg[2]),
- .I2(time_out_counter_reg[17]),
- .I3(time_out_counter_reg[16]),
- .I4(\time_out_counter[0]_i_4_n_0 ),
- .I5(\time_out_counter[0]_i_5_n_0 ),
- .O(time_out_counter));
- LUT6 #(
- .INIT(64'hFFFFEFFFFFFFFFFF))
- \time_out_counter[0]_i_3__0
- (.I0(time_out_counter_reg[1]),
- .I1(time_out_counter_reg[0]),
- .I2(time_out_counter_reg[12]),
- .I3(time_out_counter_reg[14]),
- .I4(time_out_counter_reg[13]),
- .I5(time_out_counter_reg[15]),
- .O(\time_out_counter[0]_i_3__0_n_0 ));
- LUT3 #(
- .INIT(8'hEA))
- \time_out_counter[0]_i_4
- (.I0(time_out_counter_reg[8]),
- .I1(time_out_counter_reg[6]),
- .I2(time_out_counter_reg[7]),
- .O(\time_out_counter[0]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \time_out_counter[0]_i_5
- (.I0(time_out_counter_reg[9]),
- .I1(time_out_counter_reg[11]),
- .I2(time_out_counter_reg[8]),
- .I3(time_out_counter_reg[10]),
- .I4(\time_out_counter[0]_i_7__0_n_0 ),
- .O(\time_out_counter[0]_i_5_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \time_out_counter[0]_i_6
- (.I0(time_out_counter_reg[0]),
- .O(\time_out_counter[0]_i_6_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT4 #(
- .INIT(16'hEFFF))
- \time_out_counter[0]_i_7__0
- (.I0(time_out_counter_reg[5]),
- .I1(time_out_counter_reg[3]),
- .I2(time_out_counter_reg[7]),
- .I3(time_out_counter_reg[4]),
- .O(\time_out_counter[0]_i_7__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[0]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_7 ),
- .Q(time_out_counter_reg[0]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[0]_i_2
- (.CI(1'b0),
- .CO({\time_out_counter_reg[0]_i_2_n_0 ,\time_out_counter_reg[0]_i_2_n_1 ,\time_out_counter_reg[0]_i_2_n_2 ,\time_out_counter_reg[0]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\time_out_counter_reg[0]_i_2_n_4 ,\time_out_counter_reg[0]_i_2_n_5 ,\time_out_counter_reg[0]_i_2_n_6 ,\time_out_counter_reg[0]_i_2_n_7 }),
- .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_6_n_0 }));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[10]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_5 ),
- .Q(time_out_counter_reg[10]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[11]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_4 ),
- .Q(time_out_counter_reg[11]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[12]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_7 ),
- .Q(time_out_counter_reg[12]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[12]_i_1
- (.CI(\time_out_counter_reg[8]_i_1_n_0 ),
- .CO({\time_out_counter_reg[12]_i_1_n_0 ,\time_out_counter_reg[12]_i_1_n_1 ,\time_out_counter_reg[12]_i_1_n_2 ,\time_out_counter_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[12]_i_1_n_4 ,\time_out_counter_reg[12]_i_1_n_5 ,\time_out_counter_reg[12]_i_1_n_6 ,\time_out_counter_reg[12]_i_1_n_7 }),
- .S(time_out_counter_reg[15:12]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[13]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_6 ),
- .Q(time_out_counter_reg[13]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[14]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_5 ),
- .Q(time_out_counter_reg[14]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[15]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[12]_i_1_n_4 ),
- .Q(time_out_counter_reg[15]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[16]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1_n_7 ),
- .Q(time_out_counter_reg[16]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[16]_i_1
- (.CI(\time_out_counter_reg[12]_i_1_n_0 ),
- .CO({\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED [3:1],\time_out_counter_reg[16]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED [3:2],\time_out_counter_reg[16]_i_1_n_6 ,\time_out_counter_reg[16]_i_1_n_7 }),
- .S({1'b0,1'b0,time_out_counter_reg[17:16]}));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[17]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[16]_i_1_n_6 ),
- .Q(time_out_counter_reg[17]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[1]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_6 ),
- .Q(time_out_counter_reg[1]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[2]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_5 ),
- .Q(time_out_counter_reg[2]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[3]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[0]_i_2_n_4 ),
- .Q(time_out_counter_reg[3]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[4]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_7 ),
- .Q(time_out_counter_reg[4]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[4]_i_1
- (.CI(\time_out_counter_reg[0]_i_2_n_0 ),
- .CO({\time_out_counter_reg[4]_i_1_n_0 ,\time_out_counter_reg[4]_i_1_n_1 ,\time_out_counter_reg[4]_i_1_n_2 ,\time_out_counter_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[4]_i_1_n_4 ,\time_out_counter_reg[4]_i_1_n_5 ,\time_out_counter_reg[4]_i_1_n_6 ,\time_out_counter_reg[4]_i_1_n_7 }),
- .S(time_out_counter_reg[7:4]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[5]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_6 ),
- .Q(time_out_counter_reg[5]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[6]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_5 ),
- .Q(time_out_counter_reg[6]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[7]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[4]_i_1_n_4 ),
- .Q(time_out_counter_reg[7]),
- .R(reset_time_out));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[8]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_7 ),
- .Q(time_out_counter_reg[8]),
- .R(reset_time_out));
- CARRY4 \time_out_counter_reg[8]_i_1
- (.CI(\time_out_counter_reg[4]_i_1_n_0 ),
- .CO({\time_out_counter_reg[8]_i_1_n_0 ,\time_out_counter_reg[8]_i_1_n_1 ,\time_out_counter_reg[8]_i_1_n_2 ,\time_out_counter_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\time_out_counter_reg[8]_i_1_n_4 ,\time_out_counter_reg[8]_i_1_n_5 ,\time_out_counter_reg[8]_i_1_n_6 ,\time_out_counter_reg[8]_i_1_n_7 }),
- .S(time_out_counter_reg[11:8]));
- FDRE #(
- .INIT(1'b0))
- \time_out_counter_reg[9]
- (.C(init_clk_in),
- .CE(time_out_counter),
- .D(\time_out_counter_reg[8]_i_1_n_6 ),
- .Q(time_out_counter_reg[9]),
- .R(reset_time_out));
- LUT4 #(
- .INIT(16'hAB00))
- time_out_wait_bypass_i_1
- (.I0(time_out_wait_bypass),
- .I1(\wait_bypass_count[0]_i_4_n_0 ),
- .I2(tx_fsm_reset_done_int_s3),
- .I3(run_phase_alignment_int_s3),
- .O(time_out_wait_bypass_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(time_out_wait_bypass_i_1_n_0),
- .Q(time_out_wait_bypass),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- time_out_wait_bypass_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_out_wait_bypass_s2),
- .Q(time_out_wait_bypass_s3),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h00000000AAAAAABA))
- time_tlock_max_i_1__0
- (.I0(time_tlock_max_reg_n_0),
- .I1(time_tlock_max_i_2_n_0),
- .I2(\time_out_counter[0]_i_4_n_0 ),
- .I3(time_tlock_max_i_3_n_0),
- .I4(\time_out_counter[0]_i_5_n_0 ),
- .I5(reset_time_out),
- .O(time_tlock_max_i_1__0_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFDFFFD))
- time_tlock_max_i_2
- (.I0(time_out_counter_reg[2]),
- .I1(time_out_counter_reg[0]),
- .I2(time_out_counter_reg[1]),
- .I3(time_out_counter_reg[15]),
- .I4(time_out_counter_reg[16]),
- .I5(time_out_counter_reg[17]),
- .O(time_tlock_max_i_2_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFF7))
- time_tlock_max_i_3
- (.I0(time_out_counter_reg[12]),
- .I1(time_out_counter_reg[13]),
- .I2(time_out_counter_reg[16]),
- .I3(time_out_counter_reg[17]),
- .I4(time_out_counter_reg[14]),
- .O(time_tlock_max_i_3_n_0));
- FDRE #(
- .INIT(1'b0))
- time_tlock_max_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(time_tlock_max_i_1__0_n_0),
- .Q(time_tlock_max_reg_n_0),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT5 #(
- .INIT(32'hFFFF0200))
- tx_fsm_reset_done_int_i_1
- (.I0(tx_state[0]),
- .I1(tx_state[2]),
- .I2(tx_state[1]),
- .I3(tx_state[3]),
- .I4(tx_fsm_reset_done_int),
- .O(tx_fsm_reset_done_int_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- tx_fsm_reset_done_int_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(tx_fsm_reset_done_int_i_1_n_0),
- .Q(tx_fsm_reset_done_int),
- .R(AR));
- (* equivalent_register_removal = "no" *)
- FDRE #(
- .INIT(1'b0))
- tx_fsm_reset_done_int_s3_reg
- (.C(user_clk),
- .CE(1'b1),
- .D(out),
- .Q(tx_fsm_reset_done_int_s3),
- .R(1'b0));
- LUT2 #(
- .INIT(4'h2))
- tx_lock_INST_0
- (.I0(quad1_common_lock_in),
- .I1(MMCM_RESET),
- .O(tx_lock));
- FDRE #(
- .INIT(1'b0))
- txresetdone_s3_reg
- (.C(init_clk_in),
- .CE(1'b1),
- .D(txresetdone_s2),
- .Q(txresetdone_s3),
- .R(1'b0));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_1
- (.I0(run_phase_alignment_int_s3),
- .O(clear));
- LUT2 #(
- .INIT(4'h2))
- \wait_bypass_count[0]_i_2
- (.I0(\wait_bypass_count[0]_i_4_n_0 ),
- .I1(tx_fsm_reset_done_int_s3),
- .O(\wait_bypass_count[0]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \wait_bypass_count[0]_i_4
- (.I0(\wait_bypass_count[0]_i_6_n_0 ),
- .I1(\wait_bypass_count[0]_i_7_n_0 ),
- .I2(\wait_bypass_count[0]_i_8_n_0 ),
- .I3(\wait_bypass_count[0]_i_9_n_0 ),
- .O(\wait_bypass_count[0]_i_4_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \wait_bypass_count[0]_i_5
- (.I0(wait_bypass_count_reg[0]),
- .O(\wait_bypass_count[0]_i_5_n_0 ));
- LUT4 #(
- .INIT(16'h7FFF))
- \wait_bypass_count[0]_i_6
- (.I0(wait_bypass_count_reg[5]),
- .I1(wait_bypass_count_reg[4]),
- .I2(wait_bypass_count_reg[7]),
- .I3(wait_bypass_count_reg[6]),
- .O(\wait_bypass_count[0]_i_6_n_0 ));
- LUT4 #(
- .INIT(16'h7FFF))
- \wait_bypass_count[0]_i_7
- (.I0(wait_bypass_count_reg[1]),
- .I1(wait_bypass_count_reg[0]),
- .I2(wait_bypass_count_reg[3]),
- .I3(wait_bypass_count_reg[2]),
- .O(\wait_bypass_count[0]_i_7_n_0 ));
- LUT4 #(
- .INIT(16'hFF7F))
- \wait_bypass_count[0]_i_8
- (.I0(wait_bypass_count_reg[13]),
- .I1(wait_bypass_count_reg[12]),
- .I2(wait_bypass_count_reg[15]),
- .I3(wait_bypass_count_reg[14]),
- .O(\wait_bypass_count[0]_i_8_n_0 ));
- LUT4 #(
- .INIT(16'hFFFD))
- \wait_bypass_count[0]_i_9
- (.I0(wait_bypass_count_reg[9]),
- .I1(wait_bypass_count_reg[8]),
- .I2(wait_bypass_count_reg[11]),
- .I3(wait_bypass_count_reg[10]),
- .O(\wait_bypass_count[0]_i_9_n_0 ));
- FDRE \wait_bypass_count_reg[0]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_7 ),
- .Q(wait_bypass_count_reg[0]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[0]_i_3
- (.CI(1'b0),
- .CO({\wait_bypass_count_reg[0]_i_3_n_0 ,\wait_bypass_count_reg[0]_i_3_n_1 ,\wait_bypass_count_reg[0]_i_3_n_2 ,\wait_bypass_count_reg[0]_i_3_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\wait_bypass_count_reg[0]_i_3_n_4 ,\wait_bypass_count_reg[0]_i_3_n_5 ,\wait_bypass_count_reg[0]_i_3_n_6 ,\wait_bypass_count_reg[0]_i_3_n_7 }),
- .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5_n_0 }));
- FDRE \wait_bypass_count_reg[10]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_5 ),
- .Q(wait_bypass_count_reg[10]),
- .R(clear));
- FDRE \wait_bypass_count_reg[11]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_4 ),
- .Q(wait_bypass_count_reg[11]),
- .R(clear));
- FDRE \wait_bypass_count_reg[12]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_7 ),
- .Q(wait_bypass_count_reg[12]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[12]_i_1
- (.CI(\wait_bypass_count_reg[8]_i_1_n_0 ),
- .CO({\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED [3],\wait_bypass_count_reg[12]_i_1_n_1 ,\wait_bypass_count_reg[12]_i_1_n_2 ,\wait_bypass_count_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[12]_i_1_n_4 ,\wait_bypass_count_reg[12]_i_1_n_5 ,\wait_bypass_count_reg[12]_i_1_n_6 ,\wait_bypass_count_reg[12]_i_1_n_7 }),
- .S(wait_bypass_count_reg[15:12]));
- FDRE \wait_bypass_count_reg[13]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_6 ),
- .Q(wait_bypass_count_reg[13]),
- .R(clear));
- FDRE \wait_bypass_count_reg[14]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_5 ),
- .Q(wait_bypass_count_reg[14]),
- .R(clear));
- FDRE \wait_bypass_count_reg[15]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[12]_i_1_n_4 ),
- .Q(wait_bypass_count_reg[15]),
- .R(clear));
- FDRE \wait_bypass_count_reg[1]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_6 ),
- .Q(wait_bypass_count_reg[1]),
- .R(clear));
- FDRE \wait_bypass_count_reg[2]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_5 ),
- .Q(wait_bypass_count_reg[2]),
- .R(clear));
- FDRE \wait_bypass_count_reg[3]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[0]_i_3_n_4 ),
- .Q(wait_bypass_count_reg[3]),
- .R(clear));
- FDRE \wait_bypass_count_reg[4]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_7 ),
- .Q(wait_bypass_count_reg[4]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[4]_i_1
- (.CI(\wait_bypass_count_reg[0]_i_3_n_0 ),
- .CO({\wait_bypass_count_reg[4]_i_1_n_0 ,\wait_bypass_count_reg[4]_i_1_n_1 ,\wait_bypass_count_reg[4]_i_1_n_2 ,\wait_bypass_count_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[4]_i_1_n_4 ,\wait_bypass_count_reg[4]_i_1_n_5 ,\wait_bypass_count_reg[4]_i_1_n_6 ,\wait_bypass_count_reg[4]_i_1_n_7 }),
- .S(wait_bypass_count_reg[7:4]));
- FDRE \wait_bypass_count_reg[5]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_6 ),
- .Q(wait_bypass_count_reg[5]),
- .R(clear));
- FDRE \wait_bypass_count_reg[6]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_5 ),
- .Q(wait_bypass_count_reg[6]),
- .R(clear));
- FDRE \wait_bypass_count_reg[7]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[4]_i_1_n_4 ),
- .Q(wait_bypass_count_reg[7]),
- .R(clear));
- FDRE \wait_bypass_count_reg[8]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_7 ),
- .Q(wait_bypass_count_reg[8]),
- .R(clear));
- CARRY4 \wait_bypass_count_reg[8]_i_1
- (.CI(\wait_bypass_count_reg[4]_i_1_n_0 ),
- .CO({\wait_bypass_count_reg[8]_i_1_n_0 ,\wait_bypass_count_reg[8]_i_1_n_1 ,\wait_bypass_count_reg[8]_i_1_n_2 ,\wait_bypass_count_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\wait_bypass_count_reg[8]_i_1_n_4 ,\wait_bypass_count_reg[8]_i_1_n_5 ,\wait_bypass_count_reg[8]_i_1_n_6 ,\wait_bypass_count_reg[8]_i_1_n_7 }),
- .S(wait_bypass_count_reg[11:8]));
- FDRE \wait_bypass_count_reg[9]
- (.C(user_clk),
- .CE(\wait_bypass_count[0]_i_2_n_0 ),
- .D(\wait_bypass_count_reg[8]_i_1_n_6 ),
- .Q(wait_bypass_count_reg[9]),
- .R(clear));
- LUT1 #(
- .INIT(2'h1))
- \wait_time_cnt[0]_i_1
- (.I0(wait_time_cnt_reg[0]),
- .O(wait_time_cnt0[0]));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT2 #(
- .INIT(4'h9))
- \wait_time_cnt[1]_i_1
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .O(\wait_time_cnt[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT3 #(
- .INIT(8'hE1))
- \wait_time_cnt[2]_i_1
- (.I0(wait_time_cnt_reg[0]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[2]),
- .O(wait_time_cnt0[2]));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT4 #(
- .INIT(16'hFE01))
- \wait_time_cnt[3]_i_1
- (.I0(wait_time_cnt_reg[2]),
- .I1(wait_time_cnt_reg[1]),
- .I2(wait_time_cnt_reg[0]),
- .I3(wait_time_cnt_reg[3]),
- .O(wait_time_cnt0[3]));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT5 #(
- .INIT(32'hAAAAAAA9))
- \wait_time_cnt[4]_i_1
- (.I0(wait_time_cnt_reg[4]),
- .I1(wait_time_cnt_reg[2]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[1]),
- .O(wait_time_cnt0[4]));
- LUT6 #(
- .INIT(64'hFFFFFFFE00000001))
- \wait_time_cnt[5]_i_1
- (.I0(wait_time_cnt_reg[4]),
- .I1(wait_time_cnt_reg[2]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[0]),
- .I4(wait_time_cnt_reg[1]),
- .I5(wait_time_cnt_reg[5]),
- .O(wait_time_cnt0[5]));
- LUT4 #(
- .INIT(16'h1300))
- \wait_time_cnt[6]_i_1__0
- (.I0(tx_state[1]),
- .I1(tx_state[3]),
- .I2(tx_state[2]),
- .I3(tx_state[0]),
- .O(\wait_time_cnt[6]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \wait_time_cnt[6]_i_2
- (.I0(wait_time_cnt_reg[1]),
- .I1(\wait_time_cnt[6]_i_4_n_0 ),
- .I2(wait_time_cnt_reg[5]),
- .I3(wait_time_cnt_reg[4]),
- .I4(wait_time_cnt_reg[6]),
- .I5(wait_time_cnt_reg[0]),
- .O(sel));
- LUT4 #(
- .INIT(16'hA9AA))
- \wait_time_cnt[6]_i_3
- (.I0(wait_time_cnt_reg[6]),
- .I1(wait_time_cnt_reg[4]),
- .I2(wait_time_cnt_reg[5]),
- .I3(\wait_time_cnt[6]_i_5_n_0 ),
- .O(wait_time_cnt0[6]));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT2 #(
- .INIT(4'hE))
- \wait_time_cnt[6]_i_4
- (.I0(wait_time_cnt_reg[2]),
- .I1(wait_time_cnt_reg[3]),
- .O(\wait_time_cnt[6]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT4 #(
- .INIT(16'h0001))
- \wait_time_cnt[6]_i_5
- (.I0(wait_time_cnt_reg[1]),
- .I1(wait_time_cnt_reg[0]),
- .I2(wait_time_cnt_reg[3]),
- .I3(wait_time_cnt_reg[2]),
- .O(\wait_time_cnt[6]_i_5_n_0 ));
- FDRE \wait_time_cnt_reg[0]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[0]),
- .Q(wait_time_cnt_reg[0]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDRE \wait_time_cnt_reg[1]
- (.C(init_clk_in),
- .CE(sel),
- .D(\wait_time_cnt[1]_i_1_n_0 ),
- .Q(wait_time_cnt_reg[1]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDSE \wait_time_cnt_reg[2]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[2]),
- .Q(wait_time_cnt_reg[2]),
- .S(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDRE \wait_time_cnt_reg[3]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[3]),
- .Q(wait_time_cnt_reg[3]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDRE \wait_time_cnt_reg[4]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[4]),
- .Q(wait_time_cnt_reg[4]),
- .R(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDSE \wait_time_cnt_reg[5]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[5]),
- .Q(wait_time_cnt_reg[5]),
- .S(\wait_time_cnt[6]_i_1__0_n_0 ));
- FDSE \wait_time_cnt_reg[6]
- (.C(init_clk_in),
- .CE(sel),
- .D(wait_time_cnt0[6]),
- .Q(wait_time_cnt_reg[6]),
- .S(\wait_time_cnt[6]_i_1__0_n_0 ));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_stub.v b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_stub.v
deleted file mode 100644
index 54fb9c530ec8f7720bb2effffefdbcda00795874..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_stub.v
+++ /dev/null
@@ -1,81 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 28 10:16:16 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_stub.v
-// Design : north_channel
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-module north_channel(s_axi_tx_tdata, s_axi_tx_tvalid,
- s_axi_tx_tready, s_axi_tx_tkeep, s_axi_tx_tlast, m_axi_rx_tdata, m_axi_rx_tvalid,
- m_axi_rx_tkeep, m_axi_rx_tlast, s_axi_ufc_tx_tvalid, s_axi_ufc_tx_tdata,
- s_axi_ufc_tx_tready, m_axi_ufc_rx_tdata, m_axi_ufc_rx_tkeep, m_axi_ufc_rx_tvalid,
- m_axi_ufc_rx_tlast, rxp, rxn, txp, txn, gt_refclk1, frame_err, hard_err, soft_err, channel_up,
- lane_up, user_clk, sync_clk, reset, power_down, loopback, gt_reset, tx_lock, sys_reset_out,
- init_clk_in, tx_resetdone_out, rx_resetdone_out, link_reset_out, drpclk_in, drpaddr_in,
- drpdi_in, drpdo_out, drpen_in, drprdy_out, drpwe_in, gt_common_reset_out,
- gt0_pll0refclklost_in, quad1_common_lock_in, GT0_PLL0OUTCLK_IN, GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN, GT0_PLL1OUTREFCLK_IN, tx_out_clk, pll_not_locked)
-/* synthesis syn_black_box black_box_pad_pin="s_axi_tx_tdata[0:31],s_axi_tx_tvalid,s_axi_tx_tready,s_axi_tx_tkeep[0:3],s_axi_tx_tlast,m_axi_rx_tdata[0:31],m_axi_rx_tvalid,m_axi_rx_tkeep[0:3],m_axi_rx_tlast,s_axi_ufc_tx_tvalid,s_axi_ufc_tx_tdata[0:2],s_axi_ufc_tx_tready,m_axi_ufc_rx_tdata[0:31],m_axi_ufc_rx_tkeep[0:3],m_axi_ufc_rx_tvalid,m_axi_ufc_rx_tlast,rxp[0:0],rxn[0:0],txp[0:0],txn[0:0],gt_refclk1,frame_err,hard_err,soft_err,channel_up,lane_up[0:0],user_clk,sync_clk,reset,power_down,loopback[2:0],gt_reset,tx_lock,sys_reset_out,init_clk_in,tx_resetdone_out,rx_resetdone_out,link_reset_out,drpclk_in,drpaddr_in[8:0],drpdi_in[15:0],drpdo_out[15:0],drpen_in,drprdy_out,drpwe_in,gt_common_reset_out,gt0_pll0refclklost_in,quad1_common_lock_in,GT0_PLL0OUTCLK_IN,GT0_PLL1OUTCLK_IN,GT0_PLL0OUTREFCLK_IN,GT0_PLL1OUTREFCLK_IN,tx_out_clk,pll_not_locked" */;
- input [0:31]s_axi_tx_tdata;
- input s_axi_tx_tvalid;
- output s_axi_tx_tready;
- input [0:3]s_axi_tx_tkeep;
- input s_axi_tx_tlast;
- output [0:31]m_axi_rx_tdata;
- output m_axi_rx_tvalid;
- output [0:3]m_axi_rx_tkeep;
- output m_axi_rx_tlast;
- input s_axi_ufc_tx_tvalid;
- input [0:2]s_axi_ufc_tx_tdata;
- output s_axi_ufc_tx_tready;
- output [0:31]m_axi_ufc_rx_tdata;
- output [0:3]m_axi_ufc_rx_tkeep;
- output m_axi_ufc_rx_tvalid;
- output m_axi_ufc_rx_tlast;
- input [0:0]rxp;
- input [0:0]rxn;
- output [0:0]txp;
- output [0:0]txn;
- input gt_refclk1;
- output frame_err;
- output hard_err;
- output soft_err;
- output channel_up;
- output [0:0]lane_up;
- input user_clk;
- input sync_clk;
- input reset;
- input power_down;
- input [2:0]loopback;
- input gt_reset;
- output tx_lock;
- output sys_reset_out;
- input init_clk_in;
- output tx_resetdone_out;
- output rx_resetdone_out;
- output link_reset_out;
- input drpclk_in;
- input [8:0]drpaddr_in;
- input [15:0]drpdi_in;
- output [15:0]drpdo_out;
- input drpen_in;
- output drprdy_out;
- input drpwe_in;
- output gt_common_reset_out;
- input gt0_pll0refclklost_in;
- input quad1_common_lock_in;
- input GT0_PLL0OUTCLK_IN;
- input GT0_PLL1OUTCLK_IN;
- input GT0_PLL0OUTREFCLK_IN;
- input GT0_PLL1OUTREFCLK_IN;
- output tx_out_clk;
- input pll_not_locked;
-endmodule
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/doc/aurora_8b10b_v11_1_changelog.txt b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/doc/aurora_8b10b_v11_1_changelog.txt
deleted file mode 100755
index 7216ee36fdca3a760aa5afc7696e627329ff4e39..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/doc/aurora_8b10b_v11_1_changelog.txt
+++ /dev/null
@@ -1,294 +0,0 @@
-2019.2:
- * Version 11.1 (Rev. 8)
- * Revision change in one or more subcores
-
-2019.1.3:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1.2:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1.1:
- * Version 11.1 (Rev. 7)
- * No changes
-
-2019.1:
- * Version 11.1 (Rev. 7)
- * General: Added support for AKINTEX7 devices
- * Revision change in one or more subcores
-
-2018.3.1:
- * Version 11.1 (Rev. 6)
- * No changes
-
-2018.3:
- * Version 11.1 (Rev. 6)
- * General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
- * General: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
- * Revision change in one or more subcores
-
-2018.2:
- * Version 11.1 (Rev. 5)
- * Bug Fix: Fixed display only issue showing improper clock frequencies for tx_out_clk and sync_clk in IPI flow for GTP devices.
- * Revision change in one or more subcores
-
-2018.1:
- * Version 11.1 (Rev. 4)
- * Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection
- * Bug Fix: Fixed a bug that generated unexpected error messages during re-customization of IP in IP Integrator
- * Other: Added support for Artix-7 XA7A12TCPG238/CSG325 and XA7A25TCPG238/CSG325 devices
- * Revision change in one or more subcores
-
-2017.4:
- * Version 11.1 (Rev. 3)
- * General: Added support for CPG238 packages in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * Revision change in one or more subcores
-
-2017.3:
- * Version 11.1 (Rev. 2)
- * General: GTP attribute update in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * General: Standard CC logic is enabled after lane-up itself instead of waiting till channel-up condition
- * General: Added optional parameter C_DOUBLE_GTRXRESET to assert additional reset for handling errors during lane initialisation in duplex links with very high ppm differences
- * General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides
- * Revision change in one or more subcores
-
-2017.2:
- * Version 11.1 (Rev. 1)
- * Bug Fix: Unused gtrxresetseq drp signals removed from TX-simplex based designs
- * Other: UltraScale GT Wizard version upgrade.
-
-2017.1:
- * Version 11.1
- * New Feature: US GT Wizard Instance can be brought out of Aurora IP for UltraScale devices
- * Other: gt_powergood from US GT Wizard is made an output port on Aurora core when GT is inside Aurora IP
- * Other: gt_powergood from US GT Wizard is brought to gt wrapper in example design when the GT is in example design, outside Aurora IP
- * Revision change in one or more subcores
-
-2016.4:
- * Version 11.0 (Rev. 7)
- * General: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti devices
- * Revision change in one or more subcores
-
-2016.3:
- * Version 11.0 (Rev. 6)
- * Bug Fix: Fixed issue in failure due to floating point precision difference of gt_refclk in validate BD design in IPI
- * Bug Fix: Fixed TXDIFFCTRL and DMONITOROUT port widths for UltraScale devices in IP symbol
- * Feature Enhancement: Added Advanced RX GT Options selection in GUI
- * Other: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
- * Revision change in one or more subcores
-
-2016.2:
- * Version 11.0 (Rev. 5)
- * Fixed Artix7 periodic channel up toggle issue
- * Revision change in one or more subcores
-
-2016.1:
- * Version 11.0 (Rev. 4)
- * Fixed preserving Equalizer selection issue when additional transceiver ports option is enabled
- * Adjusted line rate and associated frequency limits for -1,-1H,1HV,-1L,-1LV, -2LV speed grade devices to match UltraScale FPGAs Data Sheet
- * Revision change in one or more subcores
-
-2015.4.2:
- * Version 11.0 (Rev. 3)
- * No changes
-
-2015.4.1:
- * Version 11.0 (Rev. 3)
- * No changes
-
-2015.4:
- * Version 11.0 (Rev. 3)
- * Added support for new speedgrades of XQ7K325T and XQ7K410T devices
- * Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices
- * Added support for new speedgrade of XQ7A050T, XQ7A100T and XQ7A200T devices
- * Revision change in one or more subcores
-
-2015.3:
- * Version 11.0 (Rev. 2)
- * Updated RTL to fix CDC warnings
- * Added support for UltraScale+ devices
- * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
-
-2015.2.1:
- * Version 11.0 (Rev. 1)
- * No changes
-
-2015.2:
- * Version 11.0 (Rev. 1)
- * Added support for XQ7VX690T, XQ7Z045 and XQ7Z100 devices
- * BUFG removed on DRP Clock input
- * TXPMARESETDONE used in rxstartupfsm for GTP RX-onlySimplex configuration
- * set_false_path constrain on synchronizers updated
-
-2015.1:
- * Version 11.0
- * Added support for 7 Series devices with FFV and FBV Pb-Free RoHs package
- * Added txinhibit and pcsrsvdin optional transceiver control and status ports
- * Both reset and gt_reset ports made asynchronous to the core
- * Standard CC module made part of IP, do_cc and warn_cc ports removed
- * Flow control ports grouped into AXI4 Stream interfaces
- * Control and status ports are grouped as display interfaces
- * Added support for single ended clocking option to INIT_CLK and GTREFCLK
- * Added support for contiguous lane selection for Ultrascale devices
- * CRC resource utilization optimized
- * GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator
- * Line rate value restricted to 4 decimal digits for Ultrascale devices
- * INIT clock frequency value restricted to 6 decimal digits
-
-2014.4.1:
- * Version 10.3 (Rev. 2)
- * Ultrascale GT Wizard version updated
-
-2014.4:
- * Version 10.3 (Rev. 1)
- * Added support for new XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices
- * Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices
- * Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices
- * BUFG added to DRP Clock input
- * Line rate range for -2L speed grade 1.0V Artix devices updated to 6.25Gbps
- * Location constraint changed for Xilinx Evaluation platform boards
-
-2014.3:
- * Version 10.3
- * Ultrascale GT Wizard version updated
- * Added support for new Ultrascale devices
- * Added support for XQ7A50 devices
- * Added support for XA7Z030 devices
- * Added support for user configurable DRP clock and INIT clock through IP GUI
- * Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup
- * set_max_delay constrain changed to set_false_path constrains to destination flops
- * XDCs compliant with updated timing constraining guidelines
- * Added support for Xilinx Evaluation platform boards
- * User selectable option enabled for GT DRP interface in IPI systems
- * Added support for auto propagate to INIT and DRP clock in IPI systems
- * Fixed gt_dmonitorout_out data width mismatch issue for Zynq devices
- * Differential INIT clock input added to Ultrascale example design
- * Addressed CPLL power down circuit requirement for 7 series Transceivers - refer AR
- * GT startup fsms updated to be complain with 7 Series GT Wizard
- * Addressed update to GTH/GTP Production RX reset sequence implementation- refer AR
- * Parameter declaration issue with IES simulator addressed
-
-2014.2:
- * Version 10.2 (Rev. 1)
- * Ultrascale GT Wizard version change
- * Added support for XQ7Z045 RF900 devices
- * Fixed hold violation timing issues in Ultrascale device based designs
- * Updated channel bonding levels logic for >= 13 lanes in 4 byte mode
- * Fixed gt0_dmonitorout_out port width for GTX devices in transceiver debug ports
- * Free running INIT CLK is connected to VIO core in example design
- * Fixed latch inference issue in crc modules for VHDL designs
- * Updated CLK_COR_MIN_LAT and CLK_COR_MAX_LAT values for 16-GT (GTHE3_CHANNEL) in Ultrascale device
-
-2014.1:
- * Version 10.2
- * Added support for Ultrascale devices
- * Added support for XC7Z015, XC7A50T, XC7A35T devices
- * Added support for automotive aartix XA7A35, XA7A50T, XA7A75T & XA7A100T devices
- * Enhanced support for IP Integrator
- * Added Little endian support for data & flow control interfaces as non-default GUI selectable option
- * Fixed VHDL syntax issue on rxpmaresetdone_t signal for 7-series based designs
- * Updated OOC XDC with all the available clocks for the selected IP configuration
- * Fixed TXCRC and RXCRC modules to operate upon valid data and report correct CRC status
- * Updated core reset logic with tx_lock synchronization
- * Updated the simplex timer values for 7-series production silicon logic updates
- * Updated the hot-plug logic to handle clock domain crossing efficiently
- * Added recovery mechanism for channel bonding failure
-
-2013.4:
- * Version 10.1
- * Increased the number of optional transceiver control and status ports
-
-2013.3:
- * Version 10.0
- * Added support for XC7A75T device
- * Added startup FSM integration for 7-series GT reset sequence
- * Added GUI option to include or exclude Vivado Labtools support for debug
- * Updated line rate for A7 wire bond package devices for speed grade -2 and -3
- * Added GUI option to include or exclude shareable logic resources in the core. For details, refer to Migrating section of Product Guide - pg046-aurora-8b10b.pdf
- * Added optional transceiver control and status ports - Refer to pg046-aurora-8b10b.pdf
- * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
- * Reduced warnings in synthesis and simulation
- * Added support for Cadence IES and Synopsys VCS simulators
- * Added support for IP Integrator level 0
-
-2013.2:
- * Version 9.1
- * Artix-7 GTP and Virtex-7 GTH production attributes updates
- * XDC constraints processing order changed
- * Update for UFC packet drop in back to back data transfer
- * XQ7Z030-RB484 device support
-
-2013.1:
- * Version 9.0
- * Lower case IP level ports
- * Hot-plug timer update
- * CDC fixes
- * New reset sequence for GTRXRESET in Artix-7 GTP Production silicon
- * New reset sequence for GTRXRESET in Virtex-7 GTH Production silicon
- * Out-of-context (OOC) flow support
- * Zynq-7000 family support
-
-2012.4:
- * Version 8.3 (Rev. 1)
- * Artix-7 IES silicon support
- * Autoupgrade feature
-
-2012.3:
- * Version 8.3
- * Artix-7 family support
-
-2012.2:
- * Version 8.2
- * Virtex-7 HT device support
- * CRC feature addition
- * Hot-plug support for 7-series
- * XSIM simulator support
- * Native Vivado release
-
-(c) Copyright 2010 - 2019 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.dcp b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.dcp
deleted file mode 100644
index 43a0f61d79abb4a5f288613c929d5bd352761213..0000000000000000000000000000000000000000
Binary files a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.dcp and /dev/null differ
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.vhd b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.vhd
deleted file mode 100644
index a237579466159b1e48ee139389c7d7c53fef30ae..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.vhd
+++ /dev/null
@@ -1,346 +0,0 @@
-------------------------------------------------------------------------------/
--- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
-------------------------------------------------------------------------------/
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_misc.all;
- use IEEE.numeric_std.all;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
-
-entity south_channel is
- port (
- -- AXI TX Interface
-
- s_axi_tx_tdata : in std_logic_vector(0 to 31);
-
- s_axi_tx_tvalid : in std_logic;
- s_axi_tx_tready : out std_logic;
-
- s_axi_tx_tkeep : in std_logic_vector(0 to 3);
-
- s_axi_tx_tlast : in std_logic;
-
-
- -- AXI RX Interface
-
- m_axi_rx_tdata : out std_logic_vector(0 to 31);
-
- m_axi_rx_tvalid : out std_logic;
-
- m_axi_rx_tkeep : out std_logic_vector(0 to 3);
-
- m_axi_rx_tlast : out std_logic;
-
-
- -- User Flow Control TX Interface
- s_axi_ufc_tx_tvalid : in std_logic;
-
- s_axi_ufc_tx_tdata : in std_logic_vector(0 to 2);
- s_axi_ufc_tx_tready : out std_logic;
-
-
- -- User Flow Control RX Inteface
-
- m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31);
- m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3);
- m_axi_ufc_rx_tvalid : out std_logic;
- m_axi_ufc_rx_tlast : out std_logic;
-
-
-
- -- GT Serial I/O
- rxp : in std_logic_vector(0 downto 0);
- rxn : in std_logic_vector(0 downto 0);
-
- txp : out std_logic_vector(0 downto 0);
- txn : out std_logic_vector(0 downto 0);
-
- -- GT Reference Clock Interface
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
-
- frame_err : out std_logic;
- hard_err : out std_logic;
- soft_err : out std_logic;
- channel_up : out std_logic;
- lane_up : out std_logic_vector(0 downto 0);
-
-
-
-
- -- System Interface
- user_clk : in std_logic;
- sync_clk : in std_logic;
- reset : in std_logic;
-
- power_down : in std_logic;
- loopback : in std_logic_vector(2 downto 0);
- gt_reset : in std_logic;
- tx_lock : out std_logic;
- sys_reset_out : out std_logic;
- init_clk_in : in std_logic;
- tx_resetdone_out : out std_logic;
- rx_resetdone_out : out std_logic;
- link_reset_out : out std_logic;
-
- --DRP Ports
-
- drpclk_in : in std_logic;
- drpaddr_in : in std_logic_vector(8 downto 0);
- drpdi_in : in std_logic_vector(15 downto 0);
- drpdo_out : out std_logic_vector(15 downto 0);
- drpen_in : in std_logic;
- drprdy_out : out std_logic;
- drpwe_in : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- tx_out_clk : out std_logic;
- pll_not_locked : in std_logic
-
- );
-
-end south_channel;
-
-
-architecture STRUCTURE of south_channel is
- attribute core_generation_info : string;
- attribute core_generation_info of STRUCTURE : architecture is "south_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=1,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
-
- component south_channel_core
- port (
- -- TX Stream Interface
- S_AXI_TX_TDATA : in std_logic_vector(0 to 31);
- S_AXI_TX_TKEEP : in std_logic_vector(0 to 3);
- S_AXI_TX_TVALID : in std_logic;
- S_AXI_TX_TREADY : out std_logic;
- S_AXI_TX_TLAST : in std_logic;
-
- -- RX Stream Interface
- M_AXI_RX_TDATA : out std_logic_vector(0 to 31);
- M_AXI_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_RX_TVALID : out std_logic;
- M_AXI_RX_TLAST : out std_logic;
- -- User Flow Control TX Interface
-
- S_AXI_UFC_TX_REQ : in std_logic;
- S_AXI_UFC_TX_MS : in std_logic_vector(0 to 2);
- S_AXI_UFC_TX_ACK : out std_logic;
-
- -- User Flow Control RX Inteface
-
- M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31);
- M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3);
- M_AXI_UFC_RX_TVALID : out std_logic;
- M_AXI_UFC_RX_TLAST : out std_logic;
-
- -- GTX Serial I/O
- RXP : in std_logic;
- RXN : in std_logic;
- TXP : out std_logic;
- TXN : out std_logic;
-
- -- GT Reference Clock Interface
-
- gt_refclk1 : in std_logic;
-
- -- Error Detection Interface
- HARD_ERR : out std_logic;
- SOFT_ERR : out std_logic;
-
- -- Status
- CHANNEL_UP : out std_logic;
- LANE_UP : out std_logic;
-
-
- FRAME_ERR : out std_logic;
-
-
-
- -- Clock Compensation Control Interface
-
- -- System Interface
-
- USER_CLK : in std_logic;
- SYNC_CLK : in std_logic;
- GT_RESET : in std_logic;
- RESET : in std_logic;
- sys_reset_out : out std_logic;
- POWER_DOWN : in std_logic;
- LOOPBACK : in std_logic_vector(2 downto 0);
- TX_OUT_CLK : out std_logic;
- INIT_CLK_IN : in std_logic;
- PLL_NOT_LOCKED : in std_logic;
- TX_RESETDONE_OUT : out std_logic;
- RX_RESETDONE_OUT : out std_logic;
- LINK_RESET_OUT : out std_logic;
-
-
- drpclk_in : in std_logic;
- DRPADDR_IN : in std_logic_vector(8 downto 0);
- DRPDI_IN : in std_logic_vector(15 downto 0);
- DRPDO_OUT : out std_logic_vector(15 downto 0);
- DRPEN_IN : in std_logic;
- DRPRDY_OUT : out std_logic;
- DRPWE_IN : in std_logic;
-
- gt_common_reset_out : out std_logic;
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in : in std_logic;
- quad1_common_lock_in : in std_logic;
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN : in std_logic;
- GT0_PLL1OUTCLK_IN : in std_logic;
- GT0_PLL0OUTREFCLK_IN : in std_logic;
- GT0_PLL1OUTREFCLK_IN : in std_logic;
---____________________________COMMON PORTS_______________________________}
- TX_LOCK : out std_logic
- );
-
- end component;
-
-begin
-
- --*********************************Main Body of Code**********************************
-
- U0 : south_channel_core
- port map (
- -- AXI TX Interface
- s_axi_tx_tdata => s_axi_tx_tdata,
- s_axi_tx_tkeep => s_axi_tx_tkeep,
- s_axi_tx_tvalid => s_axi_tx_tvalid,
- s_axi_tx_tlast => s_axi_tx_tlast,
- s_axi_tx_tready => s_axi_tx_tready,
-
- -- AXI RX Interface
- m_axi_rx_tdata => m_axi_rx_tdata,
- m_axi_rx_tkeep => m_axi_rx_tkeep,
- m_axi_rx_tvalid => m_axi_rx_tvalid,
- m_axi_rx_tlast => m_axi_rx_tlast,
-
- -- User Flow Control TX Interface
- s_axi_ufc_tx_req => s_axi_ufc_tx_tvalid,
- s_axi_ufc_tx_ms => s_axi_ufc_tx_tdata,
- s_axi_ufc_tx_ack => s_axi_ufc_tx_tready,
-
- -- User Flow Control RX Inteface
- m_axi_ufc_rx_tdata => m_axi_ufc_rx_tdata,
- m_axi_ufc_rx_tkeep => m_axi_ufc_rx_tkeep,
- m_axi_ufc_rx_tvalid => m_axi_ufc_rx_tvalid,
- m_axi_ufc_rx_tlast => m_axi_ufc_rx_tlast,
-
- -- GT Serial I/O
- rxp => rxp(0),
- rxn => rxn(0),
- txp => txp(0),
- txn => txn(0),
-
- -- GT Reference Clock Interface
- gt_refclk1 => gt_refclk1,
- -- Error Detection Interface
- frame_err => frame_err,
-
- -- Error Detection Interface
- hard_err => hard_err,
- soft_err => soft_err,
-
- -- Status
- channel_up => channel_up,
- lane_up => lane_up(0),
-
-
-
-
- -- System Interface
- user_clk => user_clk,
- sync_clk => sync_clk,
- reset => reset,
- sys_reset_out => sys_reset_out,
- power_down => power_down,
- loopback => loopback,
- gt_reset => gt_reset,
- tx_lock => tx_lock,
- init_clk_in => init_clk_in,
- pll_not_locked => pll_not_locked,
- tx_resetdone_out => tx_resetdone_out,
- rx_resetdone_out => rx_resetdone_out,
- link_reset_out => link_reset_out,
- drpclk_in => drpclk_in,
- drpaddr_in => drpaddr_in,
- drpen_in => drpen_in,
- drpdi_in => drpdi_in,
- drprdy_out => drprdy_out,
- drpdo_out => drpdo_out,
- drpwe_in => drpwe_in,
---------------------{
- gt_common_reset_out => gt_common_reset_out,
---____________________________COMMON PORTS_______________________________{
- gt0_pll0refclklost_in => gt0_pll0refclklost_in,
- quad1_common_lock_in => quad1_common_lock_in,
-------------------------- Channel - Ref Clock Ports ------------------------
- GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
- GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
- GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
- GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
---____________________________COMMON PORTS_______________________________}
---------------------}
- tx_out_clk => tx_out_clk
-
- );
-
- end STRUCTURE;
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xdc b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xdc
deleted file mode 100644
index 2ebf6847332392d64b7cb5b13cc1c8c615faafe9..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xdc
+++ /dev/null
@@ -1,67 +0,0 @@
-
-################################################################################
-##
-## (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-## south_channel.xdc generated for xc7z015-clg485-2 device
-# TXOUTCLK Constraint: Value is selected based on the line rate (5.0 Gbps) and lane width (4-Byte)
-create_clock -period 4.0 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt_wrapper_i*south_channel_multi_gt_i*gt0_south_channel_i*gtpe2_i*}]]
-
-
-#### CDC Path #####
-set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *south_channel_cdc_to*}]]
-
-
-####################### GT reference clock LOC (For use in top level design) #######################
-# set_property LOC V5 [get_ports GTPQ0_N]
-# set_property LOC U5 [get_ports GTPQ0_P]
-
-############################### GT LOC (For use in top level design) ###################################
-# set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells aurora_module_i/south_channel_i/U0/gt_wrapper_i/south_channel_multi_gt_i/gt0_south_channel_i/gtpe2_i]
-
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xml b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xml
deleted file mode 100644
index a41f943c3fade8dd5fcc83288786350877aa2b39..0000000000000000000000000000000000000000
--- a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xml
+++ /dev/null
@@ -1,41343 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>customized_ip</spirit:library>
- <spirit:name>south_channel</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>USER_DATA_S_AXI_TX</spirit:name>
- <spirit:displayName>USER_DATA_S_AXI_TX</spirit:displayName>
- <spirit:description>User data AXI-Stream TX interface</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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- <spirit:physicalPort>
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- </spirit:logicalPort>
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- <spirit:portMap>
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- <spirit:name>TREADY</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
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- <spirit:name>TVALID</spirit:name>
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- </spirit:portMap>
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- <spirit:name>TDATA_NUM_BYTES</spirit:name>
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- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.user_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>sync_clk</spirit:name>
- <spirit:displayName>sync_clk</spirit:displayName>
- <spirit:description>sync_clk frequency depends on line rate and user_clk should be shorted with sync_clk</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>sync_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sync_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>init_clk_out</spirit:name>
- <spirit:displayName>init_clk_out</spirit:displayName>
- <spirit:description>200 MHz independent system clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_BUSIF">gt_reset_out</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.init_clk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>sys_reset_out</spirit:name>
- <spirit:displayName>sys_reset_out</spirit:displayName>
- <spirit:description>system reset available when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>sys_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.SYS_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_reset</spirit:name>
- <spirit:displayName>gt_reset</spirit:displayName>
- <spirit:description>GT reset sampled in INIT_CLK and asserted for 6 clock cycles and after assertion of reset</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_reset_out</spirit:name>
- <spirit:displayName>gt_reset_out</spirit:displayName>
- <spirit:description>GT reset generated when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_reset_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>link_reset_out</spirit:name>
- <spirit:displayName>link_reset_out</spirit:displayName>
- <spirit:description>Link reset is generated when IP is not receiving valid data for longer time</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>link_reset_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.LINK_RESET_OUT.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.LINK_RESET_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.link_reset_out" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))!="TX-only_Simplex"">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>init_clk_in</spirit:name>
- <spirit:displayName>init_clk_in</spirit:displayName>
- <spirit:description>Free running System clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_BUSIF">gt_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.init_clk_in" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true)) or ((spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="kintexu") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="virtexu") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="zynquplus") or (spirit:decode(id('MODELPARAM_VALUE.C_FAMILY'))="kintexuplus")) or (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=true))">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk1_out</spirit:name>
- <spirit:displayName>gt_refclk1_out</spirit:displayName>
- <spirit:description>GT REFCLK1 when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk1_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk2_out</spirit:name>
- <spirit:displayName>gt_refclk2_out</spirit:displayName>
- <spirit:description>GT REFCLK2 when shared logic is in IP</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.FREQ_HZ">200000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk2_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None") and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk1</spirit:name>
- <spirit:displayName>~</spirit:displayName>
- <spirit:description>GT REFCLK1 when shared logic is in example design</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK1.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk1" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.c_gtwiz_out'))=false)) or (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=true))">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_refclk2</spirit:name>
- <spirit:displayName>~</spirit:displayName>
- <spirit:description>GT REFCLK2 when shared logic is in example design</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_BUSIF"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.GT_REFCLK2.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt_refclk2" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=false) and (spirit:decode(id('MODELPARAM_VALUE.c_gtwiz_out'))=false)) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None")) or ((spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None") and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=true)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>GT_DIFF_REFCLK1</spirit:name>
- <spirit:displayName>GT_DIFF_REFCLK1</spirit:displayName>
- <spirit:description>Differential GT REFCLK1 and depends on line rate</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk1_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GT_DIFF_REFCLK1" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>GT_DIFF_REFCLK2</spirit:name>
- <spirit:displayName>GT_DIFF_REFCLK2</spirit:displayName>
- <spirit:description>Differential GT REFCLK2 and depends on line rate</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt_refclk2_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DIFF_REFCLK2.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GT_DIFF_REFCLK2" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.C_GT_CLOCK_2'))!="None")) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_GTREFCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>INIT_DIFF_CLK</spirit:name>
- <spirit:displayName>INIT_DIFF_CLK</spirit:displayName>
- <spirit:description>200 MHz independent system clock</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:connectionRequired>true</spirit:connectionRequired>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>init_clk_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.ASSOCIATED_RESET">gt_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INIT_DIFF_CLK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INIT_DIFF_CLK" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.supportlevel'))=true) and (spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true) and (spirit:decode(id('MODELPARAM_VALUE.SINGLEEND_INITCLK'))=false))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rx_system_reset</spirit:name>
- <spirit:displayName>rx_system_reset</spirit:displayName>
- <spirit:description>Aurora IP reset for Simplex-RX config</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rx_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.RX_SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RX_SYSTEM_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.rx_system_reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))="RX-only_Simplex")">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>tx_system_reset</spirit:name>
- <spirit:displayName>tx_system_reset</spirit:displayName>
- <spirit:description>Aurora IP reset for Simplex-TX config</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>tx_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.tx_system_reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))="TX-only_Simplex")">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>gt_drp_clk_in</spirit:name>
- <spirit:displayName>gt_drp_clk_in</spirit:displayName>
- <spirit:description>DRP clock for 7-series transceiver</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>drpclk_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_BUSIF">GT0_DRP_IF:GT1_DRP_IF:GT2_DRP_IF:GT3_DRP_IF:GT4_DRP_IF:GT5_DRP_IF:GT6_DRP_IF:GT7_DRP_IF:GT8_DRP_IF:GT9_DRP_IF:GT10_DRP_IF:GT11_DRP_IF:GT12_DRP_IF:GT13_DRP_IF:GT14_DRP_IF:GT15_DRP_IF</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_RESET"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
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- <spirit:description>Transceiver debug interface for GT1</spirit:description>
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- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="transceiver_debug_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>cplllock</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_cplllock_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>dmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_dmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescandataerror</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_eyescandataerror_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescanreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_eyescanreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescantrigger</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_eyescantrigger_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxbufreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbyteisaligned</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxbyteisaligned_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxcdrhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxcdrovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcommadet</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxcommadet_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdfelpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxdfelpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdisperr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_disp_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmen</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmen_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmhfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmhfovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmlfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmlfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxlpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorsel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxmonitorsel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxnotintable</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_not_in_table_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpcsreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxpcsreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmareset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxpmareset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmaresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxpmaresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbscntreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxprbscntreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbserr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxprbserr_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbssel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxprbssel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxrealign</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rx_realign_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_rxresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_tx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispmode</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txchardispmode_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispval</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txchardispval_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txdiffctrl</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txdiffctrl_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txinhibit</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txinhibit_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txmaincursor</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txmaincursor_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpcsreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpcsreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpmareset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpmareset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpolarity</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpolarity_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txpostcursor</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txpostcursor_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txprbsforceerr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txprbsforceerr_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txprbssel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txprbssel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txprecursor</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txprecursor_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt1_txresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.TRANSCEIVER_DEBUG1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.is_7series'))=true) and (spirit:decode(id('MODELPARAM_VALUE.TransceiverControl'))=true) and ((spirit:decode(id('MODELPARAM_VALUE.C_AURORA_LANES')))>1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>TRANSCEIVER_DEBUG2</spirit:name>
- <spirit:displayName>TRANSCEIVER_DEBUG2</spirit:displayName>
- <spirit:description>Transceiver debug interface for gt2</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="transceiver_debug" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="transceiver_debug_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>cplllock</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_cplllock_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>dmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_dmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescandataerror</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_eyescandataerror_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescanreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_eyescanreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>eyescantrigger</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_eyescantrigger_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxbufreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxbyteisaligned</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxbyteisaligned_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxcdrhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcdrovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxcdrovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxcommadet</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxcommadet_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdfelpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxdfelpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxdisperr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_disp_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmen</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmen_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmhfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmhfovrden</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmhfovrden_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmlfhold</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmlfhold_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxlpmreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxlpmreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorout</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxmonitorout_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxmonitorsel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxmonitorsel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxnotintable</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_not_in_table_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpcsreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxpcsreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmareset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxpmareset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxpmaresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxpmaresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbscntreset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxprbscntreset_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbserr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxprbserr_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxprbssel</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxprbssel_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxrealign</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rx_realign_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rxresetdone</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_rxresetdone_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbuferr</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_tx_buf_err_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txbufstatus</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txbufstatus_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispmode</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txchardispmode_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txchardispval</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txchardispval_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>txdiffctrl</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>gt2_txdiffctrl_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
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- <spirit:name>rxnotintable</spirit:name>
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- <spirit:name>rxprbscntreset</spirit:name>
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- <spirit:name>rxprbssel</spirit:name>
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- <spirit:name>gt15_rxprbssel_in</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>rxrealign</spirit:name>
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- <spirit:name>gt15_rx_realign_out</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>rxresetdone</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txbuferr</spirit:name>
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- <spirit:name>gt15_tx_buf_err_out</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txbufstatus</spirit:name>
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- <spirit:name>gt15_txbufstatus_out</spirit:name>
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- <spirit:name>txchardispmode</spirit:name>
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- <spirit:name>txchardispval</spirit:name>
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- <spirit:name>gt15_txchardispval_in</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txdiffctrl</spirit:name>
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- <spirit:name>txinhibit</spirit:name>
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- <spirit:name>gt15_txinhibit_in</spirit:name>
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- <spirit:name>txmaincursor</spirit:name>
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- <spirit:name>txpcsreset</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>txpmareset</spirit:name>
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- <spirit:name>txpolarity</spirit:name>
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- <spirit:name>txprbsforceerr</spirit:name>
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- <spirit:name>txprbssel</spirit:name>
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- <spirit:name>txresetdone</spirit:name>
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- <spirit:name>gt15_txresetdone_out</spirit:name>
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- <spirit:name>RX_SIDEBAND_SIGNALS</spirit:name>
- <spirit:displayName>RX_SIDEBAND_SIGNALS</spirit:displayName>
- <spirit:description>RX SIDEBAND Signals must be connected with TX_SIDEBAND_SIGNALS</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="SIDEBAND_Pins_RX" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_aurora" spirit:name="SIDEBAND_Pins_RX_rtl" spirit:version="1.0"/>
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- <spirit:name>rx_aligned</spirit:name>
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- <spirit:name>rx_reset</spirit:name>
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- <spirit:name>rx_verify</spirit:name>
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- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RX_SIDEBAND_SIGNALS" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))!="Duplex") and (spirit:decode(id('MODELPARAM_VALUE.DATAFLOW_CONFIG'))!="TX-only_Simplex") and (spirit:decode(id('MODELPARAM_VALUE.BACKCHANNEL_MODE'))!="Timer"))">false</xilinx:isEnabled>
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- <spirit:name>CORE_STATUS</spirit:name>
- <spirit:displayName>CORE_STATUS</spirit:displayName>
- <spirit:description>Aurora Core Status pins</spirit:description>
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