diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
index b1a1c83624387435bf2b3b46082270598d9debaa..1068ab2a6be553239e13976af5025c693dc5cffa 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
+++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
index 9f07492179e8492b096e8488be75017d8ec0a523..a0d98af4916c3a24de11b525d0d48de2a93f679f 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+
diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index 01d1e1e4dfd76424dc36e9d7b12a1a68b5c97e96..eb1348ff850ae7598c60e113cc31fb55cd6337fe 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
--- Last update: 2021-01-11
+-- Last update: 2021-05-05
--
---------------------------------------------------------------------------------
@@ -517,44 +517,54 @@ architecture arch of scalp_firmware is
signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
- -- North
- -- East
- -- attribute mark_debug of EastRXM2SxD : signal is "true";
- -- attribute keep of EastRXM2SxD : signal is "true";
- -- attribute mark_debug of EastRXS2MxD : signal is "true";
- -- attribute keep of EastRXS2MxD : signal is "true";
- -- attribute mark_debug of EastTXM2SxD : signal is "true";
- -- attribute keep of EastTXM2SxD : signal is "true";
- -- attribute mark_debug of EastTXS2MxD : signal is "true";
- -- attribute keep of EastTXS2MxD : signal is "true";
- -- South
- -- West
- -- attribute mark_debug of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
- -- attribute mark_debug of WestRXS2MxD : signal is "true";
- -- attribute keep of WestRXS2MxD : signal is "true";
- -- attribute mark_debug of WestTXM2SxD : signal is "true";
- -- attribute keep of WestTXM2SxD : signal is "true";
- -- attribute mark_debug of WestTXS2MxD : signal is "true";
- -- attribute keep of WestTXS2MxD : signal is "true";
- -- attribute mark_debug of ScalpRouterReadyxD : signal is "true";
- -- attribute keep of ScalpRouterReadyxD : signal is "true";
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
+ -- Scalp Router
-- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
-- attribute keep of RXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
-- attribute keep of RXAxiss2mVectorxD : signal is "true";
- -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
- -- attribute keep of TXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
-- attribute keep of TXAxiss2mVectorxD : signal is "true";
+ -- Scalp Aurora PHY Ready -> TX Side
+ attribute mark_debug of NorthTXM2SxD : signal is "true";
+ attribute keep of NorthTXM2SxD : signal is "true";
+ attribute mark_debug of NorthTXS2MxD : signal is "true";
+ attribute keep of NorthTXS2MxD : signal is "true";
+ attribute mark_debug of EastTXM2SxD : signal is "true";
+ attribute keep of EastTXM2SxD : signal is "true";
+ attribute mark_debug of EastTXS2MxD : signal is "true";
+ attribute keep of EastTXS2MxD : signal is "true";
+ attribute mark_debug of SouthTXM2SxD : signal is "true";
+ attribute keep of SouthTXM2SxD : signal is "true";
+ attribute mark_debug of SouthTXS2MxD : signal is "true";
+ attribute keep of SouthTXS2MxD : signal is "true";
+ attribute mark_debug of WestTXM2SxD : signal is "true";
+ attribute keep of WestTXM2SxD : signal is "true";
+ attribute mark_debug of WestTXS2MxD : signal is "true";
+ attribute keep of WestTXS2MxD : signal is "true";
+ attribute mark_debug of NorthRXM2SxD : signal is "true";
+ attribute keep of NorthRXM2SxD : signal is "true";
+ attribute mark_debug of NorthRXS2MxD : signal is "true";
+ attribute keep of NorthRXS2MxD : signal is "true";
+ attribute mark_debug of EastRXM2SxD : signal is "true";
+ attribute keep of EastRXM2SxD : signal is "true";
+ attribute mark_debug of EastRXS2MxD : signal is "true";
+ attribute keep of EastRXS2MxD : signal is "true";
+ attribute mark_debug of SouthRXM2SxD : signal is "true";
+ attribute keep of SouthRXM2SxD : signal is "true";
+ attribute mark_debug of SouthRXS2MxD : signal is "true";
+ attribute keep of SouthRXS2MxD : signal is "true";
+ attribute mark_debug of WestRXM2SxD : signal is "true";
+ attribute keep of WestRXM2SxD : signal is "true";
+ attribute mark_debug of WestRXS2MxD : signal is "true";
+ attribute keep of WestRXS2MxD : signal is "true";
begin
@@ -896,12 +906,19 @@ begin
signal ScalpPacket0xD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
(SpHeaderxD => C_SP_HEADER_110_TO_210,
SpPayloadxD => C_SP_PAYLOAD_0);
- signal ScalpPacketValid12xS : std_ulogic := '0';
+ signal ScalpPacketValid12xS : std_ulogic := '0';
--
- signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
- signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
- signal VioWrSpValidxS : std_ulogic := '0';
-
+ signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
+ signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
+ signal VioWrSpValidxS : std_ulogic := '0';
+ -- Scalp Packet
+ attribute mark_debug of ScalpPacket0xD : signal is "true";
+ attribute keep of ScalpPacket0xD : signal is "true";
+ attribute mark_debug of ScalpPacketValid12xS : signal is "true";
+ attribute keep of ScalpPacketValid12xS : signal is "true";
+ -- VIO
+ -- attribute mark_debug of VioWrSpValidxS : signal is "true";
+ -- attribute keep of VioWrSpValidxS : signal is "true";
-- attribute mark_debug of ScalpRouterResetxRNA : signal is "true";
-- attribute keep of ScalpRouterResetxRNA : signal is "true";
-- attribute mark_debug of ScalpPacket0xD : signal is "true";
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router.vhd b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
index 65a192ee3a71c6aae4619aab635df27a643ee0e7..76ff8f2fb0f6e2e727b0132350392e143a2fb412 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router (NoC).
--
--- Last update: 2020-12-21
+-- Last update: 2021-05-04
--
---------------------------------------------------------------------------------
library ieee;
@@ -117,19 +117,19 @@ architecture rtl of scalp_router is
-- Signals
-- Scalp Router
-- Local Router Network Address
- signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
-- Axi4 Stream Interfaces
- signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
- signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
-- Scalp QoS Vectors
- signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
-- Axi4 Stream Cross-Links with Neighborhood
- signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
- signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
---------------------------------------------------------------------------
-- For Simulation With Vivado Only
-- Axi4 Stream Cross-Links with Neighborhood
@@ -139,15 +139,17 @@ architecture rtl of scalp_router is
-- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_SIM_AXISS2M_VECTOR);
---------------------------------------------------------------------------
-- Scalp Booking Vectors
- signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
-- Scalp Scheduler Ack Vectors
- signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
+ -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of TXAxiss2mVectorxD : signal is "true";
-- attribute mark_debug of LocNetAddrxD : signal is "true";
-- attribute keep of LocNetAddrxD : signal is "true";
-- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
index 29aad8cabbc85c7615978a3947cbd3046ab16b87..f6c853da21f16738e1f53db2d977c3da44724786 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Interface.
--
--- Last update: 2020-11-30
+-- Last update: 2021-05-04
--
---------------------------------------------------------------------------------
library ieee;
@@ -216,6 +216,23 @@ architecture rtl of scalp_router_interface is
signal DTXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
signal DTXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
+ -- attribute keep of TXAxi4S2MLinkxD : signal is "true";
+ -- attribute mark_debug of TXAxi4s2mLinksxD : signal is "true";
+ -- attribute keep of TXAxi4s2mLinksxD : signal is "true";
+ -- attribute mark_debug of TXAxi4s2mIfxD : signal is "true";
+ -- attribute keep of TXAxi4s2mIfxD : signal is "true";
+ -- attribute mark_debug of RXAxi4s2mIfxD : signal is "true";
+ -- attribute keep of RXAxi4s2mIfxD : signal is "true";
+ -- attribute mark_debug of TXAxi4s2mLinksxD : signal is "true";
+ -- attribute keep of TXAxi4s2mLinksxD : signal is "true";
+ -- attribute mark_debug of RXAxi4s2mLinksxD : signal is "true";
+ -- attribute keep of RXAxi4s2mLinksxD : signal is "true";
+
begin -- architecture rtl
EntityIOxB : block is
diff --git a/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
index b17fa25219edb849005208c5cd11aa7c1e7d06a7..d65087d6dd4e8a8afa1edd6b922e3e29eac789d9 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp RX side state machine.
--
--- Last update: 2020-11-30
+-- Last update: 2021-05-05
--
---------------------------------------------------------------------------------
library ieee;
@@ -115,6 +115,37 @@ architecture behavioral of scalp_rx_side is
signal ReadyOutxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EnPopNPushxS : std_ulogic := '0';
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
+ attribute keep of TXAxi4S2MLinkxD : signal is "true";
+ attribute mark_debug of RXSideStatexDP : signal is "true";
+ attribute keep of RXSideStatexDP : signal is "true";
+ attribute mark_debug of RXSideStatexDN : signal is "true";
+ attribute keep of RXSideStatexDN : signal is "true";
+ attribute mark_debug of ReadyInxD : signal is "true";
+ attribute keep of ReadyInxD : signal is "true";
+ attribute mark_debug of ReadyOutxD : signal is "true";
+ attribute keep of ReadyOutxD : signal is "true";
+ attribute mark_debug of ArbitratexS : signal is "true";
+ attribute keep of ArbitratexS : signal is "true";
+ attribute mark_debug of RequestVectorxDP : signal is "true";
+ attribute keep of RequestVectorxDP : signal is "true";
+ attribute mark_debug of ArbitratedxS : signal is "true";
+ attribute keep of ArbitratedxS : signal is "true";
+ attribute mark_debug of GrantIndexxD : signal is "true";
+ attribute keep of GrantIndexxD : signal is "true";
+ attribute mark_debug of RequestVectorxDN : signal is "true";
+ attribute keep of RequestVectorxDN : signal is "true";
+ attribute mark_debug of SchedulerAckxD : signal is "true";
+ attribute keep of SchedulerAckxD : signal is "true";
+ attribute mark_debug of RXAxi4S2MLinkxD : signal is "true";
+ attribute keep of RXAxi4S2MLinkxD : signal is "true";
+ attribute mark_debug of RXAxi4M2SLinkxD : signal is "true";
+ attribute keep of RXAxi4M2SLinkxD : signal is "true";
+
begin -- architecture behavioral
-- Asynchronous Statements
diff --git a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
index 18e87957c82f1a54cfefcc9436a30d27a524123c..a2a2f373a7340072b6a15b3ac9fca507a84c6b58 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp TX side state machine.
--
--- Last update: 2020-11-30
+-- Last update: 2021-05-04
--
---------------------------------------------------------------------------------
library ieee;
@@ -90,6 +90,16 @@ architecture behavioral of scalp_tx_side is
signal ReadyInxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EnPopNPushxS : std_ulogic := '0';
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of TXSideStatexDP : signal is "true";
+ -- attribute keep of TXSideStatexDP : signal is "true";
+ -- attribute mark_debug of TXSideStatexDN : signal is "true";
+ -- attribute keep of TXSideStatexDN : signal is "true";
+ -- attribute mark_debug of ReadyInxD : signal is "true";
+ -- attribute keep of ReadyInxD : signal is "true";
+
begin -- architecture behavioral
-- Asynchronous Statements
diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
index ba0f4dbe83261e7c93f84a5b84369eee256acfb4..3ad3db1856c3e25bc35a308ce9c64856cea7ad3f 100644
--- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
--- Last update: 2021-03-22
+-- Last update: 2021-05-03
--
---------------------------------------------------------------------------------
@@ -66,8 +66,7 @@ entity scalp_zynqps_wrapper is
RdValidxSO : out std_logic;
WrAddrxDO : out std_logic_vector (11 downto 0);
WrDataxDO : out std_logic_vector (31 downto 0);
- WrValidxSO : out std_logic;
- RgbLedsCtrlPortxDO : out std_logic_vector (31 downto 0));
+ WrValidxSO : out std_logic);
end scalp_zynqps_wrapper;
@@ -110,7 +109,6 @@ begin
RdValidxSO => RdValidxSO,
WrAddrxDO => WrAddrxDO,
WrDataxDO => WrDataxDO,
- WrValidxSO => WrValidxSO,
- RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO);
+ WrValidxSO => WrValidxSO);
end arch;