From 0e87bdf04b803239080a5e8e0a0e7a755ed1535b Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Tue, 22 Sep 2020 08:44:51 +0200
Subject: [PATCH] Creation and initial tracking of scripts for the
scalp_aurora_phy IPS.
---
.../src/hdl/scalp_aurora_phy.vhd | 34 ++++
.../src/sim/tb_scalp_aurora_phy.vhd | 34 ++++
.../2019.2/lin64/.scripts/.prompt_colors.tcl | 37 ++++
.../.scripts/clean_prj_scalp_aurora_phy.sh | 40 ++++
.../.scripts/create_prj_scalp_aurora_phy.sh | 27 +++
.../.scripts/create_prj_scalp_aurora_phy.tcl | 189 ++++++++++++++++++
.../.scripts/open_prj_scalp_aurora_phy.sh | 25 +++
.../2019.2/lin64/.scripts/utils.tcl | 62 ++++++
.../scalp_aurora_phy/2019.2/lin64/setup.sh | 30 +++
.../src/ipi_tcl/scalp_aurora_phy_ipi.tcl | 0
10 files changed, 478 insertions(+)
create mode 100644 ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
create mode 100644 ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd
create mode 100644 ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/.prompt_colors.tcl
create mode 100755 ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
create mode 100755 ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
create mode 100644 ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
create mode 100755 ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
create mode 100644 ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/utils.tcl
create mode 100755 ips/vivado/scalp_aurora_phy/2019.2/lin64/setup.sh
create mode 100644 ips/vivado/scalp_aurora_phy/2019.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
new file mode 100644
index 0000000..98b067e
--- /dev/null
+++ b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_aurora_phy - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: scalp_aurora_phy
+--
+-- Last update: 2020-09-22 08:43:22
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scalp_aurora_phy is
+end scalp_aurora_phy;
+
+
+architecture arch of scalp_aurora_phy is
+
+begin
+
+end arch;
diff --git a/ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd b/ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd
new file mode 100644
index 0000000..0a9b075
--- /dev/null
+++ b/ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: tb_scalp_aurora_phy - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: Testbench for scalp_aurora_phy
+--
+-- Last update: 2020-09-22 08:43:22
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_aurora_phy is
+end tb_scalp_aurora_phy;
+
+
+architecture behavioral of tb_scalp_aurora_phy is
+
+begin
+
+end behavioral;
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000..a8e8cca
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,37 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_aurora_phy
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Console color print utility
+#
+# Last update: 2020-09-22 08:43:22
+#
+##################################################################################
+
+# Text attributes
+set RESET [exec tput sgr0]
+set BOLD [exec tput bold]
+set ITALIC [exec tput sitm]
+set BLINK [exec tput blink]
+set HIGHL [exec tput smso]
+
+# Text colors
+set RED [exec tput setaf 1]
+set GREEN [exec tput setaf 2]
+set YELLOW [exec tput setaf 3]
+set BLUE [exec tput setaf 4]
+set MAGENTA [exec tput setaf 5]
+set CYAN [exec tput setaf 6]
+set WHITE [exec tput setaf 7]
+
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
new file mode 100755
index 0000000..bf586dd
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_aurora_phy
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Cleanup project directory
+#
+# Last update: 2020-09-22 08:43:22
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_aurora_phy/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
new file mode 100755
index 0000000..eff4145
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_aurora_phy
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-22 08:43:22
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_aurora_phy.tcl -notrace
+echo "> Done"
+
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
new file mode 100644
index 0000000..058db4e
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
@@ -0,0 +1,189 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_aurora_phy
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script for re-creating Vivado project 'scalp_aurora_phy'
+#
+# Last update: 2020-09-22 08:43:22
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_aurora_phy"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part SCALP [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add HDL sources
+ set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add the constraints file (XDC)
+<find_constr_file>
+ #add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ # add IPs source file
+ #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ # add the project component
+ set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+ set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
+ # add IPs source file
+ #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+ set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
+# Add packages sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+}
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
new file mode 100755
index 0000000..7a56015
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_aurora_phy
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-22 08:43:22
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_aurora_phy/scalp_aurora_phy.xpr
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000..50fe065
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_aurora_phy
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2020-09-22 08:43:22
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/setup.sh b/ips/vivado/scalp_aurora_phy/2019.2/lin64/setup.sh
new file mode 100755
index 0000000..416a953
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy/2019.2/lin64/setup.sh
@@ -0,0 +1,30 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_aurora_phy
+# Target Device: SCALP xc7z015clg485-2
+# Tool version: 2019.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2020-09-22 08:43:22
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_aurora_phy.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_aurora_phy.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_aurora_phy.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_aurora_phy.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_aurora_phy.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_aurora_phy.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_scalp_aurora_phy.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_aurora_phy.sh && cd ..'
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl b/ips/vivado/scalp_aurora_phy/2019.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl
new file mode 100644
index 0000000..e69de29
--
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