From 183400d8abca53497fc56fed917a52d6e648c73c Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Wed, 27 Oct 2021 08:13:44 +0200
Subject: [PATCH] Updated scalp_fast_router_firmware. Support DMA sync between
two scalp_board.
---
.../src/hdl/scalp_fast_router_firmware.vhd | 313 +++++++++++++-----
.../scalp_fast_router_registers/component.xml | 217 +++++++++++-
.../src/hdl/scalp_fast_router_registers.vhd | 134 +++++---
.../xgui/scalp_fast_router_registers_v1_4.tcl | 145 ++++++++
.../xgui/scalp_fast_router_registers_v1_5.tcl | 145 ++++++++
ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd | 12 +-
.../src/hdl/scalp_router_core.vhd | 26 +-
.../src/hdl/scalp_router_interface.vhd | 15 +-
.../src/hdl/scalp_zynqps_wrapper.vhd | 104 +++---
.../2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl | 8 +-
10 files changed, 926 insertions(+), 193 deletions(-)
create mode 100644 ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_4.tcl
create mode 100644 ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_5.tcl
diff --git a/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd b/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
index 3f8147f..cc0a285 100644
--- a/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
+++ b/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_fast_router_firmware
--
--- Last update: 2021-10-22
+-- Last update: 2021-10-26
--
---------------------------------------------------------------------------------
@@ -465,6 +465,8 @@ architecture arch of scalp_fast_router_firmware is
signal RGBLed0xD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RGBLed1xD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal QoSPhyStatusxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal QoSDMAInitOcpCtrlxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal QoSDMAInitStatusxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal DMARXm2sxD : t_axi4m2s := C_NO_AXI4_M2S;
signal DMARXs2mxD : t_axi4s2m := C_NO_AXI4_S2M;
signal DMATXm2sxD : t_axi4m2s := C_NO_AXI4_M2S;
@@ -485,10 +487,65 @@ architecture arch of scalp_fast_router_firmware is
attribute keep of AuroraClkSlavexC : signal is "true";
attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
- -- attribute mark_debug of QoSVectorPhyStatusxD : signal is "true";
- -- attribute keep of QoSVectorPhyStatusxD : signal is "true";
- -- attribute mark_debug of QoSPhyStatusxD : signal is "true";
- -- attribute keep of QoSPhyStatusxD : signal is "true";
+ attribute mark_debug of QoSDMAInitOcpCtrlxD : signal is "true";
+ attribute keep of QoSDMAInitOcpCtrlxD : signal is "true";
+ attribute mark_debug of QoSDMAInitStatusxD : signal is "true";
+ attribute keep of QoSDMAInitStatusxD : signal is "true";
+ attribute mark_debug of QoSPhyStatusxD : signal is "true";
+ attribute keep of QoSPhyStatusxD : signal is "true";
+ attribute mark_debug of LocalNetAddrxD : signal is "true";
+ attribute keep of LocalNetAddrxD : signal is "true";
+ attribute mark_debug of QoSVectorPhyStatusxD : signal is "true";
+ attribute keep of QoSVectorPhyStatusxD : signal is "true";
+ -- UFC
+ -- East
+ attribute mark_debug of EastTXM2SxD : signal is "true";
+ attribute keep of EastTXM2SxD : signal is "true";
+ attribute mark_debug of EastTXS2MxD : signal is "true";
+ attribute keep of EastTXS2MxD : signal is "true";
+ attribute mark_debug of EastRXM2SxD : signal is "true";
+ attribute keep of EastRXM2SxD : signal is "true";
+ attribute mark_debug of EastRXS2MxD : signal is "true";
+ attribute keep of EastRXS2MxD : signal is "true";
+ attribute mark_debug of EastTXUFCM2SxD : signal is "true";
+ attribute keep of EastTXUFCM2SxD : signal is "true";
+ attribute mark_debug of EastTXUFCS2MxD : signal is "true";
+ attribute keep of EastTXNFCS2MxD : signal is "true";
+ attribute mark_debug of EastRXUFCM2SxD : signal is "true";
+ attribute keep of EastRXUFCM2SxD : signal is "true";
+ -- West
+ attribute mark_debug of WestTXM2SxD : signal is "true";
+ attribute keep of WestTXM2SxD : signal is "true";
+ attribute mark_debug of WestTXS2MxD : signal is "true";
+ attribute keep of WestTXS2MxD : signal is "true";
+ attribute mark_debug of WestRXM2SxD : signal is "true";
+ attribute keep of WestRXM2SxD : signal is "true";
+ attribute mark_debug of WestRXS2MxD : signal is "true";
+ attribute keep of WestRXS2MxD : signal is "true";
+ attribute mark_debug of WestTXUFCM2SxD : signal is "true";
+ attribute keep of WestTXUFCM2SxD : signal is "true";
+ attribute mark_debug of WestTXUFCS2MxD : signal is "true";
+ attribute keep of WestTXNFCS2MxD : signal is "true";
+ attribute mark_debug of WestRXUFCM2SxD : signal is "true";
+ attribute keep of WestRXUFCM2SxD : signal is "true";
+ -- Local
+ attribute mark_debug of TXAxism2sVectorxD : signal is "true";
+ attribute keep of TXAxism2sVectorxD : signal is "true";
+ attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+ attribute keep of TXAxiss2mVectorxD : signal is "true";
+ attribute mark_debug of RXAxism2sVectorxD : signal is "true";
+ attribute keep of RXAxism2sVectorxD : signal is "true";
+ attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
+ attribute keep of RXAxiss2mVectorxD : signal is "true";
+ -- DMA
+ attribute mark_debug of DMATXm2sxD : signal is "true";
+ attribute keep of DMATXm2sxD : signal is "true";
+ attribute mark_debug of DMATXs2mxD : signal is "true";
+ attribute keep of DMATXs2mxD : signal is "true";
+ attribute mark_debug of DMARXm2sxD : signal is "true";
+ attribute keep of DMARXm2sxD : signal is "true";
+ attribute mark_debug of DMARXs2mxD : signal is "true";
+ attribute keep of DMARXs2mxD : signal is "true";
begin
@@ -498,67 +555,69 @@ begin
ZynqxI : entity work.scalp_zynqps_wrapper
port map (
-- Processor interface
- FIXED_IO_ps_clk => PSClkxCIO,
- FIXED_IO_ps_porb => PSPorxSNIO,
- FIXED_IO_ps_srstb => PSSRstxRNIO,
- FclkClk0xCO => PSSysClkxC,
- FclkReset0xRO => PSSysResetxR,
+ FIXED_IO_ps_clk => PSClkxCIO,
+ FIXED_IO_ps_porb => PSPorxSNIO,
+ FIXED_IO_ps_srstb => PSSRstxRNIO,
+ FclkClk0xCO => PSSysClkxC,
+ FclkReset0xRO => PSSysResetxR,
-- DDR interface
- DDR_addr => DDRAddrxDIO,
- DDR_ba => DDRBankAddrxDIO,
- DDR_cas_n => DDRCasNxSIO,
- DDR_ck_n => DDRClkNxCIO,
- DDR_ck_p => DDRClkPxCIO,
- DDR_cke => DDRCkexSIO,
- DDR_cs_n => DDRCsNxSIO,
- DDR_dm => DDRDmxDIO,
- DDR_dq => DDRDqxDIO,
- DDR_dqs_n => DDRDqsNxDIO,
- DDR_dqs_p => DDRDqsPxDIO,
- DDR_odt => DDROdtxSIO,
- DDR_ras_n => DDRRasNxSIO,
- DDR_reset_n => DDRDRstxRNIO,
- DDR_we_n => DDRWexSNIO,
- FIXED_IO_ddr_vrn => DDRVrNxSIO,
- FIXED_IO_ddr_vrp => DDRVrPxSIO,
+ DDR_addr => DDRAddrxDIO,
+ DDR_ba => DDRBankAddrxDIO,
+ DDR_cas_n => DDRCasNxSIO,
+ DDR_ck_n => DDRClkNxCIO,
+ DDR_ck_p => DDRClkPxCIO,
+ DDR_cke => DDRCkexSIO,
+ DDR_cs_n => DDRCsNxSIO,
+ DDR_dm => DDRDmxDIO,
+ DDR_dq => DDRDqxDIO,
+ DDR_dqs_n => DDRDqsNxDIO,
+ DDR_dqs_p => DDRDqsPxDIO,
+ DDR_odt => DDROdtxSIO,
+ DDR_ras_n => DDRRasNxSIO,
+ DDR_reset_n => DDRDRstxRNIO,
+ DDR_we_n => DDRWexSNIO,
+ FIXED_IO_ddr_vrn => DDRVrNxSIO,
+ FIXED_IO_ddr_vrp => DDRVrPxSIO,
-- USB interface
- Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
+ Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
-- SPI1 used as uWire master. Clk, Data and LE signals are outputs
-- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
- Spi1MOSIxSO => Pll2V5DatauWirexSO,
- Spi1SSxSO => Pll2V5LEuWirexSO,
- Spi1SclkxCO => Pll2V5ClkuWirexCO,
+ Spi1MOSIxSO => Pll2V5DatauWirexSO,
+ Spi1SSxSO => Pll2V5LEuWirexSO,
+ Spi1SclkxCO => Pll2V5ClkuWirexCO,
-- MIO
- FIXED_IO_mio => MIOxDIO,
- UserClkxCI => AuroraClkMasterxC.UserClkxC,
- UserResetxRANI => ScalpRouterResetxRNA,
+ FIXED_IO_mio => MIOxDIO,
+ UserClkxCI => AuroraClkMasterxC.UserClkxC,
+ UserResetxRANI => ScalpRouterResetxRNA,
-- Scalp Fast Router Registers
- LocalNetAddrxDO => LocalNetAddrxD,
- RGBLed0xDO => RGBLed0xD,
- RGBLed1xDO => RGBLed1xD,
- QoSPhyStatusxDI => QoSPhyStatusxD,
+ LocalNetAddrxDO => LocalNetAddrxD,
+ RGBLed0xDO => RGBLed0xD,
+ RGBLed1xDO => RGBLed1xD,
+ QoSPhyStatusxDI => QoSPhyStatusxD,
+ QoSDMAInitOcpCtrlxDO => QoSDMAInitOcpCtrlxD,
+ QoSDMAInitStatusxDI => QoSDMAInitStatusxD,
-- RX
- DMARXm2sxDI => DMARXm2sxD,
- DMARXs2mxDO => DMARXs2mxD,
+ DMARXm2sxDI => DMARXm2sxD,
+ DMARXs2mxDO => DMARXs2mxD,
-- TX
- DMATXm2sxDO => DMATXm2sxD,
- DMATXs2mxDI => DMATXs2mxD,
+ DMATXm2sxDO => DMATXm2sxD,
+ DMATXs2mxDI => DMATXs2mxD,
-- Debug Phy
-- West Phy
- WestRXM2SxDI => WestRXM2SxD,
- WestRXS2MxDI => WestRXS2MxD,
- WestTXM2SxDI => WestTXM2SxD,
- WestTXS2MxDI => WestTXS2MxD,
+ WestRXM2SxDI => C_NO_AXI4_M2S,
+ WestRXS2MxDI => C_NO_AXI4_S2M,
+ WestTXM2SxDI => C_NO_AXI4_M2S,
+ WestTXS2MxDI => C_NO_AXI4_S2M,
-- East Phy
- EastRXM2SxDI => EastRXM2SxD,
- EastRXS2MxDI => EastRXS2MxD,
- EastTXM2SxDI => EastTXM2SxD,
- EastTXS2MxDI => EastTXS2MxD,
+ EastRXM2SxDI => C_NO_AXI4_M2S,
+ EastRXS2MxDI => C_NO_AXI4_S2M,
+ EastTXM2SxDI => C_NO_AXI4_M2S,
+ EastTXS2MxDI => C_NO_AXI4_S2M,
-- Local NoC
- LocalRXM2SxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
- LocalRXS2MxDI => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
- LocalTXM2SxDI => RXAxism2sVectorxD(C_LOCAL_IF_ID),
- LocalTXS2MxDI => RXAxiss2mVectorxD(C_LOCAL_IF_ID));
+ LocalRXM2SxDI => C_NO_AXI4_M2S, -- TXAxism2sVectorxD(C_LOCAL_IF_ID),
+ LocalRXS2MxDI => C_NO_AXI4_S2M, -- TXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ LocalTXM2SxDI => C_NO_AXI4_M2S, -- RXAxism2sVectorxD(C_LOCAL_IF_ID),
+ LocalTXS2MxDI => C_NO_AXI4_S2M); -- RXAxiss2mVectorxD(C_LOCAL_IF_ID));
end block ProcessingSystemxB;
@@ -964,26 +1023,6 @@ begin
LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocalNetAddrxD(15 downto 8)));
LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocalNetAddrxD(23 downto 16)));
- -- TX Side
- NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
- EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID);
- SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID);
- WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID);
- NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD;
- EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
- SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
- WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
-
- -- RX Side
- NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
- EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
- SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
- WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD;
- NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID);
- EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID);
- SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
- WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
-
ScalpDMALoopBackxG : if C_SCALP_DMA_LOOPBACK = true generate
DMA2DMAm2sxAS : DMARXm2sxD <= DMATXm2sxD;
@@ -1005,6 +1044,132 @@ begin
end generate ScalpDMALoopBackxG;
+ QoSUFCxB : block is
+
+ signal NorthTXUFCDataM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXUFCDataM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXUFCDataM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXUFCDataM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+
+ constant DMA_INIT_DATA_SIZE : std_ulogic_vector((C_AXI4_UFC_TX_DATA_SIZE - 1) downto 0) := "001";
+ constant DMA_INIT_MAGIC_WORD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"aa55bb44";
+
+ begin -- block QoSUFCxB
+
+ -- TX Side
+ NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID) when NorthTXS2MxD.ReadyxS = '1' else NorthTXUFCDataM2SxD;
+ EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID) when EastTXS2MxD.ReadyxS = '1' else EastTXUFCDataM2SxD;
+ SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID) when SouthTXS2MxD.ReadyxS = '1' else SouthTXUFCDataM2SxD;
+ WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID) when WestTXS2MxD.ReadyxS = '1' else WestTXUFCDataM2SxD;
+ NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD;
+ EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
+ SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
+ WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
+
+ NorthTXDataForUFCM2SxAS : NorthTXUFCDataM2SxD.DataxD <= DMA_INIT_MAGIC_WORD when NorthTXS2MxD.ReadyxS = '0' else (others => '0');
+ EastTXDataForUFCM2SxAS : EastTXUFCDataM2SxD.DataxD <= DMA_INIT_MAGIC_WORD when EastTXS2MxD.ReadyxS = '0' else (others => '0');
+ SouthTXDataForUFCM2SxAS : SouthTXUFCDataM2SxD.DataxD <= DMA_INIT_MAGIC_WORD when SouthTXS2MxD.ReadyxS = '0' else (others => '0');
+ WestTXDataForUFCM2SxAS : WestTXUFCDataM2SxD.DataxD <= DMA_INIT_MAGIC_WORD when WestTXS2MxD.ReadyxS = '0' else (others => '0');
+
+ UFCTXValidxP : process (AuroraClkMasterxC.UserClkxC,
+ ScalpRouterResetxRNA) is
+ begin -- process UFCTXValidxP
+ if ScalpRouterResetxRNA = '0' then
+ NorthTXUFCM2SxD <= C_NO_AXI4_UFC_M2S_TX;
+ EastTXUFCM2SxD <= C_NO_AXI4_UFC_M2S_TX;
+ SouthTXUFCM2SxD <= C_NO_AXI4_UFC_M2S_TX;
+ WestTXUFCM2SxD <= C_NO_AXI4_UFC_M2S_TX;
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ NorthTXUFCM2SxD <= NorthTXUFCM2SxD;
+ EastTXUFCM2SxD <= EastTXUFCM2SxD;
+ SouthTXUFCM2SxD <= SouthTXUFCM2SxD;
+ WestTXUFCM2SxD <= WestTXUFCM2SxD;
+
+ -- UFC is valid
+ -- North
+ if QoSDMAInitOcpCtrlxD(C_NORTH_IF_ID) = '1' then
+ NorthTXUFCM2SxD.ValidxS <= '1';
+ NorthTXUFCM2SxD.DataxD <= DMA_INIT_DATA_SIZE;
+ end if;
+ -- East
+ if QoSDMAInitOcpCtrlxD(C_EAST_IF_ID) = '1' then
+ EastTXUFCM2SxD.ValidxS <= '1';
+ EastTXUFCM2SxD.DataxD <= DMA_INIT_DATA_SIZE;
+ end if;
+ -- South
+ if QoSDMAInitOcpCtrlxD(C_SOUTH_IF_ID) = '1' then
+ SouthTXUFCM2SxD.ValidxS <= '1';
+ SouthTXUFCM2SxD.DataxD <= DMA_INIT_DATA_SIZE;
+ end if;
+ -- West
+ if QoSDMAInitOcpCtrlxD(C_WEST_IF_ID) = '1' then
+ WestTXUFCM2SxD.ValidxS <= '1';
+ WestTXUFCM2SxD.DataxD <= DMA_INIT_DATA_SIZE;
+ end if;
+
+ -- UFC is not valid
+ -- North
+ if NorthTXUFCS2MxD.ReadyxS = '1' then
+ NorthTXUFCM2SxD.ValidxS <= '0';
+ NorthTXUFCM2SxD.DataxD <= (others => '0');
+ end if;
+ -- East
+ if EastTXUFCS2MxD.ReadyxS = '1' then
+ EastTXUFCM2SxD.ValidxS <= '0';
+ EastTXUFCM2SxD.DataxD <= (others => '0');
+ end if;
+ -- South
+ if SouthTXUFCS2MxD.ReadyxS = '1' then
+ SouthTXUFCM2SxD.ValidxS <= '0';
+ SouthTXUFCM2SxD.DataxD <= (others => '0');
+ end if;
+ -- West
+ if WestTXUFCS2MxD.ReadyxS = '1' then
+ WestTXUFCM2SxD.ValidxS <= '0';
+ WestTXUFCM2SxD.DataxD <= (others => '0');
+ end if;
+ end if;
+ end process UFCTXValidxP;
+
+ UFCRXDataxP : process (AuroraClkMasterxC.UserClkxC,
+ ScalpRouterResetxRNA) is
+ begin -- process UFCRXDataxP
+ if ScalpRouterResetxRNA = '0' then
+ QoSDMAInitStatusxD <= (others => '0');
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ QoSDMAInitStatusxD <= QoSDMAInitStatusxD;
+
+ -- North
+ if NorthRXUFCM2SxD.ValidxS = '1' and NorthRXUFCM2SxD.DataxD = DMA_INIT_MAGIC_WORD then
+ QoSDMAInitStatusxD(C_NORTH_IF_ID) <= not QoSDMAInitStatusxD(C_NORTH_IF_ID);
+ end if;
+ -- East
+ if EastRXUFCM2SxD.ValidxS = '1' and EastRXUFCM2SxD.DataxD = DMA_INIT_MAGIC_WORD then
+ QoSDMAInitStatusxD(C_EAST_IF_ID) <= not QoSDMAInitStatusxD(C_EAST_IF_ID);
+ end if;
+ -- South
+ if SouthRXUFCM2SxD.ValidxS = '1' and SouthRXUFCM2SxD.DataxD = DMA_INIT_MAGIC_WORD then
+ QoSDMAInitStatusxD(C_SOUTH_IF_ID) <= not QoSDMAInitStatusxD(C_SOUTH_IF_ID);
+ end if;
+ -- West
+ if WestRXUFCM2SxD.ValidxS = '1' and WestRXUFCM2SxD.DataxD = DMA_INIT_MAGIC_WORD then
+ QoSDMAInitStatusxD(C_WEST_IF_ID) <= not QoSDMAInitStatusxD(C_WEST_IF_ID);
+ end if;
+ end if;
+ end process UFCRXDataxP;
+
+ -- RX Side
+ NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
+ EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
+ SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
+ WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD;
+ NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID);
+ EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID);
+ SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
+ WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
+
+ end block QoSUFCxB;
+
QoSLaneChanUpxB : block is
signal PhyStatusxD : std_ulogic_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => '0');
diff --git a/ips/hw/scalp_fast_router_registers/component.xml b/ips/hw/scalp_fast_router_registers/component.xml
index b3245dd..7fa8eda 100644
--- a/ips/hw/scalp_fast_router_registers/component.xml
+++ b/ips/hw/scalp_fast_router_registers/component.xml
@@ -3,7 +3,7 @@
<spirit:vendor>hepia.hesge.ch</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>scalp_fast_router_registers</spirit:name>
- <spirit:version>1.3</spirit:version>
+ <spirit:version>1.5</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>SAxiClkxCI</spirit:name>
@@ -28,7 +28,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_RESET">DMAFifoWrDataCntxDO:DMAFifoRrDataCntxDO:LocalNetAddrxDO:RGBLed0xDO:RGBLed1xDO:DMAFifoStatusxDI:DMAFifoWrDataCntxDI:DMAFifoRrDataCntxDI:SAxiRstxRANI:DMAFifoTXWrDataCntxDI:DMAFifoTXRrDataCntxDI:DMAFifoTXStatusxDI:DMAFifoRXWrDataCntxDI:DMAFifoRXRrDataCntxDI:DMAFifoRXStatusxDI:QoSPhyStatusxDI</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_RESET">DMAFifoWrDataCntxDO:DMAFifoRrDataCntxDO:LocalNetAddrxDO:RGBLed0xDO:RGBLed1xDO:DMAFifoStatusxDI:DMAFifoWrDataCntxDI:DMAFifoRrDataCntxDI:SAxiRstxRANI:DMAFifoTXWrDataCntxDI:DMAFifoTXRrDataCntxDI:DMAFifoTXStatusxDI:DMAFifoRXWrDataCntxDI:DMAFifoRXRrDataCntxDI:DMAFifoRXStatusxDI:QoSPhyStatusxDI:QoSDMAInitOcpCtrlxDO:QoSDMAInitStatusxDI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
@@ -390,6 +390,50 @@
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>QoSDMAInitOcpCtrlxDO</spirit:name>
+ <spirit:displayName>QoSDMAInitOcpCtrlxDO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>QoSDMAInitOcpCtrlxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>QoSDMAInitStatusxDI</spirit:name>
+ <spirit:displayName>QoSDMAInitStatusxDI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>QoSDMAInitStatusxDI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.QOSDMAINITSTATUSXDI.NUM_READ_OUTSTANDING"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.QOSDMAINITSTATUSXDI.NUM_WRITE_OUTSTANDING"/>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
@@ -417,7 +461,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>1322956f</spirit:value>
+ <spirit:value>7b355a12</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -433,7 +477,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>1322956f</spirit:value>
+ <spirit:value>7b355a12</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -898,6 +942,40 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>QoSDMAInitOcpCtrlxDO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_DATA_SIZE')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>QoSDMAInitStatusxDI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_DATA_SIZE')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
@@ -953,7 +1031,7 @@
<spirit:file>
<spirit:name>src/hdl/scalp_fast_router_registers.vhd</spirit:name>
<spirit:userFileType>vhdlSource-2008</spirit:userFileType>
- <spirit:userFileType>CHECKSUM_1322956f</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_7b355a12</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -966,14 +1044,14 @@
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>xgui/scalp_fast_router_registers_v1_3.tcl</spirit:name>
+ <spirit:name>xgui/scalp_fast_router_registers_v1_5.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_94c74469</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
- <spirit:description>scalp_fast_router_registers_v1_3</spirit:description>
+ <spirit:description>scalp_fast_router_registers_v1_5</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_AXI4_ARADDR_SIZE</spirit:name>
@@ -1053,12 +1131,12 @@
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>scalp_fast_router_registers_v1_3</xilinx:displayName>
+ <xilinx:displayName>scalp_fast_router_registers_v1_5</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:vendorDisplayName>Scalp Fast Router Registers</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://hepia.hesge.ch</xilinx:vendorURL>
- <xilinx:coreRevision>10</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2021-10-21T06:51:53Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>19</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2021-10-26T09:28:15Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@14e5815b_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@61e1c054_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
@@ -1285,14 +1363,127 @@
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+ <xilinx:tag xilinx:name="ui.data.coregen.dd@c308f58_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3143b112_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
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+ <xilinx:tag xilinx:name="ui.data.coregen.dd@69647ee9_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ee5bc34_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77454455_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@52ecd5c9_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@12563152_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@470281e_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2309114_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9067f7bf"/>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="575cacfc"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="191f6c5f"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af58bdbd"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="8f8baa03"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9d1a9ad7"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="3a9f2f1d"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d2e1fb7a"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="d7187a94"/>
</xilinx:packagingInfo>
diff --git a/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd b/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
index 07215da..e6f5903 100644
--- a/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
+++ b/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
@@ -64,7 +64,9 @@ entity scalp_fast_router_registers is
DMAFifoRXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXRrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
- QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
+ QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ QoSDMAInitOcpCtrlxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ QoSDMAInitStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
end scalp_fast_router_registers;
@@ -82,49 +84,74 @@ architecture behavioral of scalp_fast_router_registers is
-- Signals
-- Clock and reset
- signal SAxiClkxC : std_ulogic := '0';
- signal SAxiRstxRAN : std_ulogic := '0';
+ signal SAxiClkxC : std_ulogic := '0';
+ signal SAxiRstxRAN : std_ulogic := '0';
-- AXI4 Lite
- signal SAxiARReadyxS : std_ulogic := '0';
- signal SAxiRValidxS : std_ulogic := '0';
- signal SAxiBValidxS : std_ulogic := '0';
- signal SAxiWReadyxS : std_ulogic := '0';
- signal SAxiAWReadyxS : std_ulogic := '0';
- signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal SAxiARReadyxS : std_ulogic := '0';
+ signal SAxiRValidxS : std_ulogic := '0';
+ signal SAxiBValidxS : std_ulogic := '0';
+ signal SAxiWReadyxS : std_ulogic := '0';
+ signal SAxiAWReadyxS : std_ulogic := '0';
+ signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- Signals of access to the register bank
- signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RdValidxS : std_ulogic := '0';
- signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WrValidxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
-- Registers list
- signal LocalNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal LocalNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RGBLed0PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RGBLed0PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RGBLed1PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RGBLed1PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoTXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoTXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoTXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoTXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoTXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoTXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoRXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoRXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoRXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoRXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoRXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal DMAFifoRXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal QoSPhyStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal QoSPhyStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal LocalNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal LocalNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed0PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed0PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed1PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed1PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSPhyStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSPhyStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSDMAInitOcpCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSDMAInitOcpCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSDMAInitStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSDMAInitStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ -- Debug
+ signal WValidxS : std_ulogic := '0';
+ signal AWValidxS : std_ulogic := '0';
+ signal WDataxD : std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0) := (others => '0');
+ signal AWAddrxD : std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0) := (others => '0');
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
+ attribute mark_debug of WrValidxS : signal is "true";
+ attribute keep of WrValidxS : signal is "true";
+ attribute mark_debug of WrAddrxD : signal is "true";
+ attribute keep of WrAddrxD : signal is "true";
+ attribute mark_debug of WrDataxD : signal is "true";
+ attribute keep of WrDataxD : signal is "true";
+ attribute mark_debug of WValidxS : signal is "true";
+ attribute keep of WValidxS : signal is "true";
+ attribute mark_debug of AWValidxS : signal is "true";
+ attribute keep of AWValidxS : signal is "true";
+ attribute mark_debug of WDataxD : signal is "true";
+ attribute keep of WDataxD : signal is "true";
+ attribute mark_debug of AWAddrxD : signal is "true";
+ attribute keep of AWAddrxD : signal is "true";
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
@@ -160,7 +187,7 @@ begin
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
- WrValidxAS : WrValidxS <= SAxiWValidxSI;
+ WrValidxAS : WrValidxS <= SAxiWValidxSI and not SAxiAWValidxSI;
WrDataxAS : WrDataxD <= SAxiWDataxDI;
WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
@@ -169,6 +196,16 @@ begin
end block EntityIOxB;
+ DebugxB : block is
+ begin -- block DebugxB
+
+ WValidxAS : WValidxS <= SAxiWValidxSI;
+ AWValidxAS : AWValidxS <= SAxiAWValidxSI;
+ WDataxAS : WDataxD <= SAxiWDataxDI;
+ AWAddrxAS : AWAddrxD <= SAxiAWAddrxDI;
+
+ end block DebugxB;
+
AXI4LitexB : block is
begin -- block AXI4LitexB
@@ -302,7 +339,9 @@ begin
WriteRegPortxP : process (DMAFifoRXRrDataCntxDI, DMAFifoRXStatusxDI,
DMAFifoRXWrDataCntxDI, DMAFifoTXRrDataCntxDI,
DMAFifoTXStatusxDI, DMAFifoTXWrDataCntxDI,
- LocalNetAddrPortxDP, QoSPhyStatusxDI,
+ LocalNetAddrPortxDP,
+ QoSDMAInitOcpCtrlPortxDP,
+ QoSDMAInitStatusxDI, QoSPhyStatusxDI,
RGBLed0PortxDP, RGBLed1PortxDP, WrAddrxD,
WrDataxD, WrValidxS) is
begin -- process WriteRegPortxP
@@ -319,12 +358,16 @@ begin
DMAFifoRXRrDataCntPortxDN <= DMAFifoRXRrDataCntxDI;
DMAFifoRXStatusPortxDN <= DMAFifoRXStatusxDI;
QoSPhyStatusPortxDN <= QoSPhyStatusxDI;
+ QoSDMAInitOcpCtrlPortxDN <= (others => '0');
+ QoSDMAInitOcpCtrlxDO <= QoSDMAInitOcpCtrlPortxDP;
+ QoSDMAInitStatusPortxDN <= QoSDMAInitStatusxDI;
if WrValidxS = '1' then
case WrAddrxD is
- when x"000" => LocalNetAddrPortxDN <= WrDataxD;
- when x"004" => RGBLed0PortxDN <= WrDataxD;
- when x"008" => RGBLed1PortxDN <= WrDataxD;
+ when x"000" => LocalNetAddrPortxDN <= WrDataxD;
+ when x"004" => RGBLed0PortxDN <= WrDataxD;
+ when x"008" => RGBLed1PortxDN <= WrDataxD;
+ when x"028" => QoSDMAInitOcpCtrlPortxDN <= WrDataxD;
when others => null;
end case;
@@ -350,6 +393,7 @@ begin
when x"01C" => RdDataxD <= DMAFifoRXRrDataCntPortxDP;
when x"020" => RdDataxD <= DMAFifoRXStatusPortxDP;
when x"024" => RdDataxD <= QoSPhyStatusPortxDP;
+ when x"02C" => RdDataxD <= QoSDMAInitStatusPortxDP;
when others => RdDataxD <= (others => '0');
end case;
@@ -370,6 +414,8 @@ begin
DMAFifoRXRrDataCntPortxDP <= x"00000000";
DMAFifoRXStatusPortxDP <= x"00000000";
QoSPhyStatusPortxDP <= x"00000000";
+ QoSDMAInitOcpCtrlPortxDP <= x"00000000";
+ QoSDMAInitStatusPortxDP <= x"00000000";
elsif rising_edge(SAxiClkxC) then
LocalNetAddrPortxDP <= LocalNetAddrPortxDN;
@@ -382,6 +428,8 @@ begin
DMAFifoRXRrDataCntPortxDP <= DMAFifoRXRrDataCntPortxDN;
DMAFifoRXStatusPortxDP <= DMAFifoRXStatusPortxDN;
QoSPhyStatusPortxDP <= QoSPhyStatusPortxDN;
+ QoSDMAInitOcpCtrlPortxDP <= QoSDMAInitOcpCtrlPortxDN;
+ QoSDMAInitStatusPortxDP <= QoSDMAInitStatusPortxDN;
end if;
end process UpdateRegBankxP;
diff --git a/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_4.tcl b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_4.tcl
new file mode 100644
index 0000000..72aafc8
--- /dev/null
+++ b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_4.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_5.tcl b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_5.tcl
new file mode 100644
index 0000000..72aafc8
--- /dev/null
+++ b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_5.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd b/ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd
index d180616..dc4e040 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: Box for dropping packets.
--
--- Last update: 2021-10-22
+-- Last update: 2021-10-26
--
---------------------------------------------------------------------------------
library ieee;
@@ -40,6 +40,8 @@ entity scalp_dropbox is
-- System Clock and Reset
SysClkxCI : in std_ulogic;
SysRstxRNAI : in std_ulogic;
+ -- Source Interfaces Number
+ IfSrcNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
-- Destination Interface Number
IfDstNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSI : in std_ulogic;
@@ -48,6 +50,7 @@ entity scalp_dropbox is
-- QoS Vector
QoSVectorPhyStatusxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
-- Dropped signals
+ ToBeDroppedxSI : in std_ulogic;
ToBeDroppedxSO : out std_ulogic;
IsDroppedxSI : in std_ulogic);
@@ -64,11 +67,13 @@ architecture behavioral of scalp_dropbox is
constant C_SCALP_BOTTOM_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 5;
constant C_SCALP_LOCAL_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 6;
+ signal IfSrcNumInxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfDstNumInxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfNumValidInxS : std_ulogic := '0';
signal IfDstNumOutxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfNumValidOutxS : std_ulogic := '0';
signal QoSVectorPhyStatusxD : t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal ToBeDroppedFromRCxS : std_ulogic := '0';
signal ToBeDroppedxS : std_ulogic := '0';
signal IsDroppedxS : std_ulogic := '0';
@@ -81,12 +86,14 @@ begin -- architecture behavioral
EntityIOxB : block is
begin -- block EntityIOxB
+ IfSrcNumInxAS : IfSrcNumInxD <= IfSrcNumxDI;
IfDstNumInxAS : IfDstNumInxD <= IfDstNumxDI;
IfNumValidInxAS : IfNumValidInxS <= IfNumValidxSI;
IfDstNumOutxAS : IfDstNumxDO <= IfDstNumOutxD;
IfNumValidOutxAS : IfNumValidxSO <= IfNumValidOutxS;
QoSVectorPhyStatusxAS : QoSVectorPhyStatusxD <= QoSVectorPhyStatusxDI;
ToBeDroppedxAS : ToBeDroppedxSO <= ToBeDroppedxS;
+ ToBeDroppedFromRCxAS : ToBeDroppedFromRCxS <= ToBeDroppedxSI;
IsDroppedxAS : IsDroppedxS <= IsDroppedxSI;
end block EntityIOxB;
@@ -101,7 +108,8 @@ begin -- architecture behavioral
IfNumValidOutxS <= '0';
IfDstNumOutxD <= C_SCALP_NO_NUM;
- if (IfNumValidInxS = '1') and (to_integer(QoSVectorPhyStatusxD(IfDstNumInxD)) = 0) then
+ if ((IfNumValidInxS = '1') and (to_integer(QoSVectorPhyStatusxD(IfDstNumInxD)) = 0)) or
+ (ToBeDroppedFromRCxS = '1') then
ToBeDroppedxS <= '1';
IfDstNumOutxD <= C_SCALP_NO_NUM;
IfNumValidOutxS <= '0';
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
index d299524..5204bfc 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Core Algorithm
--
--- Last update: 2021-10-22
+-- Last update: 2021-10-26
--
---------------------------------------------------------------------------------
library ieee;
@@ -52,7 +52,9 @@ entity scalp_router_core is
IfDstNumxDO : out integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSO : out std_ulogic;
-- QoS Vector
- QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0));
+ QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
+ -- Dropped signals
+ ToBeDroppedxSO : out std_ulogic);
end entity scalp_router_core;
@@ -75,6 +77,7 @@ architecture behavioral_xyz of scalp_router_core is
signal IfDstNumxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfNumValidxS : std_ulogic := '0';
signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal ToBeDroppedxS : std_ulogic := '0';
-- Attributes
attribute mark_debug : string;
@@ -93,18 +96,29 @@ begin -- architecture behavioral
IfDstNumxAS : IfDstNumxDO <= IfDstNumxD;
IfNumValidxAS : IfNumValidxSO <= IfNumValidxS;
QoSVectorxAS : QoSVectorxD <= QoSVectorxDI;
+ ToBeDroppedxAS : ToBeDroppedxSO <= ToBeDroppedxS;
end block EntityIOxB;
ScalpRouterCorexP : process (SysClkxCI, SysRstxRNAI) is
begin -- process ScalpRouterCorexP
if SysRstxRNAI = '0' then
- IfDstNumxD <= C_SCALP_NO_NUM;
- IfNumValidxS <= '0';
+ IfDstNumxD <= C_SCALP_NO_NUM;
+ IfNumValidxS <= '0';
+ ToBeDroppedxS <= '0';
elsif rising_edge(SysClkxCI) then
- IfDstNumxD <= C_SCALP_NO_NUM;
- IfNumValidxS <= '0';
+ IfDstNumxD <= C_SCALP_NO_NUM;
+ IfNumValidxS <= '0';
+ ToBeDroppedxS <= '0';
if RouterNetAddrValidxS = '1' then
+ -- No Loopback on Local
+ if (LocRouterNetAddrxD.XxD = DstRouterNetAddrxD.XxD) and
+ (LocRouterNetAddrxD.YxD = DstRouterNetAddrxD.YxD) and
+ (LocRouterNetAddrxD.ZxD = DstRouterNetAddrxD.ZxD) and
+ (IfSrcNumxD = C_SCALP_LOCAL_NUM) then
+ ToBeDroppedxS <= '1';
+ end if;
+
-- Packet Type
if (PktTypexD.TypexD = C_SCALP_PACKET_TYPE_UNICAST_NEIGHBORS) and
(IfSrcNumxD /= C_SCALP_LOCAL_NUM) then
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
index 445b742..1310025 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Interface.
--
--- Last update: 2021-10-22
+-- Last update: 2021-10-26
--
---------------------------------------------------------------------------------
library ieee;
@@ -130,16 +130,21 @@ architecture rtl of scalp_router_interface is
IfSrcNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfDstNumxDO : out integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSO : out std_ulogic;
- QoSVectorxDI : in std_ulogic_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0));
+ QoSVectorxDI : in std_ulogic_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
+ ToBeDroppedxSO : out std_ulogic);
end component scalp_router_core;
component scalp_dropbox is
generic (
C_SCALP_INTERFACE_VECTOR_SIZE : integer range 0 to 255);
port (
+ SysClkxCI : in std_ulogic;
+ SysRstxRNAI : in std_ulogic;
+ IfSrcNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfDstNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSI : in std_ulogic;
QoSVectorPhyStatusxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
+ ToBeDroppedxSI : in std_ulogic;
ToBeDroppedxSO : out std_ulogic;
IsDroppedxSI : in std_ulogic);
end component scalp_dropbox;
@@ -210,6 +215,7 @@ architecture rtl of scalp_router_interface is
signal RouterNetAddrValidxS : std_ulogic := '0';
signal PktTypexD : t_scalp_type := C_SCALP_NO_TYPE;
signal ToBeDroppedxS : std_ulogic := '0';
+ signal ToBeDroppedFromRCxS : std_ulogic := '0';
signal BookingVectorValidxS : std_ulogic := '0';
signal SchedulerAckxD : std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal TXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
@@ -303,7 +309,8 @@ begin -- architecture rtl
IfSrcNumxDI => IfSrcNumxD,
IfDstNumxDO => IfDstNumFromRCxD,
IfNumValidxSO => IfNumValidFromRCxS,
- QoSVectorxDI => QoSVectorxD);
+ QoSVectorxDI => QoSVectorxD,
+ ToBeDroppedxSO => ToBeDroppedFromRCxS);
ScalpDropBoxxI : entity work.scalp_dropbox
generic map (
@@ -311,11 +318,13 @@ begin -- architecture rtl
port map (
SysClkxCI => SysClkxCI,
SysRstxRNAI => SysRstxRNAI,
+ IfSrcNumxDI => IfSrcNumxD,
IfDstNumxDI => IfDstNumFromRCxD,
IfNumValidxSI => IfNumValidFromRCxS,
IfDstNumxDO => IfDstNumFromDBxD,
IfNumValidxSO => IfNumValidFromDBxS,
QoSVectorPhyStatusxDI => QoSVectorPyhStatusxD,
+ ToBeDroppedxSI => ToBeDroppedFromRCxS,
ToBeDroppedxSO => ToBeDroppedxS,
IsDroppedxSI => TXAxi4M2SLinkxD.LastxS); -- Finish
diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
index fa4c6ef..e26a8bb 100644
--- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
--- Last update: 2021-10-21
+-- Last update: 2021-10-25
--
---------------------------------------------------------------------------------
@@ -30,67 +30,69 @@ entity scalp_zynqps_wrapper is
port (
-- Processor interface
- FIXED_IO_ps_clk : inout std_ulogic;
- FIXED_IO_ps_porb : inout std_ulogic;
- FIXED_IO_ps_srstb : inout std_ulogic;
- FclkClk0xCO : out std_ulogic;
- FclkReset0xRO : out std_ulogic;
+ FIXED_IO_ps_clk : inout std_ulogic;
+ FIXED_IO_ps_porb : inout std_ulogic;
+ FIXED_IO_ps_srstb : inout std_ulogic;
+ FclkClk0xCO : out std_ulogic;
+ FclkReset0xRO : out std_ulogic;
-- DDR interface
- DDR_addr : inout std_ulogic_vector (14 downto 0);
- DDR_ba : inout std_ulogic_vector (2 downto 0);
- DDR_cas_n : inout std_ulogic;
- DDR_ck_n : inout std_ulogic;
- DDR_ck_p : inout std_ulogic;
- DDR_cke : inout std_ulogic;
- DDR_cs_n : inout std_ulogic;
- DDR_dm : inout std_ulogic_vector (3 downto 0);
- DDR_dq : inout std_ulogic_vector (31 downto 0);
- DDR_dqs_n : inout std_ulogic_vector (3 downto 0);
- DDR_dqs_p : inout std_ulogic_vector (3 downto 0);
- DDR_odt : inout std_ulogic;
- DDR_ras_n : inout std_ulogic;
- DDR_reset_n : inout std_ulogic;
- DDR_we_n : inout std_ulogic;
- FIXED_IO_ddr_vrn : inout std_ulogic;
- FIXED_IO_ddr_vrp : inout std_ulogic;
+ DDR_addr : inout std_ulogic_vector (14 downto 0);
+ DDR_ba : inout std_ulogic_vector (2 downto 0);
+ DDR_cas_n : inout std_ulogic;
+ DDR_ck_n : inout std_ulogic;
+ DDR_ck_p : inout std_ulogic;
+ DDR_cke : inout std_ulogic;
+ DDR_cs_n : inout std_ulogic;
+ DDR_dm : inout std_ulogic_vector (3 downto 0);
+ DDR_dq : inout std_ulogic_vector (31 downto 0);
+ DDR_dqs_n : inout std_ulogic_vector (3 downto 0);
+ DDR_dqs_p : inout std_ulogic_vector (3 downto 0);
+ DDR_odt : inout std_ulogic;
+ DDR_ras_n : inout std_ulogic;
+ DDR_reset_n : inout std_ulogic;
+ DDR_we_n : inout std_ulogic;
+ FIXED_IO_ddr_vrn : inout std_ulogic;
+ FIXED_IO_ddr_vrp : inout std_ulogic;
-- USB interface
- Usb0VBusPwrFaultxSI : in std_ulogic;
+ Usb0VBusPwrFaultxSI : in std_ulogic;
-- SPI1 used as uWire master. Clk, Data and LE signals are outputs
-- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
- Spi1MOSIxSO : out std_ulogic;
- Spi1SSxSO : out std_ulogic;
- Spi1SclkxCO : out std_ulogic;
+ Spi1MOSIxSO : out std_ulogic;
+ Spi1SSxSO : out std_ulogic;
+ Spi1SclkxCO : out std_ulogic;
-- MIO
- FIXED_IO_mio : inout std_ulogic_vector (53 downto 0);
- UserClkxCI : in std_ulogic;
- UserResetxRANI : in std_ulogic;
+ FIXED_IO_mio : inout std_ulogic_vector (53 downto 0);
+ UserClkxCI : in std_ulogic;
+ UserResetxRANI : in std_ulogic;
-- Scalp Fast Router Registers
- LocalNetAddrxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
- RGBLed0xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
- RGBLed1xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
- QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ LocalNetAddrxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RGBLed0xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RGBLed1xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ QoSDMAInitOcpCtrlxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ QoSDMAInitStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
-- RX
- DMARXm2sxDI : in t_axi4m2s;
- DMARXs2mxDO : out t_axi4s2m;
+ DMARXm2sxDI : in t_axi4m2s;
+ DMARXs2mxDO : out t_axi4s2m;
-- TX
- DMATXm2sxDO : out t_axi4m2s;
- DMATXs2mxDI : in t_axi4s2m;
+ DMATXm2sxDO : out t_axi4m2s;
+ DMATXs2mxDI : in t_axi4s2m;
-- Debug
-- West Phy
- WestRXM2SxDI : in t_axi4m2s;
- WestRXS2MxDI : in t_axi4s2m;
- WestTXM2SxDI : in t_axi4m2s;
- WestTXS2MxDI : in t_axi4s2m;
+ WestRXM2SxDI : in t_axi4m2s;
+ WestRXS2MxDI : in t_axi4s2m;
+ WestTXM2SxDI : in t_axi4m2s;
+ WestTXS2MxDI : in t_axi4s2m;
-- East Phy
- EastRXM2SxDI : in t_axi4m2s;
- EastRXS2MxDI : in t_axi4s2m;
- EastTXM2SxDI : in t_axi4m2s;
- EastTXS2MxDI : in t_axi4s2m;
+ EastRXM2SxDI : in t_axi4m2s;
+ EastRXS2MxDI : in t_axi4s2m;
+ EastTXM2SxDI : in t_axi4m2s;
+ EastTXS2MxDI : in t_axi4s2m;
-- Local NoC
- LocalRXM2SxDI : in t_axi4m2s;
- LocalRXS2MxDI : in t_axi4s2m;
- LocalTXM2SxDI : in t_axi4m2s;
- LocalTXS2MxDI : in t_axi4s2m);
+ LocalRXM2SxDI : in t_axi4m2s;
+ LocalRXS2MxDI : in t_axi4s2m;
+ LocalTXM2SxDI : in t_axi4m2s;
+ LocalTXS2MxDI : in t_axi4s2m);
end scalp_zynqps_wrapper;
@@ -142,6 +144,8 @@ begin
RGBLed0xDO => RGBLed0xDO,
RGBLed1xDO => RGBLed1xDO,
QoSPhyStatusxDI => QoSPhyStatusxDI,
+ QoSDMAInitOcpCtrlxDO => QoSDMAInitOcpCtrlxDO,
+ QoSDMAInitStatusxDI => QoSDMAInitStatusxDI,
-- AXIS
-- DMA
DMARXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => DMARXm2sxDI.DataxD,
diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index 48af314..b671a14 100644
--- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -128,7 +128,7 @@ xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
hepia.hesge.ch:user:scalp_dma_fifo:1.0\
-hepia.hesge.ch:user:scalp_fast_router_registers:1.3\
+hepia.hesge.ch:user:scalp_fast_router_registers:1.5\
xilinx.com:ip:system_ila:1.1\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
@@ -257,6 +257,8 @@ proc create_root_design { parentCell } {
] $FclkClk0xCO
set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
set LocalNetAddrxDO [ create_bd_port -dir O -from 31 -to 0 -type data LocalNetAddrxDO ]
+ set QoSDMAInitOcpCtrlxDO [ create_bd_port -dir O -from 31 -to 0 -type data QoSDMAInitOcpCtrlxDO ]
+ set QoSDMAInitStatusxDI [ create_bd_port -dir I -from 31 -to 0 -type data QoSDMAInitStatusxDI ]
set QoSPhyStatusxDI [ create_bd_port -dir I -from 31 -to 0 -type data QoSPhyStatusxDI ]
set RGBLed0xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed0xDO ]
set RGBLed1xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed1xDO ]
@@ -769,7 +771,7 @@ proc create_root_design { parentCell } {
set scalp_dma_fifo_tx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_tx_0 ]
# Create instance: scalp_fast_router_registers_0, and set properties
- set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.3 scalp_fast_router_registers_0 ]
+ set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.5 scalp_fast_router_registers_0 ]
# Create instance: system_ila_0, and set properties
set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
@@ -881,6 +883,7 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO] [g
connect_bd_intf_net -intf_net scalp_dma_fifo_tx_0_DMATXxDO [get_bd_intf_ports DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMATXxDO]
# Create port connections
+ connect_bd_net -net QoSDMAInitStatusxDI_0_1 [get_bd_ports QoSDMAInitStatusxDI] [get_bd_pins scalp_fast_router_registers_0/QoSDMAInitStatusxDI]
connect_bd_net -net QoSPhyStatusxDI_0_1 [get_bd_ports QoSPhyStatusxDI] [get_bd_pins scalp_fast_router_registers_0/QoSPhyStatusxDI]
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins axi_clock_converter_2/s_axi_aclk] [get_bd_pins axi_clock_converter_3/m_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins scalp_dma_fifo_rx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_rx_0/TXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/TXClkxCI] [get_bd_pins scalp_fast_router_registers_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk]
@@ -912,6 +915,7 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO] [g
connect_bd_net -net scalp_fast_router_re_0_RGBLed0xDO [get_bd_ports RGBLed0xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed0xDO]
connect_bd_net -net scalp_fast_router_re_0_RGBLed1xDO [get_bd_ports RGBLed1xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed1xDO]
connect_bd_net -net scalp_fast_router_registers_0_LocalNetAddrxDO [get_bd_ports LocalNetAddrxDO] [get_bd_pins scalp_fast_router_registers_0/LocalNetAddrxDO]
+ connect_bd_net -net scalp_fast_router_registers_0_QoSDMAInitOcpCtrlxDO [get_bd_ports QoSDMAInitOcpCtrlxDO] [get_bd_pins scalp_fast_router_registers_0/QoSDMAInitOcpCtrlxDO]
connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
--
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