diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..c75ddeb46bfac220578813317c2ee8303d74f683
--- /dev/null
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc
@@ -0,0 +1,158 @@
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 32 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {TXAxism2sVectorxD[1][DataxD][31]} {TXAxism2sVectorxD[1][DataxD][30]} {TXAxism2sVectorxD[1][DataxD][29]} {TXAxism2sVectorxD[1][DataxD][28]} {TXAxism2sVectorxD[1][DataxD][27]} {TXAxism2sVectorxD[1][DataxD][26]} {TXAxism2sVectorxD[1][DataxD][25]} {TXAxism2sVectorxD[1][DataxD][24]} {TXAxism2sVectorxD[1][DataxD][23]} {TXAxism2sVectorxD[1][DataxD][22]} {TXAxism2sVectorxD[1][DataxD][21]} {TXAxism2sVectorxD[1][DataxD][20]} {TXAxism2sVectorxD[1][DataxD][19]} {TXAxism2sVectorxD[1][DataxD][18]} {TXAxism2sVectorxD[1][DataxD][17]} {TXAxism2sVectorxD[1][DataxD][16]} {TXAxism2sVectorxD[1][DataxD][15]} {TXAxism2sVectorxD[1][DataxD][14]} {TXAxism2sVectorxD[1][DataxD][13]} {TXAxism2sVectorxD[1][DataxD][12]} {TXAxism2sVectorxD[1][DataxD][11]} {TXAxism2sVectorxD[1][DataxD][10]} {TXAxism2sVectorxD[1][DataxD][9]} {TXAxism2sVectorxD[1][DataxD][8]} {TXAxism2sVectorxD[1][DataxD][7]} {TXAxism2sVectorxD[1][DataxD][6]} {TXAxism2sVectorxD[1][DataxD][5]} {TXAxism2sVectorxD[1][DataxD][4]} {TXAxism2sVectorxD[1][DataxD][3]} {TXAxism2sVectorxD[1][DataxD][2]} {TXAxism2sVectorxD[1][DataxD][1]} {TXAxism2sVectorxD[1][DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 32 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {TXAxism2sVectorxD[2][DataxD][31]} {TXAxism2sVectorxD[2][DataxD][30]} {TXAxism2sVectorxD[2][DataxD][29]} {TXAxism2sVectorxD[2][DataxD][28]} {TXAxism2sVectorxD[2][DataxD][27]} {TXAxism2sVectorxD[2][DataxD][26]} {TXAxism2sVectorxD[2][DataxD][25]} {TXAxism2sVectorxD[2][DataxD][24]} {TXAxism2sVectorxD[2][DataxD][23]} {TXAxism2sVectorxD[2][DataxD][22]} {TXAxism2sVectorxD[2][DataxD][21]} {TXAxism2sVectorxD[2][DataxD][20]} {TXAxism2sVectorxD[2][DataxD][19]} {TXAxism2sVectorxD[2][DataxD][18]} {TXAxism2sVectorxD[2][DataxD][17]} {TXAxism2sVectorxD[2][DataxD][16]} {TXAxism2sVectorxD[2][DataxD][15]} {TXAxism2sVectorxD[2][DataxD][14]} {TXAxism2sVectorxD[2][DataxD][13]} {TXAxism2sVectorxD[2][DataxD][12]} {TXAxism2sVectorxD[2][DataxD][11]} {TXAxism2sVectorxD[2][DataxD][10]} {TXAxism2sVectorxD[2][DataxD][9]} {TXAxism2sVectorxD[2][DataxD][8]} {TXAxism2sVectorxD[2][DataxD][7]} {TXAxism2sVectorxD[2][DataxD][6]} {TXAxism2sVectorxD[2][DataxD][5]} {TXAxism2sVectorxD[2][DataxD][4]} {TXAxism2sVectorxD[2][DataxD][3]} {TXAxism2sVectorxD[2][DataxD][2]} {TXAxism2sVectorxD[2][DataxD][1]} {TXAxism2sVectorxD[2][DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 32 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {TXAxism2sVectorxD[0][DataxD][31]} {TXAxism2sVectorxD[0][DataxD][30]} {TXAxism2sVectorxD[0][DataxD][29]} {TXAxism2sVectorxD[0][DataxD][28]} {TXAxism2sVectorxD[0][DataxD][27]} {TXAxism2sVectorxD[0][DataxD][26]} {TXAxism2sVectorxD[0][DataxD][25]} {TXAxism2sVectorxD[0][DataxD][24]} {TXAxism2sVectorxD[0][DataxD][23]} {TXAxism2sVectorxD[0][DataxD][22]} {TXAxism2sVectorxD[0][DataxD][21]} {TXAxism2sVectorxD[0][DataxD][20]} {TXAxism2sVectorxD[0][DataxD][19]} {TXAxism2sVectorxD[0][DataxD][18]} {TXAxism2sVectorxD[0][DataxD][17]} {TXAxism2sVectorxD[0][DataxD][16]} {TXAxism2sVectorxD[0][DataxD][15]} {TXAxism2sVectorxD[0][DataxD][14]} {TXAxism2sVectorxD[0][DataxD][13]} {TXAxism2sVectorxD[0][DataxD][12]} {TXAxism2sVectorxD[0][DataxD][11]} {TXAxism2sVectorxD[0][DataxD][10]} {TXAxism2sVectorxD[0][DataxD][9]} {TXAxism2sVectorxD[0][DataxD][8]} {TXAxism2sVectorxD[0][DataxD][7]} {TXAxism2sVectorxD[0][DataxD][6]} {TXAxism2sVectorxD[0][DataxD][5]} {TXAxism2sVectorxD[0][DataxD][4]} {TXAxism2sVectorxD[0][DataxD][3]} {TXAxism2sVectorxD[0][DataxD][2]} {TXAxism2sVectorxD[0][DataxD][1]} {TXAxism2sVectorxD[0][DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {TXAxism2sVectorxD[3][DataxD][31]} {TXAxism2sVectorxD[3][DataxD][30]} {TXAxism2sVectorxD[3][DataxD][29]} {TXAxism2sVectorxD[3][DataxD][28]} {TXAxism2sVectorxD[3][DataxD][27]} {TXAxism2sVectorxD[3][DataxD][26]} {TXAxism2sVectorxD[3][DataxD][25]} {TXAxism2sVectorxD[3][DataxD][24]} {TXAxism2sVectorxD[3][DataxD][23]} {TXAxism2sVectorxD[3][DataxD][22]} {TXAxism2sVectorxD[3][DataxD][21]} {TXAxism2sVectorxD[3][DataxD][20]} {TXAxism2sVectorxD[3][DataxD][19]} {TXAxism2sVectorxD[3][DataxD][18]} {TXAxism2sVectorxD[3][DataxD][17]} {TXAxism2sVectorxD[3][DataxD][16]} {TXAxism2sVectorxD[3][DataxD][15]} {TXAxism2sVectorxD[3][DataxD][14]} {TXAxism2sVectorxD[3][DataxD][13]} {TXAxism2sVectorxD[3][DataxD][12]} {TXAxism2sVectorxD[3][DataxD][11]} {TXAxism2sVectorxD[3][DataxD][10]} {TXAxism2sVectorxD[3][DataxD][9]} {TXAxism2sVectorxD[3][DataxD][8]} {TXAxism2sVectorxD[3][DataxD][7]} {TXAxism2sVectorxD[3][DataxD][6]} {TXAxism2sVectorxD[3][DataxD][5]} {TXAxism2sVectorxD[3][DataxD][4]} {TXAxism2sVectorxD[3][DataxD][3]} {TXAxism2sVectorxD[3][DataxD][2]} {TXAxism2sVectorxD[3][DataxD][1]} {TXAxism2sVectorxD[3][DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 32 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {TXAxism2sVectorxD[4][DataxD][31]} {TXAxism2sVectorxD[4][DataxD][30]} {TXAxism2sVectorxD[4][DataxD][29]} {TXAxism2sVectorxD[4][DataxD][28]} {TXAxism2sVectorxD[4][DataxD][27]} {TXAxism2sVectorxD[4][DataxD][26]} {TXAxism2sVectorxD[4][DataxD][25]} {TXAxism2sVectorxD[4][DataxD][24]} {TXAxism2sVectorxD[4][DataxD][23]} {TXAxism2sVectorxD[4][DataxD][22]} {TXAxism2sVectorxD[4][DataxD][21]} {TXAxism2sVectorxD[4][DataxD][20]} {TXAxism2sVectorxD[4][DataxD][19]} {TXAxism2sVectorxD[4][DataxD][18]} {TXAxism2sVectorxD[4][DataxD][17]} {TXAxism2sVectorxD[4][DataxD][16]} {TXAxism2sVectorxD[4][DataxD][15]} {TXAxism2sVectorxD[4][DataxD][14]} {TXAxism2sVectorxD[4][DataxD][13]} {TXAxism2sVectorxD[4][DataxD][12]} {TXAxism2sVectorxD[4][DataxD][11]} {TXAxism2sVectorxD[4][DataxD][10]} {TXAxism2sVectorxD[4][DataxD][9]} {TXAxism2sVectorxD[4][DataxD][8]} {TXAxism2sVectorxD[4][DataxD][7]} {TXAxism2sVectorxD[4][DataxD][6]} {TXAxism2sVectorxD[4][DataxD][5]} {TXAxism2sVectorxD[4][DataxD][4]} {TXAxism2sVectorxD[4][DataxD][3]} {TXAxism2sVectorxD[4][DataxD][2]} {TXAxism2sVectorxD[4][DataxD][1]} {TXAxism2sVectorxD[4][DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 32 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {TXAxism2sVectorxD[5][DataxD][31]} {TXAxism2sVectorxD[5][DataxD][30]} {TXAxism2sVectorxD[5][DataxD][29]} {TXAxism2sVectorxD[5][DataxD][28]} {TXAxism2sVectorxD[5][DataxD][27]} {TXAxism2sVectorxD[5][DataxD][26]} {TXAxism2sVectorxD[5][DataxD][25]} {TXAxism2sVectorxD[5][DataxD][24]} {TXAxism2sVectorxD[5][DataxD][23]} {TXAxism2sVectorxD[5][DataxD][22]} {TXAxism2sVectorxD[5][DataxD][21]} {TXAxism2sVectorxD[5][DataxD][20]} {TXAxism2sVectorxD[5][DataxD][19]} {TXAxism2sVectorxD[5][DataxD][18]} {TXAxism2sVectorxD[5][DataxD][17]} {TXAxism2sVectorxD[5][DataxD][16]} {TXAxism2sVectorxD[5][DataxD][15]} {TXAxism2sVectorxD[5][DataxD][14]} {TXAxism2sVectorxD[5][DataxD][13]} {TXAxism2sVectorxD[5][DataxD][12]} {TXAxism2sVectorxD[5][DataxD][11]} {TXAxism2sVectorxD[5][DataxD][10]} {TXAxism2sVectorxD[5][DataxD][9]} {TXAxism2sVectorxD[5][DataxD][8]} {TXAxism2sVectorxD[5][DataxD][7]} {TXAxism2sVectorxD[5][DataxD][6]} {TXAxism2sVectorxD[5][DataxD][5]} {TXAxism2sVectorxD[5][DataxD][4]} {TXAxism2sVectorxD[5][DataxD][3]} {TXAxism2sVectorxD[5][DataxD][2]} {TXAxism2sVectorxD[5][DataxD][1]} {TXAxism2sVectorxD[5][DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 32 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {TXAxism2sVectorxD[6][DataxD][31]} {TXAxism2sVectorxD[6][DataxD][30]} {TXAxism2sVectorxD[6][DataxD][29]} {TXAxism2sVectorxD[6][DataxD][28]} {TXAxism2sVectorxD[6][DataxD][27]} {TXAxism2sVectorxD[6][DataxD][26]} {TXAxism2sVectorxD[6][DataxD][25]} {TXAxism2sVectorxD[6][DataxD][24]} {TXAxism2sVectorxD[6][DataxD][23]} {TXAxism2sVectorxD[6][DataxD][22]} {TXAxism2sVectorxD[6][DataxD][21]} {TXAxism2sVectorxD[6][DataxD][20]} {TXAxism2sVectorxD[6][DataxD][19]} {TXAxism2sVectorxD[6][DataxD][18]} {TXAxism2sVectorxD[6][DataxD][17]} {TXAxism2sVectorxD[6][DataxD][16]} {TXAxism2sVectorxD[6][DataxD][15]} {TXAxism2sVectorxD[6][DataxD][14]} {TXAxism2sVectorxD[6][DataxD][13]} {TXAxism2sVectorxD[6][DataxD][12]} {TXAxism2sVectorxD[6][DataxD][11]} {TXAxism2sVectorxD[6][DataxD][10]} {TXAxism2sVectorxD[6][DataxD][9]} {TXAxism2sVectorxD[6][DataxD][8]} {TXAxism2sVectorxD[6][DataxD][7]} {TXAxism2sVectorxD[6][DataxD][6]} {TXAxism2sVectorxD[6][DataxD][5]} {TXAxism2sVectorxD[6][DataxD][4]} {TXAxism2sVectorxD[6][DataxD][3]} {TXAxism2sVectorxD[6][DataxD][2]} {TXAxism2sVectorxD[6][DataxD][1]} {TXAxism2sVectorxD[6][DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 32 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {WestRXM2SxD[DataxD][31]} {WestRXM2SxD[DataxD][30]} {WestRXM2SxD[DataxD][29]} {WestRXM2SxD[DataxD][28]} {WestRXM2SxD[DataxD][27]} {WestRXM2SxD[DataxD][26]} {WestRXM2SxD[DataxD][25]} {WestRXM2SxD[DataxD][24]} {WestRXM2SxD[DataxD][23]} {WestRXM2SxD[DataxD][22]} {WestRXM2SxD[DataxD][21]} {WestRXM2SxD[DataxD][20]} {WestRXM2SxD[DataxD][19]} {WestRXM2SxD[DataxD][18]} {WestRXM2SxD[DataxD][17]} {WestRXM2SxD[DataxD][16]} {WestRXM2SxD[DataxD][15]} {WestRXM2SxD[DataxD][14]} {WestRXM2SxD[DataxD][13]} {WestRXM2SxD[DataxD][12]} {WestRXM2SxD[DataxD][11]} {WestRXM2SxD[DataxD][10]} {WestRXM2SxD[DataxD][9]} {WestRXM2SxD[DataxD][8]} {WestRXM2SxD[DataxD][7]} {WestRXM2SxD[DataxD][6]} {WestRXM2SxD[DataxD][5]} {WestRXM2SxD[DataxD][4]} {WestRXM2SxD[DataxD][3]} {WestRXM2SxD[DataxD][2]} {WestRXM2SxD[DataxD][1]} {WestRXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 32 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list ScalpPacketValid12xS]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {TXAxism2sVectorxD[0][LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {TXAxism2sVectorxD[0][ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {TXAxism2sVectorxD[1][LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {TXAxism2sVectorxD[1][ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {TXAxism2sVectorxD[2][LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {TXAxism2sVectorxD[2][ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {TXAxism2sVectorxD[3][LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {TXAxism2sVectorxD[3][ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {TXAxism2sVectorxD[4][LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {TXAxism2sVectorxD[4][ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {TXAxism2sVectorxD[5][LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {TXAxism2sVectorxD[5][ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {TXAxism2sVectorxD[6][LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {TXAxism2sVectorxD[6][ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {TXAxiss2mVectorxD[0][ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {TXAxiss2mVectorxD[1][ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {TXAxiss2mVectorxD[2][ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {TXAxiss2mVectorxD[3][ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {TXAxiss2mVectorxD[4][ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {TXAxiss2mVectorxD[5][ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {TXAxiss2mVectorxD[6][ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list {WestRXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list {WestRXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list {WestRXS2MxD[ReadyxS]}]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/ibert_constraints.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/ibert_constraints.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..602b523f941544701ea24e62603c5fb40558d97e
--- /dev/null
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/ibert_constraints.xdc
@@ -0,0 +1,382 @@
+# Taken from IBERT example design
+
+##
+## Icon Constraints
+##
+create_clock -name J_CLK -period 30 [get_pins -of_objects [get_cells gen_ibert.ibert_inst/inst/bscan_inst/SERIES7_BSCAN.bscan_inst] -filter {name =~ *DRCK}]
+set_clock_groups -group [get_clocks J_CLK] -asynchronous
+##
+## System clock Divider paramter values
+##
+set_property CLKFBOUT_MULT_F 8.000 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property DIVCLK_DIVIDE 1 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property CLKIN1_PERIOD 8.0 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property CLKOUT0_DIVIDE_F 10.000 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+##
+## Refclk constraints
+##
+set_clock_groups -group [get_clocks GTP_REF_CLK_* -include_generated_clocks] -asynchronous
+#
+#
+#
+##
+## TX/RX out clock constraints
+##
+# GT X0Y0
+create_clock -name Q0_RXCLK0 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[0].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK0] -asynchronous
+create_clock -name Q0_TX0 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[0].u_ch/u_gtpe2_channel/TXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_TX0] -asynchronous
+# GT X0Y1
+create_clock -name Q0_RXCLK1 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[1].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK1] -asynchronous
+# GT X0Y2
+create_clock -name Q0_RXCLK2 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[2].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK2] -asynchronous
+# GT X0Y3
+create_clock -name Q0_RXCLK3 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[3].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK3] -asynchronous
+##
+## Timing constraint
+##
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM/CLKIN1]
+##
+## GTPE2 Channel and Common Loc constraints
+##
+set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[0].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[1].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[2].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y3 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[3].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_COMMON_X0Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+##
+## BUFH Loc constraints for TX/RX userclks
+##
+set_property LOC BUFHCE_X1Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/local_txusr.u_txusr]
+set_property LOC BUFHCE_X1Y1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr0]
+set_property LOC BUFHCE_X1Y2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr1]
+set_property LOC BUFHCE_X1Y3 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr2]
+set_property LOC BUFHCE_X1Y4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr3]
+##
+## MGT reference clock BUFFERS location constraints
+##
+
+
+set_property LOC IBUFDS_GTE2_X0Y0 [get_cells i_clocks.ibufds_GTP_REF_CLK_0]
+set_property LOC IBUFDS_GTE2_X0Y1 [get_cells i_clocks.ibufds_GTP_REF_CLK_1]
+
+##
+## Attribute values for GTPE2 Channel and Common instances
+##
+##
+##remove ASYNC_REG property
+##
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_310/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_30E/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_312/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_314/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_306/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg]
+
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg]
+
+##
+## Attribute Values for QUAD[0] - Channel
+##
+ ##------Comma Detection and Alignment---------
+set_property ALIGN_COMMA_DOUBLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_COMMA_ENABLE 10'b0001111111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_COMMA_WORD 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_MCOMMA_DET "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_MCOMMA_VALUE 10'b1010000011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_PCOMMA_DET "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_PCOMMA_VALUE 10'b0101111100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_MCOMMA_DETECT "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_PCOMMA_DETECT "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_VALID_COMMA_ONLY "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DMONITOR_CFG 24'h000A00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##--------------Channel Bonding--------------
+set_property CBCC_DATA_SOURCE_SEL "DECODED" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_KEEP_ALIGN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_MAX_SKEW 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_LEN 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_1 10'b0101111100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_1 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Clock Correction------------
+set_property CLK_COR_KEEP_IDLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_MAX_LAT 9.0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_MIN_LAT 7.0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_PRECEDENCE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_CORRECT_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_REPEAT_WAIT 0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_LEN 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_1 10'b0100011100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_1 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Channel PLL----------------------
+set_property RXOUT_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXOUT_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------Eyescan--------------
+set_property ES_CONTROL 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_ERRDET_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_EYE_SCAN_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_HORZ_OFFSET 12'h002 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_PMA_CFG 10'b0000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_PRESCALE 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_QUALIFIER 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_QUAL_MASK 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_SDATA_MASK 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_VERT_OFFSET 9'b010000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_DESKEW_SEQ_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_LANE_DESKEW_CFG 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_LANE_DESKEW_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property GEARBOX_MODE 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property OUTREFCLK_SEL_INV 2'b11 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PCS_PCIE_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PCS_RSVD_ATTR 48'h000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV 32'h00000333 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV2 32'h00002040 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV3 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV4 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV5 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV6 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV7 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_BIAS_CFG 16'b0000111100110011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_PREDRIVER_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Rx Elastic Buffer and Phase alignment-------------
+set_property RXBUF_ADDR_MODE "FAST" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EIDLE_HI_CNT 4'b1000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EIDLE_LO_CNT 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_BUFFER_CFG 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_CB_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_COMMAALIGN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_EIDLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_RATE_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUFRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_OVFLW 61 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_OVRD "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_UNDFLW 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_CFG 16'h0010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_LCFG 9'h020 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_TAP_CFG 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------RX driver, OOB signalling, Coupling and Eq., CDR------------
+set_property RXCDR_CFG 83'h0001107FE206021041010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDRFREQRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_FR_RESET_ON_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_HOLD_DURING_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_LOCK_CFG 6'b001001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_PH_RESET_ON_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDRPHRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOOB_CFG 7'b0000110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------RX Interface-------------------------
+set_property RX_DATA_WIDTH 16 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CLK25_DIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CM_SEL 2'b11 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CM_TRIM 4'b1010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DDI_SEL 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DEBUG_CFG 12'b000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##------------RX Decision Feedback Equalizer(DFE)-------------
+set_property RX_DEFER_RESET_BUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_OS_CFG 13'b0000010000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DISPERR_SEQ_MATCH "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------RX Gearbox---------------------------
+set_property RXGEARBOX_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXISCANRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG 14'b00001111110000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG2 5'b01010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG3 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HOLD_DURING_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_INCM_CFG 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_IPCM_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_LF_CFG 18'b000000001111110000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_LF_CFG2 5'b01010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_OSINT_CFG 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPCSRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPH_CFG 24'hC00002 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPHDLY_CFG 24'h084000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPH_MONITOR_SEL 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPMARESET_TIME 5'b00011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------PRBS Detection-----------------------
+set_property RXPRBS_ERR_LOOPBACK 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_SIG_VALID_DLY 10 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSLIDE_AUTO_WAIT 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSLIDE_MODE "off" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_XCLK_SEL "RXREC" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------RX Attributes for PCI Express/SATA/SAS----------
+set_property PD_TRANS_TIME_FROM_P2 12'h03c [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PD_TRANS_TIME_NONE_P2 8'h3c [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PD_TRANS_TIME_TO_P2 8'h64 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SAS_MAX_COM 64 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SAS_MIN_COM 36 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_BURST_SEQ_LEN 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_BURST_VAL 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_PLL_CFG VCO_3000MHZ [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_EIDLE_VAL 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_BURST 8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_INIT 21 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_WAKE 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_BURST 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_INIT 12 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_WAKE 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SHOW_REALIGN_COMMA "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TERM_RCAL_CFG 15'b100001000010000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TERM_RCAL_OVRD 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TRANS_TIME_RATE 8'h0E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TST_RSV 32'h00000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##------------TX Buffering and Phase Alignment----------------
+set_property TXBUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXBUF_RESET_ON_RATE_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------TX Interface-------------------------
+set_property TX_DATA_WIDTH 16 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DEEMPH0 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DEEMPH1 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_CFG 16'h0010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_LCFG 9'h020 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_TAP_CFG 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_CLK25_DIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##--------------TX Driver and OOB Signalling------------------
+set_property TX_EIDLE_ASSERT_DELAY 3'b110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_EIDLE_DEASSERT_DELAY 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_LOOPBACK_DRIVE_HIZ "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MAINCURSOR_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DRIVE_MODE "DIRECT" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------TX Gearbox---------------------------
+set_property TXGEARBOX_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##----------------TX Attributes for PCI Express---------------
+set_property TX_MARGIN_FULL_0 7'b1001110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_1 7'b1001001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_2 7'b1000101 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_3 7'b1000010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_4 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_0 7'b1000110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_1 7'b1000100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_2 7'b1000010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_3 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_4 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPCSRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPH_CFG 16'h0400 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPHDLY_CFG 24'h084000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPH_MONITOR_SEL 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPMARESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_RXDETECT_CFG 14'h1832 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_RXDETECT_REF 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_XCLK_SEL "TXOUT" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property UCODEER_CLR 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##---------------- JTAG Attributes ---------------
+set_property ACJTAG_DEBUG_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ACJTAG_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ACJTAG_RESET 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ADAPT_CFG0 20'h00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPMRESET_TIME 7'b0001111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_BIAS_STARTUP_DISABLE 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CFG 4'b0110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CFG1 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CM_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_GC_CFG 9'b101110010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_GC_CFG2 3'b001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG 43'h49000040E80 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG2 7'b0100000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG3 7'b0100000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG4 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG5 2'h0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG6 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- EYESCAN ---------------
+set_property ES_CLK_PHASE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV5 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- RX Phase Interpolator ---------------
+set_property RXPI_CFG0 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPI_CFG1 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPI_CFG2 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- TX Phase Interpolator ---------------
+set_property TXPI_CFG0 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG1 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG2 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG3 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG4 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG5 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_GREY_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_INVSTROBE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_PPMCLK_SEL TXUSRCLK2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_PPM_CFG 8'h00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_SYNFREQ_PPM 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property USE_PCS_CLK_PHASE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- LOOPBACK ---------------
+set_property LOOPBACK_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- OOB Signalling ---------------
+set_property RXOOB_CLK_CFG PMA [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOSCALRESET_TIME 5'b00011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOSCALRESET_TIMEOUT 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXOOB_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##---------------- PMA Attributes ---------------
+set_property CLK_COMMON_SWING 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CLKMUX_EN 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_CLKMUX_EN 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_LOOPBACK_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##---------------- RX SYNC ---------------
+set_property RXSYNC_MULTILANE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSYNC_OVRD 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSYNC_SKIP_DA 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- TX SYNC ---------------
+set_property TXSYNC_MULTILANE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXSYNC_OVRD 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXSYNC_SKIP_DA 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##
+## Attribute Values for QUAD[0] - Common
+##
+set_property BIAS_CFG 64'h0000000000050001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property COMMON_CFG 32'h00000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_CFG 27'h01F0319 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_CFG 27'h01F0319 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_DMON_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_DMON_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL_CLKOUT_CFG 8'h00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_INIT_CFG 24'h00001E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_INIT_CFG 24'h00001E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_LOCK_CFG 9'h1E8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_LOCK_CFG 9'h1E8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_FBDIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_FBDIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_FBDIV_45 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_FBDIV_45 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_REFCLK_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_REFCLK_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property RSVD_ATTR0 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property RSVD_ATTR1 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..876688bb5f03ebd31babcef8db2513601d750c40
--- /dev/null
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
@@ -0,0 +1,256 @@
+############################################################################
+# Programmable Logic placement constraints #
+############################################################################
+
+##### USB interface (bank 13) #####
+# USB_VBUS_PWRFAULT_i
+set_property PACKAGE_PIN AA19 [get_ports UsbVbusPwrFaultxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports UsbVbusPwrFaultxSI]
+
+##### PLL interface (banks 35 and 34) #####
+# PLL_2V5_CLKuWire_o
+set_property PACKAGE_PIN G8 [get_ports Pll2V5ClkuWirexCO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkuWirexCO]
+# PLL_2V5_DATAuWire_o
+set_property PACKAGE_PIN G7 [get_ports Pll2V5DatauWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5DatauWirexSO]
+# PLL_2V5_LEuWire_o
+set_property PACKAGE_PIN G6 [get_ports Pll2V5LEuWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LEuWirexSO]
+# PLL_2V5_GOE_o
+set_property PACKAGE_PIN F6 [get_ports Pll2V5GOExSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5GOExSO]
+# PLL_2V5_LD_i
+set_property PACKAGE_PIN H6 [get_ports Pll2V5LDxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LDxSI]
+# PLL_2V5_SYNC_n_o
+set_property PACKAGE_PIN H5 [get_ports Pll2V5SyncxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5SyncxSO]
+# PLL_2V5_CLKIN0_LOS_i (bank 34)
+set_property PACKAGE_PIN J3 [get_ports Pll2V5ClkIn0LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn0LOSxSI]
+# PLL_2V5_CLKIN1_LOS_i (bank 34)
+set_property PACKAGE_PIN K2 [get_ports Pll2V5ClkIn1LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
+
+##### GTP interfaces (bank 112) #####
+set_property PACKAGE_PIN U9 [get_ports GTPRefClk0PxCI]
+set_property PACKAGE_PIN V9 [get_ports GTPRefClk0NxCI]
+#set_property PACKAGE_PIN "U5" [get_ports "GTPRefClk1PxCI"]
+#set_property PACKAGE_PIN "V5" [get_ports "GTPRefClk1NxCI"]
+set_property PACKAGE_PIN Y8 [get_ports GTPFromNorthNxSI]
+set_property PACKAGE_PIN W8 [get_ports GTPFromNorthPxSI]
+set_property PACKAGE_PIN Y4 [get_ports GTPToNorthNxSO]
+set_property PACKAGE_PIN W4 [get_ports GTPToNorthPxSO]
+set_property PACKAGE_PIN AB7 [get_ports GTPFromSouthNxSI]
+set_property PACKAGE_PIN AA7 [get_ports GTPFromSouthPxSI]
+set_property PACKAGE_PIN AB3 [get_ports GTPToSouthNxSO]
+set_property PACKAGE_PIN AA3 [get_ports GTPToSouthPxSO]
+set_property PACKAGE_PIN AB9 [get_ports GTPFromEastNxSI]
+set_property PACKAGE_PIN AA9 [get_ports GTPFromEastPxSI]
+set_property PACKAGE_PIN AB5 [get_ports GTPToEastNxSO]
+set_property PACKAGE_PIN AA5 [get_ports GTPToEastPxSO]
+set_property PACKAGE_PIN Y6 [get_ports GTPFromWestNxSI]
+set_property PACKAGE_PIN W6 [get_ports GTPFromWestPxSI]
+set_property PACKAGE_PIN Y2 [get_ports GTPToWestNxSO]
+set_property PACKAGE_PIN W2 [get_ports GTPToWestPxSO]
+
+##### LVDS links towards edge connectors #####
+# North (bank 35)
+#set_property PACKAGE_PIN "E8" [get_ports "LVDS2V5North7PxSIO"]
+#set_property PACKAGE_PIN "D8" [get_ports "LVDS2V5North7NxSIO"]
+#set_property PACKAGE_PIN "D7" [get_ports "LVDS2V5North6PxSIO"]
+#set_property PACKAGE_PIN "D6" [get_ports "LVDS2V5North6NxSIO"]
+#set_property PACKAGE_PIN "C8" [get_ports "LVDS2V5North5PxSIO"]
+#set_property PACKAGE_PIN "B8" [get_ports "LVDS2V5North5NxSIO"]
+#set_property PACKAGE_PIN "B7" [get_ports "LVDS2V5North4PxSIO"]
+#set_property PACKAGE_PIN "B6" [get_ports "LVDS2V5North4NxSIO"]
+#set_property PACKAGE_PIN "A7" [get_ports "LVDS2V5North3PxSIO"]
+#set_property PACKAGE_PIN "A6" [get_ports "LVDS2V5North3NxSIO"]
+#set_property PACKAGE_PIN "A5" [get_ports "LVDS2V5North2PxSIO"]
+#set_property PACKAGE_PIN "A4" [get_ports "LVDS2V5North2NxSIO"]
+#set_property PACKAGE_PIN "B2" [get_ports "LVDS2V5North1PxSIO"]
+#set_property PACKAGE_PIN "B1" [get_ports "LVDS2V5North1NxSIO"]
+#set_property PACKAGE_PIN "A2" [get_ports "LVDS2V5North0PxSIO"]
+#set_property PACKAGE_PIN "A1" [get_ports "LVDS2V5North0NxSIO"]
+# South (bank 13)
+#set_property PACKAGE_PIN "V15" [get_ports "LVDS2V5South7PxSIO"]
+#set_property PACKAGE_PIN "W15" [get_ports "LVDS2V5South7NxSIO"]
+#set_property PACKAGE_PIN "AB13" [get_ports "LVDS2V5South6PxSIO"]
+#set_property PACKAGE_PIN "AB14" [get_ports "LVDS2V5South6NxSIO"]
+#set_property PACKAGE_PIN "V13" [get_ports "LVDS2V5South5PxSIO"]
+#set_property PACKAGE_PIN "V14" [get_ports "LVDS2V5South5NxSIO"]
+#set_property PACKAGE_PIN "Y12" [get_ports "LVDS2V5South4PxSIO"]
+#set_property PACKAGE_PIN "Y13" [get_ports "LVDS2V5South4NxSIO"]
+#set_property PACKAGE_PIN "AA12" [get_ports "LVDS2V5South3PxSIO"]
+#set_property PACKAGE_PIN "AB12" [get_ports "LVDS2V5South3NxSIO"]
+#set_property PACKAGE_PIN "W12" [get_ports "LVDS2V5South2PxSIO"]
+#set_property PACKAGE_PIN "W13" [get_ports "LVDS2V5South2NxSIO"]
+#set_property PACKAGE_PIN "AA11" [get_ports "LVDS2V5South1PxSIO"]
+#set_property PACKAGE_PIN "AB11" [get_ports "LVDS2V5South1NxSIO"]
+#set_property PACKAGE_PIN "V11" [get_ports "LVDS2V5South0PxSIO"]
+#set_property PACKAGE_PIN "W11" [get_ports "LVDS2V5South0NxSIO"]
+# East (bank 13)
+#set_property PACKAGE_PIN "V16" [get_ports "LVDS2V5East7PxSIO"]
+#set_property PACKAGE_PIN "W16" [get_ports "LVDS2V5East7NxSIO"]
+#set_property PACKAGE_PIN "W17" [get_ports "LVDS2V5East6PxSIO"]
+#set_property PACKAGE_PIN "Y17" [get_ports "LVDS2V5East6NxSIO"]
+#set_property PACKAGE_PIN "U13" [get_ports "LVDS2V5East5PxSIO"]
+#set_property PACKAGE_PIN "U14" [get_ports "LVDS2V5East5NxSIO"]
+#set_property PACKAGE_PIN "V18" [get_ports "LVDS2V5East4PxSIO"]
+#set_property PACKAGE_PIN "W18" [get_ports "LVDS2V5East4NxSIO"]
+#set_property PACKAGE_PIN "U11" [get_ports "LVDS2V5East3PxSIO"]
+#set_property PACKAGE_PIN "U12" [get_ports "LVDS2V5East3NxSIO"]
+#set_property PACKAGE_PIN "U19" [get_ports "LVDS2V5East2PxSIO"]
+#set_property PACKAGE_PIN "V19" [get_ports "LVDS2V5East2NxSIO"]
+#set_property PACKAGE_PIN "R17" [get_ports "LVDS2V5East1PxSIO"]
+#set_property PACKAGE_PIN "T17" [get_ports "LVDS2V5East1NxSIO"]
+#set_property PACKAGE_PIN "U17" [get_ports "LVDS2V5East0PxSIO"]
+#set_property PACKAGE_PIN "U18" [get_ports "LVDS2V5East0NxSIO"]
+# West (bank 35)
+#set_property PACKAGE_PIN "H4" [get_ports "LVDS2V5West7PxSIO"]
+#set_property PACKAGE_PIN "H3" [get_ports "LVDS2V5West7NxSIO"]
+#set_property PACKAGE_PIN "H1" [get_ports "LVDS2V5West6PxSIO"]
+#set_property PACKAGE_PIN "G1" [get_ports "LVDS2V5West6NxSIO"]
+#set_property PACKAGE_PIN "G3" [get_ports "LVDS2V5West5PxSIO"]
+#set_property PACKAGE_PIN "G2" [get_ports "LVDS2V5West5NxSIO"]
+#set_property PACKAGE_PIN "F2" [get_ports "LVDS2V5West4PxSIO"]
+#set_property PACKAGE_PIN "F1" [get_ports "LVDS2V5West4NxSIO"]
+#set_property PACKAGE_PIN "G4" [get_ports "LVDS2V5West3PxSIO"]
+#set_property PACKAGE_PIN "F4" [get_ports "LVDS2V5West3NxSIO"]
+#set_property PACKAGE_PIN "E2" [get_ports "LVDS2V5West2PxSIO"]
+#set_property PACKAGE_PIN "D2" [get_ports "LVDS2V5West2NxSIO"]
+#set_property PACKAGE_PIN "E4" [get_ports "LVDS2V5West1PxSIO"]
+#set_property PACKAGE_PIN "E3" [get_ports "LVDS2V5West1NxSIO"]
+#set_property PACKAGE_PIN "D1" [get_ports "LVDS2V5West0PxSIO"]
+#set_property PACKAGE_PIN "C1" [get_ports "LVDS2V5West0NxSIO"]
+
+##### LVDS links towards top-bottom connectors #####
+# Top (bank 34)
+#set_property PACKAGE_PIN "J8" [get_ports "LVDS2V5Top7PxSIO"]
+#set_property PACKAGE_PIN "K8" [get_ports "LVDS2V5Top7NxSIO"]
+#set_property PACKAGE_PIN "K7" [get_ports "LVDS2V5Top6PxSIO"]
+#set_property PACKAGE_PIN "L7" [get_ports "LVDS2V5Top6NxSIO"]
+#set_property PACKAGE_PIN "N8" [get_ports "LVDS2V5Top5PxSIO"]
+#set_property PACKAGE_PIN "P8" [get_ports "LVDS2V5Top5NxSIO"]
+#set_property PACKAGE_PIN "M8" [get_ports "LVDS2V5Top4PxSIO"]
+#set_property PACKAGE_PIN "M7" [get_ports "LVDS2V5Top4NxSIO"]
+#set_property PACKAGE_PIN "L6" [get_ports "LVDS2V5Top3PxSIO"]
+#set_property PACKAGE_PIN "M6" [get_ports "LVDS2V5Top3NxSIO"]
+#set_property PACKAGE_PIN "J7" [get_ports "LVDS2V5Top2PxSIO"]
+#set_property PACKAGE_PIN "J6" [get_ports "LVDS2V5Top2NxSIO"]
+#set_property PACKAGE_PIN "J5" [get_ports "LVDS2V5Top1PxSIO"]
+#set_property PACKAGE_PIN "K5" [get_ports "LVDS2V5Top1NxSIO"]
+#set_property PACKAGE_PIN "J2" [get_ports "LVDS2V5Top0PxSIO"]
+#set_property PACKAGE_PIN "J1" [get_ports "LVDS2V5Top0NxSIO"]
+# Bottom (bank 34)
+#set_property PACKAGE_PIN "N6" [get_ports "LVDS2V5Bottom7PxSIO"]
+#set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
+#set_property PACKAGE_PIN "P6" [get_ports "LVDS2V5Bottom6PxSIO"]
+#set_property PACKAGE_PIN "P5" [get_ports "LVDS2V5Bottom6NxSIO"]
+#set_property PACKAGE_PIN "R5" [get_ports "LVDS2V5Bottom5PxSIO"]
+#set_property PACKAGE_PIN "R4" [get_ports "LVDS2V5Bottom5NxSIO"]
+#set_property PACKAGE_PIN "R3" [get_ports "LVDS2V5Bottom4PxSIO"]
+#set_property PACKAGE_PIN "R2" [get_ports "LVDS2V5Bottom4NxSIO"]
+#set_property PACKAGE_PIN "P3" [get_ports "LVDS2V5Bottom3PxSIO"]
+#set_property PACKAGE_PIN "P2" [get_ports "LVDS2V5Bottom3NxSIO"]
+#set_property PACKAGE_PIN "N1" [get_ports "LVDS2V5Bottom2PxSIO"]
+#set_property PACKAGE_PIN "P1" [get_ports "LVDS2V5Bottom2NxSIO"]
+#set_property PACKAGE_PIN "N4" [get_ports "LVDS2V5Bottom1PxSIO"]
+#set_property PACKAGE_PIN "N3" [get_ports "LVDS2V5Bottom1NxSIO"]
+#set_property PACKAGE_PIN "M2" [get_ports "LVDS2V5Bottom0PxSIO"]
+#set_property PACKAGE_PIN "M1" [get_ports "LVDS2V5Bottom0NxSIO"]
+
+##### RGB LEDs (banks 34 and 13) #####
+# LED1_2V5_R_o (bank 34)
+set_property PACKAGE_PIN L2 [get_ports Led12V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5RxSO]
+# LED1_2V5_G_o (bank 34)
+set_property PACKAGE_PIN L1 [get_ports Led12V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5GxSO]
+# LED1_2V5_B_o (bank 34)
+set_property PACKAGE_PIN R8 [get_ports Led12V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5BxSO]
+# LED2_2V5_R_o (bank 13)
+set_property PACKAGE_PIN T16 [get_ports Led22V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5RxSO]
+# LED2_2V5_G_o (bank 13)
+set_property PACKAGE_PIN U16 [get_ports Led22V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5GxSO]
+# LED2_2V5_B_o (bank 13)
+set_property PACKAGE_PIN AA20 [get_ports Led22V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5BxSO]
+
+##### Self reset (bank 34) #####
+set_property PACKAGE_PIN H8 [get_ports SelfRstxRNO]
+set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
+
+##### Clock dedicated pins (Multi-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "D5" [get_ports "PLLClk2V5LocalPxCI"]
+#set_property PACKAGE_PIN "C4" [get_ports "PLLClk2V5LocalNxCI"]
+#set_property PACKAGE_PIN "B4" [get_ports "PLLClk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "B3" [get_ports "PLLClk2V5NorthNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "T2" [get_ports "PLLClk2V5TopxCI"]
+#set_property PACKAGE_PIN "L5" [get_ports "PLLClk2V5BottomxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "Y14" [get_ports "PLLClk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "Y15" [get_ports "PLLClk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "Y18" [get_ports "Clk2V5RecoveryPxCO"]
+#set_property PACKAGE_PIN "Y19" [get_ports "Clk2V5RecoveryNxCO"]
+
+##### Clock dedicated pins (Single-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "C6" [get_ports "Clk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "C5" [get_ports "Clk2V5NorthNxCI"]
+#set_property PACKAGE_PIN "D3" [get_ports "Clk2V5WestPxCI"]
+#set_property PACKAGE_PIN "C3" [get_ports "Clk2V5WestNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "K4" [get_ports "Clk2V5TopPxCI"]
+#set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
+#set_property PACKAGE_PIN "U2" [get_ports "Clk2V5BottomPxCI"]
+#set_property PACKAGE_PIN "U1" [get_ports "Clk2V5BottomNxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "AA16" [get_ports "Clk2V5EastPxCI"]
+#set_property PACKAGE_PIN "AA17" [get_ports "Clk2V5EastNxCI"]
+
+##### Clock outputs #####
+## Bank 35
+#set_property PACKAGE_PIN "F7" [get_ports "Clk2V5NorthPxCO"]
+#set_property PACKAGE_PIN "E7" [get_ports "Clk2V5NorthNxCO"]
+#set_property PACKAGE_PIN "F5" [get_ports "Clk2V5WestPxCO"]
+#set_property PACKAGE_PIN "E5" [get_ports "Clk2V5WestNxCO"]
+# Bank 34
+#set_property PACKAGE_PIN "P7" [get_ports "Clk2V5TopPxCO"]
+#set_property PACKAGE_PIN "R7" [get_ports "Clk2V5TopNxCO"]
+#set_property PACKAGE_PIN "M4" [get_ports "Clk2V5BottomPxCO"]
+#set_property PACKAGE_PIN "M3" [get_ports "Clk2V5BottomNxCO"]
+# Bank 13
+#set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
+#set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
+#set_property PACKAGE_PIN "AB21" [get_ports "Clk2V5EastPxCO"]
+#set_property PACKAGE_PIN "AB22" [get_ports "Clk2V5EastNxCO"]
+
+############################################################################
+# Other constraints #
+############################################################################
+
+##### Operating conditions (for XPE report) #####
+# Extended grade (as for -2 speed grade) and maximum consumption estimation
+set_operating_conditions -grade extended -process maximum
+# 4'' by 4'' PCB, no heatsink, no air flow
+set_operating_conditions -airflow 0 -heatsink none -board small
+
+
+
+
+
+
+
+
+
+
+
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..c646d10e2ccd5e104700a879f84a8d780765d6bb
--- /dev/null
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -0,0 +1,36 @@
+############################################################################
+# Timing constraints #
+############################################################################
+
+##### PS_CLK (125 MHz) #####
+create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
+
+##### GTP reference clocks (125 MHz) #####
+create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk1xC]
+
+##### Clocks from PLLs (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Local}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Bottom}]
+
+##### Clocks from neighbours (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_East}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_West}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Bottom}]
+
+
+
+
+
+
+
+
+
+
+
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/hdl/reset_delay_gen.vhd b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/reset_delay_gen.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..573ada50011993dde0c31c9609c9aee94f684c5b
--- /dev/null
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/reset_delay_gen.vhd
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: reset_delay_gen - behavioral
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Reset Delay Generator
+--
+-- Last update: 2020-10-12
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_misc.all;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+entity reset_delay_gen is
+
+ generic (
+ C_TICKS : integer := 10);
+
+ port (
+ ClkxCI : in std_ulogic;
+ PllLockedxSI : in std_ulogic;
+ ResetxRI : in std_ulogic;
+ ResetDelayedxRO : out std_ulogic);
+
+end entity reset_delay_gen;
+
+architecture behavioral of reset_delay_gen is
+
+ -- Signals
+ signal ResetDelayxRD : std_ulogic_vector((C_TICKS - 1) downto 0) := (others => '1');
+
+begin -- architecture behavioral
+
+ -- Asynchronous statements
+
+ ResetDelayedxAS : ResetDelayedxRO <= ResetDelayxRD(C_TICKS - 1);
+
+ -- Synchronous statements
+
+ ResetDelayGenxP : process (ClkxCI) is
+ begin -- process ResetDelayGenxP
+ if rising_edge(ClkxCI) then
+ if PllLockedxSI = '0' then
+ ResetDelayxRD <= (others => '1');
+ elsif PllLockedxSI = '1' then
+ ResetDelayxRD <= ResetDelayxRD((C_TICKS - 2) downto 0) & ResetxRI;
+ end if;
+ end if;
+ end process ResetDelayGenxP;
+
+end architecture behavioral;
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
index f7ca1d5869010ded3ce574f35ceb2736f6ad071b..2dd4c4ec09cdabfe17096e9826986510507df286 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_router_firmware
--
--- Last update: 2021-06-08 14:56:43
+-- Last update: 2021-06-08
--
---------------------------------------------------------------------------------
@@ -23,12 +23,1365 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library work;
+-- Aurora packages
+use work.aurora_status_pkg.all;
+use work.aurora_drp_pkg.all;
+-- Axi4 packages
+use work.axi4_pkg.all;
+-- Scalp
+use work.scalp_misc.all;
+use work.scalp_utility.all;
+--use work.scalp_sim_packets.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
entity scalp_router_firmware is
+
+ generic (
+ C_USE_IBERT : boolean := false;
+ C_DEBUG_MODE : boolean := false;
+ C_RX_FIFO_MODE : boolean := true;
+ C_SCALP_NUMBER_OF_INTERFACE : integer range 0 to 255 := 7;
+ C_SCALP_SCHEDULER_STRATEGY : string := "RR");
+
+ port (
+ -----------------------------------------------------------------------
+ -- Names defined and not described in the constraint file.
+ -----------------------------------------------------------------------
+ -- Zynq FIXED_IO
+ PSClkxCIO : inout std_logic;
+ PSSRstxRNIO : inout std_logic;
+ PSPorxSNIO : inout std_logic;
+ -- DDR interface
+ DDRClkNxCIO : inout std_logic;
+ DDRClkPxCIO : inout std_logic;
+ DDRDRstxRNIO : inout std_logic;
+ DDRCasNxSIO : inout std_logic;
+ DDRCkexSIO : inout std_logic;
+ DDRCsNxSIO : inout std_logic;
+ DDROdtxSIO : inout std_logic;
+ DDRRasNxSIO : inout std_logic;
+ DDRWexSNIO : inout std_logic;
+ DDRBankAddrxDIO : inout std_logic_vector(2 downto 0);
+ DDRAddrxDIO : inout std_logic_vector(14 downto 0);
+ DDRVrNxSIO : inout std_logic;
+ DDRVrPxSIO : inout std_logic;
+ DDRDmxDIO : inout std_logic_vector(3 downto 0);
+ DDRDqxDIO : inout std_logic_vector(31 downto 0);
+ DDRDqsNxDIO : inout std_logic_vector(3 downto 0);
+ DDRDqsPxDIO : inout std_logic_vector(3 downto 0);
+ -- MIO Interface
+ MIOxDIO : inout std_logic_vector(53 downto 0);
+ -----------------------------------------------------------------------
+ -- USB signals
+ UsbVbusPwrFaultxSI : in std_logic;
+ -- PLL interface
+ Pll2V5ClkuWirexCO : out std_logic; -- Clock (from SPI1_SCLK)
+ Pll2V5DatauWirexSO : out std_logic; -- Data (from SPI1_MOSI)
+ Pll2V5LEuWirexSO : out std_logic; -- Latch enable (from SPI1_SS)
+ Pll2V5GOExSO : out std_logic; -- Global Output Enable
+ Pll2V5LDxSI : in std_logic; -- Lock Detect
+ Pll2V5SyncxSO : out std_logic; -- Sync
+ Pll2V5ClkIn0LOSxSI : in std_logic; -- FPGA clock Loss of Sync
+ Pll2V5ClkIn1LOSxSI : in std_logic; -- External oscillator Loss of Sync
+ -- GTP interfaces
+ -- Clocks
+ GTPRefClk0PxCI : in std_logic;
+ GTPRefClk0NxCI : in std_logic;
+ GTPRefClk1PxCI : in std_logic;
+ GTPRefClk1NxCI : in std_logic;
+ -- North
+ GTPFromNorthPxSI : in std_logic;
+ GTPFromNorthNxSI : in std_logic;
+ GTPToNorthPxSO : out std_logic;
+ GTPToNorthNxSO : out std_logic;
+ -- East
+ GTPFromEastPxSI : in std_logic;
+ GTPFromEastNxSI : in std_logic;
+ GTPToEastPxSO : out std_logic;
+ GTPToEastNxSO : out std_logic;
+ -- South
+ GTPFromSouthPxSI : in std_logic;
+ GTPFromSouthNxSI : in std_logic;
+ GTPToSouthPxSO : out std_logic;
+ GTPToSouthNxSO : out std_logic;
+ -- West
+ GTPFromWestPxSI : in std_logic;
+ GTPFromWestNxSI : in std_logic;
+ GTPToWestPxSO : out std_logic;
+ GTPToWestNxSO : out std_logic;
+ -- LVDS links towards edge connectors
+ -- North
+ -- LVDS2V5North0PxSIO : inout std_logic;
+ -- LVDS2V5North0NxSIO : inout std_logic;
+ -- LVDS2V5North1PxSIO : inout std_logic;
+ -- LVDS2V5North1NxSIO : inout std_logic;
+ -- LVDS2V5North2PxSIO : inout std_logic;
+ -- LVDS2V5North2NxSIO : inout std_logic;
+ -- LVDS2V5North3PxSIO : inout std_logic;
+ -- LVDS2V5North3NxSIO : inout std_logic;
+ -- LVDS2V5North4PxSIO : inout std_logic;
+ -- LVDS2V5North4NxSIO : inout std_logic;
+ -- LVDS2V5North5PxSIO : inout std_logic;
+ -- LVDS2V5North5NxSIO : inout std_logic;
+ -- LVDS2V5North6PxSIO : inout std_logic;
+ -- LVDS2V5North6NxSIO : inout std_logic;
+ -- LVDS2V5North7PxSIO : inout std_logic;
+ -- LVDS2V5North7NxSIO : inout std_logic;
+ -- South
+ -- LVDS2V5South0PxSIO : inout std_logic;
+ -- LVDS2V5South0NxSIO : inout std_logic;
+ -- LVDS2V5South1PxSIO : inout std_logic;
+ -- LVDS2V5South1NxSIO : inout std_logic;
+ -- LVDS2V5South2PxSIO : inout std_logic;
+ -- LVDS2V5South2NxSIO : inout std_logic;
+ -- LVDS2V5South3PxSIO : inout std_logic;
+ -- LVDS2V5South3NxSIO : inout std_logic;
+ -- LVDS2V5South4PxSIO : inout std_logic;
+ -- LVDS2V5South4NxSIO : inout std_logic;
+ -- LVDS2V5South5PxSIO : inout std_logic;
+ -- LVDS2V5South5NxSIO : inout std_logic;
+ -- LVDS2V5South6PxSIO : inout std_logic;
+ -- LVDS2V5South6NxSIO : inout std_logic;
+ -- LVDS2V5South7PxSIO : inout std_logic;
+ -- LVDS2V5South7NxSIO : inout std_logic;
+ -- East
+ -- LVDS2V5East0PxSIO : inout std_logic;
+ -- LVDS2V5East0NxSIO : inout std_logic;
+ -- LVDS2V5East1PxSIO : inout std_logic;
+ -- LVDS2V5East1NxSIO : inout std_logic;
+ -- LVDS2V5East2PxSIO : inout std_logic;
+ -- LVDS2V5East2NxSIO : inout std_logic;
+ -- LVDS2V5East3PxSIO : inout std_logic;
+ -- LVDS2V5East3NxSIO : inout std_logic;
+ -- LVDS2V5East4PxSIO : inout std_logic;
+ -- LVDS2V5East4NxSIO : inout std_logic;
+ -- LVDS2V5East5PxSIO : inout std_logic;
+ -- LVDS2V5East5NxSIO : inout std_logic;
+ -- LVDS2V5East6PxSIO : inout std_logic;
+ -- LVDS2V5East6NxSIO : inout std_logic;
+ -- LVDS2V5East7PxSIO : inout std_logic;
+ -- LVDS2V5East7NxSIO : inout std_logic;
+ -- West
+ -- LVDS2V5West0PxSIO : inout std_logic;
+ -- LVDS2V5West0NxSIO : inout std_logic;
+ -- LVDS2V5West1PxSIO : inout std_logic;
+ -- LVDS2V5West1NxSIO : inout std_logic;
+ -- LVDS2V5West2PxSIO : inout std_logic;
+ -- LVDS2V5West2NxSIO : inout std_logic;
+ -- LVDS2V5West3PxSIO : inout std_logic;
+ -- LVDS2V5West3NxSIO : inout std_logic;
+ -- LVDS2V5West4PxSIO : inout std_logic;
+ -- LVDS2V5West4NxSIO : inout std_logic;
+ -- LVDS2V5West5PxSIO : inout std_logic;
+ -- LVDS2V5West5NxSIO : inout std_logic;
+ -- LVDS2V5West6PxSIO : inout std_logic;
+ -- LVDS2V5West6NxSIO : inout std_logic;
+ -- LVDS2V5West7PxSIO : inout std_logic;
+ -- LVDS2V5West7NxSIO : inout std_logic;
+ -- LVDS links towards top-bottom connectors
+ -- Top
+ -- LVDS2V5Top0PxSIO : inout std_logic;
+ -- LVDS2V5Top0NxSIO : inout std_logic;
+ -- LVDS2V5Top1PxSIO : inout std_logic;
+ -- LVDS2V5Top1NxSIO : inout std_logic;
+ -- LVDS2V5Top2PxSIO : inout std_logic;
+ -- LVDS2V5Top2NxSIO : inout std_logic;
+ -- LVDS2V5Top3PxSIO : inout std_logic;
+ -- LVDS2V5Top3NxSIO : inout std_logic;
+ -- LVDS2V5Top4PxSIO : inout std_logic;
+ -- LVDS2V5Top4NxSIO : inout std_logic;
+ -- LVDS2V5Top5PxSIO : inout std_logic;
+ -- LVDS2V5Top5NxSIO : inout std_logic;
+ -- LVDS2V5Top6PxSIO : inout std_logic;
+ -- LVDS2V5Top6NxSIO : inout std_logic;
+ -- LVDS2V5Top7PxSIO : inout std_logic;
+ -- LVDS2V5Top7NxSIO : inout std_logic;
+ -- Bottom
+ -- LVDS2V5Bottom0PxSIO : inout std_logic;
+ -- LVDS2V5Bottom0NxSIO : inout std_logic;
+ -- LVDS2V5Bottom1PxSIO : inout std_logic;
+ -- LVDS2V5Bottom1NxSIO : inout std_logic;
+ -- LVDS2V5Bottom2PxSIO : inout std_logic;
+ -- LVDS2V5Bottom2NxSIO : inout std_logic;
+ -- LVDS2V5Bottom3PxSIO : inout std_logic;
+ -- LVDS2V5Bottom3NxSIO : inout std_logic;
+ -- LVDS2V5Bottom4PxSIO : inout std_logic;
+ -- LVDS2V5Bottom4NxSIO : inout std_logic;
+ -- LVDS2V5Bottom5PxSIO : inout std_logic;
+ -- LVDS2V5Bottom5NxSIO : inout std_logic;
+ -- LVDS2V5Bottom6PxSIO : inout std_logic;
+ -- LVDS2V5Bottom6NxSIO : inout std_logic;
+ -- LVDS2V5Bottom7PxSIO : inout std_logic;
+ -- LVDS2V5Bottom7NxSIO : inout std_logic;
+ -- RGB LEDs
+ Led12V5RxSO : out std_logic;
+ Led12V5GxSO : out std_logic;
+ Led12V5BxSO : out std_logic;
+ Led22V5RxSO : out std_logic;
+ Led22V5GxSO : out std_logic;
+ Led22V5BxSO : out std_logic;
+ -- Self reset (connected to PS_SRSTB)
+ SelfRstxRNO : out std_logic);
+ -- Clocks from PLLs (connected to MRCC pins)
+ -- Local
+ -- PLLClk2V5LocalPxCI : in std_logic;
+ -- PLLClk2V5LocalNxCI : in std_logic;
+ -- -- North
+ -- PLLClk2V5NorthPxCI : in std_logic;
+ -- PLLClk2V5NorthNxCI : in std_logic;
+ -- -- South
+ -- PLLClk2V5SouthPxCI : in std_logic;
+ -- PLLClk2V5SouthNxCI : in std_logic;
+ -- -- Top
+ -- PLLClk2V5TopxCI : in std_logic; -- Single-ended
+ -- -- Bottom
+ -- PLLClk2V5BottomxCI : in std_logic; -- Single-ended
+ -- -- Clocks to/from neighbours
+ -- -- North
+ -- Clk2V5NorthPxCI : in std_logic;
+ -- Clk2V5NorthNxCI : in std_logic;
+ -- Clk2V5NorthPxCO : out std_logic;
+ -- Clk2V5NorthNxCO : out std_logic;
+ -- -- South
+ -- Clk2V5SouthPxCI : in std_logic;
+ -- Clk2V5SouthNxCI : in std_logic;
+ -- Clk2V5SouthPxCO : out std_logic;
+ -- Clk2V5SouthNxCO : out std_logic;
+ -- -- East
+ -- Clk2V5EastPxCI : in std_logic;
+ -- Clk2V5EastNxCI : in std_logic;
+ -- Clk2V5EastPxCO : out std_logic;
+ -- Clk2V5EastNxCO : out std_logic;
+ -- -- West
+ -- Clk2V5WestPxCI : in std_logic;
+ -- Clk2V5WestNxCI : in std_logic;
+ -- Clk2V5WestPxCO : out std_logic;
+ -- Clk2V5WestNxCO : out std_logic;
+ -- -- Top
+ -- Clk2V5TopPxCI : in std_logic;
+ -- Clk2V5TopNxCI : in std_logic;
+ -- Clk2V5TopPxCO : out std_logic;
+ -- Clk2V5TopNxCO : out std_logic;
+ -- -- Bottom
+ -- Clk2V5BottomPxCI : in std_logic;
+ -- Clk2V5BottomNxCI : in std_logic;
+ -- Clk2V5BottomPxCO : out std_logic;
+ -- Clk2V5BottomNxCO : out std_logic;
+ -- -- Recovery
+ -- Clk2V5RecoveryPxCO : out std_logic;
+ -- Clk2V5RecoveryNxCO : out std_logic);
+
end scalp_router_firmware;
architecture arch of scalp_router_firmware is
+ -- Constantes
+ -- constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
+ constant C_AXI_ADDR_SIZE : integer range 0 to 32 := 12;
+
+ component scalp_aurora_phy is
+ generic (
+ C_DEBUG_MODE : boolean;
+ C_RX_FIFO_MODE : boolean);
+ port (
+ GTRefClkxCI : in t_gt_ref_slave_clk;
+ AuroraClkxCI : in t_aurora_slave_clk;
+ AuroraClkxCO : out t_aurora_master_clk;
+ AuroraResetxRI : in t_aurora_slave_reset;
+ AuroraResetxRO : out t_aurora_master_link_reset;
+ RXResetxRI : in t_rx_reset;
+ RXFifoResetDonexDO : out t_rx_fifo_reset_done;
+ GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
+ NorthRXM2SxDO : out t_axi4m2s;
+ NorthRXS2MxDI : in t_axi4s2m;
+ NorthTXM2SxDI : in t_axi4m2s;
+ NorthTXS2MxDO : out t_axi4s2m;
+ EastRXM2SxDO : out t_axi4m2s;
+ EastRXS2MxDI : in t_axi4s2m;
+ EastTXM2SxDI : in t_axi4m2s;
+ EastTXS2MxDO : out t_axi4s2m;
+ SouthRXM2SxDO : out t_axi4m2s;
+ SouthRXS2MxDI : in t_axi4s2m;
+ SouthTXM2SxDI : in t_axi4m2s;
+ SouthTXS2MxDO : out t_axi4s2m;
+ WestRXM2SxDO : out t_axi4m2s;
+ WestRXS2MxDI : in t_axi4s2m;
+ WestTXM2SxDI : in t_axi4m2s;
+ WestTXS2MxDO : out t_axi4s2m;
+ NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ NorthRXNFCM2SxDO : out t_axi4nfcm2s;
+ NorthTXNFCM2SxDI : in t_axi4nfcm2s;
+ NorthTXNFCS2MxDO : out t_axi4nfcs2m;
+ EastRXNFCM2SxDO : out t_axi4nfcm2s;
+ EastTXNFCM2SxDI : in t_axi4nfcm2s;
+ EastTXNFCS2MxDO : out t_axi4nfcs2m;
+ SouthRXNFCM2SxDO : out t_axi4nfcm2s;
+ SouthTXNFCM2SxDI : in t_axi4nfcm2s;
+ SouthTXNFCS2mxDO : out t_axi4nfcs2m;
+ WestRXNFCM2SxDO : out t_axi4nfcm2s;
+ WestTXNFCM2SxDI : in t_axi4nfcm2s;
+ WestTXNFCS2MxDO : out t_axi4nfcs2m;
+ AuroraCtrlxDI : in t_aurora_control;
+ AuroraStatusxDO : out t_aurora_status;
+ AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
+ AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0);
+ NorthRXFifoStatusxDO : out t_axi4fifo_status;
+ EastRXFifoStatusxDO : out t_axi4fifo_status;
+ SouthRXFifoStatusxDO : out t_axi4fifo_status;
+ WestRXFifoStatusxDO : out t_axi4fifo_status;
+ AxisFifoErrorxDO : out t_axi4fifo_error);
+ end component scalp_aurora_phy;
+
+ -- Signals
+ -- Clocks
+ -- Processing system clock
+ signal PSSysClkxC : std_logic := '0';
+ -- GTP Clocks
+ -- signal GTPRefClk0xC : std_logic := '0';
+ -- signal GTPRefClk1xC : std_logic := '0';
+ signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ -- Resets
+ -- Processing system reset
+ signal PSSysResetxR : std_logic := '0';
+ -- Scalp Aurora Phy
+ signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
+ signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
+ signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
+ signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
+ signal RXResetxR : t_rx_reset := C_NO_RX_RESET;
+ signal RXFifoResetDonexD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal RXFifoResetDoneDelayedxD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
+ signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
+ signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
+ signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal NorthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal EastRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal SouthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal WestRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal AxisFifoErrorxD : t_axi4fifo_error := C_NO_AXI4_FIFO_ERROR;
+ -- Scalp Router
+ signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ -- signal ScalpRouterReadyxD : t_scalp_router_ready := C_NO_SCALP_ROUTER_READY;
+ -- Scalp Axi Lite interface and IRQ
+ signal ScalpPacketWriteDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal ScalpPacketReadDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal ScalpPacketCtrlxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal ScalpPacketStatusxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RXRdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RXWrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal TXRdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal TXWrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal LocNetAddrVectxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal TXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal TXFifoRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal TXFifoRXS2MxS : t_axi4s2m := C_NO_AXI4_S2M;
+ signal RXFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal RXFifoTXS2MxS : t_axi4s2m := C_NO_AXI4_S2M;
+ -- Zynq Reg Bank
+ -- type t_status_send_word is (E_IDLE, E_SEND);
+
+ type t_tx_fifo_wr_data_states is (E_WR_IDLE, E_WR_H0, E_WR_H1, E_WR_H2, E_WR_PLD, E_WR_NEXT);
+ type t_rx_fifo_rd_data_states is (E_RD_IDLE, E_RD_WORD, E_RD_NEXT);
+
+ constant C_WR_VALID : integer range 0 to 255 := 0;
+ constant C_WR_LAST : integer range 0 to 255 := 1;
+ constant C_WR_READY : integer range 0 to 255 := 2;
+ constant C_WR_NEXT : integer range 0 to 255 := 3;
+ constant C_RESET_ALL_FIFO : integer range 0 to 255 := 4;
+ constant C_WR_H0 : integer range 0 to 255 := 5;
+ constant C_WR_H1 : integer range 0 to 255 := 6;
+ constant C_WR_H2 : integer range 0 to 255 := 7;
+ constant C_WR_PLD : integer range 0 to 255 := 8;
+ constant C_WR_NEW_PACKET : integer range 0 to 255 := 9;
+ constant C_RD_NEXT : integer range 0 to 255 := 10;
+ constant C_RD_NEW_PACKET : integer range 0 to 255 := 11;
+ --
+ constant C_RD_VALID : integer range 0 to 255 := 0;
+ constant C_RD_LAST : integer range 0 to 255 := 1;
+ constant C_TX_PROG_FULL : integer range 0 to 255 := 2;
+ constant C_RX_PROG_FULL : integer range 0 to 255 := 3;
+ constant C_RD_WAIT_NEXT : integer range 0 to 255 := 4;
+
+ signal TXFifoWrDataStatexD : t_tx_fifo_wr_data_states := E_WR_IDLE;
+ signal TXFifoWrDataStateNextxD : t_tx_fifo_wr_data_states := E_WR_IDLE;
+ signal RXFifoRdDataStatexD : t_rx_fifo_rd_data_states := E_RD_IDLE;
+ signal RXFifoRdDataStateNextxD : t_rx_fifo_rd_data_states := E_RD_IDLE;
+
+ -- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- --
+ -- signal NorthNativeSlavexD : t_native_fifo_slave;
+ -- signal NorthNativeMasterxD : t_native_fifo_master;
+ -- signal EastNativeSlavexD : t_native_fifo_slave;
+ -- signal EastNativeMasterxD : t_native_fifo_master;
+ -- signal SouthNativeSlavexD : t_native_fifo_slave;
+ -- signal SouthNativeMasterxD : t_native_fifo_master;
+ -- signal WestNativeSlavexD : t_native_fifo_slave;
+ -- signal WestNativeMasterxD : t_native_fifo_master;
+ --
+ -- signal InterruptRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal InterruptRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- North
+ -- signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- East
+ -- signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- South
+ -- signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- West
+ -- signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- Debug
+ -- signal CntRstxR : std_ulogic := '0';
+ signal ClkEnxS : std_ulogic := '0';
+ signal NorthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal NorthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal EastDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal EastDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal SouthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal SouthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal WestDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal WestDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ --
+ signal DebugCounterResetxR : t_if_common_reset := C_NO_IF_COMMON_RESET;
+ signal DebugRXFifoResetxR : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
+ signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ -- Clocks
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
+ -- Scalp Router
+ -- attribute mark_debug of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute mark_debug of WestRXS2MxD : signal is "true";
+ -- attribute keep of WestRXS2MxD : signal is "true";
+ -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
+ -- attribute keep of TXAxism2sVectorxD : signal is "true";
+ -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of TXAxiss2mVectorxD : signal is "true";
+ -- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
+ -- attribute keep of RXAxism2sVectorxD : signal is "true";
+ -- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of RXAxiss2mVectorxD : signal is "true";
+ -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
+ -- attribute keep of TXAxism2sVectorxD : signal is "true";
+ -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of TXAxiss2mVectorxD : signal is "true";
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+
begin
+ ProcessingSystemxB : block is
+ begin -- block ProcessingSystemxB
+
+ ZynqxI : entity work.scalp_zynqps_wrapper
+ port map (
+ -- Processor interface
+ FIXED_IO_ps_clk => PSClkxCIO,
+ FIXED_IO_ps_porb => PSPorxSNIO,
+ FIXED_IO_ps_srstb => PSSRstxRNIO,
+ FclkClk0xCO => PSSysClkxC,
+ FclkReset0xRO => PSSysResetxR,
+ -- DDR interface
+ DDR_addr => DDRAddrxDIO,
+ DDR_ba => DDRBankAddrxDIO,
+ DDR_cas_n => DDRCasNxSIO,
+ DDR_ck_n => DDRClkNxCIO,
+ DDR_ck_p => DDRClkPxCIO,
+ DDR_cke => DDRCkexSIO,
+ DDR_cs_n => DDRCsNxSIO,
+ DDR_dm => DDRDmxDIO,
+ DDR_dq => DDRDqxDIO,
+ DDR_dqs_n => DDRDqsNxDIO,
+ DDR_dqs_p => DDRDqsPxDIO,
+ DDR_odt => DDROdtxSIO,
+ DDR_ras_n => DDRRasNxSIO,
+ DDR_reset_n => DDRDRstxRNIO,
+ DDR_we_n => DDRWexSNIO,
+ FIXED_IO_ddr_vrn => DDRVrNxSIO,
+ FIXED_IO_ddr_vrp => DDRVrPxSIO,
+ -- USB interface
+ Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
+ -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+ -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+ Spi1MOSIxSO => Pll2V5DatauWirexSO,
+ Spi1SSxSO => Pll2V5LEuWirexSO,
+ Spi1SclkxCO => Pll2V5ClkuWirexCO,
+ -- MIO
+ FIXED_IO_mio => MIOxDIO,
+ -- Scalp Axi Lite interface and IRQ
+ Irq0xDI => (others => '0'),
+ ScalpPacketWriteDataxDO => ScalpPacketWriteDataxD,
+ ScalpPacketReadDataxDI => ScalpPacketReadDataxD,
+ ScalpPacketCtrlxDO => ScalpPacketCtrlxD,
+ ScalpPacketStatusxDI => ScalpPacketStatusxD,
+ RXRdDataCntxDI => RXRdDataCntxD,
+ RXWrDataCntxDI => RXWrDataCntxD,
+ TXRdDataCntxDI => TXRdDataCntxD,
+ TXWrDataCntxDI => TXWrDataCntxD,
+ LocNetAddrxDO => LocNetAddrVectxD,
+ RgbLedsCtrlPortxDO => open);
+
+ end block ProcessingSystemxB;
+
+ ProgrammableLogicxB : block is
+ begin -- block ProgrammableLogicxB
+
+ InputClocksxB : block is
+ begin -- block InputClocksxB
+
+ GTPRefClk0PxAS : GTRefClk0DiffxC.ClkPxC <= GTPRefClk0PxCI;
+ GTPRefClk0NxAS : GTRefClk0DiffxC.ClkNxC <= GTPRefClk0NxCI;
+ -- GTPRefClk1PxAS : GTRefClk0DiffxC.ClkPxC <= GTPRefClk1PxCI;
+ -- GTPRefClk1NxAS : GTRefClk0DiffxC.ClkNxC <= GTPRefClk1NxCI;
+
+ -- GTP Clocks buffers
+ IBufDSGTPRefClk0xI : IBUFDS_GTE2
+ port map (
+ I => GTRefClk0DiffxC.ClkPxC,
+ IB => GTRefClk0DiffxC.ClkNxC,
+ CEB => '0',
+ O => GTRefClk0xC.GTRefClkxC,
+ ODIV2 => open);
+
+ -- IBufDSGTPRefClk1xI : IBUFDS_GTE2
+ -- port map (
+ -- I => GTRefClk0DiffxC.ClkPxC,
+ -- IB => GTRefClk0DiffxC.ClkNxC,
+ -- CEB => '0',
+ -- O => GTRefClk1xCGTRefClkxC,
+ -- ODIV2 => open);
+
+ end block InputClocksxB;
+
+ PllClocksxB : block is
+
+ constant C_AURORA_RST_DLY_TICKS : integer := 25;
+ constant C_GT_RST_DLY_TICKS : integer := 625;
+
+ signal PllLockedxS : std_ulogic := '0';
+
+ begin -- block PllClocksxB
+
+ ScalpAuroraPllxI : entity work.scalp_aurora_clk
+ port map (
+ -- Clock out ports
+ InitClkxCO => AuroraClkSlavexC.InitClkxC,
+ DrpClkxCO => AuroraClkSlavexC.DrpClkxC,
+ -- Status and control signals
+ reset => PSSysResetxR,
+ PllLockedxSO => PllLockedxS,
+ -- Clock in ports
+ PSSysClkxCI => PSSysClkxC);
+
+ AuroraRstDlyxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_AURORA_RST_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkSlavexC.InitClkxC,
+ PllLockedxSI => PllLockedxS,
+ ResetxRI => PSSysResetxR,
+ ResetDelayedxRO => AuroraResetSlavexR.ResetxR);
+
+ GTRstDlyxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_GT_RST_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkSlavexC.InitClkxC,
+ PllLockedxSI => PllLockedxS,
+ ResetxRI => PSSysResetxR,
+ ResetDelayedxRO => AuroraResetSlavexR.GTResetxR);
+
+ end block PllClocksxB;
+
+ GTPhyxB : block is
+
+ constant C_RX_FIFO_RST_DONE_DLY_TICKS : integer := 100;
+
+ begin -- block GTPhyxB
+
+ -- GTP
+ GTPFromNorthPxAS : GTPFromNorthxD.RXPxD(0) <= GTPFromNorthPxSI;
+ GTPFromNorthNxAS : GTPFromNorthxD.RXNxD(0) <= GTPFromNorthNxSI;
+ GTPToNorthPxAS : GTPToNorthPxSO <= GTPToNorthxD.TXPxD(0);
+ GTPToNorthNxAS : GTPToNorthNxSO <= GTPToNorthxD.TXNxD(0);
+ GTPFromEastPxAS : GTPFromEastxD.RXPxD(0) <= GTPFromEastPxSI;
+ GTPFromEastNxAS : GTPFromEastxD.RXNxD(0) <= GTPFromEastNxSI;
+ GTPToEastPxAS : GTPToEastPxSO <= GTPToEastxD.TXPxD(0);
+ GTPToEastNxAS : GTPToEastNxSO <= GTPToEastxD.TXNxD(0);
+ GTPFromSouthPxAS : GTPFromSouthxD.RXPxD(0) <= GTPFromSouthPxSI;
+ GTPFromSouthNxAS : GTPFromSouthxD.RXNxD(0) <= GTPFromSouthNxSI;
+ GTPToSouthPxAS : GTPToSouthPxSO <= GTPToSouthxD.TXPxD(0);
+ GTPToSouthNxAS : GTPToSouthNxSO <= GTPToSouthxD.TXNxD(0);
+ GTPFromWestPxAS : GTPFromWestxD.RXPxD(0) <= GTPFromWestPxSI;
+ GTPFromWestNxAS : GTPFromWestxD.RXNxD(0) <= GTPFromWestNxSI;
+ GTPToWestPxAS : GTPToWestPxSO <= GTPToWestxD.TXPxD(0);
+ GTPToWestNxAS : GTPToWestNxSO <= GTPToWestxD.TXNxD(0);
+
+ CtrlxB : block is
+ begin -- block CtrlxB
+
+ PowerDownxAS : AuroraCtrlxD.PowerDownxS <= '0';
+ LoopbackxAS : AuroraCtrlxD.LoopbackxD <= (others => '0');
+
+ end block CtrlxB;
+
+ ScalpAuroraPhyxI : entity work.scalp_aurora_phy
+ generic map (
+ C_DEBUG_MODE => C_DEBUG_MODE,
+ C_RX_FIFO_MODE => C_RX_FIFO_MODE,
+ C_RX_FIFO_RST_DONE_DLY_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
+ port map (
+ -- Clocks
+ -- GTP Ref Clocks
+ GTRefClkxCI => GTRefClk0xC,
+ -- Aurora System and GTP Clocks
+ AuroraClkxCI => AuroraClkSlavexC,
+ AuroraClkxCO => AuroraClkMasterxC,
+ -- Reset
+ -- Aurora Reset
+ AuroraResetxRI => AuroraResetSlavexR,
+ AuroraResetxRO => AuroraResetMasterLinkxR,
+ -- RX Fifo and Back Pressure Reset
+ RXResetxRI => RXResetxR,
+ RXFifoResetDonexDO => RXFifoResetDonexD,
+ RXFifoResetDoneDelayedxDO => RXFifoResetDoneDelayedxD,
+ -- Back Pressure Reset
+ -- GTP Serial IO
+ -- North
+ GTPFromNorthxDI => GTPFromNorthxD,
+ GTPToNorthxDO => GTPToNorthxD,
+ -- East
+ GTPFromEastxDI => GTPFromEastxD,
+ GTPToEastxDO => GTPToEastxD,
+ -- South
+ GTPFromSouthxDI => GTPFromSouthxD,
+ GTPToSouthxDO => GTPToSouthxD,
+ -- West
+ GTPFromWestxDI => GTPFromWestxD,
+ GTPToWestxDO => GTPToWestxD,
+ -- Axi4 Framing Interface
+ -- North
+ NorthRXM2SxDO => NorthRXM2SxD,
+ NorthRXS2MxDI => NorthRXS2MxD,
+ NorthTXM2SxDI => NorthTXM2SxD,
+ NorthTXS2MxDO => NorthTXS2MxD,
+ -- East
+ EastRXM2SxDO => EastRXM2SxD,
+ EastRXS2MxDI => EastRXS2MxD,
+ EastTXM2SxDI => EastTXM2SxD,
+ EastTXS2MxDO => EastTXS2MxD,
+ -- South
+ SouthRXM2SxDO => SouthRXM2SxD,
+ SouthRXS2MxDI => SouthRXS2MxD,
+ SouthTXM2SxDI => SouthTXM2SxD,
+ SouthTXS2MxDO => SouthTXS2MxD,
+ -- West
+ WestRXM2SxDO => WestRXM2SxD,
+ WestRXS2MxDI => WestRXS2MxD,
+ WestTXM2SxDI => WestTXM2SxD,
+ WestTXS2MxDO => WestTXS2MxD,
+ -- Axi4 Framing UFC Interface
+ -- North
+ NorthRXUFCM2SxDO => NorthRXUFCM2SxD,
+ NorthTXUFCM2SxDI => NorthTXUFCM2SxD,
+ NorthTXUFCS2MxDO => NorthTXUFCS2MxD,
+ -- East
+ EastRXUFCM2SxDO => EastRXUFCM2SxD,
+ EastTXUFCM2SxDI => EastTXUFCM2SxD,
+ EastTXUFCS2MxDO => EastTXUFCS2MxD,
+ -- South
+ SouthRXUFCM2SxDO => SouthRXUFCM2SxD,
+ SouthTXUFCM2SxDI => SouthTXUFCM2SxD,
+ SouthTXUFCS2MxDO => SouthTXUFCS2MxD,
+ -- West
+ WestRXUFCM2SxDO => WestRXUFCM2SxD,
+ WestTXUFCM2SxDI => WestTXUFCM2SxD,
+ WestTXUFCS2MxDO => WestTXUFCS2MxD,
+ -- Axi4 Framing NFC Interface
+ -- The NFC interface is not available when the
+ -- constant C_RX_FIFO_MODE is set to TRUE.
+ -- North
+ NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
+ NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
+ NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
+ -- East
+ EastRXNFCM2SxDO => EastRXNFCM2SxD,
+ EastTXNFCM2SxDI => EastTXNFCM2SxD,
+ EastTXNFCS2MxDO => EastTXNFCS2MxD,
+ -- South
+ SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
+ SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
+ SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
+ -- West
+ WestRXNFCM2SxDO => WestRXNFCM2SxD,
+ WestTXNFCM2SxDI => WestTXNFCM2SxD,
+ WestTXNFCS2MxDO => WestTXNFCS2MxD,
+ -- Aurora Ctrl + Status
+ AuroraCtrlxDI => AuroraCtrlxD,
+ AuroraStatusxDO => AuroraStatusxD,
+ -- DRP Port
+ AuroraDRPM2SxDI => AuroraDRPM2SxD,
+ AuroraDRPS2MxDO => AuroraDRPS2MxD,
+ -- RX Fifo Status
+ -- North
+ NorthRXFifoStatusxDO => NorthRXFifoStatusxD,
+ -- East
+ EastRXFifoStatusxDO => EastRXFifoStatusxD,
+ -- South
+ SouthRXFifoStatusxDO => SouthRXFifoStatusxD,
+ -- West
+ WestRXFifoStatusxDO => WestRXFifoStatusxD,
+ -- Axis Fifo Error
+ AxisFifoErrorxDO => AxisFifoErrorxD);
+
+ end block GTPhyxB;
+
+ NetworkLayerxB : block is
+
+ constant C_SCALP_PACKET_PAYLOAD_SIZE : integer range 1 to C_SCALP_PACKET_LENGTH_RANGE_VALUE := 8;
+ constant C_SCALP_RANDOM_READY : boolean := false;
+ ---------------------------------------------------------------------------
+ -- Scalp Packets
+ ---------------------------------------------------------------------------
+
+ constant C_SCALP_PACKET_NET_ADDR_110 : t_scalp_netaddr
+ := (XxD => 1, YxD => 1, ZxD => 0);
+ constant C_SCALP_PACKET_NET_ADDR_210 : t_scalp_netaddr
+ := (XxD => 2, YxD => 1, ZxD => 0);
+ ---------------------------------------------------------------------------
+ -- Scalp Packet Headers
+ ---------------------------------------------------------------------------
+ constant C_SP_HEADER_NULL : t_scalp_packet_header := C_NO_SCALP_PACKET_HEADER;
+ constant C_SP_HEADER_110_TO_210 : t_scalp_packet_header
+ := (DstAddrxD => C_SCALP_PACKET_NET_ADDR_210,
+ SrcAddrxD => C_SCALP_PACKET_NET_ADDR_110,
+ TypexD => 1,
+ LengthxD => C_SCALP_PACKET_PAYLOAD_SIZE);
+ ---------------------------------------------------------------------------
+ -- Scalp Packet Payloads
+ ---------------------------------------------------------------------------
+ constant C_SP_PAYLOAD_NULL : t_scalp_packet_payload(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))
+ := (0 => C_NO_SCALP_PACKET_WORD,
+ 1 => C_NO_SCALP_PACKET_WORD,
+ 2 => C_NO_SCALP_PACKET_WORD,
+ 3 => C_NO_SCALP_PACKET_WORD,
+ 4 => C_NO_SCALP_PACKET_WORD,
+ 5 => C_NO_SCALP_PACKET_WORD,
+ 6 => C_NO_SCALP_PACKET_WORD,
+ 7 => C_NO_SCALP_PACKET_WORD);
+ constant C_SP_PAYLOAD_0 : t_scalp_packet_payload(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))
+ := (0 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0abbccdd#, (C_BYTE_SIZE * 4))),
+ IdxD => 0),
+ 1 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0bccddee#, (C_BYTE_SIZE * 4))),
+ IdxD => 1),
+ 2 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0cddeeff#, (C_BYTE_SIZE * 4))),
+ IdxD => 2),
+ 3 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0deeff11#, (C_BYTE_SIZE * 4))),
+ IdxD => 3),
+ 4 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0eff1122#, (C_BYTE_SIZE * 4))),
+ IdxD => 4),
+ 5 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0f112233#, (C_BYTE_SIZE * 4))),
+ IdxD => 5),
+ 6 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#01223344#, (C_BYTE_SIZE * 4))),
+ IdxD => 6),
+ 7 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#02334455#, (C_BYTE_SIZE * 4))),
+ IdxD => 7));
+
+ -- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
+
+ type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID_0, E_WR_SP_LAST_0, E_WR_SP_LAST_1, E_WR_SP_VALID_1, E_WR_SP_WAIT);
+
+ signal ScalpRouterResetxRNA : std_ulogic := '0';
+ -- Scalp Packets
+ -- From South 101
+ ---------------------------------------------------------------------------
+ ---------------------------------------------------------------------------
+ signal ScalpPacketLocalxD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
+ (SpHeaderxD => C_SP_HEADER_NULL,
+ SpPayloadxD => C_SP_PAYLOAD_NULL);
+ signal ScalpPacketValidLocalxS : std_ulogic := '0';
+ signal ScalpPacketSelectLocalxD : integer := 0;
+ ---------------------------------------------------------------------------
+ -- Packet 0
+ signal ScalpPacket0xD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
+ (SpHeaderxD => C_SP_HEADER_110_TO_210,
+ SpPayloadxD => C_SP_PAYLOAD_0);
+ signal ScalpPacketValid12xS : std_ulogic := '0';
+ --
+ signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
+ signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
+ signal VioWrSpValidxS : std_ulogic := '0';
+ --
+ signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
+ signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
+ -- Scalp Packet
+ -- attribute mark_debug of ScalpPacket0xD : signal is "true";
+ -- attribute keep of ScalpPacket0xD : signal is "true";
+ -- attribute mark_debug of ScalpPacketValid12xS : signal is "true";
+ -- attribute keep of ScalpPacketValid12xS : signal is "true";
+ -- attribute mark_debug of ScalpPacketLocalxD : signal is "true";
+ -- attribute keep of ScalpPacketLocalxD : signal is "true";
+ -- VIO
+ -- attribute mark_debug of VioWrSpValidxS : signal is "true";
+ -- attribute keep of VioWrSpValidxS : signal is "true";
+ -- attribute mark_debug of ScalpRouterResetxRNA : signal is "true";
+ -- attribute keep of ScalpRouterResetxRNA : signal is "true";
+ -- attribute mark_debug of ScalpPacket0xD : signal is "true";
+ -- attribute keep of ScalpPacket0xD : signal is "true";
+ -- attribute mark_debug of WrSPStatexDP : signal is "true";
+ -- attribute keep of WrSPStatexDP : signal is "true";
+ -- attribute mark_debug of WrSPStatexDN : signal is "true";
+ -- attribute keep of WrSPStatexDN : signal is "true";
+ -- attribute mark_debug of VioWrSpValidxS : signal is "true";
+ -- attribute keep of VioWrSpValidxS : signal is "true";
+ -- attribute mark_debug of ScalpPacketLocalxD : signal is "true";
+ -- attribute keep of ScalpPacketLocalxD : signal is "true";
+ -- attribute mark_debug of ScalpPacketValidLocalxS : signal is "true";
+ -- attribute keep of ScalpPacketValidLocalxS : signal is "true";
+
+ begin -- block NetworkLayerxB
+
+ ResetxB : block is
+
+ constant C_CDC_TYPE : integer range 0 to 2 := 1;
+ constant C_RESET_STATE : integer range 0 to 1 := 0;
+ constant C_SINGLE_BIT : integer range 0 to 1 := 1;
+ constant C_FLOP_INPUT : integer range 0 to 1 := 1;
+ constant C_VECTOR_WIDTH : integer range 0 to 32 := 2;
+ constant C_MTBF_STAGES : integer range 0 to 6 := 5;
+
+ signal PrimaryResetxRN : std_ulogic := '0';
+ signal SecondaryResetxRN : std_ulogic := '0';
+ signal PSSysResetSyncxR : std_ulogic := '0';
+
+ begin -- block ResetxB
+
+ PrimaryResetxAS : PrimaryResetxRN <= not PSSysResetxR;
+ SecondaryResetxAS : SecondaryResetxRN <= not AuroraClkMasterxC.PllNotLockedxS;
+
+ CDCSyncResetxB : entity work.cdc_sync
+ generic map (
+ C_CDC_TYPE => C_CDC_TYPE,
+ C_RESET_STATE => C_RESET_STATE,
+ C_SINGLE_BIT => C_SINGLE_BIT,
+ C_FLOP_INPUT => C_FLOP_INPUT,
+ C_VECTOR_WIDTH => C_VECTOR_WIDTH,
+ C_MTBF_STAGES => C_MTBF_STAGES)
+ port map (
+ PrimaryClkxCAI => PSSysClkxC,
+ PrimaryResetxRNI => PrimaryResetxRN,
+ PrimaryxSI => PSSysResetxR,
+ PrimaryxDI => (others => '0'),
+ PrimaryAckxSO => open,
+ SecondaryClkxCAI => AuroraClkMasterxC.UserClkxC,
+ SecondaryResetxRNI => SecondaryResetxRN,
+ SecondaryxSO => PSSysResetSyncxR,
+ SecondaryxDO => open);
+
+ ScalpRouterResetxAS : ScalpRouterResetxRNA <= (not PSSysResetSyncxR) and
+ (not AuroraClkMasterxC.PllNotLockedxS);
+ -- RX Fifo reset 196 cycles
+ -- Clock and Resets
+ -- RX Fifo
+ NorthFifoResetxAS : RXResetxR.FifoResetxR.NorthxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ '0';
+ EastFifoResetxAS : RXResetxR.FifoResetxR.EastxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ '0';
+ SouthFifoResetxAS : RXResetxR.FifoResetxR.SouthxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ '0';
+ WestFifoResetxAS : RXResetxR.FifoResetxR.WestxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ '0';
+ -- Back pressure
+ NorthBackPressureResetxAS : RXResetxR.BackPressureResetxR.NorthxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ (RXFifoResetDonexD.NorthxS = '0') or
+ (RXFifoResetDoneDelayedxD.NorthxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ '0';
+ EastBackPressureResetxAS : RXResetxR.BackPressureResetxR.EastxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ (RXFifoResetDonexD.EastxS = '0') or
+ (RXFifoResetDoneDelayedxD.EastxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ '0';
+ SouthBackPressureResetxAS : RXResetxR.BackPressureResetxR.SouthxR <=
+ '1' when
+ (RXFifoResetDonexD.SouthxS = '0') or
+ (RXFifoResetDoneDelayedxD.SouthxS = '0') or
+ (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ '0';
+ WestBackPressureResetxAS : RXResetxR.BackPressureResetxR.WestxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ (RXFifoResetDonexD.WestxS = '0') or
+ (RXFifoResetDoneDelayedxD.WestxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ '0';
+
+ end block ResetxB;
+
+ -- ScalpRouterReadyxB : block is
+ -- begin -- block ScalpRouterReadyxB
+
+ -- ScalpRouterReadyNorthxAS : ScalpRouterReadyxD.NorthxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.NorthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.NorthxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ -- '1';
+ -- ScalpRouterReadyEastxAS : ScalpRouterReadyxD.EastxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.EastxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.EastxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ -- '1';
+ -- ScalpRouterReadySouthxAS : ScalpRouterReadyxD.SouthxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.SouthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.SouthxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ -- '1';
+ -- ScalpRouterReadyWestxAS : ScalpRouterReadyxD.WestxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.WestxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.WestxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ -- '1';
+ -- ScalpRouterReadyTopxAS : ScalpRouterReadyxD.TopxS <= '0';
+ -- ScalpRouterReadyBottomxAS : ScalpRouterReadyxD.BottomxS <= '0';
+ -- ScalpRouterReadyLocalxAS : ScalpRouterReadyxD.LocalxS <= (not PSSysResetxR) and
+ -- (not AuroraClkMasterxC.PllNotLockedxS);
+
+ -- end block ScalpRouterReadyxB;
+
+ -- Local Router Net Addr
+ -- LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_210;
+ LocNetAddrXxAS : LocNetAddrxD.XxD <= to_integer(unsigned(LocNetAddrVectxD(7 downto 0)));
+ LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocNetAddrVectxD(15 downto 8)));
+ LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocNetAddrVectxD(23 downto 16)));
+ -- TX Side
+ NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
+ EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID);
+ SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID);
+ WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID);
+ NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD;
+ EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
+ SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
+ WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
+ -- RX Side
+ NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
+ EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
+ SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
+ WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD;
+ NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID);
+ EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID);
+ SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
+ WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
+
+ WrSpValidxI : entity work.vio_axi_cnt_ctrl
+ port map (
+ clk => AuroraClkMasterxC.UserClkxC,
+ probe_out0(0) => VioWrSpValidxS);
+
+ TXFifoStatusWrDataCntxAS : TXWrDataCntxD <= TXFifoStatusxD.WrDataCntxD;
+ TXFifoStatusRdDataCntxAS : TXRdDataCntxD <= TXFifoStatusxD.RdDataCntxD;
+ TXFifoStatusProgFullxAS : ScalpPacketStatusxD(C_TX_PROG_FULL) <= TXFifoStatusxD.ProgFullxS;
+
+ TXFifoWrDataxP : process (AuroraClkMasterxC.UserClkxC,
+ ScalpRouterResetxRNA) is
+ begin -- process TXFifoWrDataxP
+ if ScalpRouterResetxRNA = '0' then
+ TXFifoRXM2SxD <= C_NO_AXI4_M2S;
+ TXFifoWrDataStatexD <= E_WR_IDLE;
+ TXFifoWrDataStateNextxD <= E_WR_IDLE;
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- Default Values
+ TXFifoRXM2SxD <= C_NO_AXI4_M2S;
+ TXFifoWrDataStatexD <= TXFifoWrDataStatexD;
+ TXFifoWrDataStateNextxD <= TXFifoWrDataStateNextxD;
+
+ case TXFifoWrDataStatexD is
+ when E_WR_IDLE =>
+ if ScalpPacketCtrlxD(C_WR_NEW_PACKET) = '1' then
+ TXFifoWrDataStatexD <= E_WR_H0;
+ end if;
+
+ when E_WR_H0 =>
+ if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
+ TXFifoRXM2SxD.DataxD <= scalp_sp_h0_to_axis_ul(ScalpPacketWriteDataxD(31 downto 24),
+ ScalpPacketWriteDataxD(23 downto 16),
+ ScalpPacketWriteDataxD(15 downto 8),
+ ScalpPacketWriteDataxD(7 downto 0));
+ TXFifoRXM2SxD.ValidxS <= '1';
+ TXFifoWrDataStatexD <= E_WR_NEXT;
+ TXFifoWrDataStateNextxD <= E_WR_H1;
+ end if;
+
+ when E_WR_H1 =>
+ if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
+ TXFifoRXM2SxD.DataxD <= scalp_sp_h1_to_axis_ul(ScalpPacketWriteDataxD(31 downto 24),
+ ScalpPacketWriteDataxD(23 downto 16),
+ ScalpPacketWriteDataxD(15 downto 8));
+ TXFifoRXM2SxD.ValidxS <= '1';
+ TXFifoWrDataStatexD <= E_WR_NEXT;
+ TXFifoWrDataStateNextxD <= E_WR_H2;
+ end if;
+
+ when E_WR_H2 =>
+ if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
+ TXFifoRXM2SxD.DataxD <= scalp_sp_h2_to_axis_ul(ScalpPacketWriteDataxD(31 downto 16));
+ TXFifoRXM2SxD.ValidxS <= '1';
+ TXFifoWrDataStatexD <= E_WR_NEXT;
+ TXFifoWrDataStateNextxD <= E_WR_PLD;
+ end if;
+
+ when E_WR_PLD =>
+ if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
+ TXFifoRXM2SxD.DataxD <= scalp_sp_p_to_axis_ul(ScalpPacketWriteDataxD);
+ TXFifoRXM2SxD.ValidxS <= '1';
+ TXFifoWrDataStatexD <= E_WR_NEXT;
+
+ if ScalpPacketCtrlxD(C_WR_LAST) = '1' then
+ TXFifoRXM2SxD.LastxS <= '1';
+ TXFifoWrDataStateNextxD <= E_WR_IDLE;
+ else
+ TXFifoWrDataStateNextxD <= E_WR_PLD;
+ end if;
+ end if;
+
+ when E_WR_NEXT =>
+ if ScalpPacketCtrlxD(C_WR_NEXT) = '1' and ScalpPacketCtrlxD(C_WR_VALID) = '0' then
+ TXFifoWrDataStatexD <= TXFifoWrDataStateNextxD;
+ end if;
+
+ when others => null;
+ end case;
+ end if;
+ end process TXFifoWrDataxP;
+
+ -- TX Fifo
+ ScalpAxisFifoWrapperTXxI : entity work.scalp_axis_fifo_wrapper
+ port map (
+ ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC,
+ ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC,
+ ResetxRI.RstxRAN => ScalpRouterResetxRNA,
+ RXM2SxDI => TXFifoRXM2SxD,
+ RXS2MxSO => TXFifoRXS2MxS,
+ TXM2SxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID),
+ TXS2MxSI => RXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ FifoStatusxDO => TXFifoStatusxD);
+
+ RXFifoStatusWrDataCntxAS : RXWrDataCntxD <= RXFifoStatusxD.WrDataCntxD;
+ RXFifoStatusRdDataCntxAS : RXRdDataCntxD <= RXFifoStatusxD.RdDataCntxD;
+ RXFifoStatusProgFullxAS : ScalpPacketStatusxD(C_RX_PROG_FULL) <= RXFifoStatusxD.ProgFullxS;
+
+ RXFifoRdDataxP : process (AuroraClkMasterxC.UserClkxC,
+ ScalpRouterResetxRNA) is
+ begin -- process RXFifoRdDataxP
+ if ScalpRouterResetxRNA = '0' then
+ RXFifoRdDataStatexD <= E_RD_IDLE;
+ RXFifoRdDataStateNextxD <= E_RD_IDLE;
+ ScalpPacketReadDataxD <= (others => '0');
+ ScalpPacketStatusxD(C_RD_VALID) <= '0';
+ ScalpPacketStatusxD(C_RD_LAST) <= '0';
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- Default Values
+ RXFifoTXS2MxS.ReadyxS <= '0';
+ ScalpPacketReadDataxD <= (others => '0');
+ ScalpPacketStatusxD(C_RD_VALID) <= '0';
+ ScalpPacketStatusxD(C_RD_LAST) <= ScalpPacketStatusxD(C_RD_LAST);
+ ScalpPacketStatusxD(C_RD_WAIT_NEXT) <= '0';
+ RXFifoRdDataStatexD <= RXFifoRdDataStatexD;
+ RXFifoRdDataStateNextxD <= RXFifoRdDataStateNextxD;
+
+ case RXFifoRdDataStatexD is
+ when E_RD_IDLE =>
+ if ScalpPacketCtrlxD(C_RD_NEW_PACKET) = '1' then
+ ScalpPacketStatusxD(C_RD_LAST) <= '0';
+ end if;
+
+ when E_RD_WORD =>
+ if RXFifoTXM2SxD.ValidxS = '1' and ScalpPacketCtrlxD(C_RD_NEXT) = '0' then
+ RXFifoTXS2MxS.ReadyxS <= '1';
+ ScalpPacketReadDataxD <= TXFifoRXM2SxD.DataxD;
+ ScalpPacketStatusxD(C_RD_VALID) <= '1';
+ RXFifoRdDataStatexD <= E_RD_NEXT;
+ RXFifoRdDataStateNextxD <= E_RD_WORD;
+
+ if RXFifoTXM2SxD.LastxS = '1' then
+ ScalpPacketStatusxD(C_RD_LAST) <= '1';
+ RXFifoRdDataStateNextxD <= E_RD_IDLE;
+ end if;
+ end if;
+
+ when E_RD_NEXT =>
+ ScalpPacketReadDataxD <= TXFifoRXM2SxD.DataxD;
+ ScalpPacketStatusxD(C_RD_VALID) <= '1';
+ ScalpPacketStatusxD(C_RD_WAIT_NEXT) <= '1';
+
+ if ScalpPacketCtrlxD(C_RD_NEXT) = '1' then
+ RXFifoRdDataStatexD <= RXFifoRdDataStateNextxD;
+ end if;
+
+ when others => null;
+ end case;
+ end if;
+ end process RXFifoRdDataxP;
+
+ -- RX Fifo
+ ScalpAxisFifoWrapperRXxI : entity work.scalp_axis_fifo_wrapper
+ port map (
+ ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC,
+ ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC,
+ ResetxRI.RstxRAN => ScalpRouterResetxRNA,
+ RXM2SxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
+ RXS2MxSO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ TXM2SxDO => RXFifoTXM2SxD,
+ TXS2MxSI => RXFifoTXS2MxS,
+ FifoStatusxDO => RXFifoStatusxD);
+
+ ScalpRouterxI : entity work.scalp_router
+ generic map (
+ C_SCALP_NUMBER_OF_INTERFACE => C_SCALP_NUMBER_OF_INTERFACE,
+ C_SCALP_SCHEDULER_STRATEGY => C_SCALP_SCHEDULER_STRATEGY)
+ port map (
+ SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ SysRstxRNAI => ScalpRouterResetxRNA,
+ LocNetAddrxDI => LocNetAddrxD,
+ RXAxism2sVectorxDI => RXAxism2sVectorxD,
+ RXAxiss2mVectorxDO => RXAxiss2mVectorxD,
+ TXAxism2sVectorxDO => TXAxism2sVectorxD,
+ TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
+ QoSVectorxDI => QoSVectorxD);
+
+ -- ScalpSP2AxisLocalxI : entity work.scalp_sp_to_axis
+ -- generic map (
+ -- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE)
+ -- port map (
+ -- SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- SysRstxRNAI => ScalpRouterResetxRNA,
+ -- ScalpPacketxDI => ScalpPacket0xD,
+ -- ScalpPacketValidxSI => ScalpPacketValid12xS,
+ -- ScalpAxism2sxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID),
+ -- ScalpAxiss2mxDI => RXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ -- ScalpRdyxSO => open);
+
+ -- ScalpAxis2SPxI : entity work.scalp_axis_to_sp
+ -- generic map (
+ -- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
+ -- C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY)
+ -- port map (
+ -- SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- SysRstxRNAI => ScalpRouterResetxRNA,
+ -- ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
+ -- ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ -- ScalpPacketxDO => ScalpPacketLocalxD,
+ -- ScalpPacketValidxSO => ScalpPacketValidLocalxS);
+
+ -- WritePacketxB : block is
+ -- begin -- block WritePacketxB
+
+ -- UpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ -- ScalpRouterResetxRNA) is
+ -- begin -- process UpdateRegxP
+ -- if ScalpRouterResetxRNA = '0' then
+ -- WrSPStatexDP <= E_WR_SP_IDLE;
+ -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- WrSPStatexDP <= WrSPStatexDN;
+ -- end if;
+ -- end process UpdateRegxP;
+
+ -- SpValidxP : process (RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS,
+ -- VioWrSpValidxS, WrSPStatexDP) is
+ -- begin -- process SpValidxP
+ -- -- Default values
+ -- WrSPStatexDN <= WrSPStatexDP;
+ -- ScalpPacketValid12xS <= '0';
+
+ -- case WrSPStatexDP is
+ -- when E_WR_SP_IDLE =>
+ -- if VioWrSpValidxS = '1' then
+ -- ScalpPacketValid12xS <= '1';
+ -- WrSPStatexDN <= E_WR_SP_VALID_0;
+ -- end if;
+
+ -- when E_WR_SP_VALID_0 =>
+ -- ScalpPacketValid12xS <= '0';
+ -- WrSPStatexDN <= E_WR_SP_LAST_0;
+
+ -- when E_WR_SP_LAST_0 =>
+ -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
+ -- WrSPStatexDN <= E_WR_SP_LAST_1;
+ -- end if;
+
+ -- when E_WR_SP_LAST_1 =>
+ -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then
+ -- ScalpPacketValid12xS <= '1';
+ -- WrSPStatexDN <= E_WR_SP_VALID_1;
+ -- end if;
+
+ -- when E_WR_SP_VALID_1 =>
+ -- ScalpPacketValid12xS <= '0';
+ -- WrSPStatexDN <= E_WR_SP_WAIT;
+
+ -- when E_WR_SP_WAIT =>
+ -- if VioWrSpValidxS = '0' then
+ -- WrSPStatexDN <= E_WR_SP_IDLE;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+ -- end process SpValidxP;
+
+ -- end block WritePacketxB;
+
+ end block NetworkLayerxB;
+
+ end block ProgrammableLogicxB;
+
end arch;