diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
deleted file mode 100644
index bd2004671a4bcb43772f5f3384231a5f0184c287..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
+++ /dev/null
@@ -1,12 +0,0 @@
-{
- "design": {
- "design_info": {
- "boundary_crc": "0x0",
- "name": "scalp_zynqps",
- "rev_ctrl_bd_flag": "RevCtrlBdOff",
- "synth_flow_mode": "Hierarchical",
- "tool_version": "2020.2"
- },
- "design_tree": {}
- }
-}
\ No newline at end of file
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml
deleted file mode 100644
index 55a1a7f16484fe74e434ebdadd264551f06e5679..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Root MajorVersion="0" MinorVersion="39">
- <CompositeFile CompositeFileTopName="scalp_zynqps" CanBeSetAsTop="false" CanDisplayChildGraph="true">
- <Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="STALE" Timestamp="1621502377"/>
- <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1621502377"/>
- <Generation Name="SIMULATION" State="STALE" Timestamp="1621502377"/>
- <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1621502377"/>
- <FileCollection Name="SOURCES" Type="SOURCES"/>
- </CompositeFile>
-</Root>
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui
deleted file mode 100644
index a7ed1822e8e0dc9af68a096fac87844ade15f966..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui
+++ /dev/null
@@ -1,12 +0,0 @@
-{
- "ActiveEmotionalView":"Default View",
- "Default View_ScaleFactor":"1.0",
- "Default View_TopLeft":"-904,-445",
- "ExpandedHierarchyInLayout":"",
- "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
-# -string -flagsOSRD
-levelinfo -pg 1 0 10
-pagesize -pg 1 -db -bbox -sgen 0 0 10 10
-"
-}
-
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml
deleted file mode 100644
index 35a67b65fe5afe4d3cf024523a0893bacee48f32..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml
+++ /dev/null
@@ -1,51 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<document>
-<!--The data in this file is primarily intended for consumption by Xilinx tools.
-The structure and the elements are likely to change over the next few releases.
-This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Thu May 20 11:21:29 2021">
-<section name="Project Information" visible="false">
-<property name="ProjectID" value="d9c1243eb87347ba8472aea5dee0b59a" type="ProjectID"/>
-<property name="ProjectIteration" value="1" type="ProjectIteration"/>
-</section>
-<section name="PlanAhead Usage" visible="true">
-<item name="Project Data">
-<property name="SrcSetCount" value="1" type="SrcSetCount"/>
-<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
-<property name="DesignMode" value="RTL" type="DesignMode"/>
-<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
-<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
-</item>
-<item name="Java Command Handlers">
-<property name="EditDelete" value="1" type="JavaHandler"/>
-<property name="EnablePartialReconfigFlow" value="1" type="JavaHandler"/>
-<property name="ExitApp" value="1" type="JavaHandler"/>
-<property name="RunScript" value="2" type="JavaHandler"/>
-</item>
-<item name="Gui Handlers">
-<property name="BaseDialog_OK" value="2" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="9" type="GuiHandlerData"/>
-<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_EXPORT" value="4" type="GuiHandlerData"/>
-<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
-<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_PROJECT" value="3" type="GuiHandlerData"/>
-<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/>
-<property name="PACommandNames_AUTO_UPDATE_HIER" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_ENABLE_PARTIAL_RECONFIGURATION" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_EXIT" value="2" type="GuiHandlerData"/>
-<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
-<property name="RDICommands_CUSTOM_COMMANDS" value="1" type="GuiHandlerData"/>
-<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
-<property name="RDICommands_RUN_SCRIPT" value="2" type="GuiHandlerData"/>
-<property name="SrcMenu_IP_HIERARCHY" value="1" type="GuiHandlerData"/>
-</item>
-<item name="Other">
-<property name="GuiMode" value="103" type="GuiMode"/>
-<property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="85" type="TclMode"/>
-</item>
-</section>
-</application>
-</document>
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt
deleted file mode 100644
index 023052cab505345c50834e560e42db8c25daf798..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt
+++ /dev/null
@@ -1 +0,0 @@
-The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr
deleted file mode 100644
index 24f1f2f355087654bace6fc15d8b99d3094ebe03..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr
+++ /dev/null
@@ -1,212 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2020.2 (64-bit) -->
-<!-- -->
-<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
-
-<Project Version="7" Minor="54" Path="/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr">
- <DefaultLaunch Dir="$PRUNDIR"/>
- <Configuration>
- <Option Name="Id" Val="0c90be26454f431f93ef1e43b95f0fb5"/>
- <Option Name="Part" Val="xc7z015clg485-2"/>
- <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
- <Option Name="CompiledLibDirXSim" Val=""/>
- <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
- <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
- <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
- <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
- <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
- <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
- <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
- <Option Name="SimulatorInstallDirModelSim" Val=""/>
- <Option Name="SimulatorInstallDirQuesta" Val=""/>
- <Option Name="SimulatorInstallDirIES" Val=""/>
- <Option Name="SimulatorInstallDirXcelium" Val=""/>
- <Option Name="SimulatorInstallDirVCS" Val=""/>
- <Option Name="SimulatorInstallDirRiviera" Val=""/>
- <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
- <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
- <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
- <Option Name="SimulatorGccInstallDirIES" Val=""/>
- <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
- <Option Name="SimulatorGccInstallDirVCS" Val=""/>
- <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
- <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
- <Option Name="TargetLanguage" Val="VHDL"/>
- <Option Name="BoardPart" Val="hepia-cores.ch:scalp_node:part0:0.1"/>
- <Option Name="ActiveSimSet" Val="sim_1"/>
- <Option Name="DefaultLib" Val="xil_defaultlib"/>
- <Option Name="ProjectType" Val="Default"/>
- <Option Name="IPRepoPath" Val="$PPRDIR/../../../../../hw"/>
- <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
- <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
- <Option Name="IPCachePermission" Val="read"/>
- <Option Name="IPCachePermission" Val="write"/>
- <Option Name="EnableCoreContainer" Val="FALSE"/>
- <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
- <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
- <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
- <Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="DSABoardId" Val="scalp_node"/>
- <Option Name="WTXSimLaunchSim" Val="0"/>
- <Option Name="WTModelSimLaunchSim" Val="0"/>
- <Option Name="WTQuestaLaunchSim" Val="0"/>
- <Option Name="WTIesLaunchSim" Val="0"/>
- <Option Name="WTVcsLaunchSim" Val="0"/>
- <Option Name="WTRivieraLaunchSim" Val="0"/>
- <Option Name="WTActivehdlLaunchSim" Val="0"/>
- <Option Name="WTXSimExportSim" Val="0"/>
- <Option Name="WTModelSimExportSim" Val="0"/>
- <Option Name="WTQuestaExportSim" Val="0"/>
- <Option Name="WTIesExportSim" Val="0"/>
- <Option Name="WTVcsExportSim" Val="0"/>
- <Option Name="WTRivieraExportSim" Val="0"/>
- <Option Name="WTActivehdlExportSim" Val="0"/>
- <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
- <Option Name="XSimRadix" Val="hex"/>
- <Option Name="XSimTimeUnit" Val="ns"/>
- <Option Name="XSimArrayDisplayLimit" Val="1024"/>
- <Option Name="XSimTraceLimit" Val="65536"/>
- <Option Name="SimTypes" Val="rtl"/>
- <Option Name="SimTypes" Val="bfm"/>
- <Option Name="SimTypes" Val="tlm"/>
- <Option Name="SimTypes" Val="tlm_dpi"/>
- <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
- <Option Name="DcpsUptoDate" Val="TRUE"/>
- </Configuration>
- <FileSets Version="1" Minor="31">
- <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../../../../../hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="scalp_zynqps_wrapper"/>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
- <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
- <Filter Type="Constrs"/>
- <Config>
- <Option Name="ConstrsType" Val="XDC"/>
- </Config>
- </FileSet>
- <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../../../../../hw/scalp_zynqps/src/sim/tb_scalp_zynqps.vhd">
- <FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="scalp_zynqps_wrapper"/>
- <Option Name="TopLib" Val="xil_defaultlib"/>
- <Option Name="TopAutoSet" Val="TRUE"/>
- <Option Name="TransportPathDelay" Val="0"/>
- <Option Name="TransportIntDelay" Val="0"/>
- <Option Name="SelectedSimModel" Val="rtl"/>
- <Option Name="PamDesignTestbench" Val=""/>
- <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
- <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
- <Option Name="PamPseudoTop" Val="pseudo_tb"/>
- <Option Name="SrcSet" Val="sources_1"/>
- </Config>
- </FileSet>
- <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
- <Filter Type="Utils"/>
- <Config>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
- </FileSets>
- <Simulators>
- <Simulator Name="XSim">
- <Option Name="Description" Val="Vivado Simulator"/>
- <Option Name="CompiledLib" Val="0"/>
- </Simulator>
- <Simulator Name="ModelSim">
- <Option Name="Description" Val="ModelSim Simulator"/>
- </Simulator>
- <Simulator Name="Questa">
- <Option Name="Description" Val="Questa Advanced Simulator"/>
- </Simulator>
- <Simulator Name="IES">
- <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
- </Simulator>
- <Simulator Name="Xcelium">
- <Option Name="Description" Val="Xcelium Parallel Simulator"/>
- </Simulator>
- <Simulator Name="VCS">
- <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
- </Simulator>
- <Simulator Name="Riviera">
- <Option Name="Description" Val="Riviera-PRO Simulator"/>
- </Simulator>
- </Simulators>
- <Runs Version="1" Minor="15">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
- <Step Id="synth_design"/>
- </Strategy>
- <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
- <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
- <RQSFiles/>
- </Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
- <Step Id="init_design"/>
- <Step Id="opt_design"/>
- <Step Id="power_opt_design"/>
- <Step Id="place_design"/>
- <Step Id="post_place_power_opt_design"/>
- <Step Id="phys_opt_design"/>
- <Step Id="route_design"/>
- <Step Id="post_route_phys_opt_design"/>
- <Step Id="write_bitstream"/>
- </Strategy>
- <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
- <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
- <RQSFiles/>
- </Run>
- </Runs>
- <Board>
- <Jumpers/>
- </Board>
- <DashboardSummary Version="1" Minor="0">
- <Dashboards>
- <Dashboard Name="default_dashboard">
- <Gadgets>
- <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
- <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
- </Gadget>
- <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
- <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
- </Gadget>
- <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
- <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
- </Gadget>
- <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
- <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
- </Gadget>
- <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
- <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
- <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
- <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
- </Gadget>
- <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
- <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
- </Gadget>
- </Gadgets>
- </Dashboard>
- <CurrentDashboard>default_dashboard</CurrentDashboard>
- </Dashboards>
- </DashboardSummary>
-</Project>
diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index 664b83c794644112a7d2aab5b529e2968f4a30a2..633e2fcc77185f6495c2ed688f235352caea713d 100644
--- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -127,7 +127,7 @@ xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
-hepia.hesge.ch:user:scalp_router_regbank:0.5\
+hepia.hesge.ch:user:scalp_router_regbank:0.8\
hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
@@ -691,7 +691,7 @@ proc create_root_design { parentCell } {
set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
# Create instance: scalp_router_regbank_0, and set properties
- set scalp_router_regbank_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:0.5 scalp_router_regbank_0 ]
+ set scalp_router_regbank_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:0.8 scalp_router_regbank_0 ]
# Create instance: scalp_safe_firmware_0, and set properties
set scalp_safe_firmware_0 [ create_bd_cell -type ip -vlnv hepia.ch:user:scalp_safe_firmware_reg_bank:1.3 scalp_safe_firmware_0 ]