diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
index aa57ef71a9c85ae01de679ec54c34efde9e50ffb..99d4bf8ad2e493cc1af8930d388d81ca3dc390bd 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Console color print utility
#
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
index 7d608d02cd8553f297e9d6e792c2dfd38f7204e5..d3dfb2adf41884cf259d19e1f04ee3cb5544c5a3 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Cleanup project directory
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
index b8f05723478981732e586ee9cfe6583b77802317..a6717d0952fb9c4b68368ceb8b233d197acdee6d 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Create Vivado project
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
index 76733a1ea5f1cc584c47ea1d1aa9f849ee03b0f2..0c01c2b93f0eccd2b8a25de0798b5ccbb598414f 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware'
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
@@ -80,6 +80,13 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
+ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
+ add_files -norecurse $vhdl_ips_file_list
+ foreach j $vhdl_ips_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
@@ -88,6 +95,7 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $j]
}
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
+ read_ip ${ip_dir}/scalp_packet_fifo_wrapper/src/ip_core/scalp_packet_fifo/scalp_packet_fifo.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
index 909d5734b09ed25be42158f1d480839ac8d6e256..fd74d83fb0234b0f77928a794d07dc3697735d36 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
index a6d1f8bf6c29e7a61bbb57c90c4aca542245f4ad..c761de294d8bd952a79e11d5d5355b5dd356ead4 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
index 378e1567c9eb8e4db2daba31a2c6658fe9d0a287..01003e2e90cf1e8c0236763e6a1ca72c8a1c9df7 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Generate bitstream file
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
index 0b38b88c289475ae015e91839c496df2ee2ddc6a..d64b7dd793a143de21aaedd474774192d954c355 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: TCL script used to generate bitstream file
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
index 2160b2fdc8e8396bca50286d4ab9658040ac9dbb..02cc757dad33bfdbf45d1a7ecf6f083042027ab1 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Generate software application
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
index 99251d420e50a1f21b00ed6b48e786fac914e8c7..f0b6768d46be9ee81c662ebd2c38bea3a27ee267 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: TCL script used to generate software application
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
index 577b49ef88e7b1c99eefff20ec04d577ce7e1b8f..ad321d5a378118edb513e0e7407288a72e37add9 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Load bitstream file
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
index 28e9e47a4d761d134400956118b6db5891ff5a91..1b87d692b6f41e4dc37e0456ea9a4f80bbee6885 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script used to load FPGA bitstream
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
index 07e5eb037e7f5420f53c67ba75df53f352a0bf22..20a872b7776891cd5188a647c722eeb82db155ef 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Load software application
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
index 82206c5eaceec41fadfcf9d83276045e128d1758..e0a242beabd1d470c68716b94eebd588c54c819f 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script used to load software application
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
index 98c24899530d27f9eb0390725486c6a77367a398..35cbfa11adc950f745f1ef43400d6c64712a7195 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Create Vivado project
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
index e6fb3e933f51f8681f077232529865e2fbd06ee8..23dd03332c88dcf55fc70a23dba76b9a98e838cd 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Project management utilities
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh b/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
index ac7f44dd6a0c7607282ddd094a73f0d0924ec635..c704bc4e98245ef380625b3014af296cd479b173 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-11-07 09:14:14
+# Last update: 2020-11-08 11:36:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
index aceb82ea9b974f12f2f29d36bd3d5deb9f2ef210..e49a1019180576010563b2b90c6ea286e4c5ed49 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
@@ -274,6 +274,7 @@ architecture arch of scalp_firmware is
-- Constantes
-- constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
+ constant C_AXI_ADDR_SIZE : integer range 0 to 32 := 12;
component scalp_aurora_phy is
generic (
@@ -337,86 +338,145 @@ architecture arch of scalp_firmware is
-- Signals
-- Clocks
-- Processing system clock
- signal PSSysClkxC : std_logic := '0';
+ signal PSSysClkxC : std_logic := '0';
-- GTP Clocks
-- signal GTPRefClk0xC : std_logic := '0';
-- signal GTPRefClk1xC : std_logic := '0';
- signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
- signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
-- Resets
-- Processing system reset
- signal PSSysResetxR : std_logic := '0';
+ signal PSSysResetxR : std_logic := '0';
-- Scalp Aurora Phy
- signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
- signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
- signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
- signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
- signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
- signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
- signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
- signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
- signal NorthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal EastFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal SouthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal WestFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
+ signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
+ signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
+ signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
+ signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
+ signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
+ signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
+ signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal NorthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal EastFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal SouthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal WestFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ -- Scalp Axi Lite interface and IRQ
+ signal InterruptxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
+ -- Zynq Reg Bank
+ type t_status_send_word is (E_IDLE, E_SEND);
+
+ signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
+ signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
+ --
+ signal NorthNativeSlavexD : t_native_fifo_slave;
+ signal NorthNativeMasterxD : t_native_fifo_master;
+ signal EastNativeSlavexD : t_native_fifo_slave;
+ signal EastNativeMasterxD : t_native_fifo_master;
+ signal SouthNativeSlavexD : t_native_fifo_slave;
+ signal SouthNativeMasterxD : t_native_fifo_master;
+ signal WestNativeSlavexD : t_native_fifo_slave;
+ signal WestNativeMasterxD : t_native_fifo_master;
+ --
+ -- signal InterruptRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal InterruptRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- North
+ signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- East
+ signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- South
+ signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- West
+ signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- Attributes
attribute mark_debug : string;
@@ -474,7 +534,15 @@ begin
Spi1SSxSO => Pll2V5LEuWirexSO,
Spi1SclkxCO => Pll2V5ClkuWirexCO,
-- MIO
- FIXED_IO_mio => MIOxDIO);
+ FIXED_IO_mio => MIOxDIO,
+ -- Scalp Axi Lite interface and IRQ
+ InterruptxSI => InterruptxS,
+ RdAddrxDO => RdAddrxD,
+ RdDataxDI => RdDataxD,
+ RdValidxSO => RdValidxS,
+ WrAddrxDO => WrAddrxD,
+ WrDataxDO => WrDataxD,
+ WrValidxSO => WrValidxS);
end block ProcessingSystemxB;
@@ -1014,6 +1082,353 @@ begin
end block GTPhyxB;
+ ZynqRegBankxB : block is
+ begin -- block ZynqRegBankxB
+
+
+ RegBankxB : block is
+ begin -- block RegBankxB
+
+ WriteRegPortxP : process (EastCtrlRegPortxDP,
+ EastWrDataRegPortxDP,
+ NorthCtrlRegPortxDP,
+ NorthWrDataRegPortxDP,
+ SouthCtrlRegPortxDP,
+ SouthWrDataRegPortxDP,
+ WestCtrlRegPortxDP,
+ WestWrDataRegPortxDP, WrAddrxD,
+ WrDataxD, WrValidxS) is
+ begin -- process WriteRegPortxP
+ -- North
+ NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP;
+ NorthWrDataRegPortxDN <= NorthWrDataRegPortxDP;
+ -- East
+ EastCtrlRegPortxDN <= EastCtrlRegPortxDP;
+ EastWrDataRegPortxDN <= EastWrDataRegPortxDP;
+ -- South
+ SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP;
+ SouthWrDataRegPortxDN <= SouthWrDataRegPortxDP;
+ -- West
+ WestCtrlRegPortxDN <= WestCtrlRegPortxDP;
+ WestWrDataRegPortxDN <= WestWrDataRegPortxDP;
+
+ if WrValidxS = '1' then
+ case WrAddrxD is
+ -- Ctrl
+ -- North
+ when x"000" => NorthCtrlRegPortxDN <= WrDataxD;
+ when x"004" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP or WrDataxD;
+ when x"008" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP and not WrDataxD;
+ -- East
+ when x"00c" => EastCtrlRegPortxDN <= WrDataxD;
+ when x"010" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP or WrDataxD;
+ when x"014" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP and not WrDataxD;
+ -- South
+ when x"018" => SouthCtrlRegPortxDN <= WrDataxD;
+ when x"01c" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP or WrDataxD;
+ when x"020" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP and not WrDataxD;
+ -- East
+ when x"024" => WestCtrlRegPortxDN <= WrDataxD;
+ when x"028" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP or WrDataxD;
+ when x"02c" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP and not WrDataxD;
+ -- Data
+ -- North
+ when x"030" => NorthWrDataRegPortxDN <= WrDataxD;
+ -- East
+ when x"034" => EastWrDataRegPortxDN <= WrDataxD;
+ -- South
+ when x"038" => SouthWrDataRegPortxDN <= WrDataxD;
+ -- West
+ when x"03c" => WestWrDataRegPortxDN <= WrDataxD;
+ when others => null;
+ end case;
+ end if;
+ end process WriteRegPortxP;
+
+ ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
+ begin -- process ReadRegPortxP
+ if PSSysResetxR = '1' then
+ RdDataxD <= (others => '0');
+ elsif rising_edge(PSSysClkxC) then
+ RdDataxD <= (others => '0');
+
+ if RdValidxS = '1' then
+ case RdAddrxD is
+ when x"000" => RdDataxD <= NorthCtrlRegPortxDP;
+ when x"00C" => RdDataxD <= EastCtrlRegPortxDP;
+ when x"018" => RdDataxD <= SouthCtrlRegPortxDP;
+ when x"024" => RdDataxD <= WestCtrlRegPortxDP;
+ when x"030" => RdDataxD <= NorthWrDataRegPortxDP;
+ when x"034" => RdDataxD <= EastWrDataRegPortxDP;
+ when x"038" => RdDataxD <= SouthWrDataRegPortxDP;
+ when x"03c" => RdDataxD <= WestWrDataRegPortxDP;
+ when x"040" => RdDataxD <= NorthStatusRegPortxDP;
+ when x"044" => RdDataxD <= EastStatusRegPortxDP;
+ when x"048" => RdDataxD <= SouthStatusRegPortxDP;
+ when x"04c" => RdDataxD <= WestStatusRegPortxDP;
+ when others => RdDataxD <= (others => '0');
+ end case;
+ end if;
+ end if;
+ end process ReadRegPortxP;
+
+ RegBankxP : process (PSSysClkxC, PSSysResetxR) is
+ begin -- process RegBankxP
+ if PSSysResetxR = '1' then
+ -- North
+ NorthStatusRegPortxDP <= (others => '0');
+ NorthCtrlRegPortxDP <= (others => '0');
+ NorthWrDataRegPortxDP <= (others => '0');
+ -- East
+ EastStatusRegPortxDP <= (others => '0');
+ EastCtrlRegPortxDP <= (others => '0');
+ EastWrDataRegPortxDP <= (others => '0');
+ -- South
+ SouthStatusRegPortxDP <= (others => '0');
+ SouthCtrlRegPortxDP <= (others => '0');
+ SouthWrDataRegPortxDP <= (others => '0');
+ -- West
+ WestStatusRegPortxDP <= (others => '0');
+ WestCtrlRegPortxDP <= (others => '0');
+ WestWrDataRegPortxDP <= (others => '0');
+ elsif rising_edge(PSSysClkxC) then
+ -- North
+ NorthStatusRegPortxDP <= NorthStatusRegPortxDN;
+ NorthCtrlRegPortxDP <= NorthCtrlRegPortxDN;
+ NorthWrDataRegPortxDP <= NorthWrDataRegPortxDN;
+ -- East
+ EastStatusRegPortxDP <= EastStatusRegPortxDN;
+ EastCtrlRegPortxDP <= EastCtrlRegPortxDN;
+ EastWrDataRegPortxDP <= EastWrDataRegPortxDN;
+ -- South
+ SouthStatusRegPortxDP <= SouthStatusRegPortxDN;
+ SouthCtrlRegPortxDP <= SouthCtrlRegPortxDN;
+ SouthWrDataRegPortxDP <= SouthWrDataRegPortxDN;
+ -- West
+ WestStatusRegPortxDP <= WestStatusRegPortxDN;
+ WestCtrlRegPortxDP <= WestCtrlRegPortxDN;
+ WestWrDataRegPortxDP <= WestWrDataRegPortxDN;
+ end if;
+ end process RegBankxP;
+
+ end block RegBankxB;
+
+ TxFifoxB : block is
+ begin -- block TxFifoxB
+
+ NorthWrDataxAS : NorthNativeSlavexD.DataxD <= NorthWrDataRegPortxDP;
+ EastWrDataxAS : EastNativeSlavexD.DataxD <= EastWrDataRegPortxDP;
+ SouthWrDataxAS : SouthNativeSlavexD.DataxD <= SouthWrDataRegPortxDN;
+ WestWrDataRegxAS : WestNativeSlavexD.DataxD <= WestWrDataRegPortxDN;
+ NorthWrEnxAS : NorthNativeSlavexD.WrEnxS <= NorthCtrlRegPortxDP(0);
+ EastWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
+ SouthWrEnxAS : SouthNativeSlavexD.WrEnxS <= SouthCtrlRegPortxDP(0);
+ WestWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
+ NorthStatusRegPortxAS : NorthStatusRegPortxDN <= (0 => NorthNativeMasterxD.FullxS,
+ 1 => NorthNativeMasterxD.EmptyxS,
+ 2 => NorthNativeMasterxD.AlmostFullxS,
+ 3 => NorthNativeMasterxD.AlmostEmptyxS,
+ 4 => NorthNativeMasterxD.WrRstBusyxS,
+ 5 => NorthNativeMasterxD.RdRstBusyxS,
+ others => '0');
+ EastStatusRegPortxAS : EastStatusRegPortxDN <= (0 => EastNativeMasterxD.FullxS,
+ 1 => EastNativeMasterxD.EmptyxS,
+ 2 => EastNativeMasterxD.AlmostFullxS,
+ 3 => EastNativeMasterxD.AlmostEmptyxS,
+ 4 => EastNativeMasterxD.WrRstBusyxS,
+ 5 => EastNativeMasterxD.RdRstBusyxS,
+ others => '0');
+ SouthStatusRegPortxAS : SouthStatusRegPortxDN <= (0 => SouthNativeMasterxD.FullxS,
+ 1 => SouthNativeMasterxD.EmptyxS,
+ 2 => SouthNativeMasterxD.AlmostFullxS,
+ 3 => SouthNativeMasterxD.AlmostEmptyxS,
+ 4 => SouthNativeMasterxD.WrRstBusyxS,
+ 5 => SouthNativeMasterxD.RdRstBusyxS,
+ others => '0');
+ WestStatusRegPortxAS : WestStatusRegPortxDN <= (0 => WestNativeMasterxD.FullxS,
+ 1 => WestNativeMasterxD.EmptyxS,
+ 2 => WestNativeMasterxD.AlmostFullxS,
+ 3 => WestNativeMasterxD.AlmostEmptyxS,
+ 4 => WestNativeMasterxD.WrRstBusyxS,
+ 5 => WestNativeMasterxD.RdRstBusyxS,
+ others => '0');
+
+ UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
+ AuroraClkMasterxC.UserClkxC) is
+ begin -- process UpdateRegxP
+ if not AuroraClkMasterxC.PllNotLockedxS then
+ NorthStatusSendWordxDP <= E_IDLE;
+ EastStatusSendWordxDP <= E_IDLE;
+ SouthStatusSendWordxDP <= E_IDLE;
+ WestStatusSendWordxDP <= E_IDLE;
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ NorthStatusSendWordxDP <= NorthStatusSendWordxDN;
+ EastStatusSendWordxDP <= EastStatusSendWordxDN;
+ SouthStatusSendWordxDP <= SouthStatusSendWordxDN;
+ WestStatusSendWordxDP <= WestStatusSendWordxDN;
+ end if;
+ end process UpdateRegxP;
+
+ NorthSendWordxP : process (NorthNativeMasterxD.DataxD,
+ NorthNativeMasterxD.EmptyxS,
+ NorthStatusSendWordxDP,
+ NorthTXS2MxD.ReadyxS) is
+ begin -- process NorthSendWordxP
+ NorthTXM2SxD.DataxD <= (others => '0');
+ NorthTXM2SxD.KeepxD <= (others => '1');
+ NorthTXM2SxD.LastxS <= '0';
+ NorthTXM2SxD.ValidxS <= '0';
+ NorthNativeSlavexD.RdEnxS <= '0';
+ NorthStatusSendWordxDN <= NorthStatusSendWordxDP;
+
+ case NorthStatusSendWordxDP is
+ when E_IDLE =>
+
+ if (NorthNativeMasterxD.EmptyxS = '0') and
+ (NorthTXS2MxD.ReadyxS = '1') then
+ NorthTXM2SxD.DataxD <= NorthNativeMasterxD.DataxD;
+ NorthTXM2SxD.LastxS <= '1';
+ NorthTXM2SxD.ValidxS <= '1';
+ NorthNativeSlavexD.RdEnxS <= '1';
+ NorthStatusSendWordxDN <= E_SEND;
+ end if;
+
+ when E_SEND =>
+ NorthStatusSendWordxDN <= E_IDLE;
+
+ when others => null;
+ end case;
+ end process NorthSendWordxP;
+
+ EastSendWordxP : process (EastNativeMasterxD.DataxD,
+ EastNativeMasterxD.EmptyxS,
+ EastStatusSendWordxDP,
+ EastTXS2MxD.ReadyxS) is
+ begin -- process EastSendWordxP
+ EastTXM2SxD.DataxD <= (others => '0');
+ EastTXM2SxD.KeepxD <= (others => '1');
+ EastTXM2SxD.LastxS <= '0';
+ EastTXM2SxD.ValidxS <= '0';
+ EastNativeSlavexD.RdEnxS <= '0';
+ EastStatusSendWordxDN <= EastStatusSendWordxDP;
+
+ case EastStatusSendWordxDP is
+ when E_IDLE =>
+
+ if (EastNativeMasterxD.EmptyxS = '0') and
+ (EastTXS2MxD.ReadyxS = '1') then
+ EastTXM2SxD.DataxD <= EastNativeMasterxD.DataxD;
+ EastTXM2SxD.LastxS <= '1';
+ EastTXM2SxD.ValidxS <= '1';
+ EastNativeSlavexD.RdEnxS <= '1';
+ EastStatusSendWordxDN <= E_SEND;
+ end if;
+
+ when E_SEND =>
+ EastStatusSendWordxDN <= E_IDLE;
+
+ when others => null;
+ end case;
+ end process EastSendWordxP;
+
+ SouthSendWordxP : process (SouthNativeMasterxD.DataxD,
+ SouthNativeMasterxD.EmptyxS,
+ SouthStatusSendWordxDP,
+ SouthTXS2MxD.ReadyxS) is
+ begin -- process SouthSendWordxP
+ SouthTXM2SxD.DataxD <= (others => '0');
+ SouthTXM2SxD.KeepxD <= (others => '1');
+ SouthTXM2SxD.LastxS <= '0';
+ SouthTXM2SxD.ValidxS <= '0';
+ SouthNativeSlavexD.RdEnxS <= '0';
+ SouthStatusSendWordxDN <= SouthStatusSendWordxDP;
+
+ case SouthStatusSendWordxDP is
+ when E_IDLE =>
+
+ if (SouthNativeMasterxD.EmptyxS = '0') and
+ (SouthTXS2MxD.ReadyxS = '1') then
+ SouthTXM2SxD.DataxD <= SouthNativeMasterxD.DataxD;
+ SouthTXM2SxD.LastxS <= '1';
+ SouthTXM2SxD.ValidxS <= '1';
+ SouthNativeSlavexD.RdEnxS <= '1';
+ SouthStatusSendWordxDN <= E_SEND;
+ end if;
+
+ when E_SEND =>
+ SouthStatusSendWordxDN <= E_IDLE;
+
+ when others => null;
+ end case;
+ end process SouthSendWordxP;
+
+ WestSendWordxP : process (WestNativeMasterxD.DataxD,
+ WestNativeMasterxD.EmptyxS,
+ WestStatusSendWordxDP,
+ WestTXS2MxD.ReadyxS) is
+ begin -- process WestSendWordxP
+ WestTXM2SxD.DataxD <= (others => '0');
+ WestTXM2SxD.KeepxD <= (others => '1');
+ WestTXM2SxD.LastxS <= '0';
+ WestTXM2SxD.ValidxS <= '0';
+ WestNativeSlavexD.RdEnxS <= '0';
+ WestStatusSendWordxDN <= WestStatusSendWordxDP;
+
+ case WestStatusSendWordxDP is
+ when E_IDLE =>
+
+ if (WestNativeMasterxD.EmptyxS = '0') and
+ (WestTXS2MxD.ReadyxS = '1') then
+ WestTXM2SxD.DataxD <= WestNativeMasterxD.DataxD;
+ WestTXM2SxD.LastxS <= '1';
+ WestTXM2SxD.ValidxS <= '1';
+ WestNativeSlavexD.RdEnxS <= '1';
+ WestStatusSendWordxDN <= E_SEND;
+ end if;
+
+ when E_SEND =>
+ WestStatusSendWordxDN <= E_IDLE;
+
+ when others => null;
+ end case;
+ end process WestSendWordxP;
+
+ NorthFifoxI : entity work.scalp_packet_fifo_wrapper
+ port map (
+ RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ WrClkxCI => PSSysClkxC,
+ ResetxRI => PSSysResetxR,
+ NativeSlavexDI => NorthNativeSlavexD,
+ NativeMasterxDO => NorthNativeMasterxD);
+
+ EastFifoxI : entity work.scalp_packet_fifo_wrapper
+ port map (
+ RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ WrClkxCI => PSSysClkxC,
+ ResetxRI => PSSysResetxR,
+ NativeSlavexDI => EastNativeSlavexD,
+ NativeMasterxDO => EastNativeMasterxD);
+
+ SouthFifoxI : entity work.scalp_packet_fifo_wrapper
+ port map (
+ RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ WrClkxCI => PSSysClkxC,
+ ResetxRI => PSSysResetxR,
+ NativeSlavexDI => SouthNativeSlavexD,
+ NativeMasterxDO => SouthNativeMasterxD);
+
+ WestFifoxI : entity work.scalp_packet_fifo_wrapper
+ port map (
+ RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ WrClkxCI => PSSysClkxC,
+ ResetxRI => PSSysResetxR,
+ NativeSlavexDI => WestNativeSlavexD,
+ NativeMasterxDO => WestNativeMasterxD);
+
+ end block TxFifoxB;
+
+ end block ZynqRegBankxB;
+
DebugxB : block is
signal CntRstxR : std_ulogic := '0';
@@ -1022,34 +1437,34 @@ begin
begin -- block DebugxB
- ClkEnxAS : ClkEnxS <= not AuroraClkMasterxC.PllNotLockedxS;
- -- North
- NorthTXDataxAS : NorthTXM2SxD.DataxD <= DataCounterxD;
- NorthTXKeepxAS : NorthTXM2SxD.KeepxD <= (others => '1');
- NorthTXLastxAS : NorthTXM2SxD.LastxS <= '0';
- NorthTXValidxAS : NorthTXM2SxD.ValidxS <= not CntRstxR;
- -- East
- EastTXDataxAS : EastTXM2SxD.DataxD <= DataCounterxD;
- EastTXKeepxAS : EastTXM2SxD.KeepxD <= (others => '1');
- EastTXLastxAS : EastTXM2SxD.LastxS <= '0';
- EastTXValidxAS : EastTXM2SxD.ValidxS <= not CntRstxR;
- -- South
- SouthTXDataxAS : SouthTXM2SxD.DataxD <= DataCounterxD;
- SouthTXKeepxAS : SouthTXM2SxD.KeepxD <= (others => '1');
- SouthTXLastxAS : SouthTXM2SxD.LastxS <= '0';
- SouthTXValidxAS : SouthTXM2SxD.ValidxS <= not CntRstxR;
- -- West
- WestTXDataxAS : WestTXM2SxD.DataxD <= DataCounterxD;
- WestTXKeepxAS : WestTXM2SxD.KeepxD <= (others => '1');
- WestTXLastxAS : WestTXM2SxD.LastxS <= '0';
- WestTXValidxAS : WestTXM2SxD.ValidxS <= not CntRstxR;
-
- DataCounterxI : entity work.data_counter
- port map (
- clk => AuroraClkMasterxC.UserClkxC,
- ce => ClkEnxS,
- sclr => CntRstxR,
- q => DataCounterxD);
+ -- ClkEnxAS : ClkEnxS <= not AuroraClkMasterxC.PllNotLockedxS;
+ -- -- North
+ -- NorthTXDataxAS : NorthTXM2SxD.DataxD <= DataCounterxD;
+ -- NorthTXKeepxAS : NorthTXM2SxD.KeepxD <= (others => '1');
+ -- NorthTXLastxAS : NorthTXM2SxD.LastxS <= '0';
+ -- NorthTXValidxAS : NorthTXM2SxD.ValidxS <= not CntRstxR;
+ -- -- East
+ -- EastTXDataxAS : EastTXM2SxD.DataxD <= DataCounterxD;
+ -- EastTXKeepxAS : EastTXM2SxD.KeepxD <= (others => '1');
+ -- EastTXLastxAS : EastTXM2SxD.LastxS <= '0';
+ -- EastTXValidxAS : EastTXM2SxD.ValidxS <= not CntRstxR;
+ -- -- South
+ -- SouthTXDataxAS : SouthTXM2SxD.DataxD <= DataCounterxD;
+ -- SouthTXKeepxAS : SouthTXM2SxD.KeepxD <= (others => '1');
+ -- SouthTXLastxAS : SouthTXM2SxD.LastxS <= '0';
+ -- SouthTXValidxAS : SouthTXM2SxD.ValidxS <= not CntRstxR;
+ -- -- West
+ -- WestTXDataxAS : WestTXM2SxD.DataxD <= DataCounterxD;
+ -- WestTXKeepxAS : WestTXM2SxD.KeepxD <= (others => '1');
+ -- WestTXLastxAS : WestTXM2SxD.LastxS <= '0';
+ -- WestTXValidxAS : WestTXM2SxD.ValidxS <= not CntRstxR;
+
+ -- DataCounterxI : entity work.data_counter
+ -- port map (
+ -- clk => AuroraClkMasterxC.UserClkxC,
+ -- ce => ClkEnxS,
+ -- sclr => CntRstxR,
+ -- q => DataCounterxD);
VioAxiCntCtrlxI : entity work.vio_axi_cnt_ctrl
port map (