diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.gitignore b/designs/vivado/scalp_firmware/2020.2/lin64/.gitignore index b84377266c8c11f3c844e58a69638b292065d8d3..0eb199c5f955f316db3c57e4a0fc7009ed74b5a5 100644 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.gitignore +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.gitignore @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: Git ignore file # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl index 26bb4764bae5b76cc8393eb8c07b8bec48126e44..af138726a20d42502b1a607bf2c72fe727e2c356 100644 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: Console color print utility # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh index 72d628d5c5fa490ac6764f6041288749246091f2..03bba8975b7a1bab635163c42213cda5516a3059 100755 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Cleanup project directory # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh index 7ca8140a2ed03fa78f30448ad58e27aa925cc2e3..760a645f6f1cf682be24c5b0cca12cc3d32c81ef 100755 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Create Vivado project # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl index c58039e46155a5dbc2246ebfa6da68bca7019f2b..c93842c3971eb4d45b2b7b7ad5d2c65bdc22c558 100644 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: TCL script for re-creating Vivado project 'scalp_firmware' # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## @@ -113,6 +113,13 @@ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_rx_link_layer/src/hdl *.vhd] print_status "VHDL 2008 mode configured for the file $j" "OK" set_property is_enabled true [get_files $j] } +set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_axis_fifo_wrapper/src/hdl *.vhd] + add_files -norecurse $vhdl_ips_file_list + foreach j $vhdl_ips_file_list { + set_property file_type {VHDL 2008} [get_files $j] + print_status "VHDL 2008 mode configured for the file $j" "OK" + set_property is_enabled true [get_files $j] + } set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd] add_files -norecurse $vhdl_ips_file_list foreach j $vhdl_ips_file_list { @@ -139,6 +146,7 @@ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.v read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci + read_ip ${ip_dir}/scalp_axis_fifo_wrapper/src/ip_core/scalp_axis_fifo/scalp_axis_fifo.xci read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh index ddb6537cbe964b36f9a4917d4cee8a33a817f37e..b8f7aea891b476a4b611b08dc4c931deb6184e4b 100755 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Export the hardware design to SDK # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl index 5b7b5b58eb5576944799c2cf952ffd2f5bb10ccd..77655b61a89081c15cc6a330edaf4ac5f1b01af4 100644 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: Export the hardware design to Vitis SDK # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh index 45716b472122cde0d084ad02341de73dd4a9a935..0992759329d77025aa92cc574f2e09fb9fe95634 100755 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Generate bitstream file # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl index 045ce645962af1137230a6f21aa0422e2013089b..830bc505fb048f4646f55bb27f08f551b5c4e864 100644 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: TCL script used to generate bitstream file # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh index dee4aa7c3f7f41c6f656c3b04edb2446a899a04a..121dc7cb58fce1540e6cdffe1dec50a69e5fba2c 100755 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Load bitstream file # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl index 2e1fa2c7885bbd5f882a81b27b02a9a47f10b422..f20df014d828784cd1fd889c03c13ab06b7f4ed5 100644 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: TCL script used to load FPGA bitstream # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh index 89f99c5b2263a04db0ec3cdf0dceb8c6222e5cc0..ff0d93b9bdf3fef32ad05db3c9ae502c55a1d5d2 100755 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Open Vivado project GUI # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl index 494cd7810881671aff66e7cc4f554d94e713ebac..0be0f9519a9d276daac75ac96831b296572faed8 100644 --- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl +++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: Project management utilities # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh b/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh index 53b4b9941868b8d0d23745df36fcd87af0679d3a..39f2c785dbfc8a91296cffd5f41f2df0bc4c36ac 100755 --- a/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh +++ b/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: TCL script creating aliases for Vivado project management scripts # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 11:15:20 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc index d6bc42ef67e2ae015b88b7dc49e92e6bc483c341..c75ddeb46bfac220578813317c2ee8303d74f683 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc +++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc @@ -2,7 +2,7 @@ create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] @@ -11,195 +11,147 @@ set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 32 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][0]}]] +connect_debug_port u_ila_0/probe0 [get_nets [list {TXAxism2sVectorxD[1][DataxD][31]} {TXAxism2sVectorxD[1][DataxD][30]} {TXAxism2sVectorxD[1][DataxD][29]} {TXAxism2sVectorxD[1][DataxD][28]} {TXAxism2sVectorxD[1][DataxD][27]} {TXAxism2sVectorxD[1][DataxD][26]} {TXAxism2sVectorxD[1][DataxD][25]} {TXAxism2sVectorxD[1][DataxD][24]} {TXAxism2sVectorxD[1][DataxD][23]} {TXAxism2sVectorxD[1][DataxD][22]} {TXAxism2sVectorxD[1][DataxD][21]} {TXAxism2sVectorxD[1][DataxD][20]} {TXAxism2sVectorxD[1][DataxD][19]} {TXAxism2sVectorxD[1][DataxD][18]} {TXAxism2sVectorxD[1][DataxD][17]} {TXAxism2sVectorxD[1][DataxD][16]} {TXAxism2sVectorxD[1][DataxD][15]} {TXAxism2sVectorxD[1][DataxD][14]} {TXAxism2sVectorxD[1][DataxD][13]} {TXAxism2sVectorxD[1][DataxD][12]} {TXAxism2sVectorxD[1][DataxD][11]} {TXAxism2sVectorxD[1][DataxD][10]} {TXAxism2sVectorxD[1][DataxD][9]} {TXAxism2sVectorxD[1][DataxD][8]} {TXAxism2sVectorxD[1][DataxD][7]} {TXAxism2sVectorxD[1][DataxD][6]} {TXAxism2sVectorxD[1][DataxD][5]} {TXAxism2sVectorxD[1][DataxD][4]} {TXAxism2sVectorxD[1][DataxD][3]} {TXAxism2sVectorxD[1][DataxD][2]} {TXAxism2sVectorxD[1][DataxD][1]} {TXAxism2sVectorxD[1][DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 32 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][0]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {TXAxism2sVectorxD[2][DataxD][31]} {TXAxism2sVectorxD[2][DataxD][30]} {TXAxism2sVectorxD[2][DataxD][29]} {TXAxism2sVectorxD[2][DataxD][28]} {TXAxism2sVectorxD[2][DataxD][27]} {TXAxism2sVectorxD[2][DataxD][26]} {TXAxism2sVectorxD[2][DataxD][25]} {TXAxism2sVectorxD[2][DataxD][24]} {TXAxism2sVectorxD[2][DataxD][23]} {TXAxism2sVectorxD[2][DataxD][22]} {TXAxism2sVectorxD[2][DataxD][21]} {TXAxism2sVectorxD[2][DataxD][20]} {TXAxism2sVectorxD[2][DataxD][19]} {TXAxism2sVectorxD[2][DataxD][18]} {TXAxism2sVectorxD[2][DataxD][17]} {TXAxism2sVectorxD[2][DataxD][16]} {TXAxism2sVectorxD[2][DataxD][15]} {TXAxism2sVectorxD[2][DataxD][14]} {TXAxism2sVectorxD[2][DataxD][13]} {TXAxism2sVectorxD[2][DataxD][12]} {TXAxism2sVectorxD[2][DataxD][11]} {TXAxism2sVectorxD[2][DataxD][10]} {TXAxism2sVectorxD[2][DataxD][9]} {TXAxism2sVectorxD[2][DataxD][8]} {TXAxism2sVectorxD[2][DataxD][7]} {TXAxism2sVectorxD[2][DataxD][6]} {TXAxism2sVectorxD[2][DataxD][5]} {TXAxism2sVectorxD[2][DataxD][4]} {TXAxism2sVectorxD[2][DataxD][3]} {TXAxism2sVectorxD[2][DataxD][2]} {TXAxism2sVectorxD[2][DataxD][1]} {TXAxism2sVectorxD[2][DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 32 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][0]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {TXAxism2sVectorxD[0][DataxD][31]} {TXAxism2sVectorxD[0][DataxD][30]} {TXAxism2sVectorxD[0][DataxD][29]} {TXAxism2sVectorxD[0][DataxD][28]} {TXAxism2sVectorxD[0][DataxD][27]} {TXAxism2sVectorxD[0][DataxD][26]} {TXAxism2sVectorxD[0][DataxD][25]} {TXAxism2sVectorxD[0][DataxD][24]} {TXAxism2sVectorxD[0][DataxD][23]} {TXAxism2sVectorxD[0][DataxD][22]} {TXAxism2sVectorxD[0][DataxD][21]} {TXAxism2sVectorxD[0][DataxD][20]} {TXAxism2sVectorxD[0][DataxD][19]} {TXAxism2sVectorxD[0][DataxD][18]} {TXAxism2sVectorxD[0][DataxD][17]} {TXAxism2sVectorxD[0][DataxD][16]} {TXAxism2sVectorxD[0][DataxD][15]} {TXAxism2sVectorxD[0][DataxD][14]} {TXAxism2sVectorxD[0][DataxD][13]} {TXAxism2sVectorxD[0][DataxD][12]} {TXAxism2sVectorxD[0][DataxD][11]} {TXAxism2sVectorxD[0][DataxD][10]} {TXAxism2sVectorxD[0][DataxD][9]} {TXAxism2sVectorxD[0][DataxD][8]} {TXAxism2sVectorxD[0][DataxD][7]} {TXAxism2sVectorxD[0][DataxD][6]} {TXAxism2sVectorxD[0][DataxD][5]} {TXAxism2sVectorxD[0][DataxD][4]} {TXAxism2sVectorxD[0][DataxD][3]} {TXAxism2sVectorxD[0][DataxD][2]} {TXAxism2sVectorxD[0][DataxD][1]} {TXAxism2sVectorxD[0][DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 32 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][0]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {TXAxism2sVectorxD[3][DataxD][31]} {TXAxism2sVectorxD[3][DataxD][30]} {TXAxism2sVectorxD[3][DataxD][29]} {TXAxism2sVectorxD[3][DataxD][28]} {TXAxism2sVectorxD[3][DataxD][27]} {TXAxism2sVectorxD[3][DataxD][26]} {TXAxism2sVectorxD[3][DataxD][25]} {TXAxism2sVectorxD[3][DataxD][24]} {TXAxism2sVectorxD[3][DataxD][23]} {TXAxism2sVectorxD[3][DataxD][22]} {TXAxism2sVectorxD[3][DataxD][21]} {TXAxism2sVectorxD[3][DataxD][20]} {TXAxism2sVectorxD[3][DataxD][19]} {TXAxism2sVectorxD[3][DataxD][18]} {TXAxism2sVectorxD[3][DataxD][17]} {TXAxism2sVectorxD[3][DataxD][16]} {TXAxism2sVectorxD[3][DataxD][15]} {TXAxism2sVectorxD[3][DataxD][14]} {TXAxism2sVectorxD[3][DataxD][13]} {TXAxism2sVectorxD[3][DataxD][12]} {TXAxism2sVectorxD[3][DataxD][11]} {TXAxism2sVectorxD[3][DataxD][10]} {TXAxism2sVectorxD[3][DataxD][9]} {TXAxism2sVectorxD[3][DataxD][8]} {TXAxism2sVectorxD[3][DataxD][7]} {TXAxism2sVectorxD[3][DataxD][6]} {TXAxism2sVectorxD[3][DataxD][5]} {TXAxism2sVectorxD[3][DataxD][4]} {TXAxism2sVectorxD[3][DataxD][3]} {TXAxism2sVectorxD[3][DataxD][2]} {TXAxism2sVectorxD[3][DataxD][1]} {TXAxism2sVectorxD[3][DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 32 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][0]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {TXAxism2sVectorxD[4][DataxD][31]} {TXAxism2sVectorxD[4][DataxD][30]} {TXAxism2sVectorxD[4][DataxD][29]} {TXAxism2sVectorxD[4][DataxD][28]} {TXAxism2sVectorxD[4][DataxD][27]} {TXAxism2sVectorxD[4][DataxD][26]} {TXAxism2sVectorxD[4][DataxD][25]} {TXAxism2sVectorxD[4][DataxD][24]} {TXAxism2sVectorxD[4][DataxD][23]} {TXAxism2sVectorxD[4][DataxD][22]} {TXAxism2sVectorxD[4][DataxD][21]} {TXAxism2sVectorxD[4][DataxD][20]} {TXAxism2sVectorxD[4][DataxD][19]} {TXAxism2sVectorxD[4][DataxD][18]} {TXAxism2sVectorxD[4][DataxD][17]} {TXAxism2sVectorxD[4][DataxD][16]} {TXAxism2sVectorxD[4][DataxD][15]} {TXAxism2sVectorxD[4][DataxD][14]} {TXAxism2sVectorxD[4][DataxD][13]} {TXAxism2sVectorxD[4][DataxD][12]} {TXAxism2sVectorxD[4][DataxD][11]} {TXAxism2sVectorxD[4][DataxD][10]} {TXAxism2sVectorxD[4][DataxD][9]} {TXAxism2sVectorxD[4][DataxD][8]} {TXAxism2sVectorxD[4][DataxD][7]} {TXAxism2sVectorxD[4][DataxD][6]} {TXAxism2sVectorxD[4][DataxD][5]} {TXAxism2sVectorxD[4][DataxD][4]} {TXAxism2sVectorxD[4][DataxD][3]} {TXAxism2sVectorxD[4][DataxD][2]} {TXAxism2sVectorxD[4][DataxD][1]} {TXAxism2sVectorxD[4][DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 32 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][0]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {TXAxism2sVectorxD[5][DataxD][31]} {TXAxism2sVectorxD[5][DataxD][30]} {TXAxism2sVectorxD[5][DataxD][29]} {TXAxism2sVectorxD[5][DataxD][28]} {TXAxism2sVectorxD[5][DataxD][27]} {TXAxism2sVectorxD[5][DataxD][26]} {TXAxism2sVectorxD[5][DataxD][25]} {TXAxism2sVectorxD[5][DataxD][24]} {TXAxism2sVectorxD[5][DataxD][23]} {TXAxism2sVectorxD[5][DataxD][22]} {TXAxism2sVectorxD[5][DataxD][21]} {TXAxism2sVectorxD[5][DataxD][20]} {TXAxism2sVectorxD[5][DataxD][19]} {TXAxism2sVectorxD[5][DataxD][18]} {TXAxism2sVectorxD[5][DataxD][17]} {TXAxism2sVectorxD[5][DataxD][16]} {TXAxism2sVectorxD[5][DataxD][15]} {TXAxism2sVectorxD[5][DataxD][14]} {TXAxism2sVectorxD[5][DataxD][13]} {TXAxism2sVectorxD[5][DataxD][12]} {TXAxism2sVectorxD[5][DataxD][11]} {TXAxism2sVectorxD[5][DataxD][10]} {TXAxism2sVectorxD[5][DataxD][9]} {TXAxism2sVectorxD[5][DataxD][8]} {TXAxism2sVectorxD[5][DataxD][7]} {TXAxism2sVectorxD[5][DataxD][6]} {TXAxism2sVectorxD[5][DataxD][5]} {TXAxism2sVectorxD[5][DataxD][4]} {TXAxism2sVectorxD[5][DataxD][3]} {TXAxism2sVectorxD[5][DataxD][2]} {TXAxism2sVectorxD[5][DataxD][1]} {TXAxism2sVectorxD[5][DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 32 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][0]}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {TXAxism2sVectorxD[6][DataxD][31]} {TXAxism2sVectorxD[6][DataxD][30]} {TXAxism2sVectorxD[6][DataxD][29]} {TXAxism2sVectorxD[6][DataxD][28]} {TXAxism2sVectorxD[6][DataxD][27]} {TXAxism2sVectorxD[6][DataxD][26]} {TXAxism2sVectorxD[6][DataxD][25]} {TXAxism2sVectorxD[6][DataxD][24]} {TXAxism2sVectorxD[6][DataxD][23]} {TXAxism2sVectorxD[6][DataxD][22]} {TXAxism2sVectorxD[6][DataxD][21]} {TXAxism2sVectorxD[6][DataxD][20]} {TXAxism2sVectorxD[6][DataxD][19]} {TXAxism2sVectorxD[6][DataxD][18]} {TXAxism2sVectorxD[6][DataxD][17]} {TXAxism2sVectorxD[6][DataxD][16]} {TXAxism2sVectorxD[6][DataxD][15]} {TXAxism2sVectorxD[6][DataxD][14]} {TXAxism2sVectorxD[6][DataxD][13]} {TXAxism2sVectorxD[6][DataxD][12]} {TXAxism2sVectorxD[6][DataxD][11]} {TXAxism2sVectorxD[6][DataxD][10]} {TXAxism2sVectorxD[6][DataxD][9]} {TXAxism2sVectorxD[6][DataxD][8]} {TXAxism2sVectorxD[6][DataxD][7]} {TXAxism2sVectorxD[6][DataxD][6]} {TXAxism2sVectorxD[6][DataxD][5]} {TXAxism2sVectorxD[6][DataxD][4]} {TXAxism2sVectorxD[6][DataxD][3]} {TXAxism2sVectorxD[6][DataxD][2]} {TXAxism2sVectorxD[6][DataxD][1]} {TXAxism2sVectorxD[6][DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 32 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][0]}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {WestRXM2SxD[DataxD][31]} {WestRXM2SxD[DataxD][30]} {WestRXM2SxD[DataxD][29]} {WestRXM2SxD[DataxD][28]} {WestRXM2SxD[DataxD][27]} {WestRXM2SxD[DataxD][26]} {WestRXM2SxD[DataxD][25]} {WestRXM2SxD[DataxD][24]} {WestRXM2SxD[DataxD][23]} {WestRXM2SxD[DataxD][22]} {WestRXM2SxD[DataxD][21]} {WestRXM2SxD[DataxD][20]} {WestRXM2SxD[DataxD][19]} {WestRXM2SxD[DataxD][18]} {WestRXM2SxD[DataxD][17]} {WestRXM2SxD[DataxD][16]} {WestRXM2SxD[DataxD][15]} {WestRXM2SxD[DataxD][14]} {WestRXM2SxD[DataxD][13]} {WestRXM2SxD[DataxD][12]} {WestRXM2SxD[DataxD][11]} {WestRXM2SxD[DataxD][10]} {WestRXM2SxD[DataxD][9]} {WestRXM2SxD[DataxD][8]} {WestRXM2SxD[DataxD][7]} {WestRXM2SxD[DataxD][6]} {WestRXM2SxD[DataxD][5]} {WestRXM2SxD[DataxD][4]} {WestRXM2SxD[DataxD][3]} {WestRXM2SxD[DataxD][2]} {WestRXM2SxD[DataxD][1]} {WestRXM2SxD[DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 32 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][0]}]] +connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 32 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][0]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list ScalpPacketValid12xS]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -set_property port_width 32 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][0]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {TXAxism2sVectorxD[0][LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -set_property port_width 32 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][0]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {TXAxism2sVectorxD[0][ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] -set_property port_width 32 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][0]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list {TXAxism2sVectorxD[1][LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] -set_property port_width 32 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][0]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {TXAxism2sVectorxD[1][ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]}]] +connect_debug_port u_ila_0/probe14 [get_nets [list {TXAxism2sVectorxD[2][LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]}]] +connect_debug_port u_ila_0/probe15 [get_nets [list {TXAxism2sVectorxD[2][ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]}]] +connect_debug_port u_ila_0/probe16 [get_nets [list {TXAxism2sVectorxD[3][LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]}]] +connect_debug_port u_ila_0/probe17 [get_nets [list {TXAxism2sVectorxD[3][ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]}]] +connect_debug_port u_ila_0/probe18 [get_nets [list {TXAxism2sVectorxD[4][LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]}]] +connect_debug_port u_ila_0/probe19 [get_nets [list {TXAxism2sVectorxD[4][ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]}]] +connect_debug_port u_ila_0/probe20 [get_nets [list {TXAxism2sVectorxD[5][LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]}]] +connect_debug_port u_ila_0/probe21 [get_nets [list {TXAxism2sVectorxD[5][ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]}]] +connect_debug_port u_ila_0/probe22 [get_nets [list {TXAxism2sVectorxD[6][LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 1 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]}]] +connect_debug_port u_ila_0/probe23 [get_nets [list {TXAxism2sVectorxD[6][ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 1 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]}]] +connect_debug_port u_ila_0/probe24 [get_nets [list {TXAxiss2mVectorxD[0][ReadyxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 1 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[LastxS]}]] +connect_debug_port u_ila_0/probe25 [get_nets [list {TXAxiss2mVectorxD[1][ReadyxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 1 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]}]] +connect_debug_port u_ila_0/probe26 [get_nets [list {TXAxiss2mVectorxD[2][ReadyxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]}]] +connect_debug_port u_ila_0/probe27 [get_nets [list {TXAxiss2mVectorxD[3][ReadyxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]}]] +connect_debug_port u_ila_0/probe28 [get_nets [list {TXAxiss2mVectorxD[4][ReadyxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]}]] +connect_debug_port u_ila_0/probe29 [get_nets [list {TXAxiss2mVectorxD[5][ReadyxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]}]] +connect_debug_port u_ila_0/probe30 [get_nets [list {TXAxiss2mVectorxD[6][ReadyxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]}]] +connect_debug_port u_ila_0/probe31 [get_nets [list {WestRXM2SxD[LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]}]] +connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[LastxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]}]] +connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]}]] +connect_debug_port u_ila_0/probe34 [get_nets [list {WestRXM2SxD[ValidxS]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] -set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] -set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] -set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] -set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[LastxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] -set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] -set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] -set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] -set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] -set_property port_width 1 [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] -set_property port_width 1 [get_debug_ports u_ila_0/probe45] -connect_debug_port u_ila_0/probe45 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] -set_property port_width 1 [get_debug_ports u_ila_0/probe46] -connect_debug_port u_ila_0/probe46 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] -set_property port_width 1 [get_debug_ports u_ila_0/probe47] -connect_debug_port u_ila_0/probe47 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]}]] +connect_debug_port u_ila_0/probe35 [get_nets [list {WestRXS2MxD[ReadyxS]}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc index 1ab8b938a8197e73502590feb7436461de582db7..876688bb5f03ebd31babcef8db2513601d750c40 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc +++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc @@ -252,3 +252,5 @@ set_operating_conditions -airflow 0 -heatsink none -board small + + diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc index dcb4ac7fd43cee4521aacf3bb794d2189871b549..c646d10e2ccd5e104700a879f84a8d780765d6bb 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc +++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc @@ -32,3 +32,5 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI] + + diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd index bc51fd4fedf22debe98c02f21d425fb73e206985..aa87b19317858832a0258dca476db165aba1ffcd 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd +++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd @@ -15,7 +15,7 @@ -- Tool version: 2020.2 -- Description: scalp_firmware -- --- Last update: 2021-05-19 +-- Last update: 2021-06-08 -- --------------------------------------------------------------------------------- @@ -442,16 +442,51 @@ architecture arch of scalp_firmware is signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS); -- signal ScalpRouterReadyxD : t_scalp_router_ready := C_NO_SCALP_ROUTER_READY; -- Scalp Axi Lite interface and IRQ - signal InterruptxS : std_ulogic := '0'; - signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0'); - signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); - signal RdValidxS : std_ulogic := '0'; - signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0'); - signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); - signal WrValidxS : std_ulogic := '0'; + signal ScalpPacketWriteDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal ScalpPacketReadDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal ScalpPacketCtrlxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal ScalpPacketStatusxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal RXRdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal RXWrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal TXRdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal TXWrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal LocNetAddrVectxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal RXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS; + signal TXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS; + signal TXFifoRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; + signal TXFifoRXS2MxS : t_axi4s2m := C_NO_AXI4_S2M; + signal RXFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; + signal RXFifoTXS2MxS : t_axi4s2m := C_NO_AXI4_S2M; -- Zynq Reg Bank -- type t_status_send_word is (E_IDLE, E_SEND); + type t_tx_fifo_wr_data_states is (E_WR_IDLE, E_WR_H0, E_WR_H1, E_WR_H2, E_WR_PLD, E_WR_NEXT); + type t_rx_fifo_rd_data_states is (E_RD_IDLE, E_RD_WORD, E_RD_NEXT); + + constant C_WR_VALID : integer range 0 to 255 := 0; + constant C_WR_LAST : integer range 0 to 255 := 1; + constant C_WR_READY : integer range 0 to 255 := 2; + constant C_WR_NEXT : integer range 0 to 255 := 3; + constant C_RESET_ALL_FIFO : integer range 0 to 255 := 4; + constant C_WR_H0 : integer range 0 to 255 := 5; + constant C_WR_H1 : integer range 0 to 255 := 6; + constant C_WR_H2 : integer range 0 to 255 := 7; + constant C_WR_PLD : integer range 0 to 255 := 8; + constant C_WR_NEW_PACKET : integer range 0 to 255 := 9; + constant C_RD_NEXT : integer range 0 to 255 := 10; + constant C_RD_NEW_PACKET : integer range 0 to 255 := 11; + -- + constant C_RD_VALID : integer range 0 to 255 := 0; + constant C_RD_LAST : integer range 0 to 255 := 1; + constant C_TX_PROG_FULL : integer range 0 to 255 := 2; + constant C_RX_PROG_FULL : integer range 0 to 255 := 3; + constant C_RD_WAIT_NEXT : integer range 0 to 255 := 4; + + signal TXFifoWrDataStatexD : t_tx_fifo_wr_data_states := E_WR_IDLE; + signal TXFifoWrDataStateNextxD : t_tx_fifo_wr_data_states := E_WR_IDLE; + signal RXFifoRdDataStatexD : t_rx_fifo_rd_data_states := E_RD_IDLE; + signal RXFifoRdDataStateNextxD : t_rx_fifo_rd_data_states := E_RD_IDLE; + -- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE; -- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE; -- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE; @@ -517,19 +552,23 @@ architecture arch of scalp_firmware is signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET; -- Attributes - attribute mark_debug : string; - attribute keep : string; + attribute mark_debug : string; + attribute keep : string; -- Clocks - attribute keep of PSSysClkxC : signal is "true"; - attribute keep of GTRefClk0xC : signal is "true"; - attribute keep of GTRefClk1xC : signal is "true"; - attribute keep of AuroraClkSlavexC : signal is "true"; - attribute keep of AuroraClkMasterxC : signal is "true"; + attribute keep of PSSysClkxC : signal is "true"; + attribute keep of GTRefClk0xC : signal is "true"; + attribute keep of GTRefClk1xC : signal is "true"; + attribute keep of AuroraClkSlavexC : signal is "true"; + attribute keep of AuroraClkMasterxC : signal is "true"; -- Scalp Router - attribute mark_debug of WestRXM2SxD : signal is "true"; - attribute keep of WestRXM2SxD : signal is "true"; - attribute mark_debug of WestRXS2MxD : signal is "true"; - attribute keep of WestRXS2MxD : signal is "true"; + -- attribute mark_debug of WestRXM2SxD : signal is "true"; + -- attribute keep of WestRXM2SxD : signal is "true"; + -- attribute mark_debug of WestRXS2MxD : signal is "true"; + -- attribute keep of WestRXS2MxD : signal is "true"; + -- attribute mark_debug of TXAxism2sVectorxD : signal is "true"; + -- attribute keep of TXAxism2sVectorxD : signal is "true"; + -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true"; + -- attribute keep of TXAxiss2mVectorxD : signal is "true"; -- attribute mark_debug of RXAxism2sVectorxD : signal is "true"; -- attribute keep of RXAxism2sVectorxD : signal is "true"; -- attribute mark_debug of RXAxiss2mVectorxD : signal is "true"; @@ -555,46 +594,50 @@ begin ZynqxI : entity work.scalp_zynqps_wrapper port map ( -- Processor interface - FIXED_IO_ps_clk => PSClkxCIO, - FIXED_IO_ps_porb => PSPorxSNIO, - FIXED_IO_ps_srstb => PSSRstxRNIO, - FclkClk0xCO => PSSysClkxC, - FclkReset0xRO => PSSysResetxR, + FIXED_IO_ps_clk => PSClkxCIO, + FIXED_IO_ps_porb => PSPorxSNIO, + FIXED_IO_ps_srstb => PSSRstxRNIO, + FclkClk0xCO => PSSysClkxC, + FclkReset0xRO => PSSysResetxR, -- DDR interface - DDR_addr => DDRAddrxDIO, - DDR_ba => DDRBankAddrxDIO, - DDR_cas_n => DDRCasNxSIO, - DDR_ck_n => DDRClkNxCIO, - DDR_ck_p => DDRClkPxCIO, - DDR_cke => DDRCkexSIO, - DDR_cs_n => DDRCsNxSIO, - DDR_dm => DDRDmxDIO, - DDR_dq => DDRDqxDIO, - DDR_dqs_n => DDRDqsNxDIO, - DDR_dqs_p => DDRDqsPxDIO, - DDR_odt => DDROdtxSIO, - DDR_ras_n => DDRRasNxSIO, - DDR_reset_n => DDRDRstxRNIO, - DDR_we_n => DDRWexSNIO, - FIXED_IO_ddr_vrn => DDRVrNxSIO, - FIXED_IO_ddr_vrp => DDRVrPxSIO, + DDR_addr => DDRAddrxDIO, + DDR_ba => DDRBankAddrxDIO, + DDR_cas_n => DDRCasNxSIO, + DDR_ck_n => DDRClkNxCIO, + DDR_ck_p => DDRClkPxCIO, + DDR_cke => DDRCkexSIO, + DDR_cs_n => DDRCsNxSIO, + DDR_dm => DDRDmxDIO, + DDR_dq => DDRDqxDIO, + DDR_dqs_n => DDRDqsNxDIO, + DDR_dqs_p => DDRDqsPxDIO, + DDR_odt => DDROdtxSIO, + DDR_ras_n => DDRRasNxSIO, + DDR_reset_n => DDRDRstxRNIO, + DDR_we_n => DDRWexSNIO, + FIXED_IO_ddr_vrn => DDRVrNxSIO, + FIXED_IO_ddr_vrp => DDRVrPxSIO, -- USB interface - Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI, + Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI, -- SPI1 used as uWire master. Clk, Data and LE signals are outputs -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS - Spi1MOSIxSO => Pll2V5DatauWirexSO, - Spi1SSxSO => Pll2V5LEuWirexSO, - Spi1SclkxCO => Pll2V5ClkuWirexCO, + Spi1MOSIxSO => Pll2V5DatauWirexSO, + Spi1SSxSO => Pll2V5LEuWirexSO, + Spi1SclkxCO => Pll2V5ClkuWirexCO, -- MIO - FIXED_IO_mio => MIOxDIO, + FIXED_IO_mio => MIOxDIO, -- Scalp Axi Lite interface and IRQ - InterruptxSI => InterruptxS, - RdAddrxDO => RdAddrxD, - RdDataxDI => RdDataxD, - RdValidxSO => RdValidxS, - WrAddrxDO => WrAddrxD, - WrDataxDO => WrDataxD, - WrValidxSO => WrValidxS); + Irq0xDI => (others => '0'), + ScalpPacketWriteDataxDO => ScalpPacketWriteDataxD, + ScalpPacketReadDataxDI => ScalpPacketReadDataxD, + ScalpPacketCtrlxDO => ScalpPacketCtrlxD, + ScalpPacketStatusxDI => ScalpPacketStatusxD, + RXRdDataCntxDI => RXRdDataCntxD, + RXWrDataCntxDI => RXWrDataCntxD, + TXRdDataCntxDI => TXRdDataCntxD, + TXWrDataCntxDI => TXWrDataCntxD, + LocNetAddrxDO => LocNetAddrVectxD, + RgbLedsCtrlPortxDO => open); end block ProcessingSystemxB; @@ -900,8 +943,8 @@ begin -- Scalp Packet -- attribute mark_debug of ScalpPacket0xD : signal is "true"; -- attribute keep of ScalpPacket0xD : signal is "true"; - attribute mark_debug of ScalpPacketValid12xS : signal is "true"; - attribute keep of ScalpPacketValid12xS : signal is "true"; + -- attribute mark_debug of ScalpPacketValid12xS : signal is "true"; + -- attribute keep of ScalpPacketValid12xS : signal is "true"; -- attribute mark_debug of ScalpPacketLocalxD : signal is "true"; -- attribute keep of ScalpPacketLocalxD : signal is "true"; -- VIO @@ -1057,42 +1100,190 @@ begin -- end block ScalpRouterReadyxB; -- Local Router Net Addr - LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_210; + -- LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_210; + LocNetAddrXxAS : LocNetAddrxD.XxD <= to_integer(unsigned(LocNetAddrVectxD(7 downto 0))); + LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocNetAddrVectxD(15 downto 8))); + LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocNetAddrVectxD(23 downto 16))); -- TX Side - NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID); - EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID); - SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID); - WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID); - NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD; - EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD; - SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD; - WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD; + NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID); + EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID); + SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID); + WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID); + NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD; + EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD; + SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD; + WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD; -- RX Side - NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD; - EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD; - SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD; - WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD; - NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID); - EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID); - SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID); - WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID); + NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD; + EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD; + SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD; + WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD; + NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID); + EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID); + SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID); + WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID); WrSpValidxI : entity work.vio_axi_cnt_ctrl port map ( clk => AuroraClkMasterxC.UserClkxC, probe_out0(0) => VioWrSpValidxS); - ScalpSP2AxisLocalxI : entity work.scalp_sp_to_axis - generic map ( - C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE) + TXFifoStatusWrDataCntxAS : TXWrDataCntxD <= TXFifoStatusxD.WrDataCntxD; + TXFifoStatusRdDataCntxAS : TXRdDataCntxD <= TXFifoStatusxD.RdDataCntxD; + TXFifoStatusProgFullxAS : ScalpPacketStatusxD(C_TX_PROG_FULL) <= TXFifoStatusxD.ProgFullxS; + + TXFifoWrDataxP : process (AuroraClkMasterxC.UserClkxC, + ScalpRouterResetxRNA) is + begin -- process TXFifoWrDataxP + if ScalpRouterResetxRNA = '0' then + TXFifoRXM2SxD <= C_NO_AXI4_M2S; + TXFifoWrDataStatexD <= E_WR_IDLE; + TXFifoWrDataStateNextxD <= E_WR_IDLE; + elsif rising_edge(AuroraClkMasterxC.UserClkxC) then + -- Default Values + TXFifoRXM2SxD <= C_NO_AXI4_M2S; + TXFifoWrDataStatexD <= TXFifoWrDataStatexD; + TXFifoWrDataStateNextxD <= TXFifoWrDataStateNextxD; + + case TXFifoWrDataStatexD is + when E_WR_IDLE => + if ScalpPacketCtrlxD(C_WR_NEW_PACKET) = '1' then + TXFifoWrDataStatexD <= E_WR_H0; + end if; + + when E_WR_H0 => + if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then + TXFifoRXM2SxD.DataxD <= scalp_sp_h0_to_axis_ul(ScalpPacketWriteDataxD(31 downto 24), + ScalpPacketWriteDataxD(23 downto 16), + ScalpPacketWriteDataxD(15 downto 8), + ScalpPacketWriteDataxD(7 downto 0)); + TXFifoRXM2SxD.ValidxS <= '1'; + TXFifoWrDataStatexD <= E_WR_NEXT; + TXFifoWrDataStateNextxD <= E_WR_H1; + end if; + + when E_WR_H1 => + if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then + TXFifoRXM2SxD.DataxD <= scalp_sp_h1_to_axis_ul(ScalpPacketWriteDataxD(31 downto 24), + ScalpPacketWriteDataxD(23 downto 16), + ScalpPacketWriteDataxD(15 downto 8)); + TXFifoRXM2SxD.ValidxS <= '1'; + TXFifoWrDataStatexD <= E_WR_NEXT; + TXFifoWrDataStateNextxD <= E_WR_H2; + end if; + + when E_WR_H2 => + if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then + TXFifoRXM2SxD.DataxD <= scalp_sp_h2_to_axis_ul(ScalpPacketWriteDataxD(31 downto 16)); + TXFifoRXM2SxD.ValidxS <= '1'; + TXFifoWrDataStatexD <= E_WR_NEXT; + TXFifoWrDataStateNextxD <= E_WR_PLD; + end if; + + when E_WR_PLD => + if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then + TXFifoRXM2SxD.DataxD <= scalp_sp_p_to_axis_ul(ScalpPacketWriteDataxD); + TXFifoRXM2SxD.ValidxS <= '1'; + TXFifoWrDataStatexD <= E_WR_NEXT; + + if ScalpPacketCtrlxD(C_WR_LAST) = '1' then + TXFifoRXM2SxD.LastxS <= '1'; + TXFifoWrDataStateNextxD <= E_WR_IDLE; + else + TXFifoWrDataStateNextxD <= E_WR_PLD; + end if; + end if; + + when E_WR_NEXT => + if ScalpPacketCtrlxD(C_WR_NEXT) = '1' and ScalpPacketCtrlxD(C_WR_VALID) = '0' then + TXFifoWrDataStatexD <= TXFifoWrDataStateNextxD; + end if; + + when others => null; + end case; + end if; + end process TXFifoWrDataxP; + + -- TX Fifo + ScalpAxisFifoWrapperTXxI : entity work.scalp_axis_fifo_wrapper port map ( - SysClkxCI => AuroraClkMasterxC.UserClkxC, - SysRstxRNAI => ScalpRouterResetxRNA, - ScalpPacketxDI => ScalpPacket0xD, - ScalpPacketValidxSI => ScalpPacketValid12xS, - ScalpAxism2sxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID), - ScalpAxiss2mxDI => RXAxiss2mVectorxD(C_LOCAL_IF_ID), - ScalpRdyxSO => open); + ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC, + ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC, + ResetxRI.RstxRAN => ScalpRouterResetxRNA, + RXM2SxDI => TXFifoRXM2SxD, + RXS2MxSO => TXFifoRXS2MxS, + TXM2SxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID), + TXS2MxSI => RXAxiss2mVectorxD(C_LOCAL_IF_ID), + FifoStatusxDO => TXFifoStatusxD); + + RXFifoStatusWrDataCntxAS : RXWrDataCntxD <= RXFifoStatusxD.WrDataCntxD; + RXFifoStatusRdDataCntxAS : RXRdDataCntxD <= RXFifoStatusxD.RdDataCntxD; + RXFifoStatusProgFullxAS : ScalpPacketStatusxD(C_RX_PROG_FULL) <= RXFifoStatusxD.ProgFullxS; + + RXFifoRdDataxP : process (AuroraClkMasterxC.UserClkxC, + ScalpRouterResetxRNA) is + begin -- process RXFifoRdDataxP + if ScalpRouterResetxRNA = '0' then + RXFifoRdDataStatexD <= E_RD_IDLE; + RXFifoRdDataStateNextxD <= E_RD_IDLE; + ScalpPacketReadDataxD <= (others => '0'); + ScalpPacketStatusxD(C_RD_VALID) <= '0'; + ScalpPacketStatusxD(C_RD_LAST) <= '0'; + elsif rising_edge(AuroraClkMasterxC.UserClkxC) then + -- Default Values + RXFifoTXS2MxS.ReadyxS <= '0'; + ScalpPacketReadDataxD <= (others => '0'); + ScalpPacketStatusxD(C_RD_VALID) <= '0'; + ScalpPacketStatusxD(C_RD_LAST) <= ScalpPacketStatusxD(C_RD_LAST); + ScalpPacketStatusxD(C_RD_WAIT_NEXT) <= '0'; + RXFifoRdDataStatexD <= RXFifoRdDataStatexD; + RXFifoRdDataStateNextxD <= RXFifoRdDataStateNextxD; + + case RXFifoRdDataStatexD is + when E_RD_IDLE => + if ScalpPacketCtrlxD(C_RD_NEW_PACKET) = '1' then + ScalpPacketStatusxD(C_RD_LAST) <= '0'; + end if; + + when E_RD_WORD => + if RXFifoTXM2SxD.ValidxS = '1' and ScalpPacketCtrlxD(C_RD_NEXT) = '0' then + RXFifoTXS2MxS.ReadyxS <= '1'; + ScalpPacketReadDataxD <= TXFifoRXM2SxD.DataxD; + ScalpPacketStatusxD(C_RD_VALID) <= '1'; + RXFifoRdDataStatexD <= E_RD_NEXT; + RXFifoRdDataStateNextxD <= E_RD_WORD; + + if RXFifoTXM2SxD.LastxS = '1' then + ScalpPacketStatusxD(C_RD_LAST) <= '1'; + RXFifoRdDataStateNextxD <= E_RD_IDLE; + end if; + end if; + + when E_RD_NEXT => + ScalpPacketReadDataxD <= TXFifoRXM2SxD.DataxD; + ScalpPacketStatusxD(C_RD_VALID) <= '1'; + ScalpPacketStatusxD(C_RD_WAIT_NEXT) <= '1'; + + if ScalpPacketCtrlxD(C_RD_NEXT) = '1' then + RXFifoRdDataStatexD <= RXFifoRdDataStateNextxD; + end if; + + when others => null; + end case; + end if; + end process RXFifoRdDataxP; + + -- RX Fifo + ScalpAxisFifoWrapperRXxI : entity work.scalp_axis_fifo_wrapper + port map ( + ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC, + ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC, + ResetxRI.RstxRAN => ScalpRouterResetxRNA, + RXM2SxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID), + RXS2MxSO => TXAxiss2mVectorxD(C_LOCAL_IF_ID), + TXM2SxDO => RXFifoTXM2SxD, + TXS2MxSI => RXFifoTXS2MxS, + FifoStatusxDO => RXFifoStatusxD); ScalpRouterxI : entity work.scalp_router generic map ( @@ -1108,1139 +1299,89 @@ begin TXAxiss2mVectorxDI => TXAxiss2mVectorxD, QoSVectorxDI => QoSVectorxD); - ScalpAxis2SPxI : entity work.scalp_axis_to_sp - generic map ( - C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE, - C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY) - port map ( - SysClkxCI => AuroraClkMasterxC.UserClkxC, - SysRstxRNAI => ScalpRouterResetxRNA, - ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID), - ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID), - ScalpPacketxDO => ScalpPacketLocalxD, - ScalpPacketValidxSO => ScalpPacketValidLocalxS); - - WritePacketxB : block is - begin -- block WritePacketxB - - UpdateRegxP : process (AuroraClkMasterxC.UserClkxC, - ScalpRouterResetxRNA) is - begin -- process UpdateRegxP - if ScalpRouterResetxRNA = '0' then - WrSPStatexDP <= E_WR_SP_IDLE; - elsif rising_edge(AuroraClkMasterxC.UserClkxC) then - WrSPStatexDP <= WrSPStatexDN; - end if; - end process UpdateRegxP; - - SpValidxP : process (RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS, - VioWrSpValidxS, WrSPStatexDP) is - begin -- process SpValidxP - -- Default values - WrSPStatexDN <= WrSPStatexDP; - ScalpPacketValid12xS <= '0'; - - case WrSPStatexDP is - when E_WR_SP_IDLE => - if VioWrSpValidxS = '1' then - ScalpPacketValid12xS <= '1'; - WrSPStatexDN <= E_WR_SP_VALID_0; - end if; - - when E_WR_SP_VALID_0 => - ScalpPacketValid12xS <= '0'; - WrSPStatexDN <= E_WR_SP_LAST_0; - - when E_WR_SP_LAST_0 => - if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then - WrSPStatexDN <= E_WR_SP_LAST_1; - end if; - - when E_WR_SP_LAST_1 => - if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then - ScalpPacketValid12xS <= '1'; - WrSPStatexDN <= E_WR_SP_VALID_1; - end if; - - when E_WR_SP_VALID_1 => - ScalpPacketValid12xS <= '0'; - WrSPStatexDN <= E_WR_SP_WAIT; - - when E_WR_SP_WAIT => - if VioWrSpValidxS = '0' then - WrSPStatexDN <= E_WR_SP_IDLE; - end if; - - when others => null; - end case; - end process SpValidxP; - - end block WritePacketxB; + -- ScalpSP2AxisLocalxI : entity work.scalp_sp_to_axis + -- generic map ( + -- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE) + -- port map ( + -- SysClkxCI => AuroraClkMasterxC.UserClkxC, + -- SysRstxRNAI => ScalpRouterResetxRNA, + -- ScalpPacketxDI => ScalpPacket0xD, + -- ScalpPacketValidxSI => ScalpPacketValid12xS, + -- ScalpAxism2sxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID), + -- ScalpAxiss2mxDI => RXAxiss2mVectorxD(C_LOCAL_IF_ID), + -- ScalpRdyxSO => open); + + -- ScalpAxis2SPxI : entity work.scalp_axis_to_sp + -- generic map ( + -- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE, + -- C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY) + -- port map ( + -- SysClkxCI => AuroraClkMasterxC.UserClkxC, + -- SysRstxRNAI => ScalpRouterResetxRNA, + -- ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID), + -- ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID), + -- ScalpPacketxDO => ScalpPacketLocalxD, + -- ScalpPacketValidxSO => ScalpPacketValidLocalxS); + + -- WritePacketxB : block is + -- begin -- block WritePacketxB + + -- UpdateRegxP : process (AuroraClkMasterxC.UserClkxC, + -- ScalpRouterResetxRNA) is + -- begin -- process UpdateRegxP + -- if ScalpRouterResetxRNA = '0' then + -- WrSPStatexDP <= E_WR_SP_IDLE; + -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then + -- WrSPStatexDP <= WrSPStatexDN; + -- end if; + -- end process UpdateRegxP; + + -- SpValidxP : process (RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS, + -- VioWrSpValidxS, WrSPStatexDP) is + -- begin -- process SpValidxP + -- -- Default values + -- WrSPStatexDN <= WrSPStatexDP; + -- ScalpPacketValid12xS <= '0'; + + -- case WrSPStatexDP is + -- when E_WR_SP_IDLE => + -- if VioWrSpValidxS = '1' then + -- ScalpPacketValid12xS <= '1'; + -- WrSPStatexDN <= E_WR_SP_VALID_0; + -- end if; + + -- when E_WR_SP_VALID_0 => + -- ScalpPacketValid12xS <= '0'; + -- WrSPStatexDN <= E_WR_SP_LAST_0; + + -- when E_WR_SP_LAST_0 => + -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then + -- WrSPStatexDN <= E_WR_SP_LAST_1; + -- end if; + + -- when E_WR_SP_LAST_1 => + -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then + -- ScalpPacketValid12xS <= '1'; + -- WrSPStatexDN <= E_WR_SP_VALID_1; + -- end if; + + -- when E_WR_SP_VALID_1 => + -- ScalpPacketValid12xS <= '0'; + -- WrSPStatexDN <= E_WR_SP_WAIT; + + -- when E_WR_SP_WAIT => + -- if VioWrSpValidxS = '0' then + -- WrSPStatexDN <= E_WR_SP_IDLE; + -- end if; + + -- when others => null; + -- end case; + -- end process SpValidxP; + + -- end block WritePacketxB; end block NetworkLayerxB; - ZynqRegBankxB : block is - begin -- block ZynqRegBankxB - - RegBankxB : block is - begin -- block RegBankxB - - WriteRegPortxP : process (NorthCtrlRegPortxDP, WrAddrxD, - WrDataxD, WrValidxS) is - begin -- process WriteRegPortxP - -- North - NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP; - -- NorthWrDataRegPortxDN <= NorthWrDataRegPortxDP; - -- -- East - -- EastCtrlRegPortxDN <= EastCtrlRegPortxDP; - -- EastWrDataRegPortxDN <= EastWrDataRegPortxDP; - -- -- South - -- SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP; - -- SouthWrDataRegPortxDN <= SouthWrDataRegPortxDP; - -- -- West - -- WestCtrlRegPortxDN <= WestCtrlRegPortxDP; - -- WestWrDataRegPortxDN <= WestWrDataRegPortxDP; - - if WrValidxS = '1' then - case WrAddrxD is - -- Ctrl - -- North - when x"000" => NorthCtrlRegPortxDN <= WrDataxD; - when x"004" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP or WrDataxD; - when x"008" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP and not WrDataxD; - -- East - -- when x"00c" => EastCtrlRegPortxDN <= WrDataxD; - -- when x"010" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP or WrDataxD; - -- when x"014" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP and not WrDataxD; - -- -- South - -- when x"018" => SouthCtrlRegPortxDN <= WrDataxD; - -- when x"01c" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP or WrDataxD; - -- when x"020" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP and not WrDataxD; - -- -- East - -- when x"024" => WestCtrlRegPortxDN <= WrDataxD; - -- when x"028" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP or WrDataxD; - -- when x"02c" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP and not WrDataxD; - -- -- Data - -- -- North - -- when x"030" => NorthWrDataRegPortxDN <= WrDataxD; - -- -- East - -- when x"034" => EastWrDataRegPortxDN <= WrDataxD; - -- -- South - -- when x"038" => SouthWrDataRegPortxDN <= WrDataxD; - -- -- West - -- when x"03c" => WestWrDataRegPortxDN <= WrDataxD; - when others => null; - end case; - end if; - end process WriteRegPortxP; - - ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is - begin -- process ReadRegPortxP - if PSSysResetxR = '1' then - RdDataxD <= (others => '0'); - elsif rising_edge(PSSysClkxC) then - RdDataxD <= (others => '0'); - - if RdValidxS = '1' then - case RdAddrxD is - when x"000" => RdDataxD <= NorthCtrlRegPortxDP; - -- when x"00C" => RdDataxD <= EastCtrlRegPortxDP; - -- when x"018" => RdDataxD <= SouthCtrlRegPortxDP; - -- when x"024" => RdDataxD <= WestCtrlRegPortxDP; - -- when x"030" => RdDataxD <= NorthWrDataRegPortxDP; - -- when x"034" => RdDataxD <= EastWrDataRegPortxDP; - -- when x"038" => RdDataxD <= SouthWrDataRegPortxDP; - -- when x"03c" => RdDataxD <= WestWrDataRegPortxDP; - -- when x"040" => RdDataxD <= NorthStatusRegPortxDP; - -- when x"044" => RdDataxD <= EastStatusRegPortxDP; - -- when x"048" => RdDataxD <= SouthStatusRegPortxDP; - -- when x"04c" => RdDataxD <= WestStatusRegPortxDP; - when others => RdDataxD <= x"aabbccdd"; - end case; - end if; - end if; - end process ReadRegPortxP; - - RegBankxP : process (PSSysClkxC, PSSysResetxR) is - begin -- process RegBankxP - if PSSysResetxR = '1' then - -- North - -- NorthStatusRegPortxDP <= (others => '0'); - NorthCtrlRegPortxDP <= (others => '0'); - -- NorthWrDataRegPortxDP <= (others => '0'); - -- East - -- EastStatusRegPortxDP <= (others => '0'); - -- EastCtrlRegPortxDP <= (others => '0'); - -- EastWrDataRegPortxDP <= (others => '0'); - -- -- South - -- SouthStatusRegPortxDP <= (others => '0'); - -- SouthCtrlRegPortxDP <= (others => '0'); - -- SouthWrDataRegPortxDP <= (others => '0'); - -- -- West - -- WestStatusRegPortxDP <= (others => '0'); - -- WestCtrlRegPortxDP <= (others => '0'); - -- WestWrDataRegPortxDP <= (others => '0'); - elsif rising_edge(PSSysClkxC) then - -- North - -- NorthStatusRegPortxDP <= NorthStatusRegPortxDN; - NorthCtrlRegPortxDP <= NorthCtrlRegPortxDN; - -- NorthWrDataRegPortxDP <= NorthWrDataRegPortxDN; - -- -- East - -- EastStatusRegPortxDP <= EastStatusRegPortxDN; - -- EastCtrlRegPortxDP <= EastCtrlRegPortxDN; - -- EastWrDataRegPortxDP <= EastWrDataRegPortxDN; - -- -- South - -- SouthStatusRegPortxDP <= SouthStatusRegPortxDN; - -- SouthCtrlRegPortxDP <= SouthCtrlRegPortxDN; - -- SouthWrDataRegPortxDP <= SouthWrDataRegPortxDN; - -- -- West - -- WestStatusRegPortxDP <= WestStatusRegPortxDN; - -- WestCtrlRegPortxDP <= WestCtrlRegPortxDN; - -- WestWrDataRegPortxDP <= WestWrDataRegPortxDN; - end if; - end process RegBankxP; - - end block RegBankxB; - - -- TxFifoxB : block is - -- begin -- block TxFifoxB - - -- NorthWrDataxAS : NorthNativeSlavexD.DataxD <= NorthWrDataRegPortxDP; - -- EastWrDataxAS : EastNativeSlavexD.DataxD <= EastWrDataRegPortxDP; - -- SouthWrDataxAS : SouthNativeSlavexD.DataxD <= SouthWrDataRegPortxDN; - -- WestWrDataRegxAS : WestNativeSlavexD.DataxD <= WestWrDataRegPortxDN; - -- NorthWrEnxAS : NorthNativeSlavexD.WrEnxS <= NorthCtrlRegPortxDP(0); - -- EastWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0); - -- SouthWrEnxAS : SouthNativeSlavexD.WrEnxS <= SouthCtrlRegPortxDP(0); - -- WestWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0); - -- NorthStatusRegPortxAS : NorthStatusRegPortxDN <= (0 => NorthNativeMasterxD.FullxS, - -- 1 => NorthNativeMasterxD.EmptyxS, - -- 2 => NorthNativeMasterxD.AlmostFullxS, - -- 3 => NorthNativeMasterxD.AlmostEmptyxS, - -- 4 => NorthNativeMasterxD.WrRstBusyxS, - -- 5 => NorthNativeMasterxD.RdRstBusyxS, - -- others => '0'); - -- EastStatusRegPortxAS : EastStatusRegPortxDN <= (0 => EastNativeMasterxD.FullxS, - -- 1 => EastNativeMasterxD.EmptyxS, - -- 2 => EastNativeMasterxD.AlmostFullxS, - -- 3 => EastNativeMasterxD.AlmostEmptyxS, - -- 4 => EastNativeMasterxD.WrRstBusyxS, - -- 5 => EastNativeMasterxD.RdRstBusyxS, - -- others => '0'); - -- SouthStatusRegPortxAS : SouthStatusRegPortxDN <= (0 => SouthNativeMasterxD.FullxS, - -- 1 => SouthNativeMasterxD.EmptyxS, - -- 2 => SouthNativeMasterxD.AlmostFullxS, - -- 3 => SouthNativeMasterxD.AlmostEmptyxS, - -- 4 => SouthNativeMasterxD.WrRstBusyxS, - -- 5 => SouthNativeMasterxD.RdRstBusyxS, - -- others => '0'); - -- WestStatusRegPortxAS : WestStatusRegPortxDN <= (0 => WestNativeMasterxD.FullxS, - -- 1 => WestNativeMasterxD.EmptyxS, - -- 2 => WestNativeMasterxD.AlmostFullxS, - -- 3 => WestNativeMasterxD.AlmostEmptyxS, - -- 4 => WestNativeMasterxD.WrRstBusyxS, - -- 5 => WestNativeMasterxD.RdRstBusyxS, - -- others => '0'); - - -- UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS, - -- AuroraClkMasterxC.UserClkxC) is - -- begin -- process UpdateRegxP - -- if not AuroraClkMasterxC.PllNotLockedxS then - -- NorthStatusSendWordxDP <= E_IDLE; - -- EastStatusSendWordxDP <= E_IDLE; - -- SouthStatusSendWordxDP <= E_IDLE; - -- WestStatusSendWordxDP <= E_IDLE; - -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then - -- NorthStatusSendWordxDP <= NorthStatusSendWordxDN; - -- EastStatusSendWordxDP <= EastStatusSendWordxDN; - -- SouthStatusSendWordxDP <= SouthStatusSendWordxDN; - -- WestStatusSendWordxDP <= WestStatusSendWordxDN; - -- end if; - -- end process UpdateRegxP; - - -- NorthSendWordxP : process (NorthNativeMasterxD.DataxD, - -- NorthNativeMasterxD.EmptyxS, - -- NorthStatusSendWordxDP, - -- NorthTXS2MxD.ReadyxS) is - -- begin -- process NorthSendWordxP - -- NorthTXM2SxD.DataxD <= (others => '0'); - -- NorthTXM2SxD.KeepxD <= (others => '1'); - -- NorthTXM2SxD.LastxS <= '0'; - -- NorthTXM2SxD.ValidxS <= '0'; - -- NorthNativeSlavexD.RdEnxS <= '0'; - -- NorthStatusSendWordxDN <= NorthStatusSendWordxDP; - - -- case NorthStatusSendWordxDP is - -- when E_IDLE => - - -- if (NorthNativeMasterxD.EmptyxS = '0') and - -- (NorthTXS2MxD.ReadyxS = '1') then - -- NorthTXM2SxD.DataxD <= NorthNativeMasterxD.DataxD; - -- NorthTXM2SxD.LastxS <= '1'; - -- NorthTXM2SxD.ValidxS <= '1'; - -- NorthNativeSlavexD.RdEnxS <= '1'; - -- NorthStatusSendWordxDN <= E_SEND; - -- end if; - - -- when E_SEND => - -- NorthStatusSendWordxDN <= E_IDLE; - - -- when others => null; - -- end case; - -- end process NorthSendWordxP; - - -- EastSendWordxP : process (EastNativeMasterxD.DataxD, - -- EastNativeMasterxD.EmptyxS, - -- EastStatusSendWordxDP, - -- EastTXS2MxD.ReadyxS) is - -- begin -- process EastSendWordxP - -- EastTXM2SxD.DataxD <= (others => '0'); - -- EastTXM2SxD.KeepxD <= (others => '1'); - -- EastTXM2SxD.LastxS <= '0'; - -- EastTXM2SxD.ValidxS <= '0'; - -- EastNativeSlavexD.RdEnxS <= '0'; - -- EastStatusSendWordxDN <= EastStatusSendWordxDP; - - -- case EastStatusSendWordxDP is - -- when E_IDLE => - - -- if (EastNativeMasterxD.EmptyxS = '0') and - -- (EastTXS2MxD.ReadyxS = '1') then - -- EastTXM2SxD.DataxD <= EastNativeMasterxD.DataxD; - -- EastTXM2SxD.LastxS <= '1'; - -- EastTXM2SxD.ValidxS <= '1'; - -- EastNativeSlavexD.RdEnxS <= '1'; - -- EastStatusSendWordxDN <= E_SEND; - -- end if; - - -- when E_SEND => - -- EastStatusSendWordxDN <= E_IDLE; - - -- when others => null; - -- end case; - -- end process EastSendWordxP; - - -- SouthSendWordxP : process (SouthNativeMasterxD.DataxD, - -- SouthNativeMasterxD.EmptyxS, - -- SouthStatusSendWordxDP, - -- SouthTXS2MxD.ReadyxS) is - -- begin -- process SouthSendWordxP - -- SouthTXM2SxD.DataxD <= (others => '0'); - -- SouthTXM2SxD.KeepxD <= (others => '1'); - -- SouthTXM2SxD.LastxS <= '0'; - -- SouthTXM2SxD.ValidxS <= '0'; - -- SouthNativeSlavexD.RdEnxS <= '0'; - -- SouthStatusSendWordxDN <= SouthStatusSendWordxDP; - - -- case SouthStatusSendWordxDP is - -- when E_IDLE => - - -- if (SouthNativeMasterxD.EmptyxS = '0') and - -- (SouthTXS2MxD.ReadyxS = '1') then - -- SouthTXM2SxD.DataxD <= SouthNativeMasterxD.DataxD; - -- SouthTXM2SxD.LastxS <= '1'; - -- SouthTXM2SxD.ValidxS <= '1'; - -- SouthNativeSlavexD.RdEnxS <= '1'; - -- SouthStatusSendWordxDN <= E_SEND; - -- end if; - - -- when E_SEND => - -- SouthStatusSendWordxDN <= E_IDLE; - - -- when others => null; - -- end case; - -- end process SouthSendWordxP; - - -- WestSendWordxP : process (WestNativeMasterxD.DataxD, - -- WestNativeMasterxD.EmptyxS, - -- WestStatusSendWordxDP, - -- WestTXS2MxD.ReadyxS) is - -- begin -- process WestSendWordxP - -- WestTXM2SxD.DataxD <= (others => '0'); - -- WestTXM2SxD.KeepxD <= (others => '1'); - -- WestTXM2SxD.LastxS <= '0'; - -- WestTXM2SxD.ValidxS <= '0'; - -- WestNativeSlavexD.RdEnxS <= '0'; - -- WestStatusSendWordxDN <= WestStatusSendWordxDP; - - -- case WestStatusSendWordxDP is - -- when E_IDLE => - - -- if (WestNativeMasterxD.EmptyxS = '0') and - -- (WestTXS2MxD.ReadyxS = '1') then - -- WestTXM2SxD.DataxD <= WestNativeMasterxD.DataxD; - -- WestTXM2SxD.LastxS <= '1'; - -- WestTXM2SxD.ValidxS <= '1'; - -- WestNativeSlavexD.RdEnxS <= '1'; - -- WestStatusSendWordxDN <= E_SEND; - -- end if; - - -- when E_SEND => - -- WestStatusSendWordxDN <= E_IDLE; - - -- when others => null; - -- end case; - -- end process WestSendWordxP; - - -- NorthFifoxI : entity work.scalp_packet_fifo_wrapper - -- port map ( - -- RdClkxCI => AuroraClkMasterxC.UserClkxC, - -- WrClkxCI => PSSysClkxC, - -- ResetxRI => PSSysResetxR, - -- NativeSlavexDI => NorthNativeSlavexD, - -- NativeMasterxDO => NorthNativeMasterxD); - - -- EastFifoxI : entity work.scalp_packet_fifo_wrapper - -- port map ( - -- RdClkxCI => AuroraClkMasterxC.UserClkxC, - -- WrClkxCI => PSSysClkxC, - -- ResetxRI => PSSysResetxR, - -- NativeSlavexDI => EastNativeSlavexD, - -- NativeMasterxDO => EastNativeMasterxD); - - -- SouthFifoxI : entity work.scalp_packet_fifo_wrapper - -- port map ( - -- RdClkxCI => AuroraClkMasterxC.UserClkxC, - -- WrClkxCI => PSSysClkxC, - -- ResetxRI => PSSysResetxR, - -- NativeSlavexDI => SouthNativeSlavexD, - -- NativeMasterxDO => SouthNativeMasterxD); - - -- WestFifoxI : entity work.scalp_packet_fifo_wrapper - -- port map ( - -- RdClkxCI => AuroraClkMasterxC.UserClkxC, - -- WrClkxCI => PSSysClkxC, - -- ResetxRI => PSSysResetxR, - -- NativeSlavexDI => WestNativeSlavexD, - -- NativeMasterxDO => WestNativeMasterxD); - - -- end block TxFifoxB; - - end block ZynqRegBankxB; - - -- DebugxB : block is - - -- -- RX Fifo reset 196 cycles - -- constant C_RX_FIFO_RST_DLY_TICKS : integer := 200; - - -- type t_read_phy_states is (E_READ_PHY_IDLE, E_READ_PHY_S0, E_READ_PHY_S1, E_READ_PHY_S2); - -- type t_write_phy_states is (E_WRITE_PHY_IDLE, E_WRITE_PHY_W0, E_WRITE_PHY_W1, - -- E_WRITE_PHY_W2, E_WRITE_PHY_W3, E_WRITE_PHY_W4, - -- E_WRITE_PHY_W5, E_WRITE_PHY_W6, E_WRITE_PHY_W7); - - -- -- North - -- signal NorthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE; - -- signal NorthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE; - -- signal NorthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE; - -- signal NorthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE; - -- -- East - -- signal EastReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE; - -- signal EastReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE; - -- signal EastWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE; - -- signal EastWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE; - -- -- South - -- signal SouthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE; - -- signal SouthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE; - -- signal SouthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE; - -- signal SouthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE; - -- -- West - -- signal WestReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE; - -- signal WestReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE; - -- signal WestWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE; - -- signal WestWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE; - - -- attribute mark_debug : string; - -- attribute keep : string; - -- -- - -- attribute mark_debug of NorthWritePhyStatexDP : signal is "true"; - -- attribute keep of NorthWritePhyStatexDP : signal is "true"; - -- -- attribute mark_debug of EastWritePhyStatexDP : signal is "true"; - -- -- attribute keep of EastWritePhyStatexDP : signal is "true"; - -- attribute mark_debug of SouthWritePhyStatexDP : signal is "true"; - -- attribute keep of SouthWritePhyStatexDP : signal is "true"; - -- -- attribute mark_debug of WestWritePhyStatexDP : signal is "true"; - -- -- attribute keep of WestWritePhyStatexDP : signal is "true"; - -- attribute mark_debug of NorthReadPhyStatexDP : signal is "true"; - -- attribute keep of NorthReadPhyStatexDP : signal is "true"; - -- -- attribute mark_debug of EastReadPhyStatexDP : signal is "true"; - -- -- attribute keep of EastReadPhyStatexDP : signal is "true"; - -- attribute mark_debug of SouthReadPhyStatexDP : signal is "true"; - -- attribute keep of SouthReadPhyStatexDP : signal is "true"; - -- -- attribute mark_debug of WestReadPhyStatexDP : signal is "true"; - -- -- attribute keep of WestReadPhyStatexDP : signal is "true"; - - -- begin -- block DebugxB - - -- -- RX Fifo reset 196 cycles - -- -- Clock and Resets - -- -- RX Fifo - -- NorthFifoResetxAS : RXResetxR.FifoResetxR.NorthxR <= - -- '1' when - -- (DebugRXFifoResetxR.NorthxR = '1') or - -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(0) = '0') else - -- '0'; - -- EastFifoResetxAS : RXResetxR.FifoResetxR.EastxR <= - -- '1' when - -- (DebugRXFifoResetxR.EastxR = '1') or - -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(1) = '0') else - -- '0'; - -- SouthFifoResetxAS : RXResetxR.FifoResetxR.SouthxR <= - -- '1' when - -- (DebugRXFifoResetxR.SouthxR = '1') or - -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(2) = '0') else - -- '0'; - -- WestFifoResetxAS : RXResetxR.FifoResetxR.WestxR <= - -- '1' when - -- (DebugRXFifoResetxR.WestxR = '1') or - -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(3) = '0') else - -- '0'; - -- -- Back pressure - -- NorthBackPressureResetxAS : RXResetxR.BackPressureResetxR.NorthxR <= - -- '1' when - -- (DebugBackPressureResetxR.NorthxR = '1') or - -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or - -- (RXFifoResetDonexD.NorthxS = '0') or - -- (RXFifoResetDoneDelayedxD.NorthxS = '0') or - -- (AuroraStatusxD.ChannelUpxD(0) = '0') else - -- '0'; - -- EastBackPressureResetxAS : RXResetxR.BackPressureResetxR.EastxR <= - -- '1' when - -- (DebugBackPressureResetxR.EastxR = '1') or - -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or - -- (RXFifoResetDonexD.EastxS = '0') or - -- (RXFifoResetDoneDelayedxD.EastxS = '0') or - -- (AuroraStatusxD.ChannelUpxD(1) = '0') else - -- '0'; - -- SouthBackPressureResetxAS : RXResetxR.BackPressureResetxR.SouthxR <= - -- '1' when - -- (DebugBackPressureResetxR.SouthxR = '1') or - -- (RXFifoResetDonexD.SouthxS = '0') or - -- (RXFifoResetDoneDelayedxD.SouthxS = '0') or - -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(2) = '0') else - -- '0'; - -- WestBackPressureResetxAS : RXResetxR.BackPressureResetxR.WestxR <= - -- '1' when - -- (DebugBackPressureResetxR.WestxR = '1') or - -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or - -- (RXFifoResetDonexD.WestxS = '0') or - -- (RXFifoResetDoneDelayedxD.WestxS = '0') or - -- (AuroraStatusxD.ChannelUpxD(3) = '0') else - -- '0'; - - -- NorthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC, - -- AuroraStatusxD.ChannelUpxD(0), - -- AuroraStatusxD.LaneUpxD(0)(0), - -- DebugCounterResetxR.NorthxR, - -- RXFifoResetDoneDelayedxD.NorthxS, - -- RXFifoResetDonexD.NorthxS) is - -- begin -- process NorthUpdateRegxP - -- if (DebugCounterResetxR.NorthxR = '1') or - -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(0) = '0') or - -- (RXFifoResetDonexD.NorthxS = '0') or - -- (RXFifoResetDoneDelayedxD.NorthxS = '0') then - -- NorthReadPhyStatexDP <= E_READ_PHY_IDLE; - -- NorthWritePhyStatexDP <= E_WRITE_PHY_IDLE; - -- NorthDataCounterxDP <= (others => '0'); - -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then - -- NorthReadPhyStatexDP <= NorthReadPhyStatexDN; - -- NorthWritePhyStatexDP <= NorthWritePhyStatexDN; - -- NorthDataCounterxDP <= NorthDataCounterxDN; - -- end if; - -- end process NorthUpdateRegxP; - - -- EastUpdateRegxP : process (AuroraClkMasterxC.UserClkxC, - -- AuroraStatusxD.ChannelUpxD(1), - -- AuroraStatusxD.LaneUpxD(1)(0), - -- DebugCounterResetxR.EastxR, - -- RXFifoResetDoneDelayedxD.EastxS, - -- RXFifoResetDonexD.EastxS) is - -- begin -- process EastUpdateRegxP - -- if (DebugCounterResetxR.EastxR = '1') or - -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(1) = '0') or - -- (RXFifoResetDonexD.EastxS = '0') or - -- (RXFifoResetDoneDelayedxD.EastxS = '0') then - -- EastReadPhyStatexDP <= E_READ_PHY_IDLE; - -- EastWritePhyStatexDP <= E_WRITE_PHY_IDLE; - -- EastDataCounterxDP <= (others => '0'); - -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then - -- EastReadPhyStatexDP <= EastReadPhyStatexDN; - -- EastWritePhyStatexDP <= EastWritePhyStatexDN; - -- EastDataCounterxDP <= EastDataCounterxDN; - -- end if; - -- end process EastUpdateRegxP; - - -- SouthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC, - -- AuroraStatusxD.ChannelUpxD(2), - -- AuroraStatusxD.LaneUpxD(2)(0), - -- DebugCounterResetxR.SouthxR, - -- RXFifoResetDoneDelayedxD.SouthxS, - -- RXFifoResetDonexD.SouthxS) is - -- begin -- process SouthUpdateRegxP - -- if (DebugCounterResetxR.SouthxR = '1') or - -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(2) = '0') or - -- (RXFifoResetDonexD.SouthxS = '0') or - -- (RXFifoResetDoneDelayedxD.SouthxS = '0') then - -- SouthReadPhyStatexDP <= E_READ_PHY_IDLE; - -- SouthWritePhyStatexDP <= E_WRITE_PHY_IDLE; - -- SouthDataCounterxDP <= (others => '0'); - -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then - -- SouthReadPhyStatexDP <= SouthReadPhyStatexDN; - -- SouthWritePhyStatexDP <= SouthWritePhyStatexDN; - -- SouthDataCounterxDP <= SouthDataCounterxDN; - -- end if; - -- end process SouthUpdateRegxP; - - -- WestUpdateRegxP : process (AuroraClkMasterxC.UserClkxC, - -- AuroraStatusxD.ChannelUpxD(3), - -- AuroraStatusxD.LaneUpxD(3)(0), - -- DebugCounterResetxR.WestxR, - -- RXFifoResetDoneDelayedxD.WestxS, - -- RXFifoResetDonexD.WestxS) is - -- begin -- process WestUpdateRegxP - -- if (DebugCounterResetxR.WestxR = '1') or - -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or - -- (AuroraStatusxD.ChannelUpxD(3) = '0') or - -- (RXFifoResetDonexD.WestxS = '0') or - -- (RXFifoResetDoneDelayedxD.WestxS = '0') then - -- WestReadPhyStatexDP <= E_READ_PHY_IDLE; - -- WestWritePhyStatexDP <= E_WRITE_PHY_IDLE; - -- WestDataCounterxDP <= (others => '0'); - -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then - -- WestReadPhyStatexDP <= WestReadPhyStatexDN; - -- WestWritePhyStatexDP <= WestWritePhyStatexDN; - -- WestDataCounterxDP <= WestDataCounterxDN; - -- end if; - -- end process WestUpdateRegxP; - - -- VioUserResetsxI : entity work.vio_user_resets - -- port map ( - -- clk => AuroraClkMasterxC.UserClkxC, - -- probe_out0(0) => DebugCounterResetxR.NorthxR, - -- probe_out1(0) => DebugCounterResetxR.EastxR, - -- probe_out2(0) => DebugCounterResetxR.SouthxR, - -- probe_out3(0) => DebugCounterResetxR.WestxR, - -- probe_out4(0) => DebugBackPressureResetxR.NorthxR, - -- probe_out5(0) => DebugBackPressureResetxR.EastxR, - -- probe_out6(0) => DebugBackPressureResetxR.SouthxR, - -- probe_out7(0) => DebugBackPressureResetxR.WestxR, - -- probe_out8(0) => DebugRXFifoResetxR.NorthxR, - -- probe_out9(0) => DebugRXFifoResetxR.EastxR, - -- probe_out10(0) => DebugRXFifoResetxR.SouthxR, - -- probe_out11(0) => DebugRXFifoResetxR.WestxR); - - -- VioStatusxI : entity work.vio_status - -- port map ( - -- clk => AuroraClkMasterxC.UserClkxC, - -- -- North - -- probe_in0(0) => AuroraStatusxD.HardErrxD(0), - -- probe_in1(0) => AuroraStatusxD.SoftErrxD(0), - -- probe_in2(0) => AuroraStatusxD.FrameErrxD(0), - -- probe_in3 => AuroraStatusxD.LaneUpxD(0), - -- probe_in4(0) => AuroraStatusxD.ChannelUpxD(0), - -- probe_in5(0) => AuroraStatusxD.RXResetDoneOutxD(0), - -- probe_in6(0) => AuroraStatusxD.TXResetDoneOutxD(0), - -- -- East - -- probe_in7(0) => AuroraStatusxD.HardErrxD(1), - -- probe_in8(0) => AuroraStatusxD.SoftErrxD(1), - -- probe_in9(0) => AuroraStatusxD.FrameErrxD(1), - -- probe_in10 => AuroraStatusxD.LaneUpxD(1), - -- probe_in11(0) => AuroraStatusxD.ChannelUpxD(1), - -- probe_in12(0) => AuroraStatusxD.RXResetDoneOutxD(1), - -- probe_in13(0) => AuroraStatusxD.TXResetDoneOutxD(1), - -- -- South - -- probe_in14(0) => AuroraStatusxD.HardErrxD(2), - -- probe_in15(0) => AuroraStatusxD.SoftErrxD(2), - -- probe_in16(0) => AuroraStatusxD.FrameErrxD(2), - -- probe_in17 => AuroraStatusxD.LaneUpxD(2), - -- probe_in18(0) => AuroraStatusxD.ChannelUpxD(2), - -- probe_in19(0) => AuroraStatusxD.RXResetDoneOutxD(2), - -- probe_in20(0) => AuroraStatusxD.TXResetDoneOutxD(2), - -- -- West - -- probe_in21(0) => AuroraStatusxD.HardErrxD(3), - -- probe_in22(0) => AuroraStatusxD.SoftErrxD(3), - -- probe_in23(0) => AuroraStatusxD.FrameErrxD(3), - -- probe_in24 => AuroraStatusxD.LaneUpxD(3), - -- probe_in25(0) => AuroraStatusxD.ChannelUpxD(3), - -- probe_in26(0) => AuroraStatusxD.RXResetDoneOutxD(3), - -- probe_in27(0) => AuroraStatusxD.TXResetDoneOutxD(3)); - - -- NorthWriteTXPhyxP : process (NorthDataCounterxDP, - -- NorthTXS2MxD.ReadyxS, - -- NorthWritePhyStatexDP) is - -- begin -- process NorthWriteTXPhyxP - -- -- Default values - -- NorthWritePhyStatexDN <= NorthWritePhyStatexDP; - -- NorthDataCounterxDN <= NorthDataCounterxDP; - -- NorthTXM2SxD.DataxD <= (others => '0'); - -- NorthTXM2SxD.KeepxD <= (others => '1'); - -- NorthTXM2SxD.ValidxS <= '0'; - -- NorthTXM2SxD.LastxS <= '0'; - - -- case NorthWritePhyStatexDP is - -- when E_WRITE_PHY_IDLE => - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W0; - - -- when E_WRITE_PHY_W0 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W1; - -- end if; - - -- when E_WRITE_PHY_W1 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W2; - -- end if; - - -- when E_WRITE_PHY_W2 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W3; - -- end if; - - -- when E_WRITE_PHY_W3 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W4; - -- end if; - - -- when E_WRITE_PHY_W4 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W5; - -- end if; - - -- when E_WRITE_PHY_W5 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W6; - -- end if; - -- when E_WRITE_PHY_W6 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W7; - -- end if; - - -- when E_WRITE_PHY_W7 => - -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP); - -- NorthTXM2SxD.ValidxS <= '1'; - -- NorthTXM2SxD.LastxS <= '1'; - - -- if NorthTXS2MxD.ReadyxS = '1' then - -- NorthWritePhyStatexDN <= E_WRITE_PHY_W0; - -- NorthDataCounterxDN <= NorthDataCounterxDP + 1; - -- end if; - - -- when others => null; - -- end case; - - -- end process NorthWriteTXPhyxP; - - -- EastWriteTXPhyxP : process (EastDataCounterxDP, - -- EastTXS2MxD.ReadyxS, - -- EastWritePhyStatexDP) is - -- begin -- process EastWriteTXPhyxP - -- -- Default values - -- EastWritePhyStatexDN <= EastWritePhyStatexDP; - -- EastDataCounterxDN <= EastDataCounterxDP; - -- EastTXM2SxD.DataxD <= (others => '0'); - -- EastTXM2SxD.KeepxD <= (others => '1'); - -- EastTXM2SxD.ValidxS <= '0'; - -- EastTXM2SxD.LastxS <= '0'; - - -- case EastWritePhyStatexDP is - -- when E_WRITE_PHY_IDLE => - -- EastWritePhyStatexDN <= E_WRITE_PHY_W0; - - -- when E_WRITE_PHY_W0 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W1; - -- end if; - - -- when E_WRITE_PHY_W1 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W2; - -- end if; - - -- when E_WRITE_PHY_W2 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W3; - -- end if; - - -- when E_WRITE_PHY_W3 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W4; - -- end if; - - -- when E_WRITE_PHY_W4 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W5; - -- end if; - - -- when E_WRITE_PHY_W5 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W6; - -- end if; - - -- when E_WRITE_PHY_W6 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W7; - -- end if; - - -- when E_WRITE_PHY_W7 => - -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP); - -- EastTXM2SxD.ValidxS <= '1'; - -- EastTXM2SxD.LastxS <= '1'; - - -- if EastTXS2MxD.ReadyxS = '1' then - -- EastWritePhyStatexDN <= E_WRITE_PHY_W0; - -- EastDataCounterxDN <= EastDataCounterxDP + 1; - -- end if; - - -- when others => null; - -- end case; - - -- end process EastWriteTXPhyxP; - - -- SouthWriteTXPhyxP : process (SouthDataCounterxDP, - -- SouthTXS2MxD.ReadyxS, - -- SouthWritePhyStatexDP) is - -- begin -- process SouthWriteTXPhyxP - -- -- Default values - -- SouthWritePhyStatexDN <= SouthWritePhyStatexDP; - -- SouthDataCounterxDN <= SouthDataCounterxDP; - -- SouthTXM2SxD.DataxD <= (others => '0'); - -- SouthTXM2SxD.KeepxD <= (others => '1'); - -- SouthTXM2SxD.ValidxS <= '0'; - -- SouthTXM2SxD.LastxS <= '0'; - - -- case SouthWritePhyStatexDP is - -- when E_WRITE_PHY_IDLE => - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W0; - - -- when E_WRITE_PHY_W0 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W1; - -- end if; - - -- when E_WRITE_PHY_W1 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W2; - -- end if; - - -- when E_WRITE_PHY_W2 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W3; - -- end if; - - -- when E_WRITE_PHY_W3 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W4; - -- end if; - - -- when E_WRITE_PHY_W4 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W5; - -- end if; - - -- when E_WRITE_PHY_W5 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W6; - -- end if; - - -- when E_WRITE_PHY_W6 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W7; - -- end if; - - -- when E_WRITE_PHY_W7 => - -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP); - -- SouthTXM2SxD.ValidxS <= '1'; - -- SouthTXM2SxD.LastxS <= '1'; - - -- if SouthTXS2MxD.ReadyxS = '1' then - -- SouthWritePhyStatexDN <= E_WRITE_PHY_W0; - -- SouthDataCounterxDN <= SouthDataCounterxDP + 1; - -- end if; - - -- when others => null; - -- end case; - - -- end process SouthWriteTXPhyxP; - - -- WestWriteTXPhyxP : process (WestDataCounterxDP, - -- WestTXS2MxD.ReadyxS, - -- WestWritePhyStatexDP) is - -- begin -- process WestWriteTXPhyxP - -- -- Default values - -- WestWritePhyStatexDN <= WestWritePhyStatexDP; - -- WestDataCounterxDN <= WestDataCounterxDP; - -- WestTXM2SxD.DataxD <= (others => '0'); - -- WestTXM2SxD.KeepxD <= (others => '1'); - -- WestTXM2SxD.ValidxS <= '0'; - -- WestTXM2SxD.LastxS <= '0'; - - -- case WestWritePhyStatexDP is - -- when E_WRITE_PHY_IDLE => - -- WestWritePhyStatexDN <= E_WRITE_PHY_W0; - - -- when E_WRITE_PHY_W0 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W1; - -- end if; - - -- when E_WRITE_PHY_W1 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W2; - -- end if; - - -- when E_WRITE_PHY_W2 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W3; - -- end if; - - -- when E_WRITE_PHY_W3 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W4; - -- end if; - - -- when E_WRITE_PHY_W4 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W5; - -- end if; - - -- when E_WRITE_PHY_W5 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W6; - -- end if; - - -- when E_WRITE_PHY_W6 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W7; - -- end if; - - -- when E_WRITE_PHY_W7 => - -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP); - -- WestTXM2SxD.ValidxS <= '1'; - -- WestTXM2SxD.LastxS <= '1'; - - -- if WestTXS2MxD.ReadyxS = '1' then - -- WestWritePhyStatexDN <= E_WRITE_PHY_W0; - -- WestDataCounterxDN <= WestDataCounterxDP + 1; - -- end if; - - -- when others => null; - -- end case; - - -- end process WestWriteTXPhyxP; - - -- NorthReadRXPhyxP : process (NorthRXFifoStatusxD.ProgEmptyxS, - -- NorthRXFifoStatusxD.ProgFullxS, - -- NorthRXM2SxD.ValidxS, - -- NorthReadPhyStatexDP) is - -- begin -- process NorthReadRXPhyxP - -- -- Default value - -- NorthReadPhyStatexDN <= NorthReadPhyStatexDP; - -- NorthRXS2MxD.ReadyxS <= '0'; - - -- case NorthReadPhyStatexDP is - -- when E_READ_PHY_IDLE => - -- if (NorthRXFifoStatusxD.ProgFullxS = '1') and - -- (NorthRXFifoStatusxD.ProgEmptyxS = '0') then - -- NorthReadPhyStatexDN <= E_READ_PHY_S0; - -- end if; - - -- when E_READ_PHY_S0 => - -- if NorthRXM2SxD.ValidxS = '1' then - -- NorthRXS2MxD.ReadyxS <= '1'; - -- end if; - - -- if (NorthRXFifoStatusxD.ProgFullxS = '0') and - -- (NorthRXFifoStatusxD.ProgEmptyxS = '1') then - -- NorthReadPhyStatexDN <= E_READ_PHY_IDLE; - -- end if; - - -- when others => null; - -- end case; - -- end process NorthReadRXPhyxP; - - -- EastReadRXPhyxP : process (EastRXFifoStatusxD.ProgEmptyxS, - -- EastRXFifoStatusxD.ProgFullxS, - -- EastRXM2SxD.ValidxS, - -- EastReadPhyStatexDP) is - -- begin -- process EastReadRXPhyxP - -- -- Default value - -- EastReadPhyStatexDN <= EastReadPhyStatexDP; - -- EastRXS2MxD.ReadyxS <= '0'; - - -- case EastReadPhyStatexDP is - -- when E_READ_PHY_IDLE => - -- if (EastRXFifoStatusxD.ProgFullxS = '1') and - -- (EastRXFifoStatusxD.ProgEmptyxS = '0') then - -- EastReadPhyStatexDN <= E_READ_PHY_S0; - -- end if; - - -- when E_READ_PHY_S0 => - -- if EastRXM2SxD.ValidxS = '1' then - -- EastRXS2MxD.ReadyxS <= '1'; - -- end if; - - -- if (EastRXFifoStatusxD.ProgFullxS = '0') and - -- (EastRXFifoStatusxD.ProgEmptyxS = '1') then - -- EastReadPhyStatexDN <= E_READ_PHY_IDLE; - -- end if; - - -- when others => null; - -- end case; - -- end process EastReadRXPhyxP; - - -- SouthReadRXPhyxP : process (SouthRXFifoStatusxD.ProgEmptyxS, - -- SouthRXFifoStatusxD.ProgFullxS, - -- SouthRXM2SxD.ValidxS, - -- SouthReadPhyStatexDP) is - -- begin -- process SouthReadRXPhyxP - -- -- Default value - -- SouthReadPhyStatexDN <= SouthReadPhyStatexDP; - -- SouthRXS2MxD.ReadyxS <= '0'; - - -- case SouthReadPhyStatexDP is - -- when E_READ_PHY_IDLE => - -- if (SouthRXFifoStatusxD.ProgFullxS = '1') and - -- (SouthRXFifoStatusxD.ProgEmptyxS = '0') then - -- SouthReadPhyStatexDN <= E_READ_PHY_S0; - -- end if; - - -- when E_READ_PHY_S0 => - -- if SouthRXM2SxD.ValidxS = '1' then - -- SouthRXS2MxD.ReadyxS <= '1'; - -- end if; - - -- if (SouthRXFifoStatusxD.ProgFullxS = '0') and - -- (SouthRXFifoStatusxD.ProgEmptyxS = '1') then - -- SouthReadPhyStatexDN <= E_READ_PHY_IDLE; - -- end if; - - -- when others => null; - -- end case; - -- end process SouthReadRXPhyxP; - - -- WestReadRXPhyxP : process (WestRXFifoStatusxD.ProgEmptyxS, - -- WestRXFifoStatusxD.ProgFullxS, - -- WestRXM2SxD.ValidxS, - -- WestReadPhyStatexDP) is - -- begin -- process WestReadRXPhyxP - -- -- Default value - -- WestReadPhyStatexDN <= WestReadPhyStatexDP; - -- WestRXS2MxD.ReadyxS <= '0'; - - -- case WestReadPhyStatexDP is - -- when E_READ_PHY_IDLE => - -- if (WestRXFifoStatusxD.ProgFullxS = '1') and - -- (WestRXFifoStatusxD.ProgEmptyxS = '0') then - -- WestReadPhyStatexDN <= E_READ_PHY_S0; - -- end if; - - -- when E_READ_PHY_S0 => - -- if WestRXM2SxD.ValidxS = '1' then - -- WestRXS2MxD.ReadyxS <= '1'; - -- end if; - - -- if (WestRXFifoStatusxD.ProgFullxS = '0') and - -- (WestRXFifoStatusxD.ProgEmptyxS = '1') then - -- WestReadPhyStatexDN <= E_READ_PHY_IDLE; - -- end if; - - -- when others => null; - -- end case; - -- end process WestReadRXPhyxP; - - -- end block DebugxB; - end block ProgrammableLogicxB; end arch; diff --git a/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd index b8e8839012988c187611c16d73ed57c569627d39..f565812f2fadf10d343ab2ab2563dd14294873f9 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd +++ b/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd @@ -15,7 +15,7 @@ -- Tool version: 2020.2 -- Description: Testbench for scalp_firmware -- --- Last update: 2021-05-17 08:38:48 +-- Last update: 2021-05-21 08:30:39 -- --------------------------------------------------------------------------------- diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl index 26bb4764bae5b76cc8393eb8c07b8bec48126e44..4735044228e0651b82ad6c157ffcd2b76dff554f 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: Console color print utility # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh index 80a7112e612d432917cc5038b6bf8c0fd2a279b9..4c35813c49e33fb85b7b4f9896530872b3eb7dcb 100755 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Cleanup Vitis SDK workspace directory # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh index eb65f07793663a1dc8abfb05000000ad248d8f79..300b20ad705770890950e266e8985909c1a69c2d 100755 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Generate Vitis workspace for software applications # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl index 92af1fabc467ad2210622163333a57f69ba7764e..3ace7bf8fd3351b71e00c385ae04c576e975ad33 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: TCL script for re-creating Vitis workspace # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh index d4f866600ed06c906db83607de6310b536f05b00..1bf85891fd9cd298c6170fc046f9d6c88279acf1 100755 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh @@ -17,7 +17,7 @@ # Tool version: 2020.2 # Description: Open the Vitis workspace # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh index 26924a8ed8aec9d4c29f5e1428850a5db70fd23f..cb687ac7d6488c6f4a0fc95463328f0b3d82a7a0 100755 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh @@ -15,7 +15,7 @@ # Tool version: 2020.2 # Description: TCL script creating aliases for Vitis workspace management scripts # -# Last update: 2021-05-17 08:38:48 +# Last update: 2021-05-21 08:30:39 # ################################################################################## diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h index d67970155c711b2e8739b8950b1999eda5700f83..e8c7f07c515002fa3b10d3c2b631f0a070ff2e96 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h @@ -15,7 +15,7 @@ -- Tool version: 2020.2 -- Description: Software application -- --- Last update: 2021-05-17 08:38:48 +-- Last update: 2021-05-21 08:30:39 -- -----------------------------------------------------------------------------*/ diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c index f582ef2e3f4b700abc2e54ab4e0371d9401d63b4..ac649f73cdac4bffd7a054db4fe7250e11a9b1b9 100644 --- a/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c +++ b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c @@ -15,7 +15,7 @@ -- Tool version: 2020.2 -- Description: Software application -- --- Last update: 2021-05-17 08:38:48 +-- Last update: 2021-05-21 08:30:39 -- -----------------------------------------------------------------------------*/ diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci b/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci index b74e7eae073e4386d12d986e064e676d8671211a..40da822d982c450fec41cba7ad9234c3fc068443 100644 --- a/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci +++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci @@ -108,7 +108,7 @@ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> - <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.gen/sources_1/ip/axis_data_fifo</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue> diff --git a/ips/hw/scalp_axis_fifo_wrapper/src/hdl/scalp_axis_fifo_wrapper.vhd b/ips/hw/scalp_axis_fifo_wrapper/src/hdl/scalp_axis_fifo_wrapper.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7aa080aa567110ab1c2ee750d815e81d844d56fd --- /dev/null +++ b/ips/hw/scalp_axis_fifo_wrapper/src/hdl/scalp_axis_fifo_wrapper.vhd @@ -0,0 +1,103 @@ +---------------------------------------------------------------------------------- +-- _ _ +-- | |_ ___ _ __(_)__ _ +-- | ' \/ -_) '_ \ / _` | +-- |_||_\___| .__/_\__,_| +-- |_| +-- +---------------------------------------------------------------------------------- +-- +-- Company: hepia +-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch +-- +-- Module Name: scalp_axis_fifo_wrapper - arch +-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +-- Tool version: 2020.2 +-- Description: scalp_axis_fifo_wrapper +-- +-- Last update: 2021-05-31 +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.axi4_pkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity scalp_axis_fifo_wrapper is + + port ( + ClkxCI : in t_axi4_dual_clk; + ResetxRI : in t_axi4_rst; + RXM2SxDI : in t_axi4m2s; + RXS2MxSO : out t_axi4s2m; + TXM2SxDO : out t_axi4m2s; + TXS2MxSI : in t_axi4s2m; + FifoStatusxDO : out t_axi4fifo_status); + +end scalp_axis_fifo_wrapper; + +architecture arch of scalp_axis_fifo_wrapper is + + component scalp_axis_fifo + port ( + s_axis_aresetn : in std_logic; + s_axis_aclk : in std_logic; + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + s_axis_tstrb : in std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0); + s_axis_tkeep : in std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0); + s_axis_tlast : in std_logic; + s_axis_tid : in std_logic_vector(0 downto 0); + s_axis_tdest : in std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0); + s_axis_tuser : in std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0); + m_axis_aclk : in std_logic; + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic; + m_axis_tdata : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + m_axis_tstrb : out std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0); + m_axis_tkeep : out std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0); + m_axis_tlast : out std_logic; + m_axis_tid : out std_logic_vector(0 downto 0); + m_axis_tdest : out std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0); + m_axis_tuser : out std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0); + axis_wr_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + axis_rd_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + prog_full : out std_logic); + end component; + +begin -- architecture arch + + ScalpAxisFifoCorexI : entity work.scalp_axis_fifo + port map ( + s_axis_aresetn => ResetxRI.RstxRAN, + s_axis_aclk => ClkxCI.RXClkxC, + s_axis_tvalid => RXM2SxDI.ValidxS, + s_axis_tready => RXS2MxSO.ReadyxS, + s_axis_tdata => RXM2SxDI.DataxD, + s_axis_tstrb => RXM2SxDI.StrbxD, + s_axis_tkeep => RXM2SxDI.KeepxD, + s_axis_tlast => RXM2SxDI.LastxS, + s_axis_tid(0) => RXM2SxDI.IdxS, + s_axis_tdest => RXM2SxDI.DestxD, + s_axis_tuser => RXM2SxDI.UserxD, + m_axis_aclk => ClkxCI.TXClkxC, + m_axis_tvalid => TXM2SxDO.ValidxS, + m_axis_tready => TXS2MxSI.ReadyxS, + m_axis_tdata => TXM2SxDO.DataxD, + m_axis_tstrb => TXM2SxDO.StrbxD, + m_axis_tkeep => TXM2SxDO.KeepxD, + m_axis_tlast => TXM2SxDO.LastxS, + m_axis_tid(0) => TXM2SxDO.IdxS, + m_axis_tdest => TXM2SxDO.DestxD, + m_axis_tuser => TXM2SxDO.UserxD, + axis_wr_data_count => FifoStatusxDO.WrDataCntxD, + axis_rd_data_count => FifoStatusxDO.RdDataCntxD, + prog_full => FifoStatusxDO.ProgFullxS); + +end architecture arch; diff --git a/ips/hw/scalp_axis_fifo_wrapper/src/ip_core/scalp_axis_fifo/scalp_axis_fifo.xci b/ips/hw/scalp_axis_fifo_wrapper/src/ip_core/scalp_axis_fifo/scalp_axis_fifo.xci new file mode 100644 index 0000000000000000000000000000000000000000..7d4b7a8c8bfe7f56b00b662c645a7e25416bbce1 --- /dev/null +++ b/ips/hw/scalp_axis_fifo_wrapper/src/ip_core/scalp_axis_fifo/scalp_axis_fifo.xci @@ -0,0 +1,163 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>scalp_axis_fifo</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_data_fifo" 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+":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}}}}}"/> + </xilinx:boundaryDescriptionInfo> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/ips/hw/scalp_axis_fifo_wrapper/src/sim/tb_scalp_axis_fifo_wrapper.vhd b/ips/hw/scalp_axis_fifo_wrapper/src/sim/tb_scalp_axis_fifo_wrapper.vhd new file mode 100644 index 0000000000000000000000000000000000000000..25b65a07d47f0ac319f5bdf746a834ee84df2eeb --- /dev/null +++ b/ips/hw/scalp_axis_fifo_wrapper/src/sim/tb_scalp_axis_fifo_wrapper.vhd @@ -0,0 +1,34 @@ +---------------------------------------------------------------------------------- +-- _ _ +-- | |_ ___ _ __(_)__ _ +-- | ' \/ -_) '_ \ / _` | +-- |_||_\___| .__/_\__,_| +-- |_| +-- +---------------------------------------------------------------------------------- +-- +-- Company: hepia +-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch +-- +-- Module Name: tb_scalp_axis_fifo_wrapper - arch +-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +-- Tool version: 2020.2 +-- Description: Testbench for scalp_axis_fifo_wrapper +-- +-- Last update: 2021-05-21 08:14:52 +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_scalp_axis_fifo_wrapper is +end tb_scalp_axis_fifo_wrapper; + + +architecture behavioral of tb_scalp_axis_fifo_wrapper is + +begin + +end behavioral; diff --git a/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd b/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd index 3a96d0e2433f5a01bb34ecc71c281c393df19cbe..e8f114aab1ce9c96489a2f77bf818c09040c44d2 100644 --- a/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd +++ b/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd @@ -15,7 +15,7 @@ -- Tool version: 2020.2 -- Description: scalp_packet_fifo_wrapper -- --- Last update: 2020-11-08 +-- Last update: 2021-05-21 -- --------------------------------------------------------------------------------- @@ -25,6 +25,9 @@ use ieee.numeric_std.all; use work.axi4_pkg.all; +library unisim; +use unisim.vcomponents.all; + entity scalp_packet_fifo_wrapper is port ( diff --git a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd index 1010ea98cd14edf89c444d2af8b7c72508973a0a..5c7904bf7f2bfc9a08c6b8f9d55317fd43aea13e 100644 --- a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd +++ b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd @@ -15,7 +15,7 @@ -- Tool version: 2018.2 -- Description: Scalp Miscellanous -- --- Last update: 2021-05-18 +-- Last update: 2021-06-07 -- --------------------------------------------------------------------------------- library ieee; @@ -297,6 +297,60 @@ package scalp_misc is DataxD : std_logic_vector) return integer; + --------------------------------------------------------------------------- + + -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian). + function scalp_sp_h0_to_axis_ul ( + SpDstAddrXxD : std_ulogic_vector; + SpDstAddrYxD : std_ulogic_vector; + SpDstAddrZxD : std_ulogic_vector; + SpTypexD : std_ulogic_vector) + return std_ulogic_vector; + + -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian). + function scalp_sp_h0_to_axis ( + SpDstAddrXxD : std_ulogic_vector; + SpDstAddrYxD : std_ulogic_vector; + SpDstAddrZxD : std_ulogic_vector; + SpTypexD : std_ulogic_vector) + return std_logic_vector; + + -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian). + function scalp_sp_h1_to_axis_ul ( + SpSrcAddrXxD : std_ulogic_vector; + SpSrcAddrYxD : std_ulogic_vector; + SpSrcAddrZxD : std_ulogic_vector) + return std_ulogic_vector; + + -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian). + function scalp_sp_h1_to_axis ( + SpSrcAddrXxD : std_ulogic_vector; + SpSrcAddrYxD : std_ulogic_vector; + SpSrcAddrZxD : std_ulogic_vector) + return std_logic_vector; + + -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian). + function scalp_sp_h2_to_axis_ul ( + SpPldSizexD : std_ulogic_vector) + return std_ulogic_vector; + + -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian). + function scalp_sp_h2_to_axis ( + SpPldSizexD : std_ulogic_vector) + return std_logic_vector; + + -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian). + function scalp_sp_p_to_axis_ul ( + SpPayloadxD : std_ulogic_vector) + return std_ulogic_vector; + + -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian). + function scalp_sp_p_to_axis ( + SpPayloadxD : std_ulogic_vector) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian). function scalp_sp_header_h0_to_axis_ul ( SpHeaderxD : t_scalp_packet_header) @@ -567,6 +621,124 @@ package body scalp_misc is return std_logic_vector(scalp_peek_pld_ul(std_ulogic_vector(DataxD))); end function scalp_peek_pld; + --------------------------------------------------------------------------- + + -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian). + function scalp_sp_h0_to_axis_ul ( + SpDstAddrXxD : std_ulogic_vector; + SpDstAddrYxD : std_ulogic_vector; + SpDstAddrZxD : std_ulogic_vector; + SpTypexD : std_ulogic_vector) + return std_ulogic_vector is + variable H0xD : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1)) := (others => '0'); + variable H0LittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0'); + variable DstAddrXxD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + variable DstAddrYxD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + variable DstAddrZxD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + variable TypexD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + begin + DstAddrXxD := std_ulogic_vector(SpDstAddrXxD(SpDstAddrXxD'left to SpDstAddrXxD'right)); + DstAddrYxD := std_ulogic_vector(SpDstAddrYxD(SpDstAddrYxD'left to SpDstAddrYxD'right)); + DstAddrZxD := std_ulogic_vector(SpDstAddrZxD(SpDstAddrZxD'left to SpDstAddrZxD'right)); + TypexD := std_ulogic_vector(SpTypexD(SpTypexD'left to SpTypexD'right)); + H0LittleEndianxD := DstAddrXxD & DstAddrYxD & DstAddrZxD & TypexD; + H0xD := change_endian_ul(H0LittleEndianxD); + return H0xD; + end function scalp_sp_h0_to_axis_ul; + + -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian). + function scalp_sp_h0_to_axis ( + SpDstAddrXxD : std_ulogic_vector; + SpDstAddrYxD : std_ulogic_vector; + SpDstAddrZxD : std_ulogic_vector; + SpTypexD : std_ulogic_vector) + return std_logic_vector is + begin + return std_logic_vector(scalp_sp_h0_to_axis_ul(SpDstAddrXxD(SpDstAddrXxD'left to SpDstAddrXxD'right), + SpDstAddrYxD(SpDstAddrYxD'left to SpDstAddrYxD'right), + SpDstAddrZxD(SpDstAddrZxD'left to SpDstAddrZxD'right), + SpTypexD(SpTypexD'left to SpTypexD'right))); + end function scalp_sp_h0_to_axis; + + -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian). + function scalp_sp_h1_to_axis_ul ( + SpSrcAddrXxD : std_ulogic_vector; + SpSrcAddrYxD : std_ulogic_vector; + SpSrcAddrZxD : std_ulogic_vector) + return std_ulogic_vector is + variable H1xD : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1)) := (others => '0'); + variable H1LittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0'); + variable SrcAddrXxD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + variable SrcAddrYxD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + variable SrcAddrZxD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + variable PadxD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0'); + begin + SrcAddrXxD := std_ulogic_vector(SpSrcAddrXxD(SpSrcAddrXxD'left to SpSrcAddrXxD'right)); + SrcAddrYxD := std_ulogic_vector(SpSrcAddrYxD(SpSrcAddrYxD'left to SpSrcAddrYxD'right)); + SrcAddrZxD := std_ulogic_vector(SpSrcAddrZxD(SpSrcAddrZxD'left to SpSrcAddrZxD'right)); + -- 31 downto 0 + H1LittleEndianxD := SrcAddrXxD & SrcAddrYxD & SrcAddrZxD & PadxD; + H1xD := change_endian_ul(H1LittleEndianxD); + return H1xD; + end function scalp_sp_h1_to_axis_ul; + + -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian). + function scalp_sp_h1_to_axis ( + SpSrcAddrXxD : std_ulogic_vector; + SpSrcAddrYxD : std_ulogic_vector; + SpSrcAddrZxD : std_ulogic_vector) + return std_logic_vector is + begin + return std_logic_vector(scalp_sp_h1_to_axis_ul(SpSrcAddrXxD(SpSrcAddrXxD'left to SpSrcAddrXxD'right), + SpSrcAddrYxD(SpSrcAddrYxD'left to SpSrcAddrYxD'right), + SpSrcAddrZxD(SpSrcAddrZxD'left to SpSrcAddrZxD'right))); + end function scalp_sp_h1_to_axis; + + -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian). + function scalp_sp_h2_to_axis_ul ( + SpPldSizexD : std_ulogic_vector) + return std_ulogic_vector is + variable H2xD : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1)) := (others => '0'); + variable H2LittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0'); + variable PldSizexD : std_ulogic_vector(((C_BYTE_SIZE * 2) - 1) downto 0) := (others => '0'); + variable PadxD : std_ulogic_vector(((C_BYTE_SIZE * 2) - 1) downto 0) := (others => '0'); + begin + PldSizexD := std_ulogic_vector(SpPldSizexD(SpPldSizexD'left to SpPldSizexD'right)); + H2LittleEndianxD := PldSizexD & PadxD; + H2xD := change_endian_ul(H2LittleEndianxD); + return H2xD; + end function scalp_sp_h2_to_axis_ul; + + -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian). + function scalp_sp_h2_to_axis ( + SpPldSizexD : std_ulogic_vector) + return std_logic_vector is + begin + return std_logic_vector(scalp_sp_h2_to_axis_ul(SpPldSizexD(SpPldSizexD'left to SpPldSizexD'right))); + end function scalp_sp_h2_to_axis; + + -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian). + function scalp_sp_p_to_axis_ul ( + SpPayloadxD : std_ulogic_vector) + return std_ulogic_vector is + variable PxD : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1)) := (others => '0'); + variable PLittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0'); + begin + PLittleEndianxD := SpPayloadxD(SpPayloadxD'left to SpPayloadxD'right); + PxD := change_endian_ul(PLittleEndianxD); + return PxD; + end function scalp_sp_p_to_axis_ul; + + -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian). + function scalp_sp_p_to_axis ( + SpPayloadxD : std_ulogic_vector) + return std_logic_vector is + begin + return std_logic_vector(scalp_sp_p_to_axis_ul(SpPayloadxD(SpPayloadxD'left to SpPayloadxD'right))); + end function scalp_sp_p_to_axis; + + --------------------------------------------------------------------------- + -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian). function scalp_sp_header_h0_to_axis_ul ( SpHeaderxD : t_scalp_packet_header) diff --git a/ips/hw/scalp_router_regbank/component.xml b/ips/hw/scalp_router_regbank/component.xml new file mode 100644 index 0000000000000000000000000000000000000000..d61eaf01d7fb7196a3f1484e715a0b7bbb91d1b8 --- /dev/null +++ b/ips/hw/scalp_router_regbank/component.xml @@ -0,0 +1,1190 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>hepia.hesge.ch</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>scalp_router_regbank</spirit:name> + <spirit:version>0.3</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>SAxiClkxCI</spirit:name> + <spirit:displayName>SAxiClkxCI</spirit:displayName> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>SAxiClkxCI</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_RESET">SAxiRstxRANI:ScalpPacketStatusxDI:ScalpPacketCtrlxDO:ScalpPacketReadDataxDI:ScalpPacketWriteDataxDO:TXWrDataCntxDI:TXRdDataCntxDI:RXWrDataCntxDI:RXRdDataCntxDI</spirit:value> + </spirit:parameter> + <spirit:parameter> + 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DO NOT EDIT THIS FILE DIRECTLY. +-- scalp_regedit v0.1 - 05.2021 +-- Author : Joachim Schmidt <joachim.schmidt@hesge.ch> + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_misc.all; + +library unisim; +use unisim.vcomponents.all; + +entity scalp_router_regbank is + + generic ( + C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32; + C_AXI4_RDATA_SIZE : integer range 0 to 32 := 32; + C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2; + C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32; + C_AXI4_WDATA_SIZE : integer range 0 to 32 := 32; + C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4; + C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2; + C_AXI4_ADDR_SIZE : integer range 0 to 32 := 12; + C_AXI4_DATA_SIZE : integer range 0 to 32 := 32); + + port ( + -- Clock and reset + SAxiClkxCI : in std_ulogic; + SAxiRstxRANI : in std_ulogic; + -- AXI4 Lite + -- Read Channel + -- Read Address Channel + SAxiARAddrxDI : in std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0); + SAxiARValidxSI : in std_ulogic; + SAxiARReadyxSO : out std_ulogic; + -- Read Data Channel + SAxiRDataxDO : out std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0); + SAxiRRespxDO : out std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0); + SAxiRValidxSO : out std_ulogic; + SAxiRReadyxSI : in std_ulogic; + -- Write Channel + -- Write Address Channel + SAxiAWAddrxDI : in std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0); + SAxiAWValidxSI : in std_ulogic; + SAxiAWReadyxSO : out std_ulogic; + -- Write Data Channel + SAxiWDataxDI : in std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0); + SAxiWStrbxDI : in std_ulogic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0); + SAxiWValidxSI : in std_ulogic; + SAxiWReadyxSO : out std_ulogic; + -- Write Response Channel + SAxiBRespxDO : out std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0); + SAxiBValidxSO : out std_ulogic; + SAxiBReadyxSI : in std_ulogic; + -- Registers list IO + ScalpPacketWriteDataxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + ScalpPacketReadDataxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + ScalpPacketCtrlxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + ScalpPacketStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + TXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + TXRdDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + RXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + RXRdDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0); + LocNetAddrxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0)); + +end scalp_router_regbank; + +architecture behavioral of scalp_router_regbank is + + -- Constants + constant C_AXI4_RRESP_OKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00"; + constant C_AXI4_RRESP_EXOKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01"; + constant C_AXI4_RRESP_SLVERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10"; + constant C_AXI4_RRESP_DECERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11"; + constant C_AXI4_BRESP_OKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00"; + constant C_AXI4_BRESP_EXOKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01"; + constant C_AXI4_BRESP_SLVERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10"; + constant C_AXI4_BRESP_DECERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11"; + + -- Signals + -- Clock and reset + signal SAxiClkxC : std_ulogic := '0'; + signal SAxiRstxRAN : std_ulogic := '0'; + -- AXI4 Lite + signal SAxiARReadyxS : std_ulogic := '0'; + signal SAxiRValidxS : std_ulogic := '0'; + signal SAxiBValidxS : std_ulogic := '0'; + signal SAxiWReadyxS : std_ulogic := '0'; + signal SAxiAWReadyxS : std_ulogic := '0'; + signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0'); + signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0'); + -- Signals of access to the register bank + signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0'); + signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal RdValidxS : std_ulogic := '0'; + signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0'); + signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); + signal WrValidxS : std_ulogic := '0'; + -- Registers list + signal ScalpPacketWriteDataPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal ScalpPacketWriteDataPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal ScalpPacketReadDataPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal ScalpPacketReadDataPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal ScalpPacketCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal ScalpPacketCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal ScalpPacketStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal ScalpPacketStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal TXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal TXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal TXRdDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal TXRdDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal RXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal RXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal RXRdDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal RXRdDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal LocNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + signal LocNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000"; + +begin + + assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE + report "RDATA and DATA vectors must be the same" severity failure; + + assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE + report "ARADDR and ADDR vectors must be the same" severity failure; + + assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE + report "WDATA and DATA vectors must be the same" severity failure; + + assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE + report "AWADDR and ADDR vectors must be the same" severity failure; + + EntityIOxB : block is + begin -- block EntityIOxB + + -- Clock and reset + SAxiClkxAS : SAxiClkxC <= SAxiClkxCI; + SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI; + -- Read Channel + SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS; + SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS; + SAxiRDataxAS : SAxiRDataxDO <= RdDataxD; + RdValidxAS : RdValidxS <= SAxiARValidxSI; + RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0); + SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY; + -- Write Channel + SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY; + SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS; + SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS; + SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS; + WrValidxAS : WrValidxS <= SAxiWValidxSI; + WrDataxAS : WrDataxD <= SAxiWDataxDI; + WrAddrOutxAS : WrAddrxD <= WrAddrxDP; + WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when + SAxiAWValidxSI = '1' else + WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0); + + end block EntityIOxB; + + AXI4LitexB : block is + begin -- block AXI4LitexB + + ReadChannelxB : block is + begin -- block ReadChannelxB + + ReadAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is + + variable StateAfterResetxS : boolean := true; + + begin -- process ReadAddrChanxP + if SAxiRstxRAN = '0' then + SAxiARReadyxS <= '0'; + StateAfterResetxS := true; + elsif rising_edge(SAxiClkxC) then + if StateAfterResetxS = true then + SAxiARReadyxS <= '1'; + StateAfterResetxS := false; + else + SAxiARReadyxS <= SAxiARReadyxS; + end if; + + if SAxiARValidxSI = '1' then + SAxiARReadyxS <= '0'; + end if; + + if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then + SAxiARReadyxS <= '1'; + end if; + end if; + end process ReadAddrChanxP; + + ReadDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is + begin -- process ReadDataChanxP + if SAxiRstxRAN = '0' then + SAxiRValidxS <= '0'; + elsif rising_edge(SAxiClkxC) then + SAxiRValidxS <= SAxiRValidxS; + + if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then + SAxiRValidxS <= '1'; + end if; + + if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then + SAxiRValidxS <= '0'; + end if; + end if; + end process ReadDataChanxP; + + end block ReadChannelxB; + + WriteChannelxB : block is + begin --block WriteChannelxB + + WrAddrRegxP : process (SAxiClkxC, SAxiRstxRAN) is + begin -- process WrAddrRegxP + if SAxiRstxRAN = '0' then + WrAddrxDP <= (others => '0'); + elsif rising_edge(SAxiClkxC) then + WrAddrxDP <= WrAddrxDN; + end if; + end process WrAddrRegxP; + + WriteAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is + + variable StateAfterResetxS : boolean := true; + + begin -- process WriteAddrChanxP + if SAxiRstxRAN = '0' then + SAxiAWReadyxS <= '0'; + StateAfterResetxS := true; + elsif rising_edge(SAxiClkxC) then + if StateAfterResetxS = true then + SAxiAWReadyxS <= '1'; + StateAfterResetxS := false; + else + SAxiAWReadyxS <= SAxiAWReadyxS; + end if; + + if SAxiAWValidxSI = '1' then + SAxiAWReadyxS <= '0'; + end if; + + if SAxiWValidxSI = '1' then + SAxiAWReadyxS <= '1'; + end if; + end if; + end process WriteAddrChanxP; + + WriteDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is + begin -- process WriteDataChanxP + if SAxiRstxRAN = '0' then + SAxiWReadyxS <= '0'; + elsif rising_edge(SAxiClkxC) then + SAxiWReadyxS <= SAxiWReadyxS; + + if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then + SAxiWReadyxS <= '1'; + end if; + + if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then + SAxiWReadyxS <= '0'; + end if; + end if; + end process WriteDataChanxP; + + WriteRespChanxP : process (SAxiClkxC, SAxiRstxRAN) is + begin -- process WriteRespChanxP + if SAxiRstxRAN = '0' then + SAxiBValidxS <= '0'; + elsif rising_edge(SAxiClkxC) then + SAxiBValidxS <= SAxiBValidxS; + + if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then + SAxiBValidxS <= '1'; + end if; + + if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then + SAxiBValidxS <= '0'; + end if; + end if; + end process WriteRespChanxP; + + end block WriteChannelxB; + + end block AXI4LitexB; + + ScalpRouterRegBankxB : block is + begin -- block ScalpRouterRegBankxB + + WriteRegPortxP : process (LocNetAddrPortxDP, RXRdDataCntxDI, + RXWrDataCntxDI, ScalpPacketCtrlPortxDP, + ScalpPacketReadDataxDI, ScalpPacketStatusxDI, + ScalpPacketWriteDataPortxDP, TXRdDataCntxDI, + TXWrDataCntxDI, WrAddrxD, WrDataxD, + WrValidxS) is + begin -- process WriteRegPortxP + ScalpPacketWriteDataPortxDN <= ScalpPacketWriteDataPortxDP; + ScalpPacketReadDataPortxDN <= ScalpPacketReadDataxDI; + ScalpPacketCtrlPortxDN <= ScalpPacketCtrlPortxDP; + ScalpPacketStatusPortxDN <= ScalpPacketStatusxDI; + TXWrDataCntPortxDN <= TXWrDataCntxDI; + TXRdDataCntPortxDN <= TXRdDataCntxDI; + RXWrDataCntPortxDN <= RXWrDataCntxDI; + RXRdDataCntPortxDN <= RXRdDataCntxDI; + LocNetAddrPortxDN <= LocNetAddrPortxDP; + + if WrValidxS = '1' then + case WrAddrxD is + when x"000" => ScalpPacketWriteDataPortxDN <= WrDataxD; + when x"008" => ScalpPacketCtrlPortxDN <= WrDataxD; + when x"00C" => ScalpPacketCtrlPortxDN <= ScalpPacketCtrlPortxDP or WrDataxD; + when x"010" => ScalpPacketCtrlPortxDN <= ScalpPacketCtrlPortxDP and not WrDataxD; + when x"028" => LocNetAddrPortxDN <= WrDataxD; + + when others => null; + end case; + end if; + end process WriteRegPortxP; + + ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is + begin -- process ReadRegPortxP + if SAxiRstxRAN = '0' then + RdDataxD <= (others => '0'); + elsif rising_edge(SAxiClkxC) then + RdDataxD <= (others => '0'); + + if RdValidxS = '1' then + case RdAddrxD is + when x"000" => RdDataxD <= ScalpPacketWriteDataPortxDP; + when x"004" => RdDataxD <= ScalpPacketReadDataPortxDP; + when x"014" => RdDataxD <= ScalpPacketStatusPortxDP; + when x"018" => RdDataxD <= TXWrDataCntPortxDP; + when x"01C" => RdDataxD <= TXRdDataCntPortxDP; + when x"020" => RdDataxD <= RXWrDataCntPortxDP; + when x"024" => RdDataxD <= RXRdDataCntPortxDP; + when x"028" => RdDataxD <= LocNetAddrPortxDP; + + when others => RdDataxD <= (others => '0'); + end case; + end if; + end if; + end process ReadRegPortxP; + + UpdateRegBankxP : process (SAxiClkxC, SAxiRstxRAN) is + begin -- process UpdateRegBankxP + if SAxiRstxRAN = '0' then + ScalpPacketWriteDataPortxDP <= x"00000000"; + ScalpPacketReadDataPortxDP <= x"00000000"; + ScalpPacketCtrlPortxDP <= x"00000000"; + ScalpPacketStatusPortxDP <= x"00000000"; + TXWrDataCntPortxDP <= x"00000000"; + TXRdDataCntPortxDP <= x"00000000"; + RXWrDataCntPortxDP <= x"00000000"; + RXRdDataCntPortxDP <= x"00000000"; + LocNetAddrPortxDP <= x"00000000"; + + elsif rising_edge(SAxiClkxC) then + ScalpPacketWriteDataPortxDP <= ScalpPacketWriteDataPortxDN; + ScalpPacketReadDataPortxDP <= ScalpPacketReadDataPortxDN; + ScalpPacketCtrlPortxDP <= ScalpPacketCtrlPortxDN; + ScalpPacketStatusPortxDP <= ScalpPacketStatusPortxDN; + TXWrDataCntPortxDP <= TXWrDataCntPortxDN; + TXRdDataCntPortxDP <= TXRdDataCntPortxDN; + RXWrDataCntPortxDP <= RXWrDataCntPortxDN; + RXRdDataCntPortxDP <= RXRdDataCntPortxDN; + LocNetAddrPortxDP <= LocNetAddrPortxDN; + + end if; + end process UpdateRegBankxP; + + end block ScalpRouterRegBankxB; + +end behavioral; diff --git a/ips/hw/scalp_router_regbank/src/sim/tb_scalp_router_regbank.vhd b/ips/hw/scalp_router_regbank/src/sim/tb_scalp_router_regbank.vhd new file mode 100644 index 0000000000000000000000000000000000000000..0ebfb27c2eaeada1924f9f302691763adf38daf2 --- /dev/null +++ b/ips/hw/scalp_router_regbank/src/sim/tb_scalp_router_regbank.vhd @@ -0,0 +1,34 @@ +---------------------------------------------------------------------------------- +-- _ _ +-- | |_ ___ _ __(_)__ _ +-- | ' \/ -_) '_ \ / _` | +-- |_||_\___| .__/_\__,_| +-- |_| +-- +---------------------------------------------------------------------------------- +-- +-- Company: hepia +-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch +-- +-- Module Name: tb_scalp_router_regbank - arch +-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +-- Tool version: 2020.2 +-- Description: Testbench for scalp_router_regbank +-- +-- Last update: 2021-05-20 11:02:08 +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_scalp_router_regbank is +end tb_scalp_router_regbank; + + +architecture behavioral of tb_scalp_router_regbank is + +begin + +end behavioral; diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_1.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_1.tcl new file mode 100644 index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38 --- /dev/null +++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_1.tcl @@ -0,0 +1,145 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to validate C_AXI4_ADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to validate C_AXI4_ARADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to validate C_AXI4_AWADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to validate C_AXI4_BRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to validate C_AXI4_DATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to validate C_AXI4_RDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to validate C_AXI4_RRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to validate C_AXI4_WDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to validate C_AXI4_WSTRB_SIZE + return true +} + + +proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE} +} + diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_2.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_2.tcl new file mode 100644 index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38 --- /dev/null +++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_2.tcl @@ -0,0 +1,145 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to validate C_AXI4_ADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to validate C_AXI4_ARADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to validate C_AXI4_AWADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to validate C_AXI4_BRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to validate C_AXI4_DATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to validate C_AXI4_RDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to validate C_AXI4_RRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to validate C_AXI4_WDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to validate C_AXI4_WSTRB_SIZE + return true +} + + +proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE} +} + diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_3.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_3.tcl new file mode 100644 index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38 --- /dev/null +++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_3.tcl @@ -0,0 +1,145 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to validate C_AXI4_ADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to validate C_AXI4_ARADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to validate C_AXI4_AWADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to validate C_AXI4_BRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to validate C_AXI4_DATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to validate C_AXI4_RDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to validate C_AXI4_RRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to validate C_AXI4_WDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to validate C_AXI4_WSTRB_SIZE + return true +} + + +proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE} +} + diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v1_0.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v1_0.tcl new file mode 100644 index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38 --- /dev/null +++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v1_0.tcl @@ -0,0 +1,145 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to validate C_AXI4_ADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to validate C_AXI4_ARADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to validate C_AXI4_AWADDR_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to validate C_AXI4_BRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to validate C_AXI4_DATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to validate C_AXI4_RDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to validate C_AXI4_RRESP_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to validate C_AXI4_WDATA_SIZE + return true +} + +proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to validate C_AXI4_WSTRB_SIZE + return true +} + + +proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE} +} + +proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE} +} + diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.gitignore b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..88ce8e45268ba077e8cc08ee6d34025597f3db35 --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.gitignore @@ -0,0 +1,23 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Git ignore file +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +# Ignore generated project directory +scalp_axis_fifo_wrapper diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/.prompt_colors.tcl new file mode 100644 index 0000000000000000000000000000000000000000..a3d35bce44c1d0b107addcf8f3fc946371859bc2 --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/.prompt_colors.tcl @@ -0,0 +1,47 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Console color print utility +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +# Try to set a variable with an execution command +# If the command fails, set the variable to an empty string +# cmd - The command to be executed +# return The variable to be set +proc try_setexec {cmd} { + set code [catch { set var [exec {*}$cmd] } ] + if { $code != 0 } { set var "" } + + return ${var} +} + +# Text attributes +set RESET [try_setexec "tput sgr0"] +set BOLD [try_setexec "tput bold"] +set ITALIC [try_setexec "tput sitm"] +set BLINK [try_setexec "tput blink"] +set HIGHL [try_setexec "tput smso"] + +# Text colors +set RED [try_setexec "tput setaf 1"] +set GREEN [try_setexec "tput setaf 2"] +set YELLOW [try_setexec "tput setaf 3"] +set BLUE [try_setexec "tput setaf 4"] +set MAGENTA [try_setexec "tput setaf 5"] +set CYAN [try_setexec "tput setaf 6"] +set WHITE [try_setexec "tput setaf 7"] diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/clean_prj_scalp_axis_fifo_wrapper.sh b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/clean_prj_scalp_axis_fifo_wrapper.sh new file mode 100755 index 0000000000000000000000000000000000000000..3d3e33cc1cba4e96d747d9b4464b2e668614b546 --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/clean_prj_scalp_axis_fifo_wrapper.sh @@ -0,0 +1,35 @@ +#!/bin/sh + +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Cleanup project directory +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +echo "> Cleanup project directory..." + +PRJ_DIR=.. + +# Clean current directory +rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null + +# Remove generated project directory +rm -rf ${PRJ_DIR}/scalp_axis_fifo_wrapper/ 2> /dev/null + +echo "> Done" + diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_axis_fifo_wrapper.sh b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_axis_fifo_wrapper.sh new file mode 100755 index 0000000000000000000000000000000000000000..b775def065e02be131e023e061d97c71a0f975f5 --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_axis_fifo_wrapper.sh @@ -0,0 +1,27 @@ +#!/bin/sh + +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Create Vivado project +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +echo "> Create Vivado project..." +vivado -nojournal -nolog -mode tcl -source create_prj_scalp_axis_fifo_wrapper.tcl -notrace +echo "> Done" + diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_axis_fifo_wrapper.tcl b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_axis_fifo_wrapper.tcl new file mode 100644 index 0000000000000000000000000000000000000000..bdf4f4f3c430355f45915cf1fa471191c581f712 --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_axis_fifo_wrapper.tcl @@ -0,0 +1,164 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: TCL script for re-creating Vivado project 'scalp_axis_fifo_wrapper' +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +# Include files +source utils.tcl + +set PRJ_DIR ".." +set prj_name "scalp_axis_fifo_wrapper" +set PKG_DIR "${PRJ_DIR}/../../../../../packages" +set SOC_DIR "${PRJ_DIR}/../../../../../soc/" + +# Set project type +set PRJ_TYPE "COMP_PRJ_TYPE" + +# Create a variable to store the start time +set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}] + +# Set the original project directory path for adding/importing sources in the new project +set src_dir "${PRJ_DIR}/../src" +set ip_dir "${PRJ_DIR}/../../../../../ips/hw" +set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw" +set comp_dir "${ip_dir}/$prj_name" +set comp_src_dir "${comp_dir}/src" +set pkg_src_dir "${PKG_DIR}/hw" +set soc_src_dir "${SOC_DIR}/hw" +print_status "Set directory paths" "OK" + +# Create the project +create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2 +set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project] +set_property target_language VHDL [current_project] +print_status "Create project" "OK" + +# Map the IP Repository so that custom IP is included +set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset] +update_ip_catalog + +#---------------------------------------------------------------- +# Add project sources +#---------------------------------------------------------------- + +# Get HDL source files directory +if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { + set hdl_src_dir "${src_dir}/hdl" + set sim_src_dir "${src_dir}/sim" +} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { + # components sources are stored in an external directory + set hdl_src_dir "${comp_src_dir}/hdl" + set sim_src_dir "${comp_src_dir}/sim" +} + +# add HDL source files +set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd] +set verilog_src_file_list [findFiles $hdl_src_dir *.v] +set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv] +set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list] + +if {$hdl_src_file_list != ""} { + add_files -norecurse $hdl_src_file_list +} else { + print_status "No sources to be added" "WARNING" +} + +# Set VHDL version +foreach j $vhdl_src_file_list { + set_property file_type {VHDL 2008} [get_files $j] + print_status "VHDL 2008 mode configured for the file $j" "OK" +} +print_status "VHDL 2008 mode configured for project sources" "OK" + +# Add constraint files and IPs source files +if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { + # add the constraints file (XDC) + add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc + set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc] + + # add IPs source files + +} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { + # add IPs source files + read_ip $comp_src_dir/ip_core/scalp_axis_fifo/scalp_axis_fifo.xci + + # add IP-XACT source file + #add_files -norecurse $comp_dir/component.xml +} +print_status "Add project sources" "OK" + +# Set packages libraries if any +#set_property library library_name [get_files $src_dir/hdl/package_name.vhd] +#update_compile_order -fileset sources_1 + +# Create the IP Integrator portion of the design +#create_bd_design "axi_design" +#update_compile_order -fileset sources_1 + +# launch the TCL script to generate the IPI design +source $src_dir/ipi_tcl/${prj_name}_ipi.tcl +print_status "Add IPI design" "OK" + +# Set the top level design +set_property top $prj_name [current_fileset] +update_compile_order -fileset sources_1 + +# Add simulation sources +set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd] +set verilog_sim_file_list [findFiles $sim_src_dir *.v] +set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv] +set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list] + +if {$hdl_sim_file_list != ""} { + add_files -fileset sim_1 -norecurse $hdl_sim_file_list + update_compile_order -fileset sim_1 + print_status "Add simulation sources" "OK" +} else { + print_status "No simulation sources to be added" "WARNING" +} + +foreach j $vhdl_sim_file_list { + set_property file_type {VHDL 2008} [get_files $j] + print_status "VHDL 2008 mode configured for the file $j" "OK" +} +print_status "VHDL 2008 mode configured for simulation sources" "OK" + +# Add packages sources + set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd] + add_files -norecurse $vhdl_pkg_file_list + foreach j $vhdl_pkg_file_list { + set_property file_type {VHDL 2008} [get_files $j] + print_status "VHDL 2008 mode configured for the file $j" "OK" + set_property is_enabled true [get_files $j] + set_property library xil_defaultlib [get_files $j] + } +print_status "Add packages sources" "OK" +print_status "VHDL 2008 mode configured for packages sources" "OK" + +# Add SoC wrapper sources files + + +# Set the completion time +set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}] + +# Display the start and end time to the screen +puts $start_time +puts $end_time + +exit diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/open_prj_scalp_axis_fifo_wrapper.sh b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/open_prj_scalp_axis_fifo_wrapper.sh new file mode 100755 index 0000000000000000000000000000000000000000..85618666fde1da39dfb08782f2fcc2fd131062ba --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/open_prj_scalp_axis_fifo_wrapper.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Open Vivado project GUI +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +echo "> Open Vivado GUI..." +vivado -nojournal -nolog -notrace ../scalp_axis_fifo_wrapper/scalp_axis_fifo_wrapper.xpr diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/utils.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c55785a4e7f418e2310141b854090b6a923f7032 --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/.scripts/utils.tcl @@ -0,0 +1,62 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Project management utilities +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +# findFiles +# basedir - the directory to start looking in +# pattern - A pattern, as defined by the glob command, that the files must match +proc findFiles { basedir pattern } { + + # Fix the directory name, this ensures the directory name is in the + # native format for the platform and contains a final directory seperator + set basedir [string trimright [file join [file normalize $basedir] { }]] + set fileList {} + + # Look in the current directory for matching files, -type {f r} + # means ony readable normal files are looked at, -nocomplain stops + # an error being thrown if the returned list is empty + foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] { + lappend fileList $fileName + } + + # Now look for any sub direcories in the current directory + foreach dirName [glob -nocomplain -type {d r} -path $basedir *] { + # Recusively call the routine on the sub directory and append any + # new files to the results + set subDirList [findFiles $dirName $pattern] + if { [llength $subDirList] > 0 } { + foreach subDirFile $subDirList { + lappend fileList $subDirFile + } + } + } + return $fileList +} + + +# Print a progress status +# str The string describing the current status +# status The status as a string (eg. "OK", "FAILED") +proc print_status {str status} { + set MAX_STR_LENGTH 70 + source .prompt_colors.tcl + puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}" +} + diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/setup.sh b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/setup.sh new file mode 100755 index 0000000000000000000000000000000000000000..2cf8d6e9179018d39fa12a4b6bf939873986bf02 --- /dev/null +++ b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/lin64/setup.sh @@ -0,0 +1,28 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_axis_fifo_wrapper +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: TCL script creating aliases for Vivado project management scripts +# +# Last update: 2021-05-21 08:14:52 +# +################################################################################## + +# Create aliases +alias create_project='cd .scripts && ./create_prj_scalp_axis_fifo_wrapper.sh && cd ..' +alias clean_project='cd .scripts && ./clean_prj_scalp_axis_fifo_wrapper.sh && cd ..' +alias export_hw='cd .scripts && ./export_hw_scalp_axis_fifo_wrapper.sh && cd ..' +alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_axis_fifo_wrapper.sh && cd ..' +alias load_bitstream='cd .scripts && ./load_bitstream_scalp_axis_fifo_wrapper.sh && cd ..' +alias open_gui='cd .scripts && ./open_prj_scalp_axis_fifo_wrapper.sh && cd ..' diff --git a/ips/vivado/scalp_axis_fifo_wrapper/2020.2/src/ipi_tcl/scalp_axis_fifo_wrapper_ipi.tcl b/ips/vivado/scalp_axis_fifo_wrapper/2020.2/src/ipi_tcl/scalp_axis_fifo_wrapper_ipi.tcl new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/.gitignore b/ips/vivado/scalp_router_regbank/2020.2/lin64/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..e97e521cfd1504b1fde0fb377fb960255fcca65c --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/.gitignore @@ -0,0 +1,23 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Git ignore file +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +# Ignore generated project directory +scalp_router_regbank diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/.prompt_colors.tcl new file mode 100644 index 0000000000000000000000000000000000000000..475c134b1bfb400e2794aae17bfd13fbd113c421 --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/.prompt_colors.tcl @@ -0,0 +1,47 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Console color print utility +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +# Try to set a variable with an execution command +# If the command fails, set the variable to an empty string +# cmd - The command to be executed +# return The variable to be set +proc try_setexec {cmd} { + set code [catch { set var [exec {*}$cmd] } ] + if { $code != 0 } { set var "" } + + return ${var} +} + +# Text attributes +set RESET [try_setexec "tput sgr0"] +set BOLD [try_setexec "tput bold"] +set ITALIC [try_setexec "tput sitm"] +set BLINK [try_setexec "tput blink"] +set HIGHL [try_setexec "tput smso"] + +# Text colors +set RED [try_setexec "tput setaf 1"] +set GREEN [try_setexec "tput setaf 2"] +set YELLOW [try_setexec "tput setaf 3"] +set BLUE [try_setexec "tput setaf 4"] +set MAGENTA [try_setexec "tput setaf 5"] +set CYAN [try_setexec "tput setaf 6"] +set WHITE [try_setexec "tput setaf 7"] diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/clean_prj_scalp_router_regbank.sh b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/clean_prj_scalp_router_regbank.sh new file mode 100755 index 0000000000000000000000000000000000000000..8ffdba607f28979d60337224951f1e5676148d60 --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/clean_prj_scalp_router_regbank.sh @@ -0,0 +1,35 @@ +#!/bin/sh + +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Cleanup project directory +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +echo "> Cleanup project directory..." + +PRJ_DIR=.. + +# Clean current directory +rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null + +# Remove generated project directory +rm -rf ${PRJ_DIR}/scalp_router_regbank/ 2> /dev/null + +echo "> Done" + diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/create_prj_scalp_router_regbank.sh b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/create_prj_scalp_router_regbank.sh new file mode 100755 index 0000000000000000000000000000000000000000..52df656e2024685303e7d52f9c02abd5105a5244 --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/create_prj_scalp_router_regbank.sh @@ -0,0 +1,27 @@ +#!/bin/sh + +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Create Vivado project +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +echo "> Create Vivado project..." +vivado -nojournal -nolog -mode tcl -source create_prj_scalp_router_regbank.tcl -notrace +echo "> Done" + diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/create_prj_scalp_router_regbank.tcl b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/create_prj_scalp_router_regbank.tcl new file mode 100644 index 0000000000000000000000000000000000000000..9d3f31fff9d7054fab86fc58f99cd755785a05a1 --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/create_prj_scalp_router_regbank.tcl @@ -0,0 +1,154 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: TCL script for re-creating Vivado project 'scalp_router_regbank' +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +# Include files +source utils.tcl + +set PRJ_DIR ".." +set prj_name "scalp_router_regbank" +set PKG_DIR "${PRJ_DIR}/../../../../../packages" +set SOC_DIR "${PRJ_DIR}/../../../../../soc/" + +# Set project type +set PRJ_TYPE "COMP_PRJ_TYPE" + +# Create a variable to store the start time +set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}] + +# Set the original project directory path for adding/importing sources in the new project +set src_dir "${PRJ_DIR}/../src" +set ip_dir "${PRJ_DIR}/../../../../../ips/hw" +set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw" +set comp_dir "${ip_dir}/$prj_name" +set comp_src_dir "${comp_dir}/src" +set pkg_src_dir "${PKG_DIR}/hw" +set soc_src_dir "${SOC_DIR}/hw" +print_status "Set directory paths" "OK" + +# Create the project +create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2 +set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project] +set_property target_language VHDL [current_project] +print_status "Create project" "OK" + +# Map the IP Repository so that custom IP is included +set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset] +update_ip_catalog + +#---------------------------------------------------------------- +# Add project sources +#---------------------------------------------------------------- + +# Get HDL source files directory +if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { + set hdl_src_dir "${src_dir}/hdl" + set sim_src_dir "${src_dir}/sim" +} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { + # components sources are stored in an external directory + set hdl_src_dir "${comp_src_dir}/hdl" + set sim_src_dir "${comp_src_dir}/sim" +} + +# add HDL source files +set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd] +set verilog_src_file_list [findFiles $hdl_src_dir *.v] +set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv] +set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list] + +if {$hdl_src_file_list != ""} { + add_files -norecurse $hdl_src_file_list +} else { + print_status "No sources to be added" "WARNING" +} + +# Set VHDL version +foreach j $vhdl_src_file_list { + set_property file_type {VHDL 2008} [get_files $j] + print_status "VHDL 2008 mode configured for the file $j" "OK" +} +print_status "VHDL 2008 mode configured for project sources" "OK" + +# Add constraint files and IPs source files +if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { + # add the constraints file (XDC) + add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc + set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc] + + # add IPs source files + +} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { + # add IPs source files + + # add IP-XACT source file + #add_files -norecurse $comp_dir/component.xml +} +print_status "Add project sources" "OK" + +# Set packages libraries if any +#set_property library library_name [get_files $src_dir/hdl/package_name.vhd] +#update_compile_order -fileset sources_1 + +# Create the IP Integrator portion of the design +#create_bd_design "axi_design" +#update_compile_order -fileset sources_1 + +# launch the TCL script to generate the IPI design +source $src_dir/ipi_tcl/${prj_name}_ipi.tcl +print_status "Add IPI design" "OK" + +# Set the top level design +set_property top $prj_name [current_fileset] +update_compile_order -fileset sources_1 + +# Add simulation sources +set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd] +set verilog_sim_file_list [findFiles $sim_src_dir *.v] +set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv] +set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list] + +if {$hdl_sim_file_list != ""} { + add_files -fileset sim_1 -norecurse $hdl_sim_file_list + update_compile_order -fileset sim_1 + print_status "Add simulation sources" "OK" +} else { + print_status "No simulation sources to be added" "WARNING" +} + +foreach j $vhdl_sim_file_list { + set_property file_type {VHDL 2008} [get_files $j] + print_status "VHDL 2008 mode configured for the file $j" "OK" +} +print_status "VHDL 2008 mode configured for simulation sources" "OK" + +# Add packages sources + + +# Add SoC wrapper sources files + + +# Set the completion time +set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}] + +# Display the start and end time to the screen +puts $start_time +puts $end_time + +exit diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/open_prj_scalp_router_regbank.sh b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/open_prj_scalp_router_regbank.sh new file mode 100755 index 0000000000000000000000000000000000000000..60025cb84969803051b97cf741ea459e55c4d39b --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/open_prj_scalp_router_regbank.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Open Vivado project GUI +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +echo "> Open Vivado GUI..." +vivado -nojournal -nolog -notrace ../scalp_router_regbank/scalp_router_regbank.xpr diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/utils.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1d7a52db84130a882d4c84e1aa0306d519abcf6c --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/.scripts/utils.tcl @@ -0,0 +1,62 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: Project management utilities +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +# findFiles +# basedir - the directory to start looking in +# pattern - A pattern, as defined by the glob command, that the files must match +proc findFiles { basedir pattern } { + + # Fix the directory name, this ensures the directory name is in the + # native format for the platform and contains a final directory seperator + set basedir [string trimright [file join [file normalize $basedir] { }]] + set fileList {} + + # Look in the current directory for matching files, -type {f r} + # means ony readable normal files are looked at, -nocomplain stops + # an error being thrown if the returned list is empty + foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] { + lappend fileList $fileName + } + + # Now look for any sub direcories in the current directory + foreach dirName [glob -nocomplain -type {d r} -path $basedir *] { + # Recusively call the routine on the sub directory and append any + # new files to the results + set subDirList [findFiles $dirName $pattern] + if { [llength $subDirList] > 0 } { + foreach subDirFile $subDirList { + lappend fileList $subDirFile + } + } + } + return $fileList +} + + +# Print a progress status +# str The string describing the current status +# status The status as a string (eg. "OK", "FAILED") +proc print_status {str status} { + set MAX_STR_LENGTH 70 + source .prompt_colors.tcl + puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}" +} + diff --git a/ips/vivado/scalp_router_regbank/2020.2/lin64/setup.sh b/ips/vivado/scalp_router_regbank/2020.2/lin64/setup.sh new file mode 100755 index 0000000000000000000000000000000000000000..dec9ea036d216e7c0655efd20775386261e9a86a --- /dev/null +++ b/ips/vivado/scalp_router_regbank/2020.2/lin64/setup.sh @@ -0,0 +1,28 @@ +################################################################################## +# _ _ +# | |_ ___ _ __(_)__ _ +# | ' \/ -_) '_ \ / _` | +# |_||_\___| .__/_\__,_| +# |_| +# +################################################################################## +# +# Company: hepia +# Author: Joachim Schmidt <joachim.schmidt@hesge.ch +# +# Project Name: scalp_router_regbank +# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 +# Tool version: 2020.2 +# Description: TCL script creating aliases for Vivado project management scripts +# +# Last update: 2021-05-20 11:02:08 +# +################################################################################## + +# Create aliases +alias create_project='cd .scripts && ./create_prj_scalp_router_regbank.sh && cd ..' +alias clean_project='cd .scripts && ./clean_prj_scalp_router_regbank.sh && cd ..' +alias export_hw='cd .scripts && ./export_hw_scalp_router_regbank.sh && cd ..' +alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_router_regbank.sh && cd ..' +alias load_bitstream='cd .scripts && ./load_bitstream_scalp_router_regbank.sh && cd ..' +alias open_gui='cd .scripts && ./open_prj_scalp_router_regbank.sh && cd ..' diff --git a/ips/vivado/scalp_router_regbank/2020.2/src/ipi_tcl/scalp_router_regbank_ipi.tcl b/ips/vivado/scalp_router_regbank/2020.2/src/ipi_tcl/scalp_router_regbank_ipi.tcl new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd index df2a4bd94c0cd87f7cffcacc02f91b331f14a7c6..8eea268bbb882881c9d7da275dde0bcf48567310 100644 --- a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd +++ b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd @@ -15,7 +15,7 @@ -- Tool version: 2020.2 -- Description: AXI4 format bus signals. -- --- Last update: 2021-05-18 +-- Last update: 2021-05-21 -- --------------------------------------------------------------------------------- @@ -65,6 +65,20 @@ package axi4_pkg is constant C_NO_AXI4_S2M : t_axi4s2m := (ReadyxS => '0'); constant C_ON_AXI4_S2M : t_axi4s2m := (ReadyxS => '1'); + type t_axi4_dual_clk is record + RXClkxC : std_ulogic; + TXClkxC : std_ulogic; + end record t_axi4_dual_clk; + + constant C_NO_AXI4_DUAL_CLK : t_axi4_dual_clk := (RXClkxC => '0', + TXClkxC => '0'); + + type t_axi4_rst is record + RstxRAN : std_ulogic; + end record t_axi4_rst; + + constant C_NO_AXI4_RST : t_axi4_rst := (RstxRAN => '1'); + -- Non-Generic Vector of AXI4 Framing Bus --------------------------------------------------------------------------- -- constant C_SIM_VIVADO_VECTOR_SIZE : integer := 6; diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd index 3ad3db1856c3e25bc35a308ce9c64856cea7ad3f..6f2139838c2e60aaedc19c4f6bb3dce2bf5eb9e9 100644 --- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd +++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd @@ -15,7 +15,7 @@ -- Tool version: 2020.2 -- Description: scalp_zynqps_wrapper -- --- Last update: 2021-05-03 +-- Last update: 2021-06-01 -- --------------------------------------------------------------------------------- @@ -27,46 +27,50 @@ entity scalp_zynqps_wrapper is port ( -- Processor interface - FIXED_IO_ps_clk : inout std_logic; - FIXED_IO_ps_porb : inout std_logic; - FIXED_IO_ps_srstb : inout std_logic; - FclkClk0xCO : out std_logic; - FclkReset0xRO : out std_logic; + FIXED_IO_ps_clk : inout std_logic; + FIXED_IO_ps_porb : inout std_logic; + FIXED_IO_ps_srstb : inout std_logic; + FclkClk0xCO : out std_logic; + FclkReset0xRO : out std_logic; -- DDR interface - DDR_addr : inout std_logic_vector (14 downto 0); - DDR_ba : inout std_logic_vector (2 downto 0); - DDR_cas_n : inout std_logic; - DDR_ck_n : inout std_logic; - DDR_ck_p : inout std_logic; - DDR_cke : inout std_logic; - DDR_cs_n : inout std_logic; - DDR_dm : inout std_logic_vector (3 downto 0); - DDR_dq : inout std_logic_vector (31 downto 0); - DDR_dqs_n : inout std_logic_vector (3 downto 0); - DDR_dqs_p : inout std_logic_vector (3 downto 0); - DDR_odt : inout std_logic; - DDR_ras_n : inout std_logic; - DDR_reset_n : inout std_logic; - DDR_we_n : inout std_logic; - FIXED_IO_ddr_vrn : inout std_logic; - FIXED_IO_ddr_vrp : inout std_logic; + DDR_addr : inout std_logic_vector (14 downto 0); + DDR_ba : inout std_logic_vector (2 downto 0); + DDR_cas_n : inout std_logic; + DDR_ck_n : inout std_logic; + DDR_ck_p : inout std_logic; + DDR_cke : inout std_logic; + DDR_cs_n : inout std_logic; + DDR_dm : inout std_logic_vector (3 downto 0); + DDR_dq : inout std_logic_vector (31 downto 0); + DDR_dqs_n : inout std_logic_vector (3 downto 0); + DDR_dqs_p : inout std_logic_vector (3 downto 0); + DDR_odt : inout std_logic; + DDR_ras_n : inout std_logic; + DDR_reset_n : inout std_logic; + DDR_we_n : inout std_logic; + FIXED_IO_ddr_vrn : inout std_logic; + FIXED_IO_ddr_vrp : inout std_logic; -- USB interface - Usb0VBusPwrFaultxSI : in std_logic; + Usb0VBusPwrFaultxSI : in std_logic; -- SPI1 used as uWire master. Clk, Data and LE signals are outputs -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS - Spi1MOSIxSO : out std_logic; - Spi1SSxSO : out std_logic; - Spi1SclkxCO : out std_logic; + Spi1MOSIxSO : out std_logic; + Spi1SSxSO : out std_logic; + Spi1SclkxCO : out std_logic; -- MIO - FIXED_IO_mio : inout std_logic_vector (53 downto 0); + FIXED_IO_mio : inout std_logic_vector (53 downto 0); -- Scalp Axi Lite interface and IRQ - InterruptxSI : in std_logic; - RdAddrxDO : out std_logic_vector (11 downto 0); - RdDataxDI : in std_logic_vector (31 downto 0); - RdValidxSO : out std_logic; - WrAddrxDO : out std_logic_vector (11 downto 0); - WrDataxDO : out std_logic_vector (31 downto 0); - WrValidxSO : out std_logic); + Irq0xDI : in std_logic_vector(0 to 0); + ScalpPacketWriteDataxDO : out std_logic_vector(31 downto 0); + ScalpPacketReadDataxDI : in std_logic_vector(31 downto 0); + ScalpPacketCtrlxDO : out std_logic_vector(31 downto 0); + ScalpPacketStatusxDI : in std_logic_vector(31 downto 0); + RgbLedsCtrlPortxDO : out std_logic_vector(31 downto 0); + RXRdDataCntxDI : in std_logic_vector(31 downto 0); + RXWrDataCntxDI : in std_logic_vector(31 downto 0); + TXRdDataCntxDI : in std_logic_vector(31 downto 0); + TXWrDataCntxDI : in std_logic_vector(31 downto 0); + LocNetAddrxDO : out std_logic_vector(31 downto 0)); end scalp_zynqps_wrapper; @@ -76,39 +80,43 @@ begin ScalpZynqPSxI : entity work.scalp_zynqps port map ( - DDR_addr => DDR_addr, - DDR_ba => DDR_ba, - DDR_cas_n => DDR_cas_n, - DDR_ck_n => DDR_ck_n, - DDR_ck_p => DDR_ck_p, - DDR_cke => DDR_cke, - DDR_cs_n => DDR_cs_n, - DDR_dm => DDR_dm, - DDR_dq => DDR_dq, - DDR_dqs_n => DDR_dqs_n, - DDR_dqs_p => DDR_dqs_p, - DDR_odt => DDR_odt, - DDR_ras_n => DDR_ras_n, - DDR_reset_n => DDR_reset_n, - DDR_we_n => DDR_we_n, - FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, - FIXED_IO_mio => FIXED_IO_mio, - FIXED_IO_ps_clk => FIXED_IO_ps_clk, - FIXED_IO_ps_porb => FIXED_IO_ps_porb, - FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, - FclkClk0xCO => FclkClk0xCO, - FclkReset0xRO(0) => FclkReset0xRO, - Spi1MOSIxSO => Spi1MOSIxSO, - Spi1SSxSO => Spi1SSxSO, - Spi1SclkxCO => Spi1SclkxCO, - Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI, - InterruptxSI => InterruptxSI, - RdAddrxDO => RdAddrxDO, - RdDataxDI => RdDataxDI, - RdValidxSO => RdValidxSO, - WrAddrxDO => WrAddrxDO, - WrDataxDO => WrDataxDO, - WrValidxSO => WrValidxSO); + DDR_addr => DDR_addr, + DDR_ba => DDR_ba, + DDR_cas_n => DDR_cas_n, + DDR_ck_n => DDR_ck_n, + DDR_ck_p => DDR_ck_p, + DDR_cke => DDR_cke, + DDR_cs_n => DDR_cs_n, + DDR_dm => DDR_dm, + DDR_dq => DDR_dq, + DDR_dqs_n => DDR_dqs_n, + DDR_dqs_p => DDR_dqs_p, + DDR_odt => DDR_odt, + DDR_ras_n => DDR_ras_n, + DDR_reset_n => DDR_reset_n, + DDR_we_n => DDR_we_n, + FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, + FIXED_IO_mio => FIXED_IO_mio, + FIXED_IO_ps_clk => FIXED_IO_ps_clk, + FIXED_IO_ps_porb => FIXED_IO_ps_porb, + FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, + FclkClk0xCO => FclkClk0xCO, + FclkReset0xRO(0) => FclkReset0xRO, + Spi1MOSIxSO => Spi1MOSIxSO, + Spi1SSxSO => Spi1SSxSO, + Spi1SclkxCO => Spi1SclkxCO, + Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI, + Irq0xDI => Irq0xDI, + ScalpPacketWriteDataxDO => ScalpPacketWriteDataxDO, + ScalpPacketReadDataxDI => ScalpPacketReadDataxDI, + ScalpPacketCtrlxDO => ScalpPacketCtrlxDO, + ScalpPacketStatusxDI => ScalpPacketStatusxDI, + RXRdDataCntxDI => RXRdDataCntxDI, + RXWrDataCntxDI => RXWrDataCntxDI, + TXRdDataCntxDI => TXRdDataCntxDI, + TXWrDataCntxDI => TXWrDataCntxDI, + RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO, + LocNetAddrxDO => LocNetAddrxDO); end arch; diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl index b38d8c4bdeb03260b6f25e9bd293a6229ee787f4..0f74a828c6348c9ba717a2c32cee413e19fa95bd 100644 --- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl +++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl @@ -126,7 +126,7 @@ xilinx.com:ip:xlconstant:1.1\ xilinx.com:ip:xlconcat:2.1\ xilinx.com:ip:processing_system7:5.5\ xilinx.com:ip:proc_sys_reset:5.0\ -hepia.hesge.ch:user:scalp_axi4lite:1.2\ +hepia.hesge.ch:user:scalp_router_regbank:0.3\ hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\ xilinx.com:ip:util_vector_logic:2.0\ xilinx.com:ip:vio:3.0\ @@ -204,18 +204,21 @@ proc create_root_design { parentCell } { CONFIG.FREQ_HZ {125000000} \ ] $FclkClk0xCO set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ] - set InterruptxSI [ create_bd_port -dir I -type intr InterruptxSI ] - set RdAddrxDO [ create_bd_port -dir O -from 11 -to 0 RdAddrxDO ] - set RdDataxDI [ create_bd_port -dir I -from 31 -to 0 RdDataxDI ] - set RdValidxSO [ create_bd_port -dir O RdValidxSO ] + set Irq0xDI [ create_bd_port -dir I -from 0 -to 0 Irq0xDI ] + set LocNetAddrxDO [ create_bd_port -dir O -from 31 -to 0 -type data LocNetAddrxDO ] + set RXRdDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data RXRdDataCntxDI ] + set RXWrDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data RXWrDataCntxDI ] set RgbLedsCtrlPortxDO [ create_bd_port -dir O -from 31 -to 0 RgbLedsCtrlPortxDO ] + set ScalpPacketCtrlxDO [ create_bd_port -dir O -from 31 -to 0 -type data ScalpPacketCtrlxDO ] + set ScalpPacketReadDataxDI [ create_bd_port -dir I -from 31 -to 0 -type data ScalpPacketReadDataxDI ] + set ScalpPacketStatusxDI [ create_bd_port -dir I -from 31 -to 0 -type data ScalpPacketStatusxDI ] + set ScalpPacketWriteDataxDO [ create_bd_port -dir O -from 31 -to 0 -type data ScalpPacketWriteDataxDO ] set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ] set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ] set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ] + set TXRdDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data TXRdDataCntxDI ] + set TXWrDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data TXWrDataCntxDI ] set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ] - set WrAddrxDO [ create_bd_port -dir O -from 11 -to 0 WrAddrxDO ] - set WrDataxDO [ create_bd_port -dir O -from 31 -to 0 WrDataxDO ] - set WrValidxSO [ create_bd_port -dir O WrValidxSO ] # Create instance: gnd_constant, and set properties set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ] @@ -681,8 +684,11 @@ proc create_root_design { parentCell } { # Create instance: rst_ps7_0_125M, and set properties set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ] - # Create instance: scalp_axi4lite_0, and set properties - set scalp_axi4lite_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_axi4lite:1.2 scalp_axi4lite_0 ] + # Create instance: scalp_router_regbank_1, and set properties + set scalp_router_regbank_1 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:0.3 scalp_router_regbank_1 ] + set_property -dict [ list \ + CONFIG.C_AXI4_ADDR_SIZE {8} \ + ] $scalp_router_regbank_1 # Create instance: scalp_safe_firmware_0, and set properties set scalp_safe_firmware_0 [ create_bd_cell -type ip -vlnv hepia.ch:user:scalp_safe_firmware_reg_bank:1.3 scalp_safe_firmware_0 ] @@ -714,35 +720,37 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_router_regbank_1/SAxiLitexDIO] connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO] # Create port connections - connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI] - connect_bd_net -net RdDataxDI_0_1 [get_bd_ports RdDataxDI] [get_bd_pins scalp_axi4lite_0/RdDataxDI] + connect_bd_net -net In0_0_1 [get_bd_ports Irq0xDI] [get_bd_pins irq_xlconcat/In0] + connect_bd_net -net RXRdDataCntxDI_0_1 [get_bd_ports RXRdDataCntxDI] [get_bd_pins scalp_router_regbank_1/RXRdDataCntxDI] + connect_bd_net -net RXWrDataCntxDI_0_1 [get_bd_ports RXWrDataCntxDI] [get_bd_pins scalp_router_regbank_1/RXWrDataCntxDI] + connect_bd_net -net ScalpPacketReadDataxDI_1 [get_bd_ports ScalpPacketReadDataxDI] [get_bd_pins scalp_router_regbank_1/ScalpPacketReadDataxDI] + connect_bd_net -net ScalpPacketStatusxDI_1 [get_bd_ports ScalpPacketStatusxDI] [get_bd_pins scalp_router_regbank_1/ScalpPacketStatusxDI] + connect_bd_net -net TXRdDataCntxDI_0_1 [get_bd_ports TXRdDataCntxDI] [get_bd_pins scalp_router_regbank_1/TXRdDataCntxDI] + connect_bd_net -net TXWrDataCntxDI_0_1 [get_bd_ports TXWrDataCntxDI] [get_bd_pins scalp_router_regbank_1/TXWrDataCntxDI] connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT] connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I] connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins vio_0/clk] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_router_regbank_1/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins vio_0/clk] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1] connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O] connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O] connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O] - connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] - connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO] - connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO] - connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO] - connect_bd_net -net scalp_axi4lite_0_WrAddrxDO [get_bd_ports WrAddrxDO] [get_bd_pins scalp_axi4lite_0/WrAddrxDO] - connect_bd_net -net scalp_axi4lite_0_WrDataxDO [get_bd_ports WrDataxDO] [get_bd_pins scalp_axi4lite_0/WrDataxDO] - connect_bd_net -net scalp_axi4lite_0_WrValidxSO [get_bd_ports WrValidxSO] [get_bd_pins scalp_axi4lite_0/WrValidxSO] + connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_router_regbank_1/SAxiRstxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] + connect_bd_net -net scalp_router_regbank_1_LocNetAddrxDO [get_bd_ports LocNetAddrxDO] [get_bd_pins scalp_router_regbank_1/LocNetAddrxDO] + connect_bd_net -net scalp_router_regbank_1_ScalpPacketCtrlxDO [get_bd_ports ScalpPacketCtrlxDO] [get_bd_pins scalp_router_regbank_1/ScalpPacketCtrlxDO] + connect_bd_net -net scalp_router_regbank_1_ScalpPacketWriteDataxDO [get_bd_ports ScalpPacketWriteDataxDO] [get_bd_pins scalp_router_regbank_1/ScalpPacketWriteDataxDO] connect_bd_net -net scalp_safe_firmware_0_RgbLedsCtrlPortxDO [get_bd_ports RgbLedsCtrlPortxDO] [get_bd_pins scalp_safe_firmware_0/RgbLedsCtrlPortxDO] connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res] connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res] connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0] # Create address segments - assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr] -force - assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force + assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_router_regbank_1/SAxiLitexDIO/Reg] -force + assign_bd_address -offset 0x43C10000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force # Restore current instance diff --git a/tools/config/scalp_axis_fifo_wrapper.json b/tools/config/scalp_axis_fifo_wrapper.json new file mode 100644 index 0000000000000000000000000000000000000000..76f9a08f55c5fab6f0ec38cf0d06a475a9ca0f5e --- /dev/null +++ b/tools/config/scalp_axis_fifo_wrapper.json @@ -0,0 +1,34 @@ +{ + "author" : { + "name" : "Joachim Schmidt", + "email" : "<joachim.schmidt@hesge.ch" + }, + "project" : { + "name" : "scalp_axis_fifo_wrapper", + "type" : "COMP_PRJ_TYPE", + "category" : "IPS", + "vivado_version" : "2020.2", + "target_language" : "VHDL", + "vhdl_version" : "VHDL 2008" + }, + "hardware" : { + "part_name" : "xc7z015clg485-2", + "board_name" : "hepia-cores.ch:scalp_node:part0:0.1" + }, + "components" : { + "packages" : { + "axi4_pkg" : { + "enable" : "true" + } + }, + "ips" : { + "scalp_axis_fifo_wrapper" : + { + "hdl" : "enable", + "xci" : { + "scalp_axis_fifo" : "enable" + } + } + } + } +} diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json index 2f3b4c89e16eb24b8cf8b8ca93c51c25c0a6c74b..b6a3fe0dafbe07195b6499d51cd55ff85339bce3 100644 --- a/tools/config/scalp_firmware.json +++ b/tools/config/scalp_firmware.json @@ -84,6 +84,13 @@ "xci" : { "scalp_packet_fifo" : "enable" } + }, + "scalp_axis_fifo_wrapper" : + { + "hdl" : "enable", + "xci" : { + "scalp_axis_fifo" : "enable" + } } } } diff --git a/tools/config/scalp_router_regbank.json b/tools/config/scalp_router_regbank.json new file mode 100644 index 0000000000000000000000000000000000000000..9c0ab2d918a92e0f7833039c58c019d7781ac00c --- /dev/null +++ b/tools/config/scalp_router_regbank.json @@ -0,0 +1,18 @@ +{ + "author" : { + "name" : "Joachim Schmidt", + "email" : "<joachim.schmidt@hesge.ch" + }, + "project" : { + "name" : "scalp_router_regbank", + "type" : "COMP_PRJ_TYPE", + "category" : "IPS", + "vivado_version" : "2020.2", + "target_language" : "VHDL", + "vhdl_version" : "VHDL 2008" + }, + "hardware" : { + "part_name" : "xc7z015clg485-2", + "board_name" : "hepia-cores.ch:scalp_node:part0:0.1" + } +}