From 5563382435136f2c12937b63b3d4dce265d5e732 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Thu, 6 May 2021 10:18:48 +0200
Subject: [PATCH] updated Scalp Router for debugging
---
.../2020.2/src/hdl/scalp_firmware.vhd | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index cfb395d..d16273d 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -893,7 +893,7 @@ begin
-- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
- type t_write_sp_states is (E_WR_SP_IDLE_0, E_WR_SP_VALID_0, E_WR_SP_WAIT_0, E_WR_SP_IDLE_1, E_WR_SP_VALID_1, E_WR_SP_WAIT_1);
+ type t_write_sp_states is (E_WR_SP_IDLE_0, E_WR_SP_VALID_0, E_WR_SP_WAIT_0, E_WR_SP_IDLE_1, E_WR_LAST_1, E_WR_SP_VALID_1, E_WR_SP_WAIT_1);
signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Scalp Packets
@@ -912,8 +912,8 @@ begin
SpPayloadxD => C_SP_PAYLOAD_0);
signal ScalpPacketValid12xS : std_ulogic := '0';
--
- signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
- signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
+ signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE_0;
+ signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE_0;
signal VioWrSpValidxS : std_ulogic := '0';
-- Scalp Packet
-- attribute mark_debug of ScalpPacket0xD : signal is "true";
@@ -1168,8 +1168,15 @@ begin
WrSPStatexDN <= E_WR_SP_IDLE_1;
when E_WR_SP_IDLE_1 =>
- ScalpPacketValid12xS <= '1';
- WrSPStatexDN <= E_WR_SP_VALID_1;
+ if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
+ WrSPStatexDN <= E_WR_LAST_1;
+ end if;
+
+ when E_WR_LAST_1 =>
+ if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then
+ ScalpPacketValid12xS <= '1';
+ WrSPStatexDN <= E_WR_SP_VALID_1;
+ end if;
when E_WR_SP_VALID_1 =>
ScalpPacketValid12xS <= '0';
--
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