From 578d41eb4c76e60c1d46f421ab1d50c55df87470 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Fri, 8 Oct 2021 10:03:45 +0200
Subject: [PATCH] Updated scalp_fast_router_firmware
---
.../2020.2/src/constrs/debug.xdc | 42 --------
.../2020.2/src/hdl/scalp_safe_firmware.vhd | 98 +++++--------------
.../2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl | 4 +-
3 files changed, 24 insertions(+), 120 deletions(-)
diff --git a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc
index b529727..e69de29 100644
--- a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc
+++ b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc
@@ -1,42 +0,0 @@
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 12 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[11]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 32 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[31]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 32 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[31]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[31]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 12 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[11]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 1 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdValidxS]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd b/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
index 1443b87..cb970c0 100644
--- a/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
+++ b/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
--- Last update: 2021-03-22
+-- Last update: 2021-10-08
--
---------------------------------------------------------------------------------
@@ -266,7 +266,6 @@ entity scalp_safe_firmware is
end scalp_safe_firmware;
-
architecture arch of scalp_safe_firmware is
-- Constantes
@@ -281,16 +280,6 @@ architecture arch of scalp_safe_firmware is
-- Processing system reset
signal PSSysResetxR : std_logic := '0';
-- Scalp Axi Lite interface and IRQ
- signal InterruptxS : std_ulogic := '0';
- signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RdValidxS : std_ulogic := '0';
- signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WrValidxS : std_ulogic := '0';
- -- Zynq Reg Bank
- signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- RGB Leds
signal Led12V5RxS : std_ulogic := '0';
signal Led12V5GxS : std_ulogic := '0';
@@ -301,9 +290,6 @@ architecture arch of scalp_safe_firmware is
-- RgbLeds Ctrl Port
signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- RGB Leds Enum
- type t_rgb_leds is (E_LED1_R, E_LED1_G, E_LED1_B, E_LED2_R, E_LED2_G, E_LED2_B);
-
-- Attributes
attribute mark_debug : string;
attribute keep : string;
@@ -350,15 +336,28 @@ begin
Spi1SclkxCO => Pll2V5ClkuWirexCO,
-- MIO
FIXED_IO_mio => MIOxDIO,
+ UserClkxCI => PSSysClkxC,
+ UserResetxRANI => PSSysResetxR,
-- Scalp Axi Lite interface and IRQ
- InterruptxSI => InterruptxS,
- RdAddrxDO => RdAddrxD,
- RdDataxDI => RdDataxD,
- RdValidxSO => RdValidxS,
- WrAddrxDO => WrAddrxD,
- WrDataxDO => WrDataxD,
- WrValidxSO => WrValidxS,
- RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD);
+ LocalNetAddrxDO => open,
+ RGBLed0xDO => RgbLedsCtrlPortxD,
+ RGBLed1xDO => open,
+ DMARXm2sxDI => C_NO_AXI4_M2S,
+ DMARXs2mxDO => open,
+ DMATXm2sxDO => open,
+ DMATXs2mxDI => C_NO_AXI4_S2M,
+ WestRXM2SxDI => C_NO_AXI4_M2S,
+ WestRXS2MxDI => C_NO_AXI4_S2M,
+ WestTXM2SxDI => C_NO_AXI4_M2S,
+ WestTXS2MxDI => C_NO_AXI4_S2M,
+ EastRXM2SxDI => C_NO_AXI4_M2S,
+ EastRXS2MxDI => C_NO_AXI4_S2M,
+ EastTXM2SxDI => C_NO_AXI4_M2S,
+ EastTXS2MxDI => C_NO_AXI4_S2M,
+ LocalRXM2SxDI => C_NO_AXI4_M2S,
+ LocalRXS2MxDI => C_NO_AXI4_S2M,
+ LocalTXM2SxDI => C_NO_AXI4_M2S,
+ LocalTXS2MxDI => C_NO_AXI4_S2M);
end block ProcessingSystemxB;
@@ -377,59 +376,6 @@ begin
end block EntityIOxB;
-
- ZynqRegBankxB : block is
- begin -- block ZynqRegBankxB
-
- RegBankxB : block is
- begin -- block RegBankxB
-
- WriteRegPortxP : process (CtrlRegPortxDP, WrAddrxD, WrDataxD,
- WrValidxS) is
- begin -- process WriteRegPortxP
- CtrlRegPortxDN <= CtrlRegPortxDP;
-
- if WrValidxS = '1' then
- case WrAddrxD is
- -- Ctrl
- -- North
- when x"000" => CtrlRegPortxDN <= WrDataxD;
- when x"004" => CtrlRegPortxDN <= CtrlRegPortxDP or WrDataxD;
- when x"008" => CtrlRegPortxDN <= CtrlRegPortxDP and not WrDataxD;
- when others => null;
- end case;
- end if;
- end process WriteRegPortxP;
-
- ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
- begin -- process ReadRegPortxP
- if PSSysResetxR = '1' then
- RdDataxD <= (others => '0');
- elsif rising_edge(PSSysClkxC) then
- RdDataxD <= (others => '0');
-
- if RdValidxS = '1' then
- case RdAddrxD is
- when x"000" => RdDataxD <= CtrlRegPortxDP;
- when others => RdDataxD <= x"aabbccdd";
- end case;
- end if;
- end if;
- end process ReadRegPortxP;
-
- RegBankxP : process (PSSysClkxC, PSSysResetxR) is
- begin -- process RegBankxP
- if PSSysResetxR = '1' then
- CtrlRegPortxDP <= (others => '0');
- elsif rising_edge(PSSysClkxC) then
- CtrlRegPortxDP <= CtrlRegPortxDN;
- end if;
- end process RegBankxP;
-
- end block RegBankxB;
-
- end block ZynqRegBankxB;
-
end block ProgrammableLogicxB;
end arch;
diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index 7185284..68a435a 100644
--- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -920,8 +920,8 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO] [g
connect_bd_net -net xlconstant_0_dout [get_bd_pins gnd_constant_1/dout] [get_bd_pins xlconcat_1/In2] [get_bd_pins xlconcat_2/In2]
# Create address segments
- assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
- assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x0C000000 -range 0x04000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x0C000000 -range 0x04000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
assign_bd_address -offset 0x40400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_fast_router_registers_0/SAxiLitexDIO/reg0] -force
--
GitLab