From 5854f55e02c4a7e6315600397e19f5b628ce2764 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Tue, 18 May 2021 11:20:22 +0200
Subject: [PATCH] Updated scalp_fifo_double_register.vhd
---
.../src/hdl/scalp_fifo_double_register.vhd | 141 +++++-------------
.../src/sim/tb_scalp_fifo_double_register.vhd | 97 ++++++------
packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd | 2 +-
3 files changed, 93 insertions(+), 147 deletions(-)
diff --git a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
index 9b03cfd..a396979 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
@@ -26,11 +26,10 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
use work.axi4_pkg.all;
-use work.scalp_misc.all;
entity scalp_fifo_double_register is
@@ -51,39 +50,36 @@ architecture behavioral of scalp_fifo_double_register is
-- Signals
-- Axis Data, Valid, Last, Keep
- signal Axism2s0xD : t_axi4m2s := C_NO_AXI4_M2S;
- signal Axism2s1xDP : t_axi4m2s := C_NO_AXI4_M2S;
- signal Axism2s1xDN : t_axi4m2s := C_NO_AXI4_M2S;
- signal Axism2s2xDP : t_axi4m2s := C_NO_AXI4_M2S;
- signal Axism2s2xDN : t_axi4m2s := C_NO_AXI4_M2S;
- signal Axism2s3xD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal Axism2s0xD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal Axism2s1xDP : t_axi4m2s := C_NO_AXI4_M2S;
+ signal Axism2s1xDN : t_axi4m2s := C_NO_AXI4_M2S;
+ signal Axism2s2xDP : t_axi4m2s := C_NO_AXI4_M2S;
+ signal Axism2s2xDN : t_axi4m2s := C_NO_AXI4_M2S;
+ signal Axism2s3xD : t_axi4m2s := C_NO_AXI4_M2S;
-- Axis Ready
- signal Axiss2m1xDN : t_axi4s2m := C_NO_AXI4_S2M;
- signal Axiss2m1xDP : t_axi4s2m := C_NO_AXI4_S2M;
- signal MUX3SelectxD : std_ulogic := '0';
+ signal Axiss2m1xDN : t_axi4s2m := C_NO_AXI4_S2M;
+ signal Axiss2m1xDP : t_axi4s2m := C_NO_AXI4_S2M;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- attribute mark_debug of Axism2s0xD : signal is "true";
- attribute keep of Axism2s0xD : signal is "true";
- attribute mark_debug of Axism2s1xDP : signal is "true";
- attribute keep of Axism2s1xDP : signal is "true";
- attribute mark_debug of Axism2s1xDN : signal is "true";
- attribute keep of Axism2s1xDN : signal is "true";
- attribute mark_debug of Axism2s2xDP : signal is "true";
- attribute keep of Axism2s2xDP : signal is "true";
- attribute mark_debug of Axism2s2xDN : signal is "true";
- attribute keep of Axism2s2xDN : signal is "true";
- attribute mark_debug of Axism2s3xD : signal is "true";
- attribute keep of Axism2s3xD : signal is "true";
- attribute mark_debug of Axiss2m1xDN : signal is "true";
- attribute keep of Axiss2m1xDN : signal is "true";
- attribute mark_debug of Axiss2m1xDP : signal is "true";
- attribute keep of Axiss2m1xDP : signal is "true";
- attribute mark_debug of MUX3SelectxD : signal is "true";
- attribute keep of MUX3SelectxD : signal is "true";
+ attribute mark_debug of Axism2s0xD : signal is "true";
+ attribute keep of Axism2s0xD : signal is "true";
+ attribute mark_debug of Axism2s1xDP : signal is "true";
+ attribute keep of Axism2s1xDP : signal is "true";
+ attribute mark_debug of Axism2s1xDN : signal is "true";
+ attribute keep of Axism2s1xDN : signal is "true";
+ attribute mark_debug of Axism2s2xDP : signal is "true";
+ attribute keep of Axism2s2xDP : signal is "true";
+ attribute mark_debug of Axism2s2xDN : signal is "true";
+ attribute keep of Axism2s2xDN : signal is "true";
+ attribute mark_debug of Axism2s3xD : signal is "true";
+ attribute keep of Axism2s3xD : signal is "true";
+ attribute mark_debug of Axiss2m1xDN : signal is "true";
+ attribute keep of Axiss2m1xDN : signal is "true";
+ attribute mark_debug of Axiss2m1xDP : signal is "true";
+ attribute keep of Axiss2m1xDP : signal is "true";
begin -- architecture behavioral
@@ -96,10 +92,18 @@ begin -- architecture behavioral
-- S2M
Axiss2mLinkInxAS : Axiss2m1xDN <= Axiss2mLinkxDI;
Axiss2mLinkOutxAS : Axiss2mLinkxDO <= Axiss2m1xDP;
- MUX3SelectxAS : MUX3SelectxD <= not Axiss2mLinkxDI.ReadyxS;
end block EntityIOxB;
+ MUXxB : block is
+ begin -- block MUXxB
+
+ MUX1xAS : Axism2s1xDN <= Axism2s0xD when Axiss2m1xDP.ReadyxS = '1' else Axism2s1xDP;
+ MUX2xAS : Axism2s2xDN <= Axism2s0xD when Axiss2m1xDN.ReadyxS = '1' else Axism2s2xDP;
+ MUX3xAS : Axism2s3xD <= Axism2s1xDP when Axiss2m1xDP.ReadyxS = '1' else Axism2s2xDP;
+
+ end block MUXxB;
+
RegistersxP : process (SysClkxCI, SysRstxRNAI) is
begin -- process RegistersxP
if SysRstxRNAI = '0' then
@@ -117,75 +121,4 @@ begin -- architecture behavioral
end if;
end process RegistersxP;
- MUXxB : block is
- begin -- block MUXxB
-
- MUX1xAS : Axism2s1xDN <= Axism2s0xD when Axiss2m1xDP.ReadyxS = '1' else Axism2s1xDP;
- MUX2xAS : Axism2s2xDN <= Axism2s0xD when Axiss2m1xDN.ReadyxS = '1' else Axism2s2xDP;
- MUX3xAS : Axism2s3xD <= Axism2s1xDP when MUX3SelectxD = '1'else Axism2s2xDP;
-
- end block MUXxB;
-
- -- EntityIOxB : block is
- -- begin -- block EntityIOxB
- -- -- Axis m2s
- -- Axism2s0FromxAS : Axism2s0xD <= Axism2sLinkxDI;
- -- Axism2s3ToxAS : Axism2sLinkxDO <= Axism2s3xD;
- -- -- Axis s2m
- -- Axiss2m0FromxAS : Axiss2m0xD <= Axiss2mLinkxDI;
- -- Axiss2m1FromxAS : Axiss2m1xDN <= Axiss2m0xD;
- -- Axiss2m1ToxAS : Axiss2mLinkxDO <= Axiss2m1xDP;
- -- end block EntityIOxB;
-
- -- AsyncStatementsxB : block is
- -- begin -- block AsyncStatementsxB
- -- Axism2s3FromxAS : Axism2s3xD <= Axism2s1xDP when
- -- (Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1') or
- -- (Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '1') else
- -- Axism2s2xDP;
- -- end block AsyncStatementsxB;
-
- -- UpdateRegxP : process (SysClkxCI, SysRstxRNAI) is
- -- begin -- process UpdateRegxP
- -- if SysRstxRNAI = '0' then
- -- -- Axis m2s
- -- Axism2s1xDP <= C_NO_AXI4_M2S;
- -- Axism2s2xDP <= C_NO_AXI4_M2S;
- -- -- Axis s2m
- -- Axiss2m1xDP <= C_NO_AXI4_S2M;
- -- -- Enable Port
- -- -- ScalpFifoEnablexSP <= '0';
- -- elsif rising_edge(SysClkxCI) then
- -- -- Axis m2s
- -- Axism2s1xDP <= Axism2s1xDN;
- -- Axism2s2xDP <= Axism2s2xDN;
- -- -- Axis s2m
- -- Axiss2m1xDP <= Axiss2m1xDN;
- -- -- Enable Port
- -- -- ScalpFifoEnablexSP <= ScalpFifoEnablexSN;
- -- end if;
- -- end process UpdateRegxP;
-
- -- TransistionOnReadyxP : process (Axism2s0xD, Axism2s1xDP, Axism2s2xDP,
- -- Axiss2m0xD.ReadyxS, Axiss2m1xDP.ReadyxS) is
- -- begin -- process TransistionOnReadyxP
- -- -- Defaults values
- -- Axism2s1xDN <= Axism2s1xDP;
- -- Axism2s2xDN <= Axism2s2xDP;
-
- -- if Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '0' then
- -- Axism2s1xDN <= Axism2s1xDP;
- -- Axism2s2xDN <= Axism2s2xDP;
- -- elsif Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1' then
- -- Axism2s1xDN <= Axism2s0xD;
- -- Axism2s2xDN <= Axism2s2xDP;
- -- elsif Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '0' then
- -- Axism2s1xDN <= Axism2s1xDP;
- -- Axism2s2xDN <= Axism2s0xD;
- -- else
- -- Axism2s1xDN <= Axism2s0xD;
- -- Axism2s2xDN <= Axism2s0xD;
- -- end if;
- -- end process TransistionOnReadyxP;
-
end architecture behavioral;
diff --git a/ips/hw/scalp_router/src/sim/tb_scalp_fifo_double_register.vhd b/ips/hw/scalp_router/src/sim/tb_scalp_fifo_double_register.vhd
index 695a145..ae0fd80 100644
--- a/ips/hw/scalp_router/src/sim/tb_scalp_fifo_double_register.vhd
+++ b/ips/hw/scalp_router/src/sim/tb_scalp_fifo_double_register.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Testbench for scalp_fifo_double_register.
--
--- Last update: 2020-02-21
+-- Last update: 2021-05-18
--
---------------------------------------------------------------------------------
library ieee;
@@ -33,9 +33,10 @@ use ieee.math_real.all;
--use UNISIM.VCOMPONENTS.all;
library work;
-use work.aurora_axi4_pkg.all;
-use work.scalp_misc.all;
-use work.scalp_utility.all;
+-- use work.aurora_axi4_pkg.all;
+use work.axi4_pkg.all;
+-- use work.scalp_misc.all;
+-- use work.scalp_utility.all;
entity tb_scalp_fifo_double_register is
@@ -47,13 +48,10 @@ architecture testbench of tb_scalp_fifo_double_register is
component scalp_fifo_double_register is
port (
- -- System Clock and Reset
SysClkxCI : in std_ulogic;
SysRstxRNAI : in std_ulogic;
- -- Axis Ports (Slave Side)
Axism2sLinkxDI : in t_axi4m2s;
Axiss2mLinkxDO : out t_axi4s2m;
- -- Axis Ports (Master Side)
Axism2sLinkxDO : out t_axi4m2s;
Axiss2mLinkxDI : in t_axi4s2m);
end component scalp_fifo_double_register;
@@ -76,7 +74,7 @@ begin -- architecture testbench
AsyncStatementsxB : block is
begin -- block AsyncStatementsxB
SysClkxAS : SysClkxC <= not SysClkxC after (C_CLK_PERIOD / 2);
- SysRstxAS : SysRstxRNA <= '1' after (C_CLK_PERIOD * 10);
+ SysRstxAS : SysRstxRNA <= '1' after (C_CLK_PERIOD * 5);
DataxAS : Axism2sLinkInxD.DataxD <= std_ulogic_vector(to_unsigned(CounterxDP, 32));
end block AsyncStatementsxB;
@@ -91,13 +89,10 @@ begin -- architecture testbench
ScalpFifoDoubleRegisterxI : entity work.scalp_fifo_double_register
port map (
- -- System Clock and Reset
SysClkxCI => SysClkxC,
SysRstxRNAI => SysRstxRNA,
- -- Axis Ports (Slave Side)
Axism2sLinkxDI => Axism2sLinkInxD,
Axiss2mLinkxDO => Axiss2mLinkOutxD,
- -- Axis Ports (Master Side)
Axism2sLinkxDO => Axism2sLinkOutxD,
Axiss2mLinkxDI => Axiss2mLinkInxD);
@@ -128,29 +123,29 @@ begin -- architecture testbench
wait until (SysRstxRNA = '1');
Axism2sLinkInxD.ValidxS <= '1';
- for i in 0 to 30 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ for i in 0 to 60 loop
+ wait until rising_edge(SysClkxC);
+ end loop; -- i
- Axism2sLinkInxD.ValidxS <= '0';
+ Axism2sLinkInxD.ValidxS <= '0';
- for i in 0 to 6 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ for i in 0 to 6 loop
+ wait until rising_edge(SysClkxC);
+ end loop; -- i
- Axism2sLinkInxD.ValidxS <= '1';
+ Axism2sLinkInxD.ValidxS <= '1';
- for i in 0 to 14 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ -- for i in 0 to 14 loop
+ -- wait until rising_edge(SysClkxC);
+ -- end loop; -- i
- Axism2sLinkInxD.ValidxS <= '0';
+ -- Axism2sLinkInxD.ValidxS <= '0';
- for i in 0 to 10 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ -- for i in 0 to 10 loop
+ -- wait until rising_edge(SysClkxC);
+ -- end loop; -- i
- Axism2sLinkInxD.ValidxS <= '1';
+ -- Axism2sLinkInxD.ValidxS <= '1';
wait;
end process ValidxP;
@@ -160,8 +155,8 @@ begin -- architecture testbench
Axiss2mLinkInxD.ReadyxS <= '0';
wait until (SysRstxRNA = '1');
Axiss2mLinkInxD.ReadyxS <= '1';
- wait until rising_edge(SysClkxC);
- wait until rising_edge(SysClkxC);
+ -- wait until rising_edge(SysClkxC);
+ -- wait until rising_edge(SysClkxC);
for i in 0 to 10 loop
wait until rising_edge(SysClkxC);
@@ -175,29 +170,47 @@ begin -- architecture testbench
Axiss2mLinkInxD.ReadyxS <= '1';
- for i in 0 to 40 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ wait until rising_edge(SysClkxC);
Axiss2mLinkInxD.ReadyxS <= '0';
- for i in 0 to 5 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ wait until rising_edge(SysClkxC);
- for i in 0 to 20 loop
+ Axiss2mLinkInxD.ReadyxS <= '1';
+
+ for i in 0 to 10 loop
wait until rising_edge(SysClkxC);
end loop; -- i
+ Axiss2mLinkInxD.ReadyxS <= '0';
+
+ wait until rising_edge(SysClkxC);
+
Axiss2mLinkInxD.ReadyxS <= '1';
- for i in 0 to 5 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ -- for i in 0 to 40 loop
+ -- wait until rising_edge(SysClkxC);
+ -- end loop; -- i
- for i in 0 to 10 loop
- wait until rising_edge(SysClkxC);
- end loop; -- i
+ -- Axiss2mLinkInxD.ReadyxS <= '0';
+
+ -- for i in 0 to 5 loop
+ -- wait until rising_edge(SysClkxC);
+ -- end loop; -- i
+
+ -- for i in 0 to 20 loop
+ -- wait until rising_edge(SysClkxC);
+ -- end loop; -- i
+
+ -- Axiss2mLinkInxD.ReadyxS <= '1';
+
+ -- for i in 0 to 5 loop
+ -- wait until rising_edge(SysClkxC);
+ -- end loop; -- i
+
+ -- for i in 0 to 10 loop
+ -- wait until rising_edge(SysClkxC);
+ -- end loop; -- i
wait;
end process ReadyxP;
diff --git a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
index 792aad9..d82274a 100644
--- a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
+++ b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: AXI4 format bus signals.
--
--- Last update: 2020-11-25
+-- Last update: 2021-05-18
--
---------------------------------------------------------------------------------
--
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