diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index dd1dfe39cb58c383230e78819109eb14e3bd306c..bc51fd4fedf22debe98c02f21d425fb73e206985 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -872,7 +872,7 @@ begin
-- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID_0, E_WR_SP_LAST, E_WR_SP_VALID_1, E_WR_SP_WAIT);
+ type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID_0, E_WR_SP_LAST_0, E_WR_SP_LAST_1, E_WR_SP_VALID_1, E_WR_SP_WAIT);
signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Scalp Packets
@@ -1149,10 +1149,15 @@ begin
when E_WR_SP_VALID_0 =>
ScalpPacketValid12xS <= '0';
- WrSPStatexDN <= E_WR_SP_LAST;
+ WrSPStatexDN <= E_WR_SP_LAST_0;
- when E_WR_SP_LAST =>
+ when E_WR_SP_LAST_0 =>
if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
+ WrSPStatexDN <= E_WR_SP_LAST_1;
+ end if;
+
+ when E_WR_SP_LAST_1 =>
+ if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then
ScalpPacketValid12xS <= '1';
WrSPStatexDN <= E_WR_SP_VALID_1;
end if;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd b/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
index 976e7b64aebea6f66d3883299efbbe091e00e7c4..65930a5d6ff9564473fded5dc6752f4f96e11014 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: AXI Stream to Scalp Packet converter.
--
--- Last update: 2021-05-10
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -27,8 +27,8 @@ use ieee.math_real.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
library work;
use work.axi4_pkg.all;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_booking_vector.vhd b/ips/hw/scalp_router/src/hdl/scalp_booking_vector.vhd
index c93f76bc8cd50aa7951b63413498c77458b1891a..a72f29473dd42615708d3be2a5ab163bd9cff846 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_booking_vector.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_booking_vector.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Manage the booking vector.
--
--- Last update: 2020-02-13
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
use work.scalp_misc.all;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
index 86b97ed0f5f0e020109d5741636fb3428bc3bc82..a384a4a5063fc6884f9e7dda877ffddb02891eb9 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Small fifo built with two registers.
--
--- Last update: 2021-05-18
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -64,22 +64,6 @@ architecture behavioral of scalp_fifo_double_register is
attribute mark_debug : string;
attribute keep : string;
--
- -- attribute mark_debug of Axism2s0xD : signal is "true";
- -- attribute keep of Axism2s0xD : signal is "true";
- -- attribute mark_debug of Axism2s1xDP : signal is "true";
- -- attribute keep of Axism2s1xDP : signal is "true";
- -- attribute mark_debug of Axism2s1xDN : signal is "true";
- -- attribute keep of Axism2s1xDN : signal is "true";
- -- attribute mark_debug of Axism2s2xDP : signal is "true";
- -- attribute keep of Axism2s2xDP : signal is "true";
- -- attribute mark_debug of Axism2s2xDN : signal is "true";
- -- attribute keep of Axism2s2xDN : signal is "true";
- -- attribute mark_debug of Axism2s3xD : signal is "true";
- -- attribute keep of Axism2s3xD : signal is "true";
- -- attribute mark_debug of Axiss2m1xDN : signal is "true";
- -- attribute keep of Axiss2m1xDN : signal is "true";
- -- attribute mark_debug of Axiss2m1xDP : signal is "true";
- -- attribute keep of Axiss2m1xDP : signal is "true";
begin -- architecture behavioral
diff --git a/ips/hw/scalp_router/src/hdl/scalp_matrix_index.vhd b/ips/hw/scalp_router/src/hdl/scalp_matrix_index.vhd
index 262889e3a9ed1ee8057a1769d3c27ed6374cba41..ced3c01e876369395e9adaab47f6c87b6abea757 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_matrix_index.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_matrix_index.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Determines the index of the output vector.
--
--- Last update: 2020-01-19
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
entity scalp_matrix_index is
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router.vhd b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
index 76ff8f2fb0f6e2e727b0132350392e143a2fb412..c34d1920117c21aaa7792c5c8b010b5f1d578e80 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router (NoC).
--
--- Last update: 2021-05-04
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -27,8 +27,8 @@ use ieee.math_real.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
library work;
use work.axi4_pkg.all;
@@ -117,19 +117,19 @@ architecture rtl of scalp_router is
-- Signals
-- Scalp Router
-- Local Router Network Address
- signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
-- Axi4 Stream Interfaces
- signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
- signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
-- Scalp QoS Vectors
- signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
-- Axi4 Stream Cross-Links with Neighborhood
- signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
- signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
---------------------------------------------------------------------------
-- For Simulation With Vivado Only
-- Axi4 Stream Cross-Links with Neighborhood
@@ -139,37 +139,15 @@ architecture rtl of scalp_router is
-- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_SIM_AXISS2M_VECTOR);
---------------------------------------------------------------------------
-- Scalp Booking Vectors
- signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
-- Scalp Scheduler Ack Vectors
- signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
- -- attribute keep of TXAxiss2mVectorxD : signal is "true";
- -- attribute mark_debug of LocNetAddrxD : signal is "true";
- -- attribute keep of LocNetAddrxD : signal is "true";
- -- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
- -- attribute keep of RXAxism2sVectorxD : signal is "true";
- -- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
- -- attribute keep of RXAxiss2mVectorxD : signal is "true";
- -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
- -- attribute keep of TXAxism2sVectorxD : signal is "true";
- -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
- -- attribute keep of TXAxiss2mVectorxD : signal is "true";
- -- attribute mark_debug of QoSVectorxD : signal is "true";
- -- attribute keep of QoSVectorxD : signal is "true";
- -- attribute mark_debug of BookingVectorsInxD : signal is "true";
- -- attribute keep of BookingVectorsInxD : signal is "true";
- -- attribute mark_debug of BookingVectorsOutxD : signal is "true";
- -- attribute keep of BookingVectorsOutxD : signal is "true";
- -- attribute mark_debug of SchedulerAckVectorsInxD : signal is "true";
- -- attribute keep of SchedulerAckVectorsInxD : signal is "true";
- -- attribute mark_debug of SchedulerAckVectorsOutxD : signal is "true";
- -- attribute keep of SchedulerAckVectorsOutxD : signal is "true";
begin -- architecture rtl
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
index 64c9576ae3ded63b050a88f6158908c94fbbf9b1..ddec2daf540b26e5afdbdb57bd3996391181b41e 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Core Algorithm
--
--- Last update: 2020-01-21
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
use work.scalp_misc.all;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
index 40da0be4ede265a016972156ff74999b3e907a8c..08a4f60efb0418d4f3ad5ba74f8f752f95d1d67e 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Interface.
--
--- Last update: 2021-05-18
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -27,8 +27,8 @@ use ieee.math_real.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
use work.axi4_pkg.all;
use work.scalp_misc.all;
@@ -93,8 +93,6 @@ architecture rtl of scalp_router_interface is
SysRstxRNAI : in std_ulogic;
DstRouterNetAddrxDO : out t_scalp_netaddr;
RouterNetAddrValidxSO : out std_ulogic;
- -- BookingVectorValidxSI : in std_ulogic;
- -- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
RXAxi4M2SLinkxDI : in t_axi4m2s;
RXAxi4S2MLinkxDO : out t_axi4s2m;
TXAxi4M2SLinkxDO : out t_axi4m2s;
@@ -217,21 +215,9 @@ architecture rtl of scalp_router_interface is
signal DTXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- -- attribute mark_debug of RXAxi4m2sIfxD : signal is "true";
- -- attribute keep of RXAxi4m2sIfxD : signal is "true";
- -- attribute mark_debug of RXAxi4s2mIfxD : signal is "true";
- -- attribute keep of RXAxi4s2mIfxD : signal is "true";
- -- attribute mark_debug of TXAxi4M2SLinkxD : signal is "true";
- -- attribute keep of TXAxi4M2SLinkxD : signal is "true";
- -- attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
- -- attribute keep of TXAxi4S2MLinkxD : signal is "true";
- -- attribute mark_debug of TXAxi4m2sLinksxD : signal is "true";
- -- attribute keep of TXAxi4m2sLinksxD : signal is "true";
- -- attribute mark_debug of TXAxi4s2mLinksxD : signal is "true";
- -- attribute keep of TXAxi4s2mLinksxD : signal is "true";
begin -- architecture rtl
@@ -261,8 +247,6 @@ begin -- architecture rtl
SysRstxRNAI => SysRstxRNAI,
DstRouterNetAddrxDO => DstRouterNetAddrxD,
RouterNetAddrValidxSO => RouterNetAddrValidxS,
- -- BookingVectorValidxSI => BookingVectorValidxS,
- -- SchedulerAckxDI => SchedulerAckxD,
RXAxi4M2SLinkxDI => RXAxi4m2sIfxD,
RXAxi4S2MLinkxDO => RXAxi4s2mIfxD,
TXAxi4M2SLinkxDO => TXAxi4M2SLinkxD,
diff --git a/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
index 706c9520a94ec41db5b9dc66756fe464c94bf529..4fe94ef776d6ece2e1c246d09f1f4c1b32966a31 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp RX side state machine.
--
--- Last update: 2021-05-11
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -27,8 +27,8 @@ use ieee.math_real.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
use work.axi4_pkg.all;
use work.scalp_misc.all;
@@ -93,8 +93,6 @@ architecture behavioral of scalp_rx_side is
-- Enity IO Signals
signal SchedulerAckxD : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => '0');
- -- signal BookingVectorxDP : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => '0');
- -- signal BookingVectorxDN : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal TXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
signal TXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
signal RXAxi4M2SLinkxD : t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => C_NO_AXI4_M2S);
@@ -104,7 +102,6 @@ architecture behavioral of scalp_rx_side is
signal RequestVectorxDP : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal RequestVectorxDN : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal ArbitratedxS : std_ulogic := '0';
- -- signal GrantVectorxD : std_ulogic_vector((C_SCALP_PORTS - 1) downto 0) := (others => '0');
signal GrantIndexxD : std_ulogic_vector((scalp_log2ceilnz(C_SCALP_NEIGHBORS_VECTOR_SIZE) - 1) downto 0) := (others => '0');
-- Rx Side States
signal RXSideStatexDP : t_scalp_rx_side_states := E_SCALP_RX_IDLE;
@@ -116,45 +113,9 @@ architecture behavioral of scalp_rx_side is
signal EnPopNPushxS : std_ulogic := '0';
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- -- attribute mark_debug of TXAxi4M2SLinkxD : signal is "true";
- -- attribute keep of TXAxi4M2SLinkxD : signal is "true";
- -- attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
- -- attribute keep of TXAxi4S2MLinkxD : signal is "true";
- -- attribute mark_debug of RXAxi4M2SLinkxD : signal is "true";
- -- attribute keep of RXAxi4M2SLinkxD : signal is "true";
- -- attribute mark_debug of RXAxi4S2MLinkxD : signal is "true";
- -- attribute keep of RXAxi4S2MLinkxD : signal is "true";
- -- attribute mark_debug of BookingVectorxDP : signal is "true";
- -- attribute keep of BookingVectorxDP : signal is "true";
- -- attribute mark_debug of BookingVectorxDN : signal is "true";
- -- attribute keep of BookingVectorxDN : signal is "true";
- -- attribute mark_debug of SchedulerAckxD : signal is "true";
- -- attribute keep of SchedulerAckxD : signal is "true";
- -- attribute mark_debug of RequestVectorxDP : signal is "true";
- -- attribute keep of RequestVectorxDP : signal is "true";
- -- attribute mark_debug of RequestVectorxDN : signal is "true";
- -- attribute keep of RequestVectorxDN : signal is "true";
- -- attribute mark_debug of ArbitratexS : signal is "true";
- -- attribute keep of ArbitratexS : signal is "true";
- -- attribute mark_debug of ArbitratedxS : signal is "true";
- -- attribute keep of ArbitratedxS : signal is "true";
- -- attribute mark_debug of GrantIndexxD : signal is "true";
- -- attribute keep of GrantIndexxD : signal is "true";
- -- attribute mark_debug of RXSideStatexDP : signal is "true";
- -- attribute keep of RXSideStatexDP : signal is "true";
- -- attribute mark_debug of RXSideStatexDN : signal is "true";
- -- attribute keep of RXSideStatexDN : signal is "true";
- -- attribute mark_debug of ReadyInxD : signal is "true";
- -- attribute keep of ReadyInxD : signal is "true";
- -- attribute mark_debug of ReadyOutxD : signal is "true";
- -- attribute keep of ReadyOutxD : signal is "true";
- -- attribute mark_debug of EnPopNPushxS : signal is "true";
- -- attribute keep of EnPopNPushxS : signal is "true";
- -- attribute mark_debug of Axism2sInxD : signal is "true";
- -- attribute keep of Axism2sInxD : signal is "true";
begin -- architecture behavioral
@@ -214,7 +175,7 @@ begin -- architecture behavioral
RXSideStatexDP <= RXSideStatexDN;
RequestVectorxDP <= RequestVectorxDN;
end if;
- end process UpdateRegxP;
+ end process UpdateRegxP;
RxSideStateMachinexP : process (ArbitratedxS, BookingVectorxDI,
GrantIndexxD, RXAxi4M2SLinkxD,
@@ -253,17 +214,12 @@ begin -- architecture behavioral
EnPopNPushxS <= '1';
if TXAxi4M2SLinkxD.LastxS = '1' then
- -- RXAxi4S2MLinkxD <= (others => C_NO_AXI4_S2M); --
- RXSideStatexDN <= E_SCALP_RX_ACK;
+ RXSideStatexDN <= E_SCALP_RX_ACK;
end if;
when E_SCALP_RX_ACK =>
SchedulerAckxD(to_integer(unsigned(GrantIndexxD))) <= '1';
- -- if to_integer(unsigned(BookingVectorxDI)) /= 0 then
- -- RXSideStatexDN <= E_SCALP_RX_ARBITRATE;
- -- else
RXSideStatexDN <= E_SCALP_RX_IDLE;
- -- end if;
when others => null;
end case;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_scheduler.vhd b/ips/hw/scalp_router/src/hdl/scalp_scheduler.vhd
index 1d9d5ff09ac1b909f6aae9975b160db63a627e02..d7b23815b4ae35499a8c96d3edbe96bbfa831470 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_scheduler.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_scheduler.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Generic Round Robin or Random Scheduler.
--
--- Last update: 2020-01-17
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,12 +26,11 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
library work;
use work.scalp_misc.all;
--- use work.scalp_utility.all;
entity scalp_scheduler is
diff --git a/ips/hw/scalp_router/src/hdl/scalp_scheduler_ack.vhd b/ips/hw/scalp_router/src/hdl/scalp_scheduler_ack.vhd
index c74b8726a38181d9b02268abb47032c5eda5e0b2..2199368ccf3db07f4d0c05aa2a09365cd59f7847 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_scheduler_ack.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_scheduler_ack.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Scheduler Acknowledge.
--
--- Last update: 2019-11-22
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
-- use work.utility.all;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd b/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd
index 4f0d7b3002ce11d4e74501f56a84f8af9ad10eff..1c1083babc417875ca67aabcefeebbfd44b0d71e 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Packet to AXI Stream converter.
--
--- Last update: 2021-01-11
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
library work;
use work.axi4_pkg.all;
@@ -113,29 +113,9 @@ architecture behavioral of scalp_sp_to_axis is
signal ScalpRdyxS : std_ulogic := '0';
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- -- attribute mark_debug of ScalpAxism2sxD : signal is "true";
- -- attribute keep of ScalpAxism2sxD : signal is "true";
- -- attribute mark_debug of ScalpAxiss2mxD : signal is "true";
- -- attribute keep of ScalpAxiss2mxD : signal is "true";
- -- attribute mark_debug of ScalpPacketStatexDP : signal is "true";
- -- attribute keep of ScalpPacketStatexDP : signal is "true";
- -- attribute mark_debug of ScalpPacketStatexDN : signal is "true";
- -- attribute keep of ScalpPacketStatexDN : signal is "true";
- -- attribute mark_debug of ScalpPacketCntxDP : signal is "true";
- -- attribute keep of ScalpPacketCntxDP : signal is "true";
- -- attribute mark_debug of ScalpPacketValidxS : signal is "true";
- -- attribute keep of ScalpPacketValidxS : signal is "true";
- -- attribute mark_debug of ScalpPacketxD : signal is "true";
- -- attribute keep of ScalpPacketxD : signal is "true";
- -- attribute mark_debug of DataxDP : signal is "true";
- -- attribute keep of DataxDP : signal is "true";
- -- attribute mark_debug of DataxDN : signal is "true";
- -- attribute keep of DataxDN : signal is "true";
- -- attribute mark_debug of ScalpRdyxS : signal is "true";
- -- attribute keep of ScalpRdyxS : signal is "true";
begin -- architecture behavioral
diff --git a/ips/hw/scalp_router/src/hdl/scalp_tx_fanout.vhd b/ips/hw/scalp_router/src/hdl/scalp_tx_fanout.vhd
index 32875001c975282af9a5dfac33ff1f4724d54a9d..4c4c1c8e36bfa928eb157dded570dbf897dfd8d2 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_tx_fanout.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_tx_fanout.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Spread of the AXI4 Stream bus.
--
--- Last update: 2020-11-30
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
-- use work.utility.all;
use work.axi4_pkg.all;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
index ed739ec929a803a33dda31fb137e1c7bb77b5a9e..1a0d99ae2e7a215ef795bf8a40a748d1db5eb5ad 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp TX side state machine.
--
--- Last update: 2021-05-18
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
---library UNISIM;
---use UNISIM.VCOMPONENTS.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
use work.axi4_pkg.all;
use work.scalp_misc.all;
@@ -44,10 +44,6 @@ entity scalp_tx_side is
-- Routeur Network Address
DstRouterNetAddrxDO : out t_scalp_netaddr;
RouterNetAddrValidxSO : out std_ulogic;
- -- Indicates when the booking vector is valid.
- -- BookingVectorValidxSI : in std_ulogic;
- -- Scheduler Acknowledgement Vector
- -- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
-- Axi4 Stream
-- Input side
RXAxi4M2SLinkxDI : in t_axi4m2s;
@@ -73,51 +69,24 @@ architecture behavioral of scalp_tx_side is
Axiss2mLinkxDI : in t_axi4s2m);
end component scalp_fifo_double_register;
- signal DstRouterNetAddrxDP : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
- signal DstRouterNetAddrxDN : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
- signal RouterNetAddrValidxSP : std_ulogic := '0';
- signal RouterNetAddrValidxSN : std_ulogic := '0';
- -- signal SchedulerAckxD : std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0) := (others => '0');
- signal RXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal RXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal TXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal TXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal DstRouterNetAddrxDP : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal DstRouterNetAddrxDN : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal RouterNetAddrValidxSP : std_ulogic := '0';
+ signal RouterNetAddrValidxSN : std_ulogic := '0';
+ signal RXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal RXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal TXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal TXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
-- TX Side States
- signal TXSideStatexDP : t_scalp_tx_side_states := E_SCALP_TX_IDLE;
- signal TXSideStatexDN : t_scalp_tx_side_states := E_SCALP_TX_IDLE;
+ signal TXSideStatexDP : t_scalp_tx_side_states := E_SCALP_TX_IDLE;
+ signal TXSideStatexDN : t_scalp_tx_side_states := E_SCALP_TX_IDLE;
-- Others
- signal ReadyInxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EnPopxS : std_ulogic := '0';
+ signal ReadyInxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EnPopxS : std_ulogic := '0';
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- attribute mark_debug of TXAxi4M2SLinkxD : signal is "true";
- attribute keep of TXAxi4M2SLinkxD : signal is "true";
- attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
- attribute keep of TXAxi4S2MLinkxD : signal is "true";
- attribute mark_debug of ReadyInxD : signal is "true";
- attribute keep of ReadyInxD : signal is "true";
- attribute mark_debug of TXSideStatexDN : signal is "true";
- attribute keep of TXSideStatexDN : signal is "true";
- attribute mark_debug of TXSideStatexDP : signal is "true";
- attribute keep of TXSideStatexDP : signal is "true";
- attribute mark_debug of RXAxi4M2SLinkxD : signal is "true";
- attribute keep of RXAxi4M2SLinkxD : signal is "true";
- attribute mark_debug of RXAxi4S2MLinkxD : signal is "true";
- attribute keep of RXAxi4S2MLinkxD : signal is "true";
- attribute mark_debug of DstRouterNetAddrxDN : signal is "true";
- attribute keep of DstRouterNetAddrxDN : signal is "true";
- attribute mark_debug of DstRouterNetAddrxDP : signal is "true";
- attribute keep of DstRouterNetAddrxDP : signal is "true";
- attribute mark_debug of RouterNetAddrValidxSN : signal is "true";
- attribute keep of RouterNetAddrValidxSN : signal is "true";
- attribute mark_debug of RouterNetAddrValidxSP : signal is "true";
- attribute keep of RouterNetAddrValidxSP : signal is "true";
- attribute mark_debug of EnPopxS : signal is "true";
- attribute keep of EnPopxS : signal is "true";
- -- attribute mark_debug of SchedulerAckxD : signal is "true";
- -- attribute keep of SchedulerAckxD : signal is "true";
begin -- architecture behavioral
@@ -127,14 +96,11 @@ begin -- architecture behavioral
begin -- block EntityIOxB
DstRouterNetAddrxAS : DstRouterNetAddrxDO <= DstRouterNetAddrxDP;
RouterNetAddrValidxAS : RouterNetAddrValidxSO <= RouterNetAddrValidxSP;
- -- SchedulerAckxAS : SchedulerAckxD <= SchedulerAckxDI;
-- Ext. Side
RXAxi4M2SLinkxAS : RXAxi4M2SLinkxD <= RXAxi4M2SLinkxDI;
RXAxi4S2MLinkxAS : RXAxi4S2MLinkxDO <= RXAxi4S2MLinkxD;
TXAxi4M2SLinkxAS : TXAxi4M2SLinkxDO <= TXAxi4M2SLinkxD;
TXAxi4S2MLinkxAS : TXAxi4S2MLinkxD <= TXAxi4S2MLinkxDI;
-
- -- BookingVectorValidxAS : BookingVectorValidxS <= BookingVectorValidxSI;
end block EntityIOxB;
AsyncStatementsxB : block is