diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.gitignore b/designs/vivado/scalp_mipi/2020.2/lin64/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..d7bb4bd7a0a0d18a8834b18f380144ad53f108ec
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.gitignore
@@ -0,0 +1,24 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_mipi
+scalp_mipi_zynqps
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1841a25d606922b89f8292c6a44a0f9b380fbbbe
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/clean_prj_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/clean_prj_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4dbcb8ed33f1be2d7859e4e604f28b9541cd2af7
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/clean_prj_scalp_mipi.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_mipi/ 2> /dev/null
+
+echo "> Done"
+
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/create_prj_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/create_prj_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..6f5c5fab4eb5c40d1f328e4aabcc133327cde1c1
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/create_prj_scalp_mipi.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_mipi.tcl -notrace
+echo "> Done"
+
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/create_prj_scalp_mipi.tcl b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/create_prj_scalp_mipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f27e51dc7b66ab73b648b886ba39038062546fc1
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/create_prj_scalp_mipi.tcl
@@ -0,0 +1,177 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_mipi'
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_mipi"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "DESIGN_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set hdl_src_dir "${src_dir}/hdl"
+ set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ set hdl_src_dir "${comp_src_dir}/hdl"
+ set sim_src_dir "${comp_src_dir}/sim"
+}
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+ add_files -norecurse $hdl_src_file_list
+} else {
+ print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
+ set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_mipi.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/scalp_mipi.xdc]
+
+ # add IPs source files
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # add IPs source files
+
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+ add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+ update_compile_order -fileset sim_1
+ print_status "Add simulation sources" "OK"
+} else {
+ print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
+
+# Add packages sources
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ set_property library xil_defaultlib [get_files $j]
+ }
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
+
+# Add SoC wrapper sources files
+ set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_mipi_zynqps/src/hdl *.vhd]
+ add_files -norecurse $vhdl_soc_file_list
+ foreach j $vhdl_soc_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+print_status "Add SoC wrapper sources" "OK"
+print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/export_hw_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/export_hw_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..3596dc3a6b5b49f23a8c66ec43c8084149185e1b
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/export_hw_scalp_mipi.sh
@@ -0,0 +1,29 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to SDK
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Export the hardware design to Vitis SDK"
+
+vivado -nojournal -nolog -mode tcl -source ./export_hw_scalp_mipi.tcl -notrace
+
+echo "> Done"
+
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/export_hw_scalp_mipi.tcl b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/export_hw_scalp_mipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cc1c9e065dea32688172f0e5375efddc8faa940e
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/export_hw_scalp_mipi.tcl
@@ -0,0 +1,43 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to Vitis SDK
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+source utils.tcl
+
+# Project paths
+set PRJ_DIR ".."
+set SRC_DIR "${PRJ_DIR}/../src"
+set EXPORT_DIR "${SRC_DIR}/sw/hw_export"
+
+# Initialize workspace directories name
+set prj_name "scalp_mipi"
+# Create the export directory if not present
+file mkdir ${EXPORT_DIR}
+print_status "Initialize workspace directories" "OK"
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/${prj_name}/${prj_name}.xpr
+print_status "Open project $prj_name" "OK"
+
+# Export the hardware including the bitstream
+write_hw_platform -fixed -force -include_bit -file ${EXPORT_DIR}/${prj_name}.xsa
+print_status "Export hardware to Vitis SDK" "OK"
+
+exit
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/gen_bitstream_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/gen_bitstream_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..1f47d351566db606d76830b9defa5d8b6b0361ff
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/gen_bitstream_scalp_mipi.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate bitstream file
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+PRJ_DIR=..
+
+echo "> Generate bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./gen_bitstream_scalp_mipi.tcl -notrace
+
+echo "> Copy bitstream file in current directory..."
+mkdir -p ${PRJ_DIR}/bitstream/
+cp ${PRJ_DIR}/scalp_mipi/scalp_mipi.runs/impl_1/scalp_mipi.bit ${PRJ_DIR}/bitstream/scalp_mipi.bit
+
+echo "> Done"
+
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/gen_bitstream_scalp_mipi.tcl b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/gen_bitstream_scalp_mipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7ef7e74e7fad91b74bc09628fcf1738644e06e8a
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/gen_bitstream_scalp_mipi.tcl
@@ -0,0 +1,56 @@
+#!/usr/bin/tcl
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to generate bitstream file
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_mipi"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
+update_compile_order -fileset sources_1
+print_status "Open project $prj_name" "OK"
+
+# Run synthesis
+print_status "Run synthesis" "IN_PROGRESS"
+launch_runs synth_1
+wait_on_run synth_1
+print_status "Run synthesis" "OK"
+
+# Run implementation
+print_status "Run implementation" "IN_PROGRESS"
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+wait_on_run impl_1
+print_status "Run implementation" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time on the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/load_bitstream_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/load_bitstream_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..042010a742cdc38b5273f7f47d723d06a0ce8f8a
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/load_bitstream_scalp_mipi.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Load bitstream file
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Load bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./load_bitstream_scalp_mipi.tcl -notrace
+echo "> Done"
+
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/load_bitstream_scalp_mipi.tcl b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/load_bitstream_scalp_mipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..da17f5d79b26548fe992a04c1a6036095d516a82
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/load_bitstream_scalp_mipi.tcl
@@ -0,0 +1,61 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to load FPGA bitstream
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_mipi"
+
+# Open the hardware manager and connect to the hardware server
+open_hw
+print_status "Open hardware manager" "OK"
+connect_hw_server -url localhost:3121
+print_status "Connect to hardware server" "OK"
+
+# Get the hardware target and open it
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
+open_hw_target
+print_status "Open hardware target" "OK"
+
+# Display targets list
+set index -1
+set targets [lindex [get_hw_devices]]
+puts "Found target(s):"
+foreach target $targets {
+ incr index
+ puts "$index : $target"
+}
+puts "Which target do you want to program?"
+set sel_target [read stdin 1]
+
+# Set the program file
+set_property PROGRAM.FILE ${PRJ_DIR}/bitstream/$prj_name.bit [lindex [get_hw_devices] $sel_target]
+current_hw_device [lindex [get_hw_devices] $sel_target]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] $sel_target]
+print_status "Set program file" "OK"
+
+# Program the device
+print_status "Program device" "IN_PROGRESS"
+program_hw_device [lindex [get_hw_devices] $sel_target]
+print_status "Program device" "OK"
+
+exit
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/open_prj_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/open_prj_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..d9e0792109991efd9ec9c04fb8e390bda6a1acdf
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/open_prj_scalp_mipi.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_mipi/scalp_mipi.xpr
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..73ab971d8aa05bfa57dcfe31a17d7c796a87edea
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/designs/vivado/scalp_mipi/2020.2/lin64/setup.sh b/designs/vivado/scalp_mipi/2020.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..ac39c185817ea986e3a3c80b058d95c45075182c
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/lin64/setup.sh
@@ -0,0 +1,28 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_mipi.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_mipi.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_mipi.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_mipi.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_mipi.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_mipi.sh && cd ..'
diff --git a/designs/vivado/scalp_mipi/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_mipi/2020.2/src/constrs/debug.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/designs/vivado/scalp_mipi/2020.2/src/constrs/ibert_constraints.xdc b/designs/vivado/scalp_mipi/2020.2/src/constrs/ibert_constraints.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..602b523f941544701ea24e62603c5fb40558d97e
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/constrs/ibert_constraints.xdc
@@ -0,0 +1,382 @@
+# Taken from IBERT example design
+
+##
+## Icon Constraints
+##
+create_clock -name J_CLK -period 30 [get_pins -of_objects [get_cells gen_ibert.ibert_inst/inst/bscan_inst/SERIES7_BSCAN.bscan_inst] -filter {name =~ *DRCK}]
+set_clock_groups -group [get_clocks J_CLK] -asynchronous
+##
+## System clock Divider paramter values
+##
+set_property CLKFBOUT_MULT_F 8.000 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property DIVCLK_DIVIDE 1 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property CLKIN1_PERIOD 8.0 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property CLKOUT0_DIVIDE_F 10.000 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+##
+## Refclk constraints
+##
+set_clock_groups -group [get_clocks GTP_REF_CLK_* -include_generated_clocks] -asynchronous
+#
+#
+#
+##
+## TX/RX out clock constraints
+##
+# GT X0Y0
+create_clock -name Q0_RXCLK0 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[0].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK0] -asynchronous
+create_clock -name Q0_TX0 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[0].u_ch/u_gtpe2_channel/TXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_TX0] -asynchronous
+# GT X0Y1
+create_clock -name Q0_RXCLK1 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[1].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK1] -asynchronous
+# GT X0Y2
+create_clock -name Q0_RXCLK2 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[2].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK2] -asynchronous
+# GT X0Y3
+create_clock -name Q0_RXCLK3 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[3].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK3] -asynchronous
+##
+## Timing constraint
+##
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM/CLKIN1]
+##
+## GTPE2 Channel and Common Loc constraints
+##
+set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[0].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[1].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[2].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y3 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[3].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_COMMON_X0Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+##
+## BUFH Loc constraints for TX/RX userclks
+##
+set_property LOC BUFHCE_X1Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/local_txusr.u_txusr]
+set_property LOC BUFHCE_X1Y1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr0]
+set_property LOC BUFHCE_X1Y2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr1]
+set_property LOC BUFHCE_X1Y3 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr2]
+set_property LOC BUFHCE_X1Y4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr3]
+##
+## MGT reference clock BUFFERS location constraints
+##
+
+
+set_property LOC IBUFDS_GTE2_X0Y0 [get_cells i_clocks.ibufds_GTP_REF_CLK_0]
+set_property LOC IBUFDS_GTE2_X0Y1 [get_cells i_clocks.ibufds_GTP_REF_CLK_1]
+
+##
+## Attribute values for GTPE2 Channel and Common instances
+##
+##
+##remove ASYNC_REG property
+##
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_310/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_30E/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_312/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_314/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_306/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg]
+
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg]
+
+##
+## Attribute Values for QUAD[0] - Channel
+##
+ ##------Comma Detection and Alignment---------
+set_property ALIGN_COMMA_DOUBLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_COMMA_ENABLE 10'b0001111111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_COMMA_WORD 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_MCOMMA_DET "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_MCOMMA_VALUE 10'b1010000011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_PCOMMA_DET "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_PCOMMA_VALUE 10'b0101111100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_MCOMMA_DETECT "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_PCOMMA_DETECT "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_VALID_COMMA_ONLY "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DMONITOR_CFG 24'h000A00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##--------------Channel Bonding--------------
+set_property CBCC_DATA_SOURCE_SEL "DECODED" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_KEEP_ALIGN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_MAX_SKEW 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_LEN 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_1 10'b0101111100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_1 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Clock Correction------------
+set_property CLK_COR_KEEP_IDLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_MAX_LAT 9.0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_MIN_LAT 7.0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_PRECEDENCE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_CORRECT_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_REPEAT_WAIT 0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_LEN 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_1 10'b0100011100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_1 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Channel PLL----------------------
+set_property RXOUT_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXOUT_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------Eyescan--------------
+set_property ES_CONTROL 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_ERRDET_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_EYE_SCAN_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_HORZ_OFFSET 12'h002 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_PMA_CFG 10'b0000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_PRESCALE 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_QUALIFIER 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_QUAL_MASK 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_SDATA_MASK 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_VERT_OFFSET 9'b010000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_DESKEW_SEQ_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_LANE_DESKEW_CFG 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_LANE_DESKEW_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property GEARBOX_MODE 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property OUTREFCLK_SEL_INV 2'b11 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PCS_PCIE_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PCS_RSVD_ATTR 48'h000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV 32'h00000333 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV2 32'h00002040 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV3 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV4 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV5 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV6 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV7 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_BIAS_CFG 16'b0000111100110011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_PREDRIVER_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Rx Elastic Buffer and Phase alignment-------------
+set_property RXBUF_ADDR_MODE "FAST" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EIDLE_HI_CNT 4'b1000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EIDLE_LO_CNT 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_BUFFER_CFG 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_CB_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_COMMAALIGN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_EIDLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_RATE_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUFRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_OVFLW 61 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_OVRD "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_UNDFLW 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_CFG 16'h0010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_LCFG 9'h020 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_TAP_CFG 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------RX driver, OOB signalling, Coupling and Eq., CDR------------
+set_property RXCDR_CFG 83'h0001107FE206021041010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDRFREQRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_FR_RESET_ON_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_HOLD_DURING_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_LOCK_CFG 6'b001001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_PH_RESET_ON_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDRPHRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOOB_CFG 7'b0000110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------RX Interface-------------------------
+set_property RX_DATA_WIDTH 16 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CLK25_DIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CM_SEL 2'b11 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CM_TRIM 4'b1010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DDI_SEL 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DEBUG_CFG 12'b000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##------------RX Decision Feedback Equalizer(DFE)-------------
+set_property RX_DEFER_RESET_BUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_OS_CFG 13'b0000010000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DISPERR_SEQ_MATCH "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------RX Gearbox---------------------------
+set_property RXGEARBOX_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXISCANRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG 14'b00001111110000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG2 5'b01010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG3 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HOLD_DURING_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_INCM_CFG 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_IPCM_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_LF_CFG 18'b000000001111110000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_LF_CFG2 5'b01010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_OSINT_CFG 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPCSRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPH_CFG 24'hC00002 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPHDLY_CFG 24'h084000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPH_MONITOR_SEL 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPMARESET_TIME 5'b00011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------PRBS Detection-----------------------
+set_property RXPRBS_ERR_LOOPBACK 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_SIG_VALID_DLY 10 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSLIDE_AUTO_WAIT 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSLIDE_MODE "off" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_XCLK_SEL "RXREC" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------RX Attributes for PCI Express/SATA/SAS----------
+set_property PD_TRANS_TIME_FROM_P2 12'h03c [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PD_TRANS_TIME_NONE_P2 8'h3c [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PD_TRANS_TIME_TO_P2 8'h64 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SAS_MAX_COM 64 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SAS_MIN_COM 36 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_BURST_SEQ_LEN 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_BURST_VAL 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_PLL_CFG VCO_3000MHZ [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_EIDLE_VAL 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_BURST 8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_INIT 21 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_WAKE 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_BURST 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_INIT 12 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_WAKE 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SHOW_REALIGN_COMMA "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TERM_RCAL_CFG 15'b100001000010000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TERM_RCAL_OVRD 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TRANS_TIME_RATE 8'h0E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TST_RSV 32'h00000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##------------TX Buffering and Phase Alignment----------------
+set_property TXBUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXBUF_RESET_ON_RATE_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------TX Interface-------------------------
+set_property TX_DATA_WIDTH 16 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DEEMPH0 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DEEMPH1 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_CFG 16'h0010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_LCFG 9'h020 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_TAP_CFG 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_CLK25_DIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##--------------TX Driver and OOB Signalling------------------
+set_property TX_EIDLE_ASSERT_DELAY 3'b110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_EIDLE_DEASSERT_DELAY 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_LOOPBACK_DRIVE_HIZ "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MAINCURSOR_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DRIVE_MODE "DIRECT" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------TX Gearbox---------------------------
+set_property TXGEARBOX_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##----------------TX Attributes for PCI Express---------------
+set_property TX_MARGIN_FULL_0 7'b1001110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_1 7'b1001001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_2 7'b1000101 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_3 7'b1000010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_4 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_0 7'b1000110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_1 7'b1000100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_2 7'b1000010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_3 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_4 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPCSRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPH_CFG 16'h0400 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPHDLY_CFG 24'h084000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPH_MONITOR_SEL 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPMARESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_RXDETECT_CFG 14'h1832 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_RXDETECT_REF 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_XCLK_SEL "TXOUT" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property UCODEER_CLR 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##---------------- JTAG Attributes ---------------
+set_property ACJTAG_DEBUG_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ACJTAG_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ACJTAG_RESET 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ADAPT_CFG0 20'h00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPMRESET_TIME 7'b0001111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_BIAS_STARTUP_DISABLE 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CFG 4'b0110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CFG1 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CM_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_GC_CFG 9'b101110010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_GC_CFG2 3'b001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG 43'h49000040E80 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG2 7'b0100000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG3 7'b0100000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG4 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG5 2'h0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG6 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- EYESCAN ---------------
+set_property ES_CLK_PHASE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV5 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- RX Phase Interpolator ---------------
+set_property RXPI_CFG0 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPI_CFG1 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPI_CFG2 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- TX Phase Interpolator ---------------
+set_property TXPI_CFG0 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG1 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG2 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG3 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG4 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG5 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_GREY_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_INVSTROBE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_PPMCLK_SEL TXUSRCLK2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_PPM_CFG 8'h00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_SYNFREQ_PPM 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property USE_PCS_CLK_PHASE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- LOOPBACK ---------------
+set_property LOOPBACK_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- OOB Signalling ---------------
+set_property RXOOB_CLK_CFG PMA [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOSCALRESET_TIME 5'b00011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOSCALRESET_TIMEOUT 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXOOB_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##---------------- PMA Attributes ---------------
+set_property CLK_COMMON_SWING 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CLKMUX_EN 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_CLKMUX_EN 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_LOOPBACK_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##---------------- RX SYNC ---------------
+set_property RXSYNC_MULTILANE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSYNC_OVRD 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSYNC_SKIP_DA 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- TX SYNC ---------------
+set_property TXSYNC_MULTILANE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXSYNC_OVRD 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXSYNC_SKIP_DA 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##
+## Attribute Values for QUAD[0] - Common
+##
+set_property BIAS_CFG 64'h0000000000050001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property COMMON_CFG 32'h00000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_CFG 27'h01F0319 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_CFG 27'h01F0319 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_DMON_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_DMON_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL_CLKOUT_CFG 8'h00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_INIT_CFG 24'h00001E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_INIT_CFG 24'h00001E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_LOCK_CFG 9'h1E8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_LOCK_CFG 9'h1E8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_FBDIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_FBDIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_FBDIV_45 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_FBDIV_45 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_REFCLK_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_REFCLK_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property RSVD_ATTR0 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property RSVD_ATTR1 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
diff --git a/designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc b/designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..1c6f11890dceff8dec33e552c46327b64189a891
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc
@@ -0,0 +1,253 @@
+############################################################################
+# Programmable Logic placement constraints #
+############################################################################
+
+##### USB interface (bank 13) #####
+# USB_VBUS_PWRFAULT_i
+set_property PACKAGE_PIN AA19 [get_ports UsbVbusPwrFaultxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports UsbVbusPwrFaultxSI]
+
+##### PLL interface (banks 35 and 34) #####
+# PLL_2V5_CLKuWire_o
+set_property PACKAGE_PIN G8 [get_ports Pll2V5ClkuWirexCO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkuWirexCO]
+# PLL_2V5_DATAuWire_o
+set_property PACKAGE_PIN G7 [get_ports Pll2V5DatauWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5DatauWirexSO]
+# PLL_2V5_LEuWire_o
+set_property PACKAGE_PIN G6 [get_ports Pll2V5LEuWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LEuWirexSO]
+# PLL_2V5_GOE_o
+set_property PACKAGE_PIN F6 [get_ports Pll2V5GOExSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5GOExSO]
+# PLL_2V5_LD_i
+set_property PACKAGE_PIN H6 [get_ports Pll2V5LDxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LDxSI]
+# PLL_2V5_SYNC_n_o
+set_property PACKAGE_PIN H5 [get_ports Pll2V5SyncxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5SyncxSO]
+# PLL_2V5_CLKIN0_LOS_i (bank 34)
+set_property PACKAGE_PIN J3 [get_ports Pll2V5ClkIn0LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn0LOSxSI]
+# PLL_2V5_CLKIN1_LOS_i (bank 34)
+set_property PACKAGE_PIN K2 [get_ports Pll2V5ClkIn1LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
+
+##### GTP interfaces (bank 112) #####
+#set_property PACKAGE_PIN U9 [get_ports GTPRefClk0PxCI]
+#set_property PACKAGE_PIN V9 [get_ports GTPRefClk0NxCI]
+#set_property PACKAGE_PIN "U5" [get_ports "GTPRefClk1PxCI"]
+#set_property PACKAGE_PIN "V5" [get_ports "GTPRefClk1NxCI"]
+#set_property PACKAGE_PIN Y8 [get_ports GTPFromNorthNxSI]
+#set_property PACKAGE_PIN W8 [get_ports GTPFromNorthPxSI]
+#set_property PACKAGE_PIN Y4 [get_ports GTPToNorthNxSO]
+#set_property PACKAGE_PIN W4 [get_ports GTPToNorthPxSO]
+#set_property PACKAGE_PIN AB7 [get_ports GTPFromSouthNxSI]
+#set_property PACKAGE_PIN AA7 [get_ports GTPFromSouthPxSI]
+#set_property PACKAGE_PIN AB3 [get_ports GTPToSouthNxSO]
+#set_property PACKAGE_PIN AA3 [get_ports GTPToSouthPxSO]
+#set_property PACKAGE_PIN AB9 [get_ports GTPFromEastNxSI]
+#set_property PACKAGE_PIN AA9 [get_ports GTPFromEastPxSI]
+#set_property PACKAGE_PIN AB5 [get_ports GTPToEastNxSO]
+#set_property PACKAGE_PIN AA5 [get_ports GTPToEastPxSO]
+#set_property PACKAGE_PIN Y6 [get_ports GTPFromWestNxSI]
+#set_property PACKAGE_PIN W6 [get_ports GTPFromWestPxSI]
+#set_property PACKAGE_PIN Y2 [get_ports GTPToWestNxSO]
+#set_property PACKAGE_PIN W2 [get_ports GTPToWestPxSO]
+
+##### LVDS links towards edge connectors #####
+# North (bank 35)
+#set_property PACKAGE_PIN "E8" [get_ports "LVDS2V5North7PxSIO"]
+#set_property PACKAGE_PIN "D8" [get_ports "LVDS2V5North7NxSIO"]
+#set_property PACKAGE_PIN "D7" [get_ports "LVDS2V5North6PxSIO"]
+#set_property PACKAGE_PIN "D6" [get_ports "LVDS2V5North6NxSIO"]
+#set_property PACKAGE_PIN "C8" [get_ports "LVDS2V5North5PxSIO"]
+#set_property PACKAGE_PIN "B8" [get_ports "LVDS2V5North5NxSIO"]
+#set_property PACKAGE_PIN "B7" [get_ports "LVDS2V5North4PxSIO"]
+#set_property PACKAGE_PIN "B6" [get_ports "LVDS2V5North4NxSIO"]
+#set_property PACKAGE_PIN "A7" [get_ports "LVDS2V5North3PxSIO"]
+#set_property PACKAGE_PIN "A6" [get_ports "LVDS2V5North3NxSIO"]
+#set_property PACKAGE_PIN "A5" [get_ports "LVDS2V5North2PxSIO"]
+#set_property PACKAGE_PIN "A4" [get_ports "LVDS2V5North2NxSIO"]
+#set_property PACKAGE_PIN "B2" [get_ports "LVDS2V5North1PxSIO"]
+#set_property PACKAGE_PIN "B1" [get_ports "LVDS2V5North1NxSIO"]
+#set_property PACKAGE_PIN "A2" [get_ports "LVDS2V5North0PxSIO"]
+#set_property PACKAGE_PIN "A1" [get_ports "LVDS2V5North0NxSIO"]
+# South (bank 13)
+#set_property PACKAGE_PIN "V15" [get_ports "LVDS2V5South7PxSIO"]
+#set_property PACKAGE_PIN "W15" [get_ports "LVDS2V5South7NxSIO"]
+#set_property PACKAGE_PIN "AB13" [get_ports "LVDS2V5South6PxSIO"]
+#set_property PACKAGE_PIN "AB14" [get_ports "LVDS2V5South6NxSIO"]
+#set_property PACKAGE_PIN "V13" [get_ports "LVDS2V5South5PxSIO"]
+#set_property PACKAGE_PIN "V14" [get_ports "LVDS2V5South5NxSIO"]
+#set_property PACKAGE_PIN "Y12" [get_ports "LVDS2V5South4PxSIO"]
+#set_property PACKAGE_PIN "Y13" [get_ports "LVDS2V5South4NxSIO"]
+#set_property PACKAGE_PIN "AA12" [get_ports "LVDS2V5South3PxSIO"]
+#set_property PACKAGE_PIN "AB12" [get_ports "LVDS2V5South3NxSIO"]
+#set_property PACKAGE_PIN "W12" [get_ports "LVDS2V5South2PxSIO"]
+#set_property PACKAGE_PIN "W13" [get_ports "LVDS2V5South2NxSIO"]
+#set_property PACKAGE_PIN "AA11" [get_ports "LVDS2V5South1PxSIO"]
+#set_property PACKAGE_PIN "AB11" [get_ports "LVDS2V5South1NxSIO"]
+#set_property PACKAGE_PIN "V11" [get_ports "LVDS2V5South0PxSIO"]
+#set_property PACKAGE_PIN "W11" [get_ports "LVDS2V5South0NxSIO"]
+# East (bank 13)
+#set_property PACKAGE_PIN "V16" [get_ports "LVDS2V5East7PxSIO"]
+#set_property PACKAGE_PIN "W16" [get_ports "LVDS2V5East7NxSIO"]
+#set_property PACKAGE_PIN "W17" [get_ports "LVDS2V5East6PxSIO"]
+#set_property PACKAGE_PIN "Y17" [get_ports "LVDS2V5East6NxSIO"]
+#set_property PACKAGE_PIN "U13" [get_ports "LVDS2V5East5PxSIO"]
+#set_property PACKAGE_PIN "U14" [get_ports "LVDS2V5East5NxSIO"]
+#set_property PACKAGE_PIN "V18" [get_ports "LVDS2V5East4PxSIO"]
+#set_property PACKAGE_PIN "W18" [get_ports "LVDS2V5East4NxSIO"]
+#set_property PACKAGE_PIN "U11" [get_ports "LVDS2V5East3PxSIO"]
+#set_property PACKAGE_PIN "U12" [get_ports "LVDS2V5East3NxSIO"]
+#set_property PACKAGE_PIN "U19" [get_ports "LVDS2V5East2PxSIO"]
+#set_property PACKAGE_PIN "V19" [get_ports "LVDS2V5East2NxSIO"]
+#set_property PACKAGE_PIN "R17" [get_ports "LVDS2V5East1PxSIO"]
+#set_property PACKAGE_PIN "T17" [get_ports "LVDS2V5East1NxSIO"]
+#set_property PACKAGE_PIN "U17" [get_ports "LVDS2V5East0PxSIO"]
+#set_property PACKAGE_PIN "U18" [get_ports "LVDS2V5East0NxSIO"]
+# West (bank 35)
+#set_property PACKAGE_PIN "H4" [get_ports "LVDS2V5West7PxSIO"]
+#set_property PACKAGE_PIN "H3" [get_ports "LVDS2V5West7NxSIO"]
+#set_property PACKAGE_PIN "H1" [get_ports "LVDS2V5West6PxSIO"]
+#set_property PACKAGE_PIN "G1" [get_ports "LVDS2V5West6NxSIO"]
+#set_property PACKAGE_PIN "G3" [get_ports "LVDS2V5West5PxSIO"]
+#set_property PACKAGE_PIN "G2" [get_ports "LVDS2V5West5NxSIO"]
+#set_property PACKAGE_PIN "F2" [get_ports "LVDS2V5West4PxSIO"]
+#set_property PACKAGE_PIN "F1" [get_ports "LVDS2V5West4NxSIO"]
+#set_property PACKAGE_PIN "G4" [get_ports "LVDS2V5West3PxSIO"]
+#set_property PACKAGE_PIN "F4" [get_ports "LVDS2V5West3NxSIO"]
+#set_property PACKAGE_PIN "E2" [get_ports "LVDS2V5West2PxSIO"]
+#set_property PACKAGE_PIN "D2" [get_ports "LVDS2V5West2NxSIO"]
+#set_property PACKAGE_PIN "E4" [get_ports "LVDS2V5West1PxSIO"]
+#set_property PACKAGE_PIN "E3" [get_ports "LVDS2V5West1NxSIO"]
+#set_property PACKAGE_PIN "D1" [get_ports "LVDS2V5West0PxSIO"]
+#set_property PACKAGE_PIN "C1" [get_ports "LVDS2V5West0NxSIO"]
+
+##### LVDS links towards top-bottom connectors #####
+# Top (bank 34)
+#set_property PACKAGE_PIN "J8" [get_ports "LVDS2V5Top7PxSIO"]
+#set_property PACKAGE_PIN "K8" [get_ports "LVDS2V5Top7NxSIO"]
+#set_property PACKAGE_PIN "K7" [get_ports "LVDS2V5Top6PxSIO"]
+#set_property PACKAGE_PIN "L7" [get_ports "LVDS2V5Top6NxSIO"]
+#set_property PACKAGE_PIN "N8" [get_ports "LVDS2V5Top5PxSIO"]
+#set_property PACKAGE_PIN "P8" [get_ports "LVDS2V5Top5NxSIO"]
+#set_property PACKAGE_PIN "M8" [get_ports "LVDS2V5Top4PxSIO"]
+#set_property PACKAGE_PIN "M7" [get_ports "LVDS2V5Top4NxSIO"]
+#set_property PACKAGE_PIN "L6" [get_ports "LVDS2V5Top3PxSIO"]
+#set_property PACKAGE_PIN "M6" [get_ports "LVDS2V5Top3NxSIO"]
+#set_property PACKAGE_PIN "J7" [get_ports "LVDS2V5Top2PxSIO"]
+#set_property PACKAGE_PIN "J6" [get_ports "LVDS2V5Top2NxSIO"]
+#set_property PACKAGE_PIN "J5" [get_ports "LVDS2V5Top1PxSIO"]
+#set_property PACKAGE_PIN "K5" [get_ports "LVDS2V5Top1NxSIO"]
+#set_property PACKAGE_PIN "J2" [get_ports "LVDS2V5Top0PxSIO"]
+#set_property PACKAGE_PIN "J1" [get_ports "LVDS2V5Top0NxSIO"]
+# Bottom (bank 34)
+#set_property PACKAGE_PIN "N6" [get_ports "LVDS2V5Bottom7PxSIO"]
+#set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
+#set_property PACKAGE_PIN "P6" [get_ports "LVDS2V5Bottom6PxSIO"]
+#set_property PACKAGE_PIN "P5" [get_ports "LVDS2V5Bottom6NxSIO"]
+#set_property PACKAGE_PIN "R5" [get_ports "LVDS2V5Bottom5PxSIO"]
+#set_property PACKAGE_PIN "R4" [get_ports "LVDS2V5Bottom5NxSIO"]
+#set_property PACKAGE_PIN "R3" [get_ports "LVDS2V5Bottom4PxSIO"]
+#set_property PACKAGE_PIN "R2" [get_ports "LVDS2V5Bottom4NxSIO"]
+#set_property PACKAGE_PIN "P3" [get_ports "LVDS2V5Bottom3PxSIO"]
+#set_property PACKAGE_PIN "P2" [get_ports "LVDS2V5Bottom3NxSIO"]
+#set_property PACKAGE_PIN "N1" [get_ports "LVDS2V5Bottom2PxSIO"]
+#set_property PACKAGE_PIN "P1" [get_ports "LVDS2V5Bottom2NxSIO"]
+#set_property PACKAGE_PIN "N4" [get_ports "LVDS2V5Bottom1PxSIO"]
+#set_property PACKAGE_PIN "N3" [get_ports "LVDS2V5Bottom1NxSIO"]
+#set_property PACKAGE_PIN "M2" [get_ports "LVDS2V5Bottom0PxSIO"]
+#set_property PACKAGE_PIN "M1" [get_ports "LVDS2V5Bottom0NxSIO"]
+
+##### RGB LEDs (banks 34 and 13) #####
+# LED1_2V5_R_o (bank 34)
+set_property PACKAGE_PIN L2 [get_ports Led12V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5RxSO]
+# LED1_2V5_G_o (bank 34)
+set_property PACKAGE_PIN L1 [get_ports Led12V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5GxSO]
+# LED1_2V5_B_o (bank 34)
+set_property PACKAGE_PIN R8 [get_ports Led12V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5BxSO]
+# LED2_2V5_R_o (bank 13)
+set_property PACKAGE_PIN T16 [get_ports Led22V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5RxSO]
+# LED2_2V5_G_o (bank 13)
+set_property PACKAGE_PIN U16 [get_ports Led22V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5GxSO]
+# LED2_2V5_B_o (bank 13)
+set_property PACKAGE_PIN AA20 [get_ports Led22V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5BxSO]
+
+##### Self reset (bank 34) #####
+set_property PACKAGE_PIN H8 [get_ports SelfRstxRNO]
+set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
+
+##### Clock dedicated pins (Multi-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "D5" [get_ports "PLLClk2V5LocalPxCI"]
+#set_property PACKAGE_PIN "C4" [get_ports "PLLClk2V5LocalNxCI"]
+#set_property PACKAGE_PIN "B4" [get_ports "PLLClk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "B3" [get_ports "PLLClk2V5NorthNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "T2" [get_ports "PLLClk2V5TopxCI"]
+#set_property PACKAGE_PIN "L5" [get_ports "PLLClk2V5BottomxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "Y14" [get_ports "PLLClk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "Y15" [get_ports "PLLClk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "Y18" [get_ports "Clk2V5RecoveryPxCO"]
+#set_property PACKAGE_PIN "Y19" [get_ports "Clk2V5RecoveryNxCO"]
+
+##### Clock dedicated pins (Single-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "C6" [get_ports "Clk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "C5" [get_ports "Clk2V5NorthNxCI"]
+#set_property PACKAGE_PIN "D3" [get_ports "Clk2V5WestPxCI"]
+#set_property PACKAGE_PIN "C3" [get_ports "Clk2V5WestNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "K4" [get_ports "Clk2V5TopPxCI"]
+#set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
+#set_property PACKAGE_PIN "U2" [get_ports "Clk2V5BottomPxCI"]
+#set_property PACKAGE_PIN "U1" [get_ports "Clk2V5BottomNxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "AA16" [get_ports "Clk2V5EastPxCI"]
+#set_property PACKAGE_PIN "AA17" [get_ports "Clk2V5EastNxCI"]
+
+##### Clock outputs #####
+## Bank 35
+#set_property PACKAGE_PIN "F7" [get_ports "Clk2V5NorthPxCO"]
+#set_property PACKAGE_PIN "E7" [get_ports "Clk2V5NorthNxCO"]
+#set_property PACKAGE_PIN "F5" [get_ports "Clk2V5WestPxCO"]
+#set_property PACKAGE_PIN "E5" [get_ports "Clk2V5WestNxCO"]
+# Bank 34
+#set_property PACKAGE_PIN "P7" [get_ports "Clk2V5TopPxCO"]
+#set_property PACKAGE_PIN "R7" [get_ports "Clk2V5TopNxCO"]
+#set_property PACKAGE_PIN "M4" [get_ports "Clk2V5BottomPxCO"]
+#set_property PACKAGE_PIN "M3" [get_ports "Clk2V5BottomNxCO"]
+# Bank 13
+#set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
+#set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
+#set_property PACKAGE_PIN "AB21" [get_ports "Clk2V5EastPxCO"]
+#set_property PACKAGE_PIN "AB22" [get_ports "Clk2V5EastNxCO"]
+
+############################################################################
+# Other constraints #
+############################################################################
+
+##### Operating conditions (for XPE report) #####
+# Extended grade (as for -2 speed grade) and maximum consumption estimation
+set_operating_conditions -grade extended -process maximum
+# 4'' by 4'' PCB, no heatsink, no air flow
+set_operating_conditions -airflow 0 -heatsink none -board small
+
+
+
+
+
+
+
+
diff --git a/designs/vivado/scalp_mipi/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_mipi/2020.2/src/constrs/timing_constraints.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..4e6bc99bf0860f3bb0b41de5d77703375e7c0b6b
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/constrs/timing_constraints.xdc
@@ -0,0 +1,33 @@
+############################################################################
+# Timing constraints #
+############################################################################
+
+##### PS_CLK (125 MHz) #####
+create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
+
+##### GTP reference clocks (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk1xC]
+
+##### Clocks from PLLs (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Local}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Bottom}]
+
+##### Clocks from neighbours (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_East}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_West}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Bottom}]
+
+
+
+
+
+
+
+
diff --git a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e66c9a8584dedcf937c28dca3e40004cdb3d6b0a
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
@@ -0,0 +1,425 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+--
+-- Module Name: scalp_mipi - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_mipi
+--
+-- Last update: 2021-04-28 16:21:16
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+-- Axi4 packages
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity scalp_mipi is
+
+ generic (
+ C_USE_IBERT : boolean := false;
+ C_DEBUG_MODE : boolean := false);
+
+ port (
+ -----------------------------------------------------------------------
+ -- Names defined and not described in the constraint file.
+ -----------------------------------------------------------------------
+ -- Zynq FIXED_IO
+ PSClkxCIO : inout std_logic;
+ PSSRstxRNIO : inout std_logic;
+ PSPorxSNIO : inout std_logic;
+ -- DDR interface
+ DDRClkNxCIO : inout std_logic;
+ DDRClkPxCIO : inout std_logic;
+ DDRDRstxRNIO : inout std_logic;
+ DDRCasNxSIO : inout std_logic;
+ DDRCkexSIO : inout std_logic;
+ DDRCsNxSIO : inout std_logic;
+ DDROdtxSIO : inout std_logic;
+ DDRRasNxSIO : inout std_logic;
+ DDRWexSNIO : inout std_logic;
+ DDRBankAddrxDIO : inout std_logic_vector(2 downto 0);
+ DDRAddrxDIO : inout std_logic_vector(14 downto 0);
+ DDRVrNxSIO : inout std_logic;
+ DDRVrPxSIO : inout std_logic;
+ DDRDmxDIO : inout std_logic_vector(3 downto 0);
+ DDRDqxDIO : inout std_logic_vector(31 downto 0);
+ DDRDqsNxDIO : inout std_logic_vector(3 downto 0);
+ DDRDqsPxDIO : inout std_logic_vector(3 downto 0);
+ -- MIO Interface
+ MIOxDIO : inout std_logic_vector(53 downto 0);
+ -----------------------------------------------------------------------
+ -- USB signals
+ UsbVbusPwrFaultxSI : in std_logic;
+ -- PLL interface
+ Pll2V5ClkuWirexCO : out std_logic; -- Clock (from SPI1_SCLK)
+ Pll2V5DatauWirexSO : out std_logic; -- Data (from SPI1_MOSI)
+ Pll2V5LEuWirexSO : out std_logic; -- Latch enable (from SPI1_SS)
+ Pll2V5GOExSO : out std_logic; -- Global Output Enable
+ Pll2V5LDxSI : in std_logic; -- Lock Detect
+ Pll2V5SyncxSO : out std_logic; -- Sync
+ Pll2V5ClkIn0LOSxSI : in std_logic; -- FPGA clock Loss of Sync
+ Pll2V5ClkIn1LOSxSI : in std_logic; -- External oscillator Loss of Sync
+ -- GTP interfaces
+ -- Clocks
+ -- GTPRefClk0PxCI : in std_logic;
+ -- GTPRefClk0NxCI : in std_logic;
+ -- GTPRefClk1PxCI : in std_logic;
+ -- GTPRefClk1NxCI : in std_logic;
+ -- North
+ -- GTPFromNorthPxSI : in std_logic;
+ -- GTPFromNorthNxSI : in std_logic;
+ -- GTPToNorthPxSO : out std_logic;
+ -- GTPToNorthNxSO : out std_logic;
+ -- East
+ -- GTPFromEastPxSI : in std_logic;
+ -- GTPFromEastNxSI : in std_logic;
+ -- GTPToEastPxSO : out std_logic;
+ -- GTPToEastNxSO : out std_logic;
+ -- South
+ -- GTPFromSouthPxSI : in std_logic;
+ -- GTPFromSouthNxSI : in std_logic;
+ -- GTPToSouthPxSO : out std_logic;
+ -- GTPToSouthNxSO : out std_logic;
+ -- West
+ -- GTPFromWestPxSI : in std_logic;
+ -- GTPFromWestNxSI : in std_logic;
+ -- GTPToWestPxSO : out std_logic;
+ -- GTPToWestNxSO : out std_logic;
+ -- LVDS links towards edge connectors
+ -- North
+ -- LVDS2V5North0PxSIO : inout std_logic;
+ -- LVDS2V5North0NxSIO : inout std_logic;
+ -- LVDS2V5North1PxSIO : inout std_logic;
+ -- LVDS2V5North1NxSIO : inout std_logic;
+ -- LVDS2V5North2PxSIO : inout std_logic;
+ -- LVDS2V5North2NxSIO : inout std_logic;
+ -- LVDS2V5North3PxSIO : inout std_logic;
+ -- LVDS2V5North3NxSIO : inout std_logic;
+ -- LVDS2V5North4PxSIO : inout std_logic;
+ -- LVDS2V5North4NxSIO : inout std_logic;
+ -- LVDS2V5North5PxSIO : inout std_logic;
+ -- LVDS2V5North5NxSIO : inout std_logic;
+ -- LVDS2V5North6PxSIO : inout std_logic;
+ -- LVDS2V5North6NxSIO : inout std_logic;
+ -- LVDS2V5North7PxSIO : inout std_logic;
+ -- LVDS2V5North7NxSIO : inout std_logic;
+ -- South
+ -- LVDS2V5South0PxSIO : inout std_logic;
+ -- LVDS2V5South0NxSIO : inout std_logic;
+ -- LVDS2V5South1PxSIO : inout std_logic;
+ -- LVDS2V5South1NxSIO : inout std_logic;
+ -- LVDS2V5South2PxSIO : inout std_logic;
+ -- LVDS2V5South2NxSIO : inout std_logic;
+ -- LVDS2V5South3PxSIO : inout std_logic;
+ -- LVDS2V5South3NxSIO : inout std_logic;
+ -- LVDS2V5South4PxSIO : inout std_logic;
+ -- LVDS2V5South4NxSIO : inout std_logic;
+ -- LVDS2V5South5PxSIO : inout std_logic;
+ -- LVDS2V5South5NxSIO : inout std_logic;
+ -- LVDS2V5South6PxSIO : inout std_logic;
+ -- LVDS2V5South6NxSIO : inout std_logic;
+ -- LVDS2V5South7PxSIO : inout std_logic;
+ -- LVDS2V5South7NxSIO : inout std_logic;
+ -- East
+ -- LVDS2V5East0PxSIO : inout std_logic;
+ -- LVDS2V5East0NxSIO : inout std_logic;
+ -- LVDS2V5East1PxSIO : inout std_logic;
+ -- LVDS2V5East1NxSIO : inout std_logic;
+ -- LVDS2V5East2PxSIO : inout std_logic;
+ -- LVDS2V5East2NxSIO : inout std_logic;
+ -- LVDS2V5East3PxSIO : inout std_logic;
+ -- LVDS2V5East3NxSIO : inout std_logic;
+ -- LVDS2V5East4PxSIO : inout std_logic;
+ -- LVDS2V5East4NxSIO : inout std_logic;
+ -- LVDS2V5East5PxSIO : inout std_logic;
+ -- LVDS2V5East5NxSIO : inout std_logic;
+ -- LVDS2V5East6PxSIO : inout std_logic;
+ -- LVDS2V5East6NxSIO : inout std_logic;
+ -- LVDS2V5East7PxSIO : inout std_logic;
+ -- LVDS2V5East7NxSIO : inout std_logic;
+ -- West
+ -- LVDS2V5West0PxSIO : inout std_logic;
+ -- LVDS2V5West0NxSIO : inout std_logic;
+ -- LVDS2V5West1PxSIO : inout std_logic;
+ -- LVDS2V5West1NxSIO : inout std_logic;
+ -- LVDS2V5West2PxSIO : inout std_logic;
+ -- LVDS2V5West2NxSIO : inout std_logic;
+ -- LVDS2V5West3PxSIO : inout std_logic;
+ -- LVDS2V5West3NxSIO : inout std_logic;
+ -- LVDS2V5West4PxSIO : inout std_logic;
+ -- LVDS2V5West4NxSIO : inout std_logic;
+ -- LVDS2V5West5PxSIO : inout std_logic;
+ -- LVDS2V5West5NxSIO : inout std_logic;
+ -- LVDS2V5West6PxSIO : inout std_logic;
+ -- LVDS2V5West6NxSIO : inout std_logic;
+ -- LVDS2V5West7PxSIO : inout std_logic;
+ -- LVDS2V5West7NxSIO : inout std_logic;
+ -- LVDS links towards top-bottom connectors
+ -- Top
+ -- LVDS2V5Top0PxSIO : inout std_logic;
+ -- LVDS2V5Top0NxSIO : inout std_logic;
+ -- LVDS2V5Top1PxSIO : inout std_logic;
+ -- LVDS2V5Top1NxSIO : inout std_logic;
+ -- LVDS2V5Top2PxSIO : inout std_logic;
+ -- LVDS2V5Top2NxSIO : inout std_logic;
+ -- LVDS2V5Top3PxSIO : inout std_logic;
+ -- LVDS2V5Top3NxSIO : inout std_logic;
+ -- LVDS2V5Top4PxSIO : inout std_logic;
+ -- LVDS2V5Top4NxSIO : inout std_logic;
+ -- LVDS2V5Top5PxSIO : inout std_logic;
+ -- LVDS2V5Top5NxSIO : inout std_logic;
+ -- LVDS2V5Top6PxSIO : inout std_logic;
+ -- LVDS2V5Top6NxSIO : inout std_logic;
+ -- LVDS2V5Top7PxSIO : inout std_logic;
+ -- LVDS2V5Top7NxSIO : inout std_logic;
+ -- Bottom
+ -- LVDS2V5Bottom0PxSIO : inout std_logic;
+ -- LVDS2V5Bottom0NxSIO : inout std_logic;
+ -- LVDS2V5Bottom1PxSIO : inout std_logic;
+ -- LVDS2V5Bottom1NxSIO : inout std_logic;
+ -- LVDS2V5Bottom2PxSIO : inout std_logic;
+ -- LVDS2V5Bottom2NxSIO : inout std_logic;
+ -- LVDS2V5Bottom3PxSIO : inout std_logic;
+ -- LVDS2V5Bottom3NxSIO : inout std_logic;
+ -- LVDS2V5Bottom4PxSIO : inout std_logic;
+ -- LVDS2V5Bottom4NxSIO : inout std_logic;
+ -- LVDS2V5Bottom5PxSIO : inout std_logic;
+ -- LVDS2V5Bottom5NxSIO : inout std_logic;
+ -- LVDS2V5Bottom6PxSIO : inout std_logic;
+ -- LVDS2V5Bottom6NxSIO : inout std_logic;
+ -- LVDS2V5Bottom7PxSIO : inout std_logic;
+ -- LVDS2V5Bottom7NxSIO : inout std_logic;
+ -- RGB LEDs
+ Led12V5RxSO : out std_logic;
+ Led12V5GxSO : out std_logic;
+ Led12V5BxSO : out std_logic;
+ Led22V5RxSO : out std_logic;
+ Led22V5GxSO : out std_logic;
+ Led22V5BxSO : out std_logic;
+ -- Self reset (connected to PS_SRSTB)
+ SelfRstxRNO : out std_logic);
+ -- Clocks from PLLs (connected to MRCC pins)
+ -- Local
+ -- PLLClk2V5LocalPxCI : in std_logic;
+ -- PLLClk2V5LocalNxCI : in std_logic;
+ -- -- North
+ -- PLLClk2V5NorthPxCI : in std_logic;
+ -- PLLClk2V5NorthNxCI : in std_logic;
+ -- -- South
+ -- PLLClk2V5SouthPxCI : in std_logic;
+ -- PLLClk2V5SouthNxCI : in std_logic;
+ -- -- Top
+ -- PLLClk2V5TopxCI : in std_logic; -- Single-ended
+ -- -- Bottom
+ -- PLLClk2V5BottomxCI : in std_logic; -- Single-ended
+ -- -- Clocks to/from neighbours
+ -- -- North
+ -- Clk2V5NorthPxCI : in std_logic;
+ -- Clk2V5NorthNxCI : in std_logic;
+ -- Clk2V5NorthPxCO : out std_logic;
+ -- Clk2V5NorthNxCO : out std_logic;
+ -- -- South
+ -- Clk2V5SouthPxCI : in std_logic;
+ -- Clk2V5SouthNxCI : in std_logic;
+ -- Clk2V5SouthPxCO : out std_logic;
+ -- Clk2V5SouthNxCO : out std_logic;
+ -- -- East
+ -- Clk2V5EastPxCI : in std_logic;
+ -- Clk2V5EastNxCI : in std_logic;
+ -- Clk2V5EastPxCO : out std_logic;
+ -- Clk2V5EastNxCO : out std_logic;
+ -- -- West
+ -- Clk2V5WestPxCI : in std_logic;
+ -- Clk2V5WestNxCI : in std_logic;
+ -- Clk2V5WestPxCO : out std_logic;
+ -- Clk2V5WestNxCO : out std_logic;
+ -- -- Top
+ -- Clk2V5TopPxCI : in std_logic;
+ -- Clk2V5TopNxCI : in std_logic;
+ -- Clk2V5TopPxCO : out std_logic;
+ -- Clk2V5TopNxCO : out std_logic;
+ -- -- Bottom
+ -- Clk2V5BottomPxCI : in std_logic;
+ -- Clk2V5BottomNxCI : in std_logic;
+ -- Clk2V5BottomPxCO : out std_logic;
+ -- Clk2V5BottomNxCO : out std_logic;
+ -- -- Recovery
+ -- Clk2V5RecoveryPxCO : out std_logic;
+ -- Clk2V5RecoveryNxCO : out std_logic);
+
+end scalp_mipi;
+
+architecture arch of scalp_mipi is
+
+ -- Constantes
+ -- constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
+ constant C_AXI_ADDR_SIZE : integer range 0 to 32 := 12;
+
+ -- Signals
+ -- Clocks
+ -- Processing system clock
+ signal PSSysClkxC : std_logic := '0';
+ -- Resets
+ -- Processing system reset
+ signal PSSysResetxR : std_logic := '0';
+ -- Scalp Axi Lite interface and IRQ
+ signal InterruptxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
+ -- Zynq Reg Bank
+ signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- RGB Leds
+ signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ -- Clocks
+ attribute keep of PSSysClkxC : signal is "true";
+
+begin
+
+ ProcessingSystemxB : block is
+ begin -- block ProcessingSystemxB
+
+ ZynqxI : entity work.scalp_mipi_zynqps_wrapper
+ port map (
+ -- Processor interface
+ FIXED_IO_ps_clk => PSClkxCIO,
+ FIXED_IO_ps_porb => PSPorxSNIO,
+ FIXED_IO_ps_srstb => PSSRstxRNIO,
+ FclkClk0xCO => PSSysClkxC,
+ FclkReset0xRO => PSSysResetxR,
+ -- DDR interface
+ DDR_addr => DDRAddrxDIO,
+ DDR_ba => DDRBankAddrxDIO,
+ DDR_cas_n => DDRCasNxSIO,
+ DDR_ck_n => DDRClkNxCIO,
+ DDR_ck_p => DDRClkPxCIO,
+ DDR_cke => DDRCkexSIO,
+ DDR_cs_n => DDRCsNxSIO,
+ DDR_dm => DDRDmxDIO,
+ DDR_dq => DDRDqxDIO,
+ DDR_dqs_n => DDRDqsNxDIO,
+ DDR_dqs_p => DDRDqsPxDIO,
+ DDR_odt => DDROdtxSIO,
+ DDR_ras_n => DDRRasNxSIO,
+ DDR_reset_n => DDRDRstxRNIO,
+ DDR_we_n => DDRWexSNIO,
+ FIXED_IO_ddr_vrn => DDRVrNxSIO,
+ FIXED_IO_ddr_vrp => DDRVrPxSIO,
+ -- USB interface
+ Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
+ -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+ -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+ Spi1MOSIxSO => Pll2V5DatauWirexSO,
+ Spi1SSxSO => Pll2V5LEuWirexSO,
+ Spi1SclkxCO => Pll2V5ClkuWirexCO,
+ -- MIO
+ FIXED_IO_mio => MIOxDIO,
+ -- Scalp Axi Lite interface and IRQ
+ InterruptxSI => InterruptxS,
+ RdAddrxDO => RdAddrxD,
+ RdDataxDI => RdDataxD,
+ RdValidxSO => RdValidxS,
+ WrAddrxDO => WrAddrxD,
+ WrDataxDO => WrDataxD,
+ WrValidxSO => WrValidxS,
+ RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD);
+
+ end block ProcessingSystemxB;
+
+ ProgrammableLogicxB : block is
+ begin -- block ProgrammableLogicxB
+
+ EntityIOxB : block is
+ begin
+
+ Led12V5RxAS : Led12V5RxSO <= RgbLedsCtrlPortxD(0);
+ Led12V5GxAS : Led12V5GxSO <= RgbLedsCtrlPortxD(1);
+ Led12V5BxAS : Led12V5BxSO <= RgbLedsCtrlPortxD(2);
+ Led22V5RxAS : Led22V5RxSO <= RgbLedsCtrlPortxD(3);
+ Led22V5GxAS : Led22V5GxSO <= RgbLedsCtrlPortxD(4);
+ Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
+
+ end block EntityIOxB;
+
+
+ ZynqRegBankxB : block is
+ begin -- block ZynqRegBankxB
+
+ RegBankxB : block is
+ begin -- block RegBankxB
+
+ WriteRegPortxP : process (CtrlRegPortxDP, WrAddrxD, WrDataxD,
+ WrValidxS) is
+ begin -- process WriteRegPortxP
+ CtrlRegPortxDN <= CtrlRegPortxDP;
+
+ if WrValidxS = '1' then
+ case WrAddrxD is
+ -- Ctrl
+ -- North
+ when x"000" => CtrlRegPortxDN <= WrDataxD;
+ when x"004" => CtrlRegPortxDN <= CtrlRegPortxDP or WrDataxD;
+ when x"008" => CtrlRegPortxDN <= CtrlRegPortxDP and not WrDataxD;
+ when others => null;
+ end case;
+ end if;
+ end process WriteRegPortxP;
+
+ ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
+ begin -- process ReadRegPortxP
+ if PSSysResetxR = '1' then
+ RdDataxD <= (others => '0');
+ elsif rising_edge(PSSysClkxC) then
+ RdDataxD <= (others => '0');
+
+ if RdValidxS = '1' then
+ case RdAddrxD is
+ when x"000" => RdDataxD <= CtrlRegPortxDP;
+ when others => RdDataxD <= x"aabbccdd";
+ end case;
+ end if;
+ end if;
+ end process ReadRegPortxP;
+
+ RegBankxP : process (PSSysClkxC, PSSysResetxR) is
+ begin -- process RegBankxP
+ if PSSysResetxR = '1' then
+ CtrlRegPortxDP <= (others => '0');
+ elsif rising_edge(PSSysClkxC) then
+ CtrlRegPortxDP <= CtrlRegPortxDN;
+ end if;
+ end process RegBankxP;
+
+ end block RegBankxB;
+
+ end block ZynqRegBankxB;
+
+ end block ProgrammableLogicxB;
+
+end arch;
diff --git a/designs/vivado/scalp_mipi/2020.2/src/ipi_tcl/scalp_mipi_ipi.tcl b/designs/vivado/scalp_mipi/2020.2/src/ipi_tcl/scalp_mipi_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3771f5c2d6d66849d6116395f1e28e0c417f8971
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/ipi_tcl/scalp_mipi_ipi.tcl
@@ -0,0 +1 @@
+source "../../../../../../soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl"
\ No newline at end of file
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sim/tb_scalp_mipi.vhd b/designs/vivado/scalp_mipi/2020.2/src/sim/tb_scalp_mipi.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..257ffd0b8ddfb5871ce5f9505e8191fb0ae0e71a
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sim/tb_scalp_mipi.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+--
+-- Module Name: tb_scalp_mipi - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_mipi
+--
+-- Last update: 2021-04-28 16:21:16
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_mipi is
+end tb_scalp_mipi;
+
+
+architecture behavioral of tb_scalp_mipi is
+
+begin
+
+end behavioral;
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1841a25d606922b89f8292c6a44a0f9b380fbbbe
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/clean_sdk_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/clean_sdk_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..250d83e53a2210cfb88365bca37ba1ca2d0800ae
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/clean_sdk_scalp_mipi.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup Vitis SDK workspace directory
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Cleanup SDK workspace directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ./xrc.log/ 2> /dev/null
+rm -rf ./.Xil/ 2> /dev/null
+
+# Remove generated workspace directory
+rm -rf ${PRJ_DIR}/vitis_workspace/ 2> /dev/null
+
+echo "> Done"
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/gen_sw_apps_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/gen_sw_apps_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f7c2e1c4c184eca8abfa4567b43ef6c0e7a8253e
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/gen_sw_apps_scalp_mipi.sh
@@ -0,0 +1,26 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate Vitis workspace for software applications
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Generate Vitis workspace software applications"
+xsct gen_sw_apps_scalp_mipi.tcl
+echo "> Done"
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/gen_sw_apps_scalp_mipi.tcl b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/gen_sw_apps_scalp_mipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e9af091b063056b60a2a5143bb44103d497fc6e7
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/gen_sw_apps_scalp_mipi.tcl
@@ -0,0 +1,101 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vitis workspace
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+#
+# Include files
+#
+source utils.tcl
+
+#
+# Procedures
+#
+# Create source directories and import application source files
+proc import_app_sources {prj_workspace app_name app_src_path} {
+ puts "Import application source file into workspace..."
+
+ # Create workspace application directory
+ set ws_app_src_dir "${prj_workspace}/${app_name}/src"
+ file mkdir "${ws_app_src_dir}"
+ print_status "Create app directory into workspace: ${ws_app_src_dir}" "OK"
+
+ foreach f [glob -nocomplain -directory ${app_src_path} *] {
+ file copy -force $f ${ws_app_src_dir}
+ print_status "Copy $f into ${ws_app_src_dir}" "OK"
+ }
+}
+
+#
+# Generate workspace
+#
+
+# Set variables
+set pwd [pwd]
+
+set prj_workspace "../vitis_workspace"
+
+set prj_platform "scalp_mipi"
+set prj_desc "Zynq platform project"
+set prj_xsa "${pwd}/../hw_export/scalp_mipi.xsa"
+
+# Generate default application for APU0
+# APU0 - Cortex-A9
+set apu_0_prj_proc "ps7_cortexa9_0"
+set apu_0_prj_os "standalone"
+
+set apu_0_domain_name "standalone_apu0_domain"
+
+set apu_0_app_sysprj "scalp_mipi_app_system"
+set apu_0_app_template "Empty Application"
+
+set apu_0_app_name "scalp_mipi_app"
+set apu_0_app_src_dir "${pwd}/../sw_apps/scalp_mipi_app/src"
+
+# Create the workspace
+file mkdir $prj_workspace
+setws $prj_workspace
+
+# Create the platform from the XSA (Xilinx Shell Archive) file
+platform create -name $prj_platform -desc $prj_desc -hw $prj_xsa
+
+# Create a domain for the APU (Core_0)
+domain create -name ${apu_0_domain_name} -proc ${apu_0_prj_proc} -os ${apu_0_prj_os}
+
+# Setup the APU_0 domain
+domain active ${apu_0_domain_name}
+# Example of how to add libraries to the BSP
+#bsp setlib -name xilfpga
+#bsp setlib -name xilsecure
+
+# Build the platform
+platform active ${prj_platform}
+platform generate
+
+# Build the APU_0 domain
+domain active ${apu_0_domain_name}
+# Create an application for APU Core_0
+app create -name ${apu_0_app_name} -sysproj ${apu_0_app_sysprj} -platform ${prj_platform} -domain ${apu_0_domain_name} -proc ${apu_0_prj_proc} -os ${apu_0_prj_os} -template ${apu_0_app_template} -lang {c}
+# Add application sources
+# Sources are copied into the workspace directory
+import_app_sources ${prj_workspace} ${apu_0_app_name} ${apu_0_app_src_dir}
+# Set includes path
+app config -name ${apu_0_app_name} -add include-path {"${workspace_loc:/${ProjName}/src/inc}"}
+# Build application
+app build ${apu_0_app_name}
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/open_sdk_scalp_mipi.sh b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/open_sdk_scalp_mipi.sh
new file mode 100755
index 0000000000000000000000000000000000000000..66bd22c0c5e647ac7ce1bc1873b490dacd7f32e3
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/open_sdk_scalp_mipi.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open the Vitis workspace
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+echo "> Open Vitis workspace..."
+vitis -workspace ../vitis_workspace
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/utils.tcl b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6f8668ee4211266fb403b4c0629a42b08e5c90ca
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Laurent Gantel <laurent.gantel@hesge.ch>
+#
+# Project Name: t01_demo_platform
+# Target Device: em.avnet.com:zed:part0:1.4 xc7z020clg484-1
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2019-12-09 09:06:01
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/setup.sh b/designs/vivado/scalp_mipi/2020.2/src/sw/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..a76a7aedd9d7859344537fd56fe1d116ec811971
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/setup.sh
@@ -0,0 +1,27 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vitis workspace management scripts
+#
+# Last update: 2021-04-28 16:21:16
+#
+##################################################################################
+
+# Create aliases
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_mipi.sh && cd ..'
+# TODO: Not supported yet
+#alias load_sw_app='cd .scripts && ./load_sw_app_scalp_mipi.sh && cd ..'
+alias open_sdk='cd .scripts && ./open_sdk_scalp_mipi.sh && cd ..'
+alias clean_sdk='cd .scripts && ./clean_sdk_scalp_mipi.sh && cd ..'
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/sw_apps/scalp_mipi_app/src/inc/scalp_mipi_app.h b/designs/vivado/scalp_mipi/2020.2/src/sw/sw_apps/scalp_mipi_app/src/inc/scalp_mipi_app.h
new file mode 100644
index 0000000000000000000000000000000000000000..4166d143f52b5063008eeb58fcc26dc5dd7cf3d6
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/sw_apps/scalp_mipi_app/src/inc/scalp_mipi_app.h
@@ -0,0 +1,48 @@
+/*-----------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+-------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+--
+-- File Name: scalp_mipi_app.h
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Software application
+--
+-- Last update: 2021-04-28 16:21:16
+--
+-----------------------------------------------------------------------------*/
+
+#ifndef SCALP_MIPI_APP_H
+#define SCALP_MIPI_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------
+// Constants
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Types
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Functions
+//--------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SCALP_MIPI_APP_H
diff --git a/designs/vivado/scalp_mipi/2020.2/src/sw/sw_apps/scalp_mipi_app/src/scalp_mipi_app.c b/designs/vivado/scalp_mipi/2020.2/src/sw/sw_apps/scalp_mipi_app/src/scalp_mipi_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..0019fc2df7fe5db695e3820d80440e2c0fe44f47
--- /dev/null
+++ b/designs/vivado/scalp_mipi/2020.2/src/sw/sw_apps/scalp_mipi_app/src/scalp_mipi_app.c
@@ -0,0 +1,60 @@
+/*-----------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+-------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+--
+-- File Name: scalp_mipi_app.c
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Software application
+--
+-- Last update: 2021-04-28 16:21:16
+--
+-----------------------------------------------------------------------------*/
+
+/* Xilinx includes. */
+#include "xil_printf.h"
+#include "xparameters.h"
+
+
+/*----------------------------------------------------------------
+// Constants
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Variables
+//--------------------------------------------------------------*/
+/** @brief Software version */
+const char * APP_VERSION = "0.0.1";
+
+
+/*----------------------------------------------------------------
+// Static Functions
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Functions
+//--------------------------------------------------------------*/
+
+/**
+ * @brief Main entry point
+ */
+int main( void )
+{
+
+ //----------------------------------------------------------------
+ xil_printf( "\r\n-- scalp_mipi app v%s\r\n", APP_VERSION);
+ xil_printf("-- %s - %s\r\n", __DATE__,__TIME__);
+
+ // Endless loop
+ for( ;; );
+}
diff --git a/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9a4b0154ff755759f33112d59025ece45794498f
--- /dev/null
+++ b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
@@ -0,0 +1,116 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+--
+-- Module Name: scalp_mipi_zynqps_wrapper - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_mipi_zynqps_wrapper
+--
+-- Last update: 2021-04-28 16:06:01
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scalp_mipi_zynqps_wrapper is
+
+ port (
+ -- Processor interface
+ FIXED_IO_ps_clk : inout std_logic;
+ FIXED_IO_ps_porb : inout std_logic;
+ FIXED_IO_ps_srstb : inout std_logic;
+ FclkClk0xCO : out std_logic;
+ FclkReset0xRO : out std_logic;
+ -- DDR interface
+ DDR_addr : inout std_logic_vector (14 downto 0);
+ DDR_ba : inout std_logic_vector (2 downto 0);
+ DDR_cas_n : inout std_logic;
+ DDR_ck_n : inout std_logic;
+ DDR_ck_p : inout std_logic;
+ DDR_cke : inout std_logic;
+ DDR_cs_n : inout std_logic;
+ DDR_dm : inout std_logic_vector (3 downto 0);
+ DDR_dq : inout std_logic_vector (31 downto 0);
+ DDR_dqs_n : inout std_logic_vector (3 downto 0);
+ DDR_dqs_p : inout std_logic_vector (3 downto 0);
+ DDR_odt : inout std_logic;
+ DDR_ras_n : inout std_logic;
+ DDR_reset_n : inout std_logic;
+ DDR_we_n : inout std_logic;
+ FIXED_IO_ddr_vrn : inout std_logic;
+ FIXED_IO_ddr_vrp : inout std_logic;
+ -- USB interface
+ Usb0VBusPwrFaultxSI : in std_logic;
+ -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+ -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+ Spi1MOSIxSO : out std_logic;
+ Spi1SSxSO : out std_logic;
+ Spi1SclkxCO : out std_logic;
+ -- MIO
+ FIXED_IO_mio : inout std_logic_vector (53 downto 0);
+ -- Scalp Axi Lite interface and IRQ
+ InterruptxSI : in std_logic;
+ RdAddrxDO : out std_logic_vector (11 downto 0);
+ RdDataxDI : in std_logic_vector (31 downto 0);
+ RdValidxSO : out std_logic;
+ WrAddrxDO : out std_logic_vector (11 downto 0);
+ WrDataxDO : out std_logic_vector (31 downto 0);
+ WrValidxSO : out std_logic;
+ RgbLedsCtrlPortxDO : out std_logic_vector (31 downto 0));
+
+end scalp_mipi_zynqps_wrapper;
+
+architecture arch of scalp_mipi_zynqps_wrapper is
+
+begin
+
+ ScalpZynqPSxI : entity work.scalp_mipi_zynqps
+ port map (
+ DDR_addr => DDR_addr,
+ DDR_ba => DDR_ba,
+ DDR_cas_n => DDR_cas_n,
+ DDR_ck_n => DDR_ck_n,
+ DDR_ck_p => DDR_ck_p,
+ DDR_cke => DDR_cke,
+ DDR_cs_n => DDR_cs_n,
+ DDR_dm => DDR_dm,
+ DDR_dq => DDR_dq,
+ DDR_dqs_n => DDR_dqs_n,
+ DDR_dqs_p => DDR_dqs_p,
+ DDR_odt => DDR_odt,
+ DDR_ras_n => DDR_ras_n,
+ DDR_reset_n => DDR_reset_n,
+ DDR_we_n => DDR_we_n,
+ FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+ FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+ FIXED_IO_mio => FIXED_IO_mio,
+ FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+ FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+ FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+ FclkClk0xCO => FclkClk0xCO,
+ FclkReset0xRO(0) => FclkReset0xRO,
+ Spi1MOSIxSO => Spi1MOSIxSO,
+ Spi1SSxSO => Spi1SSxSO,
+ Spi1SclkxCO => Spi1SclkxCO,
+ Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
+ InterruptxSI => InterruptxSI,
+ RdAddrxDO => RdAddrxDO,
+ RdDataxDI => RdDataxDI,
+ RdValidxSO => RdValidxSO,
+ WrAddrxDO => WrAddrxDO,
+ WrDataxDO => WrDataxDO,
+ WrValidxSO => WrValidxSO,
+ RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO);
+
+end arch;
diff --git a/soc/hw/scalp_mipi_zynqps/src/sim/tb_scalp_mipi_zynqps.vhd b/soc/hw/scalp_mipi_zynqps/src/sim/tb_scalp_mipi_zynqps.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8247e0a96c9cdcc944056f4621f64923dac854b0
--- /dev/null
+++ b/soc/hw/scalp_mipi_zynqps/src/sim/tb_scalp_mipi_zynqps.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+--
+-- Module Name: tb_scalp_mipi_zynqps - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_mipi_zynqps
+--
+-- Last update: 2021-04-28 16:06:01
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_mipi_zynqps is
+end tb_scalp_mipi_zynqps;
+
+
+architecture behavioral of tb_scalp_mipi_zynqps is
+
+begin
+
+end behavioral;
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.gitignore b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..8886325c93671e3c6f928dd9a69ea93268d4bfbb
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.gitignore
@@ -0,0 +1,23 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_mipi_zynqps
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/.prompt_colors.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e170a076c755b8feca68885ae532debea37ba21f
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/clean_prj_scalp_mipi_zynqps.sh b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/clean_prj_scalp_mipi_zynqps.sh
new file mode 100755
index 0000000000000000000000000000000000000000..47fb627045bcfab233a76b184d2d1f3ed7905ac2
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/clean_prj_scalp_mipi_zynqps.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_mipi_zynqps/ 2> /dev/null
+
+echo "> Done"
+
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/create_prj_scalp_mipi_zynqps.sh b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/create_prj_scalp_mipi_zynqps.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7d1b80b53aba6c43896e4b77e54800355939a329
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/create_prj_scalp_mipi_zynqps.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_mipi_zynqps.tcl -notrace
+echo "> Done"
+
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/create_prj_scalp_mipi_zynqps.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/create_prj_scalp_mipi_zynqps.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9a476d6ac416864beeae4722068e4a84905ff949
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/create_prj_scalp_mipi_zynqps.tcl
@@ -0,0 +1,154 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_mipi_zynqps'
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_mipi_zynqps"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../soc/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set hdl_src_dir "${src_dir}/hdl"
+ set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ set hdl_src_dir "${comp_src_dir}/hdl"
+ set sim_src_dir "${comp_src_dir}/sim"
+}
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+ add_files -norecurse $hdl_src_file_list
+} else {
+ print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
+ # add IPs source files
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # add IPs source files
+
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+ add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+ update_compile_order -fileset sim_1
+ print_status "Add simulation sources" "OK"
+} else {
+ print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for simulation sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/open_prj_scalp_mipi_zynqps.sh b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/open_prj_scalp_mipi_zynqps.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b3770fc7bcbeb3cc09fd470b66d2a3b02fe83b29
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/open_prj_scalp_mipi_zynqps.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_mipi_zynqps/scalp_mipi_zynqps.xpr
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/utils.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..78bab48053758017851e8a3ebfe2a533cec13b31
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/setup.sh b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b8d479579792ef128417403c3af6f7a62fcef778
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/lin64/setup.sh
@@ -0,0 +1,28 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Orphee Antoniadis <orphee.antoniadis@hesge.ch>
+#
+# Project Name: scalp_mipi_zynqps
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-04-28 16:06:01
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_mipi_zynqps.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_mipi_zynqps.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_mipi_zynqps.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_mipi_zynqps.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_mipi_zynqps.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_mipi_zynqps.sh && cd ..'
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7ae4082dd5accbd40347b063ee64462e82ef18d7
--- /dev/null
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
@@ -0,0 +1,773 @@
+
+################################################################
+# This is a generated script based on design: scalp_mipi_zynqps
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source scalp_mipi_zynqps_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xc7z015clg485-2
+ set_property BOARD_PART hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name scalp_mipi_zynqps
+
+# This script was generated for a remote BD. To create a non-remote design,
+# change the variable <run_remote_bd_flow> to <0>.
+
+set run_remote_bd_flow 1
+if { $run_remote_bd_flow == 1 } {
+ # Set the reference directory for source file relative paths (by default
+ # the value is script directory path)
+ set origin_dir .
+
+ # Use origin directory path location variable, if specified in the tcl shell
+ if { [info exists ::origin_dir_loc] } {
+ set origin_dir $::origin_dir_loc
+ }
+
+ set str_bd_folder [file normalize ${origin_dir}]
+ set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
+
+ # Check if remote design exists on disk
+ if { [file exists $str_bd_filepath ] == 1 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
+ common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
+ common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+
+ return 1
+ }
+
+ # Check if design exists in memory
+ set list_existing_designs [get_bd_designs -quiet $design_name]
+ if { $list_existing_designs ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+ common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+ return 1
+ }
+
+ # Check if design exists on disk within project
+ set list_existing_designs [get_files -quiet */${design_name}.bd]
+ if { $list_existing_designs ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
+ $list_existing_designs"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+ common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+ return 1
+ }
+
+ # Now can create the remote BD
+ # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
+ create_bd_design -dir $str_bd_folder $design_name
+} else {
+
+ # Create regular design
+ if { [catch {create_bd_design $design_name} errmsg] } {
+ common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
+
+ return 1
+ }
+}
+
+current_bd_design $design_name
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+xilinx.com:ip:xlconstant:1.1\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:proc_sys_reset:5.0\
+hepia.hesge.ch:user:scalp_axi4lite:1.2\
+hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\
+xilinx.com:ip:system_ila:1.1\
+xilinx.com:ip:util_vector_logic:2.0\
+xilinx.com:ip:vio:3.0\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+ set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+
+ set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+
+ # Create ports
+ set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $FclkClk0xCO
+ set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
+ set InterruptxSI [ create_bd_port -dir I -type intr InterruptxSI ]
+ set RdAddrxDO [ create_bd_port -dir O -from 11 -to 0 RdAddrxDO ]
+ set RdDataxDI [ create_bd_port -dir I -from 31 -to 0 RdDataxDI ]
+ set RdValidxSO [ create_bd_port -dir O RdValidxSO ]
+ set RgbLedsCtrlPortxDO [ create_bd_port -dir O -from 31 -to 0 RgbLedsCtrlPortxDO ]
+ set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
+ set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
+ set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
+ set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
+ set WrAddrxDO [ create_bd_port -dir O -from 11 -to 0 WrAddrxDO ]
+ set WrDataxDO [ create_bd_port -dir O -from 31 -to 0 WrDataxDO ]
+ set WrValidxSO [ create_bd_port -dir O WrValidxSO ]
+
+ # Create instance: gnd_constant, and set properties
+ set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $gnd_constant
+
+ # Create instance: irq_xlconcat, and set properties
+ set irq_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 irq_xlconcat ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {1} \
+ ] $irq_xlconcat
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {750.000000} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.204082} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {194.444443} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {134.615387} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {159.090912} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {750} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {30} \
+ CONFIG.PCW_CAN1_CAN1_IO {MIO 52 .. 53} \
+ CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
+ CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {18} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_CAN_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_CLK0_FREQ {125000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1500.000} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {49} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {20} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1000.000} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x0FFFFFFF} \
+ CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+ CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
+ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {14} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+ CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET_RESET_ENABLE {1} \
+ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_EN_CAN1 {1} \
+ CONFIG.PCW_EN_EMIO_CAN1 {0} \
+ CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_ENET0 {0} \
+ CONFIG.PCW_EN_EMIO_I2C0 {0} \
+ CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_SPI0 {0} \
+ CONFIG.PCW_EN_EMIO_SPI1 {1} \
+ CONFIG.PCW_EN_EMIO_UART0 {0} \
+ CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+ CONFIG.PCW_EN_ENET0 {1} \
+ CONFIG.PCW_EN_GPIO {1} \
+ CONFIG.PCW_EN_I2C0 {1} \
+ CONFIG.PCW_EN_QSPI {1} \
+ CONFIG.PCW_EN_SDIO1 {1} \
+ CONFIG.PCW_EN_SPI0 {1} \
+ CONFIG.PCW_EN_SPI1 {1} \
+ CONFIG.PCW_EN_UART0 {1} \
+ CONFIG.PCW_EN_UART1 {1} \
+ CONFIG.PCW_EN_USB0 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {7} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {125} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+ CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+ CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
+ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_I2C_RESET_ENABLE {1} \
+ CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {35} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1750.000} \
+ CONFIG.PCW_IRQ_F2P_INTR {1} \
+ CONFIG.PCW_MIO_0_DIRECTION {inout} \
+ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_0_PULLUP {enabled} \
+ CONFIG.PCW_MIO_0_SLEW {slow} \
+ CONFIG.PCW_MIO_10_DIRECTION {inout} \
+ CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_10_PULLUP {enabled} \
+ CONFIG.PCW_MIO_10_SLEW {slow} \
+ CONFIG.PCW_MIO_11_DIRECTION {inout} \
+ CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_11_PULLUP {enabled} \
+ CONFIG.PCW_MIO_11_SLEW {slow} \
+ CONFIG.PCW_MIO_12_DIRECTION {inout} \
+ CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_12_PULLUP {enabled} \
+ CONFIG.PCW_MIO_12_SLEW {slow} \
+ CONFIG.PCW_MIO_13_DIRECTION {inout} \
+ CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_13_PULLUP {enabled} \
+ CONFIG.PCW_MIO_13_SLEW {slow} \
+ CONFIG.PCW_MIO_14_DIRECTION {inout} \
+ CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_14_PULLUP {enabled} \
+ CONFIG.PCW_MIO_14_SLEW {slow} \
+ CONFIG.PCW_MIO_15_DIRECTION {inout} \
+ CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_15_PULLUP {enabled} \
+ CONFIG.PCW_MIO_15_SLEW {slow} \
+ CONFIG.PCW_MIO_16_DIRECTION {out} \
+ CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_16_PULLUP {enabled} \
+ CONFIG.PCW_MIO_16_SLEW {slow} \
+ CONFIG.PCW_MIO_17_DIRECTION {out} \
+ CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_17_PULLUP {enabled} \
+ CONFIG.PCW_MIO_17_SLEW {slow} \
+ CONFIG.PCW_MIO_18_DIRECTION {out} \
+ CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_18_PULLUP {enabled} \
+ CONFIG.PCW_MIO_18_SLEW {slow} \
+ CONFIG.PCW_MIO_19_DIRECTION {out} \
+ CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_19_PULLUP {enabled} \
+ CONFIG.PCW_MIO_19_SLEW {slow} \
+ CONFIG.PCW_MIO_1_DIRECTION {out} \
+ CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_1_PULLUP {enabled} \
+ CONFIG.PCW_MIO_1_SLEW {slow} \
+ CONFIG.PCW_MIO_20_DIRECTION {out} \
+ CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_20_PULLUP {enabled} \
+ CONFIG.PCW_MIO_20_SLEW {slow} \
+ CONFIG.PCW_MIO_21_DIRECTION {out} \
+ CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_21_PULLUP {enabled} \
+ CONFIG.PCW_MIO_21_SLEW {slow} \
+ CONFIG.PCW_MIO_22_DIRECTION {in} \
+ CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_22_PULLUP {enabled} \
+ CONFIG.PCW_MIO_22_SLEW {slow} \
+ CONFIG.PCW_MIO_23_DIRECTION {in} \
+ CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_23_PULLUP {enabled} \
+ CONFIG.PCW_MIO_23_SLEW {slow} \
+ CONFIG.PCW_MIO_24_DIRECTION {in} \
+ CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_24_PULLUP {enabled} \
+ CONFIG.PCW_MIO_24_SLEW {slow} \
+ CONFIG.PCW_MIO_25_DIRECTION {in} \
+ CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_25_PULLUP {enabled} \
+ CONFIG.PCW_MIO_25_SLEW {slow} \
+ CONFIG.PCW_MIO_26_DIRECTION {in} \
+ CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_26_PULLUP {enabled} \
+ CONFIG.PCW_MIO_26_SLEW {slow} \
+ CONFIG.PCW_MIO_27_DIRECTION {in} \
+ CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_27_PULLUP {enabled} \
+ CONFIG.PCW_MIO_27_SLEW {slow} \
+ CONFIG.PCW_MIO_28_DIRECTION {inout} \
+ CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_28_PULLUP {enabled} \
+ CONFIG.PCW_MIO_28_SLEW {slow} \
+ CONFIG.PCW_MIO_29_DIRECTION {in} \
+ CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_29_PULLUP {enabled} \
+ CONFIG.PCW_MIO_29_SLEW {slow} \
+ CONFIG.PCW_MIO_2_DIRECTION {inout} \
+ CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_2_PULLUP {disabled} \
+ CONFIG.PCW_MIO_2_SLEW {slow} \
+ CONFIG.PCW_MIO_30_DIRECTION {out} \
+ CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_30_PULLUP {enabled} \
+ CONFIG.PCW_MIO_30_SLEW {slow} \
+ CONFIG.PCW_MIO_31_DIRECTION {in} \
+ CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_31_PULLUP {enabled} \
+ CONFIG.PCW_MIO_31_SLEW {slow} \
+ CONFIG.PCW_MIO_32_DIRECTION {inout} \
+ CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_32_PULLUP {enabled} \
+ CONFIG.PCW_MIO_32_SLEW {slow} \
+ CONFIG.PCW_MIO_33_DIRECTION {inout} \
+ CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_33_PULLUP {enabled} \
+ CONFIG.PCW_MIO_33_SLEW {slow} \
+ CONFIG.PCW_MIO_34_DIRECTION {inout} \
+ CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_34_PULLUP {enabled} \
+ CONFIG.PCW_MIO_34_SLEW {slow} \
+ CONFIG.PCW_MIO_35_DIRECTION {inout} \
+ CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_35_PULLUP {enabled} \
+ CONFIG.PCW_MIO_35_SLEW {slow} \
+ CONFIG.PCW_MIO_36_DIRECTION {in} \
+ CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_36_PULLUP {enabled} \
+ CONFIG.PCW_MIO_36_SLEW {slow} \
+ CONFIG.PCW_MIO_37_DIRECTION {inout} \
+ CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_37_PULLUP {enabled} \
+ CONFIG.PCW_MIO_37_SLEW {slow} \
+ CONFIG.PCW_MIO_38_DIRECTION {inout} \
+ CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_38_PULLUP {enabled} \
+ CONFIG.PCW_MIO_38_SLEW {slow} \
+ CONFIG.PCW_MIO_39_DIRECTION {inout} \
+ CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_39_PULLUP {enabled} \
+ CONFIG.PCW_MIO_39_SLEW {slow} \
+ CONFIG.PCW_MIO_3_DIRECTION {inout} \
+ CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_3_PULLUP {disabled} \
+ CONFIG.PCW_MIO_3_SLEW {slow} \
+ CONFIG.PCW_MIO_40_DIRECTION {inout} \
+ CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_40_PULLUP {enabled} \
+ CONFIG.PCW_MIO_40_SLEW {slow} \
+ CONFIG.PCW_MIO_41_DIRECTION {inout} \
+ CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_41_PULLUP {enabled} \
+ CONFIG.PCW_MIO_41_SLEW {slow} \
+ CONFIG.PCW_MIO_42_DIRECTION {inout} \
+ CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_42_PULLUP {enabled} \
+ CONFIG.PCW_MIO_42_SLEW {slow} \
+ CONFIG.PCW_MIO_43_DIRECTION {inout} \
+ CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_43_PULLUP {enabled} \
+ CONFIG.PCW_MIO_43_SLEW {slow} \
+ CONFIG.PCW_MIO_44_DIRECTION {inout} \
+ CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_44_PULLUP {enabled} \
+ CONFIG.PCW_MIO_44_SLEW {slow} \
+ CONFIG.PCW_MIO_45_DIRECTION {inout} \
+ CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_45_PULLUP {enabled} \
+ CONFIG.PCW_MIO_45_SLEW {slow} \
+ CONFIG.PCW_MIO_46_DIRECTION {in} \
+ CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_46_PULLUP {enabled} \
+ CONFIG.PCW_MIO_46_SLEW {slow} \
+ CONFIG.PCW_MIO_47_DIRECTION {out} \
+ CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_47_PULLUP {enabled} \
+ CONFIG.PCW_MIO_47_SLEW {slow} \
+ CONFIG.PCW_MIO_48_DIRECTION {out} \
+ CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_48_PULLUP {enabled} \
+ CONFIG.PCW_MIO_48_SLEW {slow} \
+ CONFIG.PCW_MIO_49_DIRECTION {in} \
+ CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_49_PULLUP {enabled} \
+ CONFIG.PCW_MIO_49_SLEW {slow} \
+ CONFIG.PCW_MIO_4_DIRECTION {inout} \
+ CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_4_PULLUP {disabled} \
+ CONFIG.PCW_MIO_4_SLEW {slow} \
+ CONFIG.PCW_MIO_50_DIRECTION {inout} \
+ CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_50_PULLUP {enabled} \
+ CONFIG.PCW_MIO_50_SLEW {slow} \
+ CONFIG.PCW_MIO_51_DIRECTION {inout} \
+ CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_51_PULLUP {enabled} \
+ CONFIG.PCW_MIO_51_SLEW {slow} \
+ CONFIG.PCW_MIO_52_DIRECTION {out} \
+ CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_52_PULLUP {enabled} \
+ CONFIG.PCW_MIO_52_SLEW {slow} \
+ CONFIG.PCW_MIO_53_DIRECTION {in} \
+ CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_53_PULLUP {enabled} \
+ CONFIG.PCW_MIO_53_SLEW {slow} \
+ CONFIG.PCW_MIO_5_DIRECTION {inout} \
+ CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_5_PULLUP {disabled} \
+ CONFIG.PCW_MIO_5_SLEW {slow} \
+ CONFIG.PCW_MIO_6_DIRECTION {out} \
+ CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_6_PULLUP {disabled} \
+ CONFIG.PCW_MIO_6_SLEW {slow} \
+ CONFIG.PCW_MIO_7_DIRECTION {out} \
+ CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_7_PULLUP {disabled} \
+ CONFIG.PCW_MIO_7_SLEW {slow} \
+ CONFIG.PCW_MIO_8_DIRECTION {out} \
+ CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_8_PULLUP {disabled} \
+ CONFIG.PCW_MIO_8_SLEW {slow} \
+ CONFIG.PCW_MIO_9_DIRECTION {in} \
+ CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_9_PULLUP {enabled} \
+ CONFIG.PCW_MIO_9_SLEW {slow} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS { \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#GPIO#GPIO#SPI 0#UART \
+ 0#I2C 0#CAN \
+ 0#SPI 0#SPI \
+ 0#UART 0#UART \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 1#CAN 1 \
+ 1#SD 1#Enet \
+ 1#SD 1#Enet \
+ 1#SD 1#Enet \
+ 1#UART 1#I2C \
+ Flash#GPIO#GPIO#SD 1#SD \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ GPIO#Quad SPI \
+ } \
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx} \
+ CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+ CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+ CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \
+ CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 2.5V} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+ CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {13} \
+ CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {133} \
+ CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+ CONFIG.PCW_SD1_GRP_CD_ENABLE {1} \
+ CONFIG.PCW_SD1_GRP_CD_IO {MIO 9} \
+ CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+ CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+ CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {18} \
+ CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
+ CONFIG.PCW_SPI0_GRP_SS0_IO {MIO 42} \
+ CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+ CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SPI0_SPI0_IO {MIO 40 .. 45} \
+ CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
+ CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
+ CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
+ CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
+ CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
+ CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
+ CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {11} \
+ CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+ CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART0_UART0_IO {MIO 46 .. 47} \
+ CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {18} \
+ CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {500.000000} \
+ CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+ CONFIG.PCW_UIPARAM_DDR_BL {8} \
+ CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+ CONFIG.PCW_UIPARAM_DDR_CL {7} \
+ CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+ CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+ CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
+ CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+ CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+ CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
+ CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
+ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \
+ CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
+ CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+ CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
+ CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+ CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+ CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_USB0_RESET_ENABLE {0} \
+ CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+ CONFIG.PCW_USB1_RESET_ENABLE {0} \
+ CONFIG.PCW_USB_RESET_ENABLE {1} \
+ CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
+ CONFIG.PCW_USE_S_AXI_GP0 {0} \
+ ] $processing_system7_0
+
+ # Create instance: ps7_0_axi_periph, and set properties
+ set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {2} \
+ ] $ps7_0_axi_periph
+
+ # Create instance: rst_ps7_0_125M, and set properties
+ set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
+
+ # Create instance: scalp_axi4lite_0, and set properties
+ set scalp_axi4lite_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_axi4lite:1.2 scalp_axi4lite_0 ]
+
+ # Create instance: scalp_safe_firmware_0, and set properties
+ set scalp_safe_firmware_0 [ create_bd_cell -type ip -vlnv hepia.ch:user:scalp_safe_firmware_reg_bank:1.3 scalp_safe_firmware_0 ]
+
+ # Create instance: system_ila_0, and set properties
+ set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
+ set_property -dict [ list \
+ CONFIG.C_MON_TYPE {NATIVE} \
+ CONFIG.C_NUM_OF_PROBES {1} \
+ CONFIG.C_PROBE0_TYPE {0} \
+ ] $system_ila_0
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [ list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {1} \
+ CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_0
+
+ # Create instance: util_vector_logic_1, and set properties
+ set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+ set_property -dict [ list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_1
+
+ # Create instance: vio_0, and set properties
+ set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
+ CONFIG.C_NUM_PROBE_IN {0} \
+ ] $vio_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+ connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+ connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
+
+ # Create port connections
+ connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
+ connect_bd_net -net RdDataxDI_0_1 [get_bd_ports RdDataxDI] [get_bd_pins scalp_axi4lite_0/RdDataxDI]
+ connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
+ connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
+ connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins vio_0/clk]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
+ connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
+ connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
+ connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI]
+ connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO]
+ connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
+ connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
+ connect_bd_net -net scalp_axi4lite_0_WrAddrxDO [get_bd_ports WrAddrxDO] [get_bd_pins scalp_axi4lite_0/WrAddrxDO]
+ connect_bd_net -net scalp_axi4lite_0_WrDataxDO [get_bd_ports WrDataxDO] [get_bd_pins scalp_axi4lite_0/WrDataxDO] [get_bd_pins system_ila_0/probe0]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_axi4lite_0_WrDataxDO]
+ connect_bd_net -net scalp_axi4lite_0_WrValidxSO [get_bd_ports WrValidxSO] [get_bd_pins scalp_axi4lite_0/WrValidxSO]
+ connect_bd_net -net scalp_safe_firmware_0_RgbLedsCtrlPortxDO [get_bd_ports RgbLedsCtrlPortxDO] [get_bd_pins scalp_safe_firmware_0/RgbLedsCtrlPortxDO]
+ connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
+ connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
+ connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
+
+ # Create address segments
+ assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr] -force
+ assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/tools/config/scalp_mipi.json b/tools/config/scalp_mipi.json
new file mode 100644
index 0000000000000000000000000000000000000000..5869e891c270bc2d6f81a022ec16520999ee1d87
--- /dev/null
+++ b/tools/config/scalp_mipi.json
@@ -0,0 +1,34 @@
+{
+ "author" : {
+ "name" : "Orphee Antoniadis",
+ "email" : "<orphee.antoniadis@hesge.ch>"
+ },
+ "project" : {
+ "name" : "scalp_mipi",
+ "type" : "DESIGN_PRJ_TYPE",
+ "category" : "DESIGNS",
+ "vivado_version" : "2020.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+ },
+ "constraints" : {
+ "scalp_mipi" : "enable",
+ "ibert_constraints" : "disable",
+ "debug" : "enable",
+ "timing_constraints" : "enable"
+ },
+ "components" : {
+ "packages" : {
+ "axi4_pkg": {
+ "enable": "true"
+ }
+ },
+ "soc" : {
+ "scalp_mipi_zynqps" : "enable"
+ }
+ }
+}
diff --git a/tools/config/scalp_mipi_zynqps.json b/tools/config/scalp_mipi_zynqps.json
new file mode 100644
index 0000000000000000000000000000000000000000..d028e9337276903168fd24b09abb0c29d337be81
--- /dev/null
+++ b/tools/config/scalp_mipi_zynqps.json
@@ -0,0 +1,17 @@
+{
+ "author" : {
+ "name" : "Orphee Antoniadis",
+ "email" : "<orphee.antoniadis@hesge.ch>"
+ },
+ "project" : {
+ "name" : "scalp_mipi_zynqps",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "SOC",
+ "vivado_version" : "2020.2",
+ "target_language" : "VHDL"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+ }
+}