diff --git a/soc/hw/scalp_zynqps_safe/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps_safe/src/hdl/scalp_zynqps_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9c23dae5fdef5402ae04aadefa4873632a500093
--- /dev/null
+++ b/soc/hw/scalp_zynqps_safe/src/hdl/scalp_zynqps_wrapper.vhd
@@ -0,0 +1,113 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: scalp_zynqps_wrapper - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_zynqps_wrapper for safe firmware
+--
+-- Last update: 2021-10-14
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scalp_zynqps_wrapper is
+
+ port (
+ -- Processor interface
+ FIXED_IO_ps_clk : inout std_logic;
+ FIXED_IO_ps_porb : inout std_logic;
+ FIXED_IO_ps_srstb : inout std_logic;
+ FclkClk0xCO : out std_logic;
+ FclkReset0xRO : out std_logic;
+ -- DDR interface
+ DDR_addr : inout std_logic_vector (14 downto 0);
+ DDR_ba : inout std_logic_vector (2 downto 0);
+ DDR_cas_n : inout std_logic;
+ DDR_ck_n : inout std_logic;
+ DDR_ck_p : inout std_logic;
+ DDR_cke : inout std_logic;
+ DDR_cs_n : inout std_logic;
+ DDR_dm : inout std_logic_vector (3 downto 0);
+ DDR_dq : inout std_logic_vector (31 downto 0);
+ DDR_dqs_n : inout std_logic_vector (3 downto 0);
+ DDR_dqs_p : inout std_logic_vector (3 downto 0);
+ DDR_odt : inout std_logic;
+ DDR_ras_n : inout std_logic;
+ DDR_reset_n : inout std_logic;
+ DDR_we_n : inout std_logic;
+ FIXED_IO_ddr_vrn : inout std_logic;
+ FIXED_IO_ddr_vrp : inout std_logic;
+ -- USB interface
+ Usb0VBusPwrFaultxSI : in std_logic;
+ -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+ -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+ Spi1MOSIxSO : out std_logic;
+ Spi1SSxSO : out std_logic;
+ Spi1SclkxCO : out std_logic;
+ -- MIO
+ FIXED_IO_mio : inout std_logic_vector (53 downto 0);
+ -- Scalp Registers
+ RGBLed0xDO : out std_logic_vector(31 downto 0);
+ RGBLed1xDO : out std_logic_vector(31 downto 0));
+
+end scalp_zynqps_wrapper;
+
+architecture arch of scalp_zynqps_wrapper is
+
+ -- Internal signals
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+
+begin
+
+ ScalpZynqPSSafexI : entity work.scalp_zynqps_safe
+ port map (
+ DDR_addr => DDR_addr,
+ DDR_ba => DDR_ba,
+ DDR_cas_n => DDR_cas_n,
+ DDR_ck_n => DDR_ck_n,
+ DDR_ck_p => DDR_ck_p,
+ DDR_cke => DDR_cke,
+ DDR_cs_n => DDR_cs_n,
+ DDR_dm => DDR_dm,
+ DDR_dq => DDR_dq,
+ DDR_dqs_n => DDR_dqs_n,
+ DDR_dqs_p => DDR_dqs_p,
+ DDR_odt => DDR_odt,
+ DDR_ras_n => DDR_ras_n,
+ DDR_reset_n => DDR_reset_n,
+ DDR_we_n => DDR_we_n,
+ FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+ FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+ FIXED_IO_mio => FIXED_IO_mio,
+ FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+ FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+ FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+ FclkClk0xCO => FclkClk0xCO,
+ FclkReset0xRO(0) => FclkReset0xRO,
+ Spi1MOSIxSO => Spi1MOSIxSO,
+ Spi1SSxSO => Spi1SSxSO,
+ Spi1SclkxCO => Spi1SclkxCO,
+ Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
+ RGBLed0xDO => RGBLed0xDO,
+ RGBLed1xDO => RGBLed1xDO);
+
+end arch;
diff --git a/soc/hw/scalp_zynqps_safe/src/sim/tb_scalp_zynqps_safe.vhd b/soc/hw/scalp_zynqps_safe/src/sim/tb_scalp_zynqps_safe.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d9a12498c6ddc6dbce86500622a72116a37a90bf
--- /dev/null
+++ b/soc/hw/scalp_zynqps_safe/src/sim/tb_scalp_zynqps_safe.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: tb_scalp_zynqps_safe - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_zynqps_safe
+--
+-- Last update: 2021-10-14 10:42:55
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_zynqps_safe is
+end tb_scalp_zynqps_safe;
+
+
+architecture behavioral of tb_scalp_zynqps_safe is
+
+begin
+
+end behavioral;
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.gitignore b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..911f9aba93cbee702c1d018c023bbc50d29b2e98
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.gitignore
@@ -0,0 +1,25 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-10-14 10:42:55
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_zynqps_safe
+.scripts/scalp_zynqps_safe
+.scripts/.Xil
\ No newline at end of file
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/.prompt_colors.tcl b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b277394f0cfc48696c74272426b8e9bd78500331
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-10-14 10:42:56
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/clean_prj_scalp_zynqps_safe.sh b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/clean_prj_scalp_zynqps_safe.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e98396e2a2a02ee3dc939a811c9044122ef64636
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/clean_prj_scalp_zynqps_safe.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-10-14 10:42:55
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_zynqps_safe/ 2> /dev/null
+
+echo "> Done"
+
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/create_prj_scalp_zynqps_safe.sh b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/create_prj_scalp_zynqps_safe.sh
new file mode 100755
index 0000000000000000000000000000000000000000..91326f6ac26a1b041184391e9cbf60b6e1b1f7cd
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/create_prj_scalp_zynqps_safe.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-10-14 10:42:55
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_zynqps_safe.tcl -notrace
+echo "> Done"
+
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/create_prj_scalp_zynqps_safe.tcl b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/create_prj_scalp_zynqps_safe.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..45b86b016a2112dfd922cbdceefa9ce029154ddb
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/create_prj_scalp_zynqps_safe.tcl
@@ -0,0 +1,154 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_zynqps_safe'
+#
+# Last update: 2021-10-14 10:42:55
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_zynqps_safe"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../soc/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set hdl_src_dir "${src_dir}/hdl"
+ set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ set hdl_src_dir "${comp_src_dir}/hdl"
+ set sim_src_dir "${comp_src_dir}/sim"
+}
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+ add_files -norecurse $hdl_src_file_list
+} else {
+ print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
+ # add IPs source files
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # add IPs source files
+
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+ add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+ update_compile_order -fileset sim_1
+ print_status "Add simulation sources" "OK"
+} else {
+ print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for simulation sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/open_prj_scalp_zynqps_safe.sh b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/open_prj_scalp_zynqps_safe.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f88c9a78dbbe9aae4c06f3964530b4368ff4d563
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/open_prj_scalp_zynqps_safe.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-10-14 10:42:55
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_zynqps_safe/scalp_zynqps_safe.xpr
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/utils.tcl b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a80a97c545a77ad107edef2f94a67175b3cdcf01
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-10-14 10:42:55
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/lin64/setup.sh b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..18a93bc566f664b97dbd360f657ab510fe2daf86
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/lin64/setup.sh
@@ -0,0 +1,28 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_zynqps_safe
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-10-14 10:42:55
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_zynqps_safe.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_zynqps_safe.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_zynqps_safe.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_zynqps_safe.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_zynqps_safe.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_zynqps_safe.sh && cd ..'
diff --git a/soc/vivado/scalp_zynqps_safe/2020.2/src/ipi_tcl/scalp_zynqps_safe_ipi.tcl b/soc/vivado/scalp_zynqps_safe/2020.2/src/ipi_tcl/scalp_zynqps_safe_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2d09786e341f306e2ad623cf1220eb0944b70f7b
--- /dev/null
+++ b/soc/vivado/scalp_zynqps_safe/2020.2/src/ipi_tcl/scalp_zynqps_safe_ipi.tcl
@@ -0,0 +1,944 @@
+
+################################################################
+# This is a generated script based on design: scalp_zynqps
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source scalp_zynqps_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xc7z015clg485-2
+ set_property BOARD_PART hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name scalp_zynqps_safe
+
+# This script was generated for a remote BD. To create a non-remote design,
+# change the variable <run_remote_bd_flow> to <0>.
+
+set run_remote_bd_flow 1
+if { $run_remote_bd_flow == 1 } {
+ # Set the reference directory for source file relative paths (by default
+ # the value is script directory path)
+ set origin_dir .
+
+ # Use origin directory path location variable, if specified in the tcl shell
+ if { [info exists ::origin_dir_loc] } {
+ set origin_dir $::origin_dir_loc
+ }
+
+ set str_bd_folder [file normalize ${origin_dir}]
+ set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
+
+ # Check if remote design exists on disk
+ if { [file exists $str_bd_filepath ] == 1 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
+ common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
+ common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+
+ return 1
+ }
+
+ # Check if design exists in memory
+ set list_existing_designs [get_bd_designs -quiet $design_name]
+ if { $list_existing_designs ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+ common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+ return 1
+ }
+
+ # Check if design exists on disk within project
+ set list_existing_designs [get_files -quiet */${design_name}.bd]
+ if { $list_existing_designs ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
+ $list_existing_designs"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+ common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+ return 1
+ }
+
+ # Now can create the remote BD
+ # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
+ create_bd_design -dir $str_bd_folder $design_name
+} else {
+
+ # Create regular design
+ if { [catch {create_bd_design $design_name} errmsg] } {
+ common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
+
+ return 1
+ }
+}
+
+current_bd_design $design_name
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+xilinx.com:ip:axi_clock_converter:2.1\
+xilinx.com:ip:axi_dma:7.1\
+xilinx.com:ip:xlconstant:1.1\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:proc_sys_reset:5.0\
+hepia.hesge.ch:user:scalp_dma_fifo:1.0\
+hepia.hesge.ch:user:scalp_fast_router_registers:1.0\
+xilinx.com:ip:system_ila:1.1\
+xilinx.com:ip:util_vector_logic:2.0\
+xilinx.com:ip:vio:3.0\
+xilinx.com:ip:xlconcat:2.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+ set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+
+ set DMARXxDI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMARXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ CONFIG.HAS_TKEEP {0} \
+ CONFIG.HAS_TLAST {1} \
+ CONFIG.HAS_TREADY {1} \
+ CONFIG.HAS_TSTRB {0} \
+ CONFIG.LAYERED_METADATA {undef} \
+ CONFIG.TDATA_NUM_BYTES {4} \
+ CONFIG.TDEST_WIDTH {0} \
+ CONFIG.TID_WIDTH {0} \
+ CONFIG.TUSER_WIDTH {0} \
+ ] $DMARXxDI
+
+ set DMATXxDO [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMATXxDO ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $DMATXxDO
+
+ set EastRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 EastRXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $EastRXxDI
+
+ set EastTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 EastTXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $EastTXxDI
+
+ set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+ set LocalRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 LocalRXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $LocalRXxDI
+
+ set LocalTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 LocalTXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $LocalTXxDI
+
+ set WestRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 WestRXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $WestRXxDI
+
+ set WestTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 WestTXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $WestTXxDI
+
+
+ # Create ports
+ set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $FclkClk0xCO
+ set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
+ set LocalNetAddrxDO [ create_bd_port -dir O -from 31 -to 0 -type data LocalNetAddrxDO ]
+ set RGBLed0xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed0xDO ]
+ set RGBLed1xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed1xDO ]
+ set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
+ set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
+ set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
+ set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
+ set UserClkxCI [ create_bd_port -dir I -type clk -freq_hz 125000000 UserClkxCI ]
+ set_property -dict [ list \
+ CONFIG.ASSOCIATED_BUSIF {DMATXxDO:DMARXxDI:EastTXxDI:WestRXxDI:WestTXxDI:EastRXxDI:LocalTXxDI:LocalRXxDI} \
+ ] $UserClkxCI
+ set UserResetxRANI [ create_bd_port -dir I -type rst UserResetxRANI ]
+
+ # Create instance: axi_clock_converter_0, and set properties
+ set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
+
+ # Create instance: axi_clock_converter_1, and set properties
+ set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
+
+ # Create instance: axi_clock_converter_2, and set properties
+ set axi_clock_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_2 ]
+
+ # Create instance: axi_clock_converter_3, and set properties
+ set axi_clock_converter_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_3 ]
+
+ # Create instance: axi_dma_0, and set properties
+ set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
+ set_property -dict [ list \
+ CONFIG.c_include_sg {0} \
+ CONFIG.c_sg_include_stscntrl_strm {0} \
+ ] $axi_dma_0
+
+ # Create instance: axi_interconnect_0, and set properties
+ set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {1} \
+ CONFIG.NUM_SI {2} \
+ ] $axi_interconnect_0
+
+ # Create instance: gnd_constant_0, and set properties
+ set gnd_constant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $gnd_constant_0
+
+ # Create instance: gnd_constant_1, and set properties
+ set gnd_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_1 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {30} \
+ ] $gnd_constant_1
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {750.000000} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.204082} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {194.444443} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {134.615387} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {159.090912} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {750} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {30} \
+ CONFIG.PCW_CAN1_CAN1_IO {MIO 52 .. 53} \
+ CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
+ CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {18} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_CAN_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_CLK0_FREQ {125000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1500.000} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {49} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {20} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1000.000} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x0FFFFFFF} \
+ CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+ CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
+ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {14} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+ CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET_RESET_ENABLE {1} \
+ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_EN_CAN1 {1} \
+ CONFIG.PCW_EN_EMIO_CAN1 {0} \
+ CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_ENET0 {0} \
+ CONFIG.PCW_EN_EMIO_I2C0 {0} \
+ CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_SPI0 {0} \
+ CONFIG.PCW_EN_EMIO_SPI1 {1} \
+ CONFIG.PCW_EN_EMIO_UART0 {0} \
+ CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+ CONFIG.PCW_EN_ENET0 {1} \
+ CONFIG.PCW_EN_GPIO {1} \
+ CONFIG.PCW_EN_I2C0 {1} \
+ CONFIG.PCW_EN_QSPI {1} \
+ CONFIG.PCW_EN_SDIO1 {1} \
+ CONFIG.PCW_EN_SPI0 {1} \
+ CONFIG.PCW_EN_SPI1 {1} \
+ CONFIG.PCW_EN_UART0 {1} \
+ CONFIG.PCW_EN_UART1 {1} \
+ CONFIG.PCW_EN_USB0 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {7} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {125} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+ CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+ CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
+ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_I2C_RESET_ENABLE {1} \
+ CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {35} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1750.000} \
+ CONFIG.PCW_IRQ_F2P_INTR {1} \
+ CONFIG.PCW_MIO_0_DIRECTION {inout} \
+ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_0_PULLUP {enabled} \
+ CONFIG.PCW_MIO_0_SLEW {slow} \
+ CONFIG.PCW_MIO_10_DIRECTION {inout} \
+ CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_10_PULLUP {enabled} \
+ CONFIG.PCW_MIO_10_SLEW {slow} \
+ CONFIG.PCW_MIO_11_DIRECTION {inout} \
+ CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_11_PULLUP {enabled} \
+ CONFIG.PCW_MIO_11_SLEW {slow} \
+ CONFIG.PCW_MIO_12_DIRECTION {inout} \
+ CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_12_PULLUP {enabled} \
+ CONFIG.PCW_MIO_12_SLEW {slow} \
+ CONFIG.PCW_MIO_13_DIRECTION {inout} \
+ CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_13_PULLUP {enabled} \
+ CONFIG.PCW_MIO_13_SLEW {slow} \
+ CONFIG.PCW_MIO_14_DIRECTION {inout} \
+ CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_14_PULLUP {enabled} \
+ CONFIG.PCW_MIO_14_SLEW {slow} \
+ CONFIG.PCW_MIO_15_DIRECTION {inout} \
+ CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_15_PULLUP {enabled} \
+ CONFIG.PCW_MIO_15_SLEW {slow} \
+ CONFIG.PCW_MIO_16_DIRECTION {out} \
+ CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_16_PULLUP {enabled} \
+ CONFIG.PCW_MIO_16_SLEW {slow} \
+ CONFIG.PCW_MIO_17_DIRECTION {out} \
+ CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_17_PULLUP {enabled} \
+ CONFIG.PCW_MIO_17_SLEW {slow} \
+ CONFIG.PCW_MIO_18_DIRECTION {out} \
+ CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_18_PULLUP {enabled} \
+ CONFIG.PCW_MIO_18_SLEW {slow} \
+ CONFIG.PCW_MIO_19_DIRECTION {out} \
+ CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_19_PULLUP {enabled} \
+ CONFIG.PCW_MIO_19_SLEW {slow} \
+ CONFIG.PCW_MIO_1_DIRECTION {out} \
+ CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_1_PULLUP {enabled} \
+ CONFIG.PCW_MIO_1_SLEW {slow} \
+ CONFIG.PCW_MIO_20_DIRECTION {out} \
+ CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_20_PULLUP {enabled} \
+ CONFIG.PCW_MIO_20_SLEW {slow} \
+ CONFIG.PCW_MIO_21_DIRECTION {out} \
+ CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_21_PULLUP {enabled} \
+ CONFIG.PCW_MIO_21_SLEW {slow} \
+ CONFIG.PCW_MIO_22_DIRECTION {in} \
+ CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_22_PULLUP {enabled} \
+ CONFIG.PCW_MIO_22_SLEW {slow} \
+ CONFIG.PCW_MIO_23_DIRECTION {in} \
+ CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_23_PULLUP {enabled} \
+ CONFIG.PCW_MIO_23_SLEW {slow} \
+ CONFIG.PCW_MIO_24_DIRECTION {in} \
+ CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_24_PULLUP {enabled} \
+ CONFIG.PCW_MIO_24_SLEW {slow} \
+ CONFIG.PCW_MIO_25_DIRECTION {in} \
+ CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_25_PULLUP {enabled} \
+ CONFIG.PCW_MIO_25_SLEW {slow} \
+ CONFIG.PCW_MIO_26_DIRECTION {in} \
+ CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_26_PULLUP {enabled} \
+ CONFIG.PCW_MIO_26_SLEW {slow} \
+ CONFIG.PCW_MIO_27_DIRECTION {in} \
+ CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_27_PULLUP {enabled} \
+ CONFIG.PCW_MIO_27_SLEW {slow} \
+ CONFIG.PCW_MIO_28_DIRECTION {inout} \
+ CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_28_PULLUP {enabled} \
+ CONFIG.PCW_MIO_28_SLEW {slow} \
+ CONFIG.PCW_MIO_29_DIRECTION {in} \
+ CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_29_PULLUP {enabled} \
+ CONFIG.PCW_MIO_29_SLEW {slow} \
+ CONFIG.PCW_MIO_2_DIRECTION {inout} \
+ CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_2_PULLUP {disabled} \
+ CONFIG.PCW_MIO_2_SLEW {slow} \
+ CONFIG.PCW_MIO_30_DIRECTION {out} \
+ CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_30_PULLUP {enabled} \
+ CONFIG.PCW_MIO_30_SLEW {slow} \
+ CONFIG.PCW_MIO_31_DIRECTION {in} \
+ CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_31_PULLUP {enabled} \
+ CONFIG.PCW_MIO_31_SLEW {slow} \
+ CONFIG.PCW_MIO_32_DIRECTION {inout} \
+ CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_32_PULLUP {enabled} \
+ CONFIG.PCW_MIO_32_SLEW {slow} \
+ CONFIG.PCW_MIO_33_DIRECTION {inout} \
+ CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_33_PULLUP {enabled} \
+ CONFIG.PCW_MIO_33_SLEW {slow} \
+ CONFIG.PCW_MIO_34_DIRECTION {inout} \
+ CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_34_PULLUP {enabled} \
+ CONFIG.PCW_MIO_34_SLEW {slow} \
+ CONFIG.PCW_MIO_35_DIRECTION {inout} \
+ CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_35_PULLUP {enabled} \
+ CONFIG.PCW_MIO_35_SLEW {slow} \
+ CONFIG.PCW_MIO_36_DIRECTION {in} \
+ CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_36_PULLUP {enabled} \
+ CONFIG.PCW_MIO_36_SLEW {slow} \
+ CONFIG.PCW_MIO_37_DIRECTION {inout} \
+ CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_37_PULLUP {enabled} \
+ CONFIG.PCW_MIO_37_SLEW {slow} \
+ CONFIG.PCW_MIO_38_DIRECTION {inout} \
+ CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_38_PULLUP {enabled} \
+ CONFIG.PCW_MIO_38_SLEW {slow} \
+ CONFIG.PCW_MIO_39_DIRECTION {inout} \
+ CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_39_PULLUP {enabled} \
+ CONFIG.PCW_MIO_39_SLEW {slow} \
+ CONFIG.PCW_MIO_3_DIRECTION {inout} \
+ CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_3_PULLUP {disabled} \
+ CONFIG.PCW_MIO_3_SLEW {slow} \
+ CONFIG.PCW_MIO_40_DIRECTION {inout} \
+ CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_40_PULLUP {enabled} \
+ CONFIG.PCW_MIO_40_SLEW {slow} \
+ CONFIG.PCW_MIO_41_DIRECTION {inout} \
+ CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_41_PULLUP {enabled} \
+ CONFIG.PCW_MIO_41_SLEW {slow} \
+ CONFIG.PCW_MIO_42_DIRECTION {inout} \
+ CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_42_PULLUP {enabled} \
+ CONFIG.PCW_MIO_42_SLEW {slow} \
+ CONFIG.PCW_MIO_43_DIRECTION {inout} \
+ CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_43_PULLUP {enabled} \
+ CONFIG.PCW_MIO_43_SLEW {slow} \
+ CONFIG.PCW_MIO_44_DIRECTION {inout} \
+ CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_44_PULLUP {enabled} \
+ CONFIG.PCW_MIO_44_SLEW {slow} \
+ CONFIG.PCW_MIO_45_DIRECTION {inout} \
+ CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_45_PULLUP {enabled} \
+ CONFIG.PCW_MIO_45_SLEW {slow} \
+ CONFIG.PCW_MIO_46_DIRECTION {in} \
+ CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_46_PULLUP {enabled} \
+ CONFIG.PCW_MIO_46_SLEW {slow} \
+ CONFIG.PCW_MIO_47_DIRECTION {out} \
+ CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_47_PULLUP {enabled} \
+ CONFIG.PCW_MIO_47_SLEW {slow} \
+ CONFIG.PCW_MIO_48_DIRECTION {out} \
+ CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_48_PULLUP {enabled} \
+ CONFIG.PCW_MIO_48_SLEW {slow} \
+ CONFIG.PCW_MIO_49_DIRECTION {in} \
+ CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_49_PULLUP {enabled} \
+ CONFIG.PCW_MIO_49_SLEW {slow} \
+ CONFIG.PCW_MIO_4_DIRECTION {inout} \
+ CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_4_PULLUP {disabled} \
+ CONFIG.PCW_MIO_4_SLEW {slow} \
+ CONFIG.PCW_MIO_50_DIRECTION {inout} \
+ CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_50_PULLUP {enabled} \
+ CONFIG.PCW_MIO_50_SLEW {slow} \
+ CONFIG.PCW_MIO_51_DIRECTION {inout} \
+ CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_51_PULLUP {enabled} \
+ CONFIG.PCW_MIO_51_SLEW {slow} \
+ CONFIG.PCW_MIO_52_DIRECTION {out} \
+ CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_52_PULLUP {enabled} \
+ CONFIG.PCW_MIO_52_SLEW {slow} \
+ CONFIG.PCW_MIO_53_DIRECTION {in} \
+ CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_53_PULLUP {enabled} \
+ CONFIG.PCW_MIO_53_SLEW {slow} \
+ CONFIG.PCW_MIO_5_DIRECTION {inout} \
+ CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_5_PULLUP {disabled} \
+ CONFIG.PCW_MIO_5_SLEW {slow} \
+ CONFIG.PCW_MIO_6_DIRECTION {out} \
+ CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_6_PULLUP {disabled} \
+ CONFIG.PCW_MIO_6_SLEW {slow} \
+ CONFIG.PCW_MIO_7_DIRECTION {out} \
+ CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_7_PULLUP {disabled} \
+ CONFIG.PCW_MIO_7_SLEW {slow} \
+ CONFIG.PCW_MIO_8_DIRECTION {out} \
+ CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_8_PULLUP {disabled} \
+ CONFIG.PCW_MIO_8_SLEW {slow} \
+ CONFIG.PCW_MIO_9_DIRECTION {in} \
+ CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_9_PULLUP {enabled} \
+ CONFIG.PCW_MIO_9_SLEW {slow} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS { \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#GPIO#GPIO#SPI 0#UART \
+ 0#I2C 0#CAN \
+ 0#SPI 0#SPI \
+ 0#UART 0#UART \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 1#CAN 1 \
+ 1#SD 1#Enet \
+ 1#SD 1#Enet \
+ 1#SD 1#Enet \
+ 1#UART 1#I2C \
+ Flash#GPIO#GPIO#SD 1#SD \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ GPIO#Quad SPI \
+ } \
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx} \
+ CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+ CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+ CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+ CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \
+ CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 2.5V} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+ CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {13} \
+ CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {133} \
+ CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+ CONFIG.PCW_SD1_GRP_CD_ENABLE {1} \
+ CONFIG.PCW_SD1_GRP_CD_IO {MIO 9} \
+ CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+ CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+ CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {18} \
+ CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
+ CONFIG.PCW_SPI0_GRP_SS0_IO {MIO 42} \
+ CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+ CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SPI0_SPI0_IO {MIO 40 .. 45} \
+ CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
+ CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
+ CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
+ CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
+ CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
+ CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
+ CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {11} \
+ CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+ CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART0_UART0_IO {MIO 46 .. 47} \
+ CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {18} \
+ CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {500.000000} \
+ CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+ CONFIG.PCW_UIPARAM_DDR_BL {8} \
+ CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+ CONFIG.PCW_UIPARAM_DDR_CL {7} \
+ CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+ CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+ CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
+ CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+ CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+ CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
+ CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
+ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \
+ CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
+ CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+ CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+ CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
+ CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+ CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+ CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_USB0_RESET_ENABLE {0} \
+ CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+ CONFIG.PCW_USB1_RESET_ENABLE {0} \
+ CONFIG.PCW_USB_RESET_ENABLE {1} \
+ CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
+ CONFIG.PCW_USE_S_AXI_GP0 {0} \
+ CONFIG.PCW_USE_S_AXI_HP0 {1} \
+ ] $processing_system7_0
+
+ # Create instance: ps7_0_axi_periph, and set properties
+ set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {2} \
+ ] $ps7_0_axi_periph
+
+ # Create instance: rst_ps7_0_125M, and set properties
+ set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
+
+ # Create instance: scalp_dma_fifo_rx_0, and set properties
+ set scalp_dma_fifo_rx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_rx_0 ]
+
+ # Create instance: scalp_dma_fifo_tx_0, and set properties
+ set scalp_dma_fifo_tx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_tx_0 ]
+
+ # Create instance: scalp_fast_router_registers_0, and set properties
+ set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.0 scalp_fast_router_registers_0 ]
+
+ # Create instance: system_ila_0, and set properties
+ set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
+ set_property -dict [ list \
+ CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
+ CONFIG.C_ADV_TRIGGER {true} \
+ CONFIG.C_BRAM_CNT {3} \
+ CONFIG.C_EN_STRG_QUAL {1} \
+ CONFIG.C_MON_TYPE {MIX} \
+ CONFIG.C_NUM_MONITOR_SLOTS {8} \
+ CONFIG.C_NUM_OF_PROBES {9} \
+ CONFIG.C_PROBE0_MU_CNT {2} \
+ CONFIG.C_PROBE1_MU_CNT {2} \
+ CONFIG.C_PROBE2_MU_CNT {2} \
+ CONFIG.C_PROBE3_MU_CNT {2} \
+ CONFIG.C_PROBE4_MU_CNT {2} \
+ CONFIG.C_PROBE5_MU_CNT {2} \
+ CONFIG.C_PROBE6_MU_CNT {2} \
+ CONFIG.C_PROBE7_MU_CNT {2} \
+ CONFIG.C_PROBE8_MU_CNT {2} \
+ CONFIG.C_SLOT {7} \
+ CONFIG.C_SLOT_0_APC_EN {0} \
+ CONFIG.C_SLOT_0_AXI_DATA_SEL {1} \
+ CONFIG.C_SLOT_0_AXI_TRIG_SEL {1} \
+ CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_1_APC_EN {0} \
+ CONFIG.C_SLOT_1_AXI_DATA_SEL {1} \
+ CONFIG.C_SLOT_1_AXI_TRIG_SEL {1} \
+ CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_6_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_7_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ ] $system_ila_0
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [ list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {1} \
+ CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_0
+
+ # Create instance: util_vector_logic_1, and set properties
+ set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+ set_property -dict [ list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_1
+
+ # Create instance: vio_0, and set properties
+ set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
+ CONFIG.C_NUM_PROBE_IN {0} \
+ ] $vio_0
+
+ # Create instance: xlconcat_0, and set properties
+ set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+ set_property -dict [ list \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $xlconcat_0
+
+ # Create instance: xlconcat_1, and set properties
+ set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
+ set_property -dict [ list \
+ CONFIG.IN2_WIDTH {30} \
+ CONFIG.NUM_PORTS {3} \
+ ] $xlconcat_1
+
+ # Create instance: xlconcat_2, and set properties
+ set xlconcat_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_2 ]
+ set_property -dict [ list \
+ CONFIG.IN2_WIDTH {30} \
+ CONFIG.NUM_PORTS {3} \
+ ] $xlconcat_2
+
+ # Create interface connections
+connect_bd_intf_net -intf_net Conn [get_bd_intf_ports EastRXxDI] [get_bd_intf_pins system_ila_0/SLOT_2_AXIS]
+connect_bd_intf_net -intf_net Conn1 [get_bd_intf_ports EastTXxDI] [get_bd_intf_pins system_ila_0/SLOT_3_AXIS]
+connect_bd_intf_net -intf_net Conn2 [get_bd_intf_ports WestRXxDI] [get_bd_intf_pins system_ila_0/SLOT_4_AXIS]
+connect_bd_intf_net -intf_net Conn3 [get_bd_intf_ports WestTXxDI] [get_bd_intf_pins system_ila_0/SLOT_5_AXIS]
+connect_bd_intf_net -intf_net Conn4 [get_bd_intf_ports LocalRXxDI] [get_bd_intf_pins system_ila_0/SLOT_6_AXIS]
+connect_bd_intf_net -intf_net Conn5 [get_bd_intf_ports LocalTXxDI] [get_bd_intf_pins system_ila_0/SLOT_7_AXIS]
+ connect_bd_intf_net -intf_net DMARXxDI_1 [get_bd_intf_ports DMARXxDI] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMARXxDI]
+ connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_dma_0/S_AXI_LITE]
+ connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
+ connect_bd_intf_net -intf_net axi_clock_converter_2_M_AXI [get_bd_intf_pins axi_clock_converter_2/M_AXI] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
+ connect_bd_intf_net -intf_net axi_clock_converter_3_M_AXI [get_bd_intf_pins axi_clock_converter_3/M_AXI] [get_bd_intf_pins scalp_fast_router_registers_0/SAxiLitexDIO]
+ connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMARXxDI]
+connect_bd_intf_net -intf_net [get_bd_intf_nets axi_dma_0_M_AXIS_MM2S] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMARXxDI] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets axi_dma_0_M_AXIS_MM2S]
+ connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_MM2S]
+ connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_clock_converter_2/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_S2MM]
+ connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
+ connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+ connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+ connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_clock_converter_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+ connect_bd_intf_net -intf_net scalp_dma_fifo_rx_0_DMATXxDO [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMATXxDO]
+connect_bd_intf_net -intf_net [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMATXxDO] [get_bd_intf_pins system_ila_0/SLOT_1_AXIS]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO]
+ connect_bd_intf_net -intf_net scalp_dma_fifo_tx_0_DMATXxDO [get_bd_intf_ports DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMATXxDO]
+
+ # Create port connections
+ connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
+ connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins axi_clock_converter_2/s_axi_aclk] [get_bd_pins axi_clock_converter_3/m_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins scalp_dma_fifo_rx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_rx_0/TXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/TXClkxCI] [get_bd_pins scalp_fast_router_registers_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk]
+ connect_bd_net -net UserResetxRANI_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins axi_clock_converter_2/s_axi_aresetn] [get_bd_pins axi_clock_converter_3/m_axi_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins scalp_dma_fifo_rx_0/RXRstxRANI] [get_bd_pins scalp_dma_fifo_tx_0/RXRstxRANI] [get_bd_pins scalp_fast_router_registers_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn]
+ connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0]
+ connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1]
+ connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant_0/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_clock_converter_2/m_axi_aclk] [get_bd_pins axi_clock_converter_3/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins vio_0/clk]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
+ connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
+ connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
+ connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_clock_converter_2/m_axi_aresetn] [get_bd_pins axi_clock_converter_3/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn]
+ connect_bd_net -net scalp_dma_fifo_rx_0_ProgEmptyxSO [get_bd_pins scalp_dma_fifo_rx_0/ProgEmptyxSO] [get_bd_pins system_ila_0/probe2] [get_bd_pins xlconcat_2/In0]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_ProgEmptyxSO]
+ connect_bd_net -net scalp_dma_fifo_rx_0_ProgFullxSO [get_bd_pins scalp_dma_fifo_rx_0/ProgFullxSO] [get_bd_pins system_ila_0/probe3] [get_bd_pins xlconcat_2/In1]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_ProgFullxSO]
+ connect_bd_net -net scalp_dma_fifo_rx_0_RdDataCntxDO [get_bd_pins scalp_dma_fifo_rx_0/RdDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXRrDataCntxDI] [get_bd_pins system_ila_0/probe1]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_RdDataCntxDO]
+ connect_bd_net -net scalp_dma_fifo_rx_0_WrDataCntxDO [get_bd_pins scalp_dma_fifo_rx_0/WrDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXWrDataCntxDI] [get_bd_pins system_ila_0/probe0]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_WrDataCntxDO]
+ connect_bd_net -net scalp_dma_fifo_tx_0_ProgEmptyxSO [get_bd_pins scalp_dma_fifo_tx_0/ProgEmptyxSO] [get_bd_pins system_ila_0/probe6] [get_bd_pins xlconcat_1/In0]
+ connect_bd_net -net scalp_dma_fifo_tx_0_ProgFullxSO [get_bd_pins scalp_dma_fifo_tx_0/ProgFullxSO] [get_bd_pins system_ila_0/probe7] [get_bd_pins xlconcat_1/In1]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_ProgFullxSO]
+ connect_bd_net -net scalp_dma_fifo_tx_0_RdDataCntxDO [get_bd_pins scalp_dma_fifo_tx_0/RdDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXRrDataCntxDI] [get_bd_pins system_ila_0/probe5]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_RdDataCntxDO]
+ connect_bd_net -net scalp_dma_fifo_tx_0_WrDataCntxDO [get_bd_pins scalp_dma_fifo_tx_0/WrDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXWrDataCntxDI] [get_bd_pins system_ila_0/probe4]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_WrDataCntxDO]
+ connect_bd_net -net scalp_fast_router_re_0_RGBLed0xDO [get_bd_ports RGBLed0xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed0xDO]
+ connect_bd_net -net scalp_fast_router_re_0_RGBLed1xDO [get_bd_ports RGBLed1xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed1xDO]
+ connect_bd_net -net scalp_fast_router_registers_0_LocalNetAddrxDO [get_bd_ports LocalNetAddrxDO] [get_bd_pins scalp_fast_router_registers_0/LocalNetAddrxDO]
+ connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
+ connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
+ connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins system_ila_0/probe8] [get_bd_pins xlconcat_0/dout]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets xlconcat_0_dout]
+ connect_bd_net -net xlconcat_1_dout [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXStatusxDI] [get_bd_pins xlconcat_1/dout]
+ connect_bd_net -net xlconcat_2_dout [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXStatusxDI] [get_bd_pins xlconcat_2/dout]
+ connect_bd_net -net xlconstant_0_dout [get_bd_pins gnd_constant_1/dout] [get_bd_pins xlconcat_1/In2] [get_bd_pins xlconcat_2/In2]
+
+ # Create address segments
+ assign_bd_address -offset 0x0C000000 -range 0x04000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x0C000000 -range 0x04000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x40400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
+ assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_fast_router_registers_0/SAxiLitexDIO/reg0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/tools/config/scalp_zynqps_safe.json b/tools/config/scalp_zynqps_safe.json
new file mode 100644
index 0000000000000000000000000000000000000000..8bf9bc6de7bec951c554889e8e2f8e34144e623c
--- /dev/null
+++ b/tools/config/scalp_zynqps_safe.json
@@ -0,0 +1,17 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch>"
+ },
+ "project" : {
+ "name" : "scalp_zynqps_safe",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "SOC",
+ "vivado_version" : "2020.2",
+ "target_language" : "VHDL"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+ }
+}